elinkxl.c revision 1.135
1 /* $NetBSD: elinkxl.c,v 1.135 2020/02/04 05:25:39 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: elinkxl.c,v 1.135 2020/02/04 05:25:39 thorpej Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/callout.h> 38 #include <sys/kernel.h> 39 #include <sys/mbuf.h> 40 #include <sys/socket.h> 41 #include <sys/ioctl.h> 42 #include <sys/errno.h> 43 #include <sys/syslog.h> 44 #include <sys/select.h> 45 #include <sys/device.h> 46 #include <sys/rndsource.h> 47 48 #include <net/if.h> 49 #include <net/if_dl.h> 50 #include <net/if_ether.h> 51 #include <net/if_media.h> 52 #include <net/bpf.h> 53 54 #include <sys/cpu.h> 55 #include <sys/bus.h> 56 #include <sys/intr.h> 57 #include <machine/endian.h> 58 59 #include <dev/mii/miivar.h> 60 #include <dev/mii/mii.h> 61 #include <dev/mii/mii_bitbang.h> 62 63 #include <dev/ic/elink3reg.h> 64 /* #include <dev/ic/elink3var.h> */ 65 #include <dev/ic/elinkxlreg.h> 66 #include <dev/ic/elinkxlvar.h> 67 68 #ifdef DEBUG 69 int exdebug = 0; 70 #endif 71 72 /* ifmedia callbacks */ 73 int ex_media_chg(struct ifnet *ifp); 74 void ex_media_stat(struct ifnet *ifp, struct ifmediareq *req); 75 76 static int ex_ifflags_cb(struct ethercom *); 77 78 void ex_probe_media(struct ex_softc *); 79 void ex_set_filter(struct ex_softc *); 80 void ex_set_media(struct ex_softc *); 81 void ex_set_xcvr(struct ex_softc *, uint16_t); 82 struct mbuf *ex_get(struct ex_softc *, int); 83 uint16_t ex_read_eeprom(struct ex_softc *, int); 84 int ex_init(struct ifnet *); 85 void ex_read(struct ex_softc *); 86 void ex_reset(struct ex_softc *); 87 void ex_set_mc(struct ex_softc *); 88 void ex_getstats(struct ex_softc *); 89 void ex_tick(void *); 90 91 static int ex_eeprom_busy(struct ex_softc *); 92 static int ex_add_rxbuf(struct ex_softc *, struct ex_rxdesc *); 93 static void ex_init_txdescs(struct ex_softc *); 94 95 static void ex_setup_tx(struct ex_softc *); 96 static bool ex_shutdown(device_t, int); 97 static void ex_start(struct ifnet *); 98 static void ex_txstat(struct ex_softc *); 99 100 int ex_mii_readreg(device_t, int, int, uint16_t *); 101 int ex_mii_writereg(device_t, int, int, uint16_t); 102 void ex_mii_statchg(struct ifnet *); 103 104 void ex_probemedia(struct ex_softc *); 105 106 /* 107 * Structure to map media-present bits in boards to ifmedia codes and 108 * printable media names. Used for table-driven ifmedia initialization. 109 */ 110 struct ex_media { 111 int exm_mpbit; /* media present bit */ 112 const char *exm_name; /* name of medium */ 113 int exm_ifmedia; /* ifmedia word for medium */ 114 int exm_epmedia; /* ELINKMEDIA_* constant */ 115 }; 116 117 /* 118 * Media table for 3c90x chips. Note that chips with MII have no 119 * `native' media. 120 */ 121 static const struct ex_media ex_native_media[] = { 122 { ELINK_PCI_10BASE_T, "10baseT", IFM_ETHER | IFM_10_T, 123 ELINKMEDIA_10BASE_T }, 124 { ELINK_PCI_10BASE_T, "10baseT-FDX", IFM_ETHER | IFM_10_T | IFM_FDX, 125 ELINKMEDIA_10BASE_T }, 126 { ELINK_PCI_AUI, "10base5", IFM_ETHER | IFM_10_5, 127 ELINKMEDIA_AUI }, 128 { ELINK_PCI_BNC, "10base2", IFM_ETHER | IFM_10_2, 129 ELINKMEDIA_10BASE_2 }, 130 { ELINK_PCI_100BASE_TX, "100baseTX", IFM_ETHER | IFM_100_TX, 131 ELINKMEDIA_100BASE_TX }, 132 { ELINK_PCI_100BASE_TX, "100baseTX-FDX",IFM_ETHER | IFM_100_TX|IFM_FDX, 133 ELINKMEDIA_100BASE_TX }, 134 { ELINK_PCI_100BASE_FX, "100baseFX", IFM_ETHER | IFM_100_FX, 135 ELINKMEDIA_100BASE_FX }, 136 { ELINK_PCI_100BASE_MII,"manual", IFM_ETHER | IFM_MANUAL, 137 ELINKMEDIA_MII }, 138 { ELINK_PCI_100BASE_T4, "100baseT4", IFM_ETHER | IFM_100_T4, 139 ELINKMEDIA_100BASE_T4 }, 140 { 0, NULL, 0, 141 0 }, 142 }; 143 144 /* 145 * MII bit-bang glue. 146 */ 147 uint32_t ex_mii_bitbang_read(device_t); 148 void ex_mii_bitbang_write(device_t, uint32_t); 149 150 const struct mii_bitbang_ops ex_mii_bitbang_ops = { 151 ex_mii_bitbang_read, 152 ex_mii_bitbang_write, 153 { 154 ELINK_PHY_DATA, /* MII_BIT_MDO */ 155 ELINK_PHY_DATA, /* MII_BIT_MDI */ 156 ELINK_PHY_CLK, /* MII_BIT_MDC */ 157 ELINK_PHY_DIR, /* MII_BIT_DIR_HOST_PHY */ 158 0, /* MII_BIT_DIR_PHY_HOST */ 159 } 160 }; 161 162 /* 163 * Back-end attach and configure. 164 */ 165 void 166 ex_config(struct ex_softc *sc) 167 { 168 struct ifnet *ifp; 169 struct mii_data * const mii = &sc->ex_mii; 170 uint16_t val; 171 uint8_t macaddr[ETHER_ADDR_LEN] = {0}; 172 bus_space_tag_t iot = sc->sc_iot; 173 bus_space_handle_t ioh = sc->sc_ioh; 174 int i, error, attach_stage; 175 176 pmf_self_suspensor_init(sc->sc_dev, &sc->sc_suspensor, &sc->sc_qual); 177 178 callout_init(&sc->ex_mii_callout, 0); 179 180 ex_reset(sc); 181 182 val = ex_read_eeprom(sc, EEPROM_OEM_ADDR0); 183 macaddr[0] = val >> 8; 184 macaddr[1] = val & 0xff; 185 val = ex_read_eeprom(sc, EEPROM_OEM_ADDR1); 186 macaddr[2] = val >> 8; 187 macaddr[3] = val & 0xff; 188 val = ex_read_eeprom(sc, EEPROM_OEM_ADDR2); 189 macaddr[4] = val >> 8; 190 macaddr[5] = val & 0xff; 191 192 aprint_normal_dev(sc->sc_dev, "MAC address %s\n", 193 ether_sprintf(macaddr)); 194 195 if (sc->ex_conf & (EX_CONF_INV_LED_POLARITY | EX_CONF_PHY_POWER)) { 196 GO_WINDOW(2); 197 val = bus_space_read_2(iot, ioh, ELINK_W2_RESET_OPTIONS); 198 if (sc->ex_conf & EX_CONF_INV_LED_POLARITY) 199 val |= ELINK_RESET_OPT_LEDPOLAR; 200 if (sc->ex_conf & EX_CONF_PHY_POWER) 201 val |= ELINK_RESET_OPT_PHYPOWER; 202 bus_space_write_2(iot, ioh, ELINK_W2_RESET_OPTIONS, val); 203 } 204 if (sc->ex_conf & EX_CONF_NO_XCVR_PWR) { 205 GO_WINDOW(0); 206 bus_space_write_2(iot, ioh, ELINK_W0_MFG_ID, 207 EX_XCVR_PWR_MAGICBITS); 208 } 209 210 attach_stage = 0; 211 212 /* 213 * Allocate the upload descriptors, and create and load the DMA 214 * map for them. 215 */ 216 if ((error = bus_dmamem_alloc(sc->sc_dmat, 217 EX_NUPD * sizeof (struct ex_upd), PAGE_SIZE, 0, &sc->sc_useg, 1, 218 &sc->sc_urseg, BUS_DMA_NOWAIT)) != 0) { 219 aprint_error_dev(sc->sc_dev, 220 "can't allocate upload descriptors, error = %d\n", error); 221 goto fail; 222 } 223 224 attach_stage = 1; 225 226 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_useg, sc->sc_urseg, 227 EX_NUPD * sizeof (struct ex_upd), (void **)&sc->sc_upd, 228 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 229 aprint_error_dev(sc->sc_dev, 230 "can't map upload descriptors, error = %d\n", error); 231 goto fail; 232 } 233 234 attach_stage = 2; 235 236 if ((error = bus_dmamap_create(sc->sc_dmat, 237 EX_NUPD * sizeof (struct ex_upd), 1, 238 EX_NUPD * sizeof (struct ex_upd), 0, BUS_DMA_NOWAIT, 239 &sc->sc_upd_dmamap)) != 0) { 240 aprint_error_dev(sc->sc_dev, 241 "can't create upload desc. DMA map, error = %d\n", error); 242 goto fail; 243 } 244 245 attach_stage = 3; 246 247 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_upd_dmamap, 248 sc->sc_upd, EX_NUPD * sizeof (struct ex_upd), NULL, 249 BUS_DMA_NOWAIT)) != 0) { 250 aprint_error_dev(sc->sc_dev, 251 "can't load upload desc. DMA map, error = %d\n", error); 252 goto fail; 253 } 254 255 attach_stage = 4; 256 257 /* 258 * Allocate the download descriptors, and create and load the DMA 259 * map for them. 260 */ 261 if ((error = bus_dmamem_alloc(sc->sc_dmat, 262 DPDMEM_SIZE + EX_IP4CSUMTX_PADLEN, PAGE_SIZE, 0, &sc->sc_dseg, 1, 263 &sc->sc_drseg, BUS_DMA_NOWAIT)) != 0) { 264 aprint_error_dev(sc->sc_dev, 265 "can't allocate download descriptors, error = %d\n", error); 266 goto fail; 267 } 268 269 attach_stage = 5; 270 271 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dseg, sc->sc_drseg, 272 DPDMEM_SIZE + EX_IP4CSUMTX_PADLEN, (void **)&sc->sc_dpd, 273 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 274 aprint_error_dev(sc->sc_dev, 275 "can't map download descriptors, error = %d\n", error); 276 goto fail; 277 } 278 memset(sc->sc_dpd, 0, DPDMEM_SIZE + EX_IP4CSUMTX_PADLEN); 279 280 attach_stage = 6; 281 282 if ((error = bus_dmamap_create(sc->sc_dmat, 283 DPDMEM_SIZE + EX_IP4CSUMTX_PADLEN, 1, 284 DPDMEM_SIZE + EX_IP4CSUMTX_PADLEN, 0, BUS_DMA_NOWAIT, 285 &sc->sc_dpd_dmamap)) != 0) { 286 aprint_error_dev(sc->sc_dev, 287 "can't create download desc. DMA map, error = %d\n", error); 288 goto fail; 289 } 290 291 attach_stage = 7; 292 293 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dpd_dmamap, 294 sc->sc_dpd, DPDMEM_SIZE + EX_IP4CSUMTX_PADLEN, NULL, 295 BUS_DMA_NOWAIT)) != 0) { 296 aprint_error_dev(sc->sc_dev, 297 "can't load download desc. DMA map, error = %d\n", error); 298 goto fail; 299 } 300 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap, 301 DPDMEMPAD_OFF, EX_IP4CSUMTX_PADLEN, BUS_DMASYNC_PREWRITE); 302 303 attach_stage = 8; 304 305 306 /* 307 * Create the transmit buffer DMA maps. 308 */ 309 for (i = 0; i < EX_NDPD; i++) { 310 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 311 EX_NTFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 312 &sc->sc_tx_dmamaps[i])) != 0) { 313 aprint_error_dev(sc->sc_dev, 314 "can't create tx DMA map %d, error = %d\n", 315 i, error); 316 goto fail; 317 } 318 } 319 320 attach_stage = 9; 321 322 /* 323 * Create the receive buffer DMA maps. 324 */ 325 for (i = 0; i < EX_NUPD; i++) { 326 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 327 EX_NRFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 328 &sc->sc_rx_dmamaps[i])) != 0) { 329 aprint_error_dev(sc->sc_dev, 330 "can't create rx DMA map %d, error = %d\n", 331 i, error); 332 goto fail; 333 } 334 } 335 336 attach_stage = 10; 337 338 /* 339 * Create ring of upload descriptors, only once. The DMA engine 340 * will loop over this when receiving packets, stalling if it 341 * hits an UPD with a finished receive. 342 */ 343 for (i = 0; i < EX_NUPD; i++) { 344 sc->sc_rxdescs[i].rx_dmamap = sc->sc_rx_dmamaps[i]; 345 sc->sc_rxdescs[i].rx_upd = &sc->sc_upd[i]; 346 sc->sc_upd[i].upd_frags[0].fr_len = 347 htole32((MCLBYTES - 2) | EX_FR_LAST); 348 if (ex_add_rxbuf(sc, &sc->sc_rxdescs[i]) != 0) { 349 aprint_error_dev(sc->sc_dev, 350 "can't allocate or map rx buffers\n"); 351 goto fail; 352 } 353 } 354 355 bus_dmamap_sync(sc->sc_dmat, sc->sc_upd_dmamap, 0, 356 EX_NUPD * sizeof (struct ex_upd), 357 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 358 359 ex_init_txdescs(sc); 360 361 attach_stage = 11; 362 363 364 GO_WINDOW(3); 365 val = bus_space_read_2(iot, ioh, ELINK_W3_RESET_OPTIONS); 366 if (val & ELINK_MEDIACAP_MII) 367 sc->ex_conf |= EX_CONF_MII; 368 369 ifp = &sc->sc_ethercom.ec_if; 370 371 /* 372 * Initialize our media structures and MII info. We'll 373 * probe the MII if we discover that we have one. 374 */ 375 mii->mii_ifp = ifp; 376 mii->mii_readreg = ex_mii_readreg; 377 mii->mii_writereg = ex_mii_writereg; 378 mii->mii_statchg = ex_mii_statchg; 379 sc->sc_ethercom.ec_mii = mii; 380 ifmedia_init(&mii->mii_media, IFM_IMASK, ex_media_chg, ex_media_stat); 381 382 if (sc->ex_conf & EX_CONF_MII) { 383 /* 384 * Find PHY, extract media information from it. 385 * First, select the right transceiver. 386 */ 387 ex_set_xcvr(sc, val); 388 389 mii_attach(sc->sc_dev, mii, 0xffffffff, 390 MII_PHY_ANY, MII_OFFSET_ANY, 0); 391 if (LIST_FIRST(&mii->mii_phys) == NULL) { 392 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 393 0, NULL); 394 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 395 } else { 396 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 397 } 398 } else 399 ex_probemedia(sc); 400 401 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 402 ifp->if_softc = sc; 403 ifp->if_start = ex_start; 404 ifp->if_ioctl = ex_ioctl; 405 ifp->if_watchdog = ex_watchdog; 406 ifp->if_init = ex_init; 407 ifp->if_stop = ex_stop; 408 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 409 sc->sc_if_flags = ifp->if_flags; 410 IFQ_SET_READY(&ifp->if_snd); 411 412 /* 413 * We can support 802.1Q VLAN-sized frames. 414 */ 415 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 416 417 /* 418 * The 3c90xB has hardware IPv4/TCPv4/UDPv4 checksum support. 419 */ 420 if (sc->ex_conf & EX_CONF_90XB) 421 sc->sc_ethercom.ec_if.if_capabilities |= 422 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 423 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 424 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 425 426 if_attach(ifp); 427 if_deferred_start_init(ifp, NULL); 428 ether_ifattach(ifp, macaddr); 429 ether_set_ifflags_cb(&sc->sc_ethercom, ex_ifflags_cb); 430 431 GO_WINDOW(1); 432 433 sc->tx_start_thresh = 20; 434 sc->tx_succ_ok = 0; 435 436 /* TODO: set queues to 0 */ 437 438 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 439 RND_TYPE_NET, RND_FLAG_DEFAULT); 440 441 if (pmf_device_register1(sc->sc_dev, NULL, NULL, ex_shutdown)) 442 pmf_class_network_register(sc->sc_dev, &sc->sc_ethercom.ec_if); 443 else 444 aprint_error_dev(sc->sc_dev, 445 "couldn't establish power handler\n"); 446 447 /* The attach is successful. */ 448 sc->ex_flags |= EX_FLAGS_ATTACHED; 449 return; 450 451 fail: 452 /* 453 * Free any resources we've allocated during the failed attach 454 * attempt. Do this in reverse order and fall though. 455 */ 456 switch (attach_stage) { 457 case 11: 458 { 459 struct ex_rxdesc *rxd; 460 461 for (i = 0; i < EX_NUPD; i++) { 462 rxd = &sc->sc_rxdescs[i]; 463 if (rxd->rx_mbhead != NULL) { 464 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 465 m_freem(rxd->rx_mbhead); 466 } 467 } 468 } 469 /* FALLTHROUGH */ 470 471 case 10: 472 for (i = 0; i < EX_NUPD; i++) 473 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rx_dmamaps[i]); 474 /* FALLTHROUGH */ 475 476 case 9: 477 for (i = 0; i < EX_NDPD; i++) 478 bus_dmamap_destroy(sc->sc_dmat, sc->sc_tx_dmamaps[i]); 479 /* FALLTHROUGH */ 480 case 8: 481 bus_dmamap_unload(sc->sc_dmat, sc->sc_dpd_dmamap); 482 /* FALLTHROUGH */ 483 484 case 7: 485 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dpd_dmamap); 486 /* FALLTHROUGH */ 487 488 case 6: 489 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_dpd, 490 EX_NDPD * sizeof (struct ex_dpd)); 491 /* FALLTHROUGH */ 492 493 case 5: 494 bus_dmamem_free(sc->sc_dmat, &sc->sc_dseg, sc->sc_drseg); 495 break; 496 497 case 4: 498 bus_dmamap_unload(sc->sc_dmat, sc->sc_upd_dmamap); 499 /* FALLTHROUGH */ 500 501 case 3: 502 bus_dmamap_destroy(sc->sc_dmat, sc->sc_upd_dmamap); 503 /* FALLTHROUGH */ 504 505 case 2: 506 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_upd, 507 EX_NUPD * sizeof (struct ex_upd)); 508 /* FALLTHROUGH */ 509 510 case 1: 511 bus_dmamem_free(sc->sc_dmat, &sc->sc_useg, sc->sc_urseg); 512 break; 513 } 514 515 } 516 517 /* 518 * Find the media present on non-MII chips. 519 */ 520 void 521 ex_probemedia(struct ex_softc *sc) 522 { 523 bus_space_tag_t iot = sc->sc_iot; 524 bus_space_handle_t ioh = sc->sc_ioh; 525 struct ifmedia *ifm = &sc->ex_mii.mii_media; 526 const struct ex_media *exm; 527 uint16_t config1, reset_options, default_media; 528 int defmedia = 0; 529 const char *sep = "", *defmedianame = NULL; 530 531 GO_WINDOW(3); 532 config1 = bus_space_read_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG + 2); 533 reset_options = bus_space_read_1(iot, ioh, ELINK_W3_RESET_OPTIONS); 534 GO_WINDOW(0); 535 536 default_media = (config1 & CONFIG_MEDIAMASK) >> CONFIG_MEDIAMASK_SHIFT; 537 538 /* Sanity check that there are any media! */ 539 if ((reset_options & ELINK_PCI_MEDIAMASK) == 0) { 540 aprint_error_dev(sc->sc_dev, "no media present!\n"); 541 ifmedia_add(ifm, IFM_ETHER | IFM_NONE, 0, NULL); 542 ifmedia_set(ifm, IFM_ETHER | IFM_NONE); 543 return; 544 } 545 546 aprint_normal_dev(sc->sc_dev, ""); 547 548 #define PRINT(str) aprint_normal("%s%s", sep, str); sep = ", " 549 550 for (exm = ex_native_media; exm->exm_name != NULL; exm++) { 551 if (reset_options & exm->exm_mpbit) { 552 /* 553 * Default media is a little complicated. We 554 * support full-duplex which uses the same 555 * reset options bit. 556 * 557 * XXX Check EEPROM for default to FDX? 558 */ 559 if (exm->exm_epmedia == default_media) { 560 if ((exm->exm_ifmedia & IFM_FDX) == 0) { 561 defmedia = exm->exm_ifmedia; 562 defmedianame = exm->exm_name; 563 } 564 } else if (defmedia == 0) { 565 defmedia = exm->exm_ifmedia; 566 defmedianame = exm->exm_name; 567 } 568 ifmedia_add(ifm, exm->exm_ifmedia, exm->exm_epmedia, 569 NULL); 570 PRINT(exm->exm_name); 571 } 572 } 573 574 #undef PRINT 575 576 #ifdef DIAGNOSTIC 577 if (defmedia == 0) 578 panic("ex_probemedia: impossible"); 579 #endif 580 581 aprint_normal(", default %s\n", defmedianame); 582 ifmedia_set(ifm, defmedia); 583 } 584 585 /* 586 * Setup transmitter parameters. 587 */ 588 static void 589 ex_setup_tx(struct ex_softc *sc) 590 { 591 bus_space_tag_t iot = sc->sc_iot; 592 bus_space_handle_t ioh = sc->sc_ioh; 593 594 /* 595 * Disable reclaim threshold for 90xB, set free threshold to 596 * 6 * 256 = 1536 for 90x. 597 */ 598 if (sc->ex_conf & EX_CONF_90XB) 599 bus_space_write_2(iot, ioh, ELINK_COMMAND, 600 ELINK_TXRECLTHRESH | 255); 601 else 602 bus_space_write_1(iot, ioh, ELINK_TXFREETHRESH, 6); 603 604 /* Setup early transmission start threshold. */ 605 bus_space_write_2(iot, ioh, ELINK_COMMAND, 606 ELINK_TXSTARTTHRESH | sc->tx_start_thresh); 607 } 608 609 /* 610 * Bring device up. 611 */ 612 int 613 ex_init(struct ifnet *ifp) 614 { 615 struct ex_softc *sc = ifp->if_softc; 616 bus_space_tag_t iot = sc->sc_iot; 617 bus_space_handle_t ioh = sc->sc_ioh; 618 int i; 619 uint16_t val; 620 int error = 0; 621 622 if ((error = ex_enable(sc)) != 0) 623 goto out; 624 625 ex_waitcmd(sc); 626 ex_stop(ifp, 0); 627 628 GO_WINDOW(2); 629 630 /* Turn on PHY power. */ 631 if (sc->ex_conf & (EX_CONF_PHY_POWER | EX_CONF_INV_LED_POLARITY)) { 632 val = bus_space_read_2(iot, ioh, ELINK_W2_RESET_OPTIONS); 633 if (sc->ex_conf & EX_CONF_PHY_POWER) 634 val |= ELINK_RESET_OPT_PHYPOWER; /* turn on PHY power */ 635 if (sc->ex_conf & EX_CONF_INV_LED_POLARITY) 636 val |= ELINK_RESET_OPT_LEDPOLAR; /* invert LED polarity */ 637 bus_space_write_2(iot, ioh, ELINK_W2_RESET_OPTIONS, val); 638 } 639 640 /* 641 * Set the station address and clear the station mask. The latter 642 * is needed for 90x cards, 0 is the default for 90xB cards. 643 */ 644 for (i = 0; i < ETHER_ADDR_LEN; i++) { 645 bus_space_write_1(iot, ioh, ELINK_W2_ADDR_0 + i, 646 CLLADDR(ifp->if_sadl)[i]); 647 bus_space_write_1(iot, ioh, ELINK_W2_RECVMASK_0 + i, 0); 648 } 649 650 GO_WINDOW(3); 651 652 bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_RESET); 653 ex_waitcmd(sc); 654 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_RESET); 655 ex_waitcmd(sc); 656 657 /* Load Tx parameters. */ 658 ex_setup_tx(sc); 659 660 bus_space_write_2(iot, ioh, ELINK_COMMAND, 661 SET_RX_EARLY_THRESH | ELINK_THRESH_DISABLE); 662 663 bus_space_write_4(iot, ioh, ELINK_DMACTRL, 664 bus_space_read_4(iot, ioh, ELINK_DMACTRL) | ELINK_DMAC_UPRXEAREN); 665 666 bus_space_write_2(iot, ioh, ELINK_COMMAND, 667 SET_RD_0_MASK | XL_WATCHED_INTERRUPTS); 668 bus_space_write_2(iot, ioh, ELINK_COMMAND, 669 SET_INTR_MASK | XL_WATCHED_INTERRUPTS); 670 671 bus_space_write_2(iot, ioh, ELINK_COMMAND, ACK_INTR | 0xff); 672 if (sc->intr_ack) 673 (* sc->intr_ack)(sc); 674 ex_set_media(sc); 675 ex_set_mc(sc); 676 677 678 bus_space_write_2(iot, ioh, ELINK_COMMAND, STATS_ENABLE); 679 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_ENABLE); 680 bus_space_write_4(iot, ioh, ELINK_UPLISTPTR, sc->sc_upddma); 681 bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_ENABLE); 682 bus_space_write_2(iot, ioh, ELINK_COMMAND, ELINK_UPUNSTALL); 683 684 ifp->if_flags |= IFF_RUNNING; 685 ifp->if_flags &= ~IFF_OACTIVE; 686 ex_start(ifp); 687 sc->sc_if_flags = ifp->if_flags; 688 689 GO_WINDOW(1); 690 691 callout_reset(&sc->ex_mii_callout, hz, ex_tick, sc); 692 693 out: 694 if (error) { 695 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 696 ifp->if_timer = 0; 697 aprint_error_dev(sc->sc_dev, "interface not running\n"); 698 } 699 return (error); 700 } 701 702 #define MCHASHSIZE 256 703 #define ex_mchash(addr) (ether_crc32_be((addr), ETHER_ADDR_LEN) & \ 704 (MCHASHSIZE - 1)) 705 706 /* 707 * Set multicast receive filter. Also take care of promiscuous mode 708 * here (XXX). 709 */ 710 void 711 ex_set_mc(struct ex_softc *sc) 712 { 713 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 714 struct ethercom *ec = &sc->sc_ethercom; 715 struct ether_multi *enm; 716 struct ether_multistep estep; 717 int i; 718 uint16_t mask = FIL_INDIVIDUAL | FIL_BRDCST; 719 720 if (ifp->if_flags & IFF_PROMISC) { 721 mask |= FIL_PROMISC; 722 goto allmulti; 723 } 724 725 ETHER_LOCK(ec); 726 ETHER_FIRST_MULTI(estep, ec, enm); 727 if (enm == NULL) { 728 ETHER_UNLOCK(ec); 729 goto nomulti; 730 } 731 732 if ((sc->ex_conf & EX_CONF_90XB) == 0) { 733 /* No multicast hash filtering. */ 734 ETHER_UNLOCK(ec); 735 goto allmulti; 736 } 737 738 for (i = 0; i < MCHASHSIZE; i++) 739 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 740 ELINK_COMMAND, ELINK_CLEARHASHFILBIT | i); 741 742 do { 743 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 744 ETHER_ADDR_LEN) != 0) { 745 ETHER_UNLOCK(ec); 746 goto allmulti; 747 } 748 749 i = ex_mchash(enm->enm_addrlo); 750 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 751 ELINK_COMMAND, ELINK_SETHASHFILBIT | i); 752 ETHER_NEXT_MULTI(estep, enm); 753 } while (enm != NULL); 754 ETHER_UNLOCK(ec); 755 mask |= FIL_MULTIHASH; 756 757 nomulti: 758 ifp->if_flags &= ~IFF_ALLMULTI; 759 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_COMMAND, 760 SET_RX_FILTER | mask); 761 return; 762 763 allmulti: 764 ifp->if_flags |= IFF_ALLMULTI; 765 mask |= FIL_MULTICAST; 766 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_COMMAND, 767 SET_RX_FILTER | mask); 768 } 769 770 771 /* 772 * The Tx Complete interrupts occur only on errors, 773 * and this is the error handler. 774 */ 775 static void 776 ex_txstat(struct ex_softc *sc) 777 { 778 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 779 bus_space_tag_t iot = sc->sc_iot; 780 bus_space_handle_t ioh = sc->sc_ioh; 781 int i, err = 0; 782 783 /* 784 * We need to read+write TX_STATUS until we get a 0 status 785 * in order to turn off the interrupt flag. 786 * ELINK_TXSTATUS is in the upper byte of 2 with ELINK_TIMER. 787 */ 788 for (;;) { 789 i = bus_space_read_2(iot, ioh, ELINK_TIMER); 790 if ((i & TXS_COMPLETE) == 0) 791 break; 792 bus_space_write_2(iot, ioh, ELINK_TIMER, 0x0); 793 err |= i; 794 } 795 err &= ~TXS_TIMER; 796 797 if ((err & (TXS_UNDERRUN | TXS_JABBER | TXS_RECLAIM)) 798 || err == 0 /* should not happen, just in case */) { 799 /* 800 * Make sure the transmission is stopped. 801 */ 802 bus_space_write_2(iot, ioh, ELINK_COMMAND, ELINK_DNSTALL); 803 for (i = 1000; i > 0; i--) 804 if ((bus_space_read_4(iot, ioh, ELINK_DMACTRL) & 805 ELINK_DMAC_DNINPROG) == 0) 806 break; 807 808 /* 809 * Reset the transmitter. 810 */ 811 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_RESET); 812 813 /* Resetting takes a while and we will do more than wait. */ 814 815 ifp->if_flags &= ~IFF_OACTIVE; 816 if_statinc(ifp, if_oerrors); 817 aprint_error_dev(sc->sc_dev, "%s%s%s", 818 (err & TXS_UNDERRUN) ? " transmit underrun" : "", 819 (err & TXS_JABBER) ? " jabber" : "", 820 (err & TXS_RECLAIM) ? " reclaim" : ""); 821 if (err == 0) 822 aprint_error(" unknown Tx error"); 823 printf(" (%x)", err); 824 if (err & TXS_UNDERRUN) { 825 aprint_error(" @%d", sc->tx_start_thresh); 826 if (sc->tx_succ_ok < 256 && 827 (i = uimin(ETHER_MAX_LEN, sc->tx_start_thresh + 20)) 828 > sc->tx_start_thresh) { 829 aprint_error(", new threshold is %d", i); 830 sc->tx_start_thresh = i; 831 } 832 sc->tx_succ_ok = 0; 833 } 834 aprint_error("\n"); 835 if (err & TXS_MAX_COLLISION) 836 if_statinc(ifp, if_collisions); 837 838 /* Wait for TX_RESET to finish. */ 839 ex_waitcmd(sc); 840 841 /* Reload Tx parameters. */ 842 ex_setup_tx(sc); 843 } else { 844 if (err & TXS_MAX_COLLISION) 845 if_statinc(ifp, if_collisions); 846 sc->sc_ethercom.ec_if.if_flags &= ~IFF_OACTIVE; 847 } 848 849 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_ENABLE); 850 851 /* Retransmit current packet if any. */ 852 if (sc->tx_head) { 853 ifp->if_flags |= IFF_OACTIVE; 854 bus_space_write_2(iot, ioh, ELINK_COMMAND, 855 ELINK_DNUNSTALL); 856 bus_space_write_4(iot, ioh, ELINK_DNLISTPTR, 857 DPD_DMADDR(sc, sc->tx_head)); 858 859 /* Retrigger watchdog if stopped. */ 860 if (ifp->if_timer == 0) 861 ifp->if_timer = 1; 862 } 863 } 864 865 int 866 ex_media_chg(struct ifnet *ifp) 867 { 868 869 if (ifp->if_flags & IFF_UP) 870 ex_init(ifp); 871 return 0; 872 } 873 874 void 875 ex_set_xcvr(struct ex_softc *sc, const uint16_t media) 876 { 877 bus_space_tag_t iot = sc->sc_iot; 878 bus_space_handle_t ioh = sc->sc_ioh; 879 uint32_t icfg; 880 881 /* 882 * We're already in Window 3 883 */ 884 icfg = bus_space_read_4(iot, ioh, ELINK_W3_INTERNAL_CONFIG); 885 icfg &= ~(CONFIG_XCVR_SEL << 16); 886 if (media & (ELINK_MEDIACAP_MII | ELINK_MEDIACAP_100BASET4)) 887 icfg |= ELINKMEDIA_MII << (CONFIG_XCVR_SEL_SHIFT + 16); 888 if (media & ELINK_MEDIACAP_100BASETX) 889 icfg |= ELINKMEDIA_AUTO << (CONFIG_XCVR_SEL_SHIFT + 16); 890 if (media & ELINK_MEDIACAP_100BASEFX) 891 icfg |= ELINKMEDIA_100BASE_FX 892 << (CONFIG_XCVR_SEL_SHIFT + 16); 893 bus_space_write_4(iot, ioh, ELINK_W3_INTERNAL_CONFIG, icfg); 894 } 895 896 void 897 ex_set_media(struct ex_softc *sc) 898 { 899 bus_space_tag_t iot = sc->sc_iot; 900 bus_space_handle_t ioh = sc->sc_ioh; 901 uint32_t configreg; 902 903 if (((sc->ex_conf & EX_CONF_MII) && 904 (sc->ex_mii.mii_media_active & IFM_FDX)) 905 || (!(sc->ex_conf & EX_CONF_MII) && 906 (sc->ex_mii.mii_media.ifm_media & IFM_FDX))) { 907 bus_space_write_2(iot, ioh, ELINK_W3_MAC_CONTROL, 908 MAC_CONTROL_FDX); 909 } else { 910 bus_space_write_2(iot, ioh, ELINK_W3_MAC_CONTROL, 0); 911 } 912 913 /* 914 * If the device has MII, select it, and then tell the 915 * PHY which media to use. 916 */ 917 if (sc->ex_conf & EX_CONF_MII) { 918 uint16_t val; 919 920 GO_WINDOW(3); 921 val = bus_space_read_2(iot, ioh, ELINK_W3_RESET_OPTIONS); 922 ex_set_xcvr(sc, val); 923 mii_mediachg(&sc->ex_mii); 924 return; 925 } 926 927 GO_WINDOW(4); 928 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 0); 929 bus_space_write_2(iot, ioh, ELINK_COMMAND, STOP_TRANSCEIVER); 930 delay(800); 931 932 /* 933 * Now turn on the selected media/transceiver. 934 */ 935 switch (IFM_SUBTYPE(sc->ex_mii.mii_media.ifm_cur->ifm_media)) { 936 case IFM_10_T: 937 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 938 JABBER_GUARD_ENABLE | LINKBEAT_ENABLE); 939 break; 940 941 case IFM_10_2: 942 bus_space_write_2(iot, ioh, ELINK_COMMAND, START_TRANSCEIVER); 943 DELAY(800); 944 break; 945 946 case IFM_100_TX: 947 case IFM_100_FX: 948 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 949 LINKBEAT_ENABLE); 950 DELAY(800); 951 break; 952 953 case IFM_10_5: 954 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 955 SQE_ENABLE); 956 DELAY(800); 957 break; 958 959 case IFM_MANUAL: 960 break; 961 962 case IFM_NONE: 963 return; 964 965 default: 966 panic("ex_set_media: impossible"); 967 } 968 969 GO_WINDOW(3); 970 configreg = bus_space_read_4(iot, ioh, ELINK_W3_INTERNAL_CONFIG); 971 972 configreg &= ~(CONFIG_MEDIAMASK << 16); 973 configreg |= (sc->ex_mii.mii_media.ifm_cur->ifm_data << 974 (CONFIG_MEDIAMASK_SHIFT + 16)); 975 976 bus_space_write_4(iot, ioh, ELINK_W3_INTERNAL_CONFIG, configreg); 977 } 978 979 /* 980 * Get currently-selected media from card. 981 * (if_media callback, may be called before interface is brought up). 982 */ 983 void 984 ex_media_stat(struct ifnet *ifp, struct ifmediareq *req) 985 { 986 struct ex_softc *sc = ifp->if_softc; 987 uint16_t help; 988 989 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP|IFF_RUNNING)) { 990 if (sc->ex_conf & EX_CONF_MII) { 991 mii_pollstat(&sc->ex_mii); 992 req->ifm_status = sc->ex_mii.mii_media_status; 993 req->ifm_active = sc->ex_mii.mii_media_active; 994 } else { 995 GO_WINDOW(4); 996 req->ifm_status = IFM_AVALID; 997 req->ifm_active = 998 sc->ex_mii.mii_media.ifm_cur->ifm_media; 999 help = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 1000 ELINK_W4_MEDIA_TYPE); 1001 if (help & LINKBEAT_DETECT) 1002 req->ifm_status |= IFM_ACTIVE; 1003 GO_WINDOW(1); 1004 } 1005 } 1006 } 1007 1008 1009 1010 /* 1011 * Start outputting on the interface. 1012 */ 1013 static void 1014 ex_start(struct ifnet *ifp) 1015 { 1016 struct ex_softc *sc = ifp->if_softc; 1017 bus_space_tag_t iot = sc->sc_iot; 1018 bus_space_handle_t ioh = sc->sc_ioh; 1019 volatile struct ex_fraghdr *fr = NULL; 1020 volatile struct ex_dpd *dpd = NULL, *prevdpd = NULL; 1021 struct ex_txdesc *txp; 1022 struct mbuf *mb_head; 1023 bus_dmamap_t dmamap; 1024 int m_csumflags, offset, seglen, totlen, segment, error; 1025 uint32_t csum_flags; 1026 1027 if (sc->tx_head || sc->tx_free == NULL) 1028 return; 1029 1030 txp = NULL; 1031 1032 /* 1033 * We're finished if there is nothing more to add to the list or if 1034 * we're all filled up with buffers to transmit. 1035 */ 1036 while (sc->tx_free != NULL) { 1037 /* 1038 * Grab a packet to transmit. 1039 */ 1040 IFQ_DEQUEUE(&ifp->if_snd, mb_head); 1041 if (mb_head == NULL) 1042 break; 1043 1044 /* 1045 * mb_head might be updated later, 1046 * so preserve csum_flags here. 1047 */ 1048 m_csumflags = mb_head->m_pkthdr.csum_flags; 1049 1050 /* 1051 * Get pointer to next available tx desc. 1052 */ 1053 txp = sc->tx_free; 1054 dmamap = txp->tx_dmamap; 1055 1056 /* 1057 * Go through each of the mbufs in the chain and initialize 1058 * the transmit buffer descriptors with the physical address 1059 * and size of the mbuf. 1060 */ 1061 reload: 1062 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1063 mb_head, BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1064 switch (error) { 1065 case 0: 1066 /* Success. */ 1067 break; 1068 1069 case EFBIG: 1070 { 1071 struct mbuf *mn; 1072 1073 /* 1074 * We ran out of segments. We have to recopy this 1075 * mbuf chain first. Bail out if we can't get the 1076 * new buffers. 1077 */ 1078 aprint_error_dev(sc->sc_dev, "too many segments, "); 1079 1080 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1081 if (mn == NULL) { 1082 m_freem(mb_head); 1083 aprint_error("aborting\n"); 1084 goto out; 1085 } 1086 if (mb_head->m_pkthdr.len > MHLEN) { 1087 MCLGET(mn, M_DONTWAIT); 1088 if ((mn->m_flags & M_EXT) == 0) { 1089 m_freem(mn); 1090 m_freem(mb_head); 1091 aprint_error("aborting\n"); 1092 goto out; 1093 } 1094 } 1095 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1096 mtod(mn, void *)); 1097 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1098 m_freem(mb_head); 1099 mb_head = mn; 1100 aprint_error("retrying\n"); 1101 goto reload; 1102 } 1103 1104 default: 1105 /* 1106 * Some other problem; report it. 1107 */ 1108 aprint_error_dev(sc->sc_dev, 1109 "can't load mbuf chain, error = %d\n", error); 1110 m_freem(mb_head); 1111 goto out; 1112 } 1113 1114 /* 1115 * remove our tx desc from freelist. 1116 */ 1117 sc->tx_free = txp->tx_next; 1118 txp->tx_next = NULL; 1119 1120 fr = &txp->tx_dpd->dpd_frags[0]; 1121 totlen = 0; 1122 for (segment = 0; segment < dmamap->dm_nsegs; segment++, fr++) { 1123 fr->fr_addr = htole32(dmamap->dm_segs[segment].ds_addr); 1124 seglen = dmamap->dm_segs[segment].ds_len; 1125 fr->fr_len = htole32(seglen); 1126 totlen += seglen; 1127 } 1128 if (__predict_false(totlen <= EX_IP4CSUMTX_PADLEN && 1129 (m_csumflags & M_CSUM_IPv4) != 0)) { 1130 /* 1131 * Pad short packets to avoid ip4csum-tx bug. 1132 * 1133 * XXX Should we still consider if such short 1134 * (36 bytes or less) packets might already 1135 * occupy EX_NTFRAG (== 32) fragments here? 1136 */ 1137 KASSERT(segment < EX_NTFRAGS); 1138 fr->fr_addr = htole32(DPDMEMPAD_DMADDR(sc)); 1139 seglen = EX_IP4CSUMTX_PADLEN + 1 - totlen; 1140 fr->fr_len = htole32(EX_FR_LAST | seglen); 1141 totlen += seglen; 1142 } else { 1143 fr--; 1144 fr->fr_len |= htole32(EX_FR_LAST); 1145 } 1146 txp->tx_mbhead = mb_head; 1147 1148 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1149 BUS_DMASYNC_PREWRITE); 1150 1151 dpd = txp->tx_dpd; 1152 dpd->dpd_nextptr = 0; 1153 dpd->dpd_fsh = htole32(totlen); 1154 1155 /* Byte-swap constants so compiler can optimize. */ 1156 1157 if (sc->ex_conf & EX_CONF_90XB) { 1158 csum_flags = 0; 1159 1160 if (m_csumflags & M_CSUM_IPv4) 1161 csum_flags |= htole32(EX_DPD_IPCKSUM); 1162 1163 if (m_csumflags & M_CSUM_TCPv4) 1164 csum_flags |= htole32(EX_DPD_TCPCKSUM); 1165 else if (m_csumflags & M_CSUM_UDPv4) 1166 csum_flags |= htole32(EX_DPD_UDPCKSUM); 1167 1168 dpd->dpd_fsh |= csum_flags; 1169 } else { 1170 KDASSERT((mb_head->m_pkthdr.csum_flags & 1171 (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) == 0); 1172 } 1173 1174 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap, 1175 ((const char *)(intptr_t)dpd - (const char *)sc->sc_dpd), 1176 sizeof (struct ex_dpd), 1177 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1178 1179 /* 1180 * No need to stall the download engine, we know it's 1181 * not busy right now. 1182 * 1183 * Fix up pointers in both the "soft" tx and the physical 1184 * tx list. 1185 */ 1186 if (sc->tx_head != NULL) { 1187 prevdpd = sc->tx_tail->tx_dpd; 1188 offset = ((const char *)(intptr_t)prevdpd - (const char *)sc->sc_dpd); 1189 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap, 1190 offset, sizeof (struct ex_dpd), 1191 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1192 prevdpd->dpd_nextptr = htole32(DPD_DMADDR(sc, txp)); 1193 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap, 1194 offset, sizeof (struct ex_dpd), 1195 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1196 sc->tx_tail->tx_next = txp; 1197 sc->tx_tail = txp; 1198 } else { 1199 sc->tx_tail = sc->tx_head = txp; 1200 } 1201 1202 /* 1203 * Pass packet to bpf if there is a listener. 1204 */ 1205 bpf_mtap(ifp, mb_head, BPF_D_OUT); 1206 } 1207 out: 1208 if (sc->tx_head) { 1209 sc->tx_tail->tx_dpd->dpd_fsh |= htole32(EX_DPD_DNIND); 1210 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap, 1211 ((char *)sc->tx_tail->tx_dpd - (char *)sc->sc_dpd), 1212 sizeof (struct ex_dpd), 1213 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1214 ifp->if_flags |= IFF_OACTIVE; 1215 bus_space_write_2(iot, ioh, ELINK_COMMAND, ELINK_DNUNSTALL); 1216 bus_space_write_4(iot, ioh, ELINK_DNLISTPTR, 1217 DPD_DMADDR(sc, sc->tx_head)); 1218 1219 /* trigger watchdog */ 1220 ifp->if_timer = 5; 1221 } 1222 } 1223 1224 1225 int 1226 ex_intr(void *arg) 1227 { 1228 struct ex_softc *sc = arg; 1229 bus_space_tag_t iot = sc->sc_iot; 1230 bus_space_handle_t ioh = sc->sc_ioh; 1231 uint16_t stat; 1232 int ret = 0; 1233 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1234 1235 if ((ifp->if_flags & IFF_RUNNING) == 0 || 1236 !device_is_active(sc->sc_dev)) 1237 return (0); 1238 1239 for (;;) { 1240 stat = bus_space_read_2(iot, ioh, ELINK_STATUS); 1241 1242 if ((stat & XL_WATCHED_INTERRUPTS) == 0) { 1243 if ((stat & INTR_LATCH) == 0) { 1244 #if 0 1245 aprint_error_dev(sc->sc_dev, 1246 "intr latch cleared\n"); 1247 #endif 1248 break; 1249 } 1250 } 1251 1252 ret = 1; 1253 1254 /* 1255 * Acknowledge interrupts. 1256 */ 1257 bus_space_write_2(iot, ioh, ELINK_COMMAND, ACK_INTR | 1258 (stat & (XL_WATCHED_INTERRUPTS | INTR_LATCH))); 1259 if (sc->intr_ack) 1260 (*sc->intr_ack)(sc); 1261 1262 if (stat & HOST_ERROR) { 1263 aprint_error_dev(sc->sc_dev, 1264 "adapter failure (%x)\n", stat); 1265 ex_reset(sc); 1266 ex_init(ifp); 1267 return 1; 1268 } 1269 if (stat & UPD_STATS) { 1270 ex_getstats(sc); 1271 } 1272 if (stat & TX_COMPLETE) { 1273 ex_txstat(sc); 1274 #if 0 1275 if (stat & DN_COMPLETE) 1276 aprint_error_dev(sc->sc_dev, 1277 "Ignoring Dn interrupt (%x)\n", stat); 1278 #endif 1279 /* 1280 * In some rare cases, both Tx Complete and 1281 * Dn Complete bits are set. However, the packet 1282 * has been reloaded in ex_txstat() and should not 1283 * handle the Dn Complete event here. 1284 * Hence the "else" below. 1285 */ 1286 } else if (stat & DN_COMPLETE) { 1287 struct ex_txdesc *txp, *ptxp = NULL; 1288 bus_dmamap_t txmap; 1289 1290 /* reset watchdog timer, was set in ex_start() */ 1291 ifp->if_timer = 0; 1292 1293 for (txp = sc->tx_head; txp != NULL; 1294 txp = txp->tx_next) { 1295 bus_dmamap_sync(sc->sc_dmat, 1296 sc->sc_dpd_dmamap, 1297 (char *)txp->tx_dpd - (char *)sc->sc_dpd, 1298 sizeof (struct ex_dpd), 1299 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1300 if (txp->tx_mbhead != NULL) { 1301 txmap = txp->tx_dmamap; 1302 bus_dmamap_sync(sc->sc_dmat, txmap, 1303 0, txmap->dm_mapsize, 1304 BUS_DMASYNC_POSTWRITE); 1305 bus_dmamap_unload(sc->sc_dmat, txmap); 1306 m_freem(txp->tx_mbhead); 1307 txp->tx_mbhead = NULL; 1308 } 1309 ptxp = txp; 1310 } 1311 1312 /* 1313 * Move finished tx buffers back to the tx free list. 1314 */ 1315 if (sc->tx_free) { 1316 sc->tx_ftail->tx_next = sc->tx_head; 1317 sc->tx_ftail = ptxp; 1318 } else 1319 sc->tx_ftail = sc->tx_free = sc->tx_head; 1320 1321 sc->tx_head = sc->tx_tail = NULL; 1322 ifp->if_flags &= ~IFF_OACTIVE; 1323 1324 if (sc->tx_succ_ok < 256) 1325 sc->tx_succ_ok++; 1326 } 1327 1328 if (stat & UP_COMPLETE) { 1329 struct ex_rxdesc *rxd; 1330 struct mbuf *m; 1331 struct ex_upd *upd; 1332 bus_dmamap_t rxmap; 1333 uint32_t pktstat; 1334 1335 rcvloop: 1336 rxd = sc->rx_head; 1337 rxmap = rxd->rx_dmamap; 1338 m = rxd->rx_mbhead; 1339 upd = rxd->rx_upd; 1340 1341 bus_dmamap_sync(sc->sc_dmat, rxmap, 0, 1342 rxmap->dm_mapsize, 1343 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1344 bus_dmamap_sync(sc->sc_dmat, sc->sc_upd_dmamap, 1345 ((char *)upd - (char *)sc->sc_upd), 1346 sizeof (struct ex_upd), 1347 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1348 pktstat = le32toh(upd->upd_pktstatus); 1349 1350 if (pktstat & EX_UPD_COMPLETE) { 1351 /* 1352 * Remove first packet from the chain. 1353 */ 1354 sc->rx_head = rxd->rx_next; 1355 rxd->rx_next = NULL; 1356 1357 /* 1358 * Add a new buffer to the receive chain. 1359 * If this fails, the old buffer is recycled 1360 * instead. 1361 */ 1362 if (ex_add_rxbuf(sc, rxd) == 0) { 1363 uint16_t total_len; 1364 1365 if (pktstat & 1366 ((sc->sc_ethercom.ec_capenable & 1367 ETHERCAP_VLAN_MTU) ? 1368 EX_UPD_ERR_VLAN : EX_UPD_ERR)) { 1369 if_statinc(ifp, if_ierrors); 1370 m_freem(m); 1371 goto rcvloop; 1372 } 1373 1374 total_len = pktstat & EX_UPD_PKTLENMASK; 1375 if (total_len < 1376 sizeof(struct ether_header)) { 1377 m_freem(m); 1378 goto rcvloop; 1379 } 1380 m_set_rcvif(m, ifp); 1381 m->m_pkthdr.len = m->m_len = total_len; 1382 /* 1383 * Set the incoming checksum information for the packet. 1384 */ 1385 if ((sc->ex_conf & EX_CONF_90XB) != 0 && 1386 (pktstat & EX_UPD_IPCHECKED) != 0) { 1387 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1388 if (pktstat & EX_UPD_IPCKSUMERR) 1389 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1390 if (pktstat & EX_UPD_TCPCHECKED) { 1391 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1392 if (pktstat & EX_UPD_TCPCKSUMERR) 1393 m->m_pkthdr.csum_flags |= 1394 M_CSUM_TCP_UDP_BAD; 1395 } else if (pktstat & EX_UPD_UDPCHECKED) { 1396 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1397 if (pktstat & EX_UPD_UDPCKSUMERR) 1398 m->m_pkthdr.csum_flags |= 1399 M_CSUM_TCP_UDP_BAD; 1400 } 1401 } 1402 if_percpuq_enqueue(ifp->if_percpuq, m); 1403 } 1404 goto rcvloop; 1405 } 1406 /* 1407 * Just in case we filled up all UPDs and the DMA engine 1408 * stalled. We could be more subtle about this. 1409 */ 1410 if (bus_space_read_4(iot, ioh, ELINK_UPLISTPTR) == 0) { 1411 aprint_error_dev(sc->sc_dev, 1412 "uplistptr was 0\n"); 1413 ex_init(ifp); 1414 } else if (bus_space_read_4(iot, ioh, ELINK_UPPKTSTATUS) 1415 & 0x2000) { 1416 aprint_error_dev(sc->sc_dev, 1417 "receive stalled\n"); 1418 bus_space_write_2(iot, ioh, ELINK_COMMAND, 1419 ELINK_UPUNSTALL); 1420 } 1421 } 1422 1423 if (stat) 1424 rnd_add_uint32(&sc->rnd_source, stat); 1425 } 1426 1427 /* no more interrupts */ 1428 if (ret) 1429 if_schedule_deferred_start(ifp); 1430 return ret; 1431 } 1432 1433 static int 1434 ex_ifflags_cb(struct ethercom *ec) 1435 { 1436 struct ifnet *ifp = &ec->ec_if; 1437 struct ex_softc *sc = ifp->if_softc; 1438 u_short change = ifp->if_flags ^ sc->sc_if_flags; 1439 1440 if ((change & ~(IFF_CANTCHANGE | IFF_DEBUG)) != 0) 1441 return ENETRESET; 1442 else if ((change & IFF_PROMISC) != 0) 1443 ex_set_mc(sc); 1444 return 0; 1445 } 1446 1447 int 1448 ex_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1449 { 1450 struct ex_softc *sc = ifp->if_softc; 1451 int s, error; 1452 1453 s = splnet(); 1454 1455 switch (cmd) { 1456 default: 1457 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 1458 break; 1459 1460 error = 0; 1461 1462 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1463 ; 1464 else if (ifp->if_flags & IFF_RUNNING) { 1465 /* 1466 * Multicast list has changed; set the hardware filter 1467 * accordingly. 1468 */ 1469 ex_set_mc(sc); 1470 } 1471 break; 1472 } 1473 1474 sc->sc_if_flags = ifp->if_flags; 1475 splx(s); 1476 return (error); 1477 } 1478 1479 void 1480 ex_getstats(struct ex_softc *sc) 1481 { 1482 bus_space_handle_t ioh = sc->sc_ioh; 1483 bus_space_tag_t iot = sc->sc_iot; 1484 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1485 uint8_t upperok; 1486 1487 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 1488 1489 GO_WINDOW(6); 1490 upperok = bus_space_read_1(iot, ioh, UPPER_FRAMES_OK); 1491 if_statadd_ref(nsr, if_opackets, 1492 bus_space_read_1(iot, ioh, TX_FRAMES_OK)); 1493 if_statadd_ref(nsr, if_opackets, (upperok & 0x30) << 4); 1494 if_statadd_ref(nsr, if_ierrors, 1495 bus_space_read_1(iot, ioh, RX_OVERRUNS)); 1496 if_statadd_ref(nsr, if_collisions, 1497 bus_space_read_1(iot, ioh, TX_COLLISIONS)); 1498 /* 1499 * There seems to be no way to get the exact number of collisions, 1500 * this is the number that occurred at the very least. 1501 */ 1502 if_statadd_ref(nsr, if_collisions, 1503 2 * bus_space_read_1(iot, ioh, TX_AFTER_X_COLLISIONS)); 1504 1505 IF_STAT_PUTREF(ifp); 1506 1507 /* 1508 * Interface byte counts are counted by ether_input() and 1509 * ether_output(), so don't accumulate them here. Just 1510 * read the NIC counters so they don't generate overflow interrupts. 1511 * Upper byte counters are latched from reading the totals, so 1512 * they don't need to be read if we don't need their values. 1513 */ 1514 (void)bus_space_read_2(iot, ioh, RX_TOTAL_OK); 1515 (void)bus_space_read_2(iot, ioh, TX_TOTAL_OK); 1516 1517 /* 1518 * Clear the following to avoid stats overflow interrupts 1519 */ 1520 (void)bus_space_read_1(iot, ioh, TX_DEFERRALS); 1521 (void)bus_space_read_1(iot, ioh, TX_AFTER_1_COLLISION); 1522 (void)bus_space_read_1(iot, ioh, TX_NO_SQE); 1523 (void)bus_space_read_1(iot, ioh, TX_CD_LOST); 1524 GO_WINDOW(4); 1525 (void)bus_space_read_1(iot, ioh, ELINK_W4_BADSSD); 1526 GO_WINDOW(1); 1527 } 1528 1529 void 1530 ex_tick(void *arg) 1531 { 1532 struct ex_softc *sc = arg; 1533 int s; 1534 1535 if (!device_is_active(sc->sc_dev)) 1536 return; 1537 1538 s = splnet(); 1539 1540 if (sc->ex_conf & EX_CONF_MII) 1541 mii_tick(&sc->ex_mii); 1542 1543 if (!(bus_space_read_2((sc)->sc_iot, (sc)->sc_ioh, ELINK_STATUS) 1544 & COMMAND_IN_PROGRESS)) 1545 ex_getstats(sc); 1546 1547 splx(s); 1548 1549 callout_reset(&sc->ex_mii_callout, hz, ex_tick, sc); 1550 } 1551 1552 void 1553 ex_reset(struct ex_softc *sc) 1554 { 1555 uint16_t val = GLOBAL_RESET; 1556 1557 if (sc->ex_conf & EX_CONF_RESETHACK) 1558 val |= 0x10; 1559 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_COMMAND, val); 1560 /* 1561 * XXX apparently the command in progress bit can't be trusted 1562 * during a reset, so we just always wait this long. Fortunately 1563 * we normally only reset the chip during autoconfig. 1564 */ 1565 delay(100000); 1566 ex_waitcmd(sc); 1567 } 1568 1569 void 1570 ex_watchdog(struct ifnet *ifp) 1571 { 1572 struct ex_softc *sc = ifp->if_softc; 1573 1574 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 1575 if_statinc(ifp, if_oerrors); 1576 1577 ex_reset(sc); 1578 ex_init(ifp); 1579 } 1580 1581 void 1582 ex_stop(struct ifnet *ifp, int disable) 1583 { 1584 struct ex_softc *sc = ifp->if_softc; 1585 bus_space_tag_t iot = sc->sc_iot; 1586 bus_space_handle_t ioh = sc->sc_ioh; 1587 struct ex_txdesc *tx; 1588 struct ex_rxdesc *rx; 1589 int i; 1590 1591 bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_DISABLE); 1592 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_DISABLE); 1593 bus_space_write_2(iot, ioh, ELINK_COMMAND, STOP_TRANSCEIVER); 1594 1595 for (tx = sc->tx_head ; tx != NULL; tx = tx->tx_next) { 1596 if (tx->tx_mbhead == NULL) 1597 continue; 1598 m_freem(tx->tx_mbhead); 1599 tx->tx_mbhead = NULL; 1600 bus_dmamap_unload(sc->sc_dmat, tx->tx_dmamap); 1601 tx->tx_dpd->dpd_fsh = tx->tx_dpd->dpd_nextptr = 0; 1602 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap, 1603 ((char *)tx->tx_dpd - (char *)sc->sc_dpd), 1604 sizeof (struct ex_dpd), 1605 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1606 } 1607 sc->tx_tail = sc->tx_head = NULL; 1608 ex_init_txdescs(sc); 1609 1610 sc->rx_tail = sc->rx_head = 0; 1611 for (i = 0; i < EX_NUPD; i++) { 1612 rx = &sc->sc_rxdescs[i]; 1613 if (rx->rx_mbhead != NULL) { 1614 bus_dmamap_unload(sc->sc_dmat, rx->rx_dmamap); 1615 m_freem(rx->rx_mbhead); 1616 rx->rx_mbhead = NULL; 1617 } 1618 ex_add_rxbuf(sc, rx); 1619 } 1620 1621 bus_space_write_2(iot, ioh, ELINK_COMMAND, ACK_INTR | INTR_LATCH); 1622 1623 callout_stop(&sc->ex_mii_callout); 1624 if (sc->ex_conf & EX_CONF_MII) 1625 mii_down(&sc->ex_mii); 1626 1627 if (disable) 1628 ex_disable(sc); 1629 1630 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1631 sc->sc_if_flags = ifp->if_flags; 1632 ifp->if_timer = 0; 1633 } 1634 1635 static void 1636 ex_init_txdescs(struct ex_softc *sc) 1637 { 1638 int i; 1639 1640 for (i = 0; i < EX_NDPD; i++) { 1641 sc->sc_txdescs[i].tx_dmamap = sc->sc_tx_dmamaps[i]; 1642 sc->sc_txdescs[i].tx_dpd = &sc->sc_dpd[i]; 1643 if (i < EX_NDPD - 1) 1644 sc->sc_txdescs[i].tx_next = &sc->sc_txdescs[i + 1]; 1645 else 1646 sc->sc_txdescs[i].tx_next = NULL; 1647 } 1648 sc->tx_free = &sc->sc_txdescs[0]; 1649 sc->tx_ftail = &sc->sc_txdescs[EX_NDPD-1]; 1650 } 1651 1652 1653 int 1654 ex_activate(device_t self, enum devact act) 1655 { 1656 struct ex_softc *sc = device_private(self); 1657 1658 switch (act) { 1659 case DVACT_DEACTIVATE: 1660 if_deactivate(&sc->sc_ethercom.ec_if); 1661 return 0; 1662 default: 1663 return EOPNOTSUPP; 1664 } 1665 } 1666 1667 int 1668 ex_detach(struct ex_softc *sc) 1669 { 1670 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1671 struct ex_rxdesc *rxd; 1672 int i, s; 1673 1674 /* Succeed now if there's no work to do. */ 1675 if ((sc->ex_flags & EX_FLAGS_ATTACHED) == 0) 1676 return (0); 1677 1678 s = splnet(); 1679 /* Stop the interface. Callouts are stopped in it. */ 1680 ex_stop(ifp, 1); 1681 splx(s); 1682 1683 /* Destroy our callout. */ 1684 callout_destroy(&sc->ex_mii_callout); 1685 1686 if (sc->ex_conf & EX_CONF_MII) { 1687 /* Detach all PHYs */ 1688 mii_detach(&sc->ex_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1689 } 1690 1691 rnd_detach_source(&sc->rnd_source); 1692 ether_ifdetach(ifp); 1693 if_detach(ifp); 1694 1695 /* Delete all remaining media. */ 1696 ifmedia_fini(&sc->ex_mii.mii_media); 1697 1698 for (i = 0; i < EX_NUPD; i++) { 1699 rxd = &sc->sc_rxdescs[i]; 1700 if (rxd->rx_mbhead != NULL) { 1701 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 1702 m_freem(rxd->rx_mbhead); 1703 rxd->rx_mbhead = NULL; 1704 } 1705 } 1706 for (i = 0; i < EX_NUPD; i++) 1707 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rx_dmamaps[i]); 1708 for (i = 0; i < EX_NDPD; i++) 1709 bus_dmamap_destroy(sc->sc_dmat, sc->sc_tx_dmamaps[i]); 1710 bus_dmamap_unload(sc->sc_dmat, sc->sc_dpd_dmamap); 1711 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dpd_dmamap); 1712 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_dpd, 1713 EX_NDPD * sizeof (struct ex_dpd)); 1714 bus_dmamem_free(sc->sc_dmat, &sc->sc_dseg, sc->sc_drseg); 1715 bus_dmamap_unload(sc->sc_dmat, sc->sc_upd_dmamap); 1716 bus_dmamap_destroy(sc->sc_dmat, sc->sc_upd_dmamap); 1717 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_upd, 1718 EX_NUPD * sizeof (struct ex_upd)); 1719 bus_dmamem_free(sc->sc_dmat, &sc->sc_useg, sc->sc_urseg); 1720 1721 pmf_device_deregister(sc->sc_dev); 1722 1723 return (0); 1724 } 1725 1726 /* 1727 * Before reboots, reset card completely. 1728 */ 1729 static bool 1730 ex_shutdown(device_t self, int flags) 1731 { 1732 struct ex_softc *sc = device_private(self); 1733 1734 ex_stop(&sc->sc_ethercom.ec_if, 1); 1735 /* 1736 * Make sure the interface is powered up when we reboot, 1737 * otherwise firmware on some systems gets really confused. 1738 */ 1739 (void) ex_enable(sc); 1740 return true; 1741 } 1742 1743 /* 1744 * Read EEPROM data. 1745 * XXX what to do if EEPROM doesn't unbusy? 1746 */ 1747 uint16_t 1748 ex_read_eeprom(struct ex_softc *sc, int offset) 1749 { 1750 bus_space_tag_t iot = sc->sc_iot; 1751 bus_space_handle_t ioh = sc->sc_ioh; 1752 uint16_t data = 0, cmd = READ_EEPROM; 1753 int off; 1754 1755 off = sc->ex_conf & EX_CONF_EEPROM_OFF ? 0x30 : 0; 1756 cmd = sc->ex_conf & EX_CONF_EEPROM_8BIT ? READ_EEPROM8 : READ_EEPROM; 1757 1758 GO_WINDOW(0); 1759 if (ex_eeprom_busy(sc)) 1760 goto out; 1761 bus_space_write_2(iot, ioh, ELINK_W0_EEPROM_COMMAND, 1762 cmd | (off + (offset & 0x3f))); 1763 if (ex_eeprom_busy(sc)) 1764 goto out; 1765 data = bus_space_read_2(iot, ioh, ELINK_W0_EEPROM_DATA); 1766 out: 1767 return data; 1768 } 1769 1770 static int 1771 ex_eeprom_busy(struct ex_softc *sc) 1772 { 1773 bus_space_tag_t iot = sc->sc_iot; 1774 bus_space_handle_t ioh = sc->sc_ioh; 1775 int i = 100; 1776 1777 while (i--) { 1778 if (!(bus_space_read_2(iot, ioh, ELINK_W0_EEPROM_COMMAND) & 1779 EEPROM_BUSY)) 1780 return 0; 1781 delay(100); 1782 } 1783 aprint_error_dev(sc->sc_dev, "eeprom stays busy.\n"); 1784 return (1); 1785 } 1786 1787 /* 1788 * Create a new rx buffer and add it to the 'soft' rx list. 1789 */ 1790 static int 1791 ex_add_rxbuf(struct ex_softc *sc, struct ex_rxdesc *rxd) 1792 { 1793 struct mbuf *m, *oldm; 1794 bus_dmamap_t rxmap; 1795 int error, rval = 0; 1796 1797 oldm = rxd->rx_mbhead; 1798 rxmap = rxd->rx_dmamap; 1799 1800 MGETHDR(m, M_DONTWAIT, MT_DATA); 1801 if (m != NULL) { 1802 MCLGET(m, M_DONTWAIT); 1803 if ((m->m_flags & M_EXT) == 0) { 1804 m_freem(m); 1805 if (oldm == NULL) 1806 return 1; 1807 m = oldm; 1808 MRESETDATA(m); 1809 rval = 1; 1810 } 1811 } else { 1812 if (oldm == NULL) 1813 return 1; 1814 m = oldm; 1815 MRESETDATA(m); 1816 rval = 1; 1817 } 1818 1819 /* 1820 * Setup the DMA map for this receive buffer. 1821 */ 1822 if (m != oldm) { 1823 if (oldm != NULL) 1824 bus_dmamap_unload(sc->sc_dmat, rxmap); 1825 error = bus_dmamap_load(sc->sc_dmat, rxmap, 1826 m->m_ext.ext_buf, MCLBYTES, NULL, 1827 BUS_DMA_READ | BUS_DMA_NOWAIT); 1828 if (error) { 1829 aprint_error_dev(sc->sc_dev, "can't load rx buffer, error = %d\n", 1830 error); 1831 panic("ex_add_rxbuf"); /* XXX */ 1832 } 1833 } 1834 1835 /* 1836 * Align for data after 14 byte header. 1837 */ 1838 m->m_data += 2; 1839 1840 rxd->rx_mbhead = m; 1841 rxd->rx_upd->upd_pktstatus = htole32(MCLBYTES - 2); 1842 rxd->rx_upd->upd_frags[0].fr_addr = 1843 htole32(rxmap->dm_segs[0].ds_addr + 2); 1844 rxd->rx_upd->upd_nextptr = 0; 1845 1846 /* 1847 * Attach it to the end of the list. 1848 */ 1849 if (sc->rx_head != NULL) { 1850 sc->rx_tail->rx_next = rxd; 1851 sc->rx_tail->rx_upd->upd_nextptr = htole32(sc->sc_upddma + 1852 ((char *)rxd->rx_upd - (char *)sc->sc_upd)); 1853 bus_dmamap_sync(sc->sc_dmat, sc->sc_upd_dmamap, 1854 (char *)sc->rx_tail->rx_upd - (char *)sc->sc_upd, 1855 sizeof (struct ex_upd), 1856 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1857 } else { 1858 sc->rx_head = rxd; 1859 } 1860 sc->rx_tail = rxd; 1861 1862 bus_dmamap_sync(sc->sc_dmat, rxmap, 0, rxmap->dm_mapsize, 1863 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1864 bus_dmamap_sync(sc->sc_dmat, sc->sc_upd_dmamap, 1865 ((char *)rxd->rx_upd - (char *)sc->sc_upd), 1866 sizeof (struct ex_upd), BUS_DMASYNC_PREREAD |BUS_DMASYNC_PREWRITE); 1867 return (rval); 1868 } 1869 1870 uint32_t 1871 ex_mii_bitbang_read(device_t self) 1872 { 1873 struct ex_softc *sc = device_private(self); 1874 1875 /* We're already in Window 4. */ 1876 return (bus_space_read_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_PHYSMGMT)); 1877 } 1878 1879 void 1880 ex_mii_bitbang_write(device_t self, uint32_t val) 1881 { 1882 struct ex_softc *sc = device_private(self); 1883 1884 /* We're already in Window 4. */ 1885 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_PHYSMGMT, val); 1886 } 1887 1888 int 1889 ex_mii_readreg(device_t v, int phy, int reg, uint16_t *val) 1890 { 1891 struct ex_softc *sc = device_private(v); 1892 int rv; 1893 1894 if ((sc->ex_conf & EX_CONF_INTPHY) && phy != ELINK_INTPHY_ID) 1895 return -1; 1896 1897 GO_WINDOW(4); 1898 1899 rv = mii_bitbang_readreg(v, &ex_mii_bitbang_ops, phy, reg, val); 1900 1901 GO_WINDOW(1); 1902 1903 return rv; 1904 } 1905 1906 int 1907 ex_mii_writereg(device_t v, int phy, int reg, uint16_t val) 1908 { 1909 struct ex_softc *sc = device_private(v); 1910 int rv; 1911 1912 GO_WINDOW(4); 1913 1914 rv = mii_bitbang_writereg(v, &ex_mii_bitbang_ops, phy, reg, val); 1915 1916 GO_WINDOW(1); 1917 1918 return rv; 1919 } 1920 1921 void 1922 ex_mii_statchg(struct ifnet *ifp) 1923 { 1924 struct ex_softc *sc = ifp->if_softc; 1925 bus_space_tag_t iot = sc->sc_iot; 1926 bus_space_handle_t ioh = sc->sc_ioh; 1927 int mctl; 1928 1929 GO_WINDOW(3); 1930 mctl = bus_space_read_2(iot, ioh, ELINK_W3_MAC_CONTROL); 1931 if (sc->ex_mii.mii_media_active & IFM_FDX) 1932 mctl |= MAC_CONTROL_FDX; 1933 else 1934 mctl &= ~MAC_CONTROL_FDX; 1935 bus_space_write_2(iot, ioh, ELINK_W3_MAC_CONTROL, mctl); 1936 GO_WINDOW(1); /* back to operating window */ 1937 } 1938 1939 int 1940 ex_enable(struct ex_softc *sc) 1941 { 1942 if (sc->enabled == 0 && sc->enable != NULL) { 1943 if ((*sc->enable)(sc) != 0) { 1944 aprint_error_dev(sc->sc_dev, "device enable failed\n"); 1945 return (EIO); 1946 } 1947 sc->enabled = 1; 1948 } 1949 return (0); 1950 } 1951 1952 void 1953 ex_disable(struct ex_softc *sc) 1954 { 1955 if (sc->enabled == 1 && sc->disable != NULL) { 1956 (*sc->disable)(sc); 1957 sc->enabled = 0; 1958 } 1959 } 1960 1961
Indexes created Wed Oct 22 13:09:56 GMT 2025