elinkxl.c revision 1.18
1 /* $NetBSD: elinkxl.c,v 1.18 1999/11/17 08:03:30 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include "opt_inet.h" 40 #include "opt_ns.h" 41 #include "bpfilter.h" 42 #include "rnd.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/kernel.h> 47 #include <sys/mbuf.h> 48 #include <sys/socket.h> 49 #include <sys/ioctl.h> 50 #include <sys/errno.h> 51 #include <sys/syslog.h> 52 #include <sys/select.h> 53 #include <sys/device.h> 54 #if NRND > 0 55 #include <sys/rnd.h> 56 #endif 57 58 #include <net/if.h> 59 #include <net/if_dl.h> 60 #include <net/if_ether.h> 61 #include <net/if_media.h> 62 63 #ifdef INET 64 #include <netinet/in.h> 65 #include <netinet/in_systm.h> 66 #include <netinet/in_var.h> 67 #include <netinet/ip.h> 68 #include <netinet/if_inarp.h> 69 #endif 70 71 #ifdef NS 72 #include <netns/ns.h> 73 #include <netns/ns_if.h> 74 #endif 75 76 #if NBPFILTER > 0 77 #include <net/bpf.h> 78 #include <net/bpfdesc.h> 79 #endif 80 81 #include <machine/cpu.h> 82 #include <machine/bus.h> 83 #include <machine/intr.h> 84 85 #if BYTE_ORDER == BIG_ENDIAN 86 #include <machine/bswap.h> 87 #define htopci(x) bswap32(x) 88 #define pcitoh(x) bswap32(x) 89 #else 90 #define htopci(x) (x) 91 #define pcitoh(x) (x) 92 #endif 93 94 #include <vm/vm.h> 95 #include <vm/pmap.h> 96 97 #include <dev/mii/miivar.h> 98 #include <dev/mii/mii.h> 99 100 #include <dev/ic/elink3reg.h> 101 /* #include <dev/ic/elink3var.h> */ 102 #include <dev/ic/elinkxlreg.h> 103 #include <dev/ic/elinkxlvar.h> 104 105 #ifdef DEBUG 106 int exdebug = 0; 107 #endif 108 109 /* ifmedia callbacks */ 110 int ex_media_chg __P((struct ifnet *ifp)); 111 void ex_media_stat __P((struct ifnet *ifp, struct ifmediareq *req)); 112 113 void ex_probe_media __P((struct ex_softc *)); 114 void ex_set_filter __P((struct ex_softc *)); 115 void ex_set_media __P((struct ex_softc *)); 116 struct mbuf *ex_get __P((struct ex_softc *, int)); 117 u_int16_t ex_read_eeprom __P((struct ex_softc *, int)); 118 void ex_init __P((struct ex_softc *)); 119 void ex_read __P((struct ex_softc *)); 120 void ex_reset __P((struct ex_softc *)); 121 void ex_set_mc __P((struct ex_softc *)); 122 void ex_getstats __P((struct ex_softc *)); 123 void ex_printstats __P((struct ex_softc *)); 124 void ex_tick __P((void *)); 125 126 static int ex_eeprom_busy __P((struct ex_softc *)); 127 static int ex_add_rxbuf __P((struct ex_softc *, struct ex_rxdesc *)); 128 static void ex_init_txdescs __P((struct ex_softc *)); 129 130 static void ex_shutdown __P((void *)); 131 static void ex_start __P((struct ifnet *)); 132 static void ex_txstat __P((struct ex_softc *)); 133 static u_int16_t ex_mchash __P((u_char *)); 134 static void ex_mii_sendbits __P((struct ex_softc *, u_int, int)); 135 136 void ex_mii_setbit __P((void *, u_int16_t)); 137 void ex_mii_clrbit __P((void *, u_int16_t)); 138 u_int16_t ex_mii_readbit __P((void *, u_int16_t)); 139 void ex_mii_sync __P((struct ex_softc *)); 140 int ex_mii_readreg __P((struct device *, int, int)); 141 void ex_mii_writereg __P((struct device *, int, int, int)); 142 void ex_mii_statchg __P((struct device *)); 143 144 void ex_probemedia __P((struct ex_softc *)); 145 146 /* 147 * Structure to map media-present bits in boards to ifmedia codes and 148 * printable media names. Used for table-driven ifmedia initialization. 149 */ 150 struct ex_media { 151 int exm_mpbit; /* media present bit */ 152 const char *exm_name; /* name of medium */ 153 int exm_ifmedia; /* ifmedia word for medium */ 154 int exm_epmedia; /* ELINKMEDIA_* constant */ 155 }; 156 157 /* 158 * Media table for 3c90x chips. Note that chips with MII have no 159 * `native' media. 160 */ 161 struct ex_media ex_native_media[] = { 162 { ELINK_PCI_10BASE_T, "10baseT", IFM_ETHER|IFM_10_T, 163 ELINKMEDIA_10BASE_T }, 164 { ELINK_PCI_10BASE_T, "10baseT-FDX", IFM_ETHER|IFM_10_T|IFM_FDX, 165 ELINKMEDIA_10BASE_T }, 166 { ELINK_PCI_AUI, "10base5", IFM_ETHER|IFM_10_5, 167 ELINKMEDIA_AUI }, 168 { ELINK_PCI_BNC, "10base2", IFM_ETHER|IFM_10_2, 169 ELINKMEDIA_10BASE_2 }, 170 { ELINK_PCI_100BASE_TX, "100baseTX", IFM_ETHER|IFM_100_TX, 171 ELINKMEDIA_100BASE_TX }, 172 { ELINK_PCI_100BASE_TX, "100baseTX-FDX",IFM_ETHER|IFM_100_TX|IFM_FDX, 173 ELINKMEDIA_100BASE_TX }, 174 { ELINK_PCI_100BASE_FX, "100baseFX", IFM_ETHER|IFM_100_FX, 175 ELINKMEDIA_100BASE_FX }, 176 { ELINK_PCI_100BASE_MII,"manual", IFM_ETHER|IFM_MANUAL, 177 ELINKMEDIA_MII }, 178 { ELINK_PCI_100BASE_T4, "100baseT4", IFM_ETHER|IFM_100_T4, 179 ELINKMEDIA_100BASE_T4 }, 180 { 0, NULL, 0, 181 0 }, 182 }; 183 184 /* 185 * Back-end attach and configure. 186 */ 187 void 188 ex_config(sc) 189 struct ex_softc *sc; 190 { 191 struct ifnet *ifp; 192 u_int16_t val; 193 u_int8_t macaddr[ETHER_ADDR_LEN] = {0}; 194 bus_space_tag_t iot = sc->sc_iot; 195 bus_space_handle_t ioh = sc->sc_ioh; 196 bus_dma_segment_t useg, dseg; 197 int urseg, drseg, i, error, attach_stage; 198 199 ex_reset(sc); 200 201 val = ex_read_eeprom(sc, EEPROM_OEM_ADDR0); 202 macaddr[0] = val >> 8; 203 macaddr[1] = val & 0xff; 204 val = ex_read_eeprom(sc, EEPROM_OEM_ADDR1); 205 macaddr[2] = val >> 8; 206 macaddr[3] = val & 0xff; 207 val = ex_read_eeprom(sc, EEPROM_OEM_ADDR2); 208 macaddr[4] = val >> 8; 209 macaddr[5] = val & 0xff; 210 211 printf("%s: MAC address %s\n", sc->sc_dev.dv_xname, 212 ether_sprintf(macaddr)); 213 214 if (sc->intr_ack) { /* 3C575BTX specific */ 215 GO_WINDOW(2); 216 bus_space_write_2(sc->sc_iot, ioh, 12, 0x10|bus_space_read_2(sc->sc_iot, ioh, 12)); 217 } 218 219 attach_stage = 0; 220 221 /* 222 * Allocate the upload descriptors, and create and load the DMA 223 * map for them. 224 */ 225 if ((error = bus_dmamem_alloc(sc->sc_dmat, 226 EX_NUPD * sizeof (struct ex_upd), NBPG, 0, &useg, 1, &urseg, 227 BUS_DMA_NOWAIT)) != 0) { 228 printf("%s: can't allocate upload descriptors, error = %d\n", 229 sc->sc_dev.dv_xname, error); 230 goto fail; 231 } 232 233 attach_stage = 1; 234 235 if ((error = bus_dmamem_map(sc->sc_dmat, &useg, urseg, 236 EX_NUPD * sizeof (struct ex_upd), (caddr_t *)&sc->sc_upd, 237 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 238 printf("%s: can't map upload descriptors, error = %d\n", 239 sc->sc_dev.dv_xname, error); 240 goto fail; 241 } 242 243 attach_stage = 2; 244 245 if ((error = bus_dmamap_create(sc->sc_dmat, 246 EX_NUPD * sizeof (struct ex_upd), 1, 247 EX_NUPD * sizeof (struct ex_upd), 0, BUS_DMA_NOWAIT, 248 &sc->sc_upd_dmamap)) != 0) { 249 printf("%s: can't create upload desc. DMA map, error = %d\n", 250 sc->sc_dev.dv_xname, error); 251 goto fail; 252 } 253 254 attach_stage = 3; 255 256 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_upd_dmamap, 257 sc->sc_upd, EX_NUPD * sizeof (struct ex_upd), NULL, 258 BUS_DMA_NOWAIT)) != 0) { 259 printf("%s: can't load upload desc. DMA map, error = %d\n", 260 sc->sc_dev.dv_xname, error); 261 goto fail; 262 } 263 264 attach_stage = 4; 265 266 /* 267 * Allocate the download descriptors, and create and load the DMA 268 * map for them. 269 */ 270 if ((error = bus_dmamem_alloc(sc->sc_dmat, 271 EX_NDPD * sizeof (struct ex_dpd), NBPG, 0, &dseg, 1, &drseg, 272 BUS_DMA_NOWAIT)) != 0) { 273 printf("%s: can't allocate download descriptors, error = %d\n", 274 sc->sc_dev.dv_xname, error); 275 goto fail; 276 } 277 278 attach_stage = 5; 279 280 if ((error = bus_dmamem_map(sc->sc_dmat, &dseg, drseg, 281 EX_NDPD * sizeof (struct ex_dpd), (caddr_t *)&sc->sc_dpd, 282 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 283 printf("%s: can't map download descriptors, error = %d\n", 284 sc->sc_dev.dv_xname, error); 285 goto fail; 286 } 287 bzero(sc->sc_dpd, EX_NDPD * sizeof (struct ex_dpd)); 288 289 attach_stage = 6; 290 291 if ((error = bus_dmamap_create(sc->sc_dmat, 292 EX_NDPD * sizeof (struct ex_dpd), 1, 293 EX_NDPD * sizeof (struct ex_dpd), 0, BUS_DMA_NOWAIT, 294 &sc->sc_dpd_dmamap)) != 0) { 295 printf("%s: can't create download desc. DMA map, error = %d\n", 296 sc->sc_dev.dv_xname, error); 297 goto fail; 298 } 299 300 attach_stage = 7; 301 302 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dpd_dmamap, 303 sc->sc_dpd, EX_NDPD * sizeof (struct ex_dpd), NULL, 304 BUS_DMA_NOWAIT)) != 0) { 305 printf("%s: can't load download desc. DMA map, error = %d\n", 306 sc->sc_dev.dv_xname, error); 307 goto fail; 308 } 309 310 attach_stage = 8; 311 312 313 /* 314 * Create the transmit buffer DMA maps. 315 */ 316 for (i = 0; i < EX_NDPD; i++) { 317 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 318 EX_NTFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 319 &sc->sc_tx_dmamaps[i])) != 0) { 320 printf("%s: can't create tx DMA map %d, error = %d\n", 321 sc->sc_dev.dv_xname, i, error); 322 goto fail; 323 } 324 } 325 326 attach_stage = 9; 327 328 /* 329 * Create the receive buffer DMA maps. 330 */ 331 for (i = 0; i < EX_NUPD; i++) { 332 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 333 EX_NRFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 334 &sc->sc_rx_dmamaps[i])) != 0) { 335 printf("%s: can't create rx DMA map %d, error = %d\n", 336 sc->sc_dev.dv_xname, i, error); 337 goto fail; 338 } 339 } 340 341 attach_stage = 10; 342 343 /* 344 * Create ring of upload descriptors, only once. The DMA engine 345 * will loop over this when receiving packets, stalling if it 346 * hits an UPD with a finished receive. 347 */ 348 for (i = 0; i < EX_NUPD; i++) { 349 sc->sc_rxdescs[i].rx_dmamap = sc->sc_rx_dmamaps[i]; 350 sc->sc_rxdescs[i].rx_upd = &sc->sc_upd[i]; 351 sc->sc_upd[i].upd_frags[0].fr_len = 352 htopci((MCLBYTES - 2) | EX_FR_LAST); 353 if (ex_add_rxbuf(sc, &sc->sc_rxdescs[i]) != 0) { 354 printf("%s: can't allocate or map rx buffers\n", 355 sc->sc_dev.dv_xname); 356 goto fail; 357 } 358 } 359 360 bus_dmamap_sync(sc->sc_dmat, sc->sc_upd_dmamap, 0, 361 EX_NUPD * sizeof (struct ex_upd), 362 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 363 364 ex_init_txdescs(sc); 365 366 attach_stage = 11; 367 368 369 GO_WINDOW(3); 370 val = bus_space_read_2(iot, ioh, ELINK_W3_RESET_OPTIONS); 371 if (val & ELINK_MEDIACAP_MII) 372 sc->ex_conf |= EX_CONF_MII; 373 374 ifp = &sc->sc_ethercom.ec_if; 375 376 /* 377 * Initialize our media structures and MII info. We'll 378 * probe the MII if we discover that we have one. 379 */ 380 sc->ex_mii.mii_ifp = ifp; 381 sc->ex_mii.mii_readreg = ex_mii_readreg; 382 sc->ex_mii.mii_writereg = ex_mii_writereg; 383 sc->ex_mii.mii_statchg = ex_mii_statchg; 384 ifmedia_init(&sc->ex_mii.mii_media, 0, ex_media_chg, 385 ex_media_stat); 386 387 if (sc->ex_conf & EX_CONF_MII) { 388 /* 389 * Find PHY, extract media information from it. 390 * First, select the right transceiver. 391 */ 392 u_int32_t icfg; 393 394 GO_WINDOW(3); 395 icfg = bus_space_read_4(iot, ioh, ELINK_W3_INTERNAL_CONFIG); 396 icfg &= ~(CONFIG_XCVR_SEL << 16); 397 if (val & (ELINK_MEDIACAP_MII | ELINK_MEDIACAP_100BASET4)) 398 icfg |= ELINKMEDIA_MII << (CONFIG_XCVR_SEL_SHIFT + 16); 399 if (val & ELINK_MEDIACAP_100BASETX) 400 icfg |= ELINKMEDIA_AUTO << (CONFIG_XCVR_SEL_SHIFT + 16); 401 if (val & ELINK_MEDIACAP_100BASEFX) 402 icfg |= ELINKMEDIA_100BASE_FX 403 << (CONFIG_XCVR_SEL_SHIFT + 16); 404 bus_space_write_4(iot, ioh, ELINK_W3_INTERNAL_CONFIG, icfg); 405 406 mii_phy_probe(&sc->sc_dev, &sc->ex_mii, 0xffffffff, 407 MII_PHY_ANY, MII_OFFSET_ANY); 408 if (LIST_FIRST(&sc->ex_mii.mii_phys) == NULL) { 409 ifmedia_add(&sc->ex_mii.mii_media, IFM_ETHER|IFM_NONE, 410 0, NULL); 411 ifmedia_set(&sc->ex_mii.mii_media, IFM_ETHER|IFM_NONE); 412 } else { 413 ifmedia_set(&sc->ex_mii.mii_media, IFM_ETHER|IFM_AUTO); 414 } 415 } else 416 ex_probemedia(sc); 417 418 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 419 ifp->if_softc = sc; 420 ifp->if_start = ex_start; 421 ifp->if_ioctl = ex_ioctl; 422 ifp->if_watchdog = ex_watchdog; 423 ifp->if_flags = 424 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 425 426 if_attach(ifp); 427 ether_ifattach(ifp, macaddr); 428 429 GO_WINDOW(1); 430 431 sc->tx_start_thresh = 20; 432 sc->tx_succ_ok = 0; 433 434 /* TODO: set queues to 0 */ 435 436 #if NBPFILTER > 0 437 bpfattach(&sc->sc_ethercom.ec_if.if_bpf, ifp, DLT_EN10MB, 438 sizeof(struct ether_header)); 439 #endif 440 441 #if NRND > 0 442 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 443 RND_TYPE_NET, 0); 444 #endif 445 446 /* Establish callback to reset card when we reboot. */ 447 shutdownhook_establish(ex_shutdown, sc); 448 return; 449 450 fail: 451 /* 452 * Free any resources we've allocated during the failed attach 453 * attempt. Do this in reverse order and fall though. 454 */ 455 switch (attach_stage) { 456 case 11: 457 { 458 struct ex_rxdesc *rxd; 459 460 for (i = 0; i < EX_NUPD; i++) { 461 rxd = &sc->sc_rxdescs[i]; 462 if (rxd->rx_mbhead != NULL) { 463 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 464 m_freem(rxd->rx_mbhead); 465 } 466 } 467 } 468 /* FALLTHROUGH */ 469 470 case 10: 471 for (i = 0; i < EX_NUPD; i++) 472 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rx_dmamaps[i]); 473 /* FALLTHROUGH */ 474 475 case 9: 476 for (i = 0; i < EX_NDPD; i++) 477 bus_dmamap_destroy(sc->sc_dmat, sc->sc_tx_dmamaps[i]); 478 /* FALLTHROUGH */ 479 case 8: 480 bus_dmamap_unload(sc->sc_dmat, sc->sc_dpd_dmamap); 481 /* FALLTHROUGH */ 482 483 case 7: 484 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dpd_dmamap); 485 /* FALLTHROUGH */ 486 487 case 6: 488 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_dpd, 489 EX_NDPD * sizeof (struct ex_dpd)); 490 /* FALLTHROUGH */ 491 492 case 5: 493 bus_dmamem_free(sc->sc_dmat, &dseg, drseg); 494 break; 495 496 case 4: 497 bus_dmamap_unload(sc->sc_dmat, sc->sc_upd_dmamap); 498 /* FALLTHROUGH */ 499 500 case 3: 501 bus_dmamap_destroy(sc->sc_dmat, sc->sc_upd_dmamap); 502 /* FALLTHROUGH */ 503 504 case 2: 505 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_upd, 506 EX_NUPD * sizeof (struct ex_upd)); 507 /* FALLTHROUGH */ 508 509 case 1: 510 bus_dmamem_free(sc->sc_dmat, &useg, urseg); 511 break; 512 } 513 514 } 515 516 /* 517 * Find the media present on non-MII chips. 518 */ 519 void 520 ex_probemedia(sc) 521 struct ex_softc *sc; 522 { 523 bus_space_tag_t iot = sc->sc_iot; 524 bus_space_handle_t ioh = sc->sc_ioh; 525 struct ifmedia *ifm = &sc->ex_mii.mii_media; 526 struct ex_media *exm; 527 u_int16_t config1, reset_options, default_media; 528 int defmedia = 0; 529 const char *sep = "", *defmedianame = NULL; 530 531 GO_WINDOW(3); 532 config1 = bus_space_read_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG + 2); 533 reset_options = bus_space_read_1(iot, ioh, ELINK_W3_RESET_OPTIONS); 534 GO_WINDOW(0); 535 536 default_media = (config1 & CONFIG_MEDIAMASK) >> CONFIG_MEDIAMASK_SHIFT; 537 538 printf("%s: ", sc->sc_dev.dv_xname); 539 540 /* Sanity check that there are any media! */ 541 if ((reset_options & ELINK_PCI_MEDIAMASK) == 0) { 542 printf("no media present!\n"); 543 ifmedia_add(ifm, IFM_ETHER|IFM_NONE, 0, NULL); 544 ifmedia_set(ifm, IFM_ETHER|IFM_NONE); 545 return; 546 } 547 548 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 549 550 for (exm = ex_native_media; exm->exm_name != NULL; exm++) { 551 if (reset_options & exm->exm_mpbit) { 552 /* 553 * Default media is a little complicated. We 554 * support full-duplex which uses the same 555 * reset options bit. 556 * 557 * XXX Check EEPROM for default to FDX? 558 */ 559 if (exm->exm_epmedia == default_media) { 560 if ((exm->exm_ifmedia & IFM_FDX) == 0) { 561 defmedia = exm->exm_ifmedia; 562 defmedianame = exm->exm_name; 563 } 564 } else if (defmedia == 0) { 565 defmedia = exm->exm_ifmedia; 566 defmedianame = exm->exm_name; 567 } 568 ifmedia_add(ifm, exm->exm_ifmedia, exm->exm_epmedia, 569 NULL); 570 PRINT(exm->exm_name); 571 } 572 } 573 574 #undef PRINT 575 576 #ifdef DIAGNOSTIC 577 if (defmedia == 0) 578 panic("ex_probemedia: impossible"); 579 #endif 580 581 printf(", default %s\n", defmedianame); 582 ifmedia_set(ifm, defmedia); 583 } 584 585 /* 586 * Bring device up. 587 */ 588 void 589 ex_init(sc) 590 struct ex_softc *sc; 591 { 592 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 593 bus_space_tag_t iot = sc->sc_iot; 594 bus_space_handle_t ioh = sc->sc_ioh; 595 int s, i; 596 597 s = splnet(); 598 599 ex_waitcmd(sc); 600 ex_stop(sc); 601 602 /* 603 * Set the station address and clear the station mask. The latter 604 * is needed for 90x cards, 0 is the default for 90xB cards. 605 */ 606 GO_WINDOW(2); 607 for (i = 0; i < ETHER_ADDR_LEN; i++) { 608 bus_space_write_1(iot, ioh, ELINK_W2_ADDR_0 + i, 609 LLADDR(ifp->if_sadl)[i]); 610 bus_space_write_1(iot, ioh, ELINK_W2_RECVMASK_0 + i, 0); 611 } 612 613 GO_WINDOW(3); 614 615 bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_RESET); 616 ex_waitcmd(sc); 617 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_RESET); 618 ex_waitcmd(sc); 619 620 /* 621 * Disable reclaim threshold for 90xB, set free threshold to 622 * 6 * 256 = 1536 for 90x. 623 */ 624 if (sc->ex_conf & EX_CONF_90XB) 625 bus_space_write_2(iot, ioh, ELINK_COMMAND, 626 ELINK_TXRECLTHRESH | 255); 627 else 628 bus_space_write_1(iot, ioh, ELINK_TXFREETHRESH, 6); 629 630 bus_space_write_2(iot, ioh, ELINK_COMMAND, 631 SET_RX_EARLY_THRESH | ELINK_THRESH_DISABLE); 632 633 bus_space_write_4(iot, ioh, ELINK_DMACTRL, 634 bus_space_read_4(iot, ioh, ELINK_DMACTRL) | ELINK_DMAC_UPRXEAREN); 635 636 bus_space_write_2(iot, ioh, ELINK_COMMAND, SET_RD_0_MASK | S_MASK); 637 bus_space_write_2(iot, ioh, ELINK_COMMAND, SET_INTR_MASK | S_MASK); 638 639 bus_space_write_2(iot, ioh, ELINK_COMMAND, ACK_INTR | 0xff); 640 if (sc->intr_ack) 641 (* sc->intr_ack)(sc); 642 ex_set_media(sc); 643 ex_set_mc(sc); 644 645 646 bus_space_write_2(iot, ioh, ELINK_COMMAND, STATS_ENABLE); 647 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_ENABLE); 648 bus_space_write_4(iot, ioh, ELINK_UPLISTPTR, sc->sc_upddma); 649 bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_ENABLE); 650 bus_space_write_2(iot, ioh, ELINK_COMMAND, ELINK_UPUNSTALL); 651 652 ifp->if_flags |= IFF_RUNNING; 653 ifp->if_flags &= ~IFF_OACTIVE; 654 ex_start(ifp); 655 656 GO_WINDOW(1); 657 658 splx(s); 659 660 timeout(ex_tick, sc, hz); 661 } 662 663 /* 664 * Multicast hash filter according to the 3Com spec. 665 */ 666 static u_int16_t 667 ex_mchash(addr) 668 u_char *addr; 669 { 670 u_int32_t crc, carry; 671 int i, j; 672 u_char c; 673 674 /* Compute CRC for the address value. */ 675 crc = 0xffffffff; /* initial value */ 676 677 for (i = 0; i < 6; i++) { 678 c = addr[i]; 679 for (j = 0; j < 8; j++) { 680 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 681 crc <<= 1; 682 c >>= 1; 683 if (carry) 684 crc = (crc ^ 0x04c11db6) | carry; 685 } 686 } 687 688 /* Return the filter bit position. */ 689 return(crc & 0x000000ff); 690 } 691 692 693 /* 694 * Set multicast receive filter. Also take care of promiscuous mode 695 * here (XXX). 696 */ 697 void 698 ex_set_mc(sc) 699 register struct ex_softc *sc; 700 { 701 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 702 struct ethercom *ec = &sc->sc_ethercom; 703 struct ether_multi *enm; 704 struct ether_multistep estep; 705 int i; 706 u_int16_t mask = FIL_INDIVIDUAL | FIL_BRDCST; 707 708 if (ifp->if_flags & IFF_PROMISC) 709 mask |= FIL_PROMISC; 710 711 if (!(ifp->if_flags & IFF_MULTICAST)) 712 goto out; 713 714 if (!(sc->ex_conf & EX_CONF_90XB) || ifp->if_flags & IFF_ALLMULTI) { 715 mask |= (ifp->if_flags & IFF_MULTICAST) ? FIL_MULTICAST : 0; 716 } else { 717 ETHER_FIRST_MULTI(estep, ec, enm); 718 while (enm != NULL) { 719 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 720 ETHER_ADDR_LEN) != 0) 721 goto out; 722 i = ex_mchash(enm->enm_addrlo); 723 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 724 ELINK_COMMAND, ELINK_SETHASHFILBIT | i); 725 ETHER_NEXT_MULTI(estep, enm); 726 } 727 mask |= FIL_MULTIHASH; 728 } 729 out: 730 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_COMMAND, 731 SET_RX_FILTER | mask); 732 } 733 734 735 static void 736 ex_txstat(sc) 737 struct ex_softc *sc; 738 { 739 bus_space_tag_t iot = sc->sc_iot; 740 bus_space_handle_t ioh = sc->sc_ioh; 741 int i; 742 743 /* 744 * We need to read+write TX_STATUS until we get a 0 status 745 * in order to turn off the interrupt flag. 746 */ 747 while ((i = bus_space_read_1(iot, ioh, ELINK_TXSTATUS)) & TXS_COMPLETE) { 748 bus_space_write_1(iot, ioh, ELINK_TXSTATUS, 0x0); 749 750 if (i & TXS_JABBER) { 751 ++sc->sc_ethercom.ec_if.if_oerrors; 752 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 753 printf("%s: jabber (%x)\n", 754 sc->sc_dev.dv_xname, i); 755 ex_init(sc); 756 /* TODO: be more subtle here */ 757 } else if (i & TXS_UNDERRUN) { 758 ++sc->sc_ethercom.ec_if.if_oerrors; 759 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 760 printf("%s: fifo underrun (%x) @%d\n", 761 sc->sc_dev.dv_xname, i, 762 sc->tx_start_thresh); 763 if (sc->tx_succ_ok < 100) 764 sc->tx_start_thresh = min(ETHER_MAX_LEN, 765 sc->tx_start_thresh + 20); 766 sc->tx_succ_ok = 0; 767 ex_init(sc); 768 /* TODO: be more subtle here */ 769 } else if (i & TXS_MAX_COLLISION) { 770 ++sc->sc_ethercom.ec_if.if_collisions; 771 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_ENABLE); 772 sc->sc_ethercom.ec_if.if_flags &= ~IFF_OACTIVE; 773 } else 774 sc->tx_succ_ok = (sc->tx_succ_ok+1) & 127; 775 } 776 } 777 778 int 779 ex_media_chg(ifp) 780 struct ifnet *ifp; 781 { 782 struct ex_softc *sc = ifp->if_softc; 783 784 if (ifp->if_flags & IFF_UP) 785 ex_init(sc); 786 return 0; 787 } 788 789 void 790 ex_set_media(sc) 791 struct ex_softc *sc; 792 { 793 bus_space_tag_t iot = sc->sc_iot; 794 bus_space_handle_t ioh = sc->sc_ioh; 795 int config0, config1; 796 797 if (((sc->ex_conf & EX_CONF_MII) && 798 (sc->ex_mii.mii_media_active & IFM_FDX)) 799 || (!(sc->ex_conf & EX_CONF_MII) && 800 (sc->ex_mii.mii_media.ifm_media & IFM_FDX))) { 801 bus_space_write_2(iot, ioh, ELINK_W3_MAC_CONTROL, 802 MAC_CONTROL_FDX); 803 } else { 804 bus_space_write_2(iot, ioh, ELINK_W3_MAC_CONTROL, 0); 805 } 806 807 /* 808 * If the device has MII, select it, and then tell the 809 * PHY which media to use. 810 */ 811 if (sc->ex_conf & EX_CONF_MII) { 812 GO_WINDOW(3); 813 814 config0 = (u_int)bus_space_read_2(iot, ioh, 815 ELINK_W3_INTERNAL_CONFIG); 816 config1 = (u_int)bus_space_read_2(iot, ioh, 817 ELINK_W3_INTERNAL_CONFIG + 2); 818 819 config1 = config1 & ~CONFIG_MEDIAMASK; 820 config1 |= (ELINKMEDIA_MII << CONFIG_MEDIAMASK_SHIFT); 821 822 bus_space_write_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG, config0); 823 bus_space_write_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG + 2, config1); 824 mii_mediachg(&sc->ex_mii); 825 return; 826 } 827 828 GO_WINDOW(4); 829 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 0); 830 bus_space_write_2(iot, ioh, ELINK_COMMAND, STOP_TRANSCEIVER); 831 delay(800); 832 833 /* 834 * Now turn on the selected media/transceiver. 835 */ 836 switch (IFM_SUBTYPE(sc->ex_mii.mii_media.ifm_cur->ifm_media)) { 837 case IFM_10_T: 838 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 839 JABBER_GUARD_ENABLE|LINKBEAT_ENABLE); 840 break; 841 842 case IFM_10_2: 843 bus_space_write_2(iot, ioh, ELINK_COMMAND, START_TRANSCEIVER); 844 DELAY(800); 845 break; 846 847 case IFM_100_TX: 848 case IFM_100_FX: 849 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 850 LINKBEAT_ENABLE); 851 DELAY(800); 852 break; 853 854 case IFM_10_5: 855 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 856 SQE_ENABLE); 857 DELAY(800); 858 break; 859 860 case IFM_MANUAL: 861 break; 862 863 case IFM_NONE: 864 return; 865 866 default: 867 panic("ex_set_media: impossible"); 868 } 869 870 GO_WINDOW(3); 871 config0 = (u_int)bus_space_read_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG); 872 config1 = (u_int)bus_space_read_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG + 2); 873 874 config1 = config1 & ~CONFIG_MEDIAMASK; 875 config1 |= (sc->ex_mii.mii_media.ifm_cur->ifm_data << 876 CONFIG_MEDIAMASK_SHIFT); 877 878 bus_space_write_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG, config0); 879 bus_space_write_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG + 2, config1); 880 } 881 882 /* 883 * Get currently-selected media from card. 884 * (if_media callback, may be called before interface is brought up). 885 */ 886 void 887 ex_media_stat(ifp, req) 888 struct ifnet *ifp; 889 struct ifmediareq *req; 890 { 891 struct ex_softc *sc = ifp->if_softc; 892 893 if (sc->ex_conf & EX_CONF_MII) { 894 mii_pollstat(&sc->ex_mii); 895 req->ifm_status = sc->ex_mii.mii_media_status; 896 req->ifm_active = sc->ex_mii.mii_media_active; 897 } else { 898 GO_WINDOW(4); 899 req->ifm_status = IFM_AVALID; 900 req->ifm_active = sc->ex_mii.mii_media.ifm_cur->ifm_media; 901 if (bus_space_read_2(sc->sc_iot, sc->sc_ioh, 902 ELINK_W4_MEDIA_TYPE) & LINKBEAT_DETECT) 903 req->ifm_status |= IFM_ACTIVE; 904 GO_WINDOW(1); 905 } 906 } 907 908 909 910 /* 911 * Start outputting on the interface. 912 */ 913 static void 914 ex_start(ifp) 915 struct ifnet *ifp; 916 { 917 struct ex_softc *sc = ifp->if_softc; 918 bus_space_tag_t iot = sc->sc_iot; 919 bus_space_handle_t ioh = sc->sc_ioh; 920 volatile struct ex_fraghdr *fr = NULL; 921 volatile struct ex_dpd *dpd = NULL, *prevdpd = NULL; 922 struct ex_txdesc *txp; 923 bus_dmamap_t dmamap; 924 int offset, totlen; 925 926 if (sc->tx_head || sc->tx_free == NULL) 927 return; 928 929 txp = NULL; 930 931 /* 932 * We're finished if there is nothing more to add to the list or if 933 * we're all filled up with buffers to transmit. 934 */ 935 while (ifp->if_snd.ifq_head != NULL && sc->tx_free != NULL) { 936 struct mbuf *mb_head; 937 int segment, error; 938 939 /* 940 * Grab a packet to transmit. 941 */ 942 IF_DEQUEUE(&ifp->if_snd, mb_head); 943 944 /* 945 * Get pointer to next available tx desc. 946 */ 947 txp = sc->tx_free; 948 sc->tx_free = txp->tx_next; 949 txp->tx_next = NULL; 950 dmamap = txp->tx_dmamap; 951 952 /* 953 * Go through each of the mbufs in the chain and initialize 954 * the transmit buffer descriptors with the physical address 955 * and size of the mbuf. 956 */ 957 reload: 958 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 959 mb_head, BUS_DMA_NOWAIT); 960 switch (error) { 961 case 0: 962 /* Success. */ 963 break; 964 965 case EFBIG: 966 { 967 struct mbuf *mn; 968 969 /* 970 * We ran out of segments. We have to recopy this 971 * mbuf chain first. Bail out if we can't get the 972 * new buffers. 973 */ 974 printf("%s: too many segments, ", sc->sc_dev.dv_xname); 975 976 MGETHDR(mn, M_DONTWAIT, MT_DATA); 977 if (mn == NULL) { 978 m_freem(mb_head); 979 printf("aborting\n"); 980 goto out; 981 } 982 if (mb_head->m_pkthdr.len > MHLEN) { 983 MCLGET(mn, M_DONTWAIT); 984 if ((mn->m_flags & M_EXT) == 0) { 985 m_freem(mn); 986 m_freem(mb_head); 987 printf("aborting\n"); 988 goto out; 989 } 990 } 991 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 992 mtod(mn, caddr_t)); 993 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 994 m_freem(mb_head); 995 mb_head = mn; 996 printf("retrying\n"); 997 goto reload; 998 } 999 1000 default: 1001 /* 1002 * Some other problem; report it. 1003 */ 1004 printf("%s: can't load mbuf chain, error = %d\n", 1005 sc->sc_dev.dv_xname, error); 1006 m_freem(mb_head); 1007 goto out; 1008 } 1009 1010 fr = &txp->tx_dpd->dpd_frags[0]; 1011 totlen = 0; 1012 for (segment = 0; segment < dmamap->dm_nsegs; segment++, fr++) { 1013 fr->fr_addr = htopci(dmamap->dm_segs[segment].ds_addr); 1014 fr->fr_len = htopci(dmamap->dm_segs[segment].ds_len); 1015 totlen += dmamap->dm_segs[segment].ds_len; 1016 } 1017 fr--; 1018 fr->fr_len |= htopci(EX_FR_LAST); 1019 txp->tx_mbhead = mb_head; 1020 1021 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1022 BUS_DMASYNC_PREWRITE); 1023 1024 dpd = txp->tx_dpd; 1025 dpd->dpd_nextptr = 0; 1026 dpd->dpd_fsh = htopci(totlen); 1027 1028 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap, 1029 ((caddr_t)dpd - (caddr_t)sc->sc_dpd), 1030 sizeof (struct ex_dpd), 1031 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1032 1033 /* 1034 * No need to stall the download engine, we know it's 1035 * not busy right now. 1036 * 1037 * Fix up pointers in both the "soft" tx and the physical 1038 * tx list. 1039 */ 1040 if (sc->tx_head != NULL) { 1041 prevdpd = sc->tx_tail->tx_dpd; 1042 offset = ((caddr_t)prevdpd - (caddr_t)sc->sc_dpd); 1043 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap, 1044 offset, sizeof (struct ex_dpd), 1045 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1046 prevdpd->dpd_nextptr = htopci(DPD_DMADDR(sc, txp)); 1047 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap, 1048 offset, sizeof (struct ex_dpd), 1049 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1050 sc->tx_tail->tx_next = txp; 1051 sc->tx_tail = txp; 1052 } else { 1053 sc->tx_tail = sc->tx_head = txp; 1054 } 1055 1056 #if NBPFILTER > 0 1057 /* 1058 * Pass packet to bpf if there is a listener. 1059 */ 1060 if (ifp->if_bpf) 1061 bpf_mtap(ifp->if_bpf, mb_head); 1062 #endif 1063 } 1064 out: 1065 if (sc->tx_head) { 1066 sc->tx_tail->tx_dpd->dpd_fsh |= htopci(EX_DPD_DNIND); 1067 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap, 1068 ((caddr_t)sc->tx_tail->tx_dpd - (caddr_t)sc->sc_dpd), 1069 sizeof (struct ex_dpd), 1070 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1071 ifp->if_flags |= IFF_OACTIVE; 1072 bus_space_write_2(iot, ioh, ELINK_COMMAND, ELINK_DNUNSTALL); 1073 bus_space_write_4(iot, ioh, ELINK_DNLISTPTR, 1074 DPD_DMADDR(sc, sc->tx_head)); 1075 1076 /* trigger watchdog */ 1077 ifp->if_timer = 5; 1078 } 1079 } 1080 1081 1082 int 1083 ex_intr(arg) 1084 void *arg; 1085 { 1086 struct ex_softc *sc = arg; 1087 bus_space_tag_t iot = sc->sc_iot; 1088 bus_space_handle_t ioh = sc->sc_ioh; 1089 u_int16_t stat; 1090 int ret = 0; 1091 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1092 1093 if (sc->enabled == 0) { 1094 return ret; 1095 } 1096 for (;;) { 1097 stat = bus_space_read_2(iot, ioh, ELINK_STATUS); 1098 if (!(stat & S_MASK)) 1099 break; 1100 /* 1101 * Acknowledge interrupts. 1102 */ 1103 bus_space_write_2(iot, ioh, ELINK_COMMAND, ACK_INTR | 1104 (stat & S_MASK)); 1105 if (sc->intr_ack) 1106 (*sc->intr_ack)(sc); 1107 ret = 1; 1108 if (stat & S_HOST_ERROR) { 1109 printf("%s: adapter failure (%x)\n", 1110 sc->sc_dev.dv_xname, stat); 1111 bus_space_write_2(iot, ioh, ELINK_COMMAND, 1112 C_INTR_LATCH); 1113 ex_reset(sc); 1114 ex_init(sc); 1115 return 1; 1116 } 1117 if (stat & S_TX_COMPLETE) { 1118 ex_txstat(sc); 1119 } 1120 if (stat & S_UPD_STATS) { 1121 ex_getstats(sc); 1122 } 1123 if (stat & S_DN_COMPLETE) { 1124 struct ex_txdesc *txp, *ptxp = NULL; 1125 bus_dmamap_t txmap; 1126 1127 /* reset watchdog timer, was set in ex_start() */ 1128 ifp->if_timer = 0; 1129 1130 for (txp = sc->tx_head; txp != NULL; 1131 txp = txp->tx_next) { 1132 bus_dmamap_sync(sc->sc_dmat, 1133 sc->sc_dpd_dmamap, 1134 (caddr_t)txp->tx_dpd - (caddr_t)sc->sc_dpd, 1135 sizeof (struct ex_dpd), 1136 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1137 if (txp->tx_mbhead != NULL) { 1138 txmap = txp->tx_dmamap; 1139 bus_dmamap_sync(sc->sc_dmat, txmap, 1140 0, txmap->dm_mapsize, 1141 BUS_DMASYNC_POSTWRITE); 1142 bus_dmamap_unload(sc->sc_dmat, txmap); 1143 m_freem(txp->tx_mbhead); 1144 txp->tx_mbhead = NULL; 1145 } 1146 ptxp = txp; 1147 } 1148 1149 /* 1150 * Move finished tx buffers back to the tx free list. 1151 */ 1152 if (sc->tx_free) { 1153 sc->tx_ftail->tx_next = sc->tx_head; 1154 sc->tx_ftail = ptxp; 1155 } else 1156 sc->tx_ftail = sc->tx_free = sc->tx_head; 1157 1158 sc->tx_head = sc->tx_tail = NULL; 1159 ifp->if_flags &= ~IFF_OACTIVE; 1160 } 1161 1162 if (stat & S_UP_COMPLETE) { 1163 struct ex_rxdesc *rxd; 1164 struct mbuf *m; 1165 struct ex_upd *upd; 1166 bus_dmamap_t rxmap; 1167 u_int32_t pktstat; 1168 1169 rcvloop: 1170 rxd = sc->rx_head; 1171 rxmap = rxd->rx_dmamap; 1172 m = rxd->rx_mbhead; 1173 upd = rxd->rx_upd; 1174 pktstat = pcitoh(upd->upd_pktstatus); 1175 1176 bus_dmamap_sync(sc->sc_dmat, rxmap, 0, 1177 rxmap->dm_mapsize, 1178 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1179 bus_dmamap_sync(sc->sc_dmat, sc->sc_upd_dmamap, 1180 ((caddr_t)upd - (caddr_t)sc->sc_upd), 1181 sizeof (struct ex_upd), 1182 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1183 1184 if (pktstat & EX_UPD_COMPLETE) { 1185 /* 1186 * Remove first packet from the chain. 1187 */ 1188 sc->rx_head = rxd->rx_next; 1189 rxd->rx_next = NULL; 1190 1191 /* 1192 * Add a new buffer to the receive chain. 1193 * If this fails, the old buffer is recycled 1194 * instead. 1195 */ 1196 if (ex_add_rxbuf(sc, rxd) == 0) { 1197 struct ether_header *eh; 1198 u_int16_t total_len; 1199 1200 1201 if (pktstat & EX_UPD_ERR) { 1202 ifp->if_ierrors++; 1203 m_freem(m); 1204 goto rcvloop; 1205 } 1206 1207 total_len = pktstat & EX_UPD_PKTLENMASK; 1208 if (total_len < 1209 sizeof(struct ether_header)) { 1210 m_freem(m); 1211 goto rcvloop; 1212 } 1213 m->m_pkthdr.rcvif = ifp; 1214 m->m_pkthdr.len = m->m_len = total_len; 1215 eh = mtod(m, struct ether_header *); 1216 #if NBPFILTER > 0 1217 if (ifp->if_bpf) { 1218 bpf_tap(ifp->if_bpf, 1219 mtod(m, caddr_t), 1220 total_len); 1221 /* 1222 * Only pass this packet up 1223 * if it is for us. 1224 */ 1225 if ((ifp->if_flags & 1226 IFF_PROMISC) && 1227 (eh->ether_dhost[0] & 1) 1228 == 0 && 1229 bcmp(eh->ether_dhost, 1230 LLADDR(ifp->if_sadl), 1231 sizeof(eh->ether_dhost)) 1232 != 0) { 1233 m_freem(m); 1234 goto rcvloop; 1235 } 1236 } 1237 #endif /* NBPFILTER > 0 */ 1238 (*ifp->if_input)(ifp, m); 1239 } 1240 goto rcvloop; 1241 } 1242 /* 1243 * Just in case we filled up all UPDs and the DMA engine 1244 * stalled. We could be more subtle about this. 1245 */ 1246 if (bus_space_read_4(iot, ioh, ELINK_UPLISTPTR) == 0) { 1247 printf("%s: uplistptr was 0\n", 1248 sc->sc_dev.dv_xname); 1249 ex_init(sc); 1250 } else if (bus_space_read_4(iot, ioh, ELINK_UPPKTSTATUS) 1251 & 0x2000) { 1252 printf("%s: receive stalled\n", 1253 sc->sc_dev.dv_xname); 1254 bus_space_write_2(iot, ioh, ELINK_COMMAND, 1255 ELINK_UPUNSTALL); 1256 } 1257 } 1258 } 1259 if (ret) { 1260 bus_space_write_2(iot, ioh, ELINK_COMMAND, C_INTR_LATCH); 1261 if (ifp->if_snd.ifq_head != NULL) 1262 ex_start(ifp); 1263 } 1264 return ret; 1265 } 1266 1267 int 1268 ex_ioctl(ifp, cmd, data) 1269 register struct ifnet *ifp; 1270 u_long cmd; 1271 caddr_t data; 1272 { 1273 struct ex_softc *sc = ifp->if_softc; 1274 struct ifaddr *ifa = (struct ifaddr *)data; 1275 struct ifreq *ifr = (struct ifreq *)data; 1276 int s, error = 0; 1277 1278 s = splnet(); 1279 1280 switch (cmd) { 1281 1282 case SIOCSIFADDR: 1283 ifp->if_flags |= IFF_UP; 1284 switch (ifa->ifa_addr->sa_family) { 1285 #ifdef INET 1286 case AF_INET: 1287 ex_init(sc); 1288 arp_ifinit(&sc->sc_ethercom.ec_if, ifa); 1289 break; 1290 #endif 1291 #ifdef NS 1292 case AF_NS: 1293 { 1294 register struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1295 1296 if (ns_nullhost(*ina)) 1297 ina->x_host = *(union ns_host *) 1298 LLADDR(ifp->if_sadl); 1299 else 1300 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 1301 ifp->if_addrlen); 1302 /* Set new address. */ 1303 ex_init(sc); 1304 break; 1305 } 1306 #endif 1307 default: 1308 ex_init(sc); 1309 break; 1310 } 1311 break; 1312 case SIOCSIFMEDIA: 1313 case SIOCGIFMEDIA: 1314 error = ifmedia_ioctl(ifp, ifr, &sc->ex_mii.mii_media, cmd); 1315 break; 1316 1317 case SIOCSIFFLAGS: 1318 if ((ifp->if_flags & IFF_UP) == 0 && 1319 (ifp->if_flags & IFF_RUNNING) != 0) { 1320 /* 1321 * If interface is marked down and it is running, then 1322 * stop it. 1323 */ 1324 ex_stop(sc); 1325 ifp->if_flags &= ~IFF_RUNNING; 1326 } else if ((ifp->if_flags & IFF_UP) != 0 && 1327 (ifp->if_flags & IFF_RUNNING) == 0) { 1328 /* 1329 * If interface is marked up and it is stopped, then 1330 * start it. 1331 */ 1332 ex_init(sc); 1333 } else if ((ifp->if_flags & IFF_UP) != 0) { 1334 /* 1335 * Deal with other flags that change hardware 1336 * state, i.e. IFF_PROMISC. 1337 */ 1338 ex_set_mc(sc); 1339 } 1340 break; 1341 1342 case SIOCADDMULTI: 1343 case SIOCDELMULTI: 1344 error = (cmd == SIOCADDMULTI) ? 1345 ether_addmulti(ifr, &sc->sc_ethercom) : 1346 ether_delmulti(ifr, &sc->sc_ethercom); 1347 1348 if (error == ENETRESET) { 1349 /* 1350 * Multicast list has changed; set the hardware filter 1351 * accordingly. 1352 */ 1353 ex_set_mc(sc); 1354 error = 0; 1355 } 1356 break; 1357 1358 default: 1359 error = EINVAL; 1360 break; 1361 } 1362 1363 splx(s); 1364 return (error); 1365 } 1366 1367 void 1368 ex_getstats(sc) 1369 struct ex_softc *sc; 1370 { 1371 bus_space_handle_t ioh = sc->sc_ioh; 1372 bus_space_tag_t iot = sc->sc_iot; 1373 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1374 u_int8_t upperok; 1375 1376 GO_WINDOW(6); 1377 upperok = bus_space_read_1(iot, ioh, UPPER_FRAMES_OK); 1378 ifp->if_ipackets += bus_space_read_1(iot, ioh, RX_FRAMES_OK); 1379 ifp->if_ipackets += (upperok & 0x03) << 8; 1380 ifp->if_opackets += bus_space_read_1(iot, ioh, TX_FRAMES_OK); 1381 ifp->if_opackets += (upperok & 0x30) << 4; 1382 ifp->if_ierrors += bus_space_read_1(iot, ioh, RX_OVERRUNS); 1383 ifp->if_collisions += bus_space_read_1(iot, ioh, TX_COLLISIONS); 1384 /* 1385 * There seems to be no way to get the exact number of collisions, 1386 * this is the number that occured at the very least. 1387 */ 1388 ifp->if_collisions += 2 * bus_space_read_1(iot, ioh, 1389 TX_AFTER_X_COLLISIONS); 1390 ifp->if_ibytes += bus_space_read_2(iot, ioh, RX_TOTAL_OK); 1391 ifp->if_obytes += bus_space_read_2(iot, ioh, TX_TOTAL_OK); 1392 1393 /* 1394 * Clear the following to avoid stats overflow interrupts 1395 */ 1396 bus_space_read_1(iot, ioh, TX_DEFERRALS); 1397 bus_space_read_1(iot, ioh, TX_AFTER_1_COLLISION); 1398 bus_space_read_1(iot, ioh, TX_NO_SQE); 1399 bus_space_read_1(iot, ioh, TX_CD_LOST); 1400 GO_WINDOW(4); 1401 bus_space_read_1(iot, ioh, ELINK_W4_BADSSD); 1402 upperok = bus_space_read_1(iot, ioh, ELINK_W4_UBYTESOK); 1403 ifp->if_ibytes += (upperok & 0x0f) << 16; 1404 ifp->if_obytes += (upperok & 0xf0) << 12; 1405 GO_WINDOW(1); 1406 } 1407 1408 void 1409 ex_printstats(sc) 1410 struct ex_softc *sc; 1411 { 1412 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1413 1414 ex_getstats(sc); 1415 printf("in %ld out %ld ierror %ld oerror %ld ibytes %ld obytes %ld\n", 1416 ifp->if_ipackets, ifp->if_opackets, ifp->if_ierrors, 1417 ifp->if_oerrors, ifp->if_ibytes, ifp->if_obytes); 1418 } 1419 1420 void 1421 ex_tick(arg) 1422 void *arg; 1423 { 1424 struct ex_softc *sc = arg; 1425 int s = splnet(); 1426 1427 if (sc->ex_conf & EX_CONF_MII) 1428 mii_tick(&sc->ex_mii); 1429 1430 if (!(bus_space_read_2((sc)->sc_iot, (sc)->sc_ioh, ELINK_STATUS) 1431 & S_COMMAND_IN_PROGRESS)) 1432 ex_getstats(sc); 1433 1434 splx(s); 1435 1436 timeout(ex_tick, sc, hz); 1437 } 1438 1439 1440 void 1441 ex_reset(sc) 1442 struct ex_softc *sc; 1443 { 1444 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_COMMAND, GLOBAL_RESET); 1445 delay(400); 1446 ex_waitcmd(sc); 1447 } 1448 1449 void 1450 ex_watchdog(ifp) 1451 struct ifnet *ifp; 1452 { 1453 struct ex_softc *sc = ifp->if_softc; 1454 1455 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1456 ++sc->sc_ethercom.ec_if.if_oerrors; 1457 1458 ex_reset(sc); 1459 ex_init(sc); 1460 } 1461 1462 void 1463 ex_stop(sc) 1464 struct ex_softc *sc; 1465 { 1466 bus_space_tag_t iot = sc->sc_iot; 1467 bus_space_handle_t ioh = sc->sc_ioh; 1468 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1469 struct ex_txdesc *tx; 1470 struct ex_rxdesc *rx; 1471 int i; 1472 1473 bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_DISABLE); 1474 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_DISABLE); 1475 bus_space_write_2(iot, ioh, ELINK_COMMAND, STOP_TRANSCEIVER); 1476 1477 for (tx = sc->tx_head ; tx != NULL; tx = tx->tx_next) { 1478 if (tx->tx_mbhead == NULL) 1479 continue; 1480 m_freem(tx->tx_mbhead); 1481 tx->tx_mbhead = NULL; 1482 bus_dmamap_unload(sc->sc_dmat, tx->tx_dmamap); 1483 tx->tx_dpd->dpd_fsh = tx->tx_dpd->dpd_nextptr = 0; 1484 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap, 1485 ((caddr_t)tx->tx_dpd - (caddr_t)sc->sc_dpd), 1486 sizeof (struct ex_dpd), 1487 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1488 } 1489 sc->tx_tail = sc->tx_head = NULL; 1490 ex_init_txdescs(sc); 1491 1492 sc->rx_tail = sc->rx_head = 0; 1493 for (i = 0; i < EX_NUPD; i++) { 1494 rx = &sc->sc_rxdescs[i]; 1495 if (rx->rx_mbhead != NULL) { 1496 bus_dmamap_unload(sc->sc_dmat, rx->rx_dmamap); 1497 m_freem(rx->rx_mbhead); 1498 rx->rx_mbhead = NULL; 1499 } 1500 ex_add_rxbuf(sc, rx); 1501 } 1502 1503 bus_space_write_2(iot, ioh, ELINK_COMMAND, C_INTR_LATCH); 1504 1505 untimeout(ex_tick, sc); 1506 if (sc->ex_conf & EX_CONF_MII) 1507 mii_down(&sc->ex_mii); 1508 1509 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1510 ifp->if_timer = 0; 1511 } 1512 1513 static void 1514 ex_init_txdescs(sc) 1515 struct ex_softc *sc; 1516 { 1517 int i; 1518 1519 for (i = 0; i < EX_NDPD; i++) { 1520 sc->sc_txdescs[i].tx_dmamap = sc->sc_tx_dmamaps[i]; 1521 sc->sc_txdescs[i].tx_dpd = &sc->sc_dpd[i]; 1522 if (i < EX_NDPD - 1) 1523 sc->sc_txdescs[i].tx_next = &sc->sc_txdescs[i + 1]; 1524 else 1525 sc->sc_txdescs[i].tx_next = NULL; 1526 } 1527 sc->tx_free = &sc->sc_txdescs[0]; 1528 sc->tx_ftail = &sc->sc_txdescs[EX_NDPD-1]; 1529 } 1530 1531 1532 /* 1533 * Before reboots, reset card completely. 1534 */ 1535 static void 1536 ex_shutdown(arg) 1537 void *arg; 1538 { 1539 register struct ex_softc *sc = arg; 1540 1541 ex_stop(sc); 1542 } 1543 1544 /* 1545 * Read EEPROM data. 1546 * XXX what to do if EEPROM doesn't unbusy? 1547 */ 1548 u_int16_t 1549 ex_read_eeprom(sc, offset) 1550 struct ex_softc *sc; 1551 int offset; 1552 { 1553 bus_space_tag_t iot = sc->sc_iot; 1554 bus_space_handle_t ioh = sc->sc_ioh; 1555 u_int16_t data = 0; 1556 1557 GO_WINDOW(0); 1558 if (ex_eeprom_busy(sc)) 1559 goto out; 1560 switch (sc->ex_bustype) { 1561 case EX_BUS_PCI: 1562 bus_space_write_1(iot, ioh, ELINK_W0_EEPROM_COMMAND, 1563 READ_EEPROM | (offset & 0x3f)); 1564 break; 1565 case EX_BUS_CARDBUS: 1566 bus_space_write_2(iot, ioh, ELINK_W0_EEPROM_COMMAND, 1567 0x230 + (offset & 0x3f)); 1568 break; 1569 } 1570 if (ex_eeprom_busy(sc)) 1571 goto out; 1572 data = bus_space_read_2(iot, ioh, ELINK_W0_EEPROM_DATA); 1573 out: 1574 return data; 1575 } 1576 1577 static int 1578 ex_eeprom_busy(sc) 1579 struct ex_softc *sc; 1580 { 1581 bus_space_tag_t iot = sc->sc_iot; 1582 bus_space_handle_t ioh = sc->sc_ioh; 1583 int i = 100; 1584 1585 while (i--) { 1586 if (!(bus_space_read_2(iot, ioh, ELINK_W0_EEPROM_COMMAND) & 1587 EEPROM_BUSY)) 1588 return 0; 1589 delay(100); 1590 } 1591 printf("\n%s: eeprom stays busy.\n", sc->sc_dev.dv_xname); 1592 return (1); 1593 } 1594 1595 /* 1596 * Create a new rx buffer and add it to the 'soft' rx list. 1597 */ 1598 static int 1599 ex_add_rxbuf(sc, rxd) 1600 struct ex_softc *sc; 1601 struct ex_rxdesc *rxd; 1602 { 1603 struct mbuf *m, *oldm; 1604 bus_dmamap_t rxmap; 1605 int error, rval = 0; 1606 1607 oldm = rxd->rx_mbhead; 1608 rxmap = rxd->rx_dmamap; 1609 1610 MGETHDR(m, M_DONTWAIT, MT_DATA); 1611 if (m != NULL) { 1612 MCLGET(m, M_DONTWAIT); 1613 if ((m->m_flags & M_EXT) == 0) { 1614 m_freem(m); 1615 if (oldm == NULL) 1616 return 1; 1617 m = oldm; 1618 m->m_data = m->m_ext.ext_buf; 1619 rval = 1; 1620 } 1621 } else { 1622 if (oldm == NULL) 1623 return 1; 1624 m = oldm; 1625 m->m_data = m->m_ext.ext_buf; 1626 rval = 1; 1627 } 1628 1629 /* 1630 * Setup the DMA map for this receive buffer. 1631 */ 1632 if (m != oldm) { 1633 if (oldm != NULL) 1634 bus_dmamap_unload(sc->sc_dmat, rxmap); 1635 error = bus_dmamap_load(sc->sc_dmat, rxmap, 1636 m->m_ext.ext_buf, MCLBYTES, NULL, BUS_DMA_NOWAIT); 1637 if (error) { 1638 printf("%s: can't load rx buffer, error = %d\n", 1639 sc->sc_dev.dv_xname, error); 1640 panic("ex_add_rxbuf"); /* XXX */ 1641 } 1642 } 1643 1644 /* 1645 * Align for data after 14 byte header. 1646 */ 1647 m->m_data += 2; 1648 1649 rxd->rx_mbhead = m; 1650 rxd->rx_upd->upd_pktstatus = htopci(MCLBYTES - 2); 1651 rxd->rx_upd->upd_frags[0].fr_addr = 1652 htopci(rxmap->dm_segs[0].ds_addr + 2); 1653 rxd->rx_upd->upd_nextptr = 0; 1654 1655 /* 1656 * Attach it to the end of the list. 1657 */ 1658 if (sc->rx_head != NULL) { 1659 sc->rx_tail->rx_next = rxd; 1660 sc->rx_tail->rx_upd->upd_nextptr = htopci(sc->sc_upddma + 1661 ((caddr_t)rxd->rx_upd - (caddr_t)sc->sc_upd)); 1662 bus_dmamap_sync(sc->sc_dmat, sc->sc_upd_dmamap, 1663 (caddr_t)sc->rx_tail->rx_upd - (caddr_t)sc->sc_upd, 1664 sizeof (struct ex_upd), 1665 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1666 } else { 1667 sc->rx_head = rxd; 1668 } 1669 sc->rx_tail = rxd; 1670 1671 bus_dmamap_sync(sc->sc_dmat, rxmap, 0, rxmap->dm_mapsize, 1672 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1673 bus_dmamap_sync(sc->sc_dmat, sc->sc_upd_dmamap, 1674 ((caddr_t)rxd->rx_upd - (caddr_t)sc->sc_upd), 1675 sizeof (struct ex_upd), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1676 return (rval); 1677 } 1678 1679 void 1680 ex_mii_setbit(v, bit) 1681 void *v; 1682 u_int16_t bit; 1683 { 1684 struct ex_softc *sc = v; 1685 u_int16_t val; 1686 1687 val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_PHYSMGMT); 1688 val |= bit; 1689 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_PHYSMGMT, val); 1690 } 1691 1692 void 1693 ex_mii_clrbit(v, bit) 1694 void *v; 1695 u_int16_t bit; 1696 { 1697 struct ex_softc *sc = v; 1698 u_int16_t val; 1699 1700 val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_PHYSMGMT); 1701 val &= ~bit; 1702 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_PHYSMGMT, val); 1703 } 1704 1705 u_int16_t 1706 ex_mii_readbit(v, bit) 1707 void *v; 1708 u_int16_t bit; 1709 { 1710 struct ex_softc *sc = v; 1711 u_int16_t val; 1712 1713 val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_PHYSMGMT); 1714 return (val & bit); 1715 } 1716 1717 void 1718 ex_mii_sync(sc) 1719 struct ex_softc *sc; 1720 { 1721 int i; 1722 1723 /* We assume we're already in Window 4 */ 1724 ex_mii_clrbit(sc, ELINK_PHY_DIR); 1725 for (i = 0; i < 32; i++) { 1726 ex_mii_clrbit(sc, ELINK_PHY_CLK); 1727 ex_mii_setbit(sc, ELINK_PHY_CLK); 1728 } 1729 } 1730 1731 void 1732 ex_mii_sendbits(sc, data, nbits) 1733 struct ex_softc *sc; 1734 u_int32_t data; 1735 int nbits; 1736 { 1737 int i; 1738 1739 /* We assume we're already in Window 4 */ 1740 ex_mii_setbit(sc, PHYSMGMT_DIR); 1741 for (i = 1 << (nbits -1); i; i = i >> 1) { 1742 ex_mii_clrbit(sc, ELINK_PHY_CLK); 1743 ex_mii_readbit(sc, ELINK_PHY_CLK); 1744 if (data & i) 1745 ex_mii_setbit(sc, ELINK_PHY_DATA); 1746 else 1747 ex_mii_clrbit(sc, ELINK_PHY_DATA); 1748 ex_mii_setbit(sc, ELINK_PHY_CLK); 1749 ex_mii_readbit(sc, ELINK_PHY_CLK); 1750 } 1751 } 1752 1753 int 1754 ex_mii_readreg(v, phy, reg) 1755 struct device *v; 1756 int phy, reg; 1757 { 1758 struct ex_softc *sc = (struct ex_softc *)v; 1759 int val = 0, i, err; 1760 1761 if ((sc->ex_conf & EX_CONF_INTPHY) && phy != ELINK_INTPHY_ID) 1762 return 0; 1763 1764 GO_WINDOW(4); 1765 1766 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_PHYSMGMT, 0); 1767 1768 ex_mii_sync(sc); 1769 ex_mii_sendbits(sc, MII_COMMAND_START, 2); 1770 ex_mii_sendbits(sc, MII_COMMAND_READ, 2); 1771 ex_mii_sendbits(sc, phy, 5); 1772 ex_mii_sendbits(sc, reg, 5); 1773 1774 ex_mii_clrbit(sc, ELINK_PHY_DIR); 1775 ex_mii_clrbit(sc, ELINK_PHY_CLK); 1776 ex_mii_setbit(sc, ELINK_PHY_CLK); 1777 ex_mii_clrbit(sc, ELINK_PHY_CLK); 1778 1779 err = ex_mii_readbit(sc, ELINK_PHY_DATA); 1780 ex_mii_setbit(sc, ELINK_PHY_CLK); 1781 1782 /* Even if an error occurs, must still clock out the cycle. */ 1783 for (i = 0; i < 16; i++) { 1784 val <<= 1; 1785 ex_mii_clrbit(sc, ELINK_PHY_CLK); 1786 if (err == 0 && ex_mii_readbit(sc, ELINK_PHY_DATA)) 1787 val |= 1; 1788 ex_mii_setbit(sc, ELINK_PHY_CLK); 1789 } 1790 ex_mii_clrbit(sc, ELINK_PHY_CLK); 1791 ex_mii_setbit(sc, ELINK_PHY_CLK); 1792 1793 GO_WINDOW(1); 1794 1795 return (err ? 0 : val); 1796 } 1797 1798 void 1799 ex_mii_writereg(v, phy, reg, data) 1800 struct device *v; 1801 int phy; 1802 int reg; 1803 int data; 1804 { 1805 struct ex_softc *sc = (struct ex_softc *)v; 1806 1807 GO_WINDOW(4); 1808 1809 ex_mii_sync(sc); 1810 ex_mii_sendbits(sc, MII_COMMAND_START, 2); 1811 ex_mii_sendbits(sc, MII_COMMAND_WRITE, 2); 1812 ex_mii_sendbits(sc, phy, 5); 1813 ex_mii_sendbits(sc, reg, 5); 1814 ex_mii_sendbits(sc, MII_COMMAND_ACK, 2); 1815 ex_mii_sendbits(sc, data, 16); 1816 1817 ex_mii_clrbit(sc, ELINK_PHY_CLK); 1818 ex_mii_setbit(sc, ELINK_PHY_CLK); 1819 1820 GO_WINDOW(1); 1821 } 1822 1823 void 1824 ex_mii_statchg(v) 1825 struct device *v; 1826 { 1827 struct ex_softc *sc = (struct ex_softc *)v; 1828 bus_space_tag_t iot = sc->sc_iot; 1829 bus_space_handle_t ioh = sc->sc_ioh; 1830 int mctl; 1831 1832 /* XXX Update ifp->if_baudrate */ 1833 1834 GO_WINDOW(3); 1835 mctl = bus_space_read_2(iot, ioh, ELINK_W3_MAC_CONTROL); 1836 if (sc->ex_mii.mii_media_active & IFM_FDX) 1837 mctl |= MAC_CONTROL_FDX; 1838 else 1839 mctl &= ~MAC_CONTROL_FDX; 1840 bus_space_write_2(iot, ioh, ELINK_W3_MAC_CONTROL, mctl); 1841 GO_WINDOW(1); /* back to operating window */ 1842 } 1843
Indexes created Wed Oct 22 13:09:56 GMT 2025