elinkxl.c revision 1.5
1 /* $NetBSD: elinkxl.c,v 1.5 1999/02/28 17:10:53 explorer Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include "opt_inet.h" 40 #include "opt_ns.h" 41 #include "bpfilter.h" 42 #include "rnd.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/kernel.h> 47 #include <sys/mbuf.h> 48 #include <sys/socket.h> 49 #include <sys/ioctl.h> 50 #include <sys/errno.h> 51 #include <sys/syslog.h> 52 #include <sys/select.h> 53 #include <sys/device.h> 54 #if NRND > 0 55 #include <sys/rnd.h> 56 #endif 57 58 #include <net/if.h> 59 #include <net/if_dl.h> 60 #include <net/if_ether.h> 61 #include <net/if_media.h> 62 63 #ifdef INET 64 #include <netinet/in.h> 65 #include <netinet/in_systm.h> 66 #include <netinet/in_var.h> 67 #include <netinet/ip.h> 68 #include <netinet/if_inarp.h> 69 #endif 70 71 #ifdef NS 72 #include <netns/ns.h> 73 #include <netns/ns_if.h> 74 #endif 75 76 #if NBPFILTER > 0 77 #include <net/bpf.h> 78 #include <net/bpfdesc.h> 79 #endif 80 81 #include <machine/cpu.h> 82 #include <machine/bus.h> 83 #include <machine/intr.h> 84 85 #include <vm/vm.h> 86 #include <vm/pmap.h> 87 88 #include <dev/mii/miivar.h> 89 #include <dev/mii/mii.h> 90 91 #include <dev/ic/elink3reg.h> 92 /* #include <dev/ic/elink3var.h> */ 93 #include <dev/ic/elinkxlreg.h> 94 #include <dev/ic/elinkxlvar.h> 95 96 #define ETHER_MIN_LEN 64 97 #define ETHER_MAX_LEN 1518 98 #define ETHER_ADDR_LEN 6 99 100 #ifdef DEBUG 101 int exdebug = 0; 102 #endif 103 104 /* ifmedia callbacks */ 105 int ex_media_chg __P((struct ifnet *ifp)); 106 void ex_media_stat __P((struct ifnet *ifp, struct ifmediareq *req)); 107 108 void ex_probe_media __P((struct ex_softc *)); 109 void ex_set_filter __P((struct ex_softc *)); 110 void ex_set_media __P((struct ex_softc *)); 111 struct mbuf *ex_get __P((struct ex_softc *, int)); 112 u_int16_t ex_read_eeprom __P((struct ex_softc *, int)); 113 void ex_init __P((struct ex_softc *)); 114 void ex_read __P((struct ex_softc *)); 115 void ex_reset __P((struct ex_softc *)); 116 void ex_set_mc __P((struct ex_softc *)); 117 void ex_getstats __P((struct ex_softc *)); 118 void ex_printstats __P((struct ex_softc *)); 119 void ex_tick __P((void *)); 120 121 static int ex_eeprom_busy __P((struct ex_softc *)); 122 static int ex_add_rxbuf __P((struct ex_softc *, struct ex_rxdesc *)); 123 static void ex_init_txdescs __P((struct ex_softc *)); 124 125 static void ex_shutdown __P((void *)); 126 static void ex_start __P((struct ifnet *)); 127 static void ex_txstat __P((struct ex_softc *)); 128 static u_int16_t ex_mchash __P((u_char *)); 129 static void ex_mii_writebits __P((struct ex_softc *, u_int, int)); 130 131 void ex_mii_setbit __P((void *, u_int16_t)); 132 void ex_mii_clrbit __P((void *, u_int16_t)); 133 u_int16_t ex_mii_readbit __P((void *, u_int16_t)); 134 int ex_mii_readreg __P((struct device *, int, int)); 135 void ex_mii_writereg __P((struct device *, int, int, int)); 136 void ex_mii_statchg __P((struct device *)); 137 138 void ex_probemedia __P((struct ex_softc *)); 139 140 /* 141 * Structure to map media-present bits in boards to ifmedia codes and 142 * printable media names. Used for table-driven ifmedia initialization. 143 */ 144 struct ex_media { 145 int exm_mpbit; /* media present bit */ 146 const char *exm_name; /* name of medium */ 147 int exm_ifmedia; /* ifmedia word for medium */ 148 int exm_epmedia; /* ELINKMEDIA_* constant */ 149 }; 150 151 /* 152 * Media table for 3c90x chips. Note that chips with MII have no 153 * `native' media. 154 */ 155 struct ex_media ex_native_media[] = { 156 { ELINK_PCI_10BASE_T, "10baseT", IFM_ETHER|IFM_10_T, 157 ELINKMEDIA_10BASE_T }, 158 { ELINK_PCI_10BASE_T, "10baseT-FDX", IFM_ETHER|IFM_10_T|IFM_FDX, 159 ELINKMEDIA_10BASE_T }, 160 { ELINK_PCI_AUI, "10base5", IFM_ETHER|IFM_10_5, 161 ELINKMEDIA_AUI }, 162 { ELINK_PCI_BNC, "10base2", IFM_ETHER|IFM_10_2, 163 ELINKMEDIA_10BASE_2 }, 164 { ELINK_PCI_100BASE_TX, "100baseTX", IFM_ETHER|IFM_100_TX, 165 ELINKMEDIA_100BASE_TX }, 166 { ELINK_PCI_100BASE_TX, "100baseTX-FDX",IFM_ETHER|IFM_100_TX|IFM_FDX, 167 ELINKMEDIA_100BASE_TX }, 168 { ELINK_PCI_100BASE_FX, "100baseFX", IFM_ETHER|IFM_100_FX, 169 ELINKMEDIA_100BASE_FX }, 170 { ELINK_PCI_100BASE_MII,"manual", IFM_ETHER|IFM_MANUAL, 171 ELINKMEDIA_MII }, 172 { ELINK_PCI_100BASE_T4, "100baseT4", IFM_ETHER|IFM_100_T4, 173 ELINKMEDIA_100BASE_T4 }, 174 { 0, NULL, 0, 175 0 }, 176 }; 177 178 /* 179 * Back-end attach and configure. 180 */ 181 void 182 ex_config(sc) 183 struct ex_softc *sc; 184 { 185 struct ifnet *ifp; 186 u_int16_t val; 187 u_int8_t macaddr[ETHER_ADDR_LEN] = {0}; 188 bus_space_tag_t iot = sc->sc_iot; 189 bus_space_handle_t ioh = sc->sc_ioh; 190 bus_dma_segment_t useg, dseg; 191 int urseg, drseg, i, error, attach_stage; 192 193 ex_reset(sc); 194 195 val = ex_read_eeprom(sc, EEPROM_OEM_ADDR0); 196 macaddr[0] = val >> 8; 197 macaddr[1] = val & 0xff; 198 val = ex_read_eeprom(sc, EEPROM_OEM_ADDR1); 199 macaddr[2] = val >> 8; 200 macaddr[3] = val & 0xff; 201 val = ex_read_eeprom(sc, EEPROM_OEM_ADDR2); 202 macaddr[4] = val >> 8; 203 macaddr[5] = val & 0xff; 204 205 printf("%s: MAC address %s\n", sc->sc_dev.dv_xname, 206 ether_sprintf(macaddr)); 207 208 attach_stage = 0; 209 210 /* 211 * Allocate the upload descriptors, and create and load the DMA 212 * map for them. 213 */ 214 if ((error = bus_dmamem_alloc(sc->sc_dmat, 215 EX_NUPD * sizeof (struct ex_upd), NBPG, 0, &useg, 1, &urseg, 216 BUS_DMA_NOWAIT)) != 0) { 217 printf("%s: can't allocate upload descriptors, error = %d\n", 218 sc->sc_dev.dv_xname, error); 219 goto fail; 220 } 221 222 attach_stage = 1; 223 224 if ((error = bus_dmamem_map(sc->sc_dmat, &useg, urseg, 225 EX_NUPD * sizeof (struct ex_upd), (caddr_t *)&sc->sc_upd, 226 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 227 printf("%s: can't map upload descriptors, error = %d\n", 228 sc->sc_dev.dv_xname, error); 229 goto fail; 230 } 231 232 attach_stage = 2; 233 234 if ((error = bus_dmamap_create(sc->sc_dmat, 235 EX_NUPD * sizeof (struct ex_upd), 1, 236 EX_NUPD * sizeof (struct ex_upd), 0, BUS_DMA_NOWAIT, 237 &sc->sc_upd_dmamap)) != 0) { 238 printf("%s: can't create upload desc. DMA map, error = %d\n", 239 sc->sc_dev.dv_xname, error); 240 goto fail; 241 } 242 243 attach_stage = 3; 244 245 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_upd_dmamap, 246 sc->sc_upd, EX_NUPD * sizeof (struct ex_upd), NULL, 247 BUS_DMA_NOWAIT)) != 0) { 248 printf("%s: can't load upload desc. DMA map, error = %d\n", 249 sc->sc_dev.dv_xname, error); 250 goto fail; 251 } 252 253 attach_stage = 4; 254 255 /* 256 * Allocate the download descriptors, and create and load the DMA 257 * map for them. 258 */ 259 if ((error = bus_dmamem_alloc(sc->sc_dmat, 260 EX_NDPD * sizeof (struct ex_dpd), NBPG, 0, &dseg, 1, &drseg, 261 BUS_DMA_NOWAIT)) != 0) { 262 printf("%s: can't allocate download descriptors, error = %d\n", 263 sc->sc_dev.dv_xname, error); 264 goto fail; 265 } 266 267 attach_stage = 5; 268 269 if ((error = bus_dmamem_map(sc->sc_dmat, &dseg, drseg, 270 EX_NDPD * sizeof (struct ex_dpd), (caddr_t *)&sc->sc_dpd, 271 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 272 printf("%s: can't map download descriptors, error = %d\n", 273 sc->sc_dev.dv_xname, error); 274 goto fail; 275 } 276 bzero(sc->sc_dpd, EX_NDPD * sizeof (struct ex_dpd)); 277 278 attach_stage = 6; 279 280 if ((error = bus_dmamap_create(sc->sc_dmat, 281 EX_NDPD * sizeof (struct ex_dpd), 1, 282 EX_NDPD * sizeof (struct ex_dpd), 0, BUS_DMA_NOWAIT, 283 &sc->sc_dpd_dmamap)) != 0) { 284 printf("%s: can't create download desc. DMA map, error = %d\n", 285 sc->sc_dev.dv_xname, error); 286 goto fail; 287 } 288 289 attach_stage = 7; 290 291 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dpd_dmamap, 292 sc->sc_dpd, EX_NDPD * sizeof (struct ex_dpd), NULL, 293 BUS_DMA_NOWAIT)) != 0) { 294 printf("%s: can't load download desc. DMA map, error = %d\n", 295 sc->sc_dev.dv_xname, error); 296 goto fail; 297 } 298 299 attach_stage = 8; 300 301 302 /* 303 * Create the transmit buffer DMA maps. 304 */ 305 for (i = 0; i < EX_NDPD; i++) { 306 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 307 EX_NTFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 308 &sc->sc_tx_dmamaps[i])) != 0) { 309 printf("%s: can't create tx DMA map %d, error = %d\n", 310 sc->sc_dev.dv_xname, i, error); 311 goto fail; 312 } 313 } 314 315 attach_stage = 9; 316 317 /* 318 * Create the receive buffer DMA maps. 319 */ 320 for (i = 0; i < EX_NUPD; i++) { 321 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 322 EX_NRFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 323 &sc->sc_rx_dmamaps[i])) != 0) { 324 printf("%s: can't create rx DMA map %d, error = %d\n", 325 sc->sc_dev.dv_xname, i, error); 326 goto fail; 327 } 328 } 329 330 attach_stage = 10; 331 332 /* 333 * Create ring of upload descriptors, only once. The DMA engine 334 * will loop over this when receiving packets, stalling if it 335 * hits an UPD with a finished receive. 336 */ 337 for (i = 0; i < EX_NUPD; i++) { 338 sc->sc_rxdescs[i].rx_dmamap = sc->sc_rx_dmamaps[i]; 339 sc->sc_rxdescs[i].rx_upd = &sc->sc_upd[i]; 340 sc->sc_upd[i].upd_frags[0].fr_len = (MCLBYTES - 2) | EX_FR_LAST; 341 if (ex_add_rxbuf(sc, &sc->sc_rxdescs[i]) != 0) { 342 printf("%s: can't allocate or map rx buffers\n", 343 sc->sc_dev.dv_xname); 344 goto fail; 345 } 346 } 347 348 bus_dmamap_sync(sc->sc_dmat, sc->sc_upd_dmamap, 0, 349 EX_NUPD * sizeof (struct ex_upd), 350 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 351 352 ex_init_txdescs(sc); 353 354 attach_stage = 11; 355 356 357 GO_WINDOW(3); 358 val = bus_space_read_2(iot, ioh, ELINK_W3_RESET_OPTIONS); 359 if (val & ELINK_MEDIACAP_MII) 360 sc->ex_conf |= EX_CONF_MII; 361 362 ifp = &sc->sc_ethercom.ec_if; 363 364 /* 365 * Initialize our media structures and MII info. We'll 366 * probe the MII if we discover that we have one. 367 */ 368 sc->ex_mii.mii_ifp = ifp; 369 sc->ex_mii.mii_readreg = ex_mii_readreg; 370 sc->ex_mii.mii_writereg = ex_mii_writereg; 371 sc->ex_mii.mii_statchg = ex_mii_statchg; 372 ifmedia_init(&sc->ex_mii.mii_media, 0, ex_media_chg, 373 ex_media_stat); 374 375 if (sc->ex_conf & EX_CONF_MII) { 376 /* 377 * Find PHY, extract media information from it. 378 */ 379 mii_phy_probe(&sc->sc_dev, &sc->ex_mii, 0xffffffff); 380 if (LIST_FIRST(&sc->ex_mii.mii_phys) == NULL) { 381 ifmedia_add(&sc->ex_mii.mii_media, IFM_ETHER|IFM_NONE, 382 0, NULL); 383 ifmedia_set(&sc->ex_mii.mii_media, IFM_ETHER|IFM_NONE); 384 } else { 385 ifmedia_set(&sc->ex_mii.mii_media, IFM_ETHER|IFM_AUTO); 386 } 387 } else 388 ex_probemedia(sc); 389 390 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 391 ifp->if_softc = sc; 392 ifp->if_start = ex_start; 393 ifp->if_ioctl = ex_ioctl; 394 ifp->if_watchdog = ex_watchdog; 395 ifp->if_flags = 396 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 397 398 if_attach(ifp); 399 ether_ifattach(ifp, macaddr); 400 401 GO_WINDOW(1); 402 403 sc->tx_start_thresh = 20; 404 sc->tx_succ_ok = 0; 405 406 /* TODO: set queues to 0 */ 407 408 #if NBPFILTER > 0 409 bpfattach(&sc->sc_ethercom.ec_if.if_bpf, ifp, DLT_EN10MB, 410 sizeof(struct ether_header)); 411 #endif 412 413 #if NRND > 0 414 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 415 RND_TYPE_NET, 0); 416 #endif 417 418 /* Establish callback to reset card when we reboot. */ 419 shutdownhook_establish(ex_shutdown, sc); 420 return; 421 422 fail: 423 /* 424 * Free any resources we've allocated during the failed attach 425 * attempt. Do this in reverse order and fall though. 426 */ 427 switch (attach_stage) { 428 case 11: 429 { 430 struct ex_rxdesc *rxd; 431 432 for (i = 0; i < EX_NUPD; i++) { 433 rxd = &sc->sc_rxdescs[i]; 434 if (rxd->rx_mbhead != NULL) { 435 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 436 m_freem(rxd->rx_mbhead); 437 } 438 } 439 } 440 /* FALLTHROUGH */ 441 442 case 10: 443 for (i = 0; i < EX_NUPD; i++) 444 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rx_dmamaps[i]); 445 /* FALLTHROUGH */ 446 447 case 9: 448 for (i = 0; i < EX_NDPD; i++) 449 bus_dmamap_destroy(sc->sc_dmat, sc->sc_tx_dmamaps[i]); 450 /* FALLTHROUGH */ 451 case 8: 452 bus_dmamap_unload(sc->sc_dmat, sc->sc_dpd_dmamap); 453 /* FALLTHROUGH */ 454 455 case 7: 456 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dpd_dmamap); 457 /* FALLTHROUGH */ 458 459 case 6: 460 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_dpd, 461 EX_NDPD * sizeof (struct ex_dpd)); 462 /* FALLTHROUGH */ 463 464 case 5: 465 bus_dmamem_free(sc->sc_dmat, &dseg, drseg); 466 break; 467 468 case 4: 469 bus_dmamap_unload(sc->sc_dmat, sc->sc_upd_dmamap); 470 /* FALLTHROUGH */ 471 472 case 3: 473 bus_dmamap_destroy(sc->sc_dmat, sc->sc_upd_dmamap); 474 /* FALLTHROUGH */ 475 476 case 2: 477 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_upd, 478 EX_NUPD * sizeof (struct ex_upd)); 479 /* FALLTHROUGH */ 480 481 case 1: 482 bus_dmamem_free(sc->sc_dmat, &useg, urseg); 483 break; 484 } 485 486 } 487 488 /* 489 * Find the media present on non-MII chips. 490 */ 491 void 492 ex_probemedia(sc) 493 struct ex_softc *sc; 494 { 495 bus_space_tag_t iot = sc->sc_iot; 496 bus_space_handle_t ioh = sc->sc_ioh; 497 struct ifmedia *ifm = &sc->ex_mii.mii_media; 498 struct ex_media *exm; 499 u_int16_t config1, reset_options, default_media; 500 int defmedia = 0; 501 const char *sep = "", *defmedianame = NULL; 502 503 GO_WINDOW(3); 504 config1 = bus_space_read_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG + 2); 505 reset_options = bus_space_read_1(iot, ioh, ELINK_W3_RESET_OPTIONS); 506 GO_WINDOW(0); 507 508 default_media = (config1 & CONFIG_MEDIAMASK) >> CONFIG_MEDIAMASK_SHIFT; 509 510 printf("%s: ", sc->sc_dev.dv_xname); 511 512 /* Sanity check that there are any media! */ 513 if ((reset_options & ELINK_PCI_MEDIAMASK) == 0) { 514 printf("no media present!\n"); 515 ifmedia_add(ifm, IFM_ETHER|IFM_NONE, 0, NULL); 516 ifmedia_set(ifm, IFM_ETHER|IFM_NONE); 517 return; 518 } 519 520 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 521 522 for (exm = ex_native_media; exm->exm_name != NULL; exm++) { 523 if (reset_options & exm->exm_mpbit) { 524 /* 525 * Default media is a little complicated. We 526 * support full-duplex which uses the same 527 * reset options bit. 528 * 529 * XXX Check EEPROM for default to FDX? 530 */ 531 if (exm->exm_epmedia == default_media) { 532 if ((exm->exm_ifmedia & IFM_FDX) == 0) { 533 defmedia = exm->exm_ifmedia; 534 defmedianame = exm->exm_name; 535 } 536 } else if (defmedia == 0) { 537 defmedia = exm->exm_ifmedia; 538 defmedianame = exm->exm_name; 539 } 540 ifmedia_add(ifm, exm->exm_ifmedia, exm->exm_epmedia, 541 NULL); 542 PRINT(exm->exm_name); 543 } 544 } 545 546 #undef PRINT 547 548 #ifdef DIAGNOSTIC 549 if (defmedia == 0) 550 panic("ex_probemedia: impossible"); 551 #endif 552 553 printf(", default %s\n", defmedianame); 554 ifmedia_set(ifm, defmedia); 555 } 556 557 /* 558 * Bring device up. 559 */ 560 void 561 ex_init(sc) 562 struct ex_softc *sc; 563 { 564 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 565 bus_space_tag_t iot = sc->sc_iot; 566 bus_space_handle_t ioh = sc->sc_ioh; 567 int s, i; 568 569 s = splnet(); 570 571 ex_waitcmd(sc); 572 ex_stop(sc); 573 574 /* 575 * Set the station address and clear the station mask. The latter 576 * is needed for 90x cards, 0 is the default for 90xB cards. 577 */ 578 GO_WINDOW(2); 579 for (i = 0; i < ETHER_ADDR_LEN; i++) { 580 bus_space_write_1(iot, ioh, ELINK_W2_ADDR_0 + i, 581 LLADDR(ifp->if_sadl)[i]); 582 bus_space_write_1(iot, ioh, ELINK_W2_RECVMASK_0 + i, 0); 583 } 584 585 GO_WINDOW(3); 586 587 bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_RESET); 588 ex_waitcmd(sc); 589 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_RESET); 590 ex_waitcmd(sc); 591 592 /* 593 * Disable reclaim threshold for 90xB, set free threshold to 594 * 6 * 256 = 1536 for 90x. 595 */ 596 if (sc->ex_conf & EX_CONF_90XB) 597 bus_space_write_2(iot, ioh, ELINK_COMMAND, 598 ELINK_TXRECLTHRESH | 255); 599 else 600 bus_space_write_1(iot, ioh, ELINK_TXFREETHRESH, 6); 601 602 bus_space_write_2(iot, ioh, ELINK_COMMAND, 603 SET_RX_EARLY_THRESH | ELINK_THRESH_DISABLE); 604 605 bus_space_write_4(iot, ioh, ELINK_DMACTRL, 606 bus_space_read_4(iot, ioh, ELINK_DMACTRL) | ELINK_DMAC_UPRXEAREN); 607 608 bus_space_write_2(iot, ioh, ELINK_COMMAND, SET_RD_0_MASK | S_MASK); 609 bus_space_write_2(iot, ioh, ELINK_COMMAND, SET_INTR_MASK | S_MASK); 610 611 bus_space_write_2(iot, ioh, ELINK_COMMAND, ACK_INTR | 0xff); 612 613 ex_set_media(sc); 614 ex_set_mc(sc); 615 616 617 bus_space_write_2(iot, ioh, ELINK_COMMAND, STATS_ENABLE); 618 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_ENABLE); 619 bus_space_write_4(iot, ioh, ELINK_UPLISTPTR, sc->sc_upddma); 620 bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_ENABLE); 621 bus_space_write_2(iot, ioh, ELINK_COMMAND, ELINK_UPUNSTALL); 622 623 ifp->if_flags |= IFF_RUNNING; 624 ifp->if_flags &= ~IFF_OACTIVE; 625 ex_start(ifp); 626 627 GO_WINDOW(1); 628 629 splx(s); 630 631 timeout(ex_tick, sc, hz); 632 } 633 634 /* 635 * Multicast hash filter according to the 3Com spec. 636 */ 637 static u_int16_t 638 ex_mchash(addr) 639 u_char *addr; 640 { 641 u_int32_t crc, carry; 642 int i, j; 643 u_char c; 644 645 /* Compute CRC for the address value. */ 646 crc = 0xffffffff; /* initial value */ 647 648 for (i = 0; i < 6; i++) { 649 c = addr[i]; 650 for (j = 0; i < 8; i++) { 651 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 652 crc <<= 1; 653 c >>= 1; 654 if (carry) 655 crc = (crc ^ 0x04c11db6) | carry; 656 } 657 } 658 659 /* Return the filter bit position. */ 660 return(crc & 0x000000ff); 661 } 662 663 664 /* 665 * Set multicast receive filter. Also take care of promiscuous mode 666 * here (XXX). 667 */ 668 void 669 ex_set_mc(sc) 670 register struct ex_softc *sc; 671 { 672 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 673 struct ethercom *ec = &sc->sc_ethercom; 674 struct ether_multi *enm; 675 struct ether_multistep estep; 676 int i; 677 u_int16_t mask = FIL_INDIVIDUAL | FIL_BRDCST; 678 679 if (ifp->if_flags & IFF_PROMISC) 680 mask |= FIL_PROMISC; 681 682 if (!(ifp->if_flags & IFF_MULTICAST)) 683 goto out; 684 685 if (!(sc->ex_conf & EX_CONF_90XB) || ifp->if_flags & IFF_ALLMULTI) { 686 mask |= (ifp->if_flags & IFF_MULTICAST) ? FIL_MULTICAST : 0; 687 } else { 688 ETHER_FIRST_MULTI(estep, ec, enm); 689 while (enm != NULL) { 690 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 691 ETHER_ADDR_LEN) != 0) 692 goto out; 693 i = ex_mchash(enm->enm_addrlo); 694 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 695 ELINK_COMMAND, ELINK_SETHASHFILBIT | i); 696 ETHER_NEXT_MULTI(estep, enm); 697 } 698 mask |= FIL_MULTIHASH; 699 } 700 out: 701 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_COMMAND, 702 SET_RX_FILTER | mask); 703 } 704 705 706 static void 707 ex_txstat(sc) 708 struct ex_softc *sc; 709 { 710 bus_space_tag_t iot = sc->sc_iot; 711 bus_space_handle_t ioh = sc->sc_ioh; 712 int i; 713 714 /* 715 * We need to read+write TX_STATUS until we get a 0 status 716 * in order to turn off the interrupt flag. 717 */ 718 while ((i = bus_space_read_1(iot, ioh, ELINK_TXSTATUS)) & TXS_COMPLETE) { 719 bus_space_write_1(iot, ioh, ELINK_TXSTATUS, 0x0); 720 721 if (i & TXS_JABBER) { 722 ++sc->sc_ethercom.ec_if.if_oerrors; 723 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 724 printf("%s: jabber (%x)\n", 725 sc->sc_dev.dv_xname, i); 726 ex_init(sc); 727 /* TODO: be more subtle here */ 728 } else if (i & TXS_UNDERRUN) { 729 ++sc->sc_ethercom.ec_if.if_oerrors; 730 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 731 printf("%s: fifo underrun (%x) @%d\n", 732 sc->sc_dev.dv_xname, i, 733 sc->tx_start_thresh); 734 if (sc->tx_succ_ok < 100) 735 sc->tx_start_thresh = min(ETHER_MAX_LEN, 736 sc->tx_start_thresh + 20); 737 sc->tx_succ_ok = 0; 738 ex_init(sc); 739 /* TODO: be more subtle here */ 740 } else if (i & TXS_MAX_COLLISION) { 741 ++sc->sc_ethercom.ec_if.if_collisions; 742 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_ENABLE); 743 sc->sc_ethercom.ec_if.if_flags &= ~IFF_OACTIVE; 744 } else 745 sc->tx_succ_ok = (sc->tx_succ_ok+1) & 127; 746 } 747 } 748 749 int 750 ex_media_chg(ifp) 751 struct ifnet *ifp; 752 { 753 struct ex_softc *sc = ifp->if_softc; 754 755 if (ifp->if_flags & IFF_UP) 756 ex_init(sc); 757 return 0; 758 } 759 760 void 761 ex_set_media(sc) 762 struct ex_softc *sc; 763 { 764 bus_space_tag_t iot = sc->sc_iot; 765 bus_space_handle_t ioh = sc->sc_ioh; 766 int config0, config1; 767 768 if (((sc->ex_conf & EX_CONF_MII) && 769 (sc->ex_mii.mii_media_active & IFM_FDX)) 770 || (!(sc->ex_conf & EX_CONF_MII) && 771 (sc->ex_mii.mii_media.ifm_media & IFM_FDX))) { 772 bus_space_write_2(iot, ioh, ELINK_W3_MAC_CONTROL, 773 MAC_CONTROL_FDX); 774 } else { 775 bus_space_write_2(iot, ioh, ELINK_W3_MAC_CONTROL, 0); 776 } 777 778 /* 779 * If the device has MII, select it, and then tell the 780 * PHY which media to use. 781 */ 782 if (sc->ex_conf & EX_CONF_MII) { 783 GO_WINDOW(3); 784 785 config0 = (u_int)bus_space_read_2(iot, ioh, 786 ELINK_W3_INTERNAL_CONFIG); 787 config1 = (u_int)bus_space_read_2(iot, ioh, 788 ELINK_W3_INTERNAL_CONFIG + 2); 789 790 config1 = config1 & ~CONFIG_MEDIAMASK; 791 config1 |= (ELINKMEDIA_MII << CONFIG_MEDIAMASK_SHIFT); 792 793 bus_space_write_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG, config0); 794 bus_space_write_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG + 2, config1); 795 mii_mediachg(&sc->ex_mii); 796 return; 797 } 798 799 GO_WINDOW(4); 800 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 0); 801 bus_space_write_2(iot, ioh, ELINK_COMMAND, STOP_TRANSCEIVER); 802 delay(800); 803 804 /* 805 * Now turn on the selected media/transceiver. 806 */ 807 switch (IFM_SUBTYPE(sc->ex_mii.mii_media.ifm_cur->ifm_media)) { 808 case IFM_10_T: 809 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 810 JABBER_GUARD_ENABLE|LINKBEAT_ENABLE); 811 break; 812 813 case IFM_10_2: 814 bus_space_write_2(iot, ioh, ELINK_COMMAND, START_TRANSCEIVER); 815 DELAY(800); 816 break; 817 818 case IFM_100_TX: 819 case IFM_100_FX: 820 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 821 LINKBEAT_ENABLE); 822 DELAY(800); 823 break; 824 825 case IFM_10_5: 826 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 827 SQE_ENABLE); 828 DELAY(800); 829 break; 830 831 case IFM_MANUAL: 832 break; 833 834 case IFM_NONE: 835 return; 836 837 default: 838 panic("ex_set_media: impossible"); 839 } 840 841 GO_WINDOW(3); 842 config0 = (u_int)bus_space_read_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG); 843 config1 = (u_int)bus_space_read_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG + 2); 844 845 config1 = config1 & ~CONFIG_MEDIAMASK; 846 config1 |= (sc->ex_mii.mii_media.ifm_cur->ifm_data << 847 CONFIG_MEDIAMASK_SHIFT); 848 849 bus_space_write_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG, config0); 850 bus_space_write_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG + 2, config1); 851 } 852 853 /* 854 * Get currently-selected media from card. 855 * (if_media callback, may be called before interface is brought up). 856 */ 857 void 858 ex_media_stat(ifp, req) 859 struct ifnet *ifp; 860 struct ifmediareq *req; 861 { 862 struct ex_softc *sc = ifp->if_softc; 863 864 if (sc->ex_conf & EX_CONF_MII) { 865 mii_pollstat(&sc->ex_mii); 866 req->ifm_status = sc->ex_mii.mii_media_status; 867 req->ifm_active = sc->ex_mii.mii_media_active; 868 } else { 869 GO_WINDOW(4); 870 req->ifm_status = IFM_AVALID; 871 req->ifm_active = sc->ex_mii.mii_media.ifm_cur->ifm_media; 872 if (bus_space_read_2(sc->sc_iot, sc->sc_ioh, 873 ELINK_W4_MEDIA_TYPE) & LINKBEAT_DETECT) 874 req->ifm_status |= IFM_ACTIVE; 875 GO_WINDOW(1); 876 } 877 } 878 879 880 881 /* 882 * Start outputting on the interface. 883 */ 884 static void 885 ex_start(ifp) 886 struct ifnet *ifp; 887 { 888 struct ex_softc *sc = ifp->if_softc; 889 bus_space_tag_t iot = sc->sc_iot; 890 bus_space_handle_t ioh = sc->sc_ioh; 891 volatile struct ex_fraghdr *fr = NULL; 892 volatile struct ex_dpd *dpd = NULL, *prevdpd = NULL; 893 struct ex_txdesc *txp; 894 bus_dmamap_t dmamap; 895 int offset, totlen; 896 897 if (sc->tx_head || sc->tx_free == NULL) 898 return; 899 900 txp = NULL; 901 902 /* 903 * We're finished if there is nothing more to add to the list or if 904 * we're all filled up with buffers to transmit. 905 */ 906 while (ifp->if_snd.ifq_head != NULL && sc->tx_free != NULL) { 907 struct mbuf *mb_head; 908 int segment, error; 909 910 /* 911 * Grab a packet to transmit. 912 */ 913 IF_DEQUEUE(&ifp->if_snd, mb_head); 914 915 /* 916 * Get pointer to next available tx desc. 917 */ 918 txp = sc->tx_free; 919 sc->tx_free = txp->tx_next; 920 txp->tx_next = NULL; 921 dmamap = txp->tx_dmamap; 922 923 /* 924 * Go through each of the mbufs in the chain and initialize 925 * the transmit buffer descriptors with the physical address 926 * and size of the mbuf. 927 */ 928 reload: 929 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 930 mb_head, BUS_DMA_NOWAIT); 931 switch (error) { 932 case 0: 933 /* Success. */ 934 break; 935 936 case EFBIG: 937 { 938 struct mbuf *mn; 939 940 /* 941 * We ran out of segments. We have to recopy this 942 * mbuf chain first. Bail out if we can't get the 943 * new buffers. 944 */ 945 printf("%s: too many segments, ", sc->sc_dev.dv_xname); 946 947 MGETHDR(mn, M_DONTWAIT, MT_DATA); 948 if (mn == NULL) { 949 m_freem(mb_head); 950 printf("aborting\n"); 951 goto out; 952 } 953 if (mb_head->m_pkthdr.len > MHLEN) { 954 MCLGET(mn, M_DONTWAIT); 955 if ((mn->m_flags & M_EXT) == 0) { 956 m_freem(mn); 957 m_freem(mb_head); 958 printf("aborting\n"); 959 goto out; 960 } 961 } 962 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 963 mtod(mn, caddr_t)); 964 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 965 m_freem(mb_head); 966 mb_head = mn; 967 printf("retrying\n"); 968 goto reload; 969 } 970 971 default: 972 /* 973 * Some other problem; report it. 974 */ 975 printf("%s: can't load mbuf chain, error = %d\n", 976 sc->sc_dev.dv_xname, error); 977 m_freem(mb_head); 978 goto out; 979 } 980 981 fr = &txp->tx_dpd->dpd_frags[0]; 982 totlen = 0; 983 for (segment = 0; segment < dmamap->dm_nsegs; segment++, fr++) { 984 fr->fr_addr = dmamap->dm_segs[segment].ds_addr; 985 fr->fr_len = dmamap->dm_segs[segment].ds_len; 986 totlen += fr->fr_len; 987 } 988 fr--; 989 fr->fr_len |= EX_FR_LAST; 990 txp->tx_mbhead = mb_head; 991 992 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 993 BUS_DMASYNC_PREWRITE); 994 995 dpd = txp->tx_dpd; 996 dpd->dpd_nextptr = 0; 997 dpd->dpd_fsh = totlen; 998 999 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap, 1000 ((caddr_t)dpd - (caddr_t)sc->sc_dpd), 1001 sizeof (struct ex_dpd), 1002 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1003 1004 /* 1005 * No need to stall the download engine, we know it's 1006 * not busy right now. 1007 * 1008 * Fix up pointers in both the "soft" tx and the physical 1009 * tx list. 1010 */ 1011 if (sc->tx_head != NULL) { 1012 prevdpd = sc->tx_tail->tx_dpd; 1013 offset = ((caddr_t)prevdpd - (caddr_t)sc->sc_dpd); 1014 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap, 1015 offset, sizeof (struct ex_dpd), 1016 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1017 prevdpd->dpd_nextptr = DPD_DMADDR(sc, txp); 1018 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap, 1019 offset, sizeof (struct ex_dpd), 1020 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1021 sc->tx_tail->tx_next = txp; 1022 sc->tx_tail = txp; 1023 } else { 1024 sc->tx_tail = sc->tx_head = txp; 1025 } 1026 1027 #if NBPFILTER > 0 1028 /* 1029 * Pass packet to bpf if there is a listener. 1030 */ 1031 if (ifp->if_bpf) 1032 bpf_mtap(ifp->if_bpf, mb_head); 1033 #endif 1034 } 1035 out: 1036 if (sc->tx_head) { 1037 sc->tx_tail->tx_dpd->dpd_fsh |= EX_DPD_DNIND; 1038 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap, 1039 ((caddr_t)sc->tx_tail->tx_dpd - (caddr_t)sc->sc_dpd), 1040 sizeof (struct ex_dpd), 1041 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1042 ifp->if_flags |= IFF_OACTIVE; 1043 bus_space_write_2(iot, ioh, ELINK_COMMAND, ELINK_DNUNSTALL); 1044 bus_space_write_4(iot, ioh, ELINK_DNLISTPTR, 1045 DPD_DMADDR(sc, sc->tx_head)); 1046 1047 /* trigger watchdog */ 1048 ifp->if_timer = 5; 1049 } 1050 } 1051 1052 1053 int 1054 ex_intr(arg) 1055 void *arg; 1056 { 1057 struct ex_softc *sc = arg; 1058 bus_space_tag_t iot = sc->sc_iot; 1059 bus_space_handle_t ioh = sc->sc_ioh; 1060 u_int16_t stat; 1061 int ret = 0; 1062 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1063 1064 for (;;) { 1065 stat = bus_space_read_2(iot, ioh, ELINK_STATUS); 1066 if (!(stat & S_MASK)) 1067 break; 1068 /* 1069 * Acknowledge interrupts. 1070 */ 1071 bus_space_write_2(iot, ioh, ELINK_COMMAND, ACK_INTR | 1072 (stat & S_MASK)); 1073 ret = 1; 1074 if (stat & S_HOST_ERROR) { 1075 printf("%s: adapter failure (%x)\n", 1076 sc->sc_dev.dv_xname, stat); 1077 bus_space_write_2(iot, ioh, ELINK_COMMAND, 1078 C_INTR_LATCH); 1079 ex_reset(sc); 1080 ex_init(sc); 1081 return 1; 1082 } 1083 if (stat & S_TX_COMPLETE) { 1084 ex_txstat(sc); 1085 } 1086 if (stat & S_UPD_STATS) { 1087 ex_getstats(sc); 1088 } 1089 if (stat & S_DN_COMPLETE) { 1090 struct ex_txdesc *txp, *ptxp = NULL; 1091 bus_dmamap_t txmap; 1092 1093 /* reset watchdog timer, was set in ex_start() */ 1094 ifp->if_timer = 0; 1095 1096 for (txp = sc->tx_head; txp != NULL; 1097 txp = txp->tx_next) { 1098 bus_dmamap_sync(sc->sc_dmat, 1099 sc->sc_dpd_dmamap, 1100 (caddr_t)txp->tx_dpd - (caddr_t)sc->sc_dpd, 1101 sizeof (struct ex_dpd), 1102 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1103 if (txp->tx_mbhead != NULL) { 1104 txmap = txp->tx_dmamap; 1105 bus_dmamap_sync(sc->sc_dmat, txmap, 1106 0, txmap->dm_mapsize, 1107 BUS_DMASYNC_POSTWRITE); 1108 bus_dmamap_unload(sc->sc_dmat, txmap); 1109 m_freem(txp->tx_mbhead); 1110 txp->tx_mbhead = NULL; 1111 } 1112 ptxp = txp; 1113 } 1114 1115 /* 1116 * Move finished tx buffers back to the tx free list. 1117 */ 1118 if (sc->tx_free) { 1119 sc->tx_ftail->tx_next = sc->tx_head; 1120 sc->tx_ftail = ptxp; 1121 } else 1122 sc->tx_ftail = sc->tx_free = sc->tx_head; 1123 1124 sc->tx_head = sc->tx_tail = NULL; 1125 ifp->if_flags &= ~IFF_OACTIVE; 1126 } 1127 1128 if (stat & S_UP_COMPLETE) { 1129 struct ex_rxdesc *rxd; 1130 struct mbuf *m; 1131 struct ex_upd *upd; 1132 bus_dmamap_t rxmap; 1133 u_int32_t pktstat; 1134 1135 rcvloop: 1136 rxd = sc->rx_head; 1137 rxmap = rxd->rx_dmamap; 1138 m = rxd->rx_mbhead; 1139 upd = rxd->rx_upd; 1140 pktstat = upd->upd_pktstatus; 1141 1142 bus_dmamap_sync(sc->sc_dmat, rxmap, 0, 1143 rxmap->dm_mapsize, 1144 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1145 bus_dmamap_sync(sc->sc_dmat, sc->sc_upd_dmamap, 1146 ((caddr_t)upd - (caddr_t)sc->sc_upd), 1147 sizeof (struct ex_upd), 1148 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1149 1150 if (pktstat & EX_UPD_COMPLETE) { 1151 /* 1152 * Remove first packet from the chain. 1153 */ 1154 sc->rx_head = rxd->rx_next; 1155 rxd->rx_next = NULL; 1156 1157 /* 1158 * Add a new buffer to the receive chain. 1159 * If this fails, the old buffer is recycled 1160 * instead. 1161 */ 1162 if (ex_add_rxbuf(sc, rxd) == 0) { 1163 struct ether_header *eh; 1164 u_int16_t total_len; 1165 1166 1167 if (pktstat & EX_UPD_ERR) { 1168 ifp->if_ierrors++; 1169 m_freem(m); 1170 goto rcvloop; 1171 } 1172 1173 total_len = pktstat & EX_UPD_PKTLENMASK; 1174 if (total_len < 1175 sizeof(struct ether_header)) { 1176 m_freem(m); 1177 goto rcvloop; 1178 } 1179 m->m_pkthdr.rcvif = ifp; 1180 m->m_pkthdr.len = m->m_len = 1181 total_len - 1182 sizeof(struct ether_header); 1183 eh = mtod(m, struct ether_header *); 1184 #if NBPFILTER > 0 1185 if (ifp->if_bpf) { 1186 bpf_tap(ifp->if_bpf, 1187 mtod(m, caddr_t), 1188 total_len); 1189 /* 1190 * Only pass this packet up 1191 * if it is for us. 1192 */ 1193 if ((ifp->if_flags & 1194 IFF_PROMISC) && 1195 (eh->ether_dhost[0] & 1) 1196 == 0 && 1197 bcmp(eh->ether_dhost, 1198 LLADDR(ifp->if_sadl), 1199 sizeof(eh->ether_dhost)) 1200 != 0) { 1201 m_freem(m); 1202 goto rcvloop; 1203 } 1204 } 1205 #endif /* NBPFILTER > 0 */ 1206 m->m_data += 1207 sizeof(struct ether_header); 1208 ether_input(ifp, eh, m); 1209 } 1210 goto rcvloop; 1211 } 1212 /* 1213 * Just in case we filled up all UPDs and the DMA engine 1214 * stalled. We could be more subtle about this. 1215 */ 1216 if (bus_space_read_4(iot, ioh, ELINK_UPLISTPTR) == 0) { 1217 printf("%s: uplistptr was 0\n", 1218 sc->sc_dev.dv_xname); 1219 ex_init(sc); 1220 } else if (bus_space_read_4(iot, ioh, ELINK_UPPKTSTATUS) 1221 & 0x2000) { 1222 printf("%s: receive stalled\n", 1223 sc->sc_dev.dv_xname); 1224 bus_space_write_2(iot, ioh, ELINK_COMMAND, 1225 ELINK_UPUNSTALL); 1226 } 1227 } 1228 } 1229 if (ret) { 1230 bus_space_write_2(iot, ioh, ELINK_COMMAND, C_INTR_LATCH); 1231 if (ifp->if_snd.ifq_head != NULL) 1232 ex_start(ifp); 1233 } 1234 return ret; 1235 } 1236 1237 int 1238 ex_ioctl(ifp, cmd, data) 1239 register struct ifnet *ifp; 1240 u_long cmd; 1241 caddr_t data; 1242 { 1243 struct ex_softc *sc = ifp->if_softc; 1244 struct ifaddr *ifa = (struct ifaddr *)data; 1245 struct ifreq *ifr = (struct ifreq *)data; 1246 int s, error = 0; 1247 1248 s = splnet(); 1249 1250 switch (cmd) { 1251 1252 case SIOCSIFADDR: 1253 ifp->if_flags |= IFF_UP; 1254 switch (ifa->ifa_addr->sa_family) { 1255 #ifdef INET 1256 case AF_INET: 1257 ex_init(sc); 1258 arp_ifinit(&sc->sc_ethercom.ec_if, ifa); 1259 break; 1260 #endif 1261 #ifdef NS 1262 case AF_NS: 1263 { 1264 register struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1265 1266 if (ns_nullhost(*ina)) 1267 ina->x_host = *(union ns_host *) 1268 LLADDR(ifp->if_sadl); 1269 else 1270 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 1271 ifp->if_addrlen); 1272 /* Set new address. */ 1273 ex_init(sc); 1274 break; 1275 } 1276 #endif 1277 default: 1278 ex_init(sc); 1279 break; 1280 } 1281 break; 1282 case SIOCSIFMEDIA: 1283 case SIOCGIFMEDIA: 1284 error = ifmedia_ioctl(ifp, ifr, &sc->ex_mii.mii_media, cmd); 1285 break; 1286 1287 case SIOCSIFFLAGS: 1288 if ((ifp->if_flags & IFF_UP) == 0 && 1289 (ifp->if_flags & IFF_RUNNING) != 0) { 1290 /* 1291 * If interface is marked down and it is running, then 1292 * stop it. 1293 */ 1294 ex_stop(sc); 1295 ifp->if_flags &= ~IFF_RUNNING; 1296 } else if ((ifp->if_flags & IFF_UP) != 0 && 1297 (ifp->if_flags & IFF_RUNNING) == 0) { 1298 /* 1299 * If interface is marked up and it is stopped, then 1300 * start it. 1301 */ 1302 ex_init(sc); 1303 } else if ((ifp->if_flags & IFF_UP) != 0) { 1304 /* 1305 * Deal with other flags that change hardware 1306 * state, i.e. IFF_PROMISC. 1307 */ 1308 ex_set_mc(sc); 1309 } 1310 break; 1311 1312 case SIOCADDMULTI: 1313 case SIOCDELMULTI: 1314 error = (cmd == SIOCADDMULTI) ? 1315 ether_addmulti(ifr, &sc->sc_ethercom) : 1316 ether_delmulti(ifr, &sc->sc_ethercom); 1317 1318 if (error == ENETRESET) { 1319 /* 1320 * Multicast list has changed; set the hardware filter 1321 * accordingly. 1322 */ 1323 ex_set_mc(sc); 1324 error = 0; 1325 } 1326 break; 1327 1328 default: 1329 error = EINVAL; 1330 break; 1331 } 1332 1333 splx(s); 1334 return (error); 1335 } 1336 1337 void 1338 ex_getstats(sc) 1339 struct ex_softc *sc; 1340 { 1341 bus_space_handle_t ioh = sc->sc_ioh; 1342 bus_space_tag_t iot = sc->sc_iot; 1343 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1344 u_int8_t upperok; 1345 1346 GO_WINDOW(6); 1347 upperok = bus_space_read_1(iot, ioh, UPPER_FRAMES_OK); 1348 ifp->if_ipackets += bus_space_read_1(iot, ioh, RX_FRAMES_OK); 1349 ifp->if_ipackets += (upperok & 0x03) << 8; 1350 ifp->if_opackets += bus_space_read_1(iot, ioh, TX_FRAMES_OK); 1351 ifp->if_opackets += (upperok & 0x30) << 4; 1352 ifp->if_ierrors += bus_space_read_1(iot, ioh, RX_OVERRUNS); 1353 ifp->if_oerrors += bus_space_read_1(iot, ioh, TX_DEFERRALS); 1354 ifp->if_collisions += bus_space_read_1(iot, ioh, TX_COLLISIONS); 1355 /* 1356 * There seems to be no way to get the exact number of collisions, 1357 * this is the number that occured at the very least. 1358 */ 1359 ifp->if_collisions += 2 * bus_space_read_1(iot, ioh, 1360 TX_AFTER_X_COLLISIONS); 1361 ifp->if_ibytes += bus_space_read_2(iot, ioh, RX_TOTAL_OK); 1362 ifp->if_obytes += bus_space_read_2(iot, ioh, TX_TOTAL_OK); 1363 1364 /* 1365 * Clear the following to avoid stats overflow interrupts 1366 */ 1367 bus_space_read_1(iot, ioh, TX_AFTER_1_COLLISION); 1368 bus_space_read_1(iot, ioh, TX_NO_SQE); 1369 bus_space_read_1(iot, ioh, TX_CD_LOST); 1370 GO_WINDOW(4); 1371 bus_space_read_1(iot, ioh, ELINK_W4_BADSSD); 1372 upperok = bus_space_read_1(iot, ioh, ELINK_W4_UBYTESOK); 1373 ifp->if_ibytes += (upperok & 0x0f) << 16; 1374 ifp->if_obytes += (upperok & 0xf0) << 12; 1375 GO_WINDOW(1); 1376 } 1377 1378 void 1379 ex_printstats(sc) 1380 struct ex_softc *sc; 1381 { 1382 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1383 1384 ex_getstats(sc); 1385 printf("in %ld out %ld ierror %ld oerror %ld ibytes %ld obytes %ld\n", 1386 ifp->if_ipackets, ifp->if_opackets, ifp->if_ierrors, 1387 ifp->if_oerrors, ifp->if_ibytes, ifp->if_obytes); 1388 } 1389 1390 void 1391 ex_tick(arg) 1392 void *arg; 1393 { 1394 struct ex_softc *sc = arg; 1395 int s = splnet(); 1396 1397 if (sc->ex_conf & EX_CONF_MII) 1398 mii_tick(&sc->ex_mii); 1399 1400 if (!(bus_space_read_2((sc)->sc_iot, (sc)->sc_ioh, ELINK_STATUS) 1401 & S_COMMAND_IN_PROGRESS)) 1402 ex_getstats(sc); 1403 1404 splx(s); 1405 1406 timeout(ex_tick, sc, hz); 1407 } 1408 1409 1410 void 1411 ex_reset(sc) 1412 struct ex_softc *sc; 1413 { 1414 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_COMMAND, GLOBAL_RESET); 1415 ex_waitcmd(sc); 1416 } 1417 1418 void 1419 ex_watchdog(ifp) 1420 struct ifnet *ifp; 1421 { 1422 struct ex_softc *sc = ifp->if_softc; 1423 1424 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1425 ++sc->sc_ethercom.ec_if.if_oerrors; 1426 1427 ex_reset(sc); 1428 ex_init(sc); 1429 } 1430 1431 void 1432 ex_stop(sc) 1433 struct ex_softc *sc; 1434 { 1435 bus_space_tag_t iot = sc->sc_iot; 1436 bus_space_handle_t ioh = sc->sc_ioh; 1437 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1438 struct ex_txdesc *tx; 1439 struct ex_rxdesc *rx; 1440 int i; 1441 1442 bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_DISABLE); 1443 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_DISABLE); 1444 bus_space_write_2(iot, ioh, ELINK_COMMAND, STOP_TRANSCEIVER); 1445 1446 for (tx = sc->tx_head ; tx != NULL; tx = tx->tx_next) { 1447 if (tx->tx_mbhead == NULL) 1448 continue; 1449 m_freem(tx->tx_mbhead); 1450 tx->tx_mbhead = NULL; 1451 bus_dmamap_unload(sc->sc_dmat, tx->tx_dmamap); 1452 tx->tx_dpd->dpd_fsh = tx->tx_dpd->dpd_nextptr = 0; 1453 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap, 1454 ((caddr_t)tx->tx_dpd - (caddr_t)sc->sc_dpd), 1455 sizeof (struct ex_dpd), 1456 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1457 } 1458 sc->tx_tail = sc->tx_head = NULL; 1459 ex_init_txdescs(sc); 1460 1461 sc->rx_tail = sc->rx_head = 0; 1462 for (i = 0; i < EX_NUPD; i++) { 1463 rx = &sc->sc_rxdescs[i]; 1464 if (rx->rx_mbhead != NULL) { 1465 bus_dmamap_unload(sc->sc_dmat, rx->rx_dmamap); 1466 m_freem(rx->rx_mbhead); 1467 rx->rx_mbhead = NULL; 1468 } 1469 ex_add_rxbuf(sc, rx); 1470 } 1471 1472 bus_space_write_2(iot, ioh, ELINK_COMMAND, C_INTR_LATCH); 1473 1474 untimeout(ex_tick, sc); 1475 1476 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1477 ifp->if_timer = 0; 1478 } 1479 1480 static void 1481 ex_init_txdescs(sc) 1482 struct ex_softc *sc; 1483 { 1484 int i; 1485 1486 for (i = 0; i < EX_NDPD; i++) { 1487 sc->sc_txdescs[i].tx_dmamap = sc->sc_tx_dmamaps[i]; 1488 sc->sc_txdescs[i].tx_dpd = &sc->sc_dpd[i]; 1489 if (i < EX_NDPD - 1) 1490 sc->sc_txdescs[i].tx_next = &sc->sc_txdescs[i + 1]; 1491 else 1492 sc->sc_txdescs[i].tx_next = NULL; 1493 } 1494 sc->tx_free = &sc->sc_txdescs[0]; 1495 sc->tx_ftail = &sc->sc_txdescs[EX_NDPD-1]; 1496 } 1497 1498 1499 /* 1500 * Before reboots, reset card completely. 1501 */ 1502 static void 1503 ex_shutdown(arg) 1504 void *arg; 1505 { 1506 register struct ex_softc *sc = arg; 1507 1508 ex_stop(sc); 1509 } 1510 1511 /* 1512 * Read EEPROM data. 1513 * XXX what to do if EEPROM doesn't unbusy? 1514 */ 1515 u_int16_t 1516 ex_read_eeprom(sc, offset) 1517 struct ex_softc *sc; 1518 int offset; 1519 { 1520 bus_space_tag_t iot = sc->sc_iot; 1521 bus_space_handle_t ioh = sc->sc_ioh; 1522 u_int16_t data = 0; 1523 1524 GO_WINDOW(0); 1525 if (ex_eeprom_busy(sc)) 1526 goto out; 1527 bus_space_write_1(iot, ioh, ELINK_W0_EEPROM_COMMAND, 1528 READ_EEPROM | (offset & 0x3f)); 1529 if (ex_eeprom_busy(sc)) 1530 goto out; 1531 data = bus_space_read_2(iot, ioh, ELINK_W0_EEPROM_DATA); 1532 out: 1533 return data; 1534 } 1535 1536 static int 1537 ex_eeprom_busy(sc) 1538 struct ex_softc *sc; 1539 { 1540 bus_space_tag_t iot = sc->sc_iot; 1541 bus_space_handle_t ioh = sc->sc_ioh; 1542 int i = 100; 1543 1544 while (i--) { 1545 if (!(bus_space_read_2(iot, ioh, ELINK_W0_EEPROM_COMMAND) & 1546 EEPROM_BUSY)) 1547 return 0; 1548 delay(100); 1549 } 1550 printf("\n%s: eeprom stays busy.\n", sc->sc_dev.dv_xname); 1551 return (1); 1552 } 1553 1554 /* 1555 * Create a new rx buffer and add it to the 'soft' rx list. 1556 */ 1557 static int 1558 ex_add_rxbuf(sc, rxd) 1559 struct ex_softc *sc; 1560 struct ex_rxdesc *rxd; 1561 { 1562 struct mbuf *m, *oldm; 1563 bus_dmamap_t rxmap; 1564 int error, rval = 0; 1565 1566 oldm = rxd->rx_mbhead; 1567 rxmap = rxd->rx_dmamap; 1568 1569 MGETHDR(m, M_DONTWAIT, MT_DATA); 1570 if (m != NULL) { 1571 MCLGET(m, M_DONTWAIT); 1572 if ((m->m_flags & M_EXT) == 0) { 1573 m_freem(m); 1574 if (oldm == NULL) 1575 return 1; 1576 m = oldm; 1577 m->m_data = m->m_ext.ext_buf; 1578 rval = 1; 1579 } 1580 } else { 1581 if (oldm == NULL) 1582 return 1; 1583 m = oldm; 1584 m->m_data = m->m_ext.ext_buf; 1585 rval = 1; 1586 } 1587 1588 /* 1589 * Setup the DMA map for this receive buffer. 1590 */ 1591 if (m != oldm) { 1592 if (oldm != NULL) 1593 bus_dmamap_unload(sc->sc_dmat, rxmap); 1594 error = bus_dmamap_load(sc->sc_dmat, rxmap, 1595 m->m_ext.ext_buf, MCLBYTES, NULL, BUS_DMA_NOWAIT); 1596 if (error) { 1597 printf("%s: can't load rx buffer, error = %d\n", 1598 sc->sc_dev.dv_xname, error); 1599 panic("ex_add_rxbuf"); /* XXX */ 1600 } 1601 } 1602 1603 /* 1604 * Align for data after 14 byte header. 1605 */ 1606 m->m_data += 2; 1607 1608 rxd->rx_mbhead = m; 1609 rxd->rx_upd->upd_pktstatus = MCLBYTES - 2; 1610 rxd->rx_upd->upd_frags[0].fr_addr = rxmap->dm_segs[0].ds_addr + 2; 1611 rxd->rx_upd->upd_nextptr = 0; 1612 1613 /* 1614 * Attach it to the end of the list. 1615 */ 1616 if (sc->rx_head != NULL) { 1617 sc->rx_tail->rx_next = rxd; 1618 sc->rx_tail->rx_upd->upd_nextptr = sc->sc_upddma + 1619 ((caddr_t)rxd->rx_upd - (caddr_t)sc->sc_upd); 1620 bus_dmamap_sync(sc->sc_dmat, sc->sc_upd_dmamap, 1621 (caddr_t)sc->rx_tail->rx_upd - (caddr_t)sc->sc_upd, 1622 sizeof (struct ex_upd), 1623 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1624 } else { 1625 sc->rx_head = rxd; 1626 } 1627 sc->rx_tail = rxd; 1628 1629 bus_dmamap_sync(sc->sc_dmat, rxmap, 0, rxmap->dm_mapsize, 1630 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1631 bus_dmamap_sync(sc->sc_dmat, sc->sc_upd_dmamap, 1632 ((caddr_t)rxd->rx_upd - (caddr_t)sc->sc_upd), 1633 sizeof (struct ex_upd), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1634 return (rval); 1635 } 1636 1637 void 1638 ex_mii_setbit(v, bit) 1639 void *v; 1640 u_int16_t bit; 1641 { 1642 struct ex_softc *sc = v; 1643 u_int16_t val; 1644 1645 val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_PHYSMGMT); 1646 val |= bit; 1647 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_PHYSMGMT, val); 1648 } 1649 1650 void 1651 ex_mii_clrbit(v, bit) 1652 void *v; 1653 u_int16_t bit; 1654 { 1655 struct ex_softc *sc = v; 1656 u_int16_t val; 1657 1658 val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_PHYSMGMT); 1659 val &= ~bit; 1660 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_PHYSMGMT, val); 1661 } 1662 1663 u_int16_t 1664 ex_mii_readbit(v, bit) 1665 void *v; 1666 u_int16_t bit; 1667 { 1668 struct ex_softc *sc = v; 1669 u_int16_t val; 1670 1671 val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_PHYSMGMT); 1672 return (val & bit); 1673 } 1674 1675 /* 1676 * The reason why all this stuff below is here, is that we need a special 1677 * readreg function. It needs to check if we're accessing the internal 1678 * PHY on 905B-TX boards, or not. If so, the read must fail immediately, 1679 * because 905B-TX boards seem to return garbage from the MII if you 1680 * try to access non-existing PHYs. 1681 */ 1682 1683 int 1684 ex_mii_readreg(v, phy, reg) 1685 struct device *v; 1686 int phy; 1687 int reg; 1688 { 1689 struct ex_softc *sc = (struct ex_softc *)v; 1690 int val = 0; 1691 int err =0; 1692 int i; 1693 1694 if ((sc->ex_conf & EX_CONF_INTPHY) && phy != ELINK_INTPHY_ID) 1695 return 0; 1696 1697 GO_WINDOW(4); 1698 1699 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_PHYSMGMT, 0); 1700 1701 ex_mii_clrbit(sc, ELINK_PHY_DIR); 1702 for (i = 0; i < 32; i++) { 1703 ex_mii_clrbit(sc, ELINK_PHY_CLK); 1704 ex_mii_setbit(sc, ELINK_PHY_CLK); 1705 } 1706 ex_mii_writebits(sc, MII_COMMAND_START, 2); 1707 ex_mii_writebits(sc, MII_COMMAND_READ, 2); 1708 ex_mii_writebits(sc, phy, 5); 1709 ex_mii_writebits(sc, reg, 5); 1710 1711 ex_mii_clrbit(sc, ELINK_PHY_DIR); 1712 ex_mii_clrbit(sc, ELINK_PHY_CLK); 1713 ex_mii_setbit(sc, ELINK_PHY_CLK); 1714 ex_mii_clrbit(sc, ELINK_PHY_CLK); 1715 1716 err = ex_mii_readbit(sc, ELINK_PHY_DATA); 1717 ex_mii_setbit(sc, ELINK_PHY_CLK); 1718 1719 for (i = 0; i < 16; i++) { 1720 val <<= 1; 1721 ex_mii_clrbit(sc, ELINK_PHY_CLK); 1722 if (err == 0 && ex_mii_readbit(sc, ELINK_PHY_DATA)) 1723 val |= 1; 1724 ex_mii_setbit(sc, ELINK_PHY_CLK); 1725 } 1726 ex_mii_clrbit(sc, ELINK_PHY_CLK); 1727 ex_mii_setbit(sc, ELINK_PHY_CLK); 1728 1729 GO_WINDOW(1); 1730 1731 return (err ? 0 : val); 1732 } 1733 1734 static void 1735 ex_mii_writebits(sc, data, nbits) 1736 struct ex_softc *sc; 1737 unsigned int data; 1738 int nbits; 1739 { 1740 int i; 1741 1742 ex_mii_setbit(sc, ELINK_PHY_DIR); 1743 for (i = 1 << (nbits -1); i; i = i >> 1) { 1744 ex_mii_clrbit(sc, ELINK_PHY_CLK); 1745 ex_mii_readbit(sc, ELINK_PHY_CLK); 1746 if (data & i) 1747 ex_mii_setbit(sc, ELINK_PHY_DATA); 1748 else 1749 ex_mii_clrbit(sc, ELINK_PHY_DATA); 1750 ex_mii_setbit(sc, ELINK_PHY_CLK); 1751 ex_mii_readbit(sc, ELINK_PHY_CLK); 1752 } 1753 } 1754 1755 void 1756 ex_mii_writereg(v, phy, reg, data) 1757 struct device *v; 1758 int phy; 1759 int reg; 1760 int data; 1761 { 1762 struct ex_softc *sc = (struct ex_softc *)v; 1763 int i; 1764 1765 GO_WINDOW(4); 1766 1767 ex_mii_clrbit(sc, ELINK_PHY_DIR); 1768 for (i = 0; i < 32; i++) { 1769 ex_mii_clrbit(sc, ELINK_PHY_CLK); 1770 ex_mii_setbit(sc, ELINK_PHY_CLK); 1771 } 1772 ex_mii_writebits(sc, MII_COMMAND_START, 2); 1773 ex_mii_writebits(sc, MII_COMMAND_WRITE, 2); 1774 ex_mii_writebits(sc, phy, 5); 1775 ex_mii_writebits(sc, reg, 5); 1776 ex_mii_writebits(sc, MII_COMMAND_ACK, 2); 1777 ex_mii_writebits(sc, data, 16); 1778 1779 ex_mii_clrbit(sc, ELINK_PHY_CLK); 1780 ex_mii_setbit(sc, ELINK_PHY_CLK); 1781 1782 GO_WINDOW(1); 1783 } 1784 1785 void 1786 ex_mii_statchg(v) 1787 struct device *v; 1788 { 1789 struct ex_softc *sc = (struct ex_softc *)v; 1790 bus_space_tag_t iot = sc->sc_iot; 1791 bus_space_handle_t ioh = sc->sc_ioh; 1792 int mctl; 1793 1794 /* XXX Update ifp->if_baudrate */ 1795 1796 GO_WINDOW(3); 1797 mctl = bus_space_read_2(iot, ioh, ELINK_W3_MAC_CONTROL); 1798 if (sc->ex_mii.mii_media_active & IFM_FDX) 1799 mctl |= MAC_CONTROL_FDX; 1800 else 1801 mctl &= ~MAC_CONTROL_FDX; 1802 bus_space_write_2(iot, ioh, ELINK_W3_MAC_CONTROL, mctl); 1803 GO_WINDOW(1); /* back to operating window */ 1804 } 1805
Indexes created Wed Oct 22 13:09:56 GMT 2025