elinkxl.c revision 1.57
1 /* $NetBSD: elinkxl.c,v 1.57 2001/10/01 09:26:29 yamt Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include "bpfilter.h" 40 #include "rnd.h" 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/callout.h> 45 #include <sys/kernel.h> 46 #include <sys/mbuf.h> 47 #include <sys/socket.h> 48 #include <sys/ioctl.h> 49 #include <sys/errno.h> 50 #include <sys/syslog.h> 51 #include <sys/select.h> 52 #include <sys/device.h> 53 #if NRND > 0 54 #include <sys/rnd.h> 55 #endif 56 57 #include <uvm/uvm_extern.h> 58 59 #include <net/if.h> 60 #include <net/if_dl.h> 61 #include <net/if_ether.h> 62 #include <net/if_media.h> 63 64 #if NBPFILTER > 0 65 #include <net/bpf.h> 66 #include <net/bpfdesc.h> 67 #endif 68 69 #include <machine/cpu.h> 70 #include <machine/bus.h> 71 #include <machine/intr.h> 72 #include <machine/endian.h> 73 74 #include <dev/mii/miivar.h> 75 #include <dev/mii/mii.h> 76 #include <dev/mii/mii_bitbang.h> 77 78 #include <dev/ic/elink3reg.h> 79 /* #include <dev/ic/elink3var.h> */ 80 #include <dev/ic/elinkxlreg.h> 81 #include <dev/ic/elinkxlvar.h> 82 83 #ifdef DEBUG 84 int exdebug = 0; 85 #endif 86 87 /* ifmedia callbacks */ 88 int ex_media_chg __P((struct ifnet *ifp)); 89 void ex_media_stat __P((struct ifnet *ifp, struct ifmediareq *req)); 90 91 void ex_probe_media __P((struct ex_softc *)); 92 void ex_set_filter __P((struct ex_softc *)); 93 void ex_set_media __P((struct ex_softc *)); 94 struct mbuf *ex_get __P((struct ex_softc *, int)); 95 u_int16_t ex_read_eeprom __P((struct ex_softc *, int)); 96 int ex_init __P((struct ifnet *)); 97 void ex_read __P((struct ex_softc *)); 98 void ex_reset __P((struct ex_softc *)); 99 void ex_set_mc __P((struct ex_softc *)); 100 void ex_getstats __P((struct ex_softc *)); 101 void ex_printstats __P((struct ex_softc *)); 102 void ex_tick __P((void *)); 103 104 int ex_enable __P((struct ex_softc *)); 105 void ex_disable __P((struct ex_softc *)); 106 void ex_power __P((int, void *)); 107 108 static int ex_eeprom_busy __P((struct ex_softc *)); 109 static int ex_add_rxbuf __P((struct ex_softc *, struct ex_rxdesc *)); 110 static void ex_init_txdescs __P((struct ex_softc *)); 111 112 static void ex_shutdown __P((void *)); 113 static void ex_start __P((struct ifnet *)); 114 static void ex_txstat __P((struct ex_softc *)); 115 116 int ex_mii_readreg __P((struct device *, int, int)); 117 void ex_mii_writereg __P((struct device *, int, int, int)); 118 void ex_mii_statchg __P((struct device *)); 119 120 void ex_probemedia __P((struct ex_softc *)); 121 122 /* 123 * Structure to map media-present bits in boards to ifmedia codes and 124 * printable media names. Used for table-driven ifmedia initialization. 125 */ 126 struct ex_media { 127 int exm_mpbit; /* media present bit */ 128 const char *exm_name; /* name of medium */ 129 int exm_ifmedia; /* ifmedia word for medium */ 130 int exm_epmedia; /* ELINKMEDIA_* constant */ 131 }; 132 133 /* 134 * Media table for 3c90x chips. Note that chips with MII have no 135 * `native' media. 136 */ 137 struct ex_media ex_native_media[] = { 138 { ELINK_PCI_10BASE_T, "10baseT", IFM_ETHER|IFM_10_T, 139 ELINKMEDIA_10BASE_T }, 140 { ELINK_PCI_10BASE_T, "10baseT-FDX", IFM_ETHER|IFM_10_T|IFM_FDX, 141 ELINKMEDIA_10BASE_T }, 142 { ELINK_PCI_AUI, "10base5", IFM_ETHER|IFM_10_5, 143 ELINKMEDIA_AUI }, 144 { ELINK_PCI_BNC, "10base2", IFM_ETHER|IFM_10_2, 145 ELINKMEDIA_10BASE_2 }, 146 { ELINK_PCI_100BASE_TX, "100baseTX", IFM_ETHER|IFM_100_TX, 147 ELINKMEDIA_100BASE_TX }, 148 { ELINK_PCI_100BASE_TX, "100baseTX-FDX",IFM_ETHER|IFM_100_TX|IFM_FDX, 149 ELINKMEDIA_100BASE_TX }, 150 { ELINK_PCI_100BASE_FX, "100baseFX", IFM_ETHER|IFM_100_FX, 151 ELINKMEDIA_100BASE_FX }, 152 { ELINK_PCI_100BASE_MII,"manual", IFM_ETHER|IFM_MANUAL, 153 ELINKMEDIA_MII }, 154 { ELINK_PCI_100BASE_T4, "100baseT4", IFM_ETHER|IFM_100_T4, 155 ELINKMEDIA_100BASE_T4 }, 156 { 0, NULL, 0, 157 0 }, 158 }; 159 160 /* 161 * MII bit-bang glue. 162 */ 163 u_int32_t ex_mii_bitbang_read __P((struct device *)); 164 void ex_mii_bitbang_write __P((struct device *, u_int32_t)); 165 166 const struct mii_bitbang_ops ex_mii_bitbang_ops = { 167 ex_mii_bitbang_read, 168 ex_mii_bitbang_write, 169 { 170 ELINK_PHY_DATA, /* MII_BIT_MDO */ 171 ELINK_PHY_DATA, /* MII_BIT_MDI */ 172 ELINK_PHY_CLK, /* MII_BIT_MDC */ 173 ELINK_PHY_DIR, /* MII_BIT_DIR_HOST_PHY */ 174 0, /* MII_BIT_DIR_PHY_HOST */ 175 } 176 }; 177 178 /* 179 * Back-end attach and configure. 180 */ 181 void 182 ex_config(sc) 183 struct ex_softc *sc; 184 { 185 struct ifnet *ifp; 186 u_int16_t val; 187 u_int8_t macaddr[ETHER_ADDR_LEN] = {0}; 188 bus_space_tag_t iot = sc->sc_iot; 189 bus_space_handle_t ioh = sc->sc_ioh; 190 int i, error, attach_stage; 191 192 callout_init(&sc->ex_mii_callout); 193 194 ex_reset(sc); 195 196 val = ex_read_eeprom(sc, EEPROM_OEM_ADDR0); 197 macaddr[0] = val >> 8; 198 macaddr[1] = val & 0xff; 199 val = ex_read_eeprom(sc, EEPROM_OEM_ADDR1); 200 macaddr[2] = val >> 8; 201 macaddr[3] = val & 0xff; 202 val = ex_read_eeprom(sc, EEPROM_OEM_ADDR2); 203 macaddr[4] = val >> 8; 204 macaddr[5] = val & 0xff; 205 206 printf("%s: MAC address %s\n", sc->sc_dev.dv_xname, 207 ether_sprintf(macaddr)); 208 209 if (sc->ex_conf & (EX_CONF_INV_LED_POLARITY|EX_CONF_PHY_POWER)) { 210 GO_WINDOW(2); 211 val = bus_space_read_2(iot, ioh, ELINK_W2_RESET_OPTIONS); 212 if (sc->ex_conf & EX_CONF_INV_LED_POLARITY) 213 val |= ELINK_RESET_OPT_LEDPOLAR; 214 if (sc->ex_conf & EX_CONF_PHY_POWER) 215 val |= ELINK_RESET_OPT_PHYPOWER; 216 bus_space_write_2(iot, ioh, ELINK_W2_RESET_OPTIONS, val); 217 } 218 219 attach_stage = 0; 220 221 /* 222 * Allocate the upload descriptors, and create and load the DMA 223 * map for them. 224 */ 225 if ((error = bus_dmamem_alloc(sc->sc_dmat, 226 EX_NUPD * sizeof (struct ex_upd), PAGE_SIZE, 0, &sc->sc_useg, 1, 227 &sc->sc_urseg, BUS_DMA_NOWAIT)) != 0) { 228 printf("%s: can't allocate upload descriptors, error = %d\n", 229 sc->sc_dev.dv_xname, error); 230 goto fail; 231 } 232 233 attach_stage = 1; 234 235 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_useg, sc->sc_urseg, 236 EX_NUPD * sizeof (struct ex_upd), (caddr_t *)&sc->sc_upd, 237 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 238 printf("%s: can't map upload descriptors, error = %d\n", 239 sc->sc_dev.dv_xname, error); 240 goto fail; 241 } 242 243 attach_stage = 2; 244 245 if ((error = bus_dmamap_create(sc->sc_dmat, 246 EX_NUPD * sizeof (struct ex_upd), 1, 247 EX_NUPD * sizeof (struct ex_upd), 0, BUS_DMA_NOWAIT, 248 &sc->sc_upd_dmamap)) != 0) { 249 printf("%s: can't create upload desc. DMA map, error = %d\n", 250 sc->sc_dev.dv_xname, error); 251 goto fail; 252 } 253 254 attach_stage = 3; 255 256 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_upd_dmamap, 257 sc->sc_upd, EX_NUPD * sizeof (struct ex_upd), NULL, 258 BUS_DMA_NOWAIT)) != 0) { 259 printf("%s: can't load upload desc. DMA map, error = %d\n", 260 sc->sc_dev.dv_xname, error); 261 goto fail; 262 } 263 264 attach_stage = 4; 265 266 /* 267 * Allocate the download descriptors, and create and load the DMA 268 * map for them. 269 */ 270 if ((error = bus_dmamem_alloc(sc->sc_dmat, 271 EX_NDPD * sizeof (struct ex_dpd), PAGE_SIZE, 0, &sc->sc_dseg, 1, 272 &sc->sc_drseg, BUS_DMA_NOWAIT)) != 0) { 273 printf("%s: can't allocate download descriptors, error = %d\n", 274 sc->sc_dev.dv_xname, error); 275 goto fail; 276 } 277 278 attach_stage = 5; 279 280 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dseg, sc->sc_drseg, 281 EX_NDPD * sizeof (struct ex_dpd), (caddr_t *)&sc->sc_dpd, 282 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 283 printf("%s: can't map download descriptors, error = %d\n", 284 sc->sc_dev.dv_xname, error); 285 goto fail; 286 } 287 memset(sc->sc_dpd, 0, EX_NDPD * sizeof (struct ex_dpd)); 288 289 attach_stage = 6; 290 291 if ((error = bus_dmamap_create(sc->sc_dmat, 292 EX_NDPD * sizeof (struct ex_dpd), 1, 293 EX_NDPD * sizeof (struct ex_dpd), 0, BUS_DMA_NOWAIT, 294 &sc->sc_dpd_dmamap)) != 0) { 295 printf("%s: can't create download desc. DMA map, error = %d\n", 296 sc->sc_dev.dv_xname, error); 297 goto fail; 298 } 299 300 attach_stage = 7; 301 302 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dpd_dmamap, 303 sc->sc_dpd, EX_NDPD * sizeof (struct ex_dpd), NULL, 304 BUS_DMA_NOWAIT)) != 0) { 305 printf("%s: can't load download desc. DMA map, error = %d\n", 306 sc->sc_dev.dv_xname, error); 307 goto fail; 308 } 309 310 attach_stage = 8; 311 312 313 /* 314 * Create the transmit buffer DMA maps. 315 */ 316 for (i = 0; i < EX_NDPD; i++) { 317 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 318 EX_NTFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 319 &sc->sc_tx_dmamaps[i])) != 0) { 320 printf("%s: can't create tx DMA map %d, error = %d\n", 321 sc->sc_dev.dv_xname, i, error); 322 goto fail; 323 } 324 } 325 326 attach_stage = 9; 327 328 /* 329 * Create the receive buffer DMA maps. 330 */ 331 for (i = 0; i < EX_NUPD; i++) { 332 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 333 EX_NRFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 334 &sc->sc_rx_dmamaps[i])) != 0) { 335 printf("%s: can't create rx DMA map %d, error = %d\n", 336 sc->sc_dev.dv_xname, i, error); 337 goto fail; 338 } 339 } 340 341 attach_stage = 10; 342 343 /* 344 * Create ring of upload descriptors, only once. The DMA engine 345 * will loop over this when receiving packets, stalling if it 346 * hits an UPD with a finished receive. 347 */ 348 for (i = 0; i < EX_NUPD; i++) { 349 sc->sc_rxdescs[i].rx_dmamap = sc->sc_rx_dmamaps[i]; 350 sc->sc_rxdescs[i].rx_upd = &sc->sc_upd[i]; 351 sc->sc_upd[i].upd_frags[0].fr_len = 352 htole32((MCLBYTES - 2) | EX_FR_LAST); 353 if (ex_add_rxbuf(sc, &sc->sc_rxdescs[i]) != 0) { 354 printf("%s: can't allocate or map rx buffers\n", 355 sc->sc_dev.dv_xname); 356 goto fail; 357 } 358 } 359 360 bus_dmamap_sync(sc->sc_dmat, sc->sc_upd_dmamap, 0, 361 EX_NUPD * sizeof (struct ex_upd), 362 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 363 364 ex_init_txdescs(sc); 365 366 attach_stage = 11; 367 368 369 GO_WINDOW(3); 370 val = bus_space_read_2(iot, ioh, ELINK_W3_RESET_OPTIONS); 371 if (val & ELINK_MEDIACAP_MII) 372 sc->ex_conf |= EX_CONF_MII; 373 374 ifp = &sc->sc_ethercom.ec_if; 375 376 /* 377 * Initialize our media structures and MII info. We'll 378 * probe the MII if we discover that we have one. 379 */ 380 sc->ex_mii.mii_ifp = ifp; 381 sc->ex_mii.mii_readreg = ex_mii_readreg; 382 sc->ex_mii.mii_writereg = ex_mii_writereg; 383 sc->ex_mii.mii_statchg = ex_mii_statchg; 384 ifmedia_init(&sc->ex_mii.mii_media, 0, ex_media_chg, 385 ex_media_stat); 386 387 if (sc->ex_conf & EX_CONF_MII) { 388 /* 389 * Find PHY, extract media information from it. 390 * First, select the right transceiver. 391 */ 392 u_int32_t icfg; 393 394 GO_WINDOW(3); 395 icfg = bus_space_read_4(iot, ioh, ELINK_W3_INTERNAL_CONFIG); 396 icfg &= ~(CONFIG_XCVR_SEL << 16); 397 if (val & (ELINK_MEDIACAP_MII | ELINK_MEDIACAP_100BASET4)) 398 icfg |= ELINKMEDIA_MII << (CONFIG_XCVR_SEL_SHIFT + 16); 399 if (val & ELINK_MEDIACAP_100BASETX) 400 icfg |= ELINKMEDIA_AUTO << (CONFIG_XCVR_SEL_SHIFT + 16); 401 if (val & ELINK_MEDIACAP_100BASEFX) 402 icfg |= ELINKMEDIA_100BASE_FX 403 << (CONFIG_XCVR_SEL_SHIFT + 16); 404 bus_space_write_4(iot, ioh, ELINK_W3_INTERNAL_CONFIG, icfg); 405 406 mii_attach(&sc->sc_dev, &sc->ex_mii, 0xffffffff, 407 MII_PHY_ANY, MII_OFFSET_ANY, 0); 408 if (LIST_FIRST(&sc->ex_mii.mii_phys) == NULL) { 409 ifmedia_add(&sc->ex_mii.mii_media, IFM_ETHER|IFM_NONE, 410 0, NULL); 411 ifmedia_set(&sc->ex_mii.mii_media, IFM_ETHER|IFM_NONE); 412 } else { 413 ifmedia_set(&sc->ex_mii.mii_media, IFM_ETHER|IFM_AUTO); 414 } 415 } else 416 ex_probemedia(sc); 417 418 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 419 ifp->if_softc = sc; 420 ifp->if_start = ex_start; 421 ifp->if_ioctl = ex_ioctl; 422 ifp->if_watchdog = ex_watchdog; 423 ifp->if_init = ex_init; 424 ifp->if_stop = ex_stop; 425 ifp->if_flags = 426 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 427 IFQ_SET_READY(&ifp->if_snd); 428 429 /* 430 * We can support 802.1Q VLAN-sized frames. 431 */ 432 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 433 434 /* 435 * The 3c90xB has hardware IPv4/TCPv4/UDPv4 checksum support. 436 */ 437 if (sc->ex_conf & EX_CONF_90XB) 438 sc->sc_ethercom.ec_if.if_capabilities |= IFCAP_CSUM_IPv4 | 439 IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 440 441 if_attach(ifp); 442 ether_ifattach(ifp, macaddr); 443 444 GO_WINDOW(1); 445 446 sc->tx_start_thresh = 20; 447 sc->tx_succ_ok = 0; 448 449 /* TODO: set queues to 0 */ 450 451 #if NRND > 0 452 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 453 RND_TYPE_NET, 0); 454 #endif 455 456 /* Establish callback to reset card when we reboot. */ 457 sc->sc_sdhook = shutdownhook_establish(ex_shutdown, sc); 458 if (sc->sc_sdhook == NULL) 459 printf("%s: WARNING: unable to establish shutdown hook\n", 460 sc->sc_dev.dv_xname); 461 462 /* Add a suspend hook to make sure we come back up after a resume. */ 463 sc->sc_powerhook = powerhook_establish(ex_power, sc); 464 if (sc->sc_powerhook == NULL) 465 printf("%s: WARNING: unable to establish power hook\n", 466 sc->sc_dev.dv_xname); 467 468 /* The attach is successful. */ 469 sc->ex_flags |= EX_FLAGS_ATTACHED; 470 return; 471 472 fail: 473 /* 474 * Free any resources we've allocated during the failed attach 475 * attempt. Do this in reverse order and fall though. 476 */ 477 switch (attach_stage) { 478 case 11: 479 { 480 struct ex_rxdesc *rxd; 481 482 for (i = 0; i < EX_NUPD; i++) { 483 rxd = &sc->sc_rxdescs[i]; 484 if (rxd->rx_mbhead != NULL) { 485 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 486 m_freem(rxd->rx_mbhead); 487 } 488 } 489 } 490 /* FALLTHROUGH */ 491 492 case 10: 493 for (i = 0; i < EX_NUPD; i++) 494 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rx_dmamaps[i]); 495 /* FALLTHROUGH */ 496 497 case 9: 498 for (i = 0; i < EX_NDPD; i++) 499 bus_dmamap_destroy(sc->sc_dmat, sc->sc_tx_dmamaps[i]); 500 /* FALLTHROUGH */ 501 case 8: 502 bus_dmamap_unload(sc->sc_dmat, sc->sc_dpd_dmamap); 503 /* FALLTHROUGH */ 504 505 case 7: 506 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dpd_dmamap); 507 /* FALLTHROUGH */ 508 509 case 6: 510 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_dpd, 511 EX_NDPD * sizeof (struct ex_dpd)); 512 /* FALLTHROUGH */ 513 514 case 5: 515 bus_dmamem_free(sc->sc_dmat, &sc->sc_dseg, sc->sc_drseg); 516 break; 517 518 case 4: 519 bus_dmamap_unload(sc->sc_dmat, sc->sc_upd_dmamap); 520 /* FALLTHROUGH */ 521 522 case 3: 523 bus_dmamap_destroy(sc->sc_dmat, sc->sc_upd_dmamap); 524 /* FALLTHROUGH */ 525 526 case 2: 527 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_upd, 528 EX_NUPD * sizeof (struct ex_upd)); 529 /* FALLTHROUGH */ 530 531 case 1: 532 bus_dmamem_free(sc->sc_dmat, &sc->sc_useg, sc->sc_urseg); 533 break; 534 } 535 536 } 537 538 /* 539 * Find the media present on non-MII chips. 540 */ 541 void 542 ex_probemedia(sc) 543 struct ex_softc *sc; 544 { 545 bus_space_tag_t iot = sc->sc_iot; 546 bus_space_handle_t ioh = sc->sc_ioh; 547 struct ifmedia *ifm = &sc->ex_mii.mii_media; 548 struct ex_media *exm; 549 u_int16_t config1, reset_options, default_media; 550 int defmedia = 0; 551 const char *sep = "", *defmedianame = NULL; 552 553 GO_WINDOW(3); 554 config1 = bus_space_read_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG + 2); 555 reset_options = bus_space_read_1(iot, ioh, ELINK_W3_RESET_OPTIONS); 556 GO_WINDOW(0); 557 558 default_media = (config1 & CONFIG_MEDIAMASK) >> CONFIG_MEDIAMASK_SHIFT; 559 560 printf("%s: ", sc->sc_dev.dv_xname); 561 562 /* Sanity check that there are any media! */ 563 if ((reset_options & ELINK_PCI_MEDIAMASK) == 0) { 564 printf("no media present!\n"); 565 ifmedia_add(ifm, IFM_ETHER|IFM_NONE, 0, NULL); 566 ifmedia_set(ifm, IFM_ETHER|IFM_NONE); 567 return; 568 } 569 570 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 571 572 for (exm = ex_native_media; exm->exm_name != NULL; exm++) { 573 if (reset_options & exm->exm_mpbit) { 574 /* 575 * Default media is a little complicated. We 576 * support full-duplex which uses the same 577 * reset options bit. 578 * 579 * XXX Check EEPROM for default to FDX? 580 */ 581 if (exm->exm_epmedia == default_media) { 582 if ((exm->exm_ifmedia & IFM_FDX) == 0) { 583 defmedia = exm->exm_ifmedia; 584 defmedianame = exm->exm_name; 585 } 586 } else if (defmedia == 0) { 587 defmedia = exm->exm_ifmedia; 588 defmedianame = exm->exm_name; 589 } 590 ifmedia_add(ifm, exm->exm_ifmedia, exm->exm_epmedia, 591 NULL); 592 PRINT(exm->exm_name); 593 } 594 } 595 596 #undef PRINT 597 598 #ifdef DIAGNOSTIC 599 if (defmedia == 0) 600 panic("ex_probemedia: impossible"); 601 #endif 602 603 printf(", default %s\n", defmedianame); 604 ifmedia_set(ifm, defmedia); 605 } 606 607 /* 608 * Bring device up. 609 */ 610 int 611 ex_init(ifp) 612 struct ifnet *ifp; 613 { 614 struct ex_softc *sc = ifp->if_softc; 615 bus_space_tag_t iot = sc->sc_iot; 616 bus_space_handle_t ioh = sc->sc_ioh; 617 int i; 618 int error = 0; 619 620 if ((error = ex_enable(sc)) != 0) 621 goto out; 622 623 ex_waitcmd(sc); 624 ex_stop(ifp, 0); 625 626 /* 627 * Set the station address and clear the station mask. The latter 628 * is needed for 90x cards, 0 is the default for 90xB cards. 629 */ 630 GO_WINDOW(2); 631 for (i = 0; i < ETHER_ADDR_LEN; i++) { 632 bus_space_write_1(iot, ioh, ELINK_W2_ADDR_0 + i, 633 LLADDR(ifp->if_sadl)[i]); 634 bus_space_write_1(iot, ioh, ELINK_W2_RECVMASK_0 + i, 0); 635 } 636 637 GO_WINDOW(3); 638 639 bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_RESET); 640 ex_waitcmd(sc); 641 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_RESET); 642 ex_waitcmd(sc); 643 644 /* 645 * Disable reclaim threshold for 90xB, set free threshold to 646 * 6 * 256 = 1536 for 90x. 647 */ 648 if (sc->ex_conf & EX_CONF_90XB) 649 bus_space_write_2(iot, ioh, ELINK_COMMAND, 650 ELINK_TXRECLTHRESH | 255); 651 else 652 bus_space_write_1(iot, ioh, ELINK_TXFREETHRESH, 6); 653 654 bus_space_write_2(iot, ioh, ELINK_COMMAND, 655 SET_RX_EARLY_THRESH | ELINK_THRESH_DISABLE); 656 657 bus_space_write_4(iot, ioh, ELINK_DMACTRL, 658 bus_space_read_4(iot, ioh, ELINK_DMACTRL) | ELINK_DMAC_UPRXEAREN); 659 660 bus_space_write_2(iot, ioh, ELINK_COMMAND, SET_RD_0_MASK | S_MASK); 661 bus_space_write_2(iot, ioh, ELINK_COMMAND, SET_INTR_MASK | S_MASK); 662 663 bus_space_write_2(iot, ioh, ELINK_COMMAND, ACK_INTR | 0xff); 664 if (sc->intr_ack) 665 (* sc->intr_ack)(sc); 666 ex_set_media(sc); 667 ex_set_mc(sc); 668 669 670 bus_space_write_2(iot, ioh, ELINK_COMMAND, STATS_ENABLE); 671 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_ENABLE); 672 bus_space_write_4(iot, ioh, ELINK_UPLISTPTR, sc->sc_upddma); 673 bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_ENABLE); 674 bus_space_write_2(iot, ioh, ELINK_COMMAND, ELINK_UPUNSTALL); 675 676 if (sc->ex_conf & (EX_CONF_PHY_POWER | EX_CONF_INV_LED_POLARITY)) { 677 u_int16_t cbcard_config; 678 679 GO_WINDOW(2); 680 cbcard_config = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 0x0c); 681 if (sc->ex_conf & EX_CONF_PHY_POWER) { 682 cbcard_config |= 0x4000; /* turn on PHY power */ 683 } 684 if (sc->ex_conf & EX_CONF_INV_LED_POLARITY) { 685 cbcard_config |= 0x0010; /* invert LED polarity */ 686 } 687 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 0x0c, cbcard_config); 688 689 GO_WINDOW(3); 690 } 691 692 ifp->if_flags |= IFF_RUNNING; 693 ifp->if_flags &= ~IFF_OACTIVE; 694 ex_start(ifp); 695 696 GO_WINDOW(1); 697 698 callout_reset(&sc->ex_mii_callout, hz, ex_tick, sc); 699 700 out: 701 if (error) { 702 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 703 ifp->if_timer = 0; 704 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 705 } 706 return (error); 707 } 708 709 #define ex_mchash(addr) (ether_crc32_be((addr), ETHER_ADDR_LEN) & 0xff) 710 711 /* 712 * Set multicast receive filter. Also take care of promiscuous mode 713 * here (XXX). 714 */ 715 void 716 ex_set_mc(sc) 717 struct ex_softc *sc; 718 { 719 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 720 struct ethercom *ec = &sc->sc_ethercom; 721 struct ether_multi *enm; 722 struct ether_multistep estep; 723 int i; 724 u_int16_t mask = FIL_INDIVIDUAL | FIL_BRDCST; 725 726 if (ifp->if_flags & IFF_PROMISC) 727 mask |= FIL_PROMISC; 728 729 if (!(ifp->if_flags & IFF_MULTICAST)) 730 goto out; 731 732 if (!(sc->ex_conf & EX_CONF_90XB) || ifp->if_flags & IFF_ALLMULTI) { 733 mask |= (ifp->if_flags & IFF_MULTICAST) ? FIL_MULTICAST : 0; 734 } else { 735 ETHER_FIRST_MULTI(estep, ec, enm); 736 while (enm != NULL) { 737 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 738 ETHER_ADDR_LEN) != 0) 739 goto out; 740 i = ex_mchash(enm->enm_addrlo); 741 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 742 ELINK_COMMAND, ELINK_SETHASHFILBIT | i); 743 ETHER_NEXT_MULTI(estep, enm); 744 } 745 mask |= FIL_MULTIHASH; 746 } 747 out: 748 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_COMMAND, 749 SET_RX_FILTER | mask); 750 } 751 752 753 static void 754 ex_txstat(sc) 755 struct ex_softc *sc; 756 { 757 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 758 bus_space_tag_t iot = sc->sc_iot; 759 bus_space_handle_t ioh = sc->sc_ioh; 760 int i; 761 762 /* 763 * We need to read+write TX_STATUS until we get a 0 status 764 * in order to turn off the interrupt flag. 765 */ 766 while ((i = bus_space_read_1(iot, ioh, ELINK_TXSTATUS)) & TXS_COMPLETE) { 767 bus_space_write_1(iot, ioh, ELINK_TXSTATUS, 0x0); 768 769 if (i & TXS_JABBER) { 770 ++sc->sc_ethercom.ec_if.if_oerrors; 771 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 772 printf("%s: jabber (%x)\n", 773 sc->sc_dev.dv_xname, i); 774 ex_init(ifp); 775 /* TODO: be more subtle here */ 776 } else if (i & TXS_UNDERRUN) { 777 ++sc->sc_ethercom.ec_if.if_oerrors; 778 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 779 printf("%s: fifo underrun (%x) @%d\n", 780 sc->sc_dev.dv_xname, i, 781 sc->tx_start_thresh); 782 if (sc->tx_succ_ok < 100) 783 sc->tx_start_thresh = min(ETHER_MAX_LEN, 784 sc->tx_start_thresh + 20); 785 sc->tx_succ_ok = 0; 786 ex_init(ifp); 787 /* TODO: be more subtle here */ 788 } else if (i & TXS_MAX_COLLISION) { 789 ++sc->sc_ethercom.ec_if.if_collisions; 790 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_ENABLE); 791 sc->sc_ethercom.ec_if.if_flags &= ~IFF_OACTIVE; 792 } else 793 sc->tx_succ_ok = (sc->tx_succ_ok+1) & 127; 794 } 795 } 796 797 int 798 ex_media_chg(ifp) 799 struct ifnet *ifp; 800 { 801 802 if (ifp->if_flags & IFF_UP) 803 ex_init(ifp); 804 return 0; 805 } 806 807 void 808 ex_set_media(sc) 809 struct ex_softc *sc; 810 { 811 bus_space_tag_t iot = sc->sc_iot; 812 bus_space_handle_t ioh = sc->sc_ioh; 813 u_int32_t configreg; 814 815 if (((sc->ex_conf & EX_CONF_MII) && 816 (sc->ex_mii.mii_media_active & IFM_FDX)) 817 || (!(sc->ex_conf & EX_CONF_MII) && 818 (sc->ex_mii.mii_media.ifm_media & IFM_FDX))) { 819 bus_space_write_2(iot, ioh, ELINK_W3_MAC_CONTROL, 820 MAC_CONTROL_FDX); 821 } else { 822 bus_space_write_2(iot, ioh, ELINK_W3_MAC_CONTROL, 0); 823 } 824 825 /* 826 * If the device has MII, select it, and then tell the 827 * PHY which media to use. 828 */ 829 if (sc->ex_conf & EX_CONF_MII) { 830 GO_WINDOW(3); 831 832 configreg = bus_space_read_4(iot, ioh, ELINK_W3_INTERNAL_CONFIG); 833 834 configreg &= ~(CONFIG_MEDIAMASK << 16); 835 configreg |= (ELINKMEDIA_MII << (CONFIG_MEDIAMASK_SHIFT + 16)); 836 837 bus_space_write_4(iot, ioh, ELINK_W3_INTERNAL_CONFIG, configreg); 838 mii_mediachg(&sc->ex_mii); 839 return; 840 } 841 842 GO_WINDOW(4); 843 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 0); 844 bus_space_write_2(iot, ioh, ELINK_COMMAND, STOP_TRANSCEIVER); 845 delay(800); 846 847 /* 848 * Now turn on the selected media/transceiver. 849 */ 850 switch (IFM_SUBTYPE(sc->ex_mii.mii_media.ifm_cur->ifm_media)) { 851 case IFM_10_T: 852 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 853 JABBER_GUARD_ENABLE|LINKBEAT_ENABLE); 854 break; 855 856 case IFM_10_2: 857 bus_space_write_2(iot, ioh, ELINK_COMMAND, START_TRANSCEIVER); 858 DELAY(800); 859 break; 860 861 case IFM_100_TX: 862 case IFM_100_FX: 863 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 864 LINKBEAT_ENABLE); 865 DELAY(800); 866 break; 867 868 case IFM_10_5: 869 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 870 SQE_ENABLE); 871 DELAY(800); 872 break; 873 874 case IFM_MANUAL: 875 break; 876 877 case IFM_NONE: 878 return; 879 880 default: 881 panic("ex_set_media: impossible"); 882 } 883 884 GO_WINDOW(3); 885 configreg = bus_space_read_4(iot, ioh, ELINK_W3_INTERNAL_CONFIG); 886 887 configreg &= ~(CONFIG_MEDIAMASK << 16); 888 configreg |= (sc->ex_mii.mii_media.ifm_cur->ifm_data << 889 (CONFIG_MEDIAMASK_SHIFT + 16)); 890 891 bus_space_write_4(iot, ioh, ELINK_W3_INTERNAL_CONFIG, configreg); 892 } 893 894 /* 895 * Get currently-selected media from card. 896 * (if_media callback, may be called before interface is brought up). 897 */ 898 void 899 ex_media_stat(ifp, req) 900 struct ifnet *ifp; 901 struct ifmediareq *req; 902 { 903 struct ex_softc *sc = ifp->if_softc; 904 905 if (sc->ex_conf & EX_CONF_MII) { 906 mii_pollstat(&sc->ex_mii); 907 req->ifm_status = sc->ex_mii.mii_media_status; 908 req->ifm_active = sc->ex_mii.mii_media_active; 909 } else { 910 GO_WINDOW(4); 911 req->ifm_status = IFM_AVALID; 912 req->ifm_active = sc->ex_mii.mii_media.ifm_cur->ifm_media; 913 if (bus_space_read_2(sc->sc_iot, sc->sc_ioh, 914 ELINK_W4_MEDIA_TYPE) & LINKBEAT_DETECT) 915 req->ifm_status |= IFM_ACTIVE; 916 GO_WINDOW(1); 917 } 918 } 919 920 921 922 /* 923 * Start outputting on the interface. 924 */ 925 static void 926 ex_start(ifp) 927 struct ifnet *ifp; 928 { 929 struct ex_softc *sc = ifp->if_softc; 930 bus_space_tag_t iot = sc->sc_iot; 931 bus_space_handle_t ioh = sc->sc_ioh; 932 volatile struct ex_fraghdr *fr = NULL; 933 volatile struct ex_dpd *dpd = NULL, *prevdpd = NULL; 934 struct ex_txdesc *txp; 935 struct mbuf *mb_head; 936 bus_dmamap_t dmamap; 937 int offset, totlen, segment, error; 938 u_int32_t csum_flags; 939 940 if (sc->tx_head || sc->tx_free == NULL) 941 return; 942 943 txp = NULL; 944 945 /* 946 * We're finished if there is nothing more to add to the list or if 947 * we're all filled up with buffers to transmit. 948 */ 949 while (sc->tx_free != NULL) { 950 /* 951 * Grab a packet to transmit. 952 */ 953 IFQ_DEQUEUE(&ifp->if_snd, mb_head); 954 if (mb_head == NULL) 955 break; 956 957 /* 958 * Get pointer to next available tx desc. 959 */ 960 txp = sc->tx_free; 961 dmamap = txp->tx_dmamap; 962 963 /* 964 * Go through each of the mbufs in the chain and initialize 965 * the transmit buffer descriptors with the physical address 966 * and size of the mbuf. 967 */ 968 reload: 969 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 970 mb_head, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 971 switch (error) { 972 case 0: 973 /* Success. */ 974 break; 975 976 case EFBIG: 977 { 978 struct mbuf *mn; 979 980 /* 981 * We ran out of segments. We have to recopy this 982 * mbuf chain first. Bail out if we can't get the 983 * new buffers. 984 */ 985 printf("%s: too many segments, ", sc->sc_dev.dv_xname); 986 987 MGETHDR(mn, M_DONTWAIT, MT_DATA); 988 if (mn == NULL) { 989 m_freem(mb_head); 990 printf("aborting\n"); 991 goto out; 992 } 993 if (mb_head->m_pkthdr.len > MHLEN) { 994 MCLGET(mn, M_DONTWAIT); 995 if ((mn->m_flags & M_EXT) == 0) { 996 m_freem(mn); 997 m_freem(mb_head); 998 printf("aborting\n"); 999 goto out; 1000 } 1001 } 1002 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1003 mtod(mn, caddr_t)); 1004 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1005 m_freem(mb_head); 1006 mb_head = mn; 1007 printf("retrying\n"); 1008 goto reload; 1009 } 1010 1011 default: 1012 /* 1013 * Some other problem; report it. 1014 */ 1015 printf("%s: can't load mbuf chain, error = %d\n", 1016 sc->sc_dev.dv_xname, error); 1017 m_freem(mb_head); 1018 goto out; 1019 } 1020 1021 /* 1022 * remove our tx desc from freelist. 1023 */ 1024 sc->tx_free = txp->tx_next; 1025 txp->tx_next = NULL; 1026 1027 fr = &txp->tx_dpd->dpd_frags[0]; 1028 totlen = 0; 1029 for (segment = 0; segment < dmamap->dm_nsegs; segment++, fr++) { 1030 fr->fr_addr = htole32(dmamap->dm_segs[segment].ds_addr); 1031 fr->fr_len = htole32(dmamap->dm_segs[segment].ds_len); 1032 totlen += dmamap->dm_segs[segment].ds_len; 1033 } 1034 fr--; 1035 fr->fr_len |= htole32(EX_FR_LAST); 1036 txp->tx_mbhead = mb_head; 1037 1038 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1039 BUS_DMASYNC_PREWRITE); 1040 1041 dpd = txp->tx_dpd; 1042 dpd->dpd_nextptr = 0; 1043 dpd->dpd_fsh = htole32(totlen); 1044 1045 /* Byte-swap constants to compiler can optimize. */ 1046 1047 if (sc->ex_conf & EX_CONF_90XB) { 1048 csum_flags = 0; 1049 1050 if (mb_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 1051 csum_flags |= htole32(EX_DPD_IPCKSUM); 1052 1053 if (mb_head->m_pkthdr.csum_flags & M_CSUM_TCPv4) 1054 csum_flags |= htole32(EX_DPD_TCPCKSUM); 1055 else if (mb_head->m_pkthdr.csum_flags & M_CSUM_UDPv4) 1056 csum_flags |= htole32(EX_DPD_UDPCKSUM); 1057 1058 dpd->dpd_fsh |= csum_flags; 1059 } else { 1060 KDASSERT((mb_head->m_pkthdr.csum_flags & 1061 (M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4)) == 0); 1062 } 1063 1064 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap, 1065 ((caddr_t)dpd - (caddr_t)sc->sc_dpd), 1066 sizeof (struct ex_dpd), 1067 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1068 1069 /* 1070 * No need to stall the download engine, we know it's 1071 * not busy right now. 1072 * 1073 * Fix up pointers in both the "soft" tx and the physical 1074 * tx list. 1075 */ 1076 if (sc->tx_head != NULL) { 1077 prevdpd = sc->tx_tail->tx_dpd; 1078 offset = ((caddr_t)prevdpd - (caddr_t)sc->sc_dpd); 1079 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap, 1080 offset, sizeof (struct ex_dpd), 1081 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1082 prevdpd->dpd_nextptr = htole32(DPD_DMADDR(sc, txp)); 1083 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap, 1084 offset, sizeof (struct ex_dpd), 1085 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1086 sc->tx_tail->tx_next = txp; 1087 sc->tx_tail = txp; 1088 } else { 1089 sc->tx_tail = sc->tx_head = txp; 1090 } 1091 1092 #if NBPFILTER > 0 1093 /* 1094 * Pass packet to bpf if there is a listener. 1095 */ 1096 if (ifp->if_bpf) 1097 bpf_mtap(ifp->if_bpf, mb_head); 1098 #endif 1099 } 1100 out: 1101 if (sc->tx_head) { 1102 sc->tx_tail->tx_dpd->dpd_fsh |= htole32(EX_DPD_DNIND); 1103 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap, 1104 ((caddr_t)sc->tx_tail->tx_dpd - (caddr_t)sc->sc_dpd), 1105 sizeof (struct ex_dpd), 1106 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1107 ifp->if_flags |= IFF_OACTIVE; 1108 bus_space_write_2(iot, ioh, ELINK_COMMAND, ELINK_DNUNSTALL); 1109 bus_space_write_4(iot, ioh, ELINK_DNLISTPTR, 1110 DPD_DMADDR(sc, sc->tx_head)); 1111 1112 /* trigger watchdog */ 1113 ifp->if_timer = 5; 1114 } 1115 } 1116 1117 1118 int 1119 ex_intr(arg) 1120 void *arg; 1121 { 1122 struct ex_softc *sc = arg; 1123 bus_space_tag_t iot = sc->sc_iot; 1124 bus_space_handle_t ioh = sc->sc_ioh; 1125 u_int16_t stat; 1126 int ret = 0; 1127 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1128 1129 if ((ifp->if_flags & IFF_RUNNING) == 0 || 1130 (sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1131 return (0); 1132 1133 for (;;) { 1134 bus_space_write_2(iot, ioh, ELINK_COMMAND, C_INTR_LATCH); 1135 1136 stat = bus_space_read_2(iot, ioh, ELINK_STATUS); 1137 1138 if ((stat & S_MASK) == 0) { 1139 if ((stat & S_INTR_LATCH) == 0) { 1140 #if 0 1141 printf("%s: intr latch cleared\n", 1142 sc->sc_dev.dv_xname); 1143 #endif 1144 break; 1145 } 1146 } 1147 1148 ret = 1; 1149 1150 /* 1151 * Acknowledge interrupts. 1152 */ 1153 bus_space_write_2(iot, ioh, ELINK_COMMAND, ACK_INTR | 1154 (stat & S_MASK)); 1155 if (sc->intr_ack) 1156 (*sc->intr_ack)(sc); 1157 1158 if (stat & S_HOST_ERROR) { 1159 printf("%s: adapter failure (%x)\n", 1160 sc->sc_dev.dv_xname, stat); 1161 ex_reset(sc); 1162 ex_init(ifp); 1163 return 1; 1164 } 1165 if (stat & S_TX_COMPLETE) { 1166 ex_txstat(sc); 1167 } 1168 if (stat & S_UPD_STATS) { 1169 ex_getstats(sc); 1170 } 1171 if (stat & S_DN_COMPLETE) { 1172 struct ex_txdesc *txp, *ptxp = NULL; 1173 bus_dmamap_t txmap; 1174 1175 /* reset watchdog timer, was set in ex_start() */ 1176 ifp->if_timer = 0; 1177 1178 for (txp = sc->tx_head; txp != NULL; 1179 txp = txp->tx_next) { 1180 bus_dmamap_sync(sc->sc_dmat, 1181 sc->sc_dpd_dmamap, 1182 (caddr_t)txp->tx_dpd - (caddr_t)sc->sc_dpd, 1183 sizeof (struct ex_dpd), 1184 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1185 if (txp->tx_mbhead != NULL) { 1186 txmap = txp->tx_dmamap; 1187 bus_dmamap_sync(sc->sc_dmat, txmap, 1188 0, txmap->dm_mapsize, 1189 BUS_DMASYNC_POSTWRITE); 1190 bus_dmamap_unload(sc->sc_dmat, txmap); 1191 m_freem(txp->tx_mbhead); 1192 txp->tx_mbhead = NULL; 1193 } 1194 ptxp = txp; 1195 } 1196 1197 /* 1198 * Move finished tx buffers back to the tx free list. 1199 */ 1200 if (sc->tx_free) { 1201 sc->tx_ftail->tx_next = sc->tx_head; 1202 sc->tx_ftail = ptxp; 1203 } else 1204 sc->tx_ftail = sc->tx_free = sc->tx_head; 1205 1206 sc->tx_head = sc->tx_tail = NULL; 1207 ifp->if_flags &= ~IFF_OACTIVE; 1208 } 1209 1210 if (stat & S_UP_COMPLETE) { 1211 struct ex_rxdesc *rxd; 1212 struct mbuf *m; 1213 struct ex_upd *upd; 1214 bus_dmamap_t rxmap; 1215 u_int32_t pktstat; 1216 1217 rcvloop: 1218 rxd = sc->rx_head; 1219 rxmap = rxd->rx_dmamap; 1220 m = rxd->rx_mbhead; 1221 upd = rxd->rx_upd; 1222 1223 bus_dmamap_sync(sc->sc_dmat, rxmap, 0, 1224 rxmap->dm_mapsize, 1225 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1226 bus_dmamap_sync(sc->sc_dmat, sc->sc_upd_dmamap, 1227 ((caddr_t)upd - (caddr_t)sc->sc_upd), 1228 sizeof (struct ex_upd), 1229 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1230 pktstat = le32toh(upd->upd_pktstatus); 1231 1232 if (pktstat & EX_UPD_COMPLETE) { 1233 /* 1234 * Remove first packet from the chain. 1235 */ 1236 sc->rx_head = rxd->rx_next; 1237 rxd->rx_next = NULL; 1238 1239 /* 1240 * Add a new buffer to the receive chain. 1241 * If this fails, the old buffer is recycled 1242 * instead. 1243 */ 1244 if (ex_add_rxbuf(sc, rxd) == 0) { 1245 u_int16_t total_len; 1246 1247 if (pktstat & 1248 ((sc->sc_ethercom.ec_capenable & 1249 ETHERCAP_VLAN_MTU) ? 1250 EX_UPD_ERR_VLAN : EX_UPD_ERR)) { 1251 ifp->if_ierrors++; 1252 m_freem(m); 1253 goto rcvloop; 1254 } 1255 1256 total_len = pktstat & EX_UPD_PKTLENMASK; 1257 if (total_len < 1258 sizeof(struct ether_header)) { 1259 m_freem(m); 1260 goto rcvloop; 1261 } 1262 m->m_pkthdr.rcvif = ifp; 1263 m->m_pkthdr.len = m->m_len = total_len; 1264 #if NBPFILTER > 0 1265 if (ifp->if_bpf) 1266 bpf_mtap(ifp->if_bpf, m); 1267 #endif 1268 /* 1269 * Set the incoming checksum information for the packet. 1270 */ 1271 if ((sc->ex_conf & EX_CONF_90XB) != 0 && 1272 (pktstat & EX_UPD_IPCHECKED) != 0) { 1273 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1274 if (pktstat & EX_UPD_IPCKSUMERR) 1275 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1276 if (pktstat & EX_UPD_TCPCHECKED) { 1277 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1278 if (pktstat & EX_UPD_TCPCKSUMERR) 1279 m->m_pkthdr.csum_flags |= 1280 M_CSUM_TCP_UDP_BAD; 1281 } else if (pktstat & EX_UPD_UDPCHECKED) { 1282 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1283 if (pktstat & EX_UPD_UDPCKSUMERR) 1284 m->m_pkthdr.csum_flags |= 1285 M_CSUM_TCP_UDP_BAD; 1286 } 1287 } 1288 (*ifp->if_input)(ifp, m); 1289 } 1290 goto rcvloop; 1291 } 1292 /* 1293 * Just in case we filled up all UPDs and the DMA engine 1294 * stalled. We could be more subtle about this. 1295 */ 1296 if (bus_space_read_4(iot, ioh, ELINK_UPLISTPTR) == 0) { 1297 printf("%s: uplistptr was 0\n", 1298 sc->sc_dev.dv_xname); 1299 ex_init(ifp); 1300 } else if (bus_space_read_4(iot, ioh, ELINK_UPPKTSTATUS) 1301 & 0x2000) { 1302 printf("%s: receive stalled\n", 1303 sc->sc_dev.dv_xname); 1304 bus_space_write_2(iot, ioh, ELINK_COMMAND, 1305 ELINK_UPUNSTALL); 1306 } 1307 } 1308 } 1309 1310 /* no more interrupts */ 1311 if (ret && IFQ_IS_EMPTY(&ifp->if_snd) == 0) 1312 ex_start(ifp); 1313 return ret; 1314 } 1315 1316 int 1317 ex_ioctl(ifp, cmd, data) 1318 struct ifnet *ifp; 1319 u_long cmd; 1320 caddr_t data; 1321 { 1322 struct ex_softc *sc = ifp->if_softc; 1323 struct ifreq *ifr = (struct ifreq *)data; 1324 int s, error; 1325 1326 s = splnet(); 1327 1328 switch (cmd) { 1329 case SIOCSIFMEDIA: 1330 case SIOCGIFMEDIA: 1331 error = ifmedia_ioctl(ifp, ifr, &sc->ex_mii.mii_media, cmd); 1332 break; 1333 1334 default: 1335 error = ether_ioctl(ifp, cmd, data); 1336 if (error == ENETRESET) { 1337 if (sc->enabled) { 1338 /* 1339 * Multicast list has changed; set the hardware filter 1340 * accordingly. 1341 */ 1342 ex_set_mc(sc); 1343 } 1344 error = 0; 1345 } 1346 break; 1347 } 1348 1349 splx(s); 1350 return (error); 1351 } 1352 1353 void 1354 ex_getstats(sc) 1355 struct ex_softc *sc; 1356 { 1357 bus_space_handle_t ioh = sc->sc_ioh; 1358 bus_space_tag_t iot = sc->sc_iot; 1359 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1360 u_int8_t upperok; 1361 1362 GO_WINDOW(6); 1363 upperok = bus_space_read_1(iot, ioh, UPPER_FRAMES_OK); 1364 ifp->if_ipackets += bus_space_read_1(iot, ioh, RX_FRAMES_OK); 1365 ifp->if_ipackets += (upperok & 0x03) << 8; 1366 ifp->if_opackets += bus_space_read_1(iot, ioh, TX_FRAMES_OK); 1367 ifp->if_opackets += (upperok & 0x30) << 4; 1368 ifp->if_ierrors += bus_space_read_1(iot, ioh, RX_OVERRUNS); 1369 ifp->if_collisions += bus_space_read_1(iot, ioh, TX_COLLISIONS); 1370 /* 1371 * There seems to be no way to get the exact number of collisions, 1372 * this is the number that occurred at the very least. 1373 */ 1374 ifp->if_collisions += 2 * bus_space_read_1(iot, ioh, 1375 TX_AFTER_X_COLLISIONS); 1376 ifp->if_ibytes += bus_space_read_2(iot, ioh, RX_TOTAL_OK); 1377 ifp->if_obytes += bus_space_read_2(iot, ioh, TX_TOTAL_OK); 1378 1379 /* 1380 * Clear the following to avoid stats overflow interrupts 1381 */ 1382 bus_space_read_1(iot, ioh, TX_DEFERRALS); 1383 bus_space_read_1(iot, ioh, TX_AFTER_1_COLLISION); 1384 bus_space_read_1(iot, ioh, TX_NO_SQE); 1385 bus_space_read_1(iot, ioh, TX_CD_LOST); 1386 GO_WINDOW(4); 1387 bus_space_read_1(iot, ioh, ELINK_W4_BADSSD); 1388 upperok = bus_space_read_1(iot, ioh, ELINK_W4_UBYTESOK); 1389 ifp->if_ibytes += (upperok & 0x0f) << 16; 1390 ifp->if_obytes += (upperok & 0xf0) << 12; 1391 GO_WINDOW(1); 1392 } 1393 1394 void 1395 ex_printstats(sc) 1396 struct ex_softc *sc; 1397 { 1398 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1399 1400 ex_getstats(sc); 1401 printf("in %llu out %llu ierror %llu oerror %llu ibytes %llu obytes " 1402 "%llu\n", (unsigned long long)ifp->if_ipackets, 1403 (unsigned long long)ifp->if_opackets, 1404 (unsigned long long)ifp->if_ierrors, 1405 (unsigned long long)ifp->if_oerrors, 1406 (unsigned long long)ifp->if_ibytes, 1407 (unsigned long long)ifp->if_obytes); 1408 } 1409 1410 void 1411 ex_tick(arg) 1412 void *arg; 1413 { 1414 struct ex_softc *sc = arg; 1415 int s; 1416 1417 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1418 return; 1419 1420 s = splnet(); 1421 1422 if (sc->ex_conf & EX_CONF_MII) 1423 mii_tick(&sc->ex_mii); 1424 1425 if (!(bus_space_read_2((sc)->sc_iot, (sc)->sc_ioh, ELINK_STATUS) 1426 & S_COMMAND_IN_PROGRESS)) 1427 ex_getstats(sc); 1428 1429 splx(s); 1430 1431 callout_reset(&sc->ex_mii_callout, hz, ex_tick, sc); 1432 } 1433 1434 void 1435 ex_reset(sc) 1436 struct ex_softc *sc; 1437 { 1438 u_int16_t val = GLOBAL_RESET; 1439 1440 if (sc->ex_conf & EX_CONF_RESETHACK) 1441 val |= 0x10; 1442 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_COMMAND, val); 1443 /* 1444 * XXX apparently the command in progress bit can't be trusted 1445 * during a reset, so we just always wait this long. Fortunately 1446 * we normally only reset the chip during autoconfig. 1447 */ 1448 delay(100000); 1449 ex_waitcmd(sc); 1450 } 1451 1452 void 1453 ex_watchdog(ifp) 1454 struct ifnet *ifp; 1455 { 1456 struct ex_softc *sc = ifp->if_softc; 1457 1458 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1459 ++sc->sc_ethercom.ec_if.if_oerrors; 1460 1461 ex_reset(sc); 1462 ex_init(ifp); 1463 } 1464 1465 void 1466 ex_stop(ifp, disable) 1467 struct ifnet *ifp; 1468 int disable; 1469 { 1470 struct ex_softc *sc = ifp->if_softc; 1471 bus_space_tag_t iot = sc->sc_iot; 1472 bus_space_handle_t ioh = sc->sc_ioh; 1473 struct ex_txdesc *tx; 1474 struct ex_rxdesc *rx; 1475 int i; 1476 1477 bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_DISABLE); 1478 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_DISABLE); 1479 bus_space_write_2(iot, ioh, ELINK_COMMAND, STOP_TRANSCEIVER); 1480 1481 for (tx = sc->tx_head ; tx != NULL; tx = tx->tx_next) { 1482 if (tx->tx_mbhead == NULL) 1483 continue; 1484 m_freem(tx->tx_mbhead); 1485 tx->tx_mbhead = NULL; 1486 bus_dmamap_unload(sc->sc_dmat, tx->tx_dmamap); 1487 tx->tx_dpd->dpd_fsh = tx->tx_dpd->dpd_nextptr = 0; 1488 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap, 1489 ((caddr_t)tx->tx_dpd - (caddr_t)sc->sc_dpd), 1490 sizeof (struct ex_dpd), 1491 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1492 } 1493 sc->tx_tail = sc->tx_head = NULL; 1494 ex_init_txdescs(sc); 1495 1496 sc->rx_tail = sc->rx_head = 0; 1497 for (i = 0; i < EX_NUPD; i++) { 1498 rx = &sc->sc_rxdescs[i]; 1499 if (rx->rx_mbhead != NULL) { 1500 bus_dmamap_unload(sc->sc_dmat, rx->rx_dmamap); 1501 m_freem(rx->rx_mbhead); 1502 rx->rx_mbhead = NULL; 1503 } 1504 ex_add_rxbuf(sc, rx); 1505 } 1506 1507 bus_space_write_2(iot, ioh, ELINK_COMMAND, C_INTR_LATCH); 1508 1509 callout_stop(&sc->ex_mii_callout); 1510 if (sc->ex_conf & EX_CONF_MII) 1511 mii_down(&sc->ex_mii); 1512 1513 if (disable) 1514 ex_disable(sc); 1515 1516 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1517 ifp->if_timer = 0; 1518 } 1519 1520 static void 1521 ex_init_txdescs(sc) 1522 struct ex_softc *sc; 1523 { 1524 int i; 1525 1526 for (i = 0; i < EX_NDPD; i++) { 1527 sc->sc_txdescs[i].tx_dmamap = sc->sc_tx_dmamaps[i]; 1528 sc->sc_txdescs[i].tx_dpd = &sc->sc_dpd[i]; 1529 if (i < EX_NDPD - 1) 1530 sc->sc_txdescs[i].tx_next = &sc->sc_txdescs[i + 1]; 1531 else 1532 sc->sc_txdescs[i].tx_next = NULL; 1533 } 1534 sc->tx_free = &sc->sc_txdescs[0]; 1535 sc->tx_ftail = &sc->sc_txdescs[EX_NDPD-1]; 1536 } 1537 1538 1539 int 1540 ex_activate(self, act) 1541 struct device *self; 1542 enum devact act; 1543 { 1544 struct ex_softc *sc = (void *) self; 1545 int s, error = 0; 1546 1547 s = splnet(); 1548 switch (act) { 1549 case DVACT_ACTIVATE: 1550 error = EOPNOTSUPP; 1551 break; 1552 1553 case DVACT_DEACTIVATE: 1554 if (sc->ex_conf & EX_CONF_MII) 1555 mii_activate(&sc->ex_mii, act, MII_PHY_ANY, 1556 MII_OFFSET_ANY); 1557 if_deactivate(&sc->sc_ethercom.ec_if); 1558 break; 1559 } 1560 splx(s); 1561 1562 return (error); 1563 } 1564 1565 int 1566 ex_detach(sc) 1567 struct ex_softc *sc; 1568 { 1569 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1570 struct ex_rxdesc *rxd; 1571 int i; 1572 1573 /* Succeed now if there's no work to do. */ 1574 if ((sc->ex_flags & EX_FLAGS_ATTACHED) == 0) 1575 return (0); 1576 1577 /* Unhook our tick handler. */ 1578 callout_stop(&sc->ex_mii_callout); 1579 1580 if (sc->ex_conf & EX_CONF_MII) { 1581 /* Detach all PHYs */ 1582 mii_detach(&sc->ex_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1583 } 1584 1585 /* Delete all remaining media. */ 1586 ifmedia_delete_instance(&sc->ex_mii.mii_media, IFM_INST_ANY); 1587 1588 #if NRND > 0 1589 rnd_detach_source(&sc->rnd_source); 1590 #endif 1591 ether_ifdetach(ifp); 1592 if_detach(ifp); 1593 1594 for (i = 0; i < EX_NUPD; i++) { 1595 rxd = &sc->sc_rxdescs[i]; 1596 if (rxd->rx_mbhead != NULL) { 1597 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 1598 m_freem(rxd->rx_mbhead); 1599 rxd->rx_mbhead = NULL; 1600 } 1601 } 1602 for (i = 0; i < EX_NUPD; i++) 1603 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rx_dmamaps[i]); 1604 for (i = 0; i < EX_NDPD; i++) 1605 bus_dmamap_destroy(sc->sc_dmat, sc->sc_tx_dmamaps[i]); 1606 bus_dmamap_unload(sc->sc_dmat, sc->sc_dpd_dmamap); 1607 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dpd_dmamap); 1608 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_dpd, 1609 EX_NDPD * sizeof (struct ex_dpd)); 1610 bus_dmamem_free(sc->sc_dmat, &sc->sc_dseg, sc->sc_drseg); 1611 bus_dmamap_unload(sc->sc_dmat, sc->sc_upd_dmamap); 1612 bus_dmamap_destroy(sc->sc_dmat, sc->sc_upd_dmamap); 1613 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_upd, 1614 EX_NUPD * sizeof (struct ex_upd)); 1615 bus_dmamem_free(sc->sc_dmat, &sc->sc_useg, sc->sc_urseg); 1616 1617 shutdownhook_disestablish(sc->sc_sdhook); 1618 powerhook_disestablish(sc->sc_powerhook); 1619 1620 return (0); 1621 } 1622 1623 /* 1624 * Before reboots, reset card completely. 1625 */ 1626 static void 1627 ex_shutdown(arg) 1628 void *arg; 1629 { 1630 struct ex_softc *sc = arg; 1631 1632 ex_stop(&sc->sc_ethercom.ec_if, 1); 1633 } 1634 1635 /* 1636 * Read EEPROM data. 1637 * XXX what to do if EEPROM doesn't unbusy? 1638 */ 1639 u_int16_t 1640 ex_read_eeprom(sc, offset) 1641 struct ex_softc *sc; 1642 int offset; 1643 { 1644 bus_space_tag_t iot = sc->sc_iot; 1645 bus_space_handle_t ioh = sc->sc_ioh; 1646 u_int16_t data = 0, cmd = READ_EEPROM; 1647 int off; 1648 1649 off = sc->ex_conf & EX_CONF_EEPROM_OFF ? 0x30 : 0; 1650 cmd = sc->ex_conf & EX_CONF_EEPROM_8BIT ? READ_EEPROM8 : READ_EEPROM; 1651 1652 GO_WINDOW(0); 1653 if (ex_eeprom_busy(sc)) 1654 goto out; 1655 bus_space_write_2(iot, ioh, ELINK_W0_EEPROM_COMMAND, 1656 cmd | (off + (offset & 0x3f))); 1657 if (ex_eeprom_busy(sc)) 1658 goto out; 1659 data = bus_space_read_2(iot, ioh, ELINK_W0_EEPROM_DATA); 1660 out: 1661 return data; 1662 } 1663 1664 static int 1665 ex_eeprom_busy(sc) 1666 struct ex_softc *sc; 1667 { 1668 bus_space_tag_t iot = sc->sc_iot; 1669 bus_space_handle_t ioh = sc->sc_ioh; 1670 int i = 100; 1671 1672 while (i--) { 1673 if (!(bus_space_read_2(iot, ioh, ELINK_W0_EEPROM_COMMAND) & 1674 EEPROM_BUSY)) 1675 return 0; 1676 delay(100); 1677 } 1678 printf("\n%s: eeprom stays busy.\n", sc->sc_dev.dv_xname); 1679 return (1); 1680 } 1681 1682 /* 1683 * Create a new rx buffer and add it to the 'soft' rx list. 1684 */ 1685 static int 1686 ex_add_rxbuf(sc, rxd) 1687 struct ex_softc *sc; 1688 struct ex_rxdesc *rxd; 1689 { 1690 struct mbuf *m, *oldm; 1691 bus_dmamap_t rxmap; 1692 int error, rval = 0; 1693 1694 oldm = rxd->rx_mbhead; 1695 rxmap = rxd->rx_dmamap; 1696 1697 MGETHDR(m, M_DONTWAIT, MT_DATA); 1698 if (m != NULL) { 1699 MCLGET(m, M_DONTWAIT); 1700 if ((m->m_flags & M_EXT) == 0) { 1701 m_freem(m); 1702 if (oldm == NULL) 1703 return 1; 1704 m = oldm; 1705 m->m_data = m->m_ext.ext_buf; 1706 rval = 1; 1707 } 1708 } else { 1709 if (oldm == NULL) 1710 return 1; 1711 m = oldm; 1712 m->m_data = m->m_ext.ext_buf; 1713 rval = 1; 1714 } 1715 1716 /* 1717 * Setup the DMA map for this receive buffer. 1718 */ 1719 if (m != oldm) { 1720 if (oldm != NULL) 1721 bus_dmamap_unload(sc->sc_dmat, rxmap); 1722 error = bus_dmamap_load(sc->sc_dmat, rxmap, 1723 m->m_ext.ext_buf, MCLBYTES, NULL, 1724 BUS_DMA_READ|BUS_DMA_NOWAIT); 1725 if (error) { 1726 printf("%s: can't load rx buffer, error = %d\n", 1727 sc->sc_dev.dv_xname, error); 1728 panic("ex_add_rxbuf"); /* XXX */ 1729 } 1730 } 1731 1732 /* 1733 * Align for data after 14 byte header. 1734 */ 1735 m->m_data += 2; 1736 1737 rxd->rx_mbhead = m; 1738 rxd->rx_upd->upd_pktstatus = htole32(MCLBYTES - 2); 1739 rxd->rx_upd->upd_frags[0].fr_addr = 1740 htole32(rxmap->dm_segs[0].ds_addr + 2); 1741 rxd->rx_upd->upd_nextptr = 0; 1742 1743 /* 1744 * Attach it to the end of the list. 1745 */ 1746 if (sc->rx_head != NULL) { 1747 sc->rx_tail->rx_next = rxd; 1748 sc->rx_tail->rx_upd->upd_nextptr = htole32(sc->sc_upddma + 1749 ((caddr_t)rxd->rx_upd - (caddr_t)sc->sc_upd)); 1750 bus_dmamap_sync(sc->sc_dmat, sc->sc_upd_dmamap, 1751 (caddr_t)sc->rx_tail->rx_upd - (caddr_t)sc->sc_upd, 1752 sizeof (struct ex_upd), 1753 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1754 } else { 1755 sc->rx_head = rxd; 1756 } 1757 sc->rx_tail = rxd; 1758 1759 bus_dmamap_sync(sc->sc_dmat, rxmap, 0, rxmap->dm_mapsize, 1760 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1761 bus_dmamap_sync(sc->sc_dmat, sc->sc_upd_dmamap, 1762 ((caddr_t)rxd->rx_upd - (caddr_t)sc->sc_upd), 1763 sizeof (struct ex_upd), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1764 return (rval); 1765 } 1766 1767 u_int32_t 1768 ex_mii_bitbang_read(self) 1769 struct device *self; 1770 { 1771 struct ex_softc *sc = (void *) self; 1772 1773 /* We're already in Window 4. */ 1774 return (bus_space_read_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_PHYSMGMT)); 1775 } 1776 1777 void 1778 ex_mii_bitbang_write(self, val) 1779 struct device *self; 1780 u_int32_t val; 1781 { 1782 struct ex_softc *sc = (void *) self; 1783 1784 /* We're already in Window 4. */ 1785 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_PHYSMGMT, val); 1786 } 1787 1788 int 1789 ex_mii_readreg(v, phy, reg) 1790 struct device *v; 1791 int phy, reg; 1792 { 1793 struct ex_softc *sc = (struct ex_softc *)v; 1794 int val; 1795 1796 if ((sc->ex_conf & EX_CONF_INTPHY) && phy != ELINK_INTPHY_ID) 1797 return 0; 1798 1799 GO_WINDOW(4); 1800 1801 val = mii_bitbang_readreg(v, &ex_mii_bitbang_ops, phy, reg); 1802 1803 GO_WINDOW(1); 1804 1805 return (val); 1806 } 1807 1808 void 1809 ex_mii_writereg(v, phy, reg, data) 1810 struct device *v; 1811 int phy; 1812 int reg; 1813 int data; 1814 { 1815 struct ex_softc *sc = (struct ex_softc *)v; 1816 1817 GO_WINDOW(4); 1818 1819 mii_bitbang_writereg(v, &ex_mii_bitbang_ops, phy, reg, data); 1820 1821 GO_WINDOW(1); 1822 } 1823 1824 void 1825 ex_mii_statchg(v) 1826 struct device *v; 1827 { 1828 struct ex_softc *sc = (struct ex_softc *)v; 1829 bus_space_tag_t iot = sc->sc_iot; 1830 bus_space_handle_t ioh = sc->sc_ioh; 1831 int mctl; 1832 1833 GO_WINDOW(3); 1834 mctl = bus_space_read_2(iot, ioh, ELINK_W3_MAC_CONTROL); 1835 if (sc->ex_mii.mii_media_active & IFM_FDX) 1836 mctl |= MAC_CONTROL_FDX; 1837 else 1838 mctl &= ~MAC_CONTROL_FDX; 1839 bus_space_write_2(iot, ioh, ELINK_W3_MAC_CONTROL, mctl); 1840 GO_WINDOW(1); /* back to operating window */ 1841 } 1842 1843 int 1844 ex_enable(sc) 1845 struct ex_softc *sc; 1846 { 1847 if (sc->enabled == 0 && sc->enable != NULL) { 1848 if ((*sc->enable)(sc) != 0) { 1849 printf("%s: de/vice enable failed\n", 1850 sc->sc_dev.dv_xname); 1851 return (EIO); 1852 } 1853 sc->enabled = 1; 1854 } 1855 return (0); 1856 } 1857 1858 void 1859 ex_disable(sc) 1860 struct ex_softc *sc; 1861 { 1862 if (sc->enabled == 1 && sc->disable != NULL) { 1863 (*sc->disable)(sc); 1864 sc->enabled = 0; 1865 } 1866 } 1867 1868 void 1869 ex_power(why, arg) 1870 int why; 1871 void *arg; 1872 { 1873 struct ex_softc *sc = (void *)arg; 1874 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1875 int s; 1876 1877 s = splnet(); 1878 switch (why) { 1879 case PWR_SUSPEND: 1880 case PWR_STANDBY: 1881 ex_stop(ifp, 0); 1882 if (sc->power != NULL) 1883 (*sc->power)(sc, why); 1884 break; 1885 case PWR_RESUME: 1886 if (ifp->if_flags & IFF_UP) { 1887 if (sc->power != NULL) 1888 (*sc->power)(sc, why); 1889 ex_init(ifp); 1890 } 1891 break; 1892 case PWR_SOFTSUSPEND: 1893 case PWR_SOFTSTANDBY: 1894 case PWR_SOFTRESUME: 1895 break; 1896 } 1897 splx(s); 1898 } 1899
Indexes created Wed Oct 22 06:10:02 GMT 2025