elinkxl.c revision 1.63.4.1
1 /* $NetBSD: elinkxl.c,v 1.63.4.1 2002/12/12 21:34:39 he Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: elinkxl.c,v 1.63.4.1 2002/12/12 21:34:39 he Exp $"); 41 42 #include "bpfilter.h" 43 #include "rnd.h" 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/callout.h> 48 #include <sys/kernel.h> 49 #include <sys/mbuf.h> 50 #include <sys/socket.h> 51 #include <sys/ioctl.h> 52 #include <sys/errno.h> 53 #include <sys/syslog.h> 54 #include <sys/select.h> 55 #include <sys/device.h> 56 #if NRND > 0 57 #include <sys/rnd.h> 58 #endif 59 60 #include <uvm/uvm_extern.h> 61 62 #include <net/if.h> 63 #include <net/if_dl.h> 64 #include <net/if_ether.h> 65 #include <net/if_media.h> 66 67 #if NBPFILTER > 0 68 #include <net/bpf.h> 69 #include <net/bpfdesc.h> 70 #endif 71 72 #include <machine/cpu.h> 73 #include <machine/bus.h> 74 #include <machine/intr.h> 75 #include <machine/endian.h> 76 77 #include <dev/mii/miivar.h> 78 #include <dev/mii/mii.h> 79 #include <dev/mii/mii_bitbang.h> 80 81 #include <dev/ic/elink3reg.h> 82 /* #include <dev/ic/elink3var.h> */ 83 #include <dev/ic/elinkxlreg.h> 84 #include <dev/ic/elinkxlvar.h> 85 86 #ifdef DEBUG 87 int exdebug = 0; 88 #endif 89 90 /* ifmedia callbacks */ 91 int ex_media_chg __P((struct ifnet *ifp)); 92 void ex_media_stat __P((struct ifnet *ifp, struct ifmediareq *req)); 93 94 void ex_probe_media __P((struct ex_softc *)); 95 void ex_set_filter __P((struct ex_softc *)); 96 void ex_set_media __P((struct ex_softc *)); 97 struct mbuf *ex_get __P((struct ex_softc *, int)); 98 u_int16_t ex_read_eeprom __P((struct ex_softc *, int)); 99 int ex_init __P((struct ifnet *)); 100 void ex_read __P((struct ex_softc *)); 101 void ex_reset __P((struct ex_softc *)); 102 void ex_set_mc __P((struct ex_softc *)); 103 void ex_getstats __P((struct ex_softc *)); 104 void ex_printstats __P((struct ex_softc *)); 105 void ex_tick __P((void *)); 106 107 int ex_enable __P((struct ex_softc *)); 108 void ex_disable __P((struct ex_softc *)); 109 void ex_power __P((int, void *)); 110 111 static int ex_eeprom_busy __P((struct ex_softc *)); 112 static int ex_add_rxbuf __P((struct ex_softc *, struct ex_rxdesc *)); 113 static void ex_init_txdescs __P((struct ex_softc *)); 114 115 static void ex_shutdown __P((void *)); 116 static void ex_start __P((struct ifnet *)); 117 static void ex_txstat __P((struct ex_softc *)); 118 119 int ex_mii_readreg __P((struct device *, int, int)); 120 void ex_mii_writereg __P((struct device *, int, int, int)); 121 void ex_mii_statchg __P((struct device *)); 122 123 void ex_probemedia __P((struct ex_softc *)); 124 125 /* 126 * Structure to map media-present bits in boards to ifmedia codes and 127 * printable media names. Used for table-driven ifmedia initialization. 128 */ 129 struct ex_media { 130 int exm_mpbit; /* media present bit */ 131 const char *exm_name; /* name of medium */ 132 int exm_ifmedia; /* ifmedia word for medium */ 133 int exm_epmedia; /* ELINKMEDIA_* constant */ 134 }; 135 136 /* 137 * Media table for 3c90x chips. Note that chips with MII have no 138 * `native' media. 139 */ 140 struct ex_media ex_native_media[] = { 141 { ELINK_PCI_10BASE_T, "10baseT", IFM_ETHER|IFM_10_T, 142 ELINKMEDIA_10BASE_T }, 143 { ELINK_PCI_10BASE_T, "10baseT-FDX", IFM_ETHER|IFM_10_T|IFM_FDX, 144 ELINKMEDIA_10BASE_T }, 145 { ELINK_PCI_AUI, "10base5", IFM_ETHER|IFM_10_5, 146 ELINKMEDIA_AUI }, 147 { ELINK_PCI_BNC, "10base2", IFM_ETHER|IFM_10_2, 148 ELINKMEDIA_10BASE_2 }, 149 { ELINK_PCI_100BASE_TX, "100baseTX", IFM_ETHER|IFM_100_TX, 150 ELINKMEDIA_100BASE_TX }, 151 { ELINK_PCI_100BASE_TX, "100baseTX-FDX",IFM_ETHER|IFM_100_TX|IFM_FDX, 152 ELINKMEDIA_100BASE_TX }, 153 { ELINK_PCI_100BASE_FX, "100baseFX", IFM_ETHER|IFM_100_FX, 154 ELINKMEDIA_100BASE_FX }, 155 { ELINK_PCI_100BASE_MII,"manual", IFM_ETHER|IFM_MANUAL, 156 ELINKMEDIA_MII }, 157 { ELINK_PCI_100BASE_T4, "100baseT4", IFM_ETHER|IFM_100_T4, 158 ELINKMEDIA_100BASE_T4 }, 159 { 0, NULL, 0, 160 0 }, 161 }; 162 163 /* 164 * MII bit-bang glue. 165 */ 166 u_int32_t ex_mii_bitbang_read __P((struct device *)); 167 void ex_mii_bitbang_write __P((struct device *, u_int32_t)); 168 169 const struct mii_bitbang_ops ex_mii_bitbang_ops = { 170 ex_mii_bitbang_read, 171 ex_mii_bitbang_write, 172 { 173 ELINK_PHY_DATA, /* MII_BIT_MDO */ 174 ELINK_PHY_DATA, /* MII_BIT_MDI */ 175 ELINK_PHY_CLK, /* MII_BIT_MDC */ 176 ELINK_PHY_DIR, /* MII_BIT_DIR_HOST_PHY */ 177 0, /* MII_BIT_DIR_PHY_HOST */ 178 } 179 }; 180 181 /* 182 * Back-end attach and configure. 183 */ 184 void 185 ex_config(sc) 186 struct ex_softc *sc; 187 { 188 struct ifnet *ifp; 189 u_int16_t val; 190 u_int8_t macaddr[ETHER_ADDR_LEN] = {0}; 191 bus_space_tag_t iot = sc->sc_iot; 192 bus_space_handle_t ioh = sc->sc_ioh; 193 int i, error, attach_stage; 194 195 callout_init(&sc->ex_mii_callout); 196 197 ex_reset(sc); 198 199 val = ex_read_eeprom(sc, EEPROM_OEM_ADDR0); 200 macaddr[0] = val >> 8; 201 macaddr[1] = val & 0xff; 202 val = ex_read_eeprom(sc, EEPROM_OEM_ADDR1); 203 macaddr[2] = val >> 8; 204 macaddr[3] = val & 0xff; 205 val = ex_read_eeprom(sc, EEPROM_OEM_ADDR2); 206 macaddr[4] = val >> 8; 207 macaddr[5] = val & 0xff; 208 209 printf("%s: MAC address %s\n", sc->sc_dev.dv_xname, 210 ether_sprintf(macaddr)); 211 212 if (sc->ex_conf & (EX_CONF_INV_LED_POLARITY|EX_CONF_PHY_POWER)) { 213 GO_WINDOW(2); 214 val = bus_space_read_2(iot, ioh, ELINK_W2_RESET_OPTIONS); 215 if (sc->ex_conf & EX_CONF_INV_LED_POLARITY) 216 val |= ELINK_RESET_OPT_LEDPOLAR; 217 if (sc->ex_conf & EX_CONF_PHY_POWER) 218 val |= ELINK_RESET_OPT_PHYPOWER; 219 bus_space_write_2(iot, ioh, ELINK_W2_RESET_OPTIONS, val); 220 } 221 222 attach_stage = 0; 223 224 /* 225 * Allocate the upload descriptors, and create and load the DMA 226 * map for them. 227 */ 228 if ((error = bus_dmamem_alloc(sc->sc_dmat, 229 EX_NUPD * sizeof (struct ex_upd), PAGE_SIZE, 0, &sc->sc_useg, 1, 230 &sc->sc_urseg, BUS_DMA_NOWAIT)) != 0) { 231 printf("%s: can't allocate upload descriptors, error = %d\n", 232 sc->sc_dev.dv_xname, error); 233 goto fail; 234 } 235 236 attach_stage = 1; 237 238 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_useg, sc->sc_urseg, 239 EX_NUPD * sizeof (struct ex_upd), (caddr_t *)&sc->sc_upd, 240 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 241 printf("%s: can't map upload descriptors, error = %d\n", 242 sc->sc_dev.dv_xname, error); 243 goto fail; 244 } 245 246 attach_stage = 2; 247 248 if ((error = bus_dmamap_create(sc->sc_dmat, 249 EX_NUPD * sizeof (struct ex_upd), 1, 250 EX_NUPD * sizeof (struct ex_upd), 0, BUS_DMA_NOWAIT, 251 &sc->sc_upd_dmamap)) != 0) { 252 printf("%s: can't create upload desc. DMA map, error = %d\n", 253 sc->sc_dev.dv_xname, error); 254 goto fail; 255 } 256 257 attach_stage = 3; 258 259 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_upd_dmamap, 260 sc->sc_upd, EX_NUPD * sizeof (struct ex_upd), NULL, 261 BUS_DMA_NOWAIT)) != 0) { 262 printf("%s: can't load upload desc. DMA map, error = %d\n", 263 sc->sc_dev.dv_xname, error); 264 goto fail; 265 } 266 267 attach_stage = 4; 268 269 /* 270 * Allocate the download descriptors, and create and load the DMA 271 * map for them. 272 */ 273 if ((error = bus_dmamem_alloc(sc->sc_dmat, 274 EX_NDPD * sizeof (struct ex_dpd), PAGE_SIZE, 0, &sc->sc_dseg, 1, 275 &sc->sc_drseg, BUS_DMA_NOWAIT)) != 0) { 276 printf("%s: can't allocate download descriptors, error = %d\n", 277 sc->sc_dev.dv_xname, error); 278 goto fail; 279 } 280 281 attach_stage = 5; 282 283 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dseg, sc->sc_drseg, 284 EX_NDPD * sizeof (struct ex_dpd), (caddr_t *)&sc->sc_dpd, 285 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 286 printf("%s: can't map download descriptors, error = %d\n", 287 sc->sc_dev.dv_xname, error); 288 goto fail; 289 } 290 memset(sc->sc_dpd, 0, EX_NDPD * sizeof (struct ex_dpd)); 291 292 attach_stage = 6; 293 294 if ((error = bus_dmamap_create(sc->sc_dmat, 295 EX_NDPD * sizeof (struct ex_dpd), 1, 296 EX_NDPD * sizeof (struct ex_dpd), 0, BUS_DMA_NOWAIT, 297 &sc->sc_dpd_dmamap)) != 0) { 298 printf("%s: can't create download desc. DMA map, error = %d\n", 299 sc->sc_dev.dv_xname, error); 300 goto fail; 301 } 302 303 attach_stage = 7; 304 305 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dpd_dmamap, 306 sc->sc_dpd, EX_NDPD * sizeof (struct ex_dpd), NULL, 307 BUS_DMA_NOWAIT)) != 0) { 308 printf("%s: can't load download desc. DMA map, error = %d\n", 309 sc->sc_dev.dv_xname, error); 310 goto fail; 311 } 312 313 attach_stage = 8; 314 315 316 /* 317 * Create the transmit buffer DMA maps. 318 */ 319 for (i = 0; i < EX_NDPD; i++) { 320 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 321 EX_NTFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 322 &sc->sc_tx_dmamaps[i])) != 0) { 323 printf("%s: can't create tx DMA map %d, error = %d\n", 324 sc->sc_dev.dv_xname, i, error); 325 goto fail; 326 } 327 } 328 329 attach_stage = 9; 330 331 /* 332 * Create the receive buffer DMA maps. 333 */ 334 for (i = 0; i < EX_NUPD; i++) { 335 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 336 EX_NRFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 337 &sc->sc_rx_dmamaps[i])) != 0) { 338 printf("%s: can't create rx DMA map %d, error = %d\n", 339 sc->sc_dev.dv_xname, i, error); 340 goto fail; 341 } 342 } 343 344 attach_stage = 10; 345 346 /* 347 * Create ring of upload descriptors, only once. The DMA engine 348 * will loop over this when receiving packets, stalling if it 349 * hits an UPD with a finished receive. 350 */ 351 for (i = 0; i < EX_NUPD; i++) { 352 sc->sc_rxdescs[i].rx_dmamap = sc->sc_rx_dmamaps[i]; 353 sc->sc_rxdescs[i].rx_upd = &sc->sc_upd[i]; 354 sc->sc_upd[i].upd_frags[0].fr_len = 355 htole32((MCLBYTES - 2) | EX_FR_LAST); 356 if (ex_add_rxbuf(sc, &sc->sc_rxdescs[i]) != 0) { 357 printf("%s: can't allocate or map rx buffers\n", 358 sc->sc_dev.dv_xname); 359 goto fail; 360 } 361 } 362 363 bus_dmamap_sync(sc->sc_dmat, sc->sc_upd_dmamap, 0, 364 EX_NUPD * sizeof (struct ex_upd), 365 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 366 367 ex_init_txdescs(sc); 368 369 attach_stage = 11; 370 371 372 GO_WINDOW(3); 373 val = bus_space_read_2(iot, ioh, ELINK_W3_RESET_OPTIONS); 374 if (val & ELINK_MEDIACAP_MII) 375 sc->ex_conf |= EX_CONF_MII; 376 377 ifp = &sc->sc_ethercom.ec_if; 378 379 /* 380 * Initialize our media structures and MII info. We'll 381 * probe the MII if we discover that we have one. 382 */ 383 sc->ex_mii.mii_ifp = ifp; 384 sc->ex_mii.mii_readreg = ex_mii_readreg; 385 sc->ex_mii.mii_writereg = ex_mii_writereg; 386 sc->ex_mii.mii_statchg = ex_mii_statchg; 387 ifmedia_init(&sc->ex_mii.mii_media, 0, ex_media_chg, 388 ex_media_stat); 389 390 if (sc->ex_conf & EX_CONF_MII) { 391 /* 392 * Find PHY, extract media information from it. 393 * First, select the right transceiver. 394 */ 395 u_int32_t icfg; 396 397 GO_WINDOW(3); 398 icfg = bus_space_read_4(iot, ioh, ELINK_W3_INTERNAL_CONFIG); 399 icfg &= ~(CONFIG_XCVR_SEL << 16); 400 if (val & (ELINK_MEDIACAP_MII | ELINK_MEDIACAP_100BASET4)) 401 icfg |= ELINKMEDIA_MII << (CONFIG_XCVR_SEL_SHIFT + 16); 402 if (val & ELINK_MEDIACAP_100BASETX) 403 icfg |= ELINKMEDIA_AUTO << (CONFIG_XCVR_SEL_SHIFT + 16); 404 if (val & ELINK_MEDIACAP_100BASEFX) 405 icfg |= ELINKMEDIA_100BASE_FX 406 << (CONFIG_XCVR_SEL_SHIFT + 16); 407 bus_space_write_4(iot, ioh, ELINK_W3_INTERNAL_CONFIG, icfg); 408 409 mii_attach(&sc->sc_dev, &sc->ex_mii, 0xffffffff, 410 MII_PHY_ANY, MII_OFFSET_ANY, 0); 411 if (LIST_FIRST(&sc->ex_mii.mii_phys) == NULL) { 412 ifmedia_add(&sc->ex_mii.mii_media, IFM_ETHER|IFM_NONE, 413 0, NULL); 414 ifmedia_set(&sc->ex_mii.mii_media, IFM_ETHER|IFM_NONE); 415 } else { 416 ifmedia_set(&sc->ex_mii.mii_media, IFM_ETHER|IFM_AUTO); 417 } 418 } else 419 ex_probemedia(sc); 420 421 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 422 ifp->if_softc = sc; 423 ifp->if_start = ex_start; 424 ifp->if_ioctl = ex_ioctl; 425 ifp->if_watchdog = ex_watchdog; 426 ifp->if_init = ex_init; 427 ifp->if_stop = ex_stop; 428 ifp->if_flags = 429 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 430 IFQ_SET_READY(&ifp->if_snd); 431 432 /* 433 * We can support 802.1Q VLAN-sized frames. 434 */ 435 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 436 437 /* 438 * The 3c90xB has hardware IPv4/TCPv4/UDPv4 checksum support. 439 */ 440 if (sc->ex_conf & EX_CONF_90XB) 441 sc->sc_ethercom.ec_if.if_capabilities |= IFCAP_CSUM_IPv4 | 442 IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 443 444 if_attach(ifp); 445 ether_ifattach(ifp, macaddr); 446 447 GO_WINDOW(1); 448 449 sc->tx_start_thresh = 20; 450 sc->tx_succ_ok = 0; 451 452 /* TODO: set queues to 0 */ 453 454 #if NRND > 0 455 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 456 RND_TYPE_NET, 0); 457 #endif 458 459 /* Establish callback to reset card when we reboot. */ 460 sc->sc_sdhook = shutdownhook_establish(ex_shutdown, sc); 461 if (sc->sc_sdhook == NULL) 462 printf("%s: WARNING: unable to establish shutdown hook\n", 463 sc->sc_dev.dv_xname); 464 465 /* Add a suspend hook to make sure we come back up after a resume. */ 466 sc->sc_powerhook = powerhook_establish(ex_power, sc); 467 if (sc->sc_powerhook == NULL) 468 printf("%s: WARNING: unable to establish power hook\n", 469 sc->sc_dev.dv_xname); 470 471 /* The attach is successful. */ 472 sc->ex_flags |= EX_FLAGS_ATTACHED; 473 return; 474 475 fail: 476 /* 477 * Free any resources we've allocated during the failed attach 478 * attempt. Do this in reverse order and fall though. 479 */ 480 switch (attach_stage) { 481 case 11: 482 { 483 struct ex_rxdesc *rxd; 484 485 for (i = 0; i < EX_NUPD; i++) { 486 rxd = &sc->sc_rxdescs[i]; 487 if (rxd->rx_mbhead != NULL) { 488 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 489 m_freem(rxd->rx_mbhead); 490 } 491 } 492 } 493 /* FALLTHROUGH */ 494 495 case 10: 496 for (i = 0; i < EX_NUPD; i++) 497 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rx_dmamaps[i]); 498 /* FALLTHROUGH */ 499 500 case 9: 501 for (i = 0; i < EX_NDPD; i++) 502 bus_dmamap_destroy(sc->sc_dmat, sc->sc_tx_dmamaps[i]); 503 /* FALLTHROUGH */ 504 case 8: 505 bus_dmamap_unload(sc->sc_dmat, sc->sc_dpd_dmamap); 506 /* FALLTHROUGH */ 507 508 case 7: 509 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dpd_dmamap); 510 /* FALLTHROUGH */ 511 512 case 6: 513 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_dpd, 514 EX_NDPD * sizeof (struct ex_dpd)); 515 /* FALLTHROUGH */ 516 517 case 5: 518 bus_dmamem_free(sc->sc_dmat, &sc->sc_dseg, sc->sc_drseg); 519 break; 520 521 case 4: 522 bus_dmamap_unload(sc->sc_dmat, sc->sc_upd_dmamap); 523 /* FALLTHROUGH */ 524 525 case 3: 526 bus_dmamap_destroy(sc->sc_dmat, sc->sc_upd_dmamap); 527 /* FALLTHROUGH */ 528 529 case 2: 530 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_upd, 531 EX_NUPD * sizeof (struct ex_upd)); 532 /* FALLTHROUGH */ 533 534 case 1: 535 bus_dmamem_free(sc->sc_dmat, &sc->sc_useg, sc->sc_urseg); 536 break; 537 } 538 539 } 540 541 /* 542 * Find the media present on non-MII chips. 543 */ 544 void 545 ex_probemedia(sc) 546 struct ex_softc *sc; 547 { 548 bus_space_tag_t iot = sc->sc_iot; 549 bus_space_handle_t ioh = sc->sc_ioh; 550 struct ifmedia *ifm = &sc->ex_mii.mii_media; 551 struct ex_media *exm; 552 u_int16_t config1, reset_options, default_media; 553 int defmedia = 0; 554 const char *sep = "", *defmedianame = NULL; 555 556 GO_WINDOW(3); 557 config1 = bus_space_read_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG + 2); 558 reset_options = bus_space_read_1(iot, ioh, ELINK_W3_RESET_OPTIONS); 559 GO_WINDOW(0); 560 561 default_media = (config1 & CONFIG_MEDIAMASK) >> CONFIG_MEDIAMASK_SHIFT; 562 563 printf("%s: ", sc->sc_dev.dv_xname); 564 565 /* Sanity check that there are any media! */ 566 if ((reset_options & ELINK_PCI_MEDIAMASK) == 0) { 567 printf("no media present!\n"); 568 ifmedia_add(ifm, IFM_ETHER|IFM_NONE, 0, NULL); 569 ifmedia_set(ifm, IFM_ETHER|IFM_NONE); 570 return; 571 } 572 573 #define PRINT(str) printf("%s%s", sep, str); sep = ", " 574 575 for (exm = ex_native_media; exm->exm_name != NULL; exm++) { 576 if (reset_options & exm->exm_mpbit) { 577 /* 578 * Default media is a little complicated. We 579 * support full-duplex which uses the same 580 * reset options bit. 581 * 582 * XXX Check EEPROM for default to FDX? 583 */ 584 if (exm->exm_epmedia == default_media) { 585 if ((exm->exm_ifmedia & IFM_FDX) == 0) { 586 defmedia = exm->exm_ifmedia; 587 defmedianame = exm->exm_name; 588 } 589 } else if (defmedia == 0) { 590 defmedia = exm->exm_ifmedia; 591 defmedianame = exm->exm_name; 592 } 593 ifmedia_add(ifm, exm->exm_ifmedia, exm->exm_epmedia, 594 NULL); 595 PRINT(exm->exm_name); 596 } 597 } 598 599 #undef PRINT 600 601 #ifdef DIAGNOSTIC 602 if (defmedia == 0) 603 panic("ex_probemedia: impossible"); 604 #endif 605 606 printf(", default %s\n", defmedianame); 607 ifmedia_set(ifm, defmedia); 608 } 609 610 /* 611 * Bring device up. 612 */ 613 int 614 ex_init(ifp) 615 struct ifnet *ifp; 616 { 617 struct ex_softc *sc = ifp->if_softc; 618 bus_space_tag_t iot = sc->sc_iot; 619 bus_space_handle_t ioh = sc->sc_ioh; 620 int i; 621 int error = 0; 622 623 if ((error = ex_enable(sc)) != 0) 624 goto out; 625 626 ex_waitcmd(sc); 627 ex_stop(ifp, 0); 628 629 /* 630 * Set the station address and clear the station mask. The latter 631 * is needed for 90x cards, 0 is the default for 90xB cards. 632 */ 633 GO_WINDOW(2); 634 for (i = 0; i < ETHER_ADDR_LEN; i++) { 635 bus_space_write_1(iot, ioh, ELINK_W2_ADDR_0 + i, 636 LLADDR(ifp->if_sadl)[i]); 637 bus_space_write_1(iot, ioh, ELINK_W2_RECVMASK_0 + i, 0); 638 } 639 640 GO_WINDOW(3); 641 642 bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_RESET); 643 ex_waitcmd(sc); 644 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_RESET); 645 ex_waitcmd(sc); 646 647 /* 648 * Disable reclaim threshold for 90xB, set free threshold to 649 * 6 * 256 = 1536 for 90x. 650 */ 651 if (sc->ex_conf & EX_CONF_90XB) 652 bus_space_write_2(iot, ioh, ELINK_COMMAND, 653 ELINK_TXRECLTHRESH | 255); 654 else 655 bus_space_write_1(iot, ioh, ELINK_TXFREETHRESH, 6); 656 657 bus_space_write_2(iot, ioh, ELINK_COMMAND, 658 SET_RX_EARLY_THRESH | ELINK_THRESH_DISABLE); 659 660 bus_space_write_4(iot, ioh, ELINK_DMACTRL, 661 bus_space_read_4(iot, ioh, ELINK_DMACTRL) | ELINK_DMAC_UPRXEAREN); 662 663 bus_space_write_2(iot, ioh, ELINK_COMMAND, 664 SET_RD_0_MASK | XL_WATCHED_INTERRUPTS); 665 bus_space_write_2(iot, ioh, ELINK_COMMAND, 666 SET_INTR_MASK | XL_WATCHED_INTERRUPTS); 667 668 bus_space_write_2(iot, ioh, ELINK_COMMAND, ACK_INTR | 0xff); 669 if (sc->intr_ack) 670 (* sc->intr_ack)(sc); 671 ex_set_media(sc); 672 ex_set_mc(sc); 673 674 675 bus_space_write_2(iot, ioh, ELINK_COMMAND, STATS_ENABLE); 676 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_ENABLE); 677 bus_space_write_4(iot, ioh, ELINK_UPLISTPTR, sc->sc_upddma); 678 bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_ENABLE); 679 bus_space_write_2(iot, ioh, ELINK_COMMAND, ELINK_UPUNSTALL); 680 681 if (sc->ex_conf & (EX_CONF_PHY_POWER | EX_CONF_INV_LED_POLARITY)) { 682 u_int16_t cbcard_config; 683 684 GO_WINDOW(2); 685 cbcard_config = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 0x0c); 686 if (sc->ex_conf & EX_CONF_PHY_POWER) { 687 cbcard_config |= 0x4000; /* turn on PHY power */ 688 } 689 if (sc->ex_conf & EX_CONF_INV_LED_POLARITY) { 690 cbcard_config |= 0x0010; /* invert LED polarity */ 691 } 692 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 0x0c, cbcard_config); 693 694 GO_WINDOW(3); 695 } 696 697 ifp->if_flags |= IFF_RUNNING; 698 ifp->if_flags &= ~IFF_OACTIVE; 699 ex_start(ifp); 700 701 GO_WINDOW(1); 702 703 callout_reset(&sc->ex_mii_callout, hz, ex_tick, sc); 704 705 out: 706 if (error) { 707 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 708 ifp->if_timer = 0; 709 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 710 } 711 return (error); 712 } 713 714 #define MCHASHSIZE 256 715 #define ex_mchash(addr) (ether_crc32_be((addr), ETHER_ADDR_LEN) & \ 716 (MCHASHSIZE - 1)) 717 718 /* 719 * Set multicast receive filter. Also take care of promiscuous mode 720 * here (XXX). 721 */ 722 void 723 ex_set_mc(sc) 724 struct ex_softc *sc; 725 { 726 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 727 struct ethercom *ec = &sc->sc_ethercom; 728 struct ether_multi *enm; 729 struct ether_multistep estep; 730 int i; 731 u_int16_t mask = FIL_INDIVIDUAL | FIL_BRDCST; 732 733 if (ifp->if_flags & IFF_PROMISC) { 734 mask |= FIL_PROMISC; 735 goto allmulti; 736 } 737 738 ETHER_FIRST_MULTI(estep, ec, enm); 739 if (enm == NULL) 740 goto nomulti; 741 742 if ((sc->ex_conf & EX_CONF_90XB) == 0) 743 /* No multicast hash filtering. */ 744 goto allmulti; 745 746 for (i = 0; i < MCHASHSIZE; i++) 747 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 748 ELINK_COMMAND, ELINK_CLEARHASHFILBIT | i); 749 750 do { 751 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 752 ETHER_ADDR_LEN) != 0) 753 goto allmulti; 754 755 i = ex_mchash(enm->enm_addrlo); 756 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 757 ELINK_COMMAND, ELINK_SETHASHFILBIT | i); 758 ETHER_NEXT_MULTI(estep, enm); 759 } while (enm != NULL); 760 mask |= FIL_MULTIHASH; 761 762 nomulti: 763 ifp->if_flags &= ~IFF_ALLMULTI; 764 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_COMMAND, 765 SET_RX_FILTER | mask); 766 return; 767 768 allmulti: 769 ifp->if_flags |= IFF_ALLMULTI; 770 mask |= FIL_MULTICAST; 771 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_COMMAND, 772 SET_RX_FILTER | mask); 773 } 774 775 776 static void 777 ex_txstat(sc) 778 struct ex_softc *sc; 779 { 780 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 781 bus_space_tag_t iot = sc->sc_iot; 782 bus_space_handle_t ioh = sc->sc_ioh; 783 int i; 784 785 /* 786 * We need to read+write TX_STATUS until we get a 0 status 787 * in order to turn off the interrupt flag. 788 */ 789 while ((i = bus_space_read_1(iot, ioh, ELINK_TXSTATUS)) & TXS_COMPLETE) { 790 bus_space_write_1(iot, ioh, ELINK_TXSTATUS, 0x0); 791 792 if (i & TXS_JABBER) { 793 ++sc->sc_ethercom.ec_if.if_oerrors; 794 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 795 printf("%s: jabber (%x)\n", 796 sc->sc_dev.dv_xname, i); 797 ex_init(ifp); 798 /* TODO: be more subtle here */ 799 } else if (i & TXS_UNDERRUN) { 800 ++sc->sc_ethercom.ec_if.if_oerrors; 801 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 802 printf("%s: fifo underrun (%x) @%d\n", 803 sc->sc_dev.dv_xname, i, 804 sc->tx_start_thresh); 805 if (sc->tx_succ_ok < 100) 806 sc->tx_start_thresh = min(ETHER_MAX_LEN, 807 sc->tx_start_thresh + 20); 808 sc->tx_succ_ok = 0; 809 ex_init(ifp); 810 /* TODO: be more subtle here */ 811 } else if (i & TXS_MAX_COLLISION) { 812 ++sc->sc_ethercom.ec_if.if_collisions; 813 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_ENABLE); 814 sc->sc_ethercom.ec_if.if_flags &= ~IFF_OACTIVE; 815 } else 816 sc->tx_succ_ok = (sc->tx_succ_ok+1) & 127; 817 } 818 } 819 820 int 821 ex_media_chg(ifp) 822 struct ifnet *ifp; 823 { 824 825 if (ifp->if_flags & IFF_UP) 826 ex_init(ifp); 827 return 0; 828 } 829 830 void 831 ex_set_media(sc) 832 struct ex_softc *sc; 833 { 834 bus_space_tag_t iot = sc->sc_iot; 835 bus_space_handle_t ioh = sc->sc_ioh; 836 u_int32_t configreg; 837 838 if (((sc->ex_conf & EX_CONF_MII) && 839 (sc->ex_mii.mii_media_active & IFM_FDX)) 840 || (!(sc->ex_conf & EX_CONF_MII) && 841 (sc->ex_mii.mii_media.ifm_media & IFM_FDX))) { 842 bus_space_write_2(iot, ioh, ELINK_W3_MAC_CONTROL, 843 MAC_CONTROL_FDX); 844 } else { 845 bus_space_write_2(iot, ioh, ELINK_W3_MAC_CONTROL, 0); 846 } 847 848 /* 849 * If the device has MII, select it, and then tell the 850 * PHY which media to use. 851 */ 852 if (sc->ex_conf & EX_CONF_MII) { 853 GO_WINDOW(3); 854 855 configreg = bus_space_read_4(iot, ioh, ELINK_W3_INTERNAL_CONFIG); 856 857 configreg &= ~(CONFIG_MEDIAMASK << 16); 858 configreg |= (ELINKMEDIA_MII << (CONFIG_MEDIAMASK_SHIFT + 16)); 859 860 bus_space_write_4(iot, ioh, ELINK_W3_INTERNAL_CONFIG, configreg); 861 mii_mediachg(&sc->ex_mii); 862 return; 863 } 864 865 GO_WINDOW(4); 866 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 0); 867 bus_space_write_2(iot, ioh, ELINK_COMMAND, STOP_TRANSCEIVER); 868 delay(800); 869 870 /* 871 * Now turn on the selected media/transceiver. 872 */ 873 switch (IFM_SUBTYPE(sc->ex_mii.mii_media.ifm_cur->ifm_media)) { 874 case IFM_10_T: 875 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 876 JABBER_GUARD_ENABLE|LINKBEAT_ENABLE); 877 break; 878 879 case IFM_10_2: 880 bus_space_write_2(iot, ioh, ELINK_COMMAND, START_TRANSCEIVER); 881 DELAY(800); 882 break; 883 884 case IFM_100_TX: 885 case IFM_100_FX: 886 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 887 LINKBEAT_ENABLE); 888 DELAY(800); 889 break; 890 891 case IFM_10_5: 892 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 893 SQE_ENABLE); 894 DELAY(800); 895 break; 896 897 case IFM_MANUAL: 898 break; 899 900 case IFM_NONE: 901 return; 902 903 default: 904 panic("ex_set_media: impossible"); 905 } 906 907 GO_WINDOW(3); 908 configreg = bus_space_read_4(iot, ioh, ELINK_W3_INTERNAL_CONFIG); 909 910 configreg &= ~(CONFIG_MEDIAMASK << 16); 911 configreg |= (sc->ex_mii.mii_media.ifm_cur->ifm_data << 912 (CONFIG_MEDIAMASK_SHIFT + 16)); 913 914 bus_space_write_4(iot, ioh, ELINK_W3_INTERNAL_CONFIG, configreg); 915 } 916 917 /* 918 * Get currently-selected media from card. 919 * (if_media callback, may be called before interface is brought up). 920 */ 921 void 922 ex_media_stat(ifp, req) 923 struct ifnet *ifp; 924 struct ifmediareq *req; 925 { 926 struct ex_softc *sc = ifp->if_softc; 927 928 if (sc->ex_conf & EX_CONF_MII) { 929 mii_pollstat(&sc->ex_mii); 930 req->ifm_status = sc->ex_mii.mii_media_status; 931 req->ifm_active = sc->ex_mii.mii_media_active; 932 } else { 933 GO_WINDOW(4); 934 req->ifm_status = IFM_AVALID; 935 req->ifm_active = sc->ex_mii.mii_media.ifm_cur->ifm_media; 936 if (bus_space_read_2(sc->sc_iot, sc->sc_ioh, 937 ELINK_W4_MEDIA_TYPE) & LINKBEAT_DETECT) 938 req->ifm_status |= IFM_ACTIVE; 939 GO_WINDOW(1); 940 } 941 } 942 943 944 945 /* 946 * Start outputting on the interface. 947 */ 948 static void 949 ex_start(ifp) 950 struct ifnet *ifp; 951 { 952 struct ex_softc *sc = ifp->if_softc; 953 bus_space_tag_t iot = sc->sc_iot; 954 bus_space_handle_t ioh = sc->sc_ioh; 955 volatile struct ex_fraghdr *fr = NULL; 956 volatile struct ex_dpd *dpd = NULL, *prevdpd = NULL; 957 struct ex_txdesc *txp; 958 struct mbuf *mb_head; 959 bus_dmamap_t dmamap; 960 int offset, totlen, segment, error; 961 u_int32_t csum_flags; 962 963 if (sc->tx_head || sc->tx_free == NULL) 964 return; 965 966 txp = NULL; 967 968 /* 969 * We're finished if there is nothing more to add to the list or if 970 * we're all filled up with buffers to transmit. 971 */ 972 while (sc->tx_free != NULL) { 973 /* 974 * Grab a packet to transmit. 975 */ 976 IFQ_DEQUEUE(&ifp->if_snd, mb_head); 977 if (mb_head == NULL) 978 break; 979 980 /* 981 * Get pointer to next available tx desc. 982 */ 983 txp = sc->tx_free; 984 dmamap = txp->tx_dmamap; 985 986 /* 987 * Go through each of the mbufs in the chain and initialize 988 * the transmit buffer descriptors with the physical address 989 * and size of the mbuf. 990 */ 991 reload: 992 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 993 mb_head, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 994 switch (error) { 995 case 0: 996 /* Success. */ 997 break; 998 999 case EFBIG: 1000 { 1001 struct mbuf *mn; 1002 1003 /* 1004 * We ran out of segments. We have to recopy this 1005 * mbuf chain first. Bail out if we can't get the 1006 * new buffers. 1007 */ 1008 printf("%s: too many segments, ", sc->sc_dev.dv_xname); 1009 1010 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1011 if (mn == NULL) { 1012 m_freem(mb_head); 1013 printf("aborting\n"); 1014 goto out; 1015 } 1016 if (mb_head->m_pkthdr.len > MHLEN) { 1017 MCLGET(mn, M_DONTWAIT); 1018 if ((mn->m_flags & M_EXT) == 0) { 1019 m_freem(mn); 1020 m_freem(mb_head); 1021 printf("aborting\n"); 1022 goto out; 1023 } 1024 } 1025 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1026 mtod(mn, caddr_t)); 1027 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1028 m_freem(mb_head); 1029 mb_head = mn; 1030 printf("retrying\n"); 1031 goto reload; 1032 } 1033 1034 default: 1035 /* 1036 * Some other problem; report it. 1037 */ 1038 printf("%s: can't load mbuf chain, error = %d\n", 1039 sc->sc_dev.dv_xname, error); 1040 m_freem(mb_head); 1041 goto out; 1042 } 1043 1044 /* 1045 * remove our tx desc from freelist. 1046 */ 1047 sc->tx_free = txp->tx_next; 1048 txp->tx_next = NULL; 1049 1050 fr = &txp->tx_dpd->dpd_frags[0]; 1051 totlen = 0; 1052 for (segment = 0; segment < dmamap->dm_nsegs; segment++, fr++) { 1053 fr->fr_addr = htole32(dmamap->dm_segs[segment].ds_addr); 1054 fr->fr_len = htole32(dmamap->dm_segs[segment].ds_len); 1055 totlen += dmamap->dm_segs[segment].ds_len; 1056 } 1057 fr--; 1058 fr->fr_len |= htole32(EX_FR_LAST); 1059 txp->tx_mbhead = mb_head; 1060 1061 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1062 BUS_DMASYNC_PREWRITE); 1063 1064 dpd = txp->tx_dpd; 1065 dpd->dpd_nextptr = 0; 1066 dpd->dpd_fsh = htole32(totlen); 1067 1068 /* Byte-swap constants so compiler can optimize. */ 1069 1070 if (sc->ex_conf & EX_CONF_90XB) { 1071 csum_flags = 0; 1072 1073 if (mb_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 1074 csum_flags |= htole32(EX_DPD_IPCKSUM); 1075 1076 if (mb_head->m_pkthdr.csum_flags & M_CSUM_TCPv4) 1077 csum_flags |= htole32(EX_DPD_TCPCKSUM); 1078 else if (mb_head->m_pkthdr.csum_flags & M_CSUM_UDPv4) 1079 csum_flags |= htole32(EX_DPD_UDPCKSUM); 1080 1081 dpd->dpd_fsh |= csum_flags; 1082 } else { 1083 KDASSERT((mb_head->m_pkthdr.csum_flags & 1084 (M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4)) == 0); 1085 } 1086 1087 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap, 1088 ((caddr_t)dpd - (caddr_t)sc->sc_dpd), 1089 sizeof (struct ex_dpd), 1090 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1091 1092 /* 1093 * No need to stall the download engine, we know it's 1094 * not busy right now. 1095 * 1096 * Fix up pointers in both the "soft" tx and the physical 1097 * tx list. 1098 */ 1099 if (sc->tx_head != NULL) { 1100 prevdpd = sc->tx_tail->tx_dpd; 1101 offset = ((caddr_t)prevdpd - (caddr_t)sc->sc_dpd); 1102 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap, 1103 offset, sizeof (struct ex_dpd), 1104 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1105 prevdpd->dpd_nextptr = htole32(DPD_DMADDR(sc, txp)); 1106 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap, 1107 offset, sizeof (struct ex_dpd), 1108 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1109 sc->tx_tail->tx_next = txp; 1110 sc->tx_tail = txp; 1111 } else { 1112 sc->tx_tail = sc->tx_head = txp; 1113 } 1114 1115 #if NBPFILTER > 0 1116 /* 1117 * Pass packet to bpf if there is a listener. 1118 */ 1119 if (ifp->if_bpf) 1120 bpf_mtap(ifp->if_bpf, mb_head); 1121 #endif 1122 } 1123 out: 1124 if (sc->tx_head) { 1125 sc->tx_tail->tx_dpd->dpd_fsh |= htole32(EX_DPD_DNIND); 1126 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap, 1127 ((caddr_t)sc->tx_tail->tx_dpd - (caddr_t)sc->sc_dpd), 1128 sizeof (struct ex_dpd), 1129 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1130 ifp->if_flags |= IFF_OACTIVE; 1131 bus_space_write_2(iot, ioh, ELINK_COMMAND, ELINK_DNUNSTALL); 1132 bus_space_write_4(iot, ioh, ELINK_DNLISTPTR, 1133 DPD_DMADDR(sc, sc->tx_head)); 1134 1135 /* trigger watchdog */ 1136 ifp->if_timer = 5; 1137 } 1138 } 1139 1140 1141 int 1142 ex_intr(arg) 1143 void *arg; 1144 { 1145 struct ex_softc *sc = arg; 1146 bus_space_tag_t iot = sc->sc_iot; 1147 bus_space_handle_t ioh = sc->sc_ioh; 1148 u_int16_t stat; 1149 int ret = 0; 1150 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1151 1152 if ((ifp->if_flags & IFF_RUNNING) == 0 || 1153 (sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1154 return (0); 1155 1156 for (;;) { 1157 stat = bus_space_read_2(iot, ioh, ELINK_STATUS); 1158 1159 if ((stat & XL_WATCHED_INTERRUPTS) == 0) { 1160 if ((stat & INTR_LATCH) == 0) { 1161 #if 0 1162 printf("%s: intr latch cleared\n", 1163 sc->sc_dev.dv_xname); 1164 #endif 1165 break; 1166 } 1167 } 1168 1169 ret = 1; 1170 1171 /* 1172 * Acknowledge interrupts. 1173 */ 1174 bus_space_write_2(iot, ioh, ELINK_COMMAND, ACK_INTR | 1175 (stat & (XL_WATCHED_INTERRUPTS | INTR_LATCH))); 1176 if (sc->intr_ack) 1177 (*sc->intr_ack)(sc); 1178 1179 if (stat & HOST_ERROR) { 1180 printf("%s: adapter failure (%x)\n", 1181 sc->sc_dev.dv_xname, stat); 1182 ex_reset(sc); 1183 ex_init(ifp); 1184 return 1; 1185 } 1186 if (stat & TX_COMPLETE) { 1187 ex_txstat(sc); 1188 } 1189 if (stat & UPD_STATS) { 1190 ex_getstats(sc); 1191 } 1192 if (stat & DN_COMPLETE) { 1193 struct ex_txdesc *txp, *ptxp = NULL; 1194 bus_dmamap_t txmap; 1195 1196 /* reset watchdog timer, was set in ex_start() */ 1197 ifp->if_timer = 0; 1198 1199 for (txp = sc->tx_head; txp != NULL; 1200 txp = txp->tx_next) { 1201 bus_dmamap_sync(sc->sc_dmat, 1202 sc->sc_dpd_dmamap, 1203 (caddr_t)txp->tx_dpd - (caddr_t)sc->sc_dpd, 1204 sizeof (struct ex_dpd), 1205 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1206 if (txp->tx_mbhead != NULL) { 1207 txmap = txp->tx_dmamap; 1208 bus_dmamap_sync(sc->sc_dmat, txmap, 1209 0, txmap->dm_mapsize, 1210 BUS_DMASYNC_POSTWRITE); 1211 bus_dmamap_unload(sc->sc_dmat, txmap); 1212 m_freem(txp->tx_mbhead); 1213 txp->tx_mbhead = NULL; 1214 } 1215 ptxp = txp; 1216 } 1217 1218 /* 1219 * Move finished tx buffers back to the tx free list. 1220 */ 1221 if (sc->tx_free) { 1222 sc->tx_ftail->tx_next = sc->tx_head; 1223 sc->tx_ftail = ptxp; 1224 } else 1225 sc->tx_ftail = sc->tx_free = sc->tx_head; 1226 1227 sc->tx_head = sc->tx_tail = NULL; 1228 ifp->if_flags &= ~IFF_OACTIVE; 1229 } 1230 1231 if (stat & UP_COMPLETE) { 1232 struct ex_rxdesc *rxd; 1233 struct mbuf *m; 1234 struct ex_upd *upd; 1235 bus_dmamap_t rxmap; 1236 u_int32_t pktstat; 1237 1238 rcvloop: 1239 rxd = sc->rx_head; 1240 rxmap = rxd->rx_dmamap; 1241 m = rxd->rx_mbhead; 1242 upd = rxd->rx_upd; 1243 1244 bus_dmamap_sync(sc->sc_dmat, rxmap, 0, 1245 rxmap->dm_mapsize, 1246 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1247 bus_dmamap_sync(sc->sc_dmat, sc->sc_upd_dmamap, 1248 ((caddr_t)upd - (caddr_t)sc->sc_upd), 1249 sizeof (struct ex_upd), 1250 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1251 pktstat = le32toh(upd->upd_pktstatus); 1252 1253 if (pktstat & EX_UPD_COMPLETE) { 1254 /* 1255 * Remove first packet from the chain. 1256 */ 1257 sc->rx_head = rxd->rx_next; 1258 rxd->rx_next = NULL; 1259 1260 /* 1261 * Add a new buffer to the receive chain. 1262 * If this fails, the old buffer is recycled 1263 * instead. 1264 */ 1265 if (ex_add_rxbuf(sc, rxd) == 0) { 1266 u_int16_t total_len; 1267 1268 if (pktstat & 1269 ((sc->sc_ethercom.ec_capenable & 1270 ETHERCAP_VLAN_MTU) ? 1271 EX_UPD_ERR_VLAN : EX_UPD_ERR)) { 1272 ifp->if_ierrors++; 1273 m_freem(m); 1274 goto rcvloop; 1275 } 1276 1277 total_len = pktstat & EX_UPD_PKTLENMASK; 1278 if (total_len < 1279 sizeof(struct ether_header)) { 1280 m_freem(m); 1281 goto rcvloop; 1282 } 1283 m->m_pkthdr.rcvif = ifp; 1284 m->m_pkthdr.len = m->m_len = total_len; 1285 #if NBPFILTER > 0 1286 if (ifp->if_bpf) 1287 bpf_mtap(ifp->if_bpf, m); 1288 #endif 1289 /* 1290 * Set the incoming checksum information for the packet. 1291 */ 1292 if ((sc->ex_conf & EX_CONF_90XB) != 0 && 1293 (pktstat & EX_UPD_IPCHECKED) != 0) { 1294 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1295 if (pktstat & EX_UPD_IPCKSUMERR) 1296 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1297 if (pktstat & EX_UPD_TCPCHECKED) { 1298 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1299 if (pktstat & EX_UPD_TCPCKSUMERR) 1300 m->m_pkthdr.csum_flags |= 1301 M_CSUM_TCP_UDP_BAD; 1302 } else if (pktstat & EX_UPD_UDPCHECKED) { 1303 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1304 if (pktstat & EX_UPD_UDPCKSUMERR) 1305 m->m_pkthdr.csum_flags |= 1306 M_CSUM_TCP_UDP_BAD; 1307 } 1308 } 1309 (*ifp->if_input)(ifp, m); 1310 } 1311 goto rcvloop; 1312 } 1313 /* 1314 * Just in case we filled up all UPDs and the DMA engine 1315 * stalled. We could be more subtle about this. 1316 */ 1317 if (bus_space_read_4(iot, ioh, ELINK_UPLISTPTR) == 0) { 1318 printf("%s: uplistptr was 0\n", 1319 sc->sc_dev.dv_xname); 1320 ex_init(ifp); 1321 } else if (bus_space_read_4(iot, ioh, ELINK_UPPKTSTATUS) 1322 & 0x2000) { 1323 printf("%s: receive stalled\n", 1324 sc->sc_dev.dv_xname); 1325 bus_space_write_2(iot, ioh, ELINK_COMMAND, 1326 ELINK_UPUNSTALL); 1327 } 1328 } 1329 } 1330 1331 /* no more interrupts */ 1332 if (ret && IFQ_IS_EMPTY(&ifp->if_snd) == 0) 1333 ex_start(ifp); 1334 return ret; 1335 } 1336 1337 int 1338 ex_ioctl(ifp, cmd, data) 1339 struct ifnet *ifp; 1340 u_long cmd; 1341 caddr_t data; 1342 { 1343 struct ex_softc *sc = ifp->if_softc; 1344 struct ifreq *ifr = (struct ifreq *)data; 1345 int s, error; 1346 1347 s = splnet(); 1348 1349 switch (cmd) { 1350 case SIOCSIFMEDIA: 1351 case SIOCGIFMEDIA: 1352 error = ifmedia_ioctl(ifp, ifr, &sc->ex_mii.mii_media, cmd); 1353 break; 1354 1355 default: 1356 error = ether_ioctl(ifp, cmd, data); 1357 if (error == ENETRESET) { 1358 if (sc->enabled) { 1359 /* 1360 * Multicast list has changed; set the hardware filter 1361 * accordingly. 1362 */ 1363 ex_set_mc(sc); 1364 } 1365 error = 0; 1366 } 1367 break; 1368 } 1369 1370 splx(s); 1371 return (error); 1372 } 1373 1374 void 1375 ex_getstats(sc) 1376 struct ex_softc *sc; 1377 { 1378 bus_space_handle_t ioh = sc->sc_ioh; 1379 bus_space_tag_t iot = sc->sc_iot; 1380 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1381 u_int8_t upperok; 1382 1383 GO_WINDOW(6); 1384 upperok = bus_space_read_1(iot, ioh, UPPER_FRAMES_OK); 1385 ifp->if_ipackets += bus_space_read_1(iot, ioh, RX_FRAMES_OK); 1386 ifp->if_ipackets += (upperok & 0x03) << 8; 1387 ifp->if_opackets += bus_space_read_1(iot, ioh, TX_FRAMES_OK); 1388 ifp->if_opackets += (upperok & 0x30) << 4; 1389 ifp->if_ierrors += bus_space_read_1(iot, ioh, RX_OVERRUNS); 1390 ifp->if_collisions += bus_space_read_1(iot, ioh, TX_COLLISIONS); 1391 /* 1392 * There seems to be no way to get the exact number of collisions, 1393 * this is the number that occurred at the very least. 1394 */ 1395 ifp->if_collisions += 2 * bus_space_read_1(iot, ioh, 1396 TX_AFTER_X_COLLISIONS); 1397 /* 1398 * Interface byte counts are counted by ether_input() and 1399 * ether_output(), so don't accumulate them here. Just 1400 * read the NIC counters so they don't generate overflow interrupts. 1401 * Upper byte counters are latched from reading the totals, so 1402 * they don't need to be read if we don't need their values. 1403 */ 1404 bus_space_read_2(iot, ioh, RX_TOTAL_OK); 1405 bus_space_read_2(iot, ioh, TX_TOTAL_OK); 1406 1407 /* 1408 * Clear the following to avoid stats overflow interrupts 1409 */ 1410 bus_space_read_1(iot, ioh, TX_DEFERRALS); 1411 bus_space_read_1(iot, ioh, TX_AFTER_1_COLLISION); 1412 bus_space_read_1(iot, ioh, TX_NO_SQE); 1413 bus_space_read_1(iot, ioh, TX_CD_LOST); 1414 GO_WINDOW(4); 1415 bus_space_read_1(iot, ioh, ELINK_W4_BADSSD); 1416 GO_WINDOW(1); 1417 } 1418 1419 void 1420 ex_printstats(sc) 1421 struct ex_softc *sc; 1422 { 1423 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1424 1425 ex_getstats(sc); 1426 printf("in %llu out %llu ierror %llu oerror %llu ibytes %llu obytes " 1427 "%llu\n", (unsigned long long)ifp->if_ipackets, 1428 (unsigned long long)ifp->if_opackets, 1429 (unsigned long long)ifp->if_ierrors, 1430 (unsigned long long)ifp->if_oerrors, 1431 (unsigned long long)ifp->if_ibytes, 1432 (unsigned long long)ifp->if_obytes); 1433 } 1434 1435 void 1436 ex_tick(arg) 1437 void *arg; 1438 { 1439 struct ex_softc *sc = arg; 1440 int s; 1441 1442 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1443 return; 1444 1445 s = splnet(); 1446 1447 if (sc->ex_conf & EX_CONF_MII) 1448 mii_tick(&sc->ex_mii); 1449 1450 if (!(bus_space_read_2((sc)->sc_iot, (sc)->sc_ioh, ELINK_STATUS) 1451 & COMMAND_IN_PROGRESS)) 1452 ex_getstats(sc); 1453 1454 splx(s); 1455 1456 callout_reset(&sc->ex_mii_callout, hz, ex_tick, sc); 1457 } 1458 1459 void 1460 ex_reset(sc) 1461 struct ex_softc *sc; 1462 { 1463 u_int16_t val = GLOBAL_RESET; 1464 1465 if (sc->ex_conf & EX_CONF_RESETHACK) 1466 val |= 0x10; 1467 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_COMMAND, val); 1468 /* 1469 * XXX apparently the command in progress bit can't be trusted 1470 * during a reset, so we just always wait this long. Fortunately 1471 * we normally only reset the chip during autoconfig. 1472 */ 1473 delay(100000); 1474 ex_waitcmd(sc); 1475 } 1476 1477 void 1478 ex_watchdog(ifp) 1479 struct ifnet *ifp; 1480 { 1481 struct ex_softc *sc = ifp->if_softc; 1482 1483 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1484 ++sc->sc_ethercom.ec_if.if_oerrors; 1485 1486 ex_reset(sc); 1487 ex_init(ifp); 1488 } 1489 1490 void 1491 ex_stop(ifp, disable) 1492 struct ifnet *ifp; 1493 int disable; 1494 { 1495 struct ex_softc *sc = ifp->if_softc; 1496 bus_space_tag_t iot = sc->sc_iot; 1497 bus_space_handle_t ioh = sc->sc_ioh; 1498 struct ex_txdesc *tx; 1499 struct ex_rxdesc *rx; 1500 int i; 1501 1502 bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_DISABLE); 1503 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_DISABLE); 1504 bus_space_write_2(iot, ioh, ELINK_COMMAND, STOP_TRANSCEIVER); 1505 1506 for (tx = sc->tx_head ; tx != NULL; tx = tx->tx_next) { 1507 if (tx->tx_mbhead == NULL) 1508 continue; 1509 m_freem(tx->tx_mbhead); 1510 tx->tx_mbhead = NULL; 1511 bus_dmamap_unload(sc->sc_dmat, tx->tx_dmamap); 1512 tx->tx_dpd->dpd_fsh = tx->tx_dpd->dpd_nextptr = 0; 1513 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap, 1514 ((caddr_t)tx->tx_dpd - (caddr_t)sc->sc_dpd), 1515 sizeof (struct ex_dpd), 1516 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1517 } 1518 sc->tx_tail = sc->tx_head = NULL; 1519 ex_init_txdescs(sc); 1520 1521 sc->rx_tail = sc->rx_head = 0; 1522 for (i = 0; i < EX_NUPD; i++) { 1523 rx = &sc->sc_rxdescs[i]; 1524 if (rx->rx_mbhead != NULL) { 1525 bus_dmamap_unload(sc->sc_dmat, rx->rx_dmamap); 1526 m_freem(rx->rx_mbhead); 1527 rx->rx_mbhead = NULL; 1528 } 1529 ex_add_rxbuf(sc, rx); 1530 } 1531 1532 bus_space_write_2(iot, ioh, ELINK_COMMAND, ACK_INTR | INTR_LATCH); 1533 1534 callout_stop(&sc->ex_mii_callout); 1535 if (sc->ex_conf & EX_CONF_MII) 1536 mii_down(&sc->ex_mii); 1537 1538 if (disable) 1539 ex_disable(sc); 1540 1541 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1542 ifp->if_timer = 0; 1543 } 1544 1545 static void 1546 ex_init_txdescs(sc) 1547 struct ex_softc *sc; 1548 { 1549 int i; 1550 1551 for (i = 0; i < EX_NDPD; i++) { 1552 sc->sc_txdescs[i].tx_dmamap = sc->sc_tx_dmamaps[i]; 1553 sc->sc_txdescs[i].tx_dpd = &sc->sc_dpd[i]; 1554 if (i < EX_NDPD - 1) 1555 sc->sc_txdescs[i].tx_next = &sc->sc_txdescs[i + 1]; 1556 else 1557 sc->sc_txdescs[i].tx_next = NULL; 1558 } 1559 sc->tx_free = &sc->sc_txdescs[0]; 1560 sc->tx_ftail = &sc->sc_txdescs[EX_NDPD-1]; 1561 } 1562 1563 1564 int 1565 ex_activate(self, act) 1566 struct device *self; 1567 enum devact act; 1568 { 1569 struct ex_softc *sc = (void *) self; 1570 int s, error = 0; 1571 1572 s = splnet(); 1573 switch (act) { 1574 case DVACT_ACTIVATE: 1575 error = EOPNOTSUPP; 1576 break; 1577 1578 case DVACT_DEACTIVATE: 1579 if (sc->ex_conf & EX_CONF_MII) 1580 mii_activate(&sc->ex_mii, act, MII_PHY_ANY, 1581 MII_OFFSET_ANY); 1582 if_deactivate(&sc->sc_ethercom.ec_if); 1583 break; 1584 } 1585 splx(s); 1586 1587 return (error); 1588 } 1589 1590 int 1591 ex_detach(sc) 1592 struct ex_softc *sc; 1593 { 1594 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1595 struct ex_rxdesc *rxd; 1596 int i; 1597 1598 /* Succeed now if there's no work to do. */ 1599 if ((sc->ex_flags & EX_FLAGS_ATTACHED) == 0) 1600 return (0); 1601 1602 /* Unhook our tick handler. */ 1603 callout_stop(&sc->ex_mii_callout); 1604 1605 if (sc->ex_conf & EX_CONF_MII) { 1606 /* Detach all PHYs */ 1607 mii_detach(&sc->ex_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1608 } 1609 1610 /* Delete all remaining media. */ 1611 ifmedia_delete_instance(&sc->ex_mii.mii_media, IFM_INST_ANY); 1612 1613 #if NRND > 0 1614 rnd_detach_source(&sc->rnd_source); 1615 #endif 1616 ether_ifdetach(ifp); 1617 if_detach(ifp); 1618 1619 for (i = 0; i < EX_NUPD; i++) { 1620 rxd = &sc->sc_rxdescs[i]; 1621 if (rxd->rx_mbhead != NULL) { 1622 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 1623 m_freem(rxd->rx_mbhead); 1624 rxd->rx_mbhead = NULL; 1625 } 1626 } 1627 for (i = 0; i < EX_NUPD; i++) 1628 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rx_dmamaps[i]); 1629 for (i = 0; i < EX_NDPD; i++) 1630 bus_dmamap_destroy(sc->sc_dmat, sc->sc_tx_dmamaps[i]); 1631 bus_dmamap_unload(sc->sc_dmat, sc->sc_dpd_dmamap); 1632 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dpd_dmamap); 1633 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_dpd, 1634 EX_NDPD * sizeof (struct ex_dpd)); 1635 bus_dmamem_free(sc->sc_dmat, &sc->sc_dseg, sc->sc_drseg); 1636 bus_dmamap_unload(sc->sc_dmat, sc->sc_upd_dmamap); 1637 bus_dmamap_destroy(sc->sc_dmat, sc->sc_upd_dmamap); 1638 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_upd, 1639 EX_NUPD * sizeof (struct ex_upd)); 1640 bus_dmamem_free(sc->sc_dmat, &sc->sc_useg, sc->sc_urseg); 1641 1642 shutdownhook_disestablish(sc->sc_sdhook); 1643 powerhook_disestablish(sc->sc_powerhook); 1644 1645 return (0); 1646 } 1647 1648 /* 1649 * Before reboots, reset card completely. 1650 */ 1651 static void 1652 ex_shutdown(arg) 1653 void *arg; 1654 { 1655 struct ex_softc *sc = arg; 1656 1657 ex_stop(&sc->sc_ethercom.ec_if, 1); 1658 } 1659 1660 /* 1661 * Read EEPROM data. 1662 * XXX what to do if EEPROM doesn't unbusy? 1663 */ 1664 u_int16_t 1665 ex_read_eeprom(sc, offset) 1666 struct ex_softc *sc; 1667 int offset; 1668 { 1669 bus_space_tag_t iot = sc->sc_iot; 1670 bus_space_handle_t ioh = sc->sc_ioh; 1671 u_int16_t data = 0, cmd = READ_EEPROM; 1672 int off; 1673 1674 off = sc->ex_conf & EX_CONF_EEPROM_OFF ? 0x30 : 0; 1675 cmd = sc->ex_conf & EX_CONF_EEPROM_8BIT ? READ_EEPROM8 : READ_EEPROM; 1676 1677 GO_WINDOW(0); 1678 if (ex_eeprom_busy(sc)) 1679 goto out; 1680 bus_space_write_2(iot, ioh, ELINK_W0_EEPROM_COMMAND, 1681 cmd | (off + (offset & 0x3f))); 1682 if (ex_eeprom_busy(sc)) 1683 goto out; 1684 data = bus_space_read_2(iot, ioh, ELINK_W0_EEPROM_DATA); 1685 out: 1686 return data; 1687 } 1688 1689 static int 1690 ex_eeprom_busy(sc) 1691 struct ex_softc *sc; 1692 { 1693 bus_space_tag_t iot = sc->sc_iot; 1694 bus_space_handle_t ioh = sc->sc_ioh; 1695 int i = 100; 1696 1697 while (i--) { 1698 if (!(bus_space_read_2(iot, ioh, ELINK_W0_EEPROM_COMMAND) & 1699 EEPROM_BUSY)) 1700 return 0; 1701 delay(100); 1702 } 1703 printf("\n%s: eeprom stays busy.\n", sc->sc_dev.dv_xname); 1704 return (1); 1705 } 1706 1707 /* 1708 * Create a new rx buffer and add it to the 'soft' rx list. 1709 */ 1710 static int 1711 ex_add_rxbuf(sc, rxd) 1712 struct ex_softc *sc; 1713 struct ex_rxdesc *rxd; 1714 { 1715 struct mbuf *m, *oldm; 1716 bus_dmamap_t rxmap; 1717 int error, rval = 0; 1718 1719 oldm = rxd->rx_mbhead; 1720 rxmap = rxd->rx_dmamap; 1721 1722 MGETHDR(m, M_DONTWAIT, MT_DATA); 1723 if (m != NULL) { 1724 MCLGET(m, M_DONTWAIT); 1725 if ((m->m_flags & M_EXT) == 0) { 1726 m_freem(m); 1727 if (oldm == NULL) 1728 return 1; 1729 m = oldm; 1730 m->m_data = m->m_ext.ext_buf; 1731 rval = 1; 1732 } 1733 } else { 1734 if (oldm == NULL) 1735 return 1; 1736 m = oldm; 1737 m->m_data = m->m_ext.ext_buf; 1738 rval = 1; 1739 } 1740 1741 /* 1742 * Setup the DMA map for this receive buffer. 1743 */ 1744 if (m != oldm) { 1745 if (oldm != NULL) 1746 bus_dmamap_unload(sc->sc_dmat, rxmap); 1747 error = bus_dmamap_load(sc->sc_dmat, rxmap, 1748 m->m_ext.ext_buf, MCLBYTES, NULL, 1749 BUS_DMA_READ|BUS_DMA_NOWAIT); 1750 if (error) { 1751 printf("%s: can't load rx buffer, error = %d\n", 1752 sc->sc_dev.dv_xname, error); 1753 panic("ex_add_rxbuf"); /* XXX */ 1754 } 1755 } 1756 1757 /* 1758 * Align for data after 14 byte header. 1759 */ 1760 m->m_data += 2; 1761 1762 rxd->rx_mbhead = m; 1763 rxd->rx_upd->upd_pktstatus = htole32(MCLBYTES - 2); 1764 rxd->rx_upd->upd_frags[0].fr_addr = 1765 htole32(rxmap->dm_segs[0].ds_addr + 2); 1766 rxd->rx_upd->upd_nextptr = 0; 1767 1768 /* 1769 * Attach it to the end of the list. 1770 */ 1771 if (sc->rx_head != NULL) { 1772 sc->rx_tail->rx_next = rxd; 1773 sc->rx_tail->rx_upd->upd_nextptr = htole32(sc->sc_upddma + 1774 ((caddr_t)rxd->rx_upd - (caddr_t)sc->sc_upd)); 1775 bus_dmamap_sync(sc->sc_dmat, sc->sc_upd_dmamap, 1776 (caddr_t)sc->rx_tail->rx_upd - (caddr_t)sc->sc_upd, 1777 sizeof (struct ex_upd), 1778 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1779 } else { 1780 sc->rx_head = rxd; 1781 } 1782 sc->rx_tail = rxd; 1783 1784 bus_dmamap_sync(sc->sc_dmat, rxmap, 0, rxmap->dm_mapsize, 1785 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1786 bus_dmamap_sync(sc->sc_dmat, sc->sc_upd_dmamap, 1787 ((caddr_t)rxd->rx_upd - (caddr_t)sc->sc_upd), 1788 sizeof (struct ex_upd), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1789 return (rval); 1790 } 1791 1792 u_int32_t 1793 ex_mii_bitbang_read(self) 1794 struct device *self; 1795 { 1796 struct ex_softc *sc = (void *) self; 1797 1798 /* We're already in Window 4. */ 1799 return (bus_space_read_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_PHYSMGMT)); 1800 } 1801 1802 void 1803 ex_mii_bitbang_write(self, val) 1804 struct device *self; 1805 u_int32_t val; 1806 { 1807 struct ex_softc *sc = (void *) self; 1808 1809 /* We're already in Window 4. */ 1810 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_PHYSMGMT, val); 1811 } 1812 1813 int 1814 ex_mii_readreg(v, phy, reg) 1815 struct device *v; 1816 int phy, reg; 1817 { 1818 struct ex_softc *sc = (struct ex_softc *)v; 1819 int val; 1820 1821 if ((sc->ex_conf & EX_CONF_INTPHY) && phy != ELINK_INTPHY_ID) 1822 return 0; 1823 1824 GO_WINDOW(4); 1825 1826 val = mii_bitbang_readreg(v, &ex_mii_bitbang_ops, phy, reg); 1827 1828 GO_WINDOW(1); 1829 1830 return (val); 1831 } 1832 1833 void 1834 ex_mii_writereg(v, phy, reg, data) 1835 struct device *v; 1836 int phy; 1837 int reg; 1838 int data; 1839 { 1840 struct ex_softc *sc = (struct ex_softc *)v; 1841 1842 GO_WINDOW(4); 1843 1844 mii_bitbang_writereg(v, &ex_mii_bitbang_ops, phy, reg, data); 1845 1846 GO_WINDOW(1); 1847 } 1848 1849 void 1850 ex_mii_statchg(v) 1851 struct device *v; 1852 { 1853 struct ex_softc *sc = (struct ex_softc *)v; 1854 bus_space_tag_t iot = sc->sc_iot; 1855 bus_space_handle_t ioh = sc->sc_ioh; 1856 int mctl; 1857 1858 GO_WINDOW(3); 1859 mctl = bus_space_read_2(iot, ioh, ELINK_W3_MAC_CONTROL); 1860 if (sc->ex_mii.mii_media_active & IFM_FDX) 1861 mctl |= MAC_CONTROL_FDX; 1862 else 1863 mctl &= ~MAC_CONTROL_FDX; 1864 bus_space_write_2(iot, ioh, ELINK_W3_MAC_CONTROL, mctl); 1865 GO_WINDOW(1); /* back to operating window */ 1866 } 1867 1868 int 1869 ex_enable(sc) 1870 struct ex_softc *sc; 1871 { 1872 if (sc->enabled == 0 && sc->enable != NULL) { 1873 if ((*sc->enable)(sc) != 0) { 1874 printf("%s: de/vice enable failed\n", 1875 sc->sc_dev.dv_xname); 1876 return (EIO); 1877 } 1878 sc->enabled = 1; 1879 } 1880 return (0); 1881 } 1882 1883 void 1884 ex_disable(sc) 1885 struct ex_softc *sc; 1886 { 1887 if (sc->enabled == 1 && sc->disable != NULL) { 1888 (*sc->disable)(sc); 1889 sc->enabled = 0; 1890 } 1891 } 1892 1893 void 1894 ex_power(why, arg) 1895 int why; 1896 void *arg; 1897 { 1898 struct ex_softc *sc = (void *)arg; 1899 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1900 int s; 1901 1902 s = splnet(); 1903 switch (why) { 1904 case PWR_SUSPEND: 1905 case PWR_STANDBY: 1906 ex_stop(ifp, 0); 1907 if (sc->power != NULL) 1908 (*sc->power)(sc, why); 1909 break; 1910 case PWR_RESUME: 1911 if (ifp->if_flags & IFF_UP) { 1912 if (sc->power != NULL) 1913 (*sc->power)(sc, why); 1914 ex_init(ifp); 1915 } 1916 break; 1917 case PWR_SOFTSUSPEND: 1918 case PWR_SOFTSTANDBY: 1919 case PWR_SOFTRESUME: 1920 break; 1921 } 1922 splx(s); 1923 } 1924
Indexes created Wed Oct 22 13:09:56 GMT 2025