elinkxl.c revision 1.75.6.1
1 /* $NetBSD: elinkxl.c,v 1.75.6.1 2005/02/12 18:17:43 yamt Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: elinkxl.c,v 1.75.6.1 2005/02/12 18:17:43 yamt Exp $"); 41 42 #include "bpfilter.h" 43 #include "rnd.h" 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/callout.h> 48 #include <sys/kernel.h> 49 #include <sys/mbuf.h> 50 #include <sys/socket.h> 51 #include <sys/ioctl.h> 52 #include <sys/errno.h> 53 #include <sys/syslog.h> 54 #include <sys/select.h> 55 #include <sys/device.h> 56 #if NRND > 0 57 #include <sys/rnd.h> 58 #endif 59 60 #include <uvm/uvm_extern.h> 61 62 #include <net/if.h> 63 #include <net/if_dl.h> 64 #include <net/if_ether.h> 65 #include <net/if_media.h> 66 67 #if NBPFILTER > 0 68 #include <net/bpf.h> 69 #include <net/bpfdesc.h> 70 #endif 71 72 #include <machine/cpu.h> 73 #include <machine/bus.h> 74 #include <machine/intr.h> 75 #include <machine/endian.h> 76 77 #include <dev/mii/miivar.h> 78 #include <dev/mii/mii.h> 79 #include <dev/mii/mii_bitbang.h> 80 81 #include <dev/ic/elink3reg.h> 82 /* #include <dev/ic/elink3var.h> */ 83 #include <dev/ic/elinkxlreg.h> 84 #include <dev/ic/elinkxlvar.h> 85 86 #ifdef DEBUG 87 int exdebug = 0; 88 #endif 89 90 /* ifmedia callbacks */ 91 int ex_media_chg(struct ifnet *ifp); 92 void ex_media_stat(struct ifnet *ifp, struct ifmediareq *req); 93 94 void ex_probe_media(struct ex_softc *); 95 void ex_set_filter(struct ex_softc *); 96 void ex_set_media(struct ex_softc *); 97 void ex_set_xcvr(struct ex_softc *, u_int16_t); 98 struct mbuf *ex_get(struct ex_softc *, int); 99 u_int16_t ex_read_eeprom(struct ex_softc *, int); 100 int ex_init(struct ifnet *); 101 void ex_read(struct ex_softc *); 102 void ex_reset(struct ex_softc *); 103 void ex_set_mc(struct ex_softc *); 104 void ex_getstats(struct ex_softc *); 105 void ex_printstats(struct ex_softc *); 106 void ex_tick(void *); 107 108 void ex_power(int, void *); 109 110 static int ex_eeprom_busy(struct ex_softc *); 111 static int ex_add_rxbuf(struct ex_softc *, struct ex_rxdesc *); 112 static void ex_init_txdescs(struct ex_softc *); 113 114 static void ex_shutdown(void *); 115 static void ex_start(struct ifnet *); 116 static void ex_txstat(struct ex_softc *); 117 118 int ex_mii_readreg(struct device *, int, int); 119 void ex_mii_writereg(struct device *, int, int, int); 120 void ex_mii_statchg(struct device *); 121 122 void ex_probemedia(struct ex_softc *); 123 124 /* 125 * Structure to map media-present bits in boards to ifmedia codes and 126 * printable media names. Used for table-driven ifmedia initialization. 127 */ 128 struct ex_media { 129 int exm_mpbit; /* media present bit */ 130 const char *exm_name; /* name of medium */ 131 int exm_ifmedia; /* ifmedia word for medium */ 132 int exm_epmedia; /* ELINKMEDIA_* constant */ 133 }; 134 135 /* 136 * Media table for 3c90x chips. Note that chips with MII have no 137 * `native' media. 138 */ 139 struct ex_media ex_native_media[] = { 140 { ELINK_PCI_10BASE_T, "10baseT", IFM_ETHER|IFM_10_T, 141 ELINKMEDIA_10BASE_T }, 142 { ELINK_PCI_10BASE_T, "10baseT-FDX", IFM_ETHER|IFM_10_T|IFM_FDX, 143 ELINKMEDIA_10BASE_T }, 144 { ELINK_PCI_AUI, "10base5", IFM_ETHER|IFM_10_5, 145 ELINKMEDIA_AUI }, 146 { ELINK_PCI_BNC, "10base2", IFM_ETHER|IFM_10_2, 147 ELINKMEDIA_10BASE_2 }, 148 { ELINK_PCI_100BASE_TX, "100baseTX", IFM_ETHER|IFM_100_TX, 149 ELINKMEDIA_100BASE_TX }, 150 { ELINK_PCI_100BASE_TX, "100baseTX-FDX",IFM_ETHER|IFM_100_TX|IFM_FDX, 151 ELINKMEDIA_100BASE_TX }, 152 { ELINK_PCI_100BASE_FX, "100baseFX", IFM_ETHER|IFM_100_FX, 153 ELINKMEDIA_100BASE_FX }, 154 { ELINK_PCI_100BASE_MII,"manual", IFM_ETHER|IFM_MANUAL, 155 ELINKMEDIA_MII }, 156 { ELINK_PCI_100BASE_T4, "100baseT4", IFM_ETHER|IFM_100_T4, 157 ELINKMEDIA_100BASE_T4 }, 158 { 0, NULL, 0, 159 0 }, 160 }; 161 162 /* 163 * MII bit-bang glue. 164 */ 165 u_int32_t ex_mii_bitbang_read(struct device *); 166 void ex_mii_bitbang_write(struct device *, u_int32_t); 167 168 const struct mii_bitbang_ops ex_mii_bitbang_ops = { 169 ex_mii_bitbang_read, 170 ex_mii_bitbang_write, 171 { 172 ELINK_PHY_DATA, /* MII_BIT_MDO */ 173 ELINK_PHY_DATA, /* MII_BIT_MDI */ 174 ELINK_PHY_CLK, /* MII_BIT_MDC */ 175 ELINK_PHY_DIR, /* MII_BIT_DIR_HOST_PHY */ 176 0, /* MII_BIT_DIR_PHY_HOST */ 177 } 178 }; 179 180 /* 181 * Back-end attach and configure. 182 */ 183 void 184 ex_config(sc) 185 struct ex_softc *sc; 186 { 187 struct ifnet *ifp; 188 u_int16_t val; 189 u_int8_t macaddr[ETHER_ADDR_LEN] = {0}; 190 bus_space_tag_t iot = sc->sc_iot; 191 bus_space_handle_t ioh = sc->sc_ioh; 192 int i, error, attach_stage; 193 194 callout_init(&sc->ex_mii_callout); 195 196 ex_reset(sc); 197 198 val = ex_read_eeprom(sc, EEPROM_OEM_ADDR0); 199 macaddr[0] = val >> 8; 200 macaddr[1] = val & 0xff; 201 val = ex_read_eeprom(sc, EEPROM_OEM_ADDR1); 202 macaddr[2] = val >> 8; 203 macaddr[3] = val & 0xff; 204 val = ex_read_eeprom(sc, EEPROM_OEM_ADDR2); 205 macaddr[4] = val >> 8; 206 macaddr[5] = val & 0xff; 207 208 aprint_normal("%s: MAC address %s\n", sc->sc_dev.dv_xname, 209 ether_sprintf(macaddr)); 210 211 if (sc->ex_conf & (EX_CONF_INV_LED_POLARITY|EX_CONF_PHY_POWER)) { 212 GO_WINDOW(2); 213 val = bus_space_read_2(iot, ioh, ELINK_W2_RESET_OPTIONS); 214 if (sc->ex_conf & EX_CONF_INV_LED_POLARITY) 215 val |= ELINK_RESET_OPT_LEDPOLAR; 216 if (sc->ex_conf & EX_CONF_PHY_POWER) 217 val |= ELINK_RESET_OPT_PHYPOWER; 218 bus_space_write_2(iot, ioh, ELINK_W2_RESET_OPTIONS, val); 219 } 220 if (sc->ex_conf & EX_CONF_NO_XCVR_PWR) { 221 GO_WINDOW(0); 222 bus_space_write_2(iot, ioh, ELINK_W0_MFG_ID, 223 EX_XCVR_PWR_MAGICBITS); 224 } 225 226 attach_stage = 0; 227 228 /* 229 * Allocate the upload descriptors, and create and load the DMA 230 * map for them. 231 */ 232 if ((error = bus_dmamem_alloc(sc->sc_dmat, 233 EX_NUPD * sizeof (struct ex_upd), PAGE_SIZE, 0, &sc->sc_useg, 1, 234 &sc->sc_urseg, BUS_DMA_NOWAIT)) != 0) { 235 aprint_error( 236 "%s: can't allocate upload descriptors, error = %d\n", 237 sc->sc_dev.dv_xname, error); 238 goto fail; 239 } 240 241 attach_stage = 1; 242 243 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_useg, sc->sc_urseg, 244 EX_NUPD * sizeof (struct ex_upd), (caddr_t *)&sc->sc_upd, 245 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 246 aprint_error("%s: can't map upload descriptors, error = %d\n", 247 sc->sc_dev.dv_xname, error); 248 goto fail; 249 } 250 251 attach_stage = 2; 252 253 if ((error = bus_dmamap_create(sc->sc_dmat, 254 EX_NUPD * sizeof (struct ex_upd), 1, 255 EX_NUPD * sizeof (struct ex_upd), 0, BUS_DMA_NOWAIT, 256 &sc->sc_upd_dmamap)) != 0) { 257 aprint_error( 258 "%s: can't create upload desc. DMA map, error = %d\n", 259 sc->sc_dev.dv_xname, error); 260 goto fail; 261 } 262 263 attach_stage = 3; 264 265 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_upd_dmamap, 266 sc->sc_upd, EX_NUPD * sizeof (struct ex_upd), NULL, 267 BUS_DMA_NOWAIT)) != 0) { 268 aprint_error( 269 "%s: can't load upload desc. DMA map, error = %d\n", 270 sc->sc_dev.dv_xname, error); 271 goto fail; 272 } 273 274 attach_stage = 4; 275 276 /* 277 * Allocate the download descriptors, and create and load the DMA 278 * map for them. 279 */ 280 if ((error = bus_dmamem_alloc(sc->sc_dmat, 281 EX_NDPD * sizeof (struct ex_dpd), PAGE_SIZE, 0, &sc->sc_dseg, 1, 282 &sc->sc_drseg, BUS_DMA_NOWAIT)) != 0) { 283 aprint_error( 284 "%s: can't allocate download descriptors, error = %d\n", 285 sc->sc_dev.dv_xname, error); 286 goto fail; 287 } 288 289 attach_stage = 5; 290 291 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dseg, sc->sc_drseg, 292 EX_NDPD * sizeof (struct ex_dpd), (caddr_t *)&sc->sc_dpd, 293 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 294 aprint_error("%s: can't map download descriptors, error = %d\n", 295 sc->sc_dev.dv_xname, error); 296 goto fail; 297 } 298 memset(sc->sc_dpd, 0, EX_NDPD * sizeof (struct ex_dpd)); 299 300 attach_stage = 6; 301 302 if ((error = bus_dmamap_create(sc->sc_dmat, 303 EX_NDPD * sizeof (struct ex_dpd), 1, 304 EX_NDPD * sizeof (struct ex_dpd), 0, BUS_DMA_NOWAIT, 305 &sc->sc_dpd_dmamap)) != 0) { 306 aprint_error( 307 "%s: can't create download desc. DMA map, error = %d\n", 308 sc->sc_dev.dv_xname, error); 309 goto fail; 310 } 311 312 attach_stage = 7; 313 314 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dpd_dmamap, 315 sc->sc_dpd, EX_NDPD * sizeof (struct ex_dpd), NULL, 316 BUS_DMA_NOWAIT)) != 0) { 317 aprint_error( 318 "%s: can't load download desc. DMA map, error = %d\n", 319 sc->sc_dev.dv_xname, error); 320 goto fail; 321 } 322 323 attach_stage = 8; 324 325 326 /* 327 * Create the transmit buffer DMA maps. 328 */ 329 for (i = 0; i < EX_NDPD; i++) { 330 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 331 EX_NTFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 332 &sc->sc_tx_dmamaps[i])) != 0) { 333 aprint_error( 334 "%s: can't create tx DMA map %d, error = %d\n", 335 sc->sc_dev.dv_xname, i, error); 336 goto fail; 337 } 338 } 339 340 attach_stage = 9; 341 342 /* 343 * Create the receive buffer DMA maps. 344 */ 345 for (i = 0; i < EX_NUPD; i++) { 346 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 347 EX_NRFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 348 &sc->sc_rx_dmamaps[i])) != 0) { 349 aprint_error( 350 "%s: can't create rx DMA map %d, error = %d\n", 351 sc->sc_dev.dv_xname, i, error); 352 goto fail; 353 } 354 } 355 356 attach_stage = 10; 357 358 /* 359 * Create ring of upload descriptors, only once. The DMA engine 360 * will loop over this when receiving packets, stalling if it 361 * hits an UPD with a finished receive. 362 */ 363 for (i = 0; i < EX_NUPD; i++) { 364 sc->sc_rxdescs[i].rx_dmamap = sc->sc_rx_dmamaps[i]; 365 sc->sc_rxdescs[i].rx_upd = &sc->sc_upd[i]; 366 sc->sc_upd[i].upd_frags[0].fr_len = 367 htole32((MCLBYTES - 2) | EX_FR_LAST); 368 if (ex_add_rxbuf(sc, &sc->sc_rxdescs[i]) != 0) { 369 aprint_error("%s: can't allocate or map rx buffers\n", 370 sc->sc_dev.dv_xname); 371 goto fail; 372 } 373 } 374 375 bus_dmamap_sync(sc->sc_dmat, sc->sc_upd_dmamap, 0, 376 EX_NUPD * sizeof (struct ex_upd), 377 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 378 379 ex_init_txdescs(sc); 380 381 attach_stage = 11; 382 383 384 GO_WINDOW(3); 385 val = bus_space_read_2(iot, ioh, ELINK_W3_RESET_OPTIONS); 386 if (val & ELINK_MEDIACAP_MII) 387 sc->ex_conf |= EX_CONF_MII; 388 389 ifp = &sc->sc_ethercom.ec_if; 390 391 /* 392 * Initialize our media structures and MII info. We'll 393 * probe the MII if we discover that we have one. 394 */ 395 sc->ex_mii.mii_ifp = ifp; 396 sc->ex_mii.mii_readreg = ex_mii_readreg; 397 sc->ex_mii.mii_writereg = ex_mii_writereg; 398 sc->ex_mii.mii_statchg = ex_mii_statchg; 399 ifmedia_init(&sc->ex_mii.mii_media, IFM_IMASK, ex_media_chg, 400 ex_media_stat); 401 402 if (sc->ex_conf & EX_CONF_MII) { 403 /* 404 * Find PHY, extract media information from it. 405 * First, select the right transceiver. 406 */ 407 ex_set_xcvr(sc, val); 408 409 mii_attach(&sc->sc_dev, &sc->ex_mii, 0xffffffff, 410 MII_PHY_ANY, MII_OFFSET_ANY, 0); 411 if (LIST_FIRST(&sc->ex_mii.mii_phys) == NULL) { 412 ifmedia_add(&sc->ex_mii.mii_media, IFM_ETHER|IFM_NONE, 413 0, NULL); 414 ifmedia_set(&sc->ex_mii.mii_media, IFM_ETHER|IFM_NONE); 415 } else { 416 ifmedia_set(&sc->ex_mii.mii_media, IFM_ETHER|IFM_AUTO); 417 } 418 } else 419 ex_probemedia(sc); 420 421 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 422 ifp->if_softc = sc; 423 ifp->if_start = ex_start; 424 ifp->if_ioctl = ex_ioctl; 425 ifp->if_watchdog = ex_watchdog; 426 ifp->if_init = ex_init; 427 ifp->if_stop = ex_stop; 428 ifp->if_flags = 429 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 430 sc->sc_if_flags = ifp->if_flags; 431 IFQ_SET_READY(&ifp->if_snd); 432 433 /* 434 * We can support 802.1Q VLAN-sized frames. 435 */ 436 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 437 438 /* 439 * The 3c90xB has hardware IPv4/TCPv4/UDPv4 checksum support. 440 */ 441 if (sc->ex_conf & EX_CONF_90XB) 442 sc->sc_ethercom.ec_if.if_capabilities |= IFCAP_CSUM_IPv4 | 443 IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 444 445 if_attach(ifp); 446 ether_ifattach(ifp, macaddr); 447 448 GO_WINDOW(1); 449 450 sc->tx_start_thresh = 20; 451 sc->tx_succ_ok = 0; 452 453 /* TODO: set queues to 0 */ 454 455 #if NRND > 0 456 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 457 RND_TYPE_NET, 0); 458 #endif 459 460 /* Establish callback to reset card when we reboot. */ 461 sc->sc_sdhook = shutdownhook_establish(ex_shutdown, sc); 462 if (sc->sc_sdhook == NULL) 463 aprint_error("%s: WARNING: unable to establish shutdown hook\n", 464 sc->sc_dev.dv_xname); 465 466 /* Add a suspend hook to make sure we come back up after a resume. */ 467 sc->sc_powerhook = powerhook_establish(ex_power, sc); 468 if (sc->sc_powerhook == NULL) 469 aprint_error("%s: WARNING: unable to establish power hook\n", 470 sc->sc_dev.dv_xname); 471 472 /* The attach is successful. */ 473 sc->ex_flags |= EX_FLAGS_ATTACHED; 474 return; 475 476 fail: 477 /* 478 * Free any resources we've allocated during the failed attach 479 * attempt. Do this in reverse order and fall though. 480 */ 481 switch (attach_stage) { 482 case 11: 483 { 484 struct ex_rxdesc *rxd; 485 486 for (i = 0; i < EX_NUPD; i++) { 487 rxd = &sc->sc_rxdescs[i]; 488 if (rxd->rx_mbhead != NULL) { 489 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 490 m_freem(rxd->rx_mbhead); 491 } 492 } 493 } 494 /* FALLTHROUGH */ 495 496 case 10: 497 for (i = 0; i < EX_NUPD; i++) 498 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rx_dmamaps[i]); 499 /* FALLTHROUGH */ 500 501 case 9: 502 for (i = 0; i < EX_NDPD; i++) 503 bus_dmamap_destroy(sc->sc_dmat, sc->sc_tx_dmamaps[i]); 504 /* FALLTHROUGH */ 505 case 8: 506 bus_dmamap_unload(sc->sc_dmat, sc->sc_dpd_dmamap); 507 /* FALLTHROUGH */ 508 509 case 7: 510 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dpd_dmamap); 511 /* FALLTHROUGH */ 512 513 case 6: 514 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_dpd, 515 EX_NDPD * sizeof (struct ex_dpd)); 516 /* FALLTHROUGH */ 517 518 case 5: 519 bus_dmamem_free(sc->sc_dmat, &sc->sc_dseg, sc->sc_drseg); 520 break; 521 522 case 4: 523 bus_dmamap_unload(sc->sc_dmat, sc->sc_upd_dmamap); 524 /* FALLTHROUGH */ 525 526 case 3: 527 bus_dmamap_destroy(sc->sc_dmat, sc->sc_upd_dmamap); 528 /* FALLTHROUGH */ 529 530 case 2: 531 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_upd, 532 EX_NUPD * sizeof (struct ex_upd)); 533 /* FALLTHROUGH */ 534 535 case 1: 536 bus_dmamem_free(sc->sc_dmat, &sc->sc_useg, sc->sc_urseg); 537 break; 538 } 539 540 } 541 542 /* 543 * Find the media present on non-MII chips. 544 */ 545 void 546 ex_probemedia(sc) 547 struct ex_softc *sc; 548 { 549 bus_space_tag_t iot = sc->sc_iot; 550 bus_space_handle_t ioh = sc->sc_ioh; 551 struct ifmedia *ifm = &sc->ex_mii.mii_media; 552 struct ex_media *exm; 553 u_int16_t config1, reset_options, default_media; 554 int defmedia = 0; 555 const char *sep = "", *defmedianame = NULL; 556 557 GO_WINDOW(3); 558 config1 = bus_space_read_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG + 2); 559 reset_options = bus_space_read_1(iot, ioh, ELINK_W3_RESET_OPTIONS); 560 GO_WINDOW(0); 561 562 default_media = (config1 & CONFIG_MEDIAMASK) >> CONFIG_MEDIAMASK_SHIFT; 563 564 aprint_normal("%s: ", sc->sc_dev.dv_xname); 565 566 /* Sanity check that there are any media! */ 567 if ((reset_options & ELINK_PCI_MEDIAMASK) == 0) { 568 aprint_error("no media present!\n"); 569 ifmedia_add(ifm, IFM_ETHER|IFM_NONE, 0, NULL); 570 ifmedia_set(ifm, IFM_ETHER|IFM_NONE); 571 return; 572 } 573 574 #define PRINT(str) aprint_normal("%s%s", sep, str); sep = ", " 575 576 for (exm = ex_native_media; exm->exm_name != NULL; exm++) { 577 if (reset_options & exm->exm_mpbit) { 578 /* 579 * Default media is a little complicated. We 580 * support full-duplex which uses the same 581 * reset options bit. 582 * 583 * XXX Check EEPROM for default to FDX? 584 */ 585 if (exm->exm_epmedia == default_media) { 586 if ((exm->exm_ifmedia & IFM_FDX) == 0) { 587 defmedia = exm->exm_ifmedia; 588 defmedianame = exm->exm_name; 589 } 590 } else if (defmedia == 0) { 591 defmedia = exm->exm_ifmedia; 592 defmedianame = exm->exm_name; 593 } 594 ifmedia_add(ifm, exm->exm_ifmedia, exm->exm_epmedia, 595 NULL); 596 PRINT(exm->exm_name); 597 } 598 } 599 600 #undef PRINT 601 602 #ifdef DIAGNOSTIC 603 if (defmedia == 0) 604 panic("ex_probemedia: impossible"); 605 #endif 606 607 aprint_normal(", default %s\n", defmedianame); 608 ifmedia_set(ifm, defmedia); 609 } 610 611 /* 612 * Bring device up. 613 */ 614 int 615 ex_init(ifp) 616 struct ifnet *ifp; 617 { 618 struct ex_softc *sc = ifp->if_softc; 619 bus_space_tag_t iot = sc->sc_iot; 620 bus_space_handle_t ioh = sc->sc_ioh; 621 int i; 622 int error = 0; 623 624 if ((error = ex_enable(sc)) != 0) 625 goto out; 626 627 ex_waitcmd(sc); 628 ex_stop(ifp, 0); 629 630 /* 631 * Set the station address and clear the station mask. The latter 632 * is needed for 90x cards, 0 is the default for 90xB cards. 633 */ 634 GO_WINDOW(2); 635 for (i = 0; i < ETHER_ADDR_LEN; i++) { 636 bus_space_write_1(iot, ioh, ELINK_W2_ADDR_0 + i, 637 LLADDR(ifp->if_sadl)[i]); 638 bus_space_write_1(iot, ioh, ELINK_W2_RECVMASK_0 + i, 0); 639 } 640 641 GO_WINDOW(3); 642 643 bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_RESET); 644 ex_waitcmd(sc); 645 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_RESET); 646 ex_waitcmd(sc); 647 648 /* 649 * Disable reclaim threshold for 90xB, set free threshold to 650 * 6 * 256 = 1536 for 90x. 651 */ 652 if (sc->ex_conf & EX_CONF_90XB) 653 bus_space_write_2(iot, ioh, ELINK_COMMAND, 654 ELINK_TXRECLTHRESH | 255); 655 else 656 bus_space_write_1(iot, ioh, ELINK_TXFREETHRESH, 6); 657 658 bus_space_write_2(iot, ioh, ELINK_COMMAND, 659 SET_RX_EARLY_THRESH | ELINK_THRESH_DISABLE); 660 661 bus_space_write_4(iot, ioh, ELINK_DMACTRL, 662 bus_space_read_4(iot, ioh, ELINK_DMACTRL) | ELINK_DMAC_UPRXEAREN); 663 664 bus_space_write_2(iot, ioh, ELINK_COMMAND, 665 SET_RD_0_MASK | XL_WATCHED_INTERRUPTS); 666 bus_space_write_2(iot, ioh, ELINK_COMMAND, 667 SET_INTR_MASK | XL_WATCHED_INTERRUPTS); 668 669 bus_space_write_2(iot, ioh, ELINK_COMMAND, ACK_INTR | 0xff); 670 if (sc->intr_ack) 671 (* sc->intr_ack)(sc); 672 ex_set_media(sc); 673 ex_set_mc(sc); 674 675 676 bus_space_write_2(iot, ioh, ELINK_COMMAND, STATS_ENABLE); 677 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_ENABLE); 678 bus_space_write_4(iot, ioh, ELINK_UPLISTPTR, sc->sc_upddma); 679 bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_ENABLE); 680 bus_space_write_2(iot, ioh, ELINK_COMMAND, ELINK_UPUNSTALL); 681 682 if (sc->ex_conf & (EX_CONF_PHY_POWER | EX_CONF_INV_LED_POLARITY)) { 683 u_int16_t cbcard_config; 684 685 GO_WINDOW(2); 686 cbcard_config = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 0x0c); 687 if (sc->ex_conf & EX_CONF_PHY_POWER) { 688 cbcard_config |= 0x4000; /* turn on PHY power */ 689 } 690 if (sc->ex_conf & EX_CONF_INV_LED_POLARITY) { 691 cbcard_config |= 0x0010; /* invert LED polarity */ 692 } 693 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 0x0c, cbcard_config); 694 695 GO_WINDOW(3); 696 } 697 698 ifp->if_flags |= IFF_RUNNING; 699 ifp->if_flags &= ~IFF_OACTIVE; 700 ex_start(ifp); 701 sc->sc_if_flags = ifp->if_flags; 702 703 GO_WINDOW(1); 704 705 callout_reset(&sc->ex_mii_callout, hz, ex_tick, sc); 706 707 out: 708 if (error) { 709 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 710 ifp->if_timer = 0; 711 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 712 } 713 return (error); 714 } 715 716 #define MCHASHSIZE 256 717 #define ex_mchash(addr) (ether_crc32_be((addr), ETHER_ADDR_LEN) & \ 718 (MCHASHSIZE - 1)) 719 720 /* 721 * Set multicast receive filter. Also take care of promiscuous mode 722 * here (XXX). 723 */ 724 void 725 ex_set_mc(sc) 726 struct ex_softc *sc; 727 { 728 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 729 struct ethercom *ec = &sc->sc_ethercom; 730 struct ether_multi *enm; 731 struct ether_multistep estep; 732 int i; 733 u_int16_t mask = FIL_INDIVIDUAL | FIL_BRDCST; 734 735 if (ifp->if_flags & IFF_PROMISC) { 736 mask |= FIL_PROMISC; 737 goto allmulti; 738 } 739 740 ETHER_FIRST_MULTI(estep, ec, enm); 741 if (enm == NULL) 742 goto nomulti; 743 744 if ((sc->ex_conf & EX_CONF_90XB) == 0) 745 /* No multicast hash filtering. */ 746 goto allmulti; 747 748 for (i = 0; i < MCHASHSIZE; i++) 749 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 750 ELINK_COMMAND, ELINK_CLEARHASHFILBIT | i); 751 752 do { 753 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 754 ETHER_ADDR_LEN) != 0) 755 goto allmulti; 756 757 i = ex_mchash(enm->enm_addrlo); 758 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 759 ELINK_COMMAND, ELINK_SETHASHFILBIT | i); 760 ETHER_NEXT_MULTI(estep, enm); 761 } while (enm != NULL); 762 mask |= FIL_MULTIHASH; 763 764 nomulti: 765 ifp->if_flags &= ~IFF_ALLMULTI; 766 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_COMMAND, 767 SET_RX_FILTER | mask); 768 return; 769 770 allmulti: 771 ifp->if_flags |= IFF_ALLMULTI; 772 mask |= FIL_MULTICAST; 773 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_COMMAND, 774 SET_RX_FILTER | mask); 775 } 776 777 778 static void 779 ex_txstat(sc) 780 struct ex_softc *sc; 781 { 782 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 783 bus_space_tag_t iot = sc->sc_iot; 784 bus_space_handle_t ioh = sc->sc_ioh; 785 int i; 786 787 /* 788 * We need to read+write TX_STATUS until we get a 0 status 789 * in order to turn off the interrupt flag. 790 */ 791 while ((i = bus_space_read_1(iot, ioh, ELINK_TXSTATUS)) & TXS_COMPLETE) { 792 bus_space_write_1(iot, ioh, ELINK_TXSTATUS, 0x0); 793 794 if (i & TXS_JABBER) { 795 ++sc->sc_ethercom.ec_if.if_oerrors; 796 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 797 printf("%s: jabber (%x)\n", 798 sc->sc_dev.dv_xname, i); 799 ex_init(ifp); 800 /* TODO: be more subtle here */ 801 } else if (i & TXS_UNDERRUN) { 802 ++sc->sc_ethercom.ec_if.if_oerrors; 803 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 804 printf("%s: fifo underrun (%x) @%d\n", 805 sc->sc_dev.dv_xname, i, 806 sc->tx_start_thresh); 807 if (sc->tx_succ_ok < 100) 808 sc->tx_start_thresh = min(ETHER_MAX_LEN, 809 sc->tx_start_thresh + 20); 810 sc->tx_succ_ok = 0; 811 ex_init(ifp); 812 /* TODO: be more subtle here */ 813 } else if (i & TXS_MAX_COLLISION) { 814 ++sc->sc_ethercom.ec_if.if_collisions; 815 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_ENABLE); 816 sc->sc_ethercom.ec_if.if_flags &= ~IFF_OACTIVE; 817 } else 818 sc->tx_succ_ok = (sc->tx_succ_ok+1) & 127; 819 } 820 } 821 822 int 823 ex_media_chg(ifp) 824 struct ifnet *ifp; 825 { 826 827 if (ifp->if_flags & IFF_UP) 828 ex_init(ifp); 829 return 0; 830 } 831 832 void 833 ex_set_xcvr(sc, media) 834 struct ex_softc *sc; 835 const u_int16_t media; 836 { 837 bus_space_tag_t iot = sc->sc_iot; 838 bus_space_handle_t ioh = sc->sc_ioh; 839 u_int32_t icfg; 840 841 /* 842 * We're already in Window 3 843 */ 844 icfg = bus_space_read_4(iot, ioh, ELINK_W3_INTERNAL_CONFIG); 845 icfg &= ~(CONFIG_XCVR_SEL << 16); 846 if (media & (ELINK_MEDIACAP_MII | ELINK_MEDIACAP_100BASET4)) 847 icfg |= ELINKMEDIA_MII << (CONFIG_XCVR_SEL_SHIFT + 16); 848 if (media & ELINK_MEDIACAP_100BASETX) 849 icfg |= ELINKMEDIA_AUTO << (CONFIG_XCVR_SEL_SHIFT + 16); 850 if (media & ELINK_MEDIACAP_100BASEFX) 851 icfg |= ELINKMEDIA_100BASE_FX 852 << (CONFIG_XCVR_SEL_SHIFT + 16); 853 bus_space_write_4(iot, ioh, ELINK_W3_INTERNAL_CONFIG, icfg); 854 } 855 856 void 857 ex_set_media(sc) 858 struct ex_softc *sc; 859 { 860 bus_space_tag_t iot = sc->sc_iot; 861 bus_space_handle_t ioh = sc->sc_ioh; 862 u_int32_t configreg; 863 864 if (((sc->ex_conf & EX_CONF_MII) && 865 (sc->ex_mii.mii_media_active & IFM_FDX)) 866 || (!(sc->ex_conf & EX_CONF_MII) && 867 (sc->ex_mii.mii_media.ifm_media & IFM_FDX))) { 868 bus_space_write_2(iot, ioh, ELINK_W3_MAC_CONTROL, 869 MAC_CONTROL_FDX); 870 } else { 871 bus_space_write_2(iot, ioh, ELINK_W3_MAC_CONTROL, 0); 872 } 873 874 /* 875 * If the device has MII, select it, and then tell the 876 * PHY which media to use. 877 */ 878 if (sc->ex_conf & EX_CONF_MII) { 879 u_int16_t val; 880 881 GO_WINDOW(3); 882 val = bus_space_read_2(iot, ioh, ELINK_W3_RESET_OPTIONS); 883 ex_set_xcvr(sc, val); 884 mii_mediachg(&sc->ex_mii); 885 return; 886 } 887 888 GO_WINDOW(4); 889 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 0); 890 bus_space_write_2(iot, ioh, ELINK_COMMAND, STOP_TRANSCEIVER); 891 delay(800); 892 893 /* 894 * Now turn on the selected media/transceiver. 895 */ 896 switch (IFM_SUBTYPE(sc->ex_mii.mii_media.ifm_cur->ifm_media)) { 897 case IFM_10_T: 898 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 899 JABBER_GUARD_ENABLE|LINKBEAT_ENABLE); 900 break; 901 902 case IFM_10_2: 903 bus_space_write_2(iot, ioh, ELINK_COMMAND, START_TRANSCEIVER); 904 DELAY(800); 905 break; 906 907 case IFM_100_TX: 908 case IFM_100_FX: 909 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 910 LINKBEAT_ENABLE); 911 DELAY(800); 912 break; 913 914 case IFM_10_5: 915 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 916 SQE_ENABLE); 917 DELAY(800); 918 break; 919 920 case IFM_MANUAL: 921 break; 922 923 case IFM_NONE: 924 return; 925 926 default: 927 panic("ex_set_media: impossible"); 928 } 929 930 GO_WINDOW(3); 931 configreg = bus_space_read_4(iot, ioh, ELINK_W3_INTERNAL_CONFIG); 932 933 configreg &= ~(CONFIG_MEDIAMASK << 16); 934 configreg |= (sc->ex_mii.mii_media.ifm_cur->ifm_data << 935 (CONFIG_MEDIAMASK_SHIFT + 16)); 936 937 bus_space_write_4(iot, ioh, ELINK_W3_INTERNAL_CONFIG, configreg); 938 } 939 940 /* 941 * Get currently-selected media from card. 942 * (if_media callback, may be called before interface is brought up). 943 */ 944 void 945 ex_media_stat(ifp, req) 946 struct ifnet *ifp; 947 struct ifmediareq *req; 948 { 949 struct ex_softc *sc = ifp->if_softc; 950 u_int16_t help; 951 952 if ((ifp->if_flags & (IFF_UP|IFF_RUNNING)) == (IFF_UP|IFF_RUNNING)) { 953 if (sc->ex_conf & EX_CONF_MII) { 954 mii_pollstat(&sc->ex_mii); 955 req->ifm_status = sc->ex_mii.mii_media_status; 956 req->ifm_active = sc->ex_mii.mii_media_active; 957 } else { 958 GO_WINDOW(4); 959 req->ifm_status = IFM_AVALID; 960 req->ifm_active = 961 sc->ex_mii.mii_media.ifm_cur->ifm_media; 962 help = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 963 ELINK_W4_MEDIA_TYPE); 964 if (help & LINKBEAT_DETECT) 965 req->ifm_status |= IFM_ACTIVE; 966 GO_WINDOW(1); 967 } 968 } 969 } 970 971 972 973 /* 974 * Start outputting on the interface. 975 */ 976 static void 977 ex_start(ifp) 978 struct ifnet *ifp; 979 { 980 struct ex_softc *sc = ifp->if_softc; 981 bus_space_tag_t iot = sc->sc_iot; 982 bus_space_handle_t ioh = sc->sc_ioh; 983 volatile struct ex_fraghdr *fr = NULL; 984 volatile struct ex_dpd *dpd = NULL, *prevdpd = NULL; 985 struct ex_txdesc *txp; 986 struct mbuf *mb_head; 987 bus_dmamap_t dmamap; 988 int offset, totlen, segment, error; 989 u_int32_t csum_flags; 990 991 if (sc->tx_head || sc->tx_free == NULL) 992 return; 993 994 txp = NULL; 995 996 /* 997 * We're finished if there is nothing more to add to the list or if 998 * we're all filled up with buffers to transmit. 999 */ 1000 while (sc->tx_free != NULL) { 1001 /* 1002 * Grab a packet to transmit. 1003 */ 1004 IFQ_DEQUEUE(&ifp->if_snd, mb_head); 1005 if (mb_head == NULL) 1006 break; 1007 1008 /* 1009 * Get pointer to next available tx desc. 1010 */ 1011 txp = sc->tx_free; 1012 dmamap = txp->tx_dmamap; 1013 1014 /* 1015 * Go through each of the mbufs in the chain and initialize 1016 * the transmit buffer descriptors with the physical address 1017 * and size of the mbuf. 1018 */ 1019 reload: 1020 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1021 mb_head, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1022 switch (error) { 1023 case 0: 1024 /* Success. */ 1025 break; 1026 1027 case EFBIG: 1028 { 1029 struct mbuf *mn; 1030 1031 /* 1032 * We ran out of segments. We have to recopy this 1033 * mbuf chain first. Bail out if we can't get the 1034 * new buffers. 1035 */ 1036 printf("%s: too many segments, ", sc->sc_dev.dv_xname); 1037 1038 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1039 if (mn == NULL) { 1040 m_freem(mb_head); 1041 printf("aborting\n"); 1042 goto out; 1043 } 1044 if (mb_head->m_pkthdr.len > MHLEN) { 1045 MCLGET(mn, M_DONTWAIT); 1046 if ((mn->m_flags & M_EXT) == 0) { 1047 m_freem(mn); 1048 m_freem(mb_head); 1049 printf("aborting\n"); 1050 goto out; 1051 } 1052 } 1053 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1054 mtod(mn, caddr_t)); 1055 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1056 m_freem(mb_head); 1057 mb_head = mn; 1058 printf("retrying\n"); 1059 goto reload; 1060 } 1061 1062 default: 1063 /* 1064 * Some other problem; report it. 1065 */ 1066 printf("%s: can't load mbuf chain, error = %d\n", 1067 sc->sc_dev.dv_xname, error); 1068 m_freem(mb_head); 1069 goto out; 1070 } 1071 1072 /* 1073 * remove our tx desc from freelist. 1074 */ 1075 sc->tx_free = txp->tx_next; 1076 txp->tx_next = NULL; 1077 1078 fr = &txp->tx_dpd->dpd_frags[0]; 1079 totlen = 0; 1080 for (segment = 0; segment < dmamap->dm_nsegs; segment++, fr++) { 1081 fr->fr_addr = htole32(dmamap->dm_segs[segment].ds_addr); 1082 fr->fr_len = htole32(dmamap->dm_segs[segment].ds_len); 1083 totlen += dmamap->dm_segs[segment].ds_len; 1084 } 1085 fr--; 1086 fr->fr_len |= htole32(EX_FR_LAST); 1087 txp->tx_mbhead = mb_head; 1088 1089 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1090 BUS_DMASYNC_PREWRITE); 1091 1092 dpd = txp->tx_dpd; 1093 dpd->dpd_nextptr = 0; 1094 dpd->dpd_fsh = htole32(totlen); 1095 1096 /* Byte-swap constants so compiler can optimize. */ 1097 1098 if (sc->ex_conf & EX_CONF_90XB) { 1099 csum_flags = 0; 1100 1101 if (mb_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 1102 csum_flags |= htole32(EX_DPD_IPCKSUM); 1103 1104 if (mb_head->m_pkthdr.csum_flags & M_CSUM_TCPv4) 1105 csum_flags |= htole32(EX_DPD_TCPCKSUM); 1106 else if (mb_head->m_pkthdr.csum_flags & M_CSUM_UDPv4) 1107 csum_flags |= htole32(EX_DPD_UDPCKSUM); 1108 1109 dpd->dpd_fsh |= csum_flags; 1110 } else { 1111 KDASSERT((mb_head->m_pkthdr.csum_flags & 1112 (M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4)) == 0); 1113 } 1114 1115 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap, 1116 ((caddr_t)dpd - (caddr_t)sc->sc_dpd), 1117 sizeof (struct ex_dpd), 1118 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1119 1120 /* 1121 * No need to stall the download engine, we know it's 1122 * not busy right now. 1123 * 1124 * Fix up pointers in both the "soft" tx and the physical 1125 * tx list. 1126 */ 1127 if (sc->tx_head != NULL) { 1128 prevdpd = sc->tx_tail->tx_dpd; 1129 offset = ((caddr_t)prevdpd - (caddr_t)sc->sc_dpd); 1130 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap, 1131 offset, sizeof (struct ex_dpd), 1132 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1133 prevdpd->dpd_nextptr = htole32(DPD_DMADDR(sc, txp)); 1134 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap, 1135 offset, sizeof (struct ex_dpd), 1136 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1137 sc->tx_tail->tx_next = txp; 1138 sc->tx_tail = txp; 1139 } else { 1140 sc->tx_tail = sc->tx_head = txp; 1141 } 1142 1143 #if NBPFILTER > 0 1144 /* 1145 * Pass packet to bpf if there is a listener. 1146 */ 1147 if (ifp->if_bpf) 1148 bpf_mtap(ifp->if_bpf, mb_head); 1149 #endif 1150 } 1151 out: 1152 if (sc->tx_head) { 1153 sc->tx_tail->tx_dpd->dpd_fsh |= htole32(EX_DPD_DNIND); 1154 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap, 1155 ((caddr_t)sc->tx_tail->tx_dpd - (caddr_t)sc->sc_dpd), 1156 sizeof (struct ex_dpd), 1157 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1158 ifp->if_flags |= IFF_OACTIVE; 1159 bus_space_write_2(iot, ioh, ELINK_COMMAND, ELINK_DNUNSTALL); 1160 bus_space_write_4(iot, ioh, ELINK_DNLISTPTR, 1161 DPD_DMADDR(sc, sc->tx_head)); 1162 1163 /* trigger watchdog */ 1164 ifp->if_timer = 5; 1165 } 1166 } 1167 1168 1169 int 1170 ex_intr(arg) 1171 void *arg; 1172 { 1173 struct ex_softc *sc = arg; 1174 bus_space_tag_t iot = sc->sc_iot; 1175 bus_space_handle_t ioh = sc->sc_ioh; 1176 u_int16_t stat; 1177 int ret = 0; 1178 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1179 1180 if ((ifp->if_flags & IFF_RUNNING) == 0 || 1181 (sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1182 return (0); 1183 1184 for (;;) { 1185 stat = bus_space_read_2(iot, ioh, ELINK_STATUS); 1186 1187 if ((stat & XL_WATCHED_INTERRUPTS) == 0) { 1188 if ((stat & INTR_LATCH) == 0) { 1189 #if 0 1190 printf("%s: intr latch cleared\n", 1191 sc->sc_dev.dv_xname); 1192 #endif 1193 break; 1194 } 1195 } 1196 1197 ret = 1; 1198 1199 /* 1200 * Acknowledge interrupts. 1201 */ 1202 bus_space_write_2(iot, ioh, ELINK_COMMAND, ACK_INTR | 1203 (stat & (XL_WATCHED_INTERRUPTS | INTR_LATCH))); 1204 if (sc->intr_ack) 1205 (*sc->intr_ack)(sc); 1206 1207 if (stat & HOST_ERROR) { 1208 printf("%s: adapter failure (%x)\n", 1209 sc->sc_dev.dv_xname, stat); 1210 ex_reset(sc); 1211 ex_init(ifp); 1212 return 1; 1213 } 1214 if (stat & TX_COMPLETE) { 1215 ex_txstat(sc); 1216 } 1217 if (stat & UPD_STATS) { 1218 ex_getstats(sc); 1219 } 1220 if (stat & DN_COMPLETE) { 1221 struct ex_txdesc *txp, *ptxp = NULL; 1222 bus_dmamap_t txmap; 1223 1224 /* reset watchdog timer, was set in ex_start() */ 1225 ifp->if_timer = 0; 1226 1227 for (txp = sc->tx_head; txp != NULL; 1228 txp = txp->tx_next) { 1229 bus_dmamap_sync(sc->sc_dmat, 1230 sc->sc_dpd_dmamap, 1231 (caddr_t)txp->tx_dpd - (caddr_t)sc->sc_dpd, 1232 sizeof (struct ex_dpd), 1233 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1234 if (txp->tx_mbhead != NULL) { 1235 txmap = txp->tx_dmamap; 1236 bus_dmamap_sync(sc->sc_dmat, txmap, 1237 0, txmap->dm_mapsize, 1238 BUS_DMASYNC_POSTWRITE); 1239 bus_dmamap_unload(sc->sc_dmat, txmap); 1240 m_freem(txp->tx_mbhead); 1241 txp->tx_mbhead = NULL; 1242 } 1243 ptxp = txp; 1244 } 1245 1246 /* 1247 * Move finished tx buffers back to the tx free list. 1248 */ 1249 if (sc->tx_free) { 1250 sc->tx_ftail->tx_next = sc->tx_head; 1251 sc->tx_ftail = ptxp; 1252 } else 1253 sc->tx_ftail = sc->tx_free = sc->tx_head; 1254 1255 sc->tx_head = sc->tx_tail = NULL; 1256 ifp->if_flags &= ~IFF_OACTIVE; 1257 } 1258 1259 if (stat & UP_COMPLETE) { 1260 struct ex_rxdesc *rxd; 1261 struct mbuf *m; 1262 struct ex_upd *upd; 1263 bus_dmamap_t rxmap; 1264 u_int32_t pktstat; 1265 1266 rcvloop: 1267 rxd = sc->rx_head; 1268 rxmap = rxd->rx_dmamap; 1269 m = rxd->rx_mbhead; 1270 upd = rxd->rx_upd; 1271 1272 bus_dmamap_sync(sc->sc_dmat, rxmap, 0, 1273 rxmap->dm_mapsize, 1274 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1275 bus_dmamap_sync(sc->sc_dmat, sc->sc_upd_dmamap, 1276 ((caddr_t)upd - (caddr_t)sc->sc_upd), 1277 sizeof (struct ex_upd), 1278 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1279 pktstat = le32toh(upd->upd_pktstatus); 1280 1281 if (pktstat & EX_UPD_COMPLETE) { 1282 /* 1283 * Remove first packet from the chain. 1284 */ 1285 sc->rx_head = rxd->rx_next; 1286 rxd->rx_next = NULL; 1287 1288 /* 1289 * Add a new buffer to the receive chain. 1290 * If this fails, the old buffer is recycled 1291 * instead. 1292 */ 1293 if (ex_add_rxbuf(sc, rxd) == 0) { 1294 u_int16_t total_len; 1295 1296 if (pktstat & 1297 ((sc->sc_ethercom.ec_capenable & 1298 ETHERCAP_VLAN_MTU) ? 1299 EX_UPD_ERR_VLAN : EX_UPD_ERR)) { 1300 ifp->if_ierrors++; 1301 m_freem(m); 1302 goto rcvloop; 1303 } 1304 1305 total_len = pktstat & EX_UPD_PKTLENMASK; 1306 if (total_len < 1307 sizeof(struct ether_header)) { 1308 m_freem(m); 1309 goto rcvloop; 1310 } 1311 m->m_pkthdr.rcvif = ifp; 1312 m->m_pkthdr.len = m->m_len = total_len; 1313 #if NBPFILTER > 0 1314 if (ifp->if_bpf) 1315 bpf_mtap(ifp->if_bpf, m); 1316 #endif 1317 /* 1318 * Set the incoming checksum information for the packet. 1319 */ 1320 if ((sc->ex_conf & EX_CONF_90XB) != 0 && 1321 (pktstat & EX_UPD_IPCHECKED) != 0) { 1322 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1323 if (pktstat & EX_UPD_IPCKSUMERR) 1324 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1325 if (pktstat & EX_UPD_TCPCHECKED) { 1326 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1327 if (pktstat & EX_UPD_TCPCKSUMERR) 1328 m->m_pkthdr.csum_flags |= 1329 M_CSUM_TCP_UDP_BAD; 1330 } else if (pktstat & EX_UPD_UDPCHECKED) { 1331 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1332 if (pktstat & EX_UPD_UDPCKSUMERR) 1333 m->m_pkthdr.csum_flags |= 1334 M_CSUM_TCP_UDP_BAD; 1335 } 1336 } 1337 (*ifp->if_input)(ifp, m); 1338 } 1339 goto rcvloop; 1340 } 1341 /* 1342 * Just in case we filled up all UPDs and the DMA engine 1343 * stalled. We could be more subtle about this. 1344 */ 1345 if (bus_space_read_4(iot, ioh, ELINK_UPLISTPTR) == 0) { 1346 printf("%s: uplistptr was 0\n", 1347 sc->sc_dev.dv_xname); 1348 ex_init(ifp); 1349 } else if (bus_space_read_4(iot, ioh, ELINK_UPPKTSTATUS) 1350 & 0x2000) { 1351 printf("%s: receive stalled\n", 1352 sc->sc_dev.dv_xname); 1353 bus_space_write_2(iot, ioh, ELINK_COMMAND, 1354 ELINK_UPUNSTALL); 1355 } 1356 } 1357 1358 #if NRND > 0 1359 if (stat) 1360 rnd_add_uint32(&sc->rnd_source, stat); 1361 #endif 1362 } 1363 1364 /* no more interrupts */ 1365 if (ret && IFQ_IS_EMPTY(&ifp->if_snd) == 0) 1366 ex_start(ifp); 1367 return ret; 1368 } 1369 1370 int 1371 ex_ioctl(ifp, cmd, data) 1372 struct ifnet *ifp; 1373 u_long cmd; 1374 caddr_t data; 1375 { 1376 struct ex_softc *sc = ifp->if_softc; 1377 struct ifreq *ifr = (struct ifreq *)data; 1378 int s, error; 1379 1380 s = splnet(); 1381 1382 switch (cmd) { 1383 case SIOCSIFMEDIA: 1384 case SIOCGIFMEDIA: 1385 error = ifmedia_ioctl(ifp, ifr, &sc->ex_mii.mii_media, cmd); 1386 break; 1387 case SIOCSIFFLAGS: 1388 /* If the interface is up and running, only modify the receive 1389 * filter when setting promiscuous or debug mode. Otherwise 1390 * fall through to ether_ioctl, which will reset the chip. 1391 */ 1392 #define RESETIGN (IFF_CANTCHANGE|IFF_DEBUG) 1393 if (((ifp->if_flags & (IFF_UP|IFF_RUNNING)) 1394 == (IFF_UP|IFF_RUNNING)) 1395 && ((ifp->if_flags & (~RESETIGN)) 1396 == (sc->sc_if_flags & (~RESETIGN)))) { 1397 ex_set_mc(sc); 1398 error = 0; 1399 break; 1400 #undef RESETIGN 1401 } 1402 /* FALLTHROUGH */ 1403 default: 1404 error = ether_ioctl(ifp, cmd, data); 1405 if (error == ENETRESET) { 1406 /* 1407 * Multicast list has changed; set the hardware filter 1408 * accordingly. 1409 */ 1410 if (ifp->if_flags & IFF_RUNNING) 1411 ex_set_mc(sc); 1412 error = 0; 1413 } 1414 break; 1415 } 1416 1417 sc->sc_if_flags = ifp->if_flags; 1418 splx(s); 1419 return (error); 1420 } 1421 1422 void 1423 ex_getstats(sc) 1424 struct ex_softc *sc; 1425 { 1426 bus_space_handle_t ioh = sc->sc_ioh; 1427 bus_space_tag_t iot = sc->sc_iot; 1428 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1429 u_int8_t upperok; 1430 1431 GO_WINDOW(6); 1432 upperok = bus_space_read_1(iot, ioh, UPPER_FRAMES_OK); 1433 ifp->if_ipackets += bus_space_read_1(iot, ioh, RX_FRAMES_OK); 1434 ifp->if_ipackets += (upperok & 0x03) << 8; 1435 ifp->if_opackets += bus_space_read_1(iot, ioh, TX_FRAMES_OK); 1436 ifp->if_opackets += (upperok & 0x30) << 4; 1437 ifp->if_ierrors += bus_space_read_1(iot, ioh, RX_OVERRUNS); 1438 ifp->if_collisions += bus_space_read_1(iot, ioh, TX_COLLISIONS); 1439 /* 1440 * There seems to be no way to get the exact number of collisions, 1441 * this is the number that occurred at the very least. 1442 */ 1443 ifp->if_collisions += 2 * bus_space_read_1(iot, ioh, 1444 TX_AFTER_X_COLLISIONS); 1445 /* 1446 * Interface byte counts are counted by ether_input() and 1447 * ether_output(), so don't accumulate them here. Just 1448 * read the NIC counters so they don't generate overflow interrupts. 1449 * Upper byte counters are latched from reading the totals, so 1450 * they don't need to be read if we don't need their values. 1451 */ 1452 bus_space_read_2(iot, ioh, RX_TOTAL_OK); 1453 bus_space_read_2(iot, ioh, TX_TOTAL_OK); 1454 1455 /* 1456 * Clear the following to avoid stats overflow interrupts 1457 */ 1458 bus_space_read_1(iot, ioh, TX_DEFERRALS); 1459 bus_space_read_1(iot, ioh, TX_AFTER_1_COLLISION); 1460 bus_space_read_1(iot, ioh, TX_NO_SQE); 1461 bus_space_read_1(iot, ioh, TX_CD_LOST); 1462 GO_WINDOW(4); 1463 bus_space_read_1(iot, ioh, ELINK_W4_BADSSD); 1464 GO_WINDOW(1); 1465 } 1466 1467 void 1468 ex_printstats(sc) 1469 struct ex_softc *sc; 1470 { 1471 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1472 1473 ex_getstats(sc); 1474 printf("in %llu out %llu ierror %llu oerror %llu ibytes %llu obytes " 1475 "%llu\n", (unsigned long long)ifp->if_ipackets, 1476 (unsigned long long)ifp->if_opackets, 1477 (unsigned long long)ifp->if_ierrors, 1478 (unsigned long long)ifp->if_oerrors, 1479 (unsigned long long)ifp->if_ibytes, 1480 (unsigned long long)ifp->if_obytes); 1481 } 1482 1483 void 1484 ex_tick(arg) 1485 void *arg; 1486 { 1487 struct ex_softc *sc = arg; 1488 int s; 1489 1490 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1491 return; 1492 1493 s = splnet(); 1494 1495 if (sc->ex_conf & EX_CONF_MII) 1496 mii_tick(&sc->ex_mii); 1497 1498 if (!(bus_space_read_2((sc)->sc_iot, (sc)->sc_ioh, ELINK_STATUS) 1499 & COMMAND_IN_PROGRESS)) 1500 ex_getstats(sc); 1501 1502 splx(s); 1503 1504 callout_reset(&sc->ex_mii_callout, hz, ex_tick, sc); 1505 } 1506 1507 void 1508 ex_reset(sc) 1509 struct ex_softc *sc; 1510 { 1511 u_int16_t val = GLOBAL_RESET; 1512 1513 if (sc->ex_conf & EX_CONF_RESETHACK) 1514 val |= 0x10; 1515 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_COMMAND, val); 1516 /* 1517 * XXX apparently the command in progress bit can't be trusted 1518 * during a reset, so we just always wait this long. Fortunately 1519 * we normally only reset the chip during autoconfig. 1520 */ 1521 delay(100000); 1522 ex_waitcmd(sc); 1523 } 1524 1525 void 1526 ex_watchdog(ifp) 1527 struct ifnet *ifp; 1528 { 1529 struct ex_softc *sc = ifp->if_softc; 1530 1531 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1532 ++sc->sc_ethercom.ec_if.if_oerrors; 1533 1534 ex_reset(sc); 1535 ex_init(ifp); 1536 } 1537 1538 void 1539 ex_stop(ifp, disable) 1540 struct ifnet *ifp; 1541 int disable; 1542 { 1543 struct ex_softc *sc = ifp->if_softc; 1544 bus_space_tag_t iot = sc->sc_iot; 1545 bus_space_handle_t ioh = sc->sc_ioh; 1546 struct ex_txdesc *tx; 1547 struct ex_rxdesc *rx; 1548 int i; 1549 1550 bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_DISABLE); 1551 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_DISABLE); 1552 bus_space_write_2(iot, ioh, ELINK_COMMAND, STOP_TRANSCEIVER); 1553 1554 for (tx = sc->tx_head ; tx != NULL; tx = tx->tx_next) { 1555 if (tx->tx_mbhead == NULL) 1556 continue; 1557 m_freem(tx->tx_mbhead); 1558 tx->tx_mbhead = NULL; 1559 bus_dmamap_unload(sc->sc_dmat, tx->tx_dmamap); 1560 tx->tx_dpd->dpd_fsh = tx->tx_dpd->dpd_nextptr = 0; 1561 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap, 1562 ((caddr_t)tx->tx_dpd - (caddr_t)sc->sc_dpd), 1563 sizeof (struct ex_dpd), 1564 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1565 } 1566 sc->tx_tail = sc->tx_head = NULL; 1567 ex_init_txdescs(sc); 1568 1569 sc->rx_tail = sc->rx_head = 0; 1570 for (i = 0; i < EX_NUPD; i++) { 1571 rx = &sc->sc_rxdescs[i]; 1572 if (rx->rx_mbhead != NULL) { 1573 bus_dmamap_unload(sc->sc_dmat, rx->rx_dmamap); 1574 m_freem(rx->rx_mbhead); 1575 rx->rx_mbhead = NULL; 1576 } 1577 ex_add_rxbuf(sc, rx); 1578 } 1579 1580 bus_space_write_2(iot, ioh, ELINK_COMMAND, ACK_INTR | INTR_LATCH); 1581 1582 callout_stop(&sc->ex_mii_callout); 1583 if (sc->ex_conf & EX_CONF_MII) 1584 mii_down(&sc->ex_mii); 1585 1586 if (disable) 1587 ex_disable(sc); 1588 1589 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1590 sc->sc_if_flags = ifp->if_flags; 1591 ifp->if_timer = 0; 1592 } 1593 1594 static void 1595 ex_init_txdescs(sc) 1596 struct ex_softc *sc; 1597 { 1598 int i; 1599 1600 for (i = 0; i < EX_NDPD; i++) { 1601 sc->sc_txdescs[i].tx_dmamap = sc->sc_tx_dmamaps[i]; 1602 sc->sc_txdescs[i].tx_dpd = &sc->sc_dpd[i]; 1603 if (i < EX_NDPD - 1) 1604 sc->sc_txdescs[i].tx_next = &sc->sc_txdescs[i + 1]; 1605 else 1606 sc->sc_txdescs[i].tx_next = NULL; 1607 } 1608 sc->tx_free = &sc->sc_txdescs[0]; 1609 sc->tx_ftail = &sc->sc_txdescs[EX_NDPD-1]; 1610 } 1611 1612 1613 int 1614 ex_activate(self, act) 1615 struct device *self; 1616 enum devact act; 1617 { 1618 struct ex_softc *sc = (void *) self; 1619 int s, error = 0; 1620 1621 s = splnet(); 1622 switch (act) { 1623 case DVACT_ACTIVATE: 1624 error = EOPNOTSUPP; 1625 break; 1626 1627 case DVACT_DEACTIVATE: 1628 if (sc->ex_conf & EX_CONF_MII) 1629 mii_activate(&sc->ex_mii, act, MII_PHY_ANY, 1630 MII_OFFSET_ANY); 1631 if_deactivate(&sc->sc_ethercom.ec_if); 1632 break; 1633 } 1634 splx(s); 1635 1636 return (error); 1637 } 1638 1639 int 1640 ex_detach(sc) 1641 struct ex_softc *sc; 1642 { 1643 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1644 struct ex_rxdesc *rxd; 1645 int i; 1646 1647 /* Succeed now if there's no work to do. */ 1648 if ((sc->ex_flags & EX_FLAGS_ATTACHED) == 0) 1649 return (0); 1650 1651 /* Unhook our tick handler. */ 1652 callout_stop(&sc->ex_mii_callout); 1653 1654 if (sc->ex_conf & EX_CONF_MII) { 1655 /* Detach all PHYs */ 1656 mii_detach(&sc->ex_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1657 } 1658 1659 /* Delete all remaining media. */ 1660 ifmedia_delete_instance(&sc->ex_mii.mii_media, IFM_INST_ANY); 1661 1662 #if NRND > 0 1663 rnd_detach_source(&sc->rnd_source); 1664 #endif 1665 ether_ifdetach(ifp); 1666 if_detach(ifp); 1667 1668 for (i = 0; i < EX_NUPD; i++) { 1669 rxd = &sc->sc_rxdescs[i]; 1670 if (rxd->rx_mbhead != NULL) { 1671 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 1672 m_freem(rxd->rx_mbhead); 1673 rxd->rx_mbhead = NULL; 1674 } 1675 } 1676 for (i = 0; i < EX_NUPD; i++) 1677 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rx_dmamaps[i]); 1678 for (i = 0; i < EX_NDPD; i++) 1679 bus_dmamap_destroy(sc->sc_dmat, sc->sc_tx_dmamaps[i]); 1680 bus_dmamap_unload(sc->sc_dmat, sc->sc_dpd_dmamap); 1681 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dpd_dmamap); 1682 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_dpd, 1683 EX_NDPD * sizeof (struct ex_dpd)); 1684 bus_dmamem_free(sc->sc_dmat, &sc->sc_dseg, sc->sc_drseg); 1685 bus_dmamap_unload(sc->sc_dmat, sc->sc_upd_dmamap); 1686 bus_dmamap_destroy(sc->sc_dmat, sc->sc_upd_dmamap); 1687 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_upd, 1688 EX_NUPD * sizeof (struct ex_upd)); 1689 bus_dmamem_free(sc->sc_dmat, &sc->sc_useg, sc->sc_urseg); 1690 1691 shutdownhook_disestablish(sc->sc_sdhook); 1692 powerhook_disestablish(sc->sc_powerhook); 1693 1694 return (0); 1695 } 1696 1697 /* 1698 * Before reboots, reset card completely. 1699 */ 1700 static void 1701 ex_shutdown(arg) 1702 void *arg; 1703 { 1704 struct ex_softc *sc = arg; 1705 1706 ex_stop(&sc->sc_ethercom.ec_if, 1); 1707 /* 1708 * Make sure the interface is powered up when we reboot, 1709 * otherwise firmware on some systems gets really confused. 1710 */ 1711 (void) ex_enable(sc); 1712 } 1713 1714 /* 1715 * Read EEPROM data. 1716 * XXX what to do if EEPROM doesn't unbusy? 1717 */ 1718 u_int16_t 1719 ex_read_eeprom(sc, offset) 1720 struct ex_softc *sc; 1721 int offset; 1722 { 1723 bus_space_tag_t iot = sc->sc_iot; 1724 bus_space_handle_t ioh = sc->sc_ioh; 1725 u_int16_t data = 0, cmd = READ_EEPROM; 1726 int off; 1727 1728 off = sc->ex_conf & EX_CONF_EEPROM_OFF ? 0x30 : 0; 1729 cmd = sc->ex_conf & EX_CONF_EEPROM_8BIT ? READ_EEPROM8 : READ_EEPROM; 1730 1731 GO_WINDOW(0); 1732 if (ex_eeprom_busy(sc)) 1733 goto out; 1734 bus_space_write_2(iot, ioh, ELINK_W0_EEPROM_COMMAND, 1735 cmd | (off + (offset & 0x3f))); 1736 if (ex_eeprom_busy(sc)) 1737 goto out; 1738 data = bus_space_read_2(iot, ioh, ELINK_W0_EEPROM_DATA); 1739 out: 1740 return data; 1741 } 1742 1743 static int 1744 ex_eeprom_busy(sc) 1745 struct ex_softc *sc; 1746 { 1747 bus_space_tag_t iot = sc->sc_iot; 1748 bus_space_handle_t ioh = sc->sc_ioh; 1749 int i = 100; 1750 1751 while (i--) { 1752 if (!(bus_space_read_2(iot, ioh, ELINK_W0_EEPROM_COMMAND) & 1753 EEPROM_BUSY)) 1754 return 0; 1755 delay(100); 1756 } 1757 printf("\n%s: eeprom stays busy.\n", sc->sc_dev.dv_xname); 1758 return (1); 1759 } 1760 1761 /* 1762 * Create a new rx buffer and add it to the 'soft' rx list. 1763 */ 1764 static int 1765 ex_add_rxbuf(sc, rxd) 1766 struct ex_softc *sc; 1767 struct ex_rxdesc *rxd; 1768 { 1769 struct mbuf *m, *oldm; 1770 bus_dmamap_t rxmap; 1771 int error, rval = 0; 1772 1773 oldm = rxd->rx_mbhead; 1774 rxmap = rxd->rx_dmamap; 1775 1776 MGETHDR(m, M_DONTWAIT, MT_DATA); 1777 if (m != NULL) { 1778 MCLGET(m, M_DONTWAIT); 1779 if ((m->m_flags & M_EXT) == 0) { 1780 m_freem(m); 1781 if (oldm == NULL) 1782 return 1; 1783 m = oldm; 1784 MRESETDATA(m); 1785 rval = 1; 1786 } 1787 } else { 1788 if (oldm == NULL) 1789 return 1; 1790 m = oldm; 1791 MRESETDATA(m); 1792 rval = 1; 1793 } 1794 1795 /* 1796 * Setup the DMA map for this receive buffer. 1797 */ 1798 if (m != oldm) { 1799 if (oldm != NULL) 1800 bus_dmamap_unload(sc->sc_dmat, rxmap); 1801 error = bus_dmamap_load(sc->sc_dmat, rxmap, 1802 m->m_ext.ext_buf, MCLBYTES, NULL, 1803 BUS_DMA_READ|BUS_DMA_NOWAIT); 1804 if (error) { 1805 printf("%s: can't load rx buffer, error = %d\n", 1806 sc->sc_dev.dv_xname, error); 1807 panic("ex_add_rxbuf"); /* XXX */ 1808 } 1809 } 1810 1811 /* 1812 * Align for data after 14 byte header. 1813 */ 1814 m->m_data += 2; 1815 1816 rxd->rx_mbhead = m; 1817 rxd->rx_upd->upd_pktstatus = htole32(MCLBYTES - 2); 1818 rxd->rx_upd->upd_frags[0].fr_addr = 1819 htole32(rxmap->dm_segs[0].ds_addr + 2); 1820 rxd->rx_upd->upd_nextptr = 0; 1821 1822 /* 1823 * Attach it to the end of the list. 1824 */ 1825 if (sc->rx_head != NULL) { 1826 sc->rx_tail->rx_next = rxd; 1827 sc->rx_tail->rx_upd->upd_nextptr = htole32(sc->sc_upddma + 1828 ((caddr_t)rxd->rx_upd - (caddr_t)sc->sc_upd)); 1829 bus_dmamap_sync(sc->sc_dmat, sc->sc_upd_dmamap, 1830 (caddr_t)sc->rx_tail->rx_upd - (caddr_t)sc->sc_upd, 1831 sizeof (struct ex_upd), 1832 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1833 } else { 1834 sc->rx_head = rxd; 1835 } 1836 sc->rx_tail = rxd; 1837 1838 bus_dmamap_sync(sc->sc_dmat, rxmap, 0, rxmap->dm_mapsize, 1839 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1840 bus_dmamap_sync(sc->sc_dmat, sc->sc_upd_dmamap, 1841 ((caddr_t)rxd->rx_upd - (caddr_t)sc->sc_upd), 1842 sizeof (struct ex_upd), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1843 return (rval); 1844 } 1845 1846 u_int32_t 1847 ex_mii_bitbang_read(self) 1848 struct device *self; 1849 { 1850 struct ex_softc *sc = (void *) self; 1851 1852 /* We're already in Window 4. */ 1853 return (bus_space_read_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_PHYSMGMT)); 1854 } 1855 1856 void 1857 ex_mii_bitbang_write(self, val) 1858 struct device *self; 1859 u_int32_t val; 1860 { 1861 struct ex_softc *sc = (void *) self; 1862 1863 /* We're already in Window 4. */ 1864 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_PHYSMGMT, val); 1865 } 1866 1867 int 1868 ex_mii_readreg(v, phy, reg) 1869 struct device *v; 1870 int phy, reg; 1871 { 1872 struct ex_softc *sc = (struct ex_softc *)v; 1873 int val; 1874 1875 if ((sc->ex_conf & EX_CONF_INTPHY) && phy != ELINK_INTPHY_ID) 1876 return 0; 1877 1878 GO_WINDOW(4); 1879 1880 val = mii_bitbang_readreg(v, &ex_mii_bitbang_ops, phy, reg); 1881 1882 GO_WINDOW(1); 1883 1884 return (val); 1885 } 1886 1887 void 1888 ex_mii_writereg(v, phy, reg, data) 1889 struct device *v; 1890 int phy; 1891 int reg; 1892 int data; 1893 { 1894 struct ex_softc *sc = (struct ex_softc *)v; 1895 1896 GO_WINDOW(4); 1897 1898 mii_bitbang_writereg(v, &ex_mii_bitbang_ops, phy, reg, data); 1899 1900 GO_WINDOW(1); 1901 } 1902 1903 void 1904 ex_mii_statchg(v) 1905 struct device *v; 1906 { 1907 struct ex_softc *sc = (struct ex_softc *)v; 1908 bus_space_tag_t iot = sc->sc_iot; 1909 bus_space_handle_t ioh = sc->sc_ioh; 1910 int mctl; 1911 1912 GO_WINDOW(3); 1913 mctl = bus_space_read_2(iot, ioh, ELINK_W3_MAC_CONTROL); 1914 if (sc->ex_mii.mii_media_active & IFM_FDX) 1915 mctl |= MAC_CONTROL_FDX; 1916 else 1917 mctl &= ~MAC_CONTROL_FDX; 1918 bus_space_write_2(iot, ioh, ELINK_W3_MAC_CONTROL, mctl); 1919 GO_WINDOW(1); /* back to operating window */ 1920 } 1921 1922 int 1923 ex_enable(sc) 1924 struct ex_softc *sc; 1925 { 1926 if (sc->enabled == 0 && sc->enable != NULL) { 1927 if ((*sc->enable)(sc) != 0) { 1928 printf("%s: de/vice enable failed\n", 1929 sc->sc_dev.dv_xname); 1930 return (EIO); 1931 } 1932 sc->enabled = 1; 1933 } 1934 return (0); 1935 } 1936 1937 void 1938 ex_disable(sc) 1939 struct ex_softc *sc; 1940 { 1941 if (sc->enabled == 1 && sc->disable != NULL) { 1942 (*sc->disable)(sc); 1943 sc->enabled = 0; 1944 } 1945 } 1946 1947 void 1948 ex_power(why, arg) 1949 int why; 1950 void *arg; 1951 { 1952 struct ex_softc *sc = (void *)arg; 1953 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1954 int s; 1955 1956 s = splnet(); 1957 switch (why) { 1958 case PWR_SUSPEND: 1959 case PWR_STANDBY: 1960 ex_stop(ifp, 0); 1961 if (sc->power != NULL) 1962 (*sc->power)(sc, why); 1963 break; 1964 case PWR_RESUME: 1965 if (ifp->if_flags & IFF_UP) { 1966 if (sc->power != NULL) 1967 (*sc->power)(sc, why); 1968 ex_init(ifp); 1969 } 1970 break; 1971 case PWR_SOFTSUSPEND: 1972 case PWR_SOFTSTANDBY: 1973 case PWR_SOFTRESUME: 1974 break; 1975 } 1976 splx(s); 1977 } 1978
Indexes created Wed Oct 22 13:09:56 GMT 2025