elinkxl.c revision 1.8
1 /* $NetBSD: elinkxl.c,v 1.8 1999/04/13 23:07:25 jonathan Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include "opt_inet.h" 40 #include "opt_ns.h" 41 #include "bpfilter.h" 42 #include "rnd.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/kernel.h> 47 #include <sys/mbuf.h> 48 #include <sys/socket.h> 49 #include <sys/ioctl.h> 50 #include <sys/errno.h> 51 #include <sys/syslog.h> 52 #include <sys/select.h> 53 #include <sys/device.h> 54 #if NRND > 0 55 #include <sys/rnd.h> 56 #endif 57 58 #include <net/if.h> 59 #include <net/if_dl.h> 60 #include <net/if_ether.h> 61 #include <net/if_media.h> 62 63 #ifdef INET 64 #include <netinet/in.h> 65 #include <netinet/in_systm.h> 66 #include <netinet/in_var.h> 67 #include <netinet/ip.h> 68 #include <netinet/if_inarp.h> 69 #endif 70 71 #ifdef NS 72 #include <netns/ns.h> 73 #include <netns/ns_if.h> 74 #endif 75 76 #if NBPFILTER > 0 77 #include <net/bpf.h> 78 #include <net/bpfdesc.h> 79 #endif 80 81 #include <machine/cpu.h> 82 #include <machine/bus.h> 83 #include <machine/intr.h> 84 85 #include <vm/vm.h> 86 #include <vm/pmap.h> 87 88 #include <dev/mii/miivar.h> 89 #include <dev/mii/mii.h> 90 91 #include <dev/ic/elink3reg.h> 92 /* #include <dev/ic/elink3var.h> */ 93 #include <dev/ic/elinkxlreg.h> 94 #include <dev/ic/elinkxlvar.h> 95 96 #ifdef DEBUG 97 int exdebug = 0; 98 #endif 99 100 /* ifmedia callbacks */ 101 int ex_media_chg __P((struct ifnet *ifp)); 102 void ex_media_stat __P((struct ifnet *ifp, struct ifmediareq *req)); 103 104 void ex_probe_media __P((struct ex_softc *)); 105 void ex_set_filter __P((struct ex_softc *)); 106 void ex_set_media __P((struct ex_softc *)); 107 struct mbuf *ex_get __P((struct ex_softc *, int)); 108 u_int16_t ex_read_eeprom __P((struct ex_softc *, int)); 109 void ex_init __P((struct ex_softc *)); 110 void ex_read __P((struct ex_softc *)); 111 void ex_reset __P((struct ex_softc *)); 112 void ex_set_mc __P((struct ex_softc *)); 113 void ex_getstats __P((struct ex_softc *)); 114 void ex_printstats __P((struct ex_softc *)); 115 void ex_tick __P((void *)); 116 117 static int ex_eeprom_busy __P((struct ex_softc *)); 118 static int ex_add_rxbuf __P((struct ex_softc *, struct ex_rxdesc *)); 119 static void ex_init_txdescs __P((struct ex_softc *)); 120 121 static void ex_shutdown __P((void *)); 122 static void ex_start __P((struct ifnet *)); 123 static void ex_txstat __P((struct ex_softc *)); 124 static u_int16_t ex_mchash __P((u_char *)); 125 static void ex_mii_writebits __P((struct ex_softc *, u_int, int)); 126 127 void ex_mii_setbit __P((void *, u_int16_t)); 128 void ex_mii_clrbit __P((void *, u_int16_t)); 129 u_int16_t ex_mii_readbit __P((void *, u_int16_t)); 130 int ex_mii_readreg __P((struct device *, int, int)); 131 void ex_mii_writereg __P((struct device *, int, int, int)); 132 void ex_mii_statchg __P((struct device *)); 133 134 void ex_probemedia __P((struct ex_softc *)); 135 136 /* 137 * Structure to map media-present bits in boards to ifmedia codes and 138 * printable media names. Used for table-driven ifmedia initialization. 139 */ 140 struct ex_media { 141 int exm_mpbit; /* media present bit */ 142 const char *exm_name; /* name of medium */ 143 int exm_ifmedia; /* ifmedia word for medium */ 144 int exm_epmedia; /* ELINKMEDIA_* constant */ 145 }; 146 147 /* 148 * Media table for 3c90x chips. Note that chips with MII have no 149 * `native' media. 150 */ 151 struct ex_media ex_native_media[] = { 152 { ELINK_PCI_10BASE_T, "10baseT", IFM_ETHER|IFM_10_T, 153 ELINKMEDIA_10BASE_T }, 154 { ELINK_PCI_10BASE_T, "10baseT-FDX", IFM_ETHER|IFM_10_T|IFM_FDX, 155 ELINKMEDIA_10BASE_T }, 156 { ELINK_PCI_AUI, "10base5", IFM_ETHER|IFM_10_5, 157 ELINKMEDIA_AUI }, 158 { ELINK_PCI_BNC, "10base2", IFM_ETHER|IFM_10_2, 159 ELINKMEDIA_10BASE_2 }, 160 { ELINK_PCI_100BASE_TX, "100baseTX", IFM_ETHER|IFM_100_TX, 161 ELINKMEDIA_100BASE_TX }, 162 { ELINK_PCI_100BASE_TX, "100baseTX-FDX",IFM_ETHER|IFM_100_TX|IFM_FDX, 163 ELINKMEDIA_100BASE_TX }, 164 { ELINK_PCI_100BASE_FX, "100baseFX", IFM_ETHER|IFM_100_FX, 165 ELINKMEDIA_100BASE_FX }, 166 { ELINK_PCI_100BASE_MII,"manual", IFM_ETHER|IFM_MANUAL, 167 ELINKMEDIA_MII }, 168 { ELINK_PCI_100BASE_T4, "100baseT4", IFM_ETHER|IFM_100_T4, 169 ELINKMEDIA_100BASE_T4 }, 170 { 0, NULL, 0, 171 0 }, 172 }; 173 174 /* 175 * Back-end attach and configure. 176 */ 177 void 178 ex_config(sc) 179 struct ex_softc *sc; 180 { 181 struct ifnet *ifp; 182 u_int16_t val; 183 u_int8_t macaddr[ETHER_ADDR_LEN] = {0}; 184 bus_space_tag_t iot = sc->sc_iot; 185 bus_space_handle_t ioh = sc->sc_ioh; 186 bus_dma_segment_t useg, dseg; 187 int urseg, drseg, i, error, attach_stage; 188 189 ex_reset(sc); 190 191 val = ex_read_eeprom(sc, EEPROM_OEM_ADDR0); 192 macaddr[0] = val >> 8; 193 macaddr[1] = val & 0xff; 194 val = ex_read_eeprom(sc, EEPROM_OEM_ADDR1); 195 macaddr[2] = val >> 8; 196 macaddr[3] = val & 0xff; 197 val = ex_read_eeprom(sc, EEPROM_OEM_ADDR2); 198 macaddr[4] = val >> 8; 199 macaddr[5] = val & 0xff; 200 201 printf("%s: MAC address %s\n", sc->sc_dev.dv_xname, 202 ether_sprintf(macaddr)); 203 204 attach_stage = 0; 205 206 /* 207 * Allocate the upload descriptors, and create and load the DMA 208 * map for them. 209 */ 210 if ((error = bus_dmamem_alloc(sc->sc_dmat, 211 EX_NUPD * sizeof (struct ex_upd), NBPG, 0, &useg, 1, &urseg, 212 BUS_DMA_NOWAIT)) != 0) { 213 printf("%s: can't allocate upload descriptors, error = %d\n", 214 sc->sc_dev.dv_xname, error); 215 goto fail; 216 } 217 218 attach_stage = 1; 219 220 if ((error = bus_dmamem_map(sc->sc_dmat, &useg, urseg, 221 EX_NUPD * sizeof (struct ex_upd), (caddr_t *)&sc->sc_upd, 222 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 223 printf("%s: can't map upload descriptors, error = %d\n", 224 sc->sc_dev.dv_xname, error); 225 goto fail; 226 } 227 228 attach_stage = 2; 229 230 if ((error = bus_dmamap_create(sc->sc_dmat, 231 EX_NUPD * sizeof (struct ex_upd), 1, 232 EX_NUPD * sizeof (struct ex_upd), 0, BUS_DMA_NOWAIT, 233 &sc->sc_upd_dmamap)) != 0) { 234 printf("%s: can't create upload desc. DMA map, error = %d\n", 235 sc->sc_dev.dv_xname, error); 236 goto fail; 237 } 238 239 attach_stage = 3; 240 241 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_upd_dmamap, 242 sc->sc_upd, EX_NUPD * sizeof (struct ex_upd), NULL, 243 BUS_DMA_NOWAIT)) != 0) { 244 printf("%s: can't load upload desc. DMA map, error = %d\n", 245 sc->sc_dev.dv_xname, error); 246 goto fail; 247 } 248 249 attach_stage = 4; 250 251 /* 252 * Allocate the download descriptors, and create and load the DMA 253 * map for them. 254 */ 255 if ((error = bus_dmamem_alloc(sc->sc_dmat, 256 EX_NDPD * sizeof (struct ex_dpd), NBPG, 0, &dseg, 1, &drseg, 257 BUS_DMA_NOWAIT)) != 0) { 258 printf("%s: can't allocate download descriptors, error = %d\n", 259 sc->sc_dev.dv_xname, error); 260 goto fail; 261 } 262 263 attach_stage = 5; 264 265 if ((error = bus_dmamem_map(sc->sc_dmat, &dseg, drseg, 266 EX_NDPD * sizeof (struct ex_dpd), (caddr_t *)&sc->sc_dpd, 267 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 268 printf("%s: can't map download descriptors, error = %d\n", 269 sc->sc_dev.dv_xname, error); 270 goto fail; 271 } 272 bzero(sc->sc_dpd, EX_NDPD * sizeof (struct ex_dpd)); 273 274 attach_stage = 6; 275 276 if ((error = bus_dmamap_create(sc->sc_dmat, 277 EX_NDPD * sizeof (struct ex_dpd), 1, 278 EX_NDPD * sizeof (struct ex_dpd), 0, BUS_DMA_NOWAIT, 279 &sc->sc_dpd_dmamap)) != 0) { 280 printf("%s: can't create download desc. DMA map, error = %d\n", 281 sc->sc_dev.dv_xname, error); 282 goto fail; 283 } 284 285 attach_stage = 7; 286 287 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dpd_dmamap, 288 sc->sc_dpd, EX_NDPD * sizeof (struct ex_dpd), NULL, 289 BUS_DMA_NOWAIT)) != 0) { 290 printf("%s: can't load download desc. DMA map, error = %d\n", 291 sc->sc_dev.dv_xname, error); 292 goto fail; 293 } 294 295 attach_stage = 8; 296 297 298 /* 299 * Create the transmit buffer DMA maps. 300 */ 301 for (i = 0; i < EX_NDPD; i++) { 302 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 303 EX_NTFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 304 &sc->sc_tx_dmamaps[i])) != 0) { 305 printf("%s: can't create tx DMA map %d, error = %d\n", 306 sc->sc_dev.dv_xname, i, error); 307 goto fail; 308 } 309 } 310 311 attach_stage = 9; 312 313 /* 314 * Create the receive buffer DMA maps. 315 */ 316 for (i = 0; i < EX_NUPD; i++) { 317 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 318 EX_NRFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 319 &sc->sc_rx_dmamaps[i])) != 0) { 320 printf("%s: can't create rx DMA map %d, error = %d\n", 321 sc->sc_dev.dv_xname, i, error); 322 goto fail; 323 } 324 } 325 326 attach_stage = 10; 327 328 /* 329 * Create ring of upload descriptors, only once. The DMA engine 330 * will loop over this when receiving packets, stalling if it 331 * hits an UPD with a finished receive. 332 */ 333 for (i = 0; i < EX_NUPD; i++) { 334 sc->sc_rxdescs[i].rx_dmamap = sc->sc_rx_dmamaps[i]; 335 sc->sc_rxdescs[i].rx_upd = &sc->sc_upd[i]; 336 sc->sc_upd[i].upd_frags[0].fr_len = (MCLBYTES - 2) | EX_FR_LAST; 337 if (ex_add_rxbuf(sc, &sc->sc_rxdescs[i]) != 0) { 338 printf("%s: can't allocate or map rx buffers\n", 339 sc->sc_dev.dv_xname); 340 goto fail; 341 } 342 } 343 344 bus_dmamap_sync(sc->sc_dmat, sc->sc_upd_dmamap, 0, 345 EX_NUPD * sizeof (struct ex_upd), 346 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 347 348 ex_init_txdescs(sc); 349 350 attach_stage = 11; 351 352 353 GO_WINDOW(3); 354 val = bus_space_read_2(iot, ioh, ELINK_W3_RESET_OPTIONS); 355 if (val & ELINK_MEDIACAP_MII) 356 sc->ex_conf |= EX_CONF_MII; 357 358 ifp = &sc->sc_ethercom.ec_if; 359 360 /* 361 * Initialize our media structures and MII info. We'll 362 * probe the MII if we discover that we have one. 363 */ 364 sc->ex_mii.mii_ifp = ifp; 365 sc->ex_mii.mii_readreg = ex_mii_readreg; 366 sc->ex_mii.mii_writereg = ex_mii_writereg; 367 sc->ex_mii.mii_statchg = ex_mii_statchg; 368 ifmedia_init(&sc->ex_mii.mii_media, 0, ex_media_chg, 369 ex_media_stat); 370 371 if (sc->ex_conf & EX_CONF_MII) { 372 /* 373 * Find PHY, extract media information from it. 374 */ 375 mii_phy_probe(&sc->sc_dev, &sc->ex_mii, 0xffffffff); 376 if (LIST_FIRST(&sc->ex_mii.mii_phys) == NULL) { 377 ifmedia_add(&sc->ex_mii.mii_media, IFM_ETHER|IFM_NONE, 378 0, NULL); 379 ifmedia_set(&sc->ex_mii.mii_media, IFM_ETHER|IFM_NONE); 380 } else { 381 ifmedia_set(&sc->ex_mii.mii_media, IFM_ETHER|IFM_AUTO); 382 } 383 } else 384 ex_probemedia(sc); 385 386 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 387 ifp->if_softc = sc; 388 ifp->if_start = ex_start; 389 ifp->if_ioctl = ex_ioctl; 390 ifp->if_watchdog = ex_watchdog; 391 ifp->if_flags = 392 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 393 394 if_attach(ifp); 395 ether_ifattach(ifp, macaddr); 396 397 GO_WINDOW(1); 398 399 sc->tx_start_thresh = 20; 400 sc->tx_succ_ok = 0; 401 402 /* TODO: set queues to 0 */ 403 404 #if NBPFILTER > 0 405 bpfattach(&sc->sc_ethercom.ec_if.if_bpf, ifp, DLT_EN10MB, 406 sizeof(struct ether_header)); 407 #endif 408 409 #if NRND > 0 410 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 411 RND_TYPE_NET, 0); 412 #endif 413 414 /* Establish callback to reset card when we reboot. */ 415 shutdownhook_establish(ex_shutdown, sc); 416 return; 417 418 fail: 419 /* 420 * Free any resources we've allocated during the failed attach 421 * attempt. Do this in reverse order and fall though. 422 */ 423 switch (attach_stage) { 424 case 11: 425 { 426 struct ex_rxdesc *rxd; 427 428 for (i = 0; i < EX_NUPD; i++) { 429 rxd = &sc->sc_rxdescs[i]; 430 if (rxd->rx_mbhead != NULL) { 431 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 432 m_freem(rxd->rx_mbhead); 433 } 434 } 435 } 436 /* FALLTHROUGH */ 437 438 case 10: 439 for (i = 0; i < EX_NUPD; i++) 440 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rx_dmamaps[i]); 441 /* FALLTHROUGH */ 442 443 case 9: 444 for (i = 0; i < EX_NDPD; i++) 445 bus_dmamap_destroy(sc->sc_dmat, sc->sc_tx_dmamaps[i]); 446 /* FALLTHROUGH */ 447 case 8: 448 bus_dmamap_unload(sc->sc_dmat, sc->sc_dpd_dmamap); 449 /* FALLTHROUGH */ 450 451 case 7: 452 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dpd_dmamap); 453 /* FALLTHROUGH */ 454 455 case 6: 456 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_dpd, 457 EX_NDPD * sizeof (struct ex_dpd)); 458 /* FALLTHROUGH */ 459 460 case 5: 461 bus_dmamem_free(sc->sc_dmat, &dseg, drseg); 462 break; 463 464 case 4: 465 bus_dmamap_unload(sc->sc_dmat, sc->sc_upd_dmamap); 466 /* FALLTHROUGH */ 467 468 case 3: 469 bus_dmamap_destroy(sc->sc_dmat, sc->sc_upd_dmamap); 470 /* FALLTHROUGH */ 471 472 case 2: 473 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_upd, 474 EX_NUPD * sizeof (struct ex_upd)); 475 /* FALLTHROUGH */ 476 477 case 1: 478 bus_dmamem_free(sc->sc_dmat, &useg, urseg); 479 break; 480 } 481 482 } 483 484 /* 485 * Find the media present on non-MII chips. 486 */ 487 void 488 ex_probemedia(sc) 489 struct ex_softc *sc; 490 { 491 bus_space_tag_t iot = sc->sc_iot; 492 bus_space_handle_t ioh = sc->sc_ioh; 493 struct ifmedia *ifm = &sc->ex_mii.mii_media; 494 struct ex_media *exm; 495 u_int16_t config1, reset_options, default_media; 496 int defmedia = 0; 497 const char *sep = "", *defmedianame = NULL; 498 499 GO_WINDOW(3); 500 config1 = bus_space_read_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG + 2); 501 reset_options = bus_space_read_1(iot, ioh, ELINK_W3_RESET_OPTIONS); 502 GO_WINDOW(0); 503 504 default_media = (config1 & CONFIG_MEDIAMASK) >> CONFIG_MEDIAMASK_SHIFT; 505 506 printf("%s: ", sc->sc_dev.dv_xname); 507 508 /* Sanity check that there are any media! */ 509 if ((reset_options & ELINK_PCI_MEDIAMASK) == 0) { 510 printf("no media present!\n"); 511 ifmedia_add(ifm, IFM_ETHER|IFM_NONE, 0, NULL); 512 ifmedia_set(ifm, IFM_ETHER|IFM_NONE); 513 return; 514 } 515 516 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 517 518 for (exm = ex_native_media; exm->exm_name != NULL; exm++) { 519 if (reset_options & exm->exm_mpbit) { 520 /* 521 * Default media is a little complicated. We 522 * support full-duplex which uses the same 523 * reset options bit. 524 * 525 * XXX Check EEPROM for default to FDX? 526 */ 527 if (exm->exm_epmedia == default_media) { 528 if ((exm->exm_ifmedia & IFM_FDX) == 0) { 529 defmedia = exm->exm_ifmedia; 530 defmedianame = exm->exm_name; 531 } 532 } else if (defmedia == 0) { 533 defmedia = exm->exm_ifmedia; 534 defmedianame = exm->exm_name; 535 } 536 ifmedia_add(ifm, exm->exm_ifmedia, exm->exm_epmedia, 537 NULL); 538 PRINT(exm->exm_name); 539 } 540 } 541 542 #undef PRINT 543 544 #ifdef DIAGNOSTIC 545 if (defmedia == 0) 546 panic("ex_probemedia: impossible"); 547 #endif 548 549 printf(", default %s\n", defmedianame); 550 ifmedia_set(ifm, defmedia); 551 } 552 553 /* 554 * Bring device up. 555 */ 556 void 557 ex_init(sc) 558 struct ex_softc *sc; 559 { 560 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 561 bus_space_tag_t iot = sc->sc_iot; 562 bus_space_handle_t ioh = sc->sc_ioh; 563 int s, i; 564 565 s = splnet(); 566 567 ex_waitcmd(sc); 568 ex_stop(sc); 569 570 /* 571 * Set the station address and clear the station mask. The latter 572 * is needed for 90x cards, 0 is the default for 90xB cards. 573 */ 574 GO_WINDOW(2); 575 for (i = 0; i < ETHER_ADDR_LEN; i++) { 576 bus_space_write_1(iot, ioh, ELINK_W2_ADDR_0 + i, 577 LLADDR(ifp->if_sadl)[i]); 578 bus_space_write_1(iot, ioh, ELINK_W2_RECVMASK_0 + i, 0); 579 } 580 581 GO_WINDOW(3); 582 583 bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_RESET); 584 ex_waitcmd(sc); 585 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_RESET); 586 ex_waitcmd(sc); 587 588 /* 589 * Disable reclaim threshold for 90xB, set free threshold to 590 * 6 * 256 = 1536 for 90x. 591 */ 592 if (sc->ex_conf & EX_CONF_90XB) 593 bus_space_write_2(iot, ioh, ELINK_COMMAND, 594 ELINK_TXRECLTHRESH | 255); 595 else 596 bus_space_write_1(iot, ioh, ELINK_TXFREETHRESH, 6); 597 598 bus_space_write_2(iot, ioh, ELINK_COMMAND, 599 SET_RX_EARLY_THRESH | ELINK_THRESH_DISABLE); 600 601 bus_space_write_4(iot, ioh, ELINK_DMACTRL, 602 bus_space_read_4(iot, ioh, ELINK_DMACTRL) | ELINK_DMAC_UPRXEAREN); 603 604 bus_space_write_2(iot, ioh, ELINK_COMMAND, SET_RD_0_MASK | S_MASK); 605 bus_space_write_2(iot, ioh, ELINK_COMMAND, SET_INTR_MASK | S_MASK); 606 607 bus_space_write_2(iot, ioh, ELINK_COMMAND, ACK_INTR | 0xff); 608 609 ex_set_media(sc); 610 ex_set_mc(sc); 611 612 613 bus_space_write_2(iot, ioh, ELINK_COMMAND, STATS_ENABLE); 614 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_ENABLE); 615 bus_space_write_4(iot, ioh, ELINK_UPLISTPTR, sc->sc_upddma); 616 bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_ENABLE); 617 bus_space_write_2(iot, ioh, ELINK_COMMAND, ELINK_UPUNSTALL); 618 619 ifp->if_flags |= IFF_RUNNING; 620 ifp->if_flags &= ~IFF_OACTIVE; 621 ex_start(ifp); 622 623 GO_WINDOW(1); 624 625 splx(s); 626 627 timeout(ex_tick, sc, hz); 628 } 629 630 /* 631 * Multicast hash filter according to the 3Com spec. 632 */ 633 static u_int16_t 634 ex_mchash(addr) 635 u_char *addr; 636 { 637 u_int32_t crc, carry; 638 int i, j; 639 u_char c; 640 641 /* Compute CRC for the address value. */ 642 crc = 0xffffffff; /* initial value */ 643 644 for (i = 0; i < 6; i++) { 645 c = addr[i]; 646 for (j = 0; j < 8; j++) { 647 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 648 crc <<= 1; 649 c >>= 1; 650 if (carry) 651 crc = (crc ^ 0x04c11db6) | carry; 652 } 653 } 654 655 /* Return the filter bit position. */ 656 return(crc & 0x000000ff); 657 } 658 659 660 /* 661 * Set multicast receive filter. Also take care of promiscuous mode 662 * here (XXX). 663 */ 664 void 665 ex_set_mc(sc) 666 register struct ex_softc *sc; 667 { 668 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 669 struct ethercom *ec = &sc->sc_ethercom; 670 struct ether_multi *enm; 671 struct ether_multistep estep; 672 int i; 673 u_int16_t mask = FIL_INDIVIDUAL | FIL_BRDCST; 674 675 if (ifp->if_flags & IFF_PROMISC) 676 mask |= FIL_PROMISC; 677 678 if (!(ifp->if_flags & IFF_MULTICAST)) 679 goto out; 680 681 if (!(sc->ex_conf & EX_CONF_90XB) || ifp->if_flags & IFF_ALLMULTI) { 682 mask |= (ifp->if_flags & IFF_MULTICAST) ? FIL_MULTICAST : 0; 683 } else { 684 ETHER_FIRST_MULTI(estep, ec, enm); 685 while (enm != NULL) { 686 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 687 ETHER_ADDR_LEN) != 0) 688 goto out; 689 i = ex_mchash(enm->enm_addrlo); 690 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 691 ELINK_COMMAND, ELINK_SETHASHFILBIT | i); 692 ETHER_NEXT_MULTI(estep, enm); 693 } 694 mask |= FIL_MULTIHASH; 695 } 696 out: 697 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_COMMAND, 698 SET_RX_FILTER | mask); 699 } 700 701 702 static void 703 ex_txstat(sc) 704 struct ex_softc *sc; 705 { 706 bus_space_tag_t iot = sc->sc_iot; 707 bus_space_handle_t ioh = sc->sc_ioh; 708 int i; 709 710 /* 711 * We need to read+write TX_STATUS until we get a 0 status 712 * in order to turn off the interrupt flag. 713 */ 714 while ((i = bus_space_read_1(iot, ioh, ELINK_TXSTATUS)) & TXS_COMPLETE) { 715 bus_space_write_1(iot, ioh, ELINK_TXSTATUS, 0x0); 716 717 if (i & TXS_JABBER) { 718 ++sc->sc_ethercom.ec_if.if_oerrors; 719 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 720 printf("%s: jabber (%x)\n", 721 sc->sc_dev.dv_xname, i); 722 ex_init(sc); 723 /* TODO: be more subtle here */ 724 } else if (i & TXS_UNDERRUN) { 725 ++sc->sc_ethercom.ec_if.if_oerrors; 726 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 727 printf("%s: fifo underrun (%x) @%d\n", 728 sc->sc_dev.dv_xname, i, 729 sc->tx_start_thresh); 730 if (sc->tx_succ_ok < 100) 731 sc->tx_start_thresh = min(ETHER_MAX_LEN, 732 sc->tx_start_thresh + 20); 733 sc->tx_succ_ok = 0; 734 ex_init(sc); 735 /* TODO: be more subtle here */ 736 } else if (i & TXS_MAX_COLLISION) { 737 ++sc->sc_ethercom.ec_if.if_collisions; 738 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_ENABLE); 739 sc->sc_ethercom.ec_if.if_flags &= ~IFF_OACTIVE; 740 } else 741 sc->tx_succ_ok = (sc->tx_succ_ok+1) & 127; 742 } 743 } 744 745 int 746 ex_media_chg(ifp) 747 struct ifnet *ifp; 748 { 749 struct ex_softc *sc = ifp->if_softc; 750 751 if (ifp->if_flags & IFF_UP) 752 ex_init(sc); 753 return 0; 754 } 755 756 void 757 ex_set_media(sc) 758 struct ex_softc *sc; 759 { 760 bus_space_tag_t iot = sc->sc_iot; 761 bus_space_handle_t ioh = sc->sc_ioh; 762 int config0, config1; 763 764 if (((sc->ex_conf & EX_CONF_MII) && 765 (sc->ex_mii.mii_media_active & IFM_FDX)) 766 || (!(sc->ex_conf & EX_CONF_MII) && 767 (sc->ex_mii.mii_media.ifm_media & IFM_FDX))) { 768 bus_space_write_2(iot, ioh, ELINK_W3_MAC_CONTROL, 769 MAC_CONTROL_FDX); 770 } else { 771 bus_space_write_2(iot, ioh, ELINK_W3_MAC_CONTROL, 0); 772 } 773 774 /* 775 * If the device has MII, select it, and then tell the 776 * PHY which media to use. 777 */ 778 if (sc->ex_conf & EX_CONF_MII) { 779 GO_WINDOW(3); 780 781 config0 = (u_int)bus_space_read_2(iot, ioh, 782 ELINK_W3_INTERNAL_CONFIG); 783 config1 = (u_int)bus_space_read_2(iot, ioh, 784 ELINK_W3_INTERNAL_CONFIG + 2); 785 786 config1 = config1 & ~CONFIG_MEDIAMASK; 787 config1 |= (ELINKMEDIA_MII << CONFIG_MEDIAMASK_SHIFT); 788 789 bus_space_write_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG, config0); 790 bus_space_write_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG + 2, config1); 791 mii_mediachg(&sc->ex_mii); 792 return; 793 } 794 795 GO_WINDOW(4); 796 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 0); 797 bus_space_write_2(iot, ioh, ELINK_COMMAND, STOP_TRANSCEIVER); 798 delay(800); 799 800 /* 801 * Now turn on the selected media/transceiver. 802 */ 803 switch (IFM_SUBTYPE(sc->ex_mii.mii_media.ifm_cur->ifm_media)) { 804 case IFM_10_T: 805 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 806 JABBER_GUARD_ENABLE|LINKBEAT_ENABLE); 807 break; 808 809 case IFM_10_2: 810 bus_space_write_2(iot, ioh, ELINK_COMMAND, START_TRANSCEIVER); 811 DELAY(800); 812 break; 813 814 case IFM_100_TX: 815 case IFM_100_FX: 816 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 817 LINKBEAT_ENABLE); 818 DELAY(800); 819 break; 820 821 case IFM_10_5: 822 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 823 SQE_ENABLE); 824 DELAY(800); 825 break; 826 827 case IFM_MANUAL: 828 break; 829 830 case IFM_NONE: 831 return; 832 833 default: 834 panic("ex_set_media: impossible"); 835 } 836 837 GO_WINDOW(3); 838 config0 = (u_int)bus_space_read_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG); 839 config1 = (u_int)bus_space_read_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG + 2); 840 841 config1 = config1 & ~CONFIG_MEDIAMASK; 842 config1 |= (sc->ex_mii.mii_media.ifm_cur->ifm_data << 843 CONFIG_MEDIAMASK_SHIFT); 844 845 bus_space_write_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG, config0); 846 bus_space_write_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG + 2, config1); 847 } 848 849 /* 850 * Get currently-selected media from card. 851 * (if_media callback, may be called before interface is brought up). 852 */ 853 void 854 ex_media_stat(ifp, req) 855 struct ifnet *ifp; 856 struct ifmediareq *req; 857 { 858 struct ex_softc *sc = ifp->if_softc; 859 860 if (sc->ex_conf & EX_CONF_MII) { 861 mii_pollstat(&sc->ex_mii); 862 req->ifm_status = sc->ex_mii.mii_media_status; 863 req->ifm_active = sc->ex_mii.mii_media_active; 864 } else { 865 GO_WINDOW(4); 866 req->ifm_status = IFM_AVALID; 867 req->ifm_active = sc->ex_mii.mii_media.ifm_cur->ifm_media; 868 if (bus_space_read_2(sc->sc_iot, sc->sc_ioh, 869 ELINK_W4_MEDIA_TYPE) & LINKBEAT_DETECT) 870 req->ifm_status |= IFM_ACTIVE; 871 GO_WINDOW(1); 872 } 873 } 874 875 876 877 /* 878 * Start outputting on the interface. 879 */ 880 static void 881 ex_start(ifp) 882 struct ifnet *ifp; 883 { 884 struct ex_softc *sc = ifp->if_softc; 885 bus_space_tag_t iot = sc->sc_iot; 886 bus_space_handle_t ioh = sc->sc_ioh; 887 volatile struct ex_fraghdr *fr = NULL; 888 volatile struct ex_dpd *dpd = NULL, *prevdpd = NULL; 889 struct ex_txdesc *txp; 890 bus_dmamap_t dmamap; 891 int offset, totlen; 892 893 if (sc->tx_head || sc->tx_free == NULL) 894 return; 895 896 txp = NULL; 897 898 /* 899 * We're finished if there is nothing more to add to the list or if 900 * we're all filled up with buffers to transmit. 901 */ 902 while (ifp->if_snd.ifq_head != NULL && sc->tx_free != NULL) { 903 struct mbuf *mb_head; 904 int segment, error; 905 906 /* 907 * Grab a packet to transmit. 908 */ 909 IF_DEQUEUE(&ifp->if_snd, mb_head); 910 911 /* 912 * Get pointer to next available tx desc. 913 */ 914 txp = sc->tx_free; 915 sc->tx_free = txp->tx_next; 916 txp->tx_next = NULL; 917 dmamap = txp->tx_dmamap; 918 919 /* 920 * Go through each of the mbufs in the chain and initialize 921 * the transmit buffer descriptors with the physical address 922 * and size of the mbuf. 923 */ 924 reload: 925 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 926 mb_head, BUS_DMA_NOWAIT); 927 switch (error) { 928 case 0: 929 /* Success. */ 930 break; 931 932 case EFBIG: 933 { 934 struct mbuf *mn; 935 936 /* 937 * We ran out of segments. We have to recopy this 938 * mbuf chain first. Bail out if we can't get the 939 * new buffers. 940 */ 941 printf("%s: too many segments, ", sc->sc_dev.dv_xname); 942 943 MGETHDR(mn, M_DONTWAIT, MT_DATA); 944 if (mn == NULL) { 945 m_freem(mb_head); 946 printf("aborting\n"); 947 goto out; 948 } 949 if (mb_head->m_pkthdr.len > MHLEN) { 950 MCLGET(mn, M_DONTWAIT); 951 if ((mn->m_flags & M_EXT) == 0) { 952 m_freem(mn); 953 m_freem(mb_head); 954 printf("aborting\n"); 955 goto out; 956 } 957 } 958 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 959 mtod(mn, caddr_t)); 960 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 961 m_freem(mb_head); 962 mb_head = mn; 963 printf("retrying\n"); 964 goto reload; 965 } 966 967 default: 968 /* 969 * Some other problem; report it. 970 */ 971 printf("%s: can't load mbuf chain, error = %d\n", 972 sc->sc_dev.dv_xname, error); 973 m_freem(mb_head); 974 goto out; 975 } 976 977 fr = &txp->tx_dpd->dpd_frags[0]; 978 totlen = 0; 979 for (segment = 0; segment < dmamap->dm_nsegs; segment++, fr++) { 980 fr->fr_addr = dmamap->dm_segs[segment].ds_addr; 981 fr->fr_len = dmamap->dm_segs[segment].ds_len; 982 totlen += fr->fr_len; 983 } 984 fr--; 985 fr->fr_len |= EX_FR_LAST; 986 txp->tx_mbhead = mb_head; 987 988 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 989 BUS_DMASYNC_PREWRITE); 990 991 dpd = txp->tx_dpd; 992 dpd->dpd_nextptr = 0; 993 dpd->dpd_fsh = totlen; 994 995 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap, 996 ((caddr_t)dpd - (caddr_t)sc->sc_dpd), 997 sizeof (struct ex_dpd), 998 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 999 1000 /* 1001 * No need to stall the download engine, we know it's 1002 * not busy right now. 1003 * 1004 * Fix up pointers in both the "soft" tx and the physical 1005 * tx list. 1006 */ 1007 if (sc->tx_head != NULL) { 1008 prevdpd = sc->tx_tail->tx_dpd; 1009 offset = ((caddr_t)prevdpd - (caddr_t)sc->sc_dpd); 1010 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap, 1011 offset, sizeof (struct ex_dpd), 1012 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1013 prevdpd->dpd_nextptr = DPD_DMADDR(sc, txp); 1014 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap, 1015 offset, sizeof (struct ex_dpd), 1016 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1017 sc->tx_tail->tx_next = txp; 1018 sc->tx_tail = txp; 1019 } else { 1020 sc->tx_tail = sc->tx_head = txp; 1021 } 1022 1023 #if NBPFILTER > 0 1024 /* 1025 * Pass packet to bpf if there is a listener. 1026 */ 1027 if (ifp->if_bpf) 1028 bpf_mtap(ifp->if_bpf, mb_head); 1029 #endif 1030 } 1031 out: 1032 if (sc->tx_head) { 1033 sc->tx_tail->tx_dpd->dpd_fsh |= EX_DPD_DNIND; 1034 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap, 1035 ((caddr_t)sc->tx_tail->tx_dpd - (caddr_t)sc->sc_dpd), 1036 sizeof (struct ex_dpd), 1037 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1038 ifp->if_flags |= IFF_OACTIVE; 1039 bus_space_write_2(iot, ioh, ELINK_COMMAND, ELINK_DNUNSTALL); 1040 bus_space_write_4(iot, ioh, ELINK_DNLISTPTR, 1041 DPD_DMADDR(sc, sc->tx_head)); 1042 1043 /* trigger watchdog */ 1044 ifp->if_timer = 5; 1045 } 1046 } 1047 1048 1049 int 1050 ex_intr(arg) 1051 void *arg; 1052 { 1053 struct ex_softc *sc = arg; 1054 bus_space_tag_t iot = sc->sc_iot; 1055 bus_space_handle_t ioh = sc->sc_ioh; 1056 u_int16_t stat; 1057 int ret = 0; 1058 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1059 1060 for (;;) { 1061 stat = bus_space_read_2(iot, ioh, ELINK_STATUS); 1062 if (!(stat & S_MASK)) 1063 break; 1064 /* 1065 * Acknowledge interrupts. 1066 */ 1067 bus_space_write_2(iot, ioh, ELINK_COMMAND, ACK_INTR | 1068 (stat & S_MASK)); 1069 ret = 1; 1070 if (stat & S_HOST_ERROR) { 1071 printf("%s: adapter failure (%x)\n", 1072 sc->sc_dev.dv_xname, stat); 1073 bus_space_write_2(iot, ioh, ELINK_COMMAND, 1074 C_INTR_LATCH); 1075 ex_reset(sc); 1076 ex_init(sc); 1077 return 1; 1078 } 1079 if (stat & S_TX_COMPLETE) { 1080 ex_txstat(sc); 1081 } 1082 if (stat & S_UPD_STATS) { 1083 ex_getstats(sc); 1084 } 1085 if (stat & S_DN_COMPLETE) { 1086 struct ex_txdesc *txp, *ptxp = NULL; 1087 bus_dmamap_t txmap; 1088 1089 /* reset watchdog timer, was set in ex_start() */ 1090 ifp->if_timer = 0; 1091 1092 for (txp = sc->tx_head; txp != NULL; 1093 txp = txp->tx_next) { 1094 bus_dmamap_sync(sc->sc_dmat, 1095 sc->sc_dpd_dmamap, 1096 (caddr_t)txp->tx_dpd - (caddr_t)sc->sc_dpd, 1097 sizeof (struct ex_dpd), 1098 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1099 if (txp->tx_mbhead != NULL) { 1100 txmap = txp->tx_dmamap; 1101 bus_dmamap_sync(sc->sc_dmat, txmap, 1102 0, txmap->dm_mapsize, 1103 BUS_DMASYNC_POSTWRITE); 1104 bus_dmamap_unload(sc->sc_dmat, txmap); 1105 m_freem(txp->tx_mbhead); 1106 txp->tx_mbhead = NULL; 1107 } 1108 ptxp = txp; 1109 } 1110 1111 /* 1112 * Move finished tx buffers back to the tx free list. 1113 */ 1114 if (sc->tx_free) { 1115 sc->tx_ftail->tx_next = sc->tx_head; 1116 sc->tx_ftail = ptxp; 1117 } else 1118 sc->tx_ftail = sc->tx_free = sc->tx_head; 1119 1120 sc->tx_head = sc->tx_tail = NULL; 1121 ifp->if_flags &= ~IFF_OACTIVE; 1122 } 1123 1124 if (stat & S_UP_COMPLETE) { 1125 struct ex_rxdesc *rxd; 1126 struct mbuf *m; 1127 struct ex_upd *upd; 1128 bus_dmamap_t rxmap; 1129 u_int32_t pktstat; 1130 1131 rcvloop: 1132 rxd = sc->rx_head; 1133 rxmap = rxd->rx_dmamap; 1134 m = rxd->rx_mbhead; 1135 upd = rxd->rx_upd; 1136 pktstat = upd->upd_pktstatus; 1137 1138 bus_dmamap_sync(sc->sc_dmat, rxmap, 0, 1139 rxmap->dm_mapsize, 1140 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1141 bus_dmamap_sync(sc->sc_dmat, sc->sc_upd_dmamap, 1142 ((caddr_t)upd - (caddr_t)sc->sc_upd), 1143 sizeof (struct ex_upd), 1144 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1145 1146 if (pktstat & EX_UPD_COMPLETE) { 1147 /* 1148 * Remove first packet from the chain. 1149 */ 1150 sc->rx_head = rxd->rx_next; 1151 rxd->rx_next = NULL; 1152 1153 /* 1154 * Add a new buffer to the receive chain. 1155 * If this fails, the old buffer is recycled 1156 * instead. 1157 */ 1158 if (ex_add_rxbuf(sc, rxd) == 0) { 1159 struct ether_header *eh; 1160 u_int16_t total_len; 1161 1162 1163 if (pktstat & EX_UPD_ERR) { 1164 ifp->if_ierrors++; 1165 m_freem(m); 1166 goto rcvloop; 1167 } 1168 1169 total_len = pktstat & EX_UPD_PKTLENMASK; 1170 if (total_len < 1171 sizeof(struct ether_header)) { 1172 m_freem(m); 1173 goto rcvloop; 1174 } 1175 m->m_pkthdr.rcvif = ifp; 1176 m->m_pkthdr.len = m->m_len = 1177 total_len - 1178 sizeof(struct ether_header); 1179 eh = mtod(m, struct ether_header *); 1180 #if NBPFILTER > 0 1181 if (ifp->if_bpf) { 1182 bpf_tap(ifp->if_bpf, 1183 mtod(m, caddr_t), 1184 total_len); 1185 /* 1186 * Only pass this packet up 1187 * if it is for us. 1188 */ 1189 if ((ifp->if_flags & 1190 IFF_PROMISC) && 1191 (eh->ether_dhost[0] & 1) 1192 == 0 && 1193 bcmp(eh->ether_dhost, 1194 LLADDR(ifp->if_sadl), 1195 sizeof(eh->ether_dhost)) 1196 != 0) { 1197 m_freem(m); 1198 goto rcvloop; 1199 } 1200 } 1201 #endif /* NBPFILTER > 0 */ 1202 m->m_data += 1203 sizeof(struct ether_header); 1204 ether_input(ifp, eh, m); 1205 } 1206 goto rcvloop; 1207 } 1208 /* 1209 * Just in case we filled up all UPDs and the DMA engine 1210 * stalled. We could be more subtle about this. 1211 */ 1212 if (bus_space_read_4(iot, ioh, ELINK_UPLISTPTR) == 0) { 1213 printf("%s: uplistptr was 0\n", 1214 sc->sc_dev.dv_xname); 1215 ex_init(sc); 1216 } else if (bus_space_read_4(iot, ioh, ELINK_UPPKTSTATUS) 1217 & 0x2000) { 1218 printf("%s: receive stalled\n", 1219 sc->sc_dev.dv_xname); 1220 bus_space_write_2(iot, ioh, ELINK_COMMAND, 1221 ELINK_UPUNSTALL); 1222 } 1223 } 1224 } 1225 if (ret) { 1226 bus_space_write_2(iot, ioh, ELINK_COMMAND, C_INTR_LATCH); 1227 if (ifp->if_snd.ifq_head != NULL) 1228 ex_start(ifp); 1229 } 1230 return ret; 1231 } 1232 1233 int 1234 ex_ioctl(ifp, cmd, data) 1235 register struct ifnet *ifp; 1236 u_long cmd; 1237 caddr_t data; 1238 { 1239 struct ex_softc *sc = ifp->if_softc; 1240 struct ifaddr *ifa = (struct ifaddr *)data; 1241 struct ifreq *ifr = (struct ifreq *)data; 1242 int s, error = 0; 1243 1244 s = splnet(); 1245 1246 switch (cmd) { 1247 1248 case SIOCSIFADDR: 1249 ifp->if_flags |= IFF_UP; 1250 switch (ifa->ifa_addr->sa_family) { 1251 #ifdef INET 1252 case AF_INET: 1253 ex_init(sc); 1254 arp_ifinit(&sc->sc_ethercom.ec_if, ifa); 1255 break; 1256 #endif 1257 #ifdef NS 1258 case AF_NS: 1259 { 1260 register struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1261 1262 if (ns_nullhost(*ina)) 1263 ina->x_host = *(union ns_host *) 1264 LLADDR(ifp->if_sadl); 1265 else 1266 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 1267 ifp->if_addrlen); 1268 /* Set new address. */ 1269 ex_init(sc); 1270 break; 1271 } 1272 #endif 1273 default: 1274 ex_init(sc); 1275 break; 1276 } 1277 break; 1278 case SIOCSIFMEDIA: 1279 case SIOCGIFMEDIA: 1280 error = ifmedia_ioctl(ifp, ifr, &sc->ex_mii.mii_media, cmd); 1281 break; 1282 1283 case SIOCSIFFLAGS: 1284 if ((ifp->if_flags & IFF_UP) == 0 && 1285 (ifp->if_flags & IFF_RUNNING) != 0) { 1286 /* 1287 * If interface is marked down and it is running, then 1288 * stop it. 1289 */ 1290 ex_stop(sc); 1291 ifp->if_flags &= ~IFF_RUNNING; 1292 } else if ((ifp->if_flags & IFF_UP) != 0 && 1293 (ifp->if_flags & IFF_RUNNING) == 0) { 1294 /* 1295 * If interface is marked up and it is stopped, then 1296 * start it. 1297 */ 1298 ex_init(sc); 1299 } else if ((ifp->if_flags & IFF_UP) != 0) { 1300 /* 1301 * Deal with other flags that change hardware 1302 * state, i.e. IFF_PROMISC. 1303 */ 1304 ex_set_mc(sc); 1305 } 1306 break; 1307 1308 case SIOCADDMULTI: 1309 case SIOCDELMULTI: 1310 error = (cmd == SIOCADDMULTI) ? 1311 ether_addmulti(ifr, &sc->sc_ethercom) : 1312 ether_delmulti(ifr, &sc->sc_ethercom); 1313 1314 if (error == ENETRESET) { 1315 /* 1316 * Multicast list has changed; set the hardware filter 1317 * accordingly. 1318 */ 1319 ex_set_mc(sc); 1320 error = 0; 1321 } 1322 break; 1323 1324 default: 1325 error = EINVAL; 1326 break; 1327 } 1328 1329 splx(s); 1330 return (error); 1331 } 1332 1333 void 1334 ex_getstats(sc) 1335 struct ex_softc *sc; 1336 { 1337 bus_space_handle_t ioh = sc->sc_ioh; 1338 bus_space_tag_t iot = sc->sc_iot; 1339 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1340 u_int8_t upperok; 1341 1342 GO_WINDOW(6); 1343 upperok = bus_space_read_1(iot, ioh, UPPER_FRAMES_OK); 1344 ifp->if_ipackets += bus_space_read_1(iot, ioh, RX_FRAMES_OK); 1345 ifp->if_ipackets += (upperok & 0x03) << 8; 1346 ifp->if_opackets += bus_space_read_1(iot, ioh, TX_FRAMES_OK); 1347 ifp->if_opackets += (upperok & 0x30) << 4; 1348 ifp->if_ierrors += bus_space_read_1(iot, ioh, RX_OVERRUNS); 1349 ifp->if_oerrors += bus_space_read_1(iot, ioh, TX_DEFERRALS); 1350 ifp->if_collisions += bus_space_read_1(iot, ioh, TX_COLLISIONS); 1351 /* 1352 * There seems to be no way to get the exact number of collisions, 1353 * this is the number that occured at the very least. 1354 */ 1355 ifp->if_collisions += 2 * bus_space_read_1(iot, ioh, 1356 TX_AFTER_X_COLLISIONS); 1357 ifp->if_ibytes += bus_space_read_2(iot, ioh, RX_TOTAL_OK); 1358 ifp->if_obytes += bus_space_read_2(iot, ioh, TX_TOTAL_OK); 1359 1360 /* 1361 * Clear the following to avoid stats overflow interrupts 1362 */ 1363 bus_space_read_1(iot, ioh, TX_AFTER_1_COLLISION); 1364 bus_space_read_1(iot, ioh, TX_NO_SQE); 1365 bus_space_read_1(iot, ioh, TX_CD_LOST); 1366 GO_WINDOW(4); 1367 bus_space_read_1(iot, ioh, ELINK_W4_BADSSD); 1368 upperok = bus_space_read_1(iot, ioh, ELINK_W4_UBYTESOK); 1369 ifp->if_ibytes += (upperok & 0x0f) << 16; 1370 ifp->if_obytes += (upperok & 0xf0) << 12; 1371 GO_WINDOW(1); 1372 } 1373 1374 void 1375 ex_printstats(sc) 1376 struct ex_softc *sc; 1377 { 1378 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1379 1380 ex_getstats(sc); 1381 printf("in %ld out %ld ierror %ld oerror %ld ibytes %ld obytes %ld\n", 1382 ifp->if_ipackets, ifp->if_opackets, ifp->if_ierrors, 1383 ifp->if_oerrors, ifp->if_ibytes, ifp->if_obytes); 1384 } 1385 1386 void 1387 ex_tick(arg) 1388 void *arg; 1389 { 1390 struct ex_softc *sc = arg; 1391 int s = splnet(); 1392 1393 if (sc->ex_conf & EX_CONF_MII) 1394 mii_tick(&sc->ex_mii); 1395 1396 if (!(bus_space_read_2((sc)->sc_iot, (sc)->sc_ioh, ELINK_STATUS) 1397 & S_COMMAND_IN_PROGRESS)) 1398 ex_getstats(sc); 1399 1400 splx(s); 1401 1402 timeout(ex_tick, sc, hz); 1403 } 1404 1405 1406 void 1407 ex_reset(sc) 1408 struct ex_softc *sc; 1409 { 1410 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_COMMAND, GLOBAL_RESET); 1411 ex_waitcmd(sc); 1412 } 1413 1414 void 1415 ex_watchdog(ifp) 1416 struct ifnet *ifp; 1417 { 1418 struct ex_softc *sc = ifp->if_softc; 1419 1420 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1421 ++sc->sc_ethercom.ec_if.if_oerrors; 1422 1423 ex_reset(sc); 1424 ex_init(sc); 1425 } 1426 1427 void 1428 ex_stop(sc) 1429 struct ex_softc *sc; 1430 { 1431 bus_space_tag_t iot = sc->sc_iot; 1432 bus_space_handle_t ioh = sc->sc_ioh; 1433 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1434 struct ex_txdesc *tx; 1435 struct ex_rxdesc *rx; 1436 int i; 1437 1438 bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_DISABLE); 1439 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_DISABLE); 1440 bus_space_write_2(iot, ioh, ELINK_COMMAND, STOP_TRANSCEIVER); 1441 1442 for (tx = sc->tx_head ; tx != NULL; tx = tx->tx_next) { 1443 if (tx->tx_mbhead == NULL) 1444 continue; 1445 m_freem(tx->tx_mbhead); 1446 tx->tx_mbhead = NULL; 1447 bus_dmamap_unload(sc->sc_dmat, tx->tx_dmamap); 1448 tx->tx_dpd->dpd_fsh = tx->tx_dpd->dpd_nextptr = 0; 1449 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap, 1450 ((caddr_t)tx->tx_dpd - (caddr_t)sc->sc_dpd), 1451 sizeof (struct ex_dpd), 1452 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1453 } 1454 sc->tx_tail = sc->tx_head = NULL; 1455 ex_init_txdescs(sc); 1456 1457 sc->rx_tail = sc->rx_head = 0; 1458 for (i = 0; i < EX_NUPD; i++) { 1459 rx = &sc->sc_rxdescs[i]; 1460 if (rx->rx_mbhead != NULL) { 1461 bus_dmamap_unload(sc->sc_dmat, rx->rx_dmamap); 1462 m_freem(rx->rx_mbhead); 1463 rx->rx_mbhead = NULL; 1464 } 1465 ex_add_rxbuf(sc, rx); 1466 } 1467 1468 bus_space_write_2(iot, ioh, ELINK_COMMAND, C_INTR_LATCH); 1469 1470 untimeout(ex_tick, sc); 1471 1472 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1473 ifp->if_timer = 0; 1474 } 1475 1476 static void 1477 ex_init_txdescs(sc) 1478 struct ex_softc *sc; 1479 { 1480 int i; 1481 1482 for (i = 0; i < EX_NDPD; i++) { 1483 sc->sc_txdescs[i].tx_dmamap = sc->sc_tx_dmamaps[i]; 1484 sc->sc_txdescs[i].tx_dpd = &sc->sc_dpd[i]; 1485 if (i < EX_NDPD - 1) 1486 sc->sc_txdescs[i].tx_next = &sc->sc_txdescs[i + 1]; 1487 else 1488 sc->sc_txdescs[i].tx_next = NULL; 1489 } 1490 sc->tx_free = &sc->sc_txdescs[0]; 1491 sc->tx_ftail = &sc->sc_txdescs[EX_NDPD-1]; 1492 } 1493 1494 1495 /* 1496 * Before reboots, reset card completely. 1497 */ 1498 static void 1499 ex_shutdown(arg) 1500 void *arg; 1501 { 1502 register struct ex_softc *sc = arg; 1503 1504 ex_stop(sc); 1505 } 1506 1507 /* 1508 * Read EEPROM data. 1509 * XXX what to do if EEPROM doesn't unbusy? 1510 */ 1511 u_int16_t 1512 ex_read_eeprom(sc, offset) 1513 struct ex_softc *sc; 1514 int offset; 1515 { 1516 bus_space_tag_t iot = sc->sc_iot; 1517 bus_space_handle_t ioh = sc->sc_ioh; 1518 u_int16_t data = 0; 1519 1520 GO_WINDOW(0); 1521 if (ex_eeprom_busy(sc)) 1522 goto out; 1523 switch (sc->ex_bustype) { 1524 case EX_BUS_PCI: 1525 bus_space_write_1(iot, ioh, ELINK_W0_EEPROM_COMMAND, 1526 READ_EEPROM | (offset & 0x3f)); 1527 break; 1528 case EX_BUS_CARDBUS: 1529 bus_space_write_2(iot, ioh, ELINK_W0_EEPROM_COMMAND, 1530 0x230 + (offset & 0x3f)); 1531 break; 1532 } 1533 if (ex_eeprom_busy(sc)) 1534 goto out; 1535 data = bus_space_read_2(iot, ioh, ELINK_W0_EEPROM_DATA); 1536 out: 1537 return data; 1538 } 1539 1540 static int 1541 ex_eeprom_busy(sc) 1542 struct ex_softc *sc; 1543 { 1544 bus_space_tag_t iot = sc->sc_iot; 1545 bus_space_handle_t ioh = sc->sc_ioh; 1546 int i = 100; 1547 1548 while (i--) { 1549 if (!(bus_space_read_2(iot, ioh, ELINK_W0_EEPROM_COMMAND) & 1550 EEPROM_BUSY)) 1551 return 0; 1552 delay(100); 1553 } 1554 printf("\n%s: eeprom stays busy.\n", sc->sc_dev.dv_xname); 1555 return (1); 1556 } 1557 1558 /* 1559 * Create a new rx buffer and add it to the 'soft' rx list. 1560 */ 1561 static int 1562 ex_add_rxbuf(sc, rxd) 1563 struct ex_softc *sc; 1564 struct ex_rxdesc *rxd; 1565 { 1566 struct mbuf *m, *oldm; 1567 bus_dmamap_t rxmap; 1568 int error, rval = 0; 1569 1570 oldm = rxd->rx_mbhead; 1571 rxmap = rxd->rx_dmamap; 1572 1573 MGETHDR(m, M_DONTWAIT, MT_DATA); 1574 if (m != NULL) { 1575 MCLGET(m, M_DONTWAIT); 1576 if ((m->m_flags & M_EXT) == 0) { 1577 m_freem(m); 1578 if (oldm == NULL) 1579 return 1; 1580 m = oldm; 1581 m->m_data = m->m_ext.ext_buf; 1582 rval = 1; 1583 } 1584 } else { 1585 if (oldm == NULL) 1586 return 1; 1587 m = oldm; 1588 m->m_data = m->m_ext.ext_buf; 1589 rval = 1; 1590 } 1591 1592 /* 1593 * Setup the DMA map for this receive buffer. 1594 */ 1595 if (m != oldm) { 1596 if (oldm != NULL) 1597 bus_dmamap_unload(sc->sc_dmat, rxmap); 1598 error = bus_dmamap_load(sc->sc_dmat, rxmap, 1599 m->m_ext.ext_buf, MCLBYTES, NULL, BUS_DMA_NOWAIT); 1600 if (error) { 1601 printf("%s: can't load rx buffer, error = %d\n", 1602 sc->sc_dev.dv_xname, error); 1603 panic("ex_add_rxbuf"); /* XXX */ 1604 } 1605 } 1606 1607 /* 1608 * Align for data after 14 byte header. 1609 */ 1610 m->m_data += 2; 1611 1612 rxd->rx_mbhead = m; 1613 rxd->rx_upd->upd_pktstatus = MCLBYTES - 2; 1614 rxd->rx_upd->upd_frags[0].fr_addr = rxmap->dm_segs[0].ds_addr + 2; 1615 rxd->rx_upd->upd_nextptr = 0; 1616 1617 /* 1618 * Attach it to the end of the list. 1619 */ 1620 if (sc->rx_head != NULL) { 1621 sc->rx_tail->rx_next = rxd; 1622 sc->rx_tail->rx_upd->upd_nextptr = sc->sc_upddma + 1623 ((caddr_t)rxd->rx_upd - (caddr_t)sc->sc_upd); 1624 bus_dmamap_sync(sc->sc_dmat, sc->sc_upd_dmamap, 1625 (caddr_t)sc->rx_tail->rx_upd - (caddr_t)sc->sc_upd, 1626 sizeof (struct ex_upd), 1627 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1628 } else { 1629 sc->rx_head = rxd; 1630 } 1631 sc->rx_tail = rxd; 1632 1633 bus_dmamap_sync(sc->sc_dmat, rxmap, 0, rxmap->dm_mapsize, 1634 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1635 bus_dmamap_sync(sc->sc_dmat, sc->sc_upd_dmamap, 1636 ((caddr_t)rxd->rx_upd - (caddr_t)sc->sc_upd), 1637 sizeof (struct ex_upd), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1638 return (rval); 1639 } 1640 1641 void 1642 ex_mii_setbit(v, bit) 1643 void *v; 1644 u_int16_t bit; 1645 { 1646 struct ex_softc *sc = v; 1647 u_int16_t val; 1648 1649 val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_PHYSMGMT); 1650 val |= bit; 1651 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_PHYSMGMT, val); 1652 } 1653 1654 void 1655 ex_mii_clrbit(v, bit) 1656 void *v; 1657 u_int16_t bit; 1658 { 1659 struct ex_softc *sc = v; 1660 u_int16_t val; 1661 1662 val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_PHYSMGMT); 1663 val &= ~bit; 1664 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_PHYSMGMT, val); 1665 } 1666 1667 u_int16_t 1668 ex_mii_readbit(v, bit) 1669 void *v; 1670 u_int16_t bit; 1671 { 1672 struct ex_softc *sc = v; 1673 u_int16_t val; 1674 1675 val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_PHYSMGMT); 1676 return (val & bit); 1677 } 1678 1679 /* 1680 * The reason why all this stuff below is here, is that we need a special 1681 * readreg function. It needs to check if we're accessing the internal 1682 * PHY on 905B-TX boards, or not. If so, the read must fail immediately, 1683 * because 905B-TX boards seem to return garbage from the MII if you 1684 * try to access non-existing PHYs. 1685 */ 1686 1687 int 1688 ex_mii_readreg(v, phy, reg) 1689 struct device *v; 1690 int phy; 1691 int reg; 1692 { 1693 struct ex_softc *sc = (struct ex_softc *)v; 1694 int val = 0; 1695 int err =0; 1696 int i; 1697 1698 if ((sc->ex_conf & EX_CONF_INTPHY) && phy != ELINK_INTPHY_ID) 1699 return 0; 1700 1701 GO_WINDOW(4); 1702 1703 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_PHYSMGMT, 0); 1704 1705 ex_mii_clrbit(sc, ELINK_PHY_DIR); 1706 for (i = 0; i < 32; i++) { 1707 ex_mii_clrbit(sc, ELINK_PHY_CLK); 1708 ex_mii_setbit(sc, ELINK_PHY_CLK); 1709 } 1710 ex_mii_writebits(sc, MII_COMMAND_START, 2); 1711 ex_mii_writebits(sc, MII_COMMAND_READ, 2); 1712 ex_mii_writebits(sc, phy, 5); 1713 ex_mii_writebits(sc, reg, 5); 1714 1715 ex_mii_clrbit(sc, ELINK_PHY_DIR); 1716 ex_mii_clrbit(sc, ELINK_PHY_CLK); 1717 ex_mii_setbit(sc, ELINK_PHY_CLK); 1718 ex_mii_clrbit(sc, ELINK_PHY_CLK); 1719 1720 err = ex_mii_readbit(sc, ELINK_PHY_DATA); 1721 ex_mii_setbit(sc, ELINK_PHY_CLK); 1722 1723 for (i = 0; i < 16; i++) { 1724 val <<= 1; 1725 ex_mii_clrbit(sc, ELINK_PHY_CLK); 1726 if (err == 0 && ex_mii_readbit(sc, ELINK_PHY_DATA)) 1727 val |= 1; 1728 ex_mii_setbit(sc, ELINK_PHY_CLK); 1729 } 1730 ex_mii_clrbit(sc, ELINK_PHY_CLK); 1731 ex_mii_setbit(sc, ELINK_PHY_CLK); 1732 1733 GO_WINDOW(1); 1734 1735 return (err ? 0 : val); 1736 } 1737 1738 static void 1739 ex_mii_writebits(sc, data, nbits) 1740 struct ex_softc *sc; 1741 unsigned int data; 1742 int nbits; 1743 { 1744 int i; 1745 1746 ex_mii_setbit(sc, ELINK_PHY_DIR); 1747 for (i = 1 << (nbits -1); i; i = i >> 1) { 1748 ex_mii_clrbit(sc, ELINK_PHY_CLK); 1749 ex_mii_readbit(sc, ELINK_PHY_CLK); 1750 if (data & i) 1751 ex_mii_setbit(sc, ELINK_PHY_DATA); 1752 else 1753 ex_mii_clrbit(sc, ELINK_PHY_DATA); 1754 ex_mii_setbit(sc, ELINK_PHY_CLK); 1755 ex_mii_readbit(sc, ELINK_PHY_CLK); 1756 } 1757 } 1758 1759 void 1760 ex_mii_writereg(v, phy, reg, data) 1761 struct device *v; 1762 int phy; 1763 int reg; 1764 int data; 1765 { 1766 struct ex_softc *sc = (struct ex_softc *)v; 1767 int i; 1768 1769 GO_WINDOW(4); 1770 1771 ex_mii_clrbit(sc, ELINK_PHY_DIR); 1772 for (i = 0; i < 32; i++) { 1773 ex_mii_clrbit(sc, ELINK_PHY_CLK); 1774 ex_mii_setbit(sc, ELINK_PHY_CLK); 1775 } 1776 ex_mii_writebits(sc, MII_COMMAND_START, 2); 1777 ex_mii_writebits(sc, MII_COMMAND_WRITE, 2); 1778 ex_mii_writebits(sc, phy, 5); 1779 ex_mii_writebits(sc, reg, 5); 1780 ex_mii_writebits(sc, MII_COMMAND_ACK, 2); 1781 ex_mii_writebits(sc, data, 16); 1782 1783 ex_mii_clrbit(sc, ELINK_PHY_CLK); 1784 ex_mii_setbit(sc, ELINK_PHY_CLK); 1785 1786 GO_WINDOW(1); 1787 } 1788 1789 void 1790 ex_mii_statchg(v) 1791 struct device *v; 1792 { 1793 struct ex_softc *sc = (struct ex_softc *)v; 1794 bus_space_tag_t iot = sc->sc_iot; 1795 bus_space_handle_t ioh = sc->sc_ioh; 1796 int mctl; 1797 1798 /* XXX Update ifp->if_baudrate */ 1799 1800 GO_WINDOW(3); 1801 mctl = bus_space_read_2(iot, ioh, ELINK_W3_MAC_CONTROL); 1802 if (sc->ex_mii.mii_media_active & IFM_FDX) 1803 mctl |= MAC_CONTROL_FDX; 1804 else 1805 mctl &= ~MAC_CONTROL_FDX; 1806 bus_space_write_2(iot, ioh, ELINK_W3_MAC_CONTROL, mctl); 1807 GO_WINDOW(1); /* back to operating window */ 1808 } 1809
Indexes created Wed Oct 22 13:09:56 GMT 2025