elinkxl.c revision 1.83
1 /* $NetBSD: elinkxl.c,v 1.83 2005/05/31 01:48:22 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: elinkxl.c,v 1.83 2005/05/31 01:48:22 christos Exp $"); 41 42 #include "bpfilter.h" 43 #include "rnd.h" 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/callout.h> 48 #include <sys/kernel.h> 49 #include <sys/mbuf.h> 50 #include <sys/socket.h> 51 #include <sys/ioctl.h> 52 #include <sys/errno.h> 53 #include <sys/syslog.h> 54 #include <sys/select.h> 55 #include <sys/device.h> 56 #if NRND > 0 57 #include <sys/rnd.h> 58 #endif 59 60 #include <uvm/uvm_extern.h> 61 62 #include <net/if.h> 63 #include <net/if_dl.h> 64 #include <net/if_ether.h> 65 #include <net/if_media.h> 66 67 #if NBPFILTER > 0 68 #include <net/bpf.h> 69 #include <net/bpfdesc.h> 70 #endif 71 72 #include <machine/cpu.h> 73 #include <machine/bus.h> 74 #include <machine/intr.h> 75 #include <machine/endian.h> 76 77 #include <dev/mii/miivar.h> 78 #include <dev/mii/mii.h> 79 #include <dev/mii/mii_bitbang.h> 80 81 #include <dev/ic/elink3reg.h> 82 /* #include <dev/ic/elink3var.h> */ 83 #include <dev/ic/elinkxlreg.h> 84 #include <dev/ic/elinkxlvar.h> 85 86 #ifdef DEBUG 87 int exdebug = 0; 88 #endif 89 90 /* ifmedia callbacks */ 91 int ex_media_chg(struct ifnet *ifp); 92 void ex_media_stat(struct ifnet *ifp, struct ifmediareq *req); 93 94 void ex_probe_media(struct ex_softc *); 95 void ex_set_filter(struct ex_softc *); 96 void ex_set_media(struct ex_softc *); 97 void ex_set_xcvr(struct ex_softc *, u_int16_t); 98 struct mbuf *ex_get(struct ex_softc *, int); 99 u_int16_t ex_read_eeprom(struct ex_softc *, int); 100 int ex_init(struct ifnet *); 101 void ex_read(struct ex_softc *); 102 void ex_reset(struct ex_softc *); 103 void ex_set_mc(struct ex_softc *); 104 void ex_getstats(struct ex_softc *); 105 void ex_printstats(struct ex_softc *); 106 void ex_tick(void *); 107 108 void ex_power(int, void *); 109 110 static int ex_eeprom_busy(struct ex_softc *); 111 static int ex_add_rxbuf(struct ex_softc *, struct ex_rxdesc *); 112 static void ex_init_txdescs(struct ex_softc *); 113 114 static void ex_shutdown(void *); 115 static void ex_start(struct ifnet *); 116 static void ex_txstat(struct ex_softc *); 117 118 int ex_mii_readreg(struct device *, int, int); 119 void ex_mii_writereg(struct device *, int, int, int); 120 void ex_mii_statchg(struct device *); 121 122 void ex_probemedia(struct ex_softc *); 123 124 /* 125 * Structure to map media-present bits in boards to ifmedia codes and 126 * printable media names. Used for table-driven ifmedia initialization. 127 */ 128 struct ex_media { 129 int exm_mpbit; /* media present bit */ 130 const char *exm_name; /* name of medium */ 131 int exm_ifmedia; /* ifmedia word for medium */ 132 int exm_epmedia; /* ELINKMEDIA_* constant */ 133 }; 134 135 /* 136 * Media table for 3c90x chips. Note that chips with MII have no 137 * `native' media. 138 */ 139 struct ex_media ex_native_media[] = { 140 { ELINK_PCI_10BASE_T, "10baseT", IFM_ETHER|IFM_10_T, 141 ELINKMEDIA_10BASE_T }, 142 { ELINK_PCI_10BASE_T, "10baseT-FDX", IFM_ETHER|IFM_10_T|IFM_FDX, 143 ELINKMEDIA_10BASE_T }, 144 { ELINK_PCI_AUI, "10base5", IFM_ETHER|IFM_10_5, 145 ELINKMEDIA_AUI }, 146 { ELINK_PCI_BNC, "10base2", IFM_ETHER|IFM_10_2, 147 ELINKMEDIA_10BASE_2 }, 148 { ELINK_PCI_100BASE_TX, "100baseTX", IFM_ETHER|IFM_100_TX, 149 ELINKMEDIA_100BASE_TX }, 150 { ELINK_PCI_100BASE_TX, "100baseTX-FDX",IFM_ETHER|IFM_100_TX|IFM_FDX, 151 ELINKMEDIA_100BASE_TX }, 152 { ELINK_PCI_100BASE_FX, "100baseFX", IFM_ETHER|IFM_100_FX, 153 ELINKMEDIA_100BASE_FX }, 154 { ELINK_PCI_100BASE_MII,"manual", IFM_ETHER|IFM_MANUAL, 155 ELINKMEDIA_MII }, 156 { ELINK_PCI_100BASE_T4, "100baseT4", IFM_ETHER|IFM_100_T4, 157 ELINKMEDIA_100BASE_T4 }, 158 { 0, NULL, 0, 159 0 }, 160 }; 161 162 /* 163 * MII bit-bang glue. 164 */ 165 u_int32_t ex_mii_bitbang_read(struct device *); 166 void ex_mii_bitbang_write(struct device *, u_int32_t); 167 168 const struct mii_bitbang_ops ex_mii_bitbang_ops = { 169 ex_mii_bitbang_read, 170 ex_mii_bitbang_write, 171 { 172 ELINK_PHY_DATA, /* MII_BIT_MDO */ 173 ELINK_PHY_DATA, /* MII_BIT_MDI */ 174 ELINK_PHY_CLK, /* MII_BIT_MDC */ 175 ELINK_PHY_DIR, /* MII_BIT_DIR_HOST_PHY */ 176 0, /* MII_BIT_DIR_PHY_HOST */ 177 } 178 }; 179 180 /* 181 * Back-end attach and configure. 182 */ 183 void 184 ex_config(sc) 185 struct ex_softc *sc; 186 { 187 struct ifnet *ifp; 188 u_int16_t val; 189 u_int8_t macaddr[ETHER_ADDR_LEN] = {0}; 190 bus_space_tag_t iot = sc->sc_iot; 191 bus_space_handle_t ioh = sc->sc_ioh; 192 int i, error, attach_stage; 193 194 callout_init(&sc->ex_mii_callout); 195 196 ex_reset(sc); 197 198 val = ex_read_eeprom(sc, EEPROM_OEM_ADDR0); 199 macaddr[0] = val >> 8; 200 macaddr[1] = val & 0xff; 201 val = ex_read_eeprom(sc, EEPROM_OEM_ADDR1); 202 macaddr[2] = val >> 8; 203 macaddr[3] = val & 0xff; 204 val = ex_read_eeprom(sc, EEPROM_OEM_ADDR2); 205 macaddr[4] = val >> 8; 206 macaddr[5] = val & 0xff; 207 208 aprint_normal("%s: MAC address %s\n", sc->sc_dev.dv_xname, 209 ether_sprintf(macaddr)); 210 211 if (sc->ex_conf & (EX_CONF_INV_LED_POLARITY|EX_CONF_PHY_POWER)) { 212 GO_WINDOW(2); 213 val = bus_space_read_2(iot, ioh, ELINK_W2_RESET_OPTIONS); 214 if (sc->ex_conf & EX_CONF_INV_LED_POLARITY) 215 val |= ELINK_RESET_OPT_LEDPOLAR; 216 if (sc->ex_conf & EX_CONF_PHY_POWER) 217 val |= ELINK_RESET_OPT_PHYPOWER; 218 bus_space_write_2(iot, ioh, ELINK_W2_RESET_OPTIONS, val); 219 } 220 if (sc->ex_conf & EX_CONF_NO_XCVR_PWR) { 221 GO_WINDOW(0); 222 bus_space_write_2(iot, ioh, ELINK_W0_MFG_ID, 223 EX_XCVR_PWR_MAGICBITS); 224 } 225 226 attach_stage = 0; 227 228 /* 229 * Allocate the upload descriptors, and create and load the DMA 230 * map for them. 231 */ 232 if ((error = bus_dmamem_alloc(sc->sc_dmat, 233 EX_NUPD * sizeof (struct ex_upd), PAGE_SIZE, 0, &sc->sc_useg, 1, 234 &sc->sc_urseg, BUS_DMA_NOWAIT)) != 0) { 235 aprint_error( 236 "%s: can't allocate upload descriptors, error = %d\n", 237 sc->sc_dev.dv_xname, error); 238 goto fail; 239 } 240 241 attach_stage = 1; 242 243 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_useg, sc->sc_urseg, 244 EX_NUPD * sizeof (struct ex_upd), (caddr_t *)&sc->sc_upd, 245 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 246 aprint_error("%s: can't map upload descriptors, error = %d\n", 247 sc->sc_dev.dv_xname, error); 248 goto fail; 249 } 250 251 attach_stage = 2; 252 253 if ((error = bus_dmamap_create(sc->sc_dmat, 254 EX_NUPD * sizeof (struct ex_upd), 1, 255 EX_NUPD * sizeof (struct ex_upd), 0, BUS_DMA_NOWAIT, 256 &sc->sc_upd_dmamap)) != 0) { 257 aprint_error( 258 "%s: can't create upload desc. DMA map, error = %d\n", 259 sc->sc_dev.dv_xname, error); 260 goto fail; 261 } 262 263 attach_stage = 3; 264 265 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_upd_dmamap, 266 sc->sc_upd, EX_NUPD * sizeof (struct ex_upd), NULL, 267 BUS_DMA_NOWAIT)) != 0) { 268 aprint_error( 269 "%s: can't load upload desc. DMA map, error = %d\n", 270 sc->sc_dev.dv_xname, error); 271 goto fail; 272 } 273 274 attach_stage = 4; 275 276 /* 277 * Allocate the download descriptors, and create and load the DMA 278 * map for them. 279 */ 280 if ((error = bus_dmamem_alloc(sc->sc_dmat, 281 EX_NDPD * sizeof (struct ex_dpd), PAGE_SIZE, 0, &sc->sc_dseg, 1, 282 &sc->sc_drseg, BUS_DMA_NOWAIT)) != 0) { 283 aprint_error( 284 "%s: can't allocate download descriptors, error = %d\n", 285 sc->sc_dev.dv_xname, error); 286 goto fail; 287 } 288 289 attach_stage = 5; 290 291 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dseg, sc->sc_drseg, 292 EX_NDPD * sizeof (struct ex_dpd), (caddr_t *)&sc->sc_dpd, 293 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 294 aprint_error("%s: can't map download descriptors, error = %d\n", 295 sc->sc_dev.dv_xname, error); 296 goto fail; 297 } 298 memset(sc->sc_dpd, 0, EX_NDPD * sizeof (struct ex_dpd)); 299 300 attach_stage = 6; 301 302 if ((error = bus_dmamap_create(sc->sc_dmat, 303 EX_NDPD * sizeof (struct ex_dpd), 1, 304 EX_NDPD * sizeof (struct ex_dpd), 0, BUS_DMA_NOWAIT, 305 &sc->sc_dpd_dmamap)) != 0) { 306 aprint_error( 307 "%s: can't create download desc. DMA map, error = %d\n", 308 sc->sc_dev.dv_xname, error); 309 goto fail; 310 } 311 312 attach_stage = 7; 313 314 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dpd_dmamap, 315 sc->sc_dpd, EX_NDPD * sizeof (struct ex_dpd), NULL, 316 BUS_DMA_NOWAIT)) != 0) { 317 aprint_error( 318 "%s: can't load download desc. DMA map, error = %d\n", 319 sc->sc_dev.dv_xname, error); 320 goto fail; 321 } 322 323 attach_stage = 8; 324 325 326 /* 327 * Create the transmit buffer DMA maps. 328 */ 329 for (i = 0; i < EX_NDPD; i++) { 330 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 331 EX_NTFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 332 &sc->sc_tx_dmamaps[i])) != 0) { 333 aprint_error( 334 "%s: can't create tx DMA map %d, error = %d\n", 335 sc->sc_dev.dv_xname, i, error); 336 goto fail; 337 } 338 } 339 340 attach_stage = 9; 341 342 /* 343 * Create the receive buffer DMA maps. 344 */ 345 for (i = 0; i < EX_NUPD; i++) { 346 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 347 EX_NRFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 348 &sc->sc_rx_dmamaps[i])) != 0) { 349 aprint_error( 350 "%s: can't create rx DMA map %d, error = %d\n", 351 sc->sc_dev.dv_xname, i, error); 352 goto fail; 353 } 354 } 355 356 attach_stage = 10; 357 358 /* 359 * Create ring of upload descriptors, only once. The DMA engine 360 * will loop over this when receiving packets, stalling if it 361 * hits an UPD with a finished receive. 362 */ 363 for (i = 0; i < EX_NUPD; i++) { 364 sc->sc_rxdescs[i].rx_dmamap = sc->sc_rx_dmamaps[i]; 365 sc->sc_rxdescs[i].rx_upd = &sc->sc_upd[i]; 366 sc->sc_upd[i].upd_frags[0].fr_len = 367 htole32((MCLBYTES - 2) | EX_FR_LAST); 368 if (ex_add_rxbuf(sc, &sc->sc_rxdescs[i]) != 0) { 369 aprint_error("%s: can't allocate or map rx buffers\n", 370 sc->sc_dev.dv_xname); 371 goto fail; 372 } 373 } 374 375 bus_dmamap_sync(sc->sc_dmat, sc->sc_upd_dmamap, 0, 376 EX_NUPD * sizeof (struct ex_upd), 377 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 378 379 ex_init_txdescs(sc); 380 381 attach_stage = 11; 382 383 384 GO_WINDOW(3); 385 val = bus_space_read_2(iot, ioh, ELINK_W3_RESET_OPTIONS); 386 if (val & ELINK_MEDIACAP_MII) 387 sc->ex_conf |= EX_CONF_MII; 388 389 ifp = &sc->sc_ethercom.ec_if; 390 391 /* 392 * Initialize our media structures and MII info. We'll 393 * probe the MII if we discover that we have one. 394 */ 395 sc->ex_mii.mii_ifp = ifp; 396 sc->ex_mii.mii_readreg = ex_mii_readreg; 397 sc->ex_mii.mii_writereg = ex_mii_writereg; 398 sc->ex_mii.mii_statchg = ex_mii_statchg; 399 ifmedia_init(&sc->ex_mii.mii_media, IFM_IMASK, ex_media_chg, 400 ex_media_stat); 401 402 if (sc->ex_conf & EX_CONF_MII) { 403 /* 404 * Find PHY, extract media information from it. 405 * First, select the right transceiver. 406 */ 407 ex_set_xcvr(sc, val); 408 409 mii_attach(&sc->sc_dev, &sc->ex_mii, 0xffffffff, 410 MII_PHY_ANY, MII_OFFSET_ANY, 0); 411 if (LIST_FIRST(&sc->ex_mii.mii_phys) == NULL) { 412 ifmedia_add(&sc->ex_mii.mii_media, IFM_ETHER|IFM_NONE, 413 0, NULL); 414 ifmedia_set(&sc->ex_mii.mii_media, IFM_ETHER|IFM_NONE); 415 } else { 416 ifmedia_set(&sc->ex_mii.mii_media, IFM_ETHER|IFM_AUTO); 417 } 418 } else 419 ex_probemedia(sc); 420 421 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 422 ifp->if_softc = sc; 423 ifp->if_start = ex_start; 424 ifp->if_ioctl = ex_ioctl; 425 ifp->if_watchdog = ex_watchdog; 426 ifp->if_init = ex_init; 427 ifp->if_stop = ex_stop; 428 ifp->if_flags = 429 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 430 sc->sc_if_flags = ifp->if_flags; 431 IFQ_SET_READY(&ifp->if_snd); 432 433 /* 434 * We can support 802.1Q VLAN-sized frames. 435 */ 436 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 437 438 /* 439 * The 3c90xB has hardware IPv4/TCPv4/UDPv4 checksum support. 440 */ 441 if (sc->ex_conf & EX_CONF_90XB) 442 sc->sc_ethercom.ec_if.if_capabilities |= 443 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 444 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 445 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 446 447 if_attach(ifp); 448 ether_ifattach(ifp, macaddr); 449 450 GO_WINDOW(1); 451 452 sc->tx_start_thresh = 20; 453 sc->tx_succ_ok = 0; 454 455 /* TODO: set queues to 0 */ 456 457 #if NRND > 0 458 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 459 RND_TYPE_NET, 0); 460 #endif 461 462 /* Establish callback to reset card when we reboot. */ 463 sc->sc_sdhook = shutdownhook_establish(ex_shutdown, sc); 464 if (sc->sc_sdhook == NULL) 465 aprint_error("%s: WARNING: unable to establish shutdown hook\n", 466 sc->sc_dev.dv_xname); 467 468 /* Add a suspend hook to make sure we come back up after a resume. */ 469 sc->sc_powerhook = powerhook_establish(ex_power, sc); 470 if (sc->sc_powerhook == NULL) 471 aprint_error("%s: WARNING: unable to establish power hook\n", 472 sc->sc_dev.dv_xname); 473 474 /* The attach is successful. */ 475 sc->ex_flags |= EX_FLAGS_ATTACHED; 476 return; 477 478 fail: 479 /* 480 * Free any resources we've allocated during the failed attach 481 * attempt. Do this in reverse order and fall though. 482 */ 483 switch (attach_stage) { 484 case 11: 485 { 486 struct ex_rxdesc *rxd; 487 488 for (i = 0; i < EX_NUPD; i++) { 489 rxd = &sc->sc_rxdescs[i]; 490 if (rxd->rx_mbhead != NULL) { 491 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 492 m_freem(rxd->rx_mbhead); 493 } 494 } 495 } 496 /* FALLTHROUGH */ 497 498 case 10: 499 for (i = 0; i < EX_NUPD; i++) 500 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rx_dmamaps[i]); 501 /* FALLTHROUGH */ 502 503 case 9: 504 for (i = 0; i < EX_NDPD; i++) 505 bus_dmamap_destroy(sc->sc_dmat, sc->sc_tx_dmamaps[i]); 506 /* FALLTHROUGH */ 507 case 8: 508 bus_dmamap_unload(sc->sc_dmat, sc->sc_dpd_dmamap); 509 /* FALLTHROUGH */ 510 511 case 7: 512 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dpd_dmamap); 513 /* FALLTHROUGH */ 514 515 case 6: 516 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_dpd, 517 EX_NDPD * sizeof (struct ex_dpd)); 518 /* FALLTHROUGH */ 519 520 case 5: 521 bus_dmamem_free(sc->sc_dmat, &sc->sc_dseg, sc->sc_drseg); 522 break; 523 524 case 4: 525 bus_dmamap_unload(sc->sc_dmat, sc->sc_upd_dmamap); 526 /* FALLTHROUGH */ 527 528 case 3: 529 bus_dmamap_destroy(sc->sc_dmat, sc->sc_upd_dmamap); 530 /* FALLTHROUGH */ 531 532 case 2: 533 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_upd, 534 EX_NUPD * sizeof (struct ex_upd)); 535 /* FALLTHROUGH */ 536 537 case 1: 538 bus_dmamem_free(sc->sc_dmat, &sc->sc_useg, sc->sc_urseg); 539 break; 540 } 541 542 } 543 544 /* 545 * Find the media present on non-MII chips. 546 */ 547 void 548 ex_probemedia(sc) 549 struct ex_softc *sc; 550 { 551 bus_space_tag_t iot = sc->sc_iot; 552 bus_space_handle_t ioh = sc->sc_ioh; 553 struct ifmedia *ifm = &sc->ex_mii.mii_media; 554 struct ex_media *exm; 555 u_int16_t config1, reset_options, default_media; 556 int defmedia = 0; 557 const char *sep = "", *defmedianame = NULL; 558 559 GO_WINDOW(3); 560 config1 = bus_space_read_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG + 2); 561 reset_options = bus_space_read_1(iot, ioh, ELINK_W3_RESET_OPTIONS); 562 GO_WINDOW(0); 563 564 default_media = (config1 & CONFIG_MEDIAMASK) >> CONFIG_MEDIAMASK_SHIFT; 565 566 aprint_normal("%s: ", sc->sc_dev.dv_xname); 567 568 /* Sanity check that there are any media! */ 569 if ((reset_options & ELINK_PCI_MEDIAMASK) == 0) { 570 aprint_error("no media present!\n"); 571 ifmedia_add(ifm, IFM_ETHER|IFM_NONE, 0, NULL); 572 ifmedia_set(ifm, IFM_ETHER|IFM_NONE); 573 return; 574 } 575 576 #define PRINT(str) aprint_normal("%s%s", sep, str); sep = ", " 577 578 for (exm = ex_native_media; exm->exm_name != NULL; exm++) { 579 if (reset_options & exm->exm_mpbit) { 580 /* 581 * Default media is a little complicated. We 582 * support full-duplex which uses the same 583 * reset options bit. 584 * 585 * XXX Check EEPROM for default to FDX? 586 */ 587 if (exm->exm_epmedia == default_media) { 588 if ((exm->exm_ifmedia & IFM_FDX) == 0) { 589 defmedia = exm->exm_ifmedia; 590 defmedianame = exm->exm_name; 591 } 592 } else if (defmedia == 0) { 593 defmedia = exm->exm_ifmedia; 594 defmedianame = exm->exm_name; 595 } 596 ifmedia_add(ifm, exm->exm_ifmedia, exm->exm_epmedia, 597 NULL); 598 PRINT(exm->exm_name); 599 } 600 } 601 602 #undef PRINT 603 604 #ifdef DIAGNOSTIC 605 if (defmedia == 0) 606 panic("ex_probemedia: impossible"); 607 #endif 608 609 aprint_normal(", default %s\n", defmedianame); 610 ifmedia_set(ifm, defmedia); 611 } 612 613 /* 614 * Bring device up. 615 */ 616 int 617 ex_init(ifp) 618 struct ifnet *ifp; 619 { 620 struct ex_softc *sc = ifp->if_softc; 621 bus_space_tag_t iot = sc->sc_iot; 622 bus_space_handle_t ioh = sc->sc_ioh; 623 int i; 624 int error = 0; 625 626 if ((error = ex_enable(sc)) != 0) 627 goto out; 628 629 ex_waitcmd(sc); 630 ex_stop(ifp, 0); 631 632 /* 633 * Set the station address and clear the station mask. The latter 634 * is needed for 90x cards, 0 is the default for 90xB cards. 635 */ 636 GO_WINDOW(2); 637 for (i = 0; i < ETHER_ADDR_LEN; i++) { 638 bus_space_write_1(iot, ioh, ELINK_W2_ADDR_0 + i, 639 LLADDR(ifp->if_sadl)[i]); 640 bus_space_write_1(iot, ioh, ELINK_W2_RECVMASK_0 + i, 0); 641 } 642 643 GO_WINDOW(3); 644 645 bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_RESET); 646 ex_waitcmd(sc); 647 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_RESET); 648 ex_waitcmd(sc); 649 650 /* 651 * Disable reclaim threshold for 90xB, set free threshold to 652 * 6 * 256 = 1536 for 90x. 653 */ 654 if (sc->ex_conf & EX_CONF_90XB) 655 bus_space_write_2(iot, ioh, ELINK_COMMAND, 656 ELINK_TXRECLTHRESH | 255); 657 else 658 bus_space_write_1(iot, ioh, ELINK_TXFREETHRESH, 6); 659 660 bus_space_write_2(iot, ioh, ELINK_COMMAND, 661 SET_RX_EARLY_THRESH | ELINK_THRESH_DISABLE); 662 663 bus_space_write_4(iot, ioh, ELINK_DMACTRL, 664 bus_space_read_4(iot, ioh, ELINK_DMACTRL) | ELINK_DMAC_UPRXEAREN); 665 666 bus_space_write_2(iot, ioh, ELINK_COMMAND, 667 SET_RD_0_MASK | XL_WATCHED_INTERRUPTS); 668 bus_space_write_2(iot, ioh, ELINK_COMMAND, 669 SET_INTR_MASK | XL_WATCHED_INTERRUPTS); 670 671 bus_space_write_2(iot, ioh, ELINK_COMMAND, ACK_INTR | 0xff); 672 if (sc->intr_ack) 673 (* sc->intr_ack)(sc); 674 ex_set_media(sc); 675 ex_set_mc(sc); 676 677 678 bus_space_write_2(iot, ioh, ELINK_COMMAND, STATS_ENABLE); 679 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_ENABLE); 680 bus_space_write_4(iot, ioh, ELINK_UPLISTPTR, sc->sc_upddma); 681 bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_ENABLE); 682 bus_space_write_2(iot, ioh, ELINK_COMMAND, ELINK_UPUNSTALL); 683 684 if (sc->ex_conf & (EX_CONF_PHY_POWER | EX_CONF_INV_LED_POLARITY)) { 685 u_int16_t cbcard_config; 686 687 GO_WINDOW(2); 688 cbcard_config = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 0x0c); 689 if (sc->ex_conf & EX_CONF_PHY_POWER) { 690 cbcard_config |= 0x4000; /* turn on PHY power */ 691 } 692 if (sc->ex_conf & EX_CONF_INV_LED_POLARITY) { 693 cbcard_config |= 0x0010; /* invert LED polarity */ 694 } 695 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 0x0c, cbcard_config); 696 697 GO_WINDOW(3); 698 } 699 700 ifp->if_flags |= IFF_RUNNING; 701 ifp->if_flags &= ~IFF_OACTIVE; 702 ex_start(ifp); 703 sc->sc_if_flags = ifp->if_flags; 704 705 GO_WINDOW(1); 706 707 callout_reset(&sc->ex_mii_callout, hz, ex_tick, sc); 708 709 out: 710 if (error) { 711 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 712 ifp->if_timer = 0; 713 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 714 } 715 return (error); 716 } 717 718 #define MCHASHSIZE 256 719 #define ex_mchash(addr) (ether_crc32_be((addr), ETHER_ADDR_LEN) & \ 720 (MCHASHSIZE - 1)) 721 722 /* 723 * Set multicast receive filter. Also take care of promiscuous mode 724 * here (XXX). 725 */ 726 void 727 ex_set_mc(sc) 728 struct ex_softc *sc; 729 { 730 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 731 struct ethercom *ec = &sc->sc_ethercom; 732 struct ether_multi *enm; 733 struct ether_multistep estep; 734 int i; 735 u_int16_t mask = FIL_INDIVIDUAL | FIL_BRDCST; 736 737 if (ifp->if_flags & IFF_PROMISC) { 738 mask |= FIL_PROMISC; 739 goto allmulti; 740 } 741 742 ETHER_FIRST_MULTI(estep, ec, enm); 743 if (enm == NULL) 744 goto nomulti; 745 746 if ((sc->ex_conf & EX_CONF_90XB) == 0) 747 /* No multicast hash filtering. */ 748 goto allmulti; 749 750 for (i = 0; i < MCHASHSIZE; i++) 751 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 752 ELINK_COMMAND, ELINK_CLEARHASHFILBIT | i); 753 754 do { 755 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 756 ETHER_ADDR_LEN) != 0) 757 goto allmulti; 758 759 i = ex_mchash(enm->enm_addrlo); 760 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 761 ELINK_COMMAND, ELINK_SETHASHFILBIT | i); 762 ETHER_NEXT_MULTI(estep, enm); 763 } while (enm != NULL); 764 mask |= FIL_MULTIHASH; 765 766 nomulti: 767 ifp->if_flags &= ~IFF_ALLMULTI; 768 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_COMMAND, 769 SET_RX_FILTER | mask); 770 return; 771 772 allmulti: 773 ifp->if_flags |= IFF_ALLMULTI; 774 mask |= FIL_MULTICAST; 775 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_COMMAND, 776 SET_RX_FILTER | mask); 777 } 778 779 780 static void 781 ex_txstat(sc) 782 struct ex_softc *sc; 783 { 784 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 785 bus_space_tag_t iot = sc->sc_iot; 786 bus_space_handle_t ioh = sc->sc_ioh; 787 int i; 788 789 /* 790 * We need to read+write TX_STATUS until we get a 0 status 791 * in order to turn off the interrupt flag. 792 */ 793 while ((i = bus_space_read_1(iot, ioh, ELINK_TXSTATUS)) & TXS_COMPLETE) { 794 bus_space_write_1(iot, ioh, ELINK_TXSTATUS, 0x0); 795 796 if (i & TXS_JABBER) { 797 ++sc->sc_ethercom.ec_if.if_oerrors; 798 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 799 printf("%s: jabber (%x)\n", 800 sc->sc_dev.dv_xname, i); 801 ex_init(ifp); 802 /* TODO: be more subtle here */ 803 } else if (i & TXS_UNDERRUN) { 804 ++sc->sc_ethercom.ec_if.if_oerrors; 805 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 806 printf("%s: fifo underrun (%x) @%d\n", 807 sc->sc_dev.dv_xname, i, 808 sc->tx_start_thresh); 809 if (sc->tx_succ_ok < 100) 810 sc->tx_start_thresh = min(ETHER_MAX_LEN, 811 sc->tx_start_thresh + 20); 812 sc->tx_succ_ok = 0; 813 ex_init(ifp); 814 /* TODO: be more subtle here */ 815 } else if (i & TXS_MAX_COLLISION) { 816 ++sc->sc_ethercom.ec_if.if_collisions; 817 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_ENABLE); 818 sc->sc_ethercom.ec_if.if_flags &= ~IFF_OACTIVE; 819 } else 820 sc->tx_succ_ok = (sc->tx_succ_ok+1) & 127; 821 } 822 } 823 824 int 825 ex_media_chg(ifp) 826 struct ifnet *ifp; 827 { 828 829 if (ifp->if_flags & IFF_UP) 830 ex_init(ifp); 831 return 0; 832 } 833 834 void 835 ex_set_xcvr(sc, media) 836 struct ex_softc *sc; 837 const u_int16_t media; 838 { 839 bus_space_tag_t iot = sc->sc_iot; 840 bus_space_handle_t ioh = sc->sc_ioh; 841 u_int32_t icfg; 842 843 /* 844 * We're already in Window 3 845 */ 846 icfg = bus_space_read_4(iot, ioh, ELINK_W3_INTERNAL_CONFIG); 847 icfg &= ~(CONFIG_XCVR_SEL << 16); 848 if (media & (ELINK_MEDIACAP_MII | ELINK_MEDIACAP_100BASET4)) 849 icfg |= ELINKMEDIA_MII << (CONFIG_XCVR_SEL_SHIFT + 16); 850 if (media & ELINK_MEDIACAP_100BASETX) 851 icfg |= ELINKMEDIA_AUTO << (CONFIG_XCVR_SEL_SHIFT + 16); 852 if (media & ELINK_MEDIACAP_100BASEFX) 853 icfg |= ELINKMEDIA_100BASE_FX 854 << (CONFIG_XCVR_SEL_SHIFT + 16); 855 bus_space_write_4(iot, ioh, ELINK_W3_INTERNAL_CONFIG, icfg); 856 } 857 858 void 859 ex_set_media(sc) 860 struct ex_softc *sc; 861 { 862 bus_space_tag_t iot = sc->sc_iot; 863 bus_space_handle_t ioh = sc->sc_ioh; 864 u_int32_t configreg; 865 866 if (((sc->ex_conf & EX_CONF_MII) && 867 (sc->ex_mii.mii_media_active & IFM_FDX)) 868 || (!(sc->ex_conf & EX_CONF_MII) && 869 (sc->ex_mii.mii_media.ifm_media & IFM_FDX))) { 870 bus_space_write_2(iot, ioh, ELINK_W3_MAC_CONTROL, 871 MAC_CONTROL_FDX); 872 } else { 873 bus_space_write_2(iot, ioh, ELINK_W3_MAC_CONTROL, 0); 874 } 875 876 /* 877 * If the device has MII, select it, and then tell the 878 * PHY which media to use. 879 */ 880 if (sc->ex_conf & EX_CONF_MII) { 881 u_int16_t val; 882 883 GO_WINDOW(3); 884 val = bus_space_read_2(iot, ioh, ELINK_W3_RESET_OPTIONS); 885 ex_set_xcvr(sc, val); 886 mii_mediachg(&sc->ex_mii); 887 return; 888 } 889 890 GO_WINDOW(4); 891 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 0); 892 bus_space_write_2(iot, ioh, ELINK_COMMAND, STOP_TRANSCEIVER); 893 delay(800); 894 895 /* 896 * Now turn on the selected media/transceiver. 897 */ 898 switch (IFM_SUBTYPE(sc->ex_mii.mii_media.ifm_cur->ifm_media)) { 899 case IFM_10_T: 900 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 901 JABBER_GUARD_ENABLE|LINKBEAT_ENABLE); 902 break; 903 904 case IFM_10_2: 905 bus_space_write_2(iot, ioh, ELINK_COMMAND, START_TRANSCEIVER); 906 DELAY(800); 907 break; 908 909 case IFM_100_TX: 910 case IFM_100_FX: 911 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 912 LINKBEAT_ENABLE); 913 DELAY(800); 914 break; 915 916 case IFM_10_5: 917 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 918 SQE_ENABLE); 919 DELAY(800); 920 break; 921 922 case IFM_MANUAL: 923 break; 924 925 case IFM_NONE: 926 return; 927 928 default: 929 panic("ex_set_media: impossible"); 930 } 931 932 GO_WINDOW(3); 933 configreg = bus_space_read_4(iot, ioh, ELINK_W3_INTERNAL_CONFIG); 934 935 configreg &= ~(CONFIG_MEDIAMASK << 16); 936 configreg |= (sc->ex_mii.mii_media.ifm_cur->ifm_data << 937 (CONFIG_MEDIAMASK_SHIFT + 16)); 938 939 bus_space_write_4(iot, ioh, ELINK_W3_INTERNAL_CONFIG, configreg); 940 } 941 942 /* 943 * Get currently-selected media from card. 944 * (if_media callback, may be called before interface is brought up). 945 */ 946 void 947 ex_media_stat(ifp, req) 948 struct ifnet *ifp; 949 struct ifmediareq *req; 950 { 951 struct ex_softc *sc = ifp->if_softc; 952 u_int16_t help; 953 954 if ((ifp->if_flags & (IFF_UP|IFF_RUNNING)) == (IFF_UP|IFF_RUNNING)) { 955 if (sc->ex_conf & EX_CONF_MII) { 956 mii_pollstat(&sc->ex_mii); 957 req->ifm_status = sc->ex_mii.mii_media_status; 958 req->ifm_active = sc->ex_mii.mii_media_active; 959 } else { 960 GO_WINDOW(4); 961 req->ifm_status = IFM_AVALID; 962 req->ifm_active = 963 sc->ex_mii.mii_media.ifm_cur->ifm_media; 964 help = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 965 ELINK_W4_MEDIA_TYPE); 966 if (help & LINKBEAT_DETECT) 967 req->ifm_status |= IFM_ACTIVE; 968 GO_WINDOW(1); 969 } 970 } 971 } 972 973 974 975 /* 976 * Start outputting on the interface. 977 */ 978 static void 979 ex_start(ifp) 980 struct ifnet *ifp; 981 { 982 struct ex_softc *sc = ifp->if_softc; 983 bus_space_tag_t iot = sc->sc_iot; 984 bus_space_handle_t ioh = sc->sc_ioh; 985 volatile struct ex_fraghdr *fr = NULL; 986 volatile struct ex_dpd *dpd = NULL, *prevdpd = NULL; 987 struct ex_txdesc *txp; 988 struct mbuf *mb_head; 989 bus_dmamap_t dmamap; 990 int offset, totlen, segment, error; 991 u_int32_t csum_flags; 992 993 if (sc->tx_head || sc->tx_free == NULL) 994 return; 995 996 txp = NULL; 997 998 /* 999 * We're finished if there is nothing more to add to the list or if 1000 * we're all filled up with buffers to transmit. 1001 */ 1002 while (sc->tx_free != NULL) { 1003 /* 1004 * Grab a packet to transmit. 1005 */ 1006 IFQ_DEQUEUE(&ifp->if_snd, mb_head); 1007 if (mb_head == NULL) 1008 break; 1009 1010 /* 1011 * Get pointer to next available tx desc. 1012 */ 1013 txp = sc->tx_free; 1014 dmamap = txp->tx_dmamap; 1015 1016 /* 1017 * Go through each of the mbufs in the chain and initialize 1018 * the transmit buffer descriptors with the physical address 1019 * and size of the mbuf. 1020 */ 1021 reload: 1022 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1023 mb_head, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1024 switch (error) { 1025 case 0: 1026 /* Success. */ 1027 break; 1028 1029 case EFBIG: 1030 { 1031 struct mbuf *mn; 1032 1033 /* 1034 * We ran out of segments. We have to recopy this 1035 * mbuf chain first. Bail out if we can't get the 1036 * new buffers. 1037 */ 1038 printf("%s: too many segments, ", sc->sc_dev.dv_xname); 1039 1040 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1041 if (mn == NULL) { 1042 m_freem(mb_head); 1043 printf("aborting\n"); 1044 goto out; 1045 } 1046 if (mb_head->m_pkthdr.len > MHLEN) { 1047 MCLGET(mn, M_DONTWAIT); 1048 if ((mn->m_flags & M_EXT) == 0) { 1049 m_freem(mn); 1050 m_freem(mb_head); 1051 printf("aborting\n"); 1052 goto out; 1053 } 1054 } 1055 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1056 mtod(mn, caddr_t)); 1057 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1058 m_freem(mb_head); 1059 mb_head = mn; 1060 printf("retrying\n"); 1061 goto reload; 1062 } 1063 1064 default: 1065 /* 1066 * Some other problem; report it. 1067 */ 1068 printf("%s: can't load mbuf chain, error = %d\n", 1069 sc->sc_dev.dv_xname, error); 1070 m_freem(mb_head); 1071 goto out; 1072 } 1073 1074 /* 1075 * remove our tx desc from freelist. 1076 */ 1077 sc->tx_free = txp->tx_next; 1078 txp->tx_next = NULL; 1079 1080 fr = &txp->tx_dpd->dpd_frags[0]; 1081 totlen = 0; 1082 for (segment = 0; segment < dmamap->dm_nsegs; segment++, fr++) { 1083 fr->fr_addr = htole32(dmamap->dm_segs[segment].ds_addr); 1084 fr->fr_len = htole32(dmamap->dm_segs[segment].ds_len); 1085 totlen += dmamap->dm_segs[segment].ds_len; 1086 } 1087 fr--; 1088 fr->fr_len |= htole32(EX_FR_LAST); 1089 txp->tx_mbhead = mb_head; 1090 1091 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1092 BUS_DMASYNC_PREWRITE); 1093 1094 dpd = txp->tx_dpd; 1095 dpd->dpd_nextptr = 0; 1096 dpd->dpd_fsh = htole32(totlen); 1097 1098 /* Byte-swap constants so compiler can optimize. */ 1099 1100 if (sc->ex_conf & EX_CONF_90XB) { 1101 csum_flags = 0; 1102 1103 if (mb_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 1104 csum_flags |= htole32(EX_DPD_IPCKSUM); 1105 1106 if (mb_head->m_pkthdr.csum_flags & M_CSUM_TCPv4) 1107 csum_flags |= htole32(EX_DPD_TCPCKSUM); 1108 else if (mb_head->m_pkthdr.csum_flags & M_CSUM_UDPv4) 1109 csum_flags |= htole32(EX_DPD_UDPCKSUM); 1110 1111 dpd->dpd_fsh |= csum_flags; 1112 } else { 1113 KDASSERT((mb_head->m_pkthdr.csum_flags & 1114 (M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4)) == 0); 1115 } 1116 1117 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap, 1118 ((const char *)(intptr_t)dpd - (const char *)sc->sc_dpd), 1119 sizeof (struct ex_dpd), 1120 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1121 1122 /* 1123 * No need to stall the download engine, we know it's 1124 * not busy right now. 1125 * 1126 * Fix up pointers in both the "soft" tx and the physical 1127 * tx list. 1128 */ 1129 if (sc->tx_head != NULL) { 1130 prevdpd = sc->tx_tail->tx_dpd; 1131 offset = ((const char *)(intptr_t)prevdpd - (const char *)sc->sc_dpd); 1132 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap, 1133 offset, sizeof (struct ex_dpd), 1134 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1135 prevdpd->dpd_nextptr = htole32(DPD_DMADDR(sc, txp)); 1136 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap, 1137 offset, sizeof (struct ex_dpd), 1138 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1139 sc->tx_tail->tx_next = txp; 1140 sc->tx_tail = txp; 1141 } else { 1142 sc->tx_tail = sc->tx_head = txp; 1143 } 1144 1145 #if NBPFILTER > 0 1146 /* 1147 * Pass packet to bpf if there is a listener. 1148 */ 1149 if (ifp->if_bpf) 1150 bpf_mtap(ifp->if_bpf, mb_head); 1151 #endif 1152 } 1153 out: 1154 if (sc->tx_head) { 1155 sc->tx_tail->tx_dpd->dpd_fsh |= htole32(EX_DPD_DNIND); 1156 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap, 1157 ((caddr_t)sc->tx_tail->tx_dpd - (caddr_t)sc->sc_dpd), 1158 sizeof (struct ex_dpd), 1159 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1160 ifp->if_flags |= IFF_OACTIVE; 1161 bus_space_write_2(iot, ioh, ELINK_COMMAND, ELINK_DNUNSTALL); 1162 bus_space_write_4(iot, ioh, ELINK_DNLISTPTR, 1163 DPD_DMADDR(sc, sc->tx_head)); 1164 1165 /* trigger watchdog */ 1166 ifp->if_timer = 5; 1167 } 1168 } 1169 1170 1171 int 1172 ex_intr(arg) 1173 void *arg; 1174 { 1175 struct ex_softc *sc = arg; 1176 bus_space_tag_t iot = sc->sc_iot; 1177 bus_space_handle_t ioh = sc->sc_ioh; 1178 u_int16_t stat; 1179 int ret = 0; 1180 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1181 1182 if ((ifp->if_flags & IFF_RUNNING) == 0 || 1183 (sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1184 return (0); 1185 1186 for (;;) { 1187 stat = bus_space_read_2(iot, ioh, ELINK_STATUS); 1188 1189 if ((stat & XL_WATCHED_INTERRUPTS) == 0) { 1190 if ((stat & INTR_LATCH) == 0) { 1191 #if 0 1192 printf("%s: intr latch cleared\n", 1193 sc->sc_dev.dv_xname); 1194 #endif 1195 break; 1196 } 1197 } 1198 1199 ret = 1; 1200 1201 /* 1202 * Acknowledge interrupts. 1203 */ 1204 bus_space_write_2(iot, ioh, ELINK_COMMAND, ACK_INTR | 1205 (stat & (XL_WATCHED_INTERRUPTS | INTR_LATCH))); 1206 if (sc->intr_ack) 1207 (*sc->intr_ack)(sc); 1208 1209 if (stat & HOST_ERROR) { 1210 printf("%s: adapter failure (%x)\n", 1211 sc->sc_dev.dv_xname, stat); 1212 ex_reset(sc); 1213 ex_init(ifp); 1214 return 1; 1215 } 1216 if (stat & TX_COMPLETE) { 1217 ex_txstat(sc); 1218 } 1219 if (stat & UPD_STATS) { 1220 ex_getstats(sc); 1221 } 1222 if (stat & DN_COMPLETE) { 1223 struct ex_txdesc *txp, *ptxp = NULL; 1224 bus_dmamap_t txmap; 1225 1226 /* reset watchdog timer, was set in ex_start() */ 1227 ifp->if_timer = 0; 1228 1229 for (txp = sc->tx_head; txp != NULL; 1230 txp = txp->tx_next) { 1231 bus_dmamap_sync(sc->sc_dmat, 1232 sc->sc_dpd_dmamap, 1233 (caddr_t)txp->tx_dpd - (caddr_t)sc->sc_dpd, 1234 sizeof (struct ex_dpd), 1235 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1236 if (txp->tx_mbhead != NULL) { 1237 txmap = txp->tx_dmamap; 1238 bus_dmamap_sync(sc->sc_dmat, txmap, 1239 0, txmap->dm_mapsize, 1240 BUS_DMASYNC_POSTWRITE); 1241 bus_dmamap_unload(sc->sc_dmat, txmap); 1242 m_freem(txp->tx_mbhead); 1243 txp->tx_mbhead = NULL; 1244 } 1245 ptxp = txp; 1246 } 1247 1248 /* 1249 * Move finished tx buffers back to the tx free list. 1250 */ 1251 if (sc->tx_free) { 1252 sc->tx_ftail->tx_next = sc->tx_head; 1253 sc->tx_ftail = ptxp; 1254 } else 1255 sc->tx_ftail = sc->tx_free = sc->tx_head; 1256 1257 sc->tx_head = sc->tx_tail = NULL; 1258 ifp->if_flags &= ~IFF_OACTIVE; 1259 } 1260 1261 if (stat & UP_COMPLETE) { 1262 struct ex_rxdesc *rxd; 1263 struct mbuf *m; 1264 struct ex_upd *upd; 1265 bus_dmamap_t rxmap; 1266 u_int32_t pktstat; 1267 1268 rcvloop: 1269 rxd = sc->rx_head; 1270 rxmap = rxd->rx_dmamap; 1271 m = rxd->rx_mbhead; 1272 upd = rxd->rx_upd; 1273 1274 bus_dmamap_sync(sc->sc_dmat, rxmap, 0, 1275 rxmap->dm_mapsize, 1276 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1277 bus_dmamap_sync(sc->sc_dmat, sc->sc_upd_dmamap, 1278 ((caddr_t)upd - (caddr_t)sc->sc_upd), 1279 sizeof (struct ex_upd), 1280 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1281 pktstat = le32toh(upd->upd_pktstatus); 1282 1283 if (pktstat & EX_UPD_COMPLETE) { 1284 /* 1285 * Remove first packet from the chain. 1286 */ 1287 sc->rx_head = rxd->rx_next; 1288 rxd->rx_next = NULL; 1289 1290 /* 1291 * Add a new buffer to the receive chain. 1292 * If this fails, the old buffer is recycled 1293 * instead. 1294 */ 1295 if (ex_add_rxbuf(sc, rxd) == 0) { 1296 u_int16_t total_len; 1297 1298 if (pktstat & 1299 ((sc->sc_ethercom.ec_capenable & 1300 ETHERCAP_VLAN_MTU) ? 1301 EX_UPD_ERR_VLAN : EX_UPD_ERR)) { 1302 ifp->if_ierrors++; 1303 m_freem(m); 1304 goto rcvloop; 1305 } 1306 1307 total_len = pktstat & EX_UPD_PKTLENMASK; 1308 if (total_len < 1309 sizeof(struct ether_header)) { 1310 m_freem(m); 1311 goto rcvloop; 1312 } 1313 m->m_pkthdr.rcvif = ifp; 1314 m->m_pkthdr.len = m->m_len = total_len; 1315 #if NBPFILTER > 0 1316 if (ifp->if_bpf) 1317 bpf_mtap(ifp->if_bpf, m); 1318 #endif 1319 /* 1320 * Set the incoming checksum information for the packet. 1321 */ 1322 if ((sc->ex_conf & EX_CONF_90XB) != 0 && 1323 (pktstat & EX_UPD_IPCHECKED) != 0) { 1324 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1325 if (pktstat & EX_UPD_IPCKSUMERR) 1326 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1327 if (pktstat & EX_UPD_TCPCHECKED) { 1328 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1329 if (pktstat & EX_UPD_TCPCKSUMERR) 1330 m->m_pkthdr.csum_flags |= 1331 M_CSUM_TCP_UDP_BAD; 1332 } else if (pktstat & EX_UPD_UDPCHECKED) { 1333 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1334 if (pktstat & EX_UPD_UDPCKSUMERR) 1335 m->m_pkthdr.csum_flags |= 1336 M_CSUM_TCP_UDP_BAD; 1337 } 1338 } 1339 (*ifp->if_input)(ifp, m); 1340 } 1341 goto rcvloop; 1342 } 1343 /* 1344 * Just in case we filled up all UPDs and the DMA engine 1345 * stalled. We could be more subtle about this. 1346 */ 1347 if (bus_space_read_4(iot, ioh, ELINK_UPLISTPTR) == 0) { 1348 printf("%s: uplistptr was 0\n", 1349 sc->sc_dev.dv_xname); 1350 ex_init(ifp); 1351 } else if (bus_space_read_4(iot, ioh, ELINK_UPPKTSTATUS) 1352 & 0x2000) { 1353 printf("%s: receive stalled\n", 1354 sc->sc_dev.dv_xname); 1355 bus_space_write_2(iot, ioh, ELINK_COMMAND, 1356 ELINK_UPUNSTALL); 1357 } 1358 } 1359 1360 #if NRND > 0 1361 if (stat) 1362 rnd_add_uint32(&sc->rnd_source, stat); 1363 #endif 1364 } 1365 1366 /* no more interrupts */ 1367 if (ret && IFQ_IS_EMPTY(&ifp->if_snd) == 0) 1368 ex_start(ifp); 1369 return ret; 1370 } 1371 1372 int 1373 ex_ioctl(ifp, cmd, data) 1374 struct ifnet *ifp; 1375 u_long cmd; 1376 caddr_t data; 1377 { 1378 struct ex_softc *sc = ifp->if_softc; 1379 struct ifreq *ifr = (struct ifreq *)data; 1380 int s, error; 1381 1382 s = splnet(); 1383 1384 switch (cmd) { 1385 case SIOCSIFMEDIA: 1386 case SIOCGIFMEDIA: 1387 error = ifmedia_ioctl(ifp, ifr, &sc->ex_mii.mii_media, cmd); 1388 break; 1389 case SIOCSIFFLAGS: 1390 /* If the interface is up and running, only modify the receive 1391 * filter when setting promiscuous or debug mode. Otherwise 1392 * fall through to ether_ioctl, which will reset the chip. 1393 */ 1394 #define RESETIGN (IFF_CANTCHANGE|IFF_DEBUG) 1395 if (((ifp->if_flags & (IFF_UP|IFF_RUNNING)) 1396 == (IFF_UP|IFF_RUNNING)) 1397 && ((ifp->if_flags & (~RESETIGN)) 1398 == (sc->sc_if_flags & (~RESETIGN)))) { 1399 ex_set_mc(sc); 1400 error = 0; 1401 break; 1402 #undef RESETIGN 1403 } 1404 /* FALLTHROUGH */ 1405 default: 1406 error = ether_ioctl(ifp, cmd, data); 1407 if (error == ENETRESET) { 1408 /* 1409 * Multicast list has changed; set the hardware filter 1410 * accordingly. 1411 */ 1412 if (ifp->if_flags & IFF_RUNNING) 1413 ex_set_mc(sc); 1414 error = 0; 1415 } 1416 break; 1417 } 1418 1419 sc->sc_if_flags = ifp->if_flags; 1420 splx(s); 1421 return (error); 1422 } 1423 1424 void 1425 ex_getstats(sc) 1426 struct ex_softc *sc; 1427 { 1428 bus_space_handle_t ioh = sc->sc_ioh; 1429 bus_space_tag_t iot = sc->sc_iot; 1430 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1431 u_int8_t upperok; 1432 1433 GO_WINDOW(6); 1434 upperok = bus_space_read_1(iot, ioh, UPPER_FRAMES_OK); 1435 ifp->if_ipackets += bus_space_read_1(iot, ioh, RX_FRAMES_OK); 1436 ifp->if_ipackets += (upperok & 0x03) << 8; 1437 ifp->if_opackets += bus_space_read_1(iot, ioh, TX_FRAMES_OK); 1438 ifp->if_opackets += (upperok & 0x30) << 4; 1439 ifp->if_ierrors += bus_space_read_1(iot, ioh, RX_OVERRUNS); 1440 ifp->if_collisions += bus_space_read_1(iot, ioh, TX_COLLISIONS); 1441 /* 1442 * There seems to be no way to get the exact number of collisions, 1443 * this is the number that occurred at the very least. 1444 */ 1445 ifp->if_collisions += 2 * bus_space_read_1(iot, ioh, 1446 TX_AFTER_X_COLLISIONS); 1447 /* 1448 * Interface byte counts are counted by ether_input() and 1449 * ether_output(), so don't accumulate them here. Just 1450 * read the NIC counters so they don't generate overflow interrupts. 1451 * Upper byte counters are latched from reading the totals, so 1452 * they don't need to be read if we don't need their values. 1453 */ 1454 bus_space_read_2(iot, ioh, RX_TOTAL_OK); 1455 bus_space_read_2(iot, ioh, TX_TOTAL_OK); 1456 1457 /* 1458 * Clear the following to avoid stats overflow interrupts 1459 */ 1460 bus_space_read_1(iot, ioh, TX_DEFERRALS); 1461 bus_space_read_1(iot, ioh, TX_AFTER_1_COLLISION); 1462 bus_space_read_1(iot, ioh, TX_NO_SQE); 1463 bus_space_read_1(iot, ioh, TX_CD_LOST); 1464 GO_WINDOW(4); 1465 bus_space_read_1(iot, ioh, ELINK_W4_BADSSD); 1466 GO_WINDOW(1); 1467 } 1468 1469 void 1470 ex_printstats(sc) 1471 struct ex_softc *sc; 1472 { 1473 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1474 1475 ex_getstats(sc); 1476 printf("in %llu out %llu ierror %llu oerror %llu ibytes %llu obytes " 1477 "%llu\n", (unsigned long long)ifp->if_ipackets, 1478 (unsigned long long)ifp->if_opackets, 1479 (unsigned long long)ifp->if_ierrors, 1480 (unsigned long long)ifp->if_oerrors, 1481 (unsigned long long)ifp->if_ibytes, 1482 (unsigned long long)ifp->if_obytes); 1483 } 1484 1485 void 1486 ex_tick(arg) 1487 void *arg; 1488 { 1489 struct ex_softc *sc = arg; 1490 int s; 1491 1492 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1493 return; 1494 1495 s = splnet(); 1496 1497 if (sc->ex_conf & EX_CONF_MII) 1498 mii_tick(&sc->ex_mii); 1499 1500 if (!(bus_space_read_2((sc)->sc_iot, (sc)->sc_ioh, ELINK_STATUS) 1501 & COMMAND_IN_PROGRESS)) 1502 ex_getstats(sc); 1503 1504 splx(s); 1505 1506 callout_reset(&sc->ex_mii_callout, hz, ex_tick, sc); 1507 } 1508 1509 void 1510 ex_reset(sc) 1511 struct ex_softc *sc; 1512 { 1513 u_int16_t val = GLOBAL_RESET; 1514 1515 if (sc->ex_conf & EX_CONF_RESETHACK) 1516 val |= 0x10; 1517 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_COMMAND, val); 1518 /* 1519 * XXX apparently the command in progress bit can't be trusted 1520 * during a reset, so we just always wait this long. Fortunately 1521 * we normally only reset the chip during autoconfig. 1522 */ 1523 delay(100000); 1524 ex_waitcmd(sc); 1525 } 1526 1527 void 1528 ex_watchdog(ifp) 1529 struct ifnet *ifp; 1530 { 1531 struct ex_softc *sc = ifp->if_softc; 1532 1533 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1534 ++sc->sc_ethercom.ec_if.if_oerrors; 1535 1536 ex_reset(sc); 1537 ex_init(ifp); 1538 } 1539 1540 void 1541 ex_stop(ifp, disable) 1542 struct ifnet *ifp; 1543 int disable; 1544 { 1545 struct ex_softc *sc = ifp->if_softc; 1546 bus_space_tag_t iot = sc->sc_iot; 1547 bus_space_handle_t ioh = sc->sc_ioh; 1548 struct ex_txdesc *tx; 1549 struct ex_rxdesc *rx; 1550 int i; 1551 1552 bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_DISABLE); 1553 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_DISABLE); 1554 bus_space_write_2(iot, ioh, ELINK_COMMAND, STOP_TRANSCEIVER); 1555 1556 for (tx = sc->tx_head ; tx != NULL; tx = tx->tx_next) { 1557 if (tx->tx_mbhead == NULL) 1558 continue; 1559 m_freem(tx->tx_mbhead); 1560 tx->tx_mbhead = NULL; 1561 bus_dmamap_unload(sc->sc_dmat, tx->tx_dmamap); 1562 tx->tx_dpd->dpd_fsh = tx->tx_dpd->dpd_nextptr = 0; 1563 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap, 1564 ((caddr_t)tx->tx_dpd - (caddr_t)sc->sc_dpd), 1565 sizeof (struct ex_dpd), 1566 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1567 } 1568 sc->tx_tail = sc->tx_head = NULL; 1569 ex_init_txdescs(sc); 1570 1571 sc->rx_tail = sc->rx_head = 0; 1572 for (i = 0; i < EX_NUPD; i++) { 1573 rx = &sc->sc_rxdescs[i]; 1574 if (rx->rx_mbhead != NULL) { 1575 bus_dmamap_unload(sc->sc_dmat, rx->rx_dmamap); 1576 m_freem(rx->rx_mbhead); 1577 rx->rx_mbhead = NULL; 1578 } 1579 ex_add_rxbuf(sc, rx); 1580 } 1581 1582 bus_space_write_2(iot, ioh, ELINK_COMMAND, ACK_INTR | INTR_LATCH); 1583 1584 callout_stop(&sc->ex_mii_callout); 1585 if (sc->ex_conf & EX_CONF_MII) 1586 mii_down(&sc->ex_mii); 1587 1588 if (disable) 1589 ex_disable(sc); 1590 1591 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1592 sc->sc_if_flags = ifp->if_flags; 1593 ifp->if_timer = 0; 1594 } 1595 1596 static void 1597 ex_init_txdescs(sc) 1598 struct ex_softc *sc; 1599 { 1600 int i; 1601 1602 for (i = 0; i < EX_NDPD; i++) { 1603 sc->sc_txdescs[i].tx_dmamap = sc->sc_tx_dmamaps[i]; 1604 sc->sc_txdescs[i].tx_dpd = &sc->sc_dpd[i]; 1605 if (i < EX_NDPD - 1) 1606 sc->sc_txdescs[i].tx_next = &sc->sc_txdescs[i + 1]; 1607 else 1608 sc->sc_txdescs[i].tx_next = NULL; 1609 } 1610 sc->tx_free = &sc->sc_txdescs[0]; 1611 sc->tx_ftail = &sc->sc_txdescs[EX_NDPD-1]; 1612 } 1613 1614 1615 int 1616 ex_activate(self, act) 1617 struct device *self; 1618 enum devact act; 1619 { 1620 struct ex_softc *sc = (void *) self; 1621 int s, error = 0; 1622 1623 s = splnet(); 1624 switch (act) { 1625 case DVACT_ACTIVATE: 1626 error = EOPNOTSUPP; 1627 break; 1628 1629 case DVACT_DEACTIVATE: 1630 if (sc->ex_conf & EX_CONF_MII) 1631 mii_activate(&sc->ex_mii, act, MII_PHY_ANY, 1632 MII_OFFSET_ANY); 1633 if_deactivate(&sc->sc_ethercom.ec_if); 1634 break; 1635 } 1636 splx(s); 1637 1638 return (error); 1639 } 1640 1641 int 1642 ex_detach(sc) 1643 struct ex_softc *sc; 1644 { 1645 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1646 struct ex_rxdesc *rxd; 1647 int i; 1648 1649 /* Succeed now if there's no work to do. */ 1650 if ((sc->ex_flags & EX_FLAGS_ATTACHED) == 0) 1651 return (0); 1652 1653 /* Unhook our tick handler. */ 1654 callout_stop(&sc->ex_mii_callout); 1655 1656 if (sc->ex_conf & EX_CONF_MII) { 1657 /* Detach all PHYs */ 1658 mii_detach(&sc->ex_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1659 } 1660 1661 /* Delete all remaining media. */ 1662 ifmedia_delete_instance(&sc->ex_mii.mii_media, IFM_INST_ANY); 1663 1664 #if NRND > 0 1665 rnd_detach_source(&sc->rnd_source); 1666 #endif 1667 ether_ifdetach(ifp); 1668 if_detach(ifp); 1669 1670 for (i = 0; i < EX_NUPD; i++) { 1671 rxd = &sc->sc_rxdescs[i]; 1672 if (rxd->rx_mbhead != NULL) { 1673 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 1674 m_freem(rxd->rx_mbhead); 1675 rxd->rx_mbhead = NULL; 1676 } 1677 } 1678 for (i = 0; i < EX_NUPD; i++) 1679 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rx_dmamaps[i]); 1680 for (i = 0; i < EX_NDPD; i++) 1681 bus_dmamap_destroy(sc->sc_dmat, sc->sc_tx_dmamaps[i]); 1682 bus_dmamap_unload(sc->sc_dmat, sc->sc_dpd_dmamap); 1683 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dpd_dmamap); 1684 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_dpd, 1685 EX_NDPD * sizeof (struct ex_dpd)); 1686 bus_dmamem_free(sc->sc_dmat, &sc->sc_dseg, sc->sc_drseg); 1687 bus_dmamap_unload(sc->sc_dmat, sc->sc_upd_dmamap); 1688 bus_dmamap_destroy(sc->sc_dmat, sc->sc_upd_dmamap); 1689 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_upd, 1690 EX_NUPD * sizeof (struct ex_upd)); 1691 bus_dmamem_free(sc->sc_dmat, &sc->sc_useg, sc->sc_urseg); 1692 1693 shutdownhook_disestablish(sc->sc_sdhook); 1694 powerhook_disestablish(sc->sc_powerhook); 1695 1696 return (0); 1697 } 1698 1699 /* 1700 * Before reboots, reset card completely. 1701 */ 1702 static void 1703 ex_shutdown(arg) 1704 void *arg; 1705 { 1706 struct ex_softc *sc = arg; 1707 1708 ex_stop(&sc->sc_ethercom.ec_if, 1); 1709 /* 1710 * Make sure the interface is powered up when we reboot, 1711 * otherwise firmware on some systems gets really confused. 1712 */ 1713 (void) ex_enable(sc); 1714 } 1715 1716 /* 1717 * Read EEPROM data. 1718 * XXX what to do if EEPROM doesn't unbusy? 1719 */ 1720 u_int16_t 1721 ex_read_eeprom(sc, offset) 1722 struct ex_softc *sc; 1723 int offset; 1724 { 1725 bus_space_tag_t iot = sc->sc_iot; 1726 bus_space_handle_t ioh = sc->sc_ioh; 1727 u_int16_t data = 0, cmd = READ_EEPROM; 1728 int off; 1729 1730 off = sc->ex_conf & EX_CONF_EEPROM_OFF ? 0x30 : 0; 1731 cmd = sc->ex_conf & EX_CONF_EEPROM_8BIT ? READ_EEPROM8 : READ_EEPROM; 1732 1733 GO_WINDOW(0); 1734 if (ex_eeprom_busy(sc)) 1735 goto out; 1736 bus_space_write_2(iot, ioh, ELINK_W0_EEPROM_COMMAND, 1737 cmd | (off + (offset & 0x3f))); 1738 if (ex_eeprom_busy(sc)) 1739 goto out; 1740 data = bus_space_read_2(iot, ioh, ELINK_W0_EEPROM_DATA); 1741 out: 1742 return data; 1743 } 1744 1745 static int 1746 ex_eeprom_busy(sc) 1747 struct ex_softc *sc; 1748 { 1749 bus_space_tag_t iot = sc->sc_iot; 1750 bus_space_handle_t ioh = sc->sc_ioh; 1751 int i = 100; 1752 1753 while (i--) { 1754 if (!(bus_space_read_2(iot, ioh, ELINK_W0_EEPROM_COMMAND) & 1755 EEPROM_BUSY)) 1756 return 0; 1757 delay(100); 1758 } 1759 printf("\n%s: eeprom stays busy.\n", sc->sc_dev.dv_xname); 1760 return (1); 1761 } 1762 1763 /* 1764 * Create a new rx buffer and add it to the 'soft' rx list. 1765 */ 1766 static int 1767 ex_add_rxbuf(sc, rxd) 1768 struct ex_softc *sc; 1769 struct ex_rxdesc *rxd; 1770 { 1771 struct mbuf *m, *oldm; 1772 bus_dmamap_t rxmap; 1773 int error, rval = 0; 1774 1775 oldm = rxd->rx_mbhead; 1776 rxmap = rxd->rx_dmamap; 1777 1778 MGETHDR(m, M_DONTWAIT, MT_DATA); 1779 if (m != NULL) { 1780 MCLGET(m, M_DONTWAIT); 1781 if ((m->m_flags & M_EXT) == 0) { 1782 m_freem(m); 1783 if (oldm == NULL) 1784 return 1; 1785 m = oldm; 1786 MRESETDATA(m); 1787 rval = 1; 1788 } 1789 } else { 1790 if (oldm == NULL) 1791 return 1; 1792 m = oldm; 1793 MRESETDATA(m); 1794 rval = 1; 1795 } 1796 1797 /* 1798 * Setup the DMA map for this receive buffer. 1799 */ 1800 if (m != oldm) { 1801 if (oldm != NULL) 1802 bus_dmamap_unload(sc->sc_dmat, rxmap); 1803 error = bus_dmamap_load(sc->sc_dmat, rxmap, 1804 m->m_ext.ext_buf, MCLBYTES, NULL, 1805 BUS_DMA_READ|BUS_DMA_NOWAIT); 1806 if (error) { 1807 printf("%s: can't load rx buffer, error = %d\n", 1808 sc->sc_dev.dv_xname, error); 1809 panic("ex_add_rxbuf"); /* XXX */ 1810 } 1811 } 1812 1813 /* 1814 * Align for data after 14 byte header. 1815 */ 1816 m->m_data += 2; 1817 1818 rxd->rx_mbhead = m; 1819 rxd->rx_upd->upd_pktstatus = htole32(MCLBYTES - 2); 1820 rxd->rx_upd->upd_frags[0].fr_addr = 1821 htole32(rxmap->dm_segs[0].ds_addr + 2); 1822 rxd->rx_upd->upd_nextptr = 0; 1823 1824 /* 1825 * Attach it to the end of the list. 1826 */ 1827 if (sc->rx_head != NULL) { 1828 sc->rx_tail->rx_next = rxd; 1829 sc->rx_tail->rx_upd->upd_nextptr = htole32(sc->sc_upddma + 1830 ((caddr_t)rxd->rx_upd - (caddr_t)sc->sc_upd)); 1831 bus_dmamap_sync(sc->sc_dmat, sc->sc_upd_dmamap, 1832 (caddr_t)sc->rx_tail->rx_upd - (caddr_t)sc->sc_upd, 1833 sizeof (struct ex_upd), 1834 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1835 } else { 1836 sc->rx_head = rxd; 1837 } 1838 sc->rx_tail = rxd; 1839 1840 bus_dmamap_sync(sc->sc_dmat, rxmap, 0, rxmap->dm_mapsize, 1841 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1842 bus_dmamap_sync(sc->sc_dmat, sc->sc_upd_dmamap, 1843 ((caddr_t)rxd->rx_upd - (caddr_t)sc->sc_upd), 1844 sizeof (struct ex_upd), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1845 return (rval); 1846 } 1847 1848 u_int32_t 1849 ex_mii_bitbang_read(self) 1850 struct device *self; 1851 { 1852 struct ex_softc *sc = (void *) self; 1853 1854 /* We're already in Window 4. */ 1855 return (bus_space_read_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_PHYSMGMT)); 1856 } 1857 1858 void 1859 ex_mii_bitbang_write(self, val) 1860 struct device *self; 1861 u_int32_t val; 1862 { 1863 struct ex_softc *sc = (void *) self; 1864 1865 /* We're already in Window 4. */ 1866 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_PHYSMGMT, val); 1867 } 1868 1869 int 1870 ex_mii_readreg(v, phy, reg) 1871 struct device *v; 1872 int phy, reg; 1873 { 1874 struct ex_softc *sc = (struct ex_softc *)v; 1875 int val; 1876 1877 if ((sc->ex_conf & EX_CONF_INTPHY) && phy != ELINK_INTPHY_ID) 1878 return 0; 1879 1880 GO_WINDOW(4); 1881 1882 val = mii_bitbang_readreg(v, &ex_mii_bitbang_ops, phy, reg); 1883 1884 GO_WINDOW(1); 1885 1886 return (val); 1887 } 1888 1889 void 1890 ex_mii_writereg(v, phy, reg, data) 1891 struct device *v; 1892 int phy; 1893 int reg; 1894 int data; 1895 { 1896 struct ex_softc *sc = (struct ex_softc *)v; 1897 1898 GO_WINDOW(4); 1899 1900 mii_bitbang_writereg(v, &ex_mii_bitbang_ops, phy, reg, data); 1901 1902 GO_WINDOW(1); 1903 } 1904 1905 void 1906 ex_mii_statchg(v) 1907 struct device *v; 1908 { 1909 struct ex_softc *sc = (struct ex_softc *)v; 1910 bus_space_tag_t iot = sc->sc_iot; 1911 bus_space_handle_t ioh = sc->sc_ioh; 1912 int mctl; 1913 1914 GO_WINDOW(3); 1915 mctl = bus_space_read_2(iot, ioh, ELINK_W3_MAC_CONTROL); 1916 if (sc->ex_mii.mii_media_active & IFM_FDX) 1917 mctl |= MAC_CONTROL_FDX; 1918 else 1919 mctl &= ~MAC_CONTROL_FDX; 1920 bus_space_write_2(iot, ioh, ELINK_W3_MAC_CONTROL, mctl); 1921 GO_WINDOW(1); /* back to operating window */ 1922 } 1923 1924 int 1925 ex_enable(sc) 1926 struct ex_softc *sc; 1927 { 1928 if (sc->enabled == 0 && sc->enable != NULL) { 1929 if ((*sc->enable)(sc) != 0) { 1930 printf("%s: de/vice enable failed\n", 1931 sc->sc_dev.dv_xname); 1932 return (EIO); 1933 } 1934 sc->enabled = 1; 1935 } 1936 return (0); 1937 } 1938 1939 void 1940 ex_disable(sc) 1941 struct ex_softc *sc; 1942 { 1943 if (sc->enabled == 1 && sc->disable != NULL) { 1944 (*sc->disable)(sc); 1945 sc->enabled = 0; 1946 } 1947 } 1948 1949 void 1950 ex_power(why, arg) 1951 int why; 1952 void *arg; 1953 { 1954 struct ex_softc *sc = (void *)arg; 1955 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1956 int s; 1957 1958 s = splnet(); 1959 switch (why) { 1960 case PWR_SUSPEND: 1961 case PWR_STANDBY: 1962 ex_stop(ifp, 0); 1963 if (sc->power != NULL) 1964 (*sc->power)(sc, why); 1965 break; 1966 case PWR_RESUME: 1967 if (ifp->if_flags & IFF_UP) { 1968 if (sc->power != NULL) 1969 (*sc->power)(sc, why); 1970 ex_init(ifp); 1971 } 1972 break; 1973 case PWR_SOFTSUSPEND: 1974 case PWR_SOFTSTANDBY: 1975 case PWR_SOFTRESUME: 1976 break; 1977 } 1978 splx(s); 1979 } 1980
Indexes created Tue Oct 21 12:09:54 GMT 2025