elinkxl.c revision 1.90
1 /* $NetBSD: elinkxl.c,v 1.90 2006/10/29 05:56:35 itohy Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Frank van der Linden. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: elinkxl.c,v 1.90 2006/10/29 05:56:35 itohy Exp $"); 41 42 #include "bpfilter.h" 43 #include "rnd.h" 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/callout.h> 48 #include <sys/kernel.h> 49 #include <sys/mbuf.h> 50 #include <sys/socket.h> 51 #include <sys/ioctl.h> 52 #include <sys/errno.h> 53 #include <sys/syslog.h> 54 #include <sys/select.h> 55 #include <sys/device.h> 56 #if NRND > 0 57 #include <sys/rnd.h> 58 #endif 59 60 #include <uvm/uvm_extern.h> 61 62 #include <net/if.h> 63 #include <net/if_dl.h> 64 #include <net/if_ether.h> 65 #include <net/if_media.h> 66 67 #if NBPFILTER > 0 68 #include <net/bpf.h> 69 #include <net/bpfdesc.h> 70 #endif 71 72 #include <machine/cpu.h> 73 #include <machine/bus.h> 74 #include <machine/intr.h> 75 #include <machine/endian.h> 76 77 #include <dev/mii/miivar.h> 78 #include <dev/mii/mii.h> 79 #include <dev/mii/mii_bitbang.h> 80 81 #include <dev/ic/elink3reg.h> 82 /* #include <dev/ic/elink3var.h> */ 83 #include <dev/ic/elinkxlreg.h> 84 #include <dev/ic/elinkxlvar.h> 85 86 #ifdef DEBUG 87 int exdebug = 0; 88 #endif 89 90 /* ifmedia callbacks */ 91 int ex_media_chg(struct ifnet *ifp); 92 void ex_media_stat(struct ifnet *ifp, struct ifmediareq *req); 93 94 void ex_probe_media(struct ex_softc *); 95 void ex_set_filter(struct ex_softc *); 96 void ex_set_media(struct ex_softc *); 97 void ex_set_xcvr(struct ex_softc *, u_int16_t); 98 struct mbuf *ex_get(struct ex_softc *, int); 99 u_int16_t ex_read_eeprom(struct ex_softc *, int); 100 int ex_init(struct ifnet *); 101 void ex_read(struct ex_softc *); 102 void ex_reset(struct ex_softc *); 103 void ex_set_mc(struct ex_softc *); 104 void ex_getstats(struct ex_softc *); 105 void ex_printstats(struct ex_softc *); 106 void ex_tick(void *); 107 108 void ex_power(int, void *); 109 110 static int ex_eeprom_busy(struct ex_softc *); 111 static int ex_add_rxbuf(struct ex_softc *, struct ex_rxdesc *); 112 static void ex_init_txdescs(struct ex_softc *); 113 114 static void ex_shutdown(void *); 115 static void ex_start(struct ifnet *); 116 static void ex_txstat(struct ex_softc *); 117 118 int ex_mii_readreg(struct device *, int, int); 119 void ex_mii_writereg(struct device *, int, int, int); 120 void ex_mii_statchg(struct device *); 121 122 void ex_probemedia(struct ex_softc *); 123 124 /* 125 * Structure to map media-present bits in boards to ifmedia codes and 126 * printable media names. Used for table-driven ifmedia initialization. 127 */ 128 struct ex_media { 129 int exm_mpbit; /* media present bit */ 130 const char *exm_name; /* name of medium */ 131 int exm_ifmedia; /* ifmedia word for medium */ 132 int exm_epmedia; /* ELINKMEDIA_* constant */ 133 }; 134 135 /* 136 * Media table for 3c90x chips. Note that chips with MII have no 137 * `native' media. 138 */ 139 struct ex_media ex_native_media[] = { 140 { ELINK_PCI_10BASE_T, "10baseT", IFM_ETHER|IFM_10_T, 141 ELINKMEDIA_10BASE_T }, 142 { ELINK_PCI_10BASE_T, "10baseT-FDX", IFM_ETHER|IFM_10_T|IFM_FDX, 143 ELINKMEDIA_10BASE_T }, 144 { ELINK_PCI_AUI, "10base5", IFM_ETHER|IFM_10_5, 145 ELINKMEDIA_AUI }, 146 { ELINK_PCI_BNC, "10base2", IFM_ETHER|IFM_10_2, 147 ELINKMEDIA_10BASE_2 }, 148 { ELINK_PCI_100BASE_TX, "100baseTX", IFM_ETHER|IFM_100_TX, 149 ELINKMEDIA_100BASE_TX }, 150 { ELINK_PCI_100BASE_TX, "100baseTX-FDX",IFM_ETHER|IFM_100_TX|IFM_FDX, 151 ELINKMEDIA_100BASE_TX }, 152 { ELINK_PCI_100BASE_FX, "100baseFX", IFM_ETHER|IFM_100_FX, 153 ELINKMEDIA_100BASE_FX }, 154 { ELINK_PCI_100BASE_MII,"manual", IFM_ETHER|IFM_MANUAL, 155 ELINKMEDIA_MII }, 156 { ELINK_PCI_100BASE_T4, "100baseT4", IFM_ETHER|IFM_100_T4, 157 ELINKMEDIA_100BASE_T4 }, 158 { 0, NULL, 0, 159 0 }, 160 }; 161 162 /* 163 * MII bit-bang glue. 164 */ 165 u_int32_t ex_mii_bitbang_read(struct device *); 166 void ex_mii_bitbang_write(struct device *, u_int32_t); 167 168 const struct mii_bitbang_ops ex_mii_bitbang_ops = { 169 ex_mii_bitbang_read, 170 ex_mii_bitbang_write, 171 { 172 ELINK_PHY_DATA, /* MII_BIT_MDO */ 173 ELINK_PHY_DATA, /* MII_BIT_MDI */ 174 ELINK_PHY_CLK, /* MII_BIT_MDC */ 175 ELINK_PHY_DIR, /* MII_BIT_DIR_HOST_PHY */ 176 0, /* MII_BIT_DIR_PHY_HOST */ 177 } 178 }; 179 180 /* 181 * Back-end attach and configure. 182 */ 183 void 184 ex_config(sc) 185 struct ex_softc *sc; 186 { 187 struct ifnet *ifp; 188 u_int16_t val; 189 u_int8_t macaddr[ETHER_ADDR_LEN] = {0}; 190 bus_space_tag_t iot = sc->sc_iot; 191 bus_space_handle_t ioh = sc->sc_ioh; 192 int i, error, attach_stage; 193 194 callout_init(&sc->ex_mii_callout); 195 196 ex_reset(sc); 197 198 val = ex_read_eeprom(sc, EEPROM_OEM_ADDR0); 199 macaddr[0] = val >> 8; 200 macaddr[1] = val & 0xff; 201 val = ex_read_eeprom(sc, EEPROM_OEM_ADDR1); 202 macaddr[2] = val >> 8; 203 macaddr[3] = val & 0xff; 204 val = ex_read_eeprom(sc, EEPROM_OEM_ADDR2); 205 macaddr[4] = val >> 8; 206 macaddr[5] = val & 0xff; 207 208 aprint_normal("%s: MAC address %s\n", sc->sc_dev.dv_xname, 209 ether_sprintf(macaddr)); 210 211 if (sc->ex_conf & (EX_CONF_INV_LED_POLARITY|EX_CONF_PHY_POWER)) { 212 GO_WINDOW(2); 213 val = bus_space_read_2(iot, ioh, ELINK_W2_RESET_OPTIONS); 214 if (sc->ex_conf & EX_CONF_INV_LED_POLARITY) 215 val |= ELINK_RESET_OPT_LEDPOLAR; 216 if (sc->ex_conf & EX_CONF_PHY_POWER) 217 val |= ELINK_RESET_OPT_PHYPOWER; 218 bus_space_write_2(iot, ioh, ELINK_W2_RESET_OPTIONS, val); 219 } 220 if (sc->ex_conf & EX_CONF_NO_XCVR_PWR) { 221 GO_WINDOW(0); 222 bus_space_write_2(iot, ioh, ELINK_W0_MFG_ID, 223 EX_XCVR_PWR_MAGICBITS); 224 } 225 226 attach_stage = 0; 227 228 /* 229 * Allocate the upload descriptors, and create and load the DMA 230 * map for them. 231 */ 232 if ((error = bus_dmamem_alloc(sc->sc_dmat, 233 EX_NUPD * sizeof (struct ex_upd), PAGE_SIZE, 0, &sc->sc_useg, 1, 234 &sc->sc_urseg, BUS_DMA_NOWAIT)) != 0) { 235 aprint_error( 236 "%s: can't allocate upload descriptors, error = %d\n", 237 sc->sc_dev.dv_xname, error); 238 goto fail; 239 } 240 241 attach_stage = 1; 242 243 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_useg, sc->sc_urseg, 244 EX_NUPD * sizeof (struct ex_upd), (caddr_t *)&sc->sc_upd, 245 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 246 aprint_error("%s: can't map upload descriptors, error = %d\n", 247 sc->sc_dev.dv_xname, error); 248 goto fail; 249 } 250 251 attach_stage = 2; 252 253 if ((error = bus_dmamap_create(sc->sc_dmat, 254 EX_NUPD * sizeof (struct ex_upd), 1, 255 EX_NUPD * sizeof (struct ex_upd), 0, BUS_DMA_NOWAIT, 256 &sc->sc_upd_dmamap)) != 0) { 257 aprint_error( 258 "%s: can't create upload desc. DMA map, error = %d\n", 259 sc->sc_dev.dv_xname, error); 260 goto fail; 261 } 262 263 attach_stage = 3; 264 265 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_upd_dmamap, 266 sc->sc_upd, EX_NUPD * sizeof (struct ex_upd), NULL, 267 BUS_DMA_NOWAIT)) != 0) { 268 aprint_error( 269 "%s: can't load upload desc. DMA map, error = %d\n", 270 sc->sc_dev.dv_xname, error); 271 goto fail; 272 } 273 274 attach_stage = 4; 275 276 /* 277 * Allocate the download descriptors, and create and load the DMA 278 * map for them. 279 */ 280 if ((error = bus_dmamem_alloc(sc->sc_dmat, 281 EX_NDPD * sizeof (struct ex_dpd), PAGE_SIZE, 0, &sc->sc_dseg, 1, 282 &sc->sc_drseg, BUS_DMA_NOWAIT)) != 0) { 283 aprint_error( 284 "%s: can't allocate download descriptors, error = %d\n", 285 sc->sc_dev.dv_xname, error); 286 goto fail; 287 } 288 289 attach_stage = 5; 290 291 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dseg, sc->sc_drseg, 292 EX_NDPD * sizeof (struct ex_dpd), (caddr_t *)&sc->sc_dpd, 293 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 294 aprint_error("%s: can't map download descriptors, error = %d\n", 295 sc->sc_dev.dv_xname, error); 296 goto fail; 297 } 298 memset(sc->sc_dpd, 0, EX_NDPD * sizeof (struct ex_dpd)); 299 300 attach_stage = 6; 301 302 if ((error = bus_dmamap_create(sc->sc_dmat, 303 EX_NDPD * sizeof (struct ex_dpd), 1, 304 EX_NDPD * sizeof (struct ex_dpd), 0, BUS_DMA_NOWAIT, 305 &sc->sc_dpd_dmamap)) != 0) { 306 aprint_error( 307 "%s: can't create download desc. DMA map, error = %d\n", 308 sc->sc_dev.dv_xname, error); 309 goto fail; 310 } 311 312 attach_stage = 7; 313 314 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dpd_dmamap, 315 sc->sc_dpd, EX_NDPD * sizeof (struct ex_dpd), NULL, 316 BUS_DMA_NOWAIT)) != 0) { 317 aprint_error( 318 "%s: can't load download desc. DMA map, error = %d\n", 319 sc->sc_dev.dv_xname, error); 320 goto fail; 321 } 322 323 attach_stage = 8; 324 325 326 /* 327 * Create the transmit buffer DMA maps. 328 */ 329 for (i = 0; i < EX_NDPD; i++) { 330 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 331 EX_NTFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 332 &sc->sc_tx_dmamaps[i])) != 0) { 333 aprint_error( 334 "%s: can't create tx DMA map %d, error = %d\n", 335 sc->sc_dev.dv_xname, i, error); 336 goto fail; 337 } 338 } 339 340 attach_stage = 9; 341 342 /* 343 * Create the receive buffer DMA maps. 344 */ 345 for (i = 0; i < EX_NUPD; i++) { 346 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 347 EX_NRFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 348 &sc->sc_rx_dmamaps[i])) != 0) { 349 aprint_error( 350 "%s: can't create rx DMA map %d, error = %d\n", 351 sc->sc_dev.dv_xname, i, error); 352 goto fail; 353 } 354 } 355 356 attach_stage = 10; 357 358 /* 359 * Create ring of upload descriptors, only once. The DMA engine 360 * will loop over this when receiving packets, stalling if it 361 * hits an UPD with a finished receive. 362 */ 363 for (i = 0; i < EX_NUPD; i++) { 364 sc->sc_rxdescs[i].rx_dmamap = sc->sc_rx_dmamaps[i]; 365 sc->sc_rxdescs[i].rx_upd = &sc->sc_upd[i]; 366 sc->sc_upd[i].upd_frags[0].fr_len = 367 htole32((MCLBYTES - 2) | EX_FR_LAST); 368 if (ex_add_rxbuf(sc, &sc->sc_rxdescs[i]) != 0) { 369 aprint_error("%s: can't allocate or map rx buffers\n", 370 sc->sc_dev.dv_xname); 371 goto fail; 372 } 373 } 374 375 bus_dmamap_sync(sc->sc_dmat, sc->sc_upd_dmamap, 0, 376 EX_NUPD * sizeof (struct ex_upd), 377 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 378 379 ex_init_txdescs(sc); 380 381 attach_stage = 11; 382 383 384 GO_WINDOW(3); 385 val = bus_space_read_2(iot, ioh, ELINK_W3_RESET_OPTIONS); 386 if (val & ELINK_MEDIACAP_MII) 387 sc->ex_conf |= EX_CONF_MII; 388 389 ifp = &sc->sc_ethercom.ec_if; 390 391 /* 392 * Initialize our media structures and MII info. We'll 393 * probe the MII if we discover that we have one. 394 */ 395 sc->ex_mii.mii_ifp = ifp; 396 sc->ex_mii.mii_readreg = ex_mii_readreg; 397 sc->ex_mii.mii_writereg = ex_mii_writereg; 398 sc->ex_mii.mii_statchg = ex_mii_statchg; 399 ifmedia_init(&sc->ex_mii.mii_media, IFM_IMASK, ex_media_chg, 400 ex_media_stat); 401 402 if (sc->ex_conf & EX_CONF_MII) { 403 /* 404 * Find PHY, extract media information from it. 405 * First, select the right transceiver. 406 */ 407 ex_set_xcvr(sc, val); 408 409 mii_attach(&sc->sc_dev, &sc->ex_mii, 0xffffffff, 410 MII_PHY_ANY, MII_OFFSET_ANY, 0); 411 if (LIST_FIRST(&sc->ex_mii.mii_phys) == NULL) { 412 ifmedia_add(&sc->ex_mii.mii_media, IFM_ETHER|IFM_NONE, 413 0, NULL); 414 ifmedia_set(&sc->ex_mii.mii_media, IFM_ETHER|IFM_NONE); 415 } else { 416 ifmedia_set(&sc->ex_mii.mii_media, IFM_ETHER|IFM_AUTO); 417 } 418 } else 419 ex_probemedia(sc); 420 421 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 422 ifp->if_softc = sc; 423 ifp->if_start = ex_start; 424 ifp->if_ioctl = ex_ioctl; 425 ifp->if_watchdog = ex_watchdog; 426 ifp->if_init = ex_init; 427 ifp->if_stop = ex_stop; 428 ifp->if_flags = 429 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 430 sc->sc_if_flags = ifp->if_flags; 431 IFQ_SET_READY(&ifp->if_snd); 432 433 /* 434 * We can support 802.1Q VLAN-sized frames. 435 */ 436 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 437 438 /* 439 * The 3c90xB has hardware IPv4/TCPv4/UDPv4 checksum support. 440 */ 441 if (sc->ex_conf & EX_CONF_90XB) 442 sc->sc_ethercom.ec_if.if_capabilities |= 443 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 444 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 445 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 446 447 if_attach(ifp); 448 ether_ifattach(ifp, macaddr); 449 450 GO_WINDOW(1); 451 452 sc->tx_start_thresh = 20; 453 sc->tx_succ_ok = 0; 454 455 /* TODO: set queues to 0 */ 456 457 #if NRND > 0 458 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 459 RND_TYPE_NET, 0); 460 #endif 461 462 /* Establish callback to reset card when we reboot. */ 463 sc->sc_sdhook = shutdownhook_establish(ex_shutdown, sc); 464 if (sc->sc_sdhook == NULL) 465 aprint_error("%s: WARNING: unable to establish shutdown hook\n", 466 sc->sc_dev.dv_xname); 467 468 /* Add a suspend hook to make sure we come back up after a resume. */ 469 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 470 ex_power, sc); 471 if (sc->sc_powerhook == NULL) 472 aprint_error("%s: WARNING: unable to establish power hook\n", 473 sc->sc_dev.dv_xname); 474 475 /* The attach is successful. */ 476 sc->ex_flags |= EX_FLAGS_ATTACHED; 477 return; 478 479 fail: 480 /* 481 * Free any resources we've allocated during the failed attach 482 * attempt. Do this in reverse order and fall though. 483 */ 484 switch (attach_stage) { 485 case 11: 486 { 487 struct ex_rxdesc *rxd; 488 489 for (i = 0; i < EX_NUPD; i++) { 490 rxd = &sc->sc_rxdescs[i]; 491 if (rxd->rx_mbhead != NULL) { 492 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 493 m_freem(rxd->rx_mbhead); 494 } 495 } 496 } 497 /* FALLTHROUGH */ 498 499 case 10: 500 for (i = 0; i < EX_NUPD; i++) 501 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rx_dmamaps[i]); 502 /* FALLTHROUGH */ 503 504 case 9: 505 for (i = 0; i < EX_NDPD; i++) 506 bus_dmamap_destroy(sc->sc_dmat, sc->sc_tx_dmamaps[i]); 507 /* FALLTHROUGH */ 508 case 8: 509 bus_dmamap_unload(sc->sc_dmat, sc->sc_dpd_dmamap); 510 /* FALLTHROUGH */ 511 512 case 7: 513 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dpd_dmamap); 514 /* FALLTHROUGH */ 515 516 case 6: 517 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_dpd, 518 EX_NDPD * sizeof (struct ex_dpd)); 519 /* FALLTHROUGH */ 520 521 case 5: 522 bus_dmamem_free(sc->sc_dmat, &sc->sc_dseg, sc->sc_drseg); 523 break; 524 525 case 4: 526 bus_dmamap_unload(sc->sc_dmat, sc->sc_upd_dmamap); 527 /* FALLTHROUGH */ 528 529 case 3: 530 bus_dmamap_destroy(sc->sc_dmat, sc->sc_upd_dmamap); 531 /* FALLTHROUGH */ 532 533 case 2: 534 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_upd, 535 EX_NUPD * sizeof (struct ex_upd)); 536 /* FALLTHROUGH */ 537 538 case 1: 539 bus_dmamem_free(sc->sc_dmat, &sc->sc_useg, sc->sc_urseg); 540 break; 541 } 542 543 } 544 545 /* 546 * Find the media present on non-MII chips. 547 */ 548 void 549 ex_probemedia(sc) 550 struct ex_softc *sc; 551 { 552 bus_space_tag_t iot = sc->sc_iot; 553 bus_space_handle_t ioh = sc->sc_ioh; 554 struct ifmedia *ifm = &sc->ex_mii.mii_media; 555 struct ex_media *exm; 556 u_int16_t config1, reset_options, default_media; 557 int defmedia = 0; 558 const char *sep = "", *defmedianame = NULL; 559 560 GO_WINDOW(3); 561 config1 = bus_space_read_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG + 2); 562 reset_options = bus_space_read_1(iot, ioh, ELINK_W3_RESET_OPTIONS); 563 GO_WINDOW(0); 564 565 default_media = (config1 & CONFIG_MEDIAMASK) >> CONFIG_MEDIAMASK_SHIFT; 566 567 aprint_normal("%s: ", sc->sc_dev.dv_xname); 568 569 /* Sanity check that there are any media! */ 570 if ((reset_options & ELINK_PCI_MEDIAMASK) == 0) { 571 aprint_error("no media present!\n"); 572 ifmedia_add(ifm, IFM_ETHER|IFM_NONE, 0, NULL); 573 ifmedia_set(ifm, IFM_ETHER|IFM_NONE); 574 return; 575 } 576 577 #define PRINT(str) aprint_normal("%s%s", sep, str); sep = ", " 578 579 for (exm = ex_native_media; exm->exm_name != NULL; exm++) { 580 if (reset_options & exm->exm_mpbit) { 581 /* 582 * Default media is a little complicated. We 583 * support full-duplex which uses the same 584 * reset options bit. 585 * 586 * XXX Check EEPROM for default to FDX? 587 */ 588 if (exm->exm_epmedia == default_media) { 589 if ((exm->exm_ifmedia & IFM_FDX) == 0) { 590 defmedia = exm->exm_ifmedia; 591 defmedianame = exm->exm_name; 592 } 593 } else if (defmedia == 0) { 594 defmedia = exm->exm_ifmedia; 595 defmedianame = exm->exm_name; 596 } 597 ifmedia_add(ifm, exm->exm_ifmedia, exm->exm_epmedia, 598 NULL); 599 PRINT(exm->exm_name); 600 } 601 } 602 603 #undef PRINT 604 605 #ifdef DIAGNOSTIC 606 if (defmedia == 0) 607 panic("ex_probemedia: impossible"); 608 #endif 609 610 aprint_normal(", default %s\n", defmedianame); 611 ifmedia_set(ifm, defmedia); 612 } 613 614 /* 615 * Bring device up. 616 */ 617 int 618 ex_init(ifp) 619 struct ifnet *ifp; 620 { 621 struct ex_softc *sc = ifp->if_softc; 622 bus_space_tag_t iot = sc->sc_iot; 623 bus_space_handle_t ioh = sc->sc_ioh; 624 int i; 625 u_int16_t val; 626 int error = 0; 627 628 if ((error = ex_enable(sc)) != 0) 629 goto out; 630 631 ex_waitcmd(sc); 632 ex_stop(ifp, 0); 633 634 GO_WINDOW(2); 635 636 /* Turn on PHY power. */ 637 if (sc->ex_conf & (EX_CONF_PHY_POWER | EX_CONF_INV_LED_POLARITY)) { 638 val = bus_space_read_2(iot, ioh, ELINK_W2_RESET_OPTIONS); 639 if (sc->ex_conf & EX_CONF_PHY_POWER) 640 val |= ELINK_RESET_OPT_PHYPOWER; /* turn on PHY power */ 641 if (sc->ex_conf & EX_CONF_INV_LED_POLARITY) 642 val |= ELINK_RESET_OPT_LEDPOLAR; /* invert LED polarity */ 643 bus_space_write_2(iot, ioh, ELINK_W2_RESET_OPTIONS, val); 644 } 645 646 /* 647 * Set the station address and clear the station mask. The latter 648 * is needed for 90x cards, 0 is the default for 90xB cards. 649 */ 650 for (i = 0; i < ETHER_ADDR_LEN; i++) { 651 bus_space_write_1(iot, ioh, ELINK_W2_ADDR_0 + i, 652 LLADDR(ifp->if_sadl)[i]); 653 bus_space_write_1(iot, ioh, ELINK_W2_RECVMASK_0 + i, 0); 654 } 655 656 GO_WINDOW(3); 657 658 bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_RESET); 659 ex_waitcmd(sc); 660 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_RESET); 661 ex_waitcmd(sc); 662 663 /* 664 * Disable reclaim threshold for 90xB, set free threshold to 665 * 6 * 256 = 1536 for 90x. 666 */ 667 if (sc->ex_conf & EX_CONF_90XB) 668 bus_space_write_2(iot, ioh, ELINK_COMMAND, 669 ELINK_TXRECLTHRESH | 255); 670 else 671 bus_space_write_1(iot, ioh, ELINK_TXFREETHRESH, 6); 672 673 bus_space_write_2(iot, ioh, ELINK_COMMAND, 674 SET_RX_EARLY_THRESH | ELINK_THRESH_DISABLE); 675 676 bus_space_write_4(iot, ioh, ELINK_DMACTRL, 677 bus_space_read_4(iot, ioh, ELINK_DMACTRL) | ELINK_DMAC_UPRXEAREN); 678 679 bus_space_write_2(iot, ioh, ELINK_COMMAND, 680 SET_RD_0_MASK | XL_WATCHED_INTERRUPTS); 681 bus_space_write_2(iot, ioh, ELINK_COMMAND, 682 SET_INTR_MASK | XL_WATCHED_INTERRUPTS); 683 684 bus_space_write_2(iot, ioh, ELINK_COMMAND, ACK_INTR | 0xff); 685 if (sc->intr_ack) 686 (* sc->intr_ack)(sc); 687 ex_set_media(sc); 688 ex_set_mc(sc); 689 690 691 bus_space_write_2(iot, ioh, ELINK_COMMAND, STATS_ENABLE); 692 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_ENABLE); 693 bus_space_write_4(iot, ioh, ELINK_UPLISTPTR, sc->sc_upddma); 694 bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_ENABLE); 695 bus_space_write_2(iot, ioh, ELINK_COMMAND, ELINK_UPUNSTALL); 696 697 ifp->if_flags |= IFF_RUNNING; 698 ifp->if_flags &= ~IFF_OACTIVE; 699 ex_start(ifp); 700 sc->sc_if_flags = ifp->if_flags; 701 702 GO_WINDOW(1); 703 704 callout_reset(&sc->ex_mii_callout, hz, ex_tick, sc); 705 706 out: 707 if (error) { 708 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 709 ifp->if_timer = 0; 710 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 711 } 712 return (error); 713 } 714 715 #define MCHASHSIZE 256 716 #define ex_mchash(addr) (ether_crc32_be((addr), ETHER_ADDR_LEN) & \ 717 (MCHASHSIZE - 1)) 718 719 /* 720 * Set multicast receive filter. Also take care of promiscuous mode 721 * here (XXX). 722 */ 723 void 724 ex_set_mc(sc) 725 struct ex_softc *sc; 726 { 727 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 728 struct ethercom *ec = &sc->sc_ethercom; 729 struct ether_multi *enm; 730 struct ether_multistep estep; 731 int i; 732 u_int16_t mask = FIL_INDIVIDUAL | FIL_BRDCST; 733 734 if (ifp->if_flags & IFF_PROMISC) { 735 mask |= FIL_PROMISC; 736 goto allmulti; 737 } 738 739 ETHER_FIRST_MULTI(estep, ec, enm); 740 if (enm == NULL) 741 goto nomulti; 742 743 if ((sc->ex_conf & EX_CONF_90XB) == 0) 744 /* No multicast hash filtering. */ 745 goto allmulti; 746 747 for (i = 0; i < MCHASHSIZE; i++) 748 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 749 ELINK_COMMAND, ELINK_CLEARHASHFILBIT | i); 750 751 do { 752 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 753 ETHER_ADDR_LEN) != 0) 754 goto allmulti; 755 756 i = ex_mchash(enm->enm_addrlo); 757 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 758 ELINK_COMMAND, ELINK_SETHASHFILBIT | i); 759 ETHER_NEXT_MULTI(estep, enm); 760 } while (enm != NULL); 761 mask |= FIL_MULTIHASH; 762 763 nomulti: 764 ifp->if_flags &= ~IFF_ALLMULTI; 765 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_COMMAND, 766 SET_RX_FILTER | mask); 767 return; 768 769 allmulti: 770 ifp->if_flags |= IFF_ALLMULTI; 771 mask |= FIL_MULTICAST; 772 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_COMMAND, 773 SET_RX_FILTER | mask); 774 } 775 776 777 static void 778 ex_txstat(sc) 779 struct ex_softc *sc; 780 { 781 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 782 bus_space_tag_t iot = sc->sc_iot; 783 bus_space_handle_t ioh = sc->sc_ioh; 784 int i; 785 786 /* 787 * We need to read+write TX_STATUS until we get a 0 status 788 * in order to turn off the interrupt flag. 789 * ELINK_TXSTATUS is in the upper byte of 2 with ELINK_TIMER 790 * XXX: Big Endian? Can we assume that TXSTATUS will be the 791 * upper byte? 792 */ 793 while ((i = bus_space_read_2(iot, ioh, ELINK_TIMER)) & TXS_COMPLETE) { 794 bus_space_write_2(iot, ioh, ELINK_TIMER, 0x0); 795 796 if (i & TXS_JABBER) { 797 ++sc->sc_ethercom.ec_if.if_oerrors; 798 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 799 printf("%s: jabber (%x)\n", 800 sc->sc_dev.dv_xname, i); 801 ex_init(ifp); 802 /* TODO: be more subtle here */ 803 } else if (i & TXS_UNDERRUN) { 804 ++sc->sc_ethercom.ec_if.if_oerrors; 805 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG) 806 printf("%s: fifo underrun (%x) @%d\n", 807 sc->sc_dev.dv_xname, i, 808 sc->tx_start_thresh); 809 if (sc->tx_succ_ok < 100) 810 sc->tx_start_thresh = min(ETHER_MAX_LEN, 811 sc->tx_start_thresh + 20); 812 sc->tx_succ_ok = 0; 813 ex_init(ifp); 814 /* TODO: be more subtle here */ 815 } else if (i & TXS_MAX_COLLISION) { 816 ++sc->sc_ethercom.ec_if.if_oerrors; 817 ++sc->sc_ethercom.ec_if.if_collisions; 818 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_ENABLE); 819 sc->sc_ethercom.ec_if.if_flags &= ~IFF_OACTIVE; 820 } else if (sc->tx_succ_ok < 100) 821 sc->tx_succ_ok++; 822 } 823 } 824 825 int 826 ex_media_chg(ifp) 827 struct ifnet *ifp; 828 { 829 830 if (ifp->if_flags & IFF_UP) 831 ex_init(ifp); 832 return 0; 833 } 834 835 void 836 ex_set_xcvr(sc, media) 837 struct ex_softc *sc; 838 const u_int16_t media; 839 { 840 bus_space_tag_t iot = sc->sc_iot; 841 bus_space_handle_t ioh = sc->sc_ioh; 842 u_int32_t icfg; 843 844 /* 845 * We're already in Window 3 846 */ 847 icfg = bus_space_read_4(iot, ioh, ELINK_W3_INTERNAL_CONFIG); 848 icfg &= ~(CONFIG_XCVR_SEL << 16); 849 if (media & (ELINK_MEDIACAP_MII | ELINK_MEDIACAP_100BASET4)) 850 icfg |= ELINKMEDIA_MII << (CONFIG_XCVR_SEL_SHIFT + 16); 851 if (media & ELINK_MEDIACAP_100BASETX) 852 icfg |= ELINKMEDIA_AUTO << (CONFIG_XCVR_SEL_SHIFT + 16); 853 if (media & ELINK_MEDIACAP_100BASEFX) 854 icfg |= ELINKMEDIA_100BASE_FX 855 << (CONFIG_XCVR_SEL_SHIFT + 16); 856 bus_space_write_4(iot, ioh, ELINK_W3_INTERNAL_CONFIG, icfg); 857 } 858 859 void 860 ex_set_media(sc) 861 struct ex_softc *sc; 862 { 863 bus_space_tag_t iot = sc->sc_iot; 864 bus_space_handle_t ioh = sc->sc_ioh; 865 u_int32_t configreg; 866 867 if (((sc->ex_conf & EX_CONF_MII) && 868 (sc->ex_mii.mii_media_active & IFM_FDX)) 869 || (!(sc->ex_conf & EX_CONF_MII) && 870 (sc->ex_mii.mii_media.ifm_media & IFM_FDX))) { 871 bus_space_write_2(iot, ioh, ELINK_W3_MAC_CONTROL, 872 MAC_CONTROL_FDX); 873 } else { 874 bus_space_write_2(iot, ioh, ELINK_W3_MAC_CONTROL, 0); 875 } 876 877 /* 878 * If the device has MII, select it, and then tell the 879 * PHY which media to use. 880 */ 881 if (sc->ex_conf & EX_CONF_MII) { 882 u_int16_t val; 883 884 GO_WINDOW(3); 885 val = bus_space_read_2(iot, ioh, ELINK_W3_RESET_OPTIONS); 886 ex_set_xcvr(sc, val); 887 mii_mediachg(&sc->ex_mii); 888 return; 889 } 890 891 GO_WINDOW(4); 892 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 0); 893 bus_space_write_2(iot, ioh, ELINK_COMMAND, STOP_TRANSCEIVER); 894 delay(800); 895 896 /* 897 * Now turn on the selected media/transceiver. 898 */ 899 switch (IFM_SUBTYPE(sc->ex_mii.mii_media.ifm_cur->ifm_media)) { 900 case IFM_10_T: 901 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 902 JABBER_GUARD_ENABLE|LINKBEAT_ENABLE); 903 break; 904 905 case IFM_10_2: 906 bus_space_write_2(iot, ioh, ELINK_COMMAND, START_TRANSCEIVER); 907 DELAY(800); 908 break; 909 910 case IFM_100_TX: 911 case IFM_100_FX: 912 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 913 LINKBEAT_ENABLE); 914 DELAY(800); 915 break; 916 917 case IFM_10_5: 918 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 919 SQE_ENABLE); 920 DELAY(800); 921 break; 922 923 case IFM_MANUAL: 924 break; 925 926 case IFM_NONE: 927 return; 928 929 default: 930 panic("ex_set_media: impossible"); 931 } 932 933 GO_WINDOW(3); 934 configreg = bus_space_read_4(iot, ioh, ELINK_W3_INTERNAL_CONFIG); 935 936 configreg &= ~(CONFIG_MEDIAMASK << 16); 937 configreg |= (sc->ex_mii.mii_media.ifm_cur->ifm_data << 938 (CONFIG_MEDIAMASK_SHIFT + 16)); 939 940 bus_space_write_4(iot, ioh, ELINK_W3_INTERNAL_CONFIG, configreg); 941 } 942 943 /* 944 * Get currently-selected media from card. 945 * (if_media callback, may be called before interface is brought up). 946 */ 947 void 948 ex_media_stat(ifp, req) 949 struct ifnet *ifp; 950 struct ifmediareq *req; 951 { 952 struct ex_softc *sc = ifp->if_softc; 953 u_int16_t help; 954 955 if ((ifp->if_flags & (IFF_UP|IFF_RUNNING)) == (IFF_UP|IFF_RUNNING)) { 956 if (sc->ex_conf & EX_CONF_MII) { 957 mii_pollstat(&sc->ex_mii); 958 req->ifm_status = sc->ex_mii.mii_media_status; 959 req->ifm_active = sc->ex_mii.mii_media_active; 960 } else { 961 GO_WINDOW(4); 962 req->ifm_status = IFM_AVALID; 963 req->ifm_active = 964 sc->ex_mii.mii_media.ifm_cur->ifm_media; 965 help = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 966 ELINK_W4_MEDIA_TYPE); 967 if (help & LINKBEAT_DETECT) 968 req->ifm_status |= IFM_ACTIVE; 969 GO_WINDOW(1); 970 } 971 } 972 } 973 974 975 976 /* 977 * Start outputting on the interface. 978 */ 979 static void 980 ex_start(ifp) 981 struct ifnet *ifp; 982 { 983 struct ex_softc *sc = ifp->if_softc; 984 bus_space_tag_t iot = sc->sc_iot; 985 bus_space_handle_t ioh = sc->sc_ioh; 986 volatile struct ex_fraghdr *fr = NULL; 987 volatile struct ex_dpd *dpd = NULL, *prevdpd = NULL; 988 struct ex_txdesc *txp; 989 struct mbuf *mb_head; 990 bus_dmamap_t dmamap; 991 int offset, totlen, segment, error; 992 u_int32_t csum_flags; 993 994 if (sc->tx_head || sc->tx_free == NULL) 995 return; 996 997 txp = NULL; 998 999 /* 1000 * We're finished if there is nothing more to add to the list or if 1001 * we're all filled up with buffers to transmit. 1002 */ 1003 while (sc->tx_free != NULL) { 1004 /* 1005 * Grab a packet to transmit. 1006 */ 1007 IFQ_DEQUEUE(&ifp->if_snd, mb_head); 1008 if (mb_head == NULL) 1009 break; 1010 1011 /* 1012 * Get pointer to next available tx desc. 1013 */ 1014 txp = sc->tx_free; 1015 dmamap = txp->tx_dmamap; 1016 1017 /* 1018 * Go through each of the mbufs in the chain and initialize 1019 * the transmit buffer descriptors with the physical address 1020 * and size of the mbuf. 1021 */ 1022 reload: 1023 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 1024 mb_head, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1025 switch (error) { 1026 case 0: 1027 /* Success. */ 1028 break; 1029 1030 case EFBIG: 1031 { 1032 struct mbuf *mn; 1033 1034 /* 1035 * We ran out of segments. We have to recopy this 1036 * mbuf chain first. Bail out if we can't get the 1037 * new buffers. 1038 */ 1039 printf("%s: too many segments, ", sc->sc_dev.dv_xname); 1040 1041 MGETHDR(mn, M_DONTWAIT, MT_DATA); 1042 if (mn == NULL) { 1043 m_freem(mb_head); 1044 printf("aborting\n"); 1045 goto out; 1046 } 1047 if (mb_head->m_pkthdr.len > MHLEN) { 1048 MCLGET(mn, M_DONTWAIT); 1049 if ((mn->m_flags & M_EXT) == 0) { 1050 m_freem(mn); 1051 m_freem(mb_head); 1052 printf("aborting\n"); 1053 goto out; 1054 } 1055 } 1056 m_copydata(mb_head, 0, mb_head->m_pkthdr.len, 1057 mtod(mn, caddr_t)); 1058 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len; 1059 m_freem(mb_head); 1060 mb_head = mn; 1061 printf("retrying\n"); 1062 goto reload; 1063 } 1064 1065 default: 1066 /* 1067 * Some other problem; report it. 1068 */ 1069 printf("%s: can't load mbuf chain, error = %d\n", 1070 sc->sc_dev.dv_xname, error); 1071 m_freem(mb_head); 1072 goto out; 1073 } 1074 1075 /* 1076 * remove our tx desc from freelist. 1077 */ 1078 sc->tx_free = txp->tx_next; 1079 txp->tx_next = NULL; 1080 1081 fr = &txp->tx_dpd->dpd_frags[0]; 1082 totlen = 0; 1083 for (segment = 0; segment < dmamap->dm_nsegs; segment++, fr++) { 1084 fr->fr_addr = htole32(dmamap->dm_segs[segment].ds_addr); 1085 fr->fr_len = htole32(dmamap->dm_segs[segment].ds_len); 1086 totlen += dmamap->dm_segs[segment].ds_len; 1087 } 1088 fr--; 1089 fr->fr_len |= htole32(EX_FR_LAST); 1090 txp->tx_mbhead = mb_head; 1091 1092 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 1093 BUS_DMASYNC_PREWRITE); 1094 1095 dpd = txp->tx_dpd; 1096 dpd->dpd_nextptr = 0; 1097 dpd->dpd_fsh = htole32(totlen); 1098 1099 /* Byte-swap constants so compiler can optimize. */ 1100 1101 if (sc->ex_conf & EX_CONF_90XB) { 1102 csum_flags = 0; 1103 1104 if (mb_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 1105 csum_flags |= htole32(EX_DPD_IPCKSUM); 1106 1107 if (mb_head->m_pkthdr.csum_flags & M_CSUM_TCPv4) 1108 csum_flags |= htole32(EX_DPD_TCPCKSUM); 1109 else if (mb_head->m_pkthdr.csum_flags & M_CSUM_UDPv4) 1110 csum_flags |= htole32(EX_DPD_UDPCKSUM); 1111 1112 dpd->dpd_fsh |= csum_flags; 1113 } else { 1114 KDASSERT((mb_head->m_pkthdr.csum_flags & 1115 (M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4)) == 0); 1116 } 1117 1118 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap, 1119 ((const char *)(intptr_t)dpd - (const char *)sc->sc_dpd), 1120 sizeof (struct ex_dpd), 1121 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1122 1123 /* 1124 * No need to stall the download engine, we know it's 1125 * not busy right now. 1126 * 1127 * Fix up pointers in both the "soft" tx and the physical 1128 * tx list. 1129 */ 1130 if (sc->tx_head != NULL) { 1131 prevdpd = sc->tx_tail->tx_dpd; 1132 offset = ((const char *)(intptr_t)prevdpd - (const char *)sc->sc_dpd); 1133 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap, 1134 offset, sizeof (struct ex_dpd), 1135 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1136 prevdpd->dpd_nextptr = htole32(DPD_DMADDR(sc, txp)); 1137 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap, 1138 offset, sizeof (struct ex_dpd), 1139 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1140 sc->tx_tail->tx_next = txp; 1141 sc->tx_tail = txp; 1142 } else { 1143 sc->tx_tail = sc->tx_head = txp; 1144 } 1145 1146 #if NBPFILTER > 0 1147 /* 1148 * Pass packet to bpf if there is a listener. 1149 */ 1150 if (ifp->if_bpf) 1151 bpf_mtap(ifp->if_bpf, mb_head); 1152 #endif 1153 } 1154 out: 1155 if (sc->tx_head) { 1156 sc->tx_tail->tx_dpd->dpd_fsh |= htole32(EX_DPD_DNIND); 1157 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap, 1158 ((caddr_t)sc->tx_tail->tx_dpd - (caddr_t)sc->sc_dpd), 1159 sizeof (struct ex_dpd), 1160 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1161 ifp->if_flags |= IFF_OACTIVE; 1162 bus_space_write_2(iot, ioh, ELINK_COMMAND, ELINK_DNUNSTALL); 1163 bus_space_write_4(iot, ioh, ELINK_DNLISTPTR, 1164 DPD_DMADDR(sc, sc->tx_head)); 1165 1166 /* trigger watchdog */ 1167 ifp->if_timer = 5; 1168 } 1169 } 1170 1171 1172 int 1173 ex_intr(arg) 1174 void *arg; 1175 { 1176 struct ex_softc *sc = arg; 1177 bus_space_tag_t iot = sc->sc_iot; 1178 bus_space_handle_t ioh = sc->sc_ioh; 1179 u_int16_t stat; 1180 int ret = 0; 1181 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1182 1183 if ((ifp->if_flags & IFF_RUNNING) == 0 || 1184 !device_is_active(&sc->sc_dev)) 1185 return (0); 1186 1187 for (;;) { 1188 stat = bus_space_read_2(iot, ioh, ELINK_STATUS); 1189 1190 if ((stat & XL_WATCHED_INTERRUPTS) == 0) { 1191 if ((stat & INTR_LATCH) == 0) { 1192 #if 0 1193 printf("%s: intr latch cleared\n", 1194 sc->sc_dev.dv_xname); 1195 #endif 1196 break; 1197 } 1198 } 1199 1200 ret = 1; 1201 1202 /* 1203 * Acknowledge interrupts. 1204 */ 1205 bus_space_write_2(iot, ioh, ELINK_COMMAND, ACK_INTR | 1206 (stat & (XL_WATCHED_INTERRUPTS | INTR_LATCH))); 1207 if (sc->intr_ack) 1208 (*sc->intr_ack)(sc); 1209 1210 if (stat & HOST_ERROR) { 1211 printf("%s: adapter failure (%x)\n", 1212 sc->sc_dev.dv_xname, stat); 1213 ex_reset(sc); 1214 ex_init(ifp); 1215 return 1; 1216 } 1217 if (stat & TX_COMPLETE) { 1218 ex_txstat(sc); 1219 } 1220 if (stat & UPD_STATS) { 1221 ex_getstats(sc); 1222 } 1223 if (stat & DN_COMPLETE) { 1224 struct ex_txdesc *txp, *ptxp = NULL; 1225 bus_dmamap_t txmap; 1226 1227 /* reset watchdog timer, was set in ex_start() */ 1228 ifp->if_timer = 0; 1229 1230 for (txp = sc->tx_head; txp != NULL; 1231 txp = txp->tx_next) { 1232 bus_dmamap_sync(sc->sc_dmat, 1233 sc->sc_dpd_dmamap, 1234 (caddr_t)txp->tx_dpd - (caddr_t)sc->sc_dpd, 1235 sizeof (struct ex_dpd), 1236 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1237 if (txp->tx_mbhead != NULL) { 1238 txmap = txp->tx_dmamap; 1239 bus_dmamap_sync(sc->sc_dmat, txmap, 1240 0, txmap->dm_mapsize, 1241 BUS_DMASYNC_POSTWRITE); 1242 bus_dmamap_unload(sc->sc_dmat, txmap); 1243 m_freem(txp->tx_mbhead); 1244 txp->tx_mbhead = NULL; 1245 } 1246 ptxp = txp; 1247 } 1248 1249 /* 1250 * Move finished tx buffers back to the tx free list. 1251 */ 1252 if (sc->tx_free) { 1253 sc->tx_ftail->tx_next = sc->tx_head; 1254 sc->tx_ftail = ptxp; 1255 } else 1256 sc->tx_ftail = sc->tx_free = sc->tx_head; 1257 1258 sc->tx_head = sc->tx_tail = NULL; 1259 ifp->if_flags &= ~IFF_OACTIVE; 1260 } 1261 1262 if (stat & UP_COMPLETE) { 1263 struct ex_rxdesc *rxd; 1264 struct mbuf *m; 1265 struct ex_upd *upd; 1266 bus_dmamap_t rxmap; 1267 u_int32_t pktstat; 1268 1269 rcvloop: 1270 rxd = sc->rx_head; 1271 rxmap = rxd->rx_dmamap; 1272 m = rxd->rx_mbhead; 1273 upd = rxd->rx_upd; 1274 1275 bus_dmamap_sync(sc->sc_dmat, rxmap, 0, 1276 rxmap->dm_mapsize, 1277 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1278 bus_dmamap_sync(sc->sc_dmat, sc->sc_upd_dmamap, 1279 ((caddr_t)upd - (caddr_t)sc->sc_upd), 1280 sizeof (struct ex_upd), 1281 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1282 pktstat = le32toh(upd->upd_pktstatus); 1283 1284 if (pktstat & EX_UPD_COMPLETE) { 1285 /* 1286 * Remove first packet from the chain. 1287 */ 1288 sc->rx_head = rxd->rx_next; 1289 rxd->rx_next = NULL; 1290 1291 /* 1292 * Add a new buffer to the receive chain. 1293 * If this fails, the old buffer is recycled 1294 * instead. 1295 */ 1296 if (ex_add_rxbuf(sc, rxd) == 0) { 1297 u_int16_t total_len; 1298 1299 if (pktstat & 1300 ((sc->sc_ethercom.ec_capenable & 1301 ETHERCAP_VLAN_MTU) ? 1302 EX_UPD_ERR_VLAN : EX_UPD_ERR)) { 1303 ifp->if_ierrors++; 1304 m_freem(m); 1305 goto rcvloop; 1306 } 1307 1308 total_len = pktstat & EX_UPD_PKTLENMASK; 1309 if (total_len < 1310 sizeof(struct ether_header)) { 1311 m_freem(m); 1312 goto rcvloop; 1313 } 1314 m->m_pkthdr.rcvif = ifp; 1315 m->m_pkthdr.len = m->m_len = total_len; 1316 #if NBPFILTER > 0 1317 if (ifp->if_bpf) 1318 bpf_mtap(ifp->if_bpf, m); 1319 #endif 1320 /* 1321 * Set the incoming checksum information for the packet. 1322 */ 1323 if ((sc->ex_conf & EX_CONF_90XB) != 0 && 1324 (pktstat & EX_UPD_IPCHECKED) != 0) { 1325 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1326 if (pktstat & EX_UPD_IPCKSUMERR) 1327 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1328 if (pktstat & EX_UPD_TCPCHECKED) { 1329 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1330 if (pktstat & EX_UPD_TCPCKSUMERR) 1331 m->m_pkthdr.csum_flags |= 1332 M_CSUM_TCP_UDP_BAD; 1333 } else if (pktstat & EX_UPD_UDPCHECKED) { 1334 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1335 if (pktstat & EX_UPD_UDPCKSUMERR) 1336 m->m_pkthdr.csum_flags |= 1337 M_CSUM_TCP_UDP_BAD; 1338 } 1339 } 1340 (*ifp->if_input)(ifp, m); 1341 } 1342 goto rcvloop; 1343 } 1344 /* 1345 * Just in case we filled up all UPDs and the DMA engine 1346 * stalled. We could be more subtle about this. 1347 */ 1348 if (bus_space_read_4(iot, ioh, ELINK_UPLISTPTR) == 0) { 1349 printf("%s: uplistptr was 0\n", 1350 sc->sc_dev.dv_xname); 1351 ex_init(ifp); 1352 } else if (bus_space_read_4(iot, ioh, ELINK_UPPKTSTATUS) 1353 & 0x2000) { 1354 printf("%s: receive stalled\n", 1355 sc->sc_dev.dv_xname); 1356 bus_space_write_2(iot, ioh, ELINK_COMMAND, 1357 ELINK_UPUNSTALL); 1358 } 1359 } 1360 1361 #if NRND > 0 1362 if (stat) 1363 rnd_add_uint32(&sc->rnd_source, stat); 1364 #endif 1365 } 1366 1367 /* no more interrupts */ 1368 if (ret && IFQ_IS_EMPTY(&ifp->if_snd) == 0) 1369 ex_start(ifp); 1370 return ret; 1371 } 1372 1373 int 1374 ex_ioctl(ifp, cmd, data) 1375 struct ifnet *ifp; 1376 u_long cmd; 1377 caddr_t data; 1378 { 1379 struct ex_softc *sc = ifp->if_softc; 1380 struct ifreq *ifr = (struct ifreq *)data; 1381 int s, error; 1382 1383 s = splnet(); 1384 1385 switch (cmd) { 1386 case SIOCSIFMEDIA: 1387 case SIOCGIFMEDIA: 1388 error = ifmedia_ioctl(ifp, ifr, &sc->ex_mii.mii_media, cmd); 1389 break; 1390 case SIOCSIFFLAGS: 1391 /* If the interface is up and running, only modify the receive 1392 * filter when setting promiscuous or debug mode. Otherwise 1393 * fall through to ether_ioctl, which will reset the chip. 1394 */ 1395 #define RESETIGN (IFF_CANTCHANGE|IFF_DEBUG) 1396 if (((ifp->if_flags & (IFF_UP|IFF_RUNNING)) 1397 == (IFF_UP|IFF_RUNNING)) 1398 && ((ifp->if_flags & (~RESETIGN)) 1399 == (sc->sc_if_flags & (~RESETIGN)))) { 1400 ex_set_mc(sc); 1401 error = 0; 1402 break; 1403 #undef RESETIGN 1404 } 1405 /* FALLTHROUGH */ 1406 default: 1407 error = ether_ioctl(ifp, cmd, data); 1408 if (error == ENETRESET) { 1409 /* 1410 * Multicast list has changed; set the hardware filter 1411 * accordingly. 1412 */ 1413 if (ifp->if_flags & IFF_RUNNING) 1414 ex_set_mc(sc); 1415 error = 0; 1416 } 1417 break; 1418 } 1419 1420 sc->sc_if_flags = ifp->if_flags; 1421 splx(s); 1422 return (error); 1423 } 1424 1425 void 1426 ex_getstats(sc) 1427 struct ex_softc *sc; 1428 { 1429 bus_space_handle_t ioh = sc->sc_ioh; 1430 bus_space_tag_t iot = sc->sc_iot; 1431 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1432 u_int8_t upperok; 1433 1434 GO_WINDOW(6); 1435 upperok = bus_space_read_1(iot, ioh, UPPER_FRAMES_OK); 1436 ifp->if_ipackets += bus_space_read_1(iot, ioh, RX_FRAMES_OK); 1437 ifp->if_ipackets += (upperok & 0x03) << 8; 1438 ifp->if_opackets += bus_space_read_1(iot, ioh, TX_FRAMES_OK); 1439 ifp->if_opackets += (upperok & 0x30) << 4; 1440 ifp->if_ierrors += bus_space_read_1(iot, ioh, RX_OVERRUNS); 1441 ifp->if_collisions += bus_space_read_1(iot, ioh, TX_COLLISIONS); 1442 /* 1443 * There seems to be no way to get the exact number of collisions, 1444 * this is the number that occurred at the very least. 1445 */ 1446 ifp->if_collisions += 2 * bus_space_read_1(iot, ioh, 1447 TX_AFTER_X_COLLISIONS); 1448 /* 1449 * Interface byte counts are counted by ether_input() and 1450 * ether_output(), so don't accumulate them here. Just 1451 * read the NIC counters so they don't generate overflow interrupts. 1452 * Upper byte counters are latched from reading the totals, so 1453 * they don't need to be read if we don't need their values. 1454 */ 1455 (void)bus_space_read_2(iot, ioh, RX_TOTAL_OK); 1456 (void)bus_space_read_2(iot, ioh, TX_TOTAL_OK); 1457 1458 /* 1459 * Clear the following to avoid stats overflow interrupts 1460 */ 1461 (void)bus_space_read_1(iot, ioh, TX_DEFERRALS); 1462 (void)bus_space_read_1(iot, ioh, TX_AFTER_1_COLLISION); 1463 (void)bus_space_read_1(iot, ioh, TX_NO_SQE); 1464 (void)bus_space_read_1(iot, ioh, TX_CD_LOST); 1465 GO_WINDOW(4); 1466 (void)bus_space_read_1(iot, ioh, ELINK_W4_BADSSD); 1467 GO_WINDOW(1); 1468 } 1469 1470 void 1471 ex_printstats(sc) 1472 struct ex_softc *sc; 1473 { 1474 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1475 1476 ex_getstats(sc); 1477 printf("in %llu out %llu ierror %llu oerror %llu ibytes %llu obytes " 1478 "%llu\n", (unsigned long long)ifp->if_ipackets, 1479 (unsigned long long)ifp->if_opackets, 1480 (unsigned long long)ifp->if_ierrors, 1481 (unsigned long long)ifp->if_oerrors, 1482 (unsigned long long)ifp->if_ibytes, 1483 (unsigned long long)ifp->if_obytes); 1484 } 1485 1486 void 1487 ex_tick(arg) 1488 void *arg; 1489 { 1490 struct ex_softc *sc = arg; 1491 int s; 1492 1493 if (!device_is_active(&sc->sc_dev)) 1494 return; 1495 1496 s = splnet(); 1497 1498 if (sc->ex_conf & EX_CONF_MII) 1499 mii_tick(&sc->ex_mii); 1500 1501 if (!(bus_space_read_2((sc)->sc_iot, (sc)->sc_ioh, ELINK_STATUS) 1502 & COMMAND_IN_PROGRESS)) 1503 ex_getstats(sc); 1504 1505 splx(s); 1506 1507 callout_reset(&sc->ex_mii_callout, hz, ex_tick, sc); 1508 } 1509 1510 void 1511 ex_reset(sc) 1512 struct ex_softc *sc; 1513 { 1514 u_int16_t val = GLOBAL_RESET; 1515 1516 if (sc->ex_conf & EX_CONF_RESETHACK) 1517 val |= 0x10; 1518 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_COMMAND, val); 1519 /* 1520 * XXX apparently the command in progress bit can't be trusted 1521 * during a reset, so we just always wait this long. Fortunately 1522 * we normally only reset the chip during autoconfig. 1523 */ 1524 delay(100000); 1525 ex_waitcmd(sc); 1526 } 1527 1528 void 1529 ex_watchdog(ifp) 1530 struct ifnet *ifp; 1531 { 1532 struct ex_softc *sc = ifp->if_softc; 1533 1534 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1535 ++sc->sc_ethercom.ec_if.if_oerrors; 1536 1537 ex_reset(sc); 1538 ex_init(ifp); 1539 } 1540 1541 void 1542 ex_stop(ifp, disable) 1543 struct ifnet *ifp; 1544 int disable; 1545 { 1546 struct ex_softc *sc = ifp->if_softc; 1547 bus_space_tag_t iot = sc->sc_iot; 1548 bus_space_handle_t ioh = sc->sc_ioh; 1549 struct ex_txdesc *tx; 1550 struct ex_rxdesc *rx; 1551 int i; 1552 1553 bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_DISABLE); 1554 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_DISABLE); 1555 bus_space_write_2(iot, ioh, ELINK_COMMAND, STOP_TRANSCEIVER); 1556 1557 for (tx = sc->tx_head ; tx != NULL; tx = tx->tx_next) { 1558 if (tx->tx_mbhead == NULL) 1559 continue; 1560 m_freem(tx->tx_mbhead); 1561 tx->tx_mbhead = NULL; 1562 bus_dmamap_unload(sc->sc_dmat, tx->tx_dmamap); 1563 tx->tx_dpd->dpd_fsh = tx->tx_dpd->dpd_nextptr = 0; 1564 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap, 1565 ((caddr_t)tx->tx_dpd - (caddr_t)sc->sc_dpd), 1566 sizeof (struct ex_dpd), 1567 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1568 } 1569 sc->tx_tail = sc->tx_head = NULL; 1570 ex_init_txdescs(sc); 1571 1572 sc->rx_tail = sc->rx_head = 0; 1573 for (i = 0; i < EX_NUPD; i++) { 1574 rx = &sc->sc_rxdescs[i]; 1575 if (rx->rx_mbhead != NULL) { 1576 bus_dmamap_unload(sc->sc_dmat, rx->rx_dmamap); 1577 m_freem(rx->rx_mbhead); 1578 rx->rx_mbhead = NULL; 1579 } 1580 ex_add_rxbuf(sc, rx); 1581 } 1582 1583 bus_space_write_2(iot, ioh, ELINK_COMMAND, ACK_INTR | INTR_LATCH); 1584 1585 callout_stop(&sc->ex_mii_callout); 1586 if (sc->ex_conf & EX_CONF_MII) 1587 mii_down(&sc->ex_mii); 1588 1589 if (disable) 1590 ex_disable(sc); 1591 1592 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1593 sc->sc_if_flags = ifp->if_flags; 1594 ifp->if_timer = 0; 1595 } 1596 1597 static void 1598 ex_init_txdescs(sc) 1599 struct ex_softc *sc; 1600 { 1601 int i; 1602 1603 for (i = 0; i < EX_NDPD; i++) { 1604 sc->sc_txdescs[i].tx_dmamap = sc->sc_tx_dmamaps[i]; 1605 sc->sc_txdescs[i].tx_dpd = &sc->sc_dpd[i]; 1606 if (i < EX_NDPD - 1) 1607 sc->sc_txdescs[i].tx_next = &sc->sc_txdescs[i + 1]; 1608 else 1609 sc->sc_txdescs[i].tx_next = NULL; 1610 } 1611 sc->tx_free = &sc->sc_txdescs[0]; 1612 sc->tx_ftail = &sc->sc_txdescs[EX_NDPD-1]; 1613 } 1614 1615 1616 int 1617 ex_activate(self, act) 1618 struct device *self; 1619 enum devact act; 1620 { 1621 struct ex_softc *sc = (void *) self; 1622 int s, error = 0; 1623 1624 s = splnet(); 1625 switch (act) { 1626 case DVACT_ACTIVATE: 1627 error = EOPNOTSUPP; 1628 break; 1629 1630 case DVACT_DEACTIVATE: 1631 if (sc->ex_conf & EX_CONF_MII) 1632 mii_activate(&sc->ex_mii, act, MII_PHY_ANY, 1633 MII_OFFSET_ANY); 1634 if_deactivate(&sc->sc_ethercom.ec_if); 1635 break; 1636 } 1637 splx(s); 1638 1639 return (error); 1640 } 1641 1642 int 1643 ex_detach(sc) 1644 struct ex_softc *sc; 1645 { 1646 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1647 struct ex_rxdesc *rxd; 1648 int i; 1649 1650 /* Succeed now if there's no work to do. */ 1651 if ((sc->ex_flags & EX_FLAGS_ATTACHED) == 0) 1652 return (0); 1653 1654 /* Unhook our tick handler. */ 1655 callout_stop(&sc->ex_mii_callout); 1656 1657 if (sc->ex_conf & EX_CONF_MII) { 1658 /* Detach all PHYs */ 1659 mii_detach(&sc->ex_mii, MII_PHY_ANY, MII_OFFSET_ANY); 1660 } 1661 1662 /* Delete all remaining media. */ 1663 ifmedia_delete_instance(&sc->ex_mii.mii_media, IFM_INST_ANY); 1664 1665 #if NRND > 0 1666 rnd_detach_source(&sc->rnd_source); 1667 #endif 1668 ether_ifdetach(ifp); 1669 if_detach(ifp); 1670 1671 for (i = 0; i < EX_NUPD; i++) { 1672 rxd = &sc->sc_rxdescs[i]; 1673 if (rxd->rx_mbhead != NULL) { 1674 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap); 1675 m_freem(rxd->rx_mbhead); 1676 rxd->rx_mbhead = NULL; 1677 } 1678 } 1679 for (i = 0; i < EX_NUPD; i++) 1680 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rx_dmamaps[i]); 1681 for (i = 0; i < EX_NDPD; i++) 1682 bus_dmamap_destroy(sc->sc_dmat, sc->sc_tx_dmamaps[i]); 1683 bus_dmamap_unload(sc->sc_dmat, sc->sc_dpd_dmamap); 1684 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dpd_dmamap); 1685 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_dpd, 1686 EX_NDPD * sizeof (struct ex_dpd)); 1687 bus_dmamem_free(sc->sc_dmat, &sc->sc_dseg, sc->sc_drseg); 1688 bus_dmamap_unload(sc->sc_dmat, sc->sc_upd_dmamap); 1689 bus_dmamap_destroy(sc->sc_dmat, sc->sc_upd_dmamap); 1690 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_upd, 1691 EX_NUPD * sizeof (struct ex_upd)); 1692 bus_dmamem_free(sc->sc_dmat, &sc->sc_useg, sc->sc_urseg); 1693 1694 shutdownhook_disestablish(sc->sc_sdhook); 1695 powerhook_disestablish(sc->sc_powerhook); 1696 1697 return (0); 1698 } 1699 1700 /* 1701 * Before reboots, reset card completely. 1702 */ 1703 static void 1704 ex_shutdown(arg) 1705 void *arg; 1706 { 1707 struct ex_softc *sc = arg; 1708 1709 ex_stop(&sc->sc_ethercom.ec_if, 1); 1710 /* 1711 * Make sure the interface is powered up when we reboot, 1712 * otherwise firmware on some systems gets really confused. 1713 */ 1714 (void) ex_enable(sc); 1715 } 1716 1717 /* 1718 * Read EEPROM data. 1719 * XXX what to do if EEPROM doesn't unbusy? 1720 */ 1721 u_int16_t 1722 ex_read_eeprom(sc, offset) 1723 struct ex_softc *sc; 1724 int offset; 1725 { 1726 bus_space_tag_t iot = sc->sc_iot; 1727 bus_space_handle_t ioh = sc->sc_ioh; 1728 u_int16_t data = 0, cmd = READ_EEPROM; 1729 int off; 1730 1731 off = sc->ex_conf & EX_CONF_EEPROM_OFF ? 0x30 : 0; 1732 cmd = sc->ex_conf & EX_CONF_EEPROM_8BIT ? READ_EEPROM8 : READ_EEPROM; 1733 1734 GO_WINDOW(0); 1735 if (ex_eeprom_busy(sc)) 1736 goto out; 1737 bus_space_write_2(iot, ioh, ELINK_W0_EEPROM_COMMAND, 1738 cmd | (off + (offset & 0x3f))); 1739 if (ex_eeprom_busy(sc)) 1740 goto out; 1741 data = bus_space_read_2(iot, ioh, ELINK_W0_EEPROM_DATA); 1742 out: 1743 return data; 1744 } 1745 1746 static int 1747 ex_eeprom_busy(sc) 1748 struct ex_softc *sc; 1749 { 1750 bus_space_tag_t iot = sc->sc_iot; 1751 bus_space_handle_t ioh = sc->sc_ioh; 1752 int i = 100; 1753 1754 while (i--) { 1755 if (!(bus_space_read_2(iot, ioh, ELINK_W0_EEPROM_COMMAND) & 1756 EEPROM_BUSY)) 1757 return 0; 1758 delay(100); 1759 } 1760 printf("\n%s: eeprom stays busy.\n", sc->sc_dev.dv_xname); 1761 return (1); 1762 } 1763 1764 /* 1765 * Create a new rx buffer and add it to the 'soft' rx list. 1766 */ 1767 static int 1768 ex_add_rxbuf(sc, rxd) 1769 struct ex_softc *sc; 1770 struct ex_rxdesc *rxd; 1771 { 1772 struct mbuf *m, *oldm; 1773 bus_dmamap_t rxmap; 1774 int error, rval = 0; 1775 1776 oldm = rxd->rx_mbhead; 1777 rxmap = rxd->rx_dmamap; 1778 1779 MGETHDR(m, M_DONTWAIT, MT_DATA); 1780 if (m != NULL) { 1781 MCLGET(m, M_DONTWAIT); 1782 if ((m->m_flags & M_EXT) == 0) { 1783 m_freem(m); 1784 if (oldm == NULL) 1785 return 1; 1786 m = oldm; 1787 MRESETDATA(m); 1788 rval = 1; 1789 } 1790 } else { 1791 if (oldm == NULL) 1792 return 1; 1793 m = oldm; 1794 MRESETDATA(m); 1795 rval = 1; 1796 } 1797 1798 /* 1799 * Setup the DMA map for this receive buffer. 1800 */ 1801 if (m != oldm) { 1802 if (oldm != NULL) 1803 bus_dmamap_unload(sc->sc_dmat, rxmap); 1804 error = bus_dmamap_load(sc->sc_dmat, rxmap, 1805 m->m_ext.ext_buf, MCLBYTES, NULL, 1806 BUS_DMA_READ|BUS_DMA_NOWAIT); 1807 if (error) { 1808 printf("%s: can't load rx buffer, error = %d\n", 1809 sc->sc_dev.dv_xname, error); 1810 panic("ex_add_rxbuf"); /* XXX */ 1811 } 1812 } 1813 1814 /* 1815 * Align for data after 14 byte header. 1816 */ 1817 m->m_data += 2; 1818 1819 rxd->rx_mbhead = m; 1820 rxd->rx_upd->upd_pktstatus = htole32(MCLBYTES - 2); 1821 rxd->rx_upd->upd_frags[0].fr_addr = 1822 htole32(rxmap->dm_segs[0].ds_addr + 2); 1823 rxd->rx_upd->upd_nextptr = 0; 1824 1825 /* 1826 * Attach it to the end of the list. 1827 */ 1828 if (sc->rx_head != NULL) { 1829 sc->rx_tail->rx_next = rxd; 1830 sc->rx_tail->rx_upd->upd_nextptr = htole32(sc->sc_upddma + 1831 ((caddr_t)rxd->rx_upd - (caddr_t)sc->sc_upd)); 1832 bus_dmamap_sync(sc->sc_dmat, sc->sc_upd_dmamap, 1833 (caddr_t)sc->rx_tail->rx_upd - (caddr_t)sc->sc_upd, 1834 sizeof (struct ex_upd), 1835 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1836 } else { 1837 sc->rx_head = rxd; 1838 } 1839 sc->rx_tail = rxd; 1840 1841 bus_dmamap_sync(sc->sc_dmat, rxmap, 0, rxmap->dm_mapsize, 1842 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1843 bus_dmamap_sync(sc->sc_dmat, sc->sc_upd_dmamap, 1844 ((caddr_t)rxd->rx_upd - (caddr_t)sc->sc_upd), 1845 sizeof (struct ex_upd), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1846 return (rval); 1847 } 1848 1849 u_int32_t 1850 ex_mii_bitbang_read(self) 1851 struct device *self; 1852 { 1853 struct ex_softc *sc = (void *) self; 1854 1855 /* We're already in Window 4. */ 1856 return (bus_space_read_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_PHYSMGMT)); 1857 } 1858 1859 void 1860 ex_mii_bitbang_write(self, val) 1861 struct device *self; 1862 u_int32_t val; 1863 { 1864 struct ex_softc *sc = (void *) self; 1865 1866 /* We're already in Window 4. */ 1867 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_PHYSMGMT, val); 1868 } 1869 1870 int 1871 ex_mii_readreg(v, phy, reg) 1872 struct device *v; 1873 int phy, reg; 1874 { 1875 struct ex_softc *sc = (struct ex_softc *)v; 1876 int val; 1877 1878 if ((sc->ex_conf & EX_CONF_INTPHY) && phy != ELINK_INTPHY_ID) 1879 return 0; 1880 1881 GO_WINDOW(4); 1882 1883 val = mii_bitbang_readreg(v, &ex_mii_bitbang_ops, phy, reg); 1884 1885 GO_WINDOW(1); 1886 1887 return (val); 1888 } 1889 1890 void 1891 ex_mii_writereg(v, phy, reg, data) 1892 struct device *v; 1893 int phy; 1894 int reg; 1895 int data; 1896 { 1897 struct ex_softc *sc = (struct ex_softc *)v; 1898 1899 GO_WINDOW(4); 1900 1901 mii_bitbang_writereg(v, &ex_mii_bitbang_ops, phy, reg, data); 1902 1903 GO_WINDOW(1); 1904 } 1905 1906 void 1907 ex_mii_statchg(v) 1908 struct device *v; 1909 { 1910 struct ex_softc *sc = (struct ex_softc *)v; 1911 bus_space_tag_t iot = sc->sc_iot; 1912 bus_space_handle_t ioh = sc->sc_ioh; 1913 int mctl; 1914 1915 GO_WINDOW(3); 1916 mctl = bus_space_read_2(iot, ioh, ELINK_W3_MAC_CONTROL); 1917 if (sc->ex_mii.mii_media_active & IFM_FDX) 1918 mctl |= MAC_CONTROL_FDX; 1919 else 1920 mctl &= ~MAC_CONTROL_FDX; 1921 bus_space_write_2(iot, ioh, ELINK_W3_MAC_CONTROL, mctl); 1922 GO_WINDOW(1); /* back to operating window */ 1923 } 1924 1925 int 1926 ex_enable(sc) 1927 struct ex_softc *sc; 1928 { 1929 if (sc->enabled == 0 && sc->enable != NULL) { 1930 if ((*sc->enable)(sc) != 0) { 1931 printf("%s: de/vice enable failed\n", 1932 sc->sc_dev.dv_xname); 1933 return (EIO); 1934 } 1935 sc->enabled = 1; 1936 } 1937 return (0); 1938 } 1939 1940 void 1941 ex_disable(sc) 1942 struct ex_softc *sc; 1943 { 1944 if (sc->enabled == 1 && sc->disable != NULL) { 1945 (*sc->disable)(sc); 1946 sc->enabled = 0; 1947 } 1948 } 1949 1950 void 1951 ex_power(why, arg) 1952 int why; 1953 void *arg; 1954 { 1955 struct ex_softc *sc = (void *)arg; 1956 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1957 int s; 1958 1959 s = splnet(); 1960 switch (why) { 1961 case PWR_SUSPEND: 1962 case PWR_STANDBY: 1963 ex_stop(ifp, 0); 1964 if (sc->power != NULL) 1965 (*sc->power)(sc, why); 1966 break; 1967 case PWR_RESUME: 1968 if (ifp->if_flags & IFF_UP) { 1969 if (sc->power != NULL) 1970 (*sc->power)(sc, why); 1971 ex_init(ifp); 1972 } 1973 break; 1974 case PWR_SOFTSUSPEND: 1975 case PWR_SOFTSTANDBY: 1976 case PWR_SOFTRESUME: 1977 break; 1978 } 1979 splx(s); 1980 } 1981
Indexes created Wed Oct 22 13:09:56 GMT 2025