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gem.c revision 1.77
      1  1.77   xtraeme /*	$NetBSD: gem.c,v 1.77 2008/05/04 17:16:27 xtraeme Exp $ */
      2   1.1       eeh 
      3   1.1       eeh /*
      4  1.31      heas  *
      5   1.1       eeh  * Copyright (C) 2001 Eduardo Horvath.
      6  1.68       jdc  * Copyright (c) 2001-2003 Thomas Moestl
      7   1.1       eeh  * All rights reserved.
      8   1.1       eeh  *
      9   1.1       eeh  *
     10   1.1       eeh  * Redistribution and use in source and binary forms, with or without
     11   1.1       eeh  * modification, are permitted provided that the following conditions
     12   1.1       eeh  * are met:
     13   1.1       eeh  * 1. Redistributions of source code must retain the above copyright
     14   1.1       eeh  *    notice, this list of conditions and the following disclaimer.
     15   1.1       eeh  * 2. Redistributions in binary form must reproduce the above copyright
     16   1.1       eeh  *    notice, this list of conditions and the following disclaimer in the
     17   1.1       eeh  *    documentation and/or other materials provided with the distribution.
     18  1.31      heas  *
     19   1.1       eeh  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR  ``AS IS'' AND
     20   1.1       eeh  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     21   1.1       eeh  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     22   1.1       eeh  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR  BE LIABLE
     23   1.1       eeh  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     24   1.1       eeh  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     25   1.1       eeh  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     26   1.1       eeh  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     27   1.1       eeh  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     28   1.1       eeh  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     29   1.1       eeh  * SUCH DAMAGE.
     30   1.1       eeh  *
     31   1.1       eeh  */
     32   1.1       eeh 
     33   1.1       eeh /*
     34  1.68       jdc  * Driver for Apple GMAC, Sun ERI and Sun GEM Ethernet controllers
     35  1.68       jdc  * See `GEM Gigabit Ethernet ASIC Specification'
     36  1.68       jdc  *   http://www.sun.com/processors/manuals/ge.pdf
     37   1.1       eeh  */
     38  1.10     lukem 
     39  1.10     lukem #include <sys/cdefs.h>
     40  1.77   xtraeme __KERNEL_RCSID(0, "$NetBSD: gem.c,v 1.77 2008/05/04 17:16:27 xtraeme Exp $");
     41   1.1       eeh 
     42  1.35      heas #include "opt_inet.h"
     43   1.1       eeh #include "bpfilter.h"
     44   1.1       eeh 
     45   1.1       eeh #include <sys/param.h>
     46  1.31      heas #include <sys/systm.h>
     47   1.1       eeh #include <sys/callout.h>
     48  1.31      heas #include <sys/mbuf.h>
     49   1.1       eeh #include <sys/syslog.h>
     50   1.1       eeh #include <sys/malloc.h>
     51   1.1       eeh #include <sys/kernel.h>
     52   1.1       eeh #include <sys/socket.h>
     53   1.1       eeh #include <sys/ioctl.h>
     54   1.1       eeh #include <sys/errno.h>
     55   1.1       eeh #include <sys/device.h>
     56   1.1       eeh 
     57   1.1       eeh #include <machine/endian.h>
     58   1.1       eeh 
     59   1.1       eeh #include <uvm/uvm_extern.h>
     60  1.31      heas 
     61   1.1       eeh #include <net/if.h>
     62   1.1       eeh #include <net/if_dl.h>
     63   1.1       eeh #include <net/if_media.h>
     64   1.1       eeh #include <net/if_ether.h>
     65   1.1       eeh 
     66  1.35      heas #ifdef INET
     67  1.35      heas #include <netinet/in.h>
     68  1.35      heas #include <netinet/in_systm.h>
     69  1.35      heas #include <netinet/in_var.h>
     70  1.35      heas #include <netinet/ip.h>
     71  1.35      heas #include <netinet/tcp.h>
     72  1.35      heas #include <netinet/udp.h>
     73  1.35      heas #endif
     74  1.35      heas 
     75  1.31      heas #if NBPFILTER > 0
     76   1.1       eeh #include <net/bpf.h>
     77  1.31      heas #endif
     78   1.1       eeh 
     79  1.60        ad #include <sys/bus.h>
     80  1.60        ad #include <sys/intr.h>
     81   1.1       eeh 
     82   1.1       eeh #include <dev/mii/mii.h>
     83   1.1       eeh #include <dev/mii/miivar.h>
     84   1.1       eeh #include <dev/mii/mii_bitbang.h>
     85   1.1       eeh 
     86   1.1       eeh #include <dev/ic/gemreg.h>
     87   1.1       eeh #include <dev/ic/gemvar.h>
     88   1.1       eeh 
     89   1.1       eeh #define TRIES	10000
     90   1.1       eeh 
     91  1.41  christos static void	gem_start(struct ifnet *);
     92  1.41  christos static void	gem_stop(struct ifnet *, int);
     93  1.53  christos int		gem_ioctl(struct ifnet *, u_long, void *);
     94  1.34     perry void		gem_tick(void *);
     95  1.34     perry void		gem_watchdog(struct ifnet *);
     96  1.34     perry void		gem_shutdown(void *);
     97  1.68       jdc void		gem_pcs_start(struct gem_softc *sc);
     98  1.68       jdc void		gem_pcs_stop(struct gem_softc *sc, int);
     99  1.34     perry int		gem_init(struct ifnet *);
    100   1.1       eeh void		gem_init_regs(struct gem_softc *sc);
    101   1.1       eeh static int	gem_ringsize(int sz);
    102  1.41  christos static int	gem_meminit(struct gem_softc *);
    103  1.34     perry void		gem_mifinit(struct gem_softc *);
    104  1.50    martin static int	gem_bitwait(struct gem_softc *sc, bus_space_handle_t, int,
    105  1.50    martin 		    u_int32_t, u_int32_t);
    106  1.34     perry void		gem_reset(struct gem_softc *);
    107   1.1       eeh int		gem_reset_rx(struct gem_softc *sc);
    108  1.68       jdc static void	gem_reset_rxdma(struct gem_softc *sc);
    109  1.68       jdc static void	gem_rx_common(struct gem_softc *sc);
    110   1.1       eeh int		gem_reset_tx(struct gem_softc *sc);
    111   1.1       eeh int		gem_disable_rx(struct gem_softc *sc);
    112   1.1       eeh int		gem_disable_tx(struct gem_softc *sc);
    113  1.41  christos static void	gem_rxdrain(struct gem_softc *sc);
    114   1.1       eeh int		gem_add_rxbuf(struct gem_softc *sc, int idx);
    115  1.34     perry void		gem_setladrf(struct gem_softc *);
    116   1.1       eeh 
    117   1.1       eeh /* MII methods & callbacks */
    118  1.34     perry static int	gem_mii_readreg(struct device *, int, int);
    119  1.34     perry static void	gem_mii_writereg(struct device *, int, int, int);
    120  1.34     perry static void	gem_mii_statchg(struct device *);
    121  1.34     perry 
    122  1.68       jdc void		gem_statuschange(struct gem_softc *);
    123  1.68       jdc 
    124  1.69    dyoung int		gem_ser_mediachange(struct ifnet *);
    125  1.69    dyoung void		gem_ser_mediastatus(struct ifnet *, struct ifmediareq *);
    126  1.34     perry 
    127  1.34     perry struct mbuf	*gem_get(struct gem_softc *, int, int);
    128  1.34     perry int		gem_put(struct gem_softc *, int, struct mbuf *);
    129  1.34     perry void		gem_read(struct gem_softc *, int, int);
    130  1.68       jdc int		gem_pint(struct gem_softc *);
    131  1.34     perry int		gem_eint(struct gem_softc *, u_int);
    132  1.34     perry int		gem_rint(struct gem_softc *);
    133  1.34     perry int		gem_tint(struct gem_softc *);
    134  1.34     perry void		gem_power(int, void *);
    135   1.1       eeh 
    136   1.1       eeh #ifdef GEM_DEBUG
    137  1.67    dyoung static void gem_txsoft_print(const struct gem_softc *, int, int);
    138   1.1       eeh #define	DPRINTF(sc, x)	if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \
    139   1.1       eeh 				printf x
    140   1.1       eeh #else
    141   1.1       eeh #define	DPRINTF(sc, x)	/* nothing */
    142   1.1       eeh #endif
    143   1.1       eeh 
    144  1.40    bouyer #define ETHER_MIN_TX (ETHERMIN + sizeof(struct ether_header))
    145  1.40    bouyer 
    146   1.1       eeh 
    147   1.1       eeh /*
    148   1.6   thorpej  * gem_attach:
    149   1.1       eeh  *
    150   1.1       eeh  *	Attach a Gem interface to the system.
    151   1.1       eeh  */
    152   1.1       eeh void
    153   1.6   thorpej gem_attach(sc, enaddr)
    154   1.1       eeh 	struct gem_softc *sc;
    155   1.6   thorpej 	const uint8_t *enaddr;
    156   1.1       eeh {
    157   1.1       eeh 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
    158   1.1       eeh 	struct mii_data *mii = &sc->sc_mii;
    159  1.68       jdc 	bus_space_tag_t t = sc->sc_bustag;
    160  1.68       jdc 	bus_space_handle_t h = sc->sc_h1;
    161  1.15      matt 	struct ifmedia_entry *ifm;
    162   1.1       eeh 	int i, error;
    163  1.15      matt 	u_int32_t v;
    164  1.40    bouyer 	char *nullbuf;
    165   1.1       eeh 
    166   1.1       eeh 	/* Make sure the chip is stopped. */
    167   1.1       eeh 	ifp->if_softc = sc;
    168   1.1       eeh 	gem_reset(sc);
    169   1.1       eeh 
    170   1.1       eeh 	/*
    171   1.1       eeh 	 * Allocate the control data structures, and create and load the
    172  1.40    bouyer 	 * DMA map for it. gem_control_data is 9216 bytes, we have space for
    173  1.40    bouyer 	 * the padding buffer in the bus_dmamem_alloc()'d memory.
    174   1.1       eeh 	 */
    175   1.1       eeh 	if ((error = bus_dmamem_alloc(sc->sc_dmatag,
    176  1.40    bouyer 	    sizeof(struct gem_control_data) + ETHER_MIN_TX, PAGE_SIZE,
    177  1.40    bouyer 	    0, &sc->sc_cdseg, 1, &sc->sc_cdnseg, 0)) != 0) {
    178  1.76    cegger 		aprint_error_dev(&sc->sc_dev,
    179  1.76    cegger 		   "unable to allocate control data, error = %d\n",
    180  1.76    cegger 		    error);
    181   1.1       eeh 		goto fail_0;
    182   1.1       eeh 	}
    183   1.1       eeh 
    184  1.68       jdc 	/* XXX should map this in with correct endianness */
    185   1.1       eeh 	if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg,
    186  1.53  christos 	    sizeof(struct gem_control_data), (void **)&sc->sc_control_data,
    187   1.1       eeh 	    BUS_DMA_COHERENT)) != 0) {
    188  1.76    cegger 		aprint_error_dev(&sc->sc_dev, "unable to map control data, error = %d\n",
    189  1.76    cegger 		    error);
    190   1.1       eeh 		goto fail_1;
    191   1.1       eeh 	}
    192   1.1       eeh 
    193  1.40    bouyer 	nullbuf =
    194  1.54  christos 	    (char *)sc->sc_control_data + sizeof(struct gem_control_data);
    195  1.40    bouyer 
    196   1.1       eeh 	if ((error = bus_dmamap_create(sc->sc_dmatag,
    197   1.1       eeh 	    sizeof(struct gem_control_data), 1,
    198   1.1       eeh 	    sizeof(struct gem_control_data), 0, 0, &sc->sc_cddmamap)) != 0) {
    199  1.76    cegger 		aprint_error_dev(&sc->sc_dev, "unable to create control data DMA map, "
    200  1.76    cegger 		    "error = %d\n", error);
    201   1.1       eeh 		goto fail_2;
    202   1.1       eeh 	}
    203   1.1       eeh 
    204   1.1       eeh 	if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap,
    205   1.1       eeh 	    sc->sc_control_data, sizeof(struct gem_control_data), NULL,
    206   1.1       eeh 	    0)) != 0) {
    207  1.76    cegger 		aprint_error_dev(&sc->sc_dev,
    208  1.76    cegger 		    "unable to load control data DMA map, error = %d\n",
    209  1.76    cegger 		    error);
    210   1.1       eeh 		goto fail_3;
    211   1.1       eeh 	}
    212   1.1       eeh 
    213  1.40    bouyer 	memset(nullbuf, 0, ETHER_MIN_TX);
    214  1.40    bouyer 	if ((error = bus_dmamap_create(sc->sc_dmatag,
    215  1.40    bouyer 	    ETHER_MIN_TX, 1, ETHER_MIN_TX, 0, 0, &sc->sc_nulldmamap)) != 0) {
    216  1.76    cegger 		aprint_error_dev(&sc->sc_dev, "unable to create padding DMA map, "
    217  1.76    cegger 		    "error = %d\n", error);
    218  1.40    bouyer 		goto fail_4;
    219  1.40    bouyer 	}
    220  1.40    bouyer 
    221  1.40    bouyer 	if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_nulldmamap,
    222  1.40    bouyer 	    nullbuf, ETHER_MIN_TX, NULL, 0)) != 0) {
    223  1.76    cegger 		aprint_error_dev(&sc->sc_dev,
    224  1.76    cegger 		    "unable to load padding DMA map, error = %d\n",
    225  1.76    cegger 		    error);
    226  1.40    bouyer 		goto fail_5;
    227  1.40    bouyer 	}
    228  1.40    bouyer 
    229  1.40    bouyer 	bus_dmamap_sync(sc->sc_dmatag, sc->sc_nulldmamap, 0, ETHER_MIN_TX,
    230  1.40    bouyer 	    BUS_DMASYNC_PREWRITE);
    231  1.40    bouyer 
    232   1.1       eeh 	/*
    233   1.1       eeh 	 * Initialize the transmit job descriptors.
    234   1.1       eeh 	 */
    235   1.1       eeh 	SIMPLEQ_INIT(&sc->sc_txfreeq);
    236   1.1       eeh 	SIMPLEQ_INIT(&sc->sc_txdirtyq);
    237   1.1       eeh 
    238   1.1       eeh 	/*
    239   1.1       eeh 	 * Create the transmit buffer DMA maps.
    240   1.1       eeh 	 */
    241   1.1       eeh 	for (i = 0; i < GEM_TXQUEUELEN; i++) {
    242   1.1       eeh 		struct gem_txsoft *txs;
    243   1.1       eeh 
    244   1.1       eeh 		txs = &sc->sc_txsoft[i];
    245   1.1       eeh 		txs->txs_mbuf = NULL;
    246  1.15      matt 		if ((error = bus_dmamap_create(sc->sc_dmatag,
    247  1.15      matt 		    ETHER_MAX_LEN_JUMBO, GEM_NTXSEGS,
    248  1.15      matt 		    ETHER_MAX_LEN_JUMBO, 0, 0,
    249   1.1       eeh 		    &txs->txs_dmamap)) != 0) {
    250  1.76    cegger 			aprint_error_dev(&sc->sc_dev, "unable to create tx DMA map %d, "
    251  1.76    cegger 			    "error = %d\n", i, error);
    252  1.40    bouyer 			goto fail_6;
    253   1.1       eeh 		}
    254   1.1       eeh 		SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
    255   1.1       eeh 	}
    256   1.1       eeh 
    257   1.1       eeh 	/*
    258   1.1       eeh 	 * Create the receive buffer DMA maps.
    259   1.1       eeh 	 */
    260   1.1       eeh 	for (i = 0; i < GEM_NRXDESC; i++) {
    261   1.1       eeh 		if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1,
    262   1.1       eeh 		    MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) {
    263  1.76    cegger 			aprint_error_dev(&sc->sc_dev, "unable to create rx DMA map %d, "
    264  1.76    cegger 			    "error = %d\n", i, error);
    265  1.40    bouyer 			goto fail_7;
    266   1.1       eeh 		}
    267   1.1       eeh 		sc->sc_rxsoft[i].rxs_mbuf = NULL;
    268   1.1       eeh 	}
    269   1.1       eeh 
    270  1.68       jdc 	/* Initialize ifmedia structures and MII info */
    271  1.68       jdc 	mii->mii_ifp = ifp;
    272  1.68       jdc 	mii->mii_readreg = gem_mii_readreg;
    273  1.68       jdc 	mii->mii_writereg = gem_mii_writereg;
    274  1.68       jdc 	mii->mii_statchg = gem_mii_statchg;
    275  1.68       jdc 
    276  1.69    dyoung 	sc->sc_ethercom.ec_mii = mii;
    277  1.68       jdc 
    278  1.68       jdc 	/*
    279  1.68       jdc 	 * Initialization based  on `GEM Gigabit Ethernet ASIC Specification'
    280  1.68       jdc 	 * Section 3.2.1 `Initialization Sequence'.
    281  1.68       jdc 	 * However, we can't assume SERDES or Serialink if neither
    282  1.68       jdc 	 * GEM_MIF_CONFIG_MDI0 nor GEM_MIF_CONFIG_MDI1 are set
    283  1.68       jdc 	 * being set, as both are set on Sun X1141A (with SERDES).  So,
    284  1.68       jdc 	 * we rely on our bus attachment setting GEM_SERDES or GEM_SERIAL.
    285  1.70       jdc 	 * Also, for Apple variants with 2 PHY's, we prefer the external
    286  1.70       jdc 	 * PHY over the internal PHY.
    287  1.68       jdc 	 */
    288  1.68       jdc 	gem_mifinit(sc);
    289  1.68       jdc 
    290  1.68       jdc 	if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) {
    291  1.69    dyoung 		ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange,
    292  1.69    dyoung 		    ether_mediastatus);
    293  1.68       jdc 		mii_attach(&sc->sc_dev, mii, 0xffffffff,
    294  1.68       jdc 		    MII_PHY_ANY, MII_OFFSET_ANY, MIIF_FORCEANEG);
    295  1.69    dyoung 		if (LIST_EMPTY(&mii->mii_phys)) {
    296  1.68       jdc 				/* No PHY attached */
    297  1.76    cegger 				aprint_error_dev(&sc->sc_dev, "PHY probe failed\n");
    298  1.68       jdc 				goto fail_7;
    299  1.68       jdc 		} else {
    300  1.69    dyoung 			struct mii_softc *child;
    301  1.69    dyoung 
    302  1.68       jdc 			/*
    303  1.68       jdc 			 * Walk along the list of attached MII devices and
    304  1.68       jdc 			 * establish an `MII instance' to `PHY number'
    305  1.68       jdc 			 * mapping.
    306  1.68       jdc 			 */
    307  1.69    dyoung 			LIST_FOREACH(child, &mii->mii_phys, mii_list) {
    308  1.68       jdc 				/*
    309  1.68       jdc 				 * Note: we support just one PHY: the internal
    310  1.68       jdc 				 * or external MII is already selected for us
    311  1.68       jdc 				 * by the GEM_MIF_CONFIG  register.
    312  1.68       jdc 				 */
    313  1.68       jdc 				if (child->mii_phy > 1 || child->mii_inst > 0) {
    314  1.76    cegger 					aprint_error_dev(&sc->sc_dev,
    315  1.76    cegger 					    "cannot accommodate MII device"
    316  1.68       jdc 					    " %s at PHY %d, instance %d\n",
    317  1.77   xtraeme 					       device_xname(child->mii_dev),
    318  1.68       jdc 					       child->mii_phy, child->mii_inst);
    319  1.68       jdc 					continue;
    320  1.68       jdc 				}
    321  1.68       jdc 				sc->sc_phys[child->mii_inst] = child->mii_phy;
    322  1.68       jdc 			}
    323  1.68       jdc 
    324  1.70       jdc 			/*
    325  1.70       jdc 			 * Now select and activate the PHY we will use.
    326  1.70       jdc 			 *
    327  1.70       jdc 			 * The order of preference is External (MDI1),
    328  1.70       jdc 			 * then Internal (MDI0),
    329  1.70       jdc 			 */
    330  1.70       jdc 			if (sc->sc_phys[1]) {
    331  1.68       jdc #ifdef GEM_DEBUG
    332  1.76    cegger 				aprint_debug_dev(&sc->sc_dev, "using external PHY\n");
    333  1.68       jdc #endif
    334  1.70       jdc 				sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL;
    335  1.68       jdc 			} else {
    336  1.68       jdc #ifdef GEM_DEBUG
    337  1.76    cegger 				aprint_debug_dev(&sc->sc_dev, "using internal PHY\n");
    338  1.70       jdc 				sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL;
    339  1.68       jdc #endif
    340  1.68       jdc 			}
    341  1.70       jdc 			bus_space_write_4(t, h, GEM_MIF_CONFIG,
    342  1.70       jdc 			    sc->sc_mif_config);
    343  1.68       jdc 			if (sc->sc_variant != GEM_SUN_ERI)
    344  1.68       jdc 				bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE,
    345  1.68       jdc 				    GEM_MII_DATAPATH_MII);
    346  1.68       jdc 
    347  1.68       jdc 			/*
    348  1.68       jdc 			 * XXX - we can really do the following ONLY if the
    349  1.68       jdc 			 * PHY indeed has the auto negotiation capability!!
    350  1.68       jdc 			 */
    351  1.69    dyoung 			ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
    352  1.68       jdc 		}
    353  1.68       jdc 	} else {
    354  1.69    dyoung 		ifmedia_init(&mii->mii_media, IFM_IMASK, gem_ser_mediachange,
    355  1.69    dyoung 		    gem_ser_mediastatus);
    356  1.68       jdc 		/* SERDES or Serialink */
    357  1.68       jdc 		if (sc->sc_flags & GEM_SERDES) {
    358  1.68       jdc 			bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE,
    359  1.68       jdc 			    GEM_MII_DATAPATH_SERDES);
    360  1.68       jdc 		} else {
    361  1.68       jdc 			sc->sc_flags |= GEM_SERIAL;
    362  1.68       jdc 			bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE,
    363  1.68       jdc 			    GEM_MII_DATAPATH_SERIAL);
    364  1.68       jdc 		}
    365  1.68       jdc 
    366  1.76    cegger 		aprint_normal_dev(&sc->sc_dev, "using external PCS %s: ",
    367  1.68       jdc 		    sc->sc_flags & GEM_SERDES ? "SERDES" : "Serialink");
    368  1.68       jdc 
    369  1.69    dyoung 		ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO, 0, NULL);
    370  1.68       jdc 		/* Check for FDX and HDX capabilities */
    371  1.68       jdc 		sc->sc_mii_anar = bus_space_read_4(t, h, GEM_MII_ANAR);
    372  1.68       jdc 		if (sc->sc_mii_anar & GEM_MII_ANEG_FUL_DUPLX) {
    373  1.69    dyoung 			ifmedia_add(&sc->sc_mii.mii_media,
    374  1.68       jdc 			    IFM_ETHER|IFM_1000_SX|IFM_MANUAL|IFM_FDX, 0, NULL);
    375  1.68       jdc 			aprint_normal("1000baseSX-FDX, ");
    376  1.68       jdc 		}
    377  1.68       jdc 		if (sc->sc_mii_anar & GEM_MII_ANEG_HLF_DUPLX) {
    378  1.69    dyoung 			ifmedia_add(&sc->sc_mii.mii_media,
    379  1.68       jdc 			    IFM_ETHER|IFM_1000_SX|IFM_MANUAL|IFM_HDX, 0, NULL);
    380  1.68       jdc 			aprint_normal("1000baseSX-HDX, ");
    381  1.68       jdc 		}
    382  1.69    dyoung 		ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
    383  1.68       jdc 		sc->sc_mii_media = IFM_AUTO;
    384  1.68       jdc 		aprint_normal("auto\n");
    385  1.68       jdc 
    386  1.68       jdc 		gem_pcs_stop(sc, 1);
    387  1.68       jdc 	}
    388  1.68       jdc 
    389   1.1       eeh 	/*
    390   1.1       eeh 	 * From this point forward, the attachment cannot fail.  A failure
    391   1.1       eeh 	 * before this point releases all resources that may have been
    392   1.1       eeh 	 * allocated.
    393   1.1       eeh 	 */
    394   1.1       eeh 
    395   1.1       eeh 	/* Announce ourselves. */
    396  1.76    cegger 	aprint_normal_dev(&sc->sc_dev, "Ethernet address %s",
    397   1.6   thorpej 	    ether_sprintf(enaddr));
    398   1.1       eeh 
    399  1.15      matt 	/* Get RX FIFO size */
    400  1.15      matt 	sc->sc_rxfifosize = 64 *
    401  1.68       jdc 	    bus_space_read_4(t, h, GEM_RX_FIFO_SIZE);
    402  1.24   thorpej 	aprint_normal(", %uKB RX fifo", sc->sc_rxfifosize / 1024);
    403  1.15      matt 
    404  1.15      matt 	/* Get TX FIFO size */
    405  1.68       jdc 	v = bus_space_read_4(t, h, GEM_TX_FIFO_SIZE);
    406  1.24   thorpej 	aprint_normal(", %uKB TX fifo\n", v / 16);
    407  1.15      matt 
    408   1.1       eeh 	/* Initialize ifnet structure. */
    409  1.76    cegger 	strlcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ);
    410   1.1       eeh 	ifp->if_softc = sc;
    411   1.1       eeh 	ifp->if_flags =
    412   1.1       eeh 	    IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST;
    413  1.41  christos 	sc->sc_if_flags = ifp->if_flags;
    414  1.73       jdc 	/*
    415  1.73       jdc 	 * The GEM hardware supports basic TCP checksum offloading only.
    416  1.73       jdc 	 * Several (all?) revisions (Sun rev. 01 and Apple rev. 00 and 80)
    417  1.73       jdc 	 * have bugs in the receive checksum, so don't enable it for now.
    418  1.73       jdc 	if ((GEM_IS_SUN(sc) && sc->sc_chiprev != 1) ||
    419  1.73       jdc 	    (GEM_IS_APPLE(sc) &&
    420  1.73       jdc 	    (sc->sc_chiprev != 0 && sc->sc_chiprev != 0x80)))
    421  1.73       jdc 		ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Rx;
    422  1.73       jdc 	*/
    423  1.73       jdc 	ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Tx;
    424   1.1       eeh 	ifp->if_start = gem_start;
    425   1.1       eeh 	ifp->if_ioctl = gem_ioctl;
    426   1.1       eeh 	ifp->if_watchdog = gem_watchdog;
    427   1.1       eeh 	ifp->if_stop = gem_stop;
    428   1.1       eeh 	ifp->if_init = gem_init;
    429   1.1       eeh 	IFQ_SET_READY(&ifp->if_snd);
    430   1.1       eeh 
    431  1.15      matt 	/*
    432  1.15      matt 	 * If we support GigE media, we support jumbo frames too.
    433  1.15      matt 	 * Unless we are Apple.
    434  1.15      matt 	 */
    435  1.69    dyoung 	TAILQ_FOREACH(ifm, &sc->sc_mii.mii_media.ifm_list, ifm_list) {
    436  1.15      matt 		if (IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_T ||
    437  1.15      matt 		    IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_SX ||
    438  1.15      matt 		    IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_LX ||
    439  1.15      matt 		    IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_CX) {
    440  1.70       jdc 			if (!GEM_IS_APPLE(sc))
    441  1.15      matt 				sc->sc_ethercom.ec_capabilities
    442  1.15      matt 				    |= ETHERCAP_JUMBO_MTU;
    443  1.15      matt 			sc->sc_flags |= GEM_GIGABIT;
    444  1.15      matt 			break;
    445  1.15      matt 		}
    446  1.15      matt 	}
    447  1.15      matt 
    448   1.1       eeh 	/* claim 802.1q capability */
    449   1.1       eeh 	sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU;
    450   1.1       eeh 
    451   1.1       eeh 	/* Attach the interface. */
    452   1.1       eeh 	if_attach(ifp);
    453   1.6   thorpej 	ether_ifattach(ifp, enaddr);
    454   1.1       eeh 
    455   1.1       eeh 	sc->sc_sh = shutdownhook_establish(gem_shutdown, sc);
    456   1.1       eeh 	if (sc->sc_sh == NULL)
    457   1.1       eeh 		panic("gem_config: can't establish shutdownhook");
    458   1.1       eeh 
    459   1.1       eeh #if NRND > 0
    460  1.76    cegger 	rnd_attach_source(&sc->rnd_source, device_xname(&sc->sc_dev),
    461   1.1       eeh 			  RND_TYPE_NET, 0);
    462   1.1       eeh #endif
    463   1.1       eeh 
    464  1.18      matt 	evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR,
    465  1.76    cegger 	    NULL, device_xname(&sc->sc_dev), "interrupts");
    466  1.19      matt #ifdef GEM_COUNTERS
    467  1.18      matt 	evcnt_attach_dynamic(&sc->sc_ev_txint, EVCNT_TYPE_INTR,
    468  1.76    cegger 	    &sc->sc_ev_intr, device_xname(&sc->sc_dev), "tx interrupts");
    469  1.18      matt 	evcnt_attach_dynamic(&sc->sc_ev_rxint, EVCNT_TYPE_INTR,
    470  1.76    cegger 	    &sc->sc_ev_intr, device_xname(&sc->sc_dev), "rx interrupts");
    471  1.18      matt 	evcnt_attach_dynamic(&sc->sc_ev_rxfull, EVCNT_TYPE_INTR,
    472  1.76    cegger 	    &sc->sc_ev_rxint, device_xname(&sc->sc_dev), "rx ring full");
    473  1.18      matt 	evcnt_attach_dynamic(&sc->sc_ev_rxnobuf, EVCNT_TYPE_INTR,
    474  1.76    cegger 	    &sc->sc_ev_rxint, device_xname(&sc->sc_dev), "rx malloc failure");
    475  1.18      matt 	evcnt_attach_dynamic(&sc->sc_ev_rxhist[0], EVCNT_TYPE_INTR,
    476  1.76    cegger 	    &sc->sc_ev_rxint, device_xname(&sc->sc_dev), "rx 0desc");
    477  1.18      matt 	evcnt_attach_dynamic(&sc->sc_ev_rxhist[1], EVCNT_TYPE_INTR,
    478  1.76    cegger 	    &sc->sc_ev_rxint, device_xname(&sc->sc_dev), "rx 1desc");
    479  1.18      matt 	evcnt_attach_dynamic(&sc->sc_ev_rxhist[2], EVCNT_TYPE_INTR,
    480  1.76    cegger 	    &sc->sc_ev_rxint, device_xname(&sc->sc_dev), "rx 2desc");
    481  1.18      matt 	evcnt_attach_dynamic(&sc->sc_ev_rxhist[3], EVCNT_TYPE_INTR,
    482  1.76    cegger 	    &sc->sc_ev_rxint, device_xname(&sc->sc_dev), "rx 3desc");
    483  1.18      matt 	evcnt_attach_dynamic(&sc->sc_ev_rxhist[4], EVCNT_TYPE_INTR,
    484  1.76    cegger 	    &sc->sc_ev_rxint, device_xname(&sc->sc_dev), "rx >3desc");
    485  1.18      matt 	evcnt_attach_dynamic(&sc->sc_ev_rxhist[5], EVCNT_TYPE_INTR,
    486  1.76    cegger 	    &sc->sc_ev_rxint, device_xname(&sc->sc_dev), "rx >7desc");
    487  1.18      matt 	evcnt_attach_dynamic(&sc->sc_ev_rxhist[6], EVCNT_TYPE_INTR,
    488  1.76    cegger 	    &sc->sc_ev_rxint, device_xname(&sc->sc_dev), "rx >15desc");
    489  1.18      matt 	evcnt_attach_dynamic(&sc->sc_ev_rxhist[7], EVCNT_TYPE_INTR,
    490  1.76    cegger 	    &sc->sc_ev_rxint, device_xname(&sc->sc_dev), "rx >31desc");
    491  1.18      matt 	evcnt_attach_dynamic(&sc->sc_ev_rxhist[8], EVCNT_TYPE_INTR,
    492  1.76    cegger 	    &sc->sc_ev_rxint, device_xname(&sc->sc_dev), "rx >63desc");
    493  1.19      matt #endif
    494   1.1       eeh 
    495   1.1       eeh #if notyet
    496   1.1       eeh 	/*
    497   1.1       eeh 	 * Add a suspend hook to make sure we come back up after a
    498   1.1       eeh 	 * resume.
    499   1.1       eeh 	 */
    500  1.76    cegger 	sc->sc_powerhook = powerhook_establish(device_xname(&sc->sc_dev),
    501  1.48  jmcneill 	    gem_power, sc);
    502   1.1       eeh 	if (sc->sc_powerhook == NULL)
    503  1.76    cegger 		aprint_error_dev(&sc->sc_dev, "WARNING: unable to establish power hook\n");
    504   1.1       eeh #endif
    505   1.1       eeh 
    506  1.57        ad 	callout_init(&sc->sc_tick_ch, 0);
    507   1.1       eeh 	return;
    508   1.1       eeh 
    509   1.1       eeh 	/*
    510   1.1       eeh 	 * Free any resources we've allocated during the failed attach
    511   1.1       eeh 	 * attempt.  Do this in reverse order and fall through.
    512   1.1       eeh 	 */
    513  1.40    bouyer  fail_7:
    514   1.1       eeh 	for (i = 0; i < GEM_NRXDESC; i++) {
    515   1.1       eeh 		if (sc->sc_rxsoft[i].rxs_dmamap != NULL)
    516   1.1       eeh 			bus_dmamap_destroy(sc->sc_dmatag,
    517   1.1       eeh 			    sc->sc_rxsoft[i].rxs_dmamap);
    518   1.1       eeh 	}
    519  1.40    bouyer  fail_6:
    520   1.1       eeh 	for (i = 0; i < GEM_TXQUEUELEN; i++) {
    521   1.1       eeh 		if (sc->sc_txsoft[i].txs_dmamap != NULL)
    522   1.1       eeh 			bus_dmamap_destroy(sc->sc_dmatag,
    523   1.1       eeh 			    sc->sc_txsoft[i].txs_dmamap);
    524   1.1       eeh 	}
    525   1.1       eeh 	bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap);
    526  1.40    bouyer  fail_5:
    527  1.40    bouyer 	bus_dmamap_destroy(sc->sc_dmatag, sc->sc_nulldmamap);
    528  1.40    bouyer  fail_4:
    529  1.53  christos 	bus_dmamem_unmap(sc->sc_dmatag, (void *)nullbuf, ETHER_MIN_TX);
    530   1.1       eeh  fail_3:
    531   1.1       eeh 	bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap);
    532   1.1       eeh  fail_2:
    533  1.53  christos 	bus_dmamem_unmap(sc->sc_dmatag, (void *)sc->sc_control_data,
    534   1.1       eeh 	    sizeof(struct gem_control_data));
    535   1.1       eeh  fail_1:
    536   1.1       eeh 	bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg);
    537   1.1       eeh  fail_0:
    538   1.1       eeh 	return;
    539   1.1       eeh }
    540   1.1       eeh 
    541   1.1       eeh 
    542   1.1       eeh void
    543   1.1       eeh gem_tick(arg)
    544   1.1       eeh 	void *arg;
    545   1.1       eeh {
    546   1.1       eeh 	struct gem_softc *sc = arg;
    547   1.1       eeh 	int s;
    548   1.1       eeh 
    549  1.68       jdc 	if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) {
    550  1.68       jdc 		/*
    551  1.68       jdc 		 * We have to reset everything if we failed to get a
    552  1.68       jdc 		 * PCS interrupt.  Restarting the callout is handled
    553  1.68       jdc 		 * in gem_pcs_start().
    554  1.68       jdc 		 */
    555  1.68       jdc 		gem_init(&sc->sc_ethercom.ec_if);
    556  1.68       jdc 	} else {
    557  1.68       jdc 		s = splnet();
    558  1.68       jdc 		mii_tick(&sc->sc_mii);
    559  1.68       jdc 		splx(s);
    560  1.68       jdc 		callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc);
    561  1.68       jdc 	}
    562   1.1       eeh }
    563   1.1       eeh 
    564  1.41  christos static int
    565  1.50    martin gem_bitwait(sc, h, r, clr, set)
    566  1.41  christos 	struct gem_softc *sc;
    567  1.50    martin 	bus_space_handle_t h;
    568  1.41  christos 	int r;
    569  1.41  christos 	u_int32_t clr;
    570  1.41  christos 	u_int32_t set;
    571  1.41  christos {
    572  1.41  christos 	int i;
    573  1.41  christos 	u_int32_t reg;
    574  1.46     blymn 
    575  1.41  christos 	for (i = TRIES; i--; DELAY(100)) {
    576  1.50    martin 		reg = bus_space_read_4(sc->sc_bustag, h, r);
    577  1.50    martin 		if ((reg & clr) == 0 && (reg & set) == set)
    578  1.41  christos 			return (1);
    579  1.41  christos 	}
    580  1.41  christos 	return (0);
    581  1.41  christos }
    582  1.41  christos 
    583   1.1       eeh void
    584   1.1       eeh gem_reset(sc)
    585   1.1       eeh 	struct gem_softc *sc;
    586   1.1       eeh {
    587   1.1       eeh 	bus_space_tag_t t = sc->sc_bustag;
    588  1.50    martin 	bus_space_handle_t h = sc->sc_h2;
    589   1.1       eeh 	int s;
    590   1.1       eeh 
    591   1.1       eeh 	s = splnet();
    592  1.76    cegger 	DPRINTF(sc, ("%s: gem_reset\n", device_xname(&sc->sc_dev)));
    593   1.1       eeh 	gem_reset_rx(sc);
    594   1.1       eeh 	gem_reset_tx(sc);
    595   1.1       eeh 
    596   1.1       eeh 	/* Do a full reset */
    597   1.1       eeh 	bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX|GEM_RESET_TX);
    598  1.50    martin 	if (!gem_bitwait(sc, h, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0))
    599  1.76    cegger 		aprint_error_dev(&sc->sc_dev, "cannot reset device\n");
    600   1.1       eeh 	splx(s);
    601   1.1       eeh }
    602   1.1       eeh 
    603   1.1       eeh 
    604   1.1       eeh /*
    605   1.1       eeh  * gem_rxdrain:
    606   1.1       eeh  *
    607   1.1       eeh  *	Drain the receive queue.
    608   1.1       eeh  */
    609  1.41  christos static void
    610   1.1       eeh gem_rxdrain(struct gem_softc *sc)
    611   1.1       eeh {
    612   1.1       eeh 	struct gem_rxsoft *rxs;
    613   1.1       eeh 	int i;
    614   1.1       eeh 
    615   1.1       eeh 	for (i = 0; i < GEM_NRXDESC; i++) {
    616   1.1       eeh 		rxs = &sc->sc_rxsoft[i];
    617   1.1       eeh 		if (rxs->rxs_mbuf != NULL) {
    618  1.41  christos 			bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0,
    619  1.41  christos 			    rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
    620   1.1       eeh 			bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap);
    621   1.1       eeh 			m_freem(rxs->rxs_mbuf);
    622   1.1       eeh 			rxs->rxs_mbuf = NULL;
    623   1.1       eeh 		}
    624   1.1       eeh 	}
    625   1.1       eeh }
    626   1.1       eeh 
    627  1.31      heas /*
    628   1.1       eeh  * Reset the whole thing.
    629   1.1       eeh  */
    630  1.41  christos static void
    631   1.1       eeh gem_stop(struct ifnet *ifp, int disable)
    632   1.1       eeh {
    633   1.1       eeh 	struct gem_softc *sc = (struct gem_softc *)ifp->if_softc;
    634   1.1       eeh 	struct gem_txsoft *txs;
    635   1.1       eeh 
    636  1.76    cegger 	DPRINTF(sc, ("%s: gem_stop\n", device_xname(&sc->sc_dev)));
    637   1.1       eeh 
    638   1.1       eeh 	callout_stop(&sc->sc_tick_ch);
    639  1.68       jdc 	if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0)
    640  1.68       jdc 		gem_pcs_stop(sc, disable);
    641  1.68       jdc 	else
    642  1.68       jdc 		mii_down(&sc->sc_mii);
    643   1.1       eeh 
    644   1.1       eeh 	/* XXX - Should we reset these instead? */
    645  1.68       jdc 	gem_disable_tx(sc);
    646   1.1       eeh 	gem_disable_rx(sc);
    647   1.1       eeh 
    648   1.1       eeh 	/*
    649   1.1       eeh 	 * Release any queued transmit buffers.
    650   1.1       eeh 	 */
    651   1.1       eeh 	while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
    652  1.21     lukem 		SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q);
    653   1.1       eeh 		if (txs->txs_mbuf != NULL) {
    654  1.41  christos 			bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 0,
    655  1.41  christos 			    txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
    656   1.1       eeh 			bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap);
    657   1.1       eeh 			m_freem(txs->txs_mbuf);
    658   1.1       eeh 			txs->txs_mbuf = NULL;
    659   1.1       eeh 		}
    660   1.1       eeh 		SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
    661   1.1       eeh 	}
    662   1.1       eeh 
    663   1.1       eeh 	/*
    664   1.1       eeh 	 * Mark the interface down and cancel the watchdog timer.
    665   1.1       eeh 	 */
    666   1.1       eeh 	ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
    667  1.41  christos 	sc->sc_if_flags = ifp->if_flags;
    668   1.1       eeh 	ifp->if_timer = 0;
    669  1.75    dyoung 
    670  1.75    dyoung 	if (disable)
    671  1.75    dyoung 		gem_rxdrain(sc);
    672   1.1       eeh }
    673   1.1       eeh 
    674   1.1       eeh 
    675   1.1       eeh /*
    676   1.1       eeh  * Reset the receiver
    677   1.1       eeh  */
    678   1.1       eeh int
    679   1.1       eeh gem_reset_rx(struct gem_softc *sc)
    680   1.1       eeh {
    681   1.1       eeh 	bus_space_tag_t t = sc->sc_bustag;
    682  1.50    martin 	bus_space_handle_t h = sc->sc_h1, h2 = sc->sc_h2;
    683   1.1       eeh 
    684   1.1       eeh 	/*
    685   1.1       eeh 	 * Resetting while DMA is in progress can cause a bus hang, so we
    686   1.1       eeh 	 * disable DMA first.
    687   1.1       eeh 	 */
    688   1.1       eeh 	gem_disable_rx(sc);
    689   1.1       eeh 	bus_space_write_4(t, h, GEM_RX_CONFIG, 0);
    690  1.68       jdc 	bus_space_barrier(t, h, GEM_RX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE);
    691   1.1       eeh 	/* Wait till it finishes */
    692  1.50    martin 	if (!gem_bitwait(sc, h, GEM_RX_CONFIG, 1, 0))
    693  1.76    cegger 		aprint_error_dev(&sc->sc_dev, "cannot disable read dma\n");
    694   1.1       eeh 
    695   1.1       eeh 	/* Finally, reset the ERX */
    696  1.50    martin 	bus_space_write_4(t, h2, GEM_RESET, GEM_RESET_RX);
    697  1.68       jdc 	bus_space_barrier(t, h, GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE);
    698   1.1       eeh 	/* Wait till it finishes */
    699  1.50    martin 	if (!gem_bitwait(sc, h2, GEM_RESET, GEM_RESET_RX, 0)) {
    700  1.76    cegger 		aprint_error_dev(&sc->sc_dev, "cannot reset receiver\n");
    701   1.1       eeh 		return (1);
    702   1.1       eeh 	}
    703   1.1       eeh 	return (0);
    704   1.1       eeh }
    705   1.1       eeh 
    706   1.1       eeh 
    707   1.1       eeh /*
    708  1.68       jdc  * Reset the receiver DMA engine.
    709  1.68       jdc  *
    710  1.68       jdc  * Intended to be used in case of GEM_INTR_RX_TAG_ERR, GEM_MAC_RX_OVERFLOW
    711  1.68       jdc  * etc in order to reset the receiver DMA engine only and not do a full
    712  1.68       jdc  * reset which amongst others also downs the link and clears the FIFOs.
    713  1.68       jdc  */
    714  1.68       jdc static void
    715  1.68       jdc gem_reset_rxdma(struct gem_softc *sc)
    716  1.68       jdc {
    717  1.68       jdc 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
    718  1.68       jdc 	bus_space_tag_t t = sc->sc_bustag;
    719  1.68       jdc 	bus_space_handle_t h = sc->sc_h1;
    720  1.68       jdc 	int i;
    721  1.68       jdc 
    722  1.68       jdc 	if (gem_reset_rx(sc) != 0) {
    723  1.68       jdc 		gem_init(ifp);
    724  1.68       jdc 		return;
    725  1.68       jdc 	}
    726  1.68       jdc 	for (i = 0; i < GEM_NRXDESC; i++)
    727  1.68       jdc 		if (sc->sc_rxsoft[i].rxs_mbuf != NULL)
    728  1.68       jdc 			GEM_UPDATE_RXDESC(sc, i);
    729  1.68       jdc 	sc->sc_rxptr = 0;
    730  1.68       jdc 	GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE);
    731  1.68       jdc 	GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD);
    732  1.68       jdc 
    733  1.68       jdc 	/* Reprogram Descriptor Ring Base Addresses */
    734  1.68       jdc 	/* NOTE: we use only 32-bit DMA addresses here. */
    735  1.68       jdc 	bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0);
    736  1.68       jdc 	bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0));
    737  1.68       jdc 
    738  1.68       jdc 	/* Redo ERX Configuration */
    739  1.68       jdc 	gem_rx_common(sc);
    740  1.68       jdc 
    741  1.68       jdc 	/* Give the reciever a swift kick */
    742  1.68       jdc 	bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC - 4);
    743  1.68       jdc }
    744  1.68       jdc 
    745  1.68       jdc /*
    746  1.68       jdc  * Common RX configuration for gem_init() and gem_reset_rxdma().
    747  1.68       jdc  */
    748  1.68       jdc static void
    749  1.68       jdc gem_rx_common(struct gem_softc *sc)
    750  1.68       jdc {
    751  1.68       jdc 	bus_space_tag_t t = sc->sc_bustag;
    752  1.68       jdc 	bus_space_handle_t h = sc->sc_h1;
    753  1.68       jdc 	u_int32_t v;
    754  1.68       jdc 
    755  1.68       jdc 	/* Encode Receive Descriptor ring size: four possible values */
    756  1.68       jdc 	v = gem_ringsize(GEM_NRXDESC /*XXX*/);
    757  1.68       jdc 
    758  1.68       jdc 	/* Set receive h/w checksum offset */
    759  1.68       jdc #ifdef INET
    760  1.68       jdc 	v |= (ETHER_HDR_LEN + sizeof(struct ip) +
    761  1.68       jdc 	    ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ?
    762  1.68       jdc 	    ETHER_VLAN_ENCAP_LEN : 0)) << GEM_RX_CONFIG_CXM_START_SHFT;
    763  1.68       jdc #endif
    764  1.68       jdc 
    765  1.68       jdc 	/* Enable RX DMA */
    766  1.68       jdc 	bus_space_write_4(t, h, GEM_RX_CONFIG,
    767  1.68       jdc 	    v | (GEM_THRSH_1024 << GEM_RX_CONFIG_FIFO_THRS_SHIFT) |
    768  1.68       jdc 	    (2 << GEM_RX_CONFIG_FBOFF_SHFT) | GEM_RX_CONFIG_RXDMA_EN);
    769  1.68       jdc 
    770  1.68       jdc 	/*
    771  1.68       jdc 	 * The following value is for an OFF Threshold of about 3/4 full
    772  1.68       jdc 	 * and an ON Threshold of 1/4 full.
    773  1.68       jdc 	 */
    774  1.68       jdc 	bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH,
    775  1.68       jdc 	    (3 * sc->sc_rxfifosize / 256) |
    776  1.68       jdc 	    ((sc->sc_rxfifosize / 256) << 12));
    777  1.68       jdc 	bus_space_write_4(t, h, GEM_RX_BLANKING,
    778  1.68       jdc 	    (6 << GEM_RX_BLANKING_TIME_SHIFT) | 6);
    779  1.68       jdc }
    780  1.68       jdc 
    781  1.68       jdc /*
    782   1.1       eeh  * Reset the transmitter
    783   1.1       eeh  */
    784   1.1       eeh int
    785   1.1       eeh gem_reset_tx(struct gem_softc *sc)
    786   1.1       eeh {
    787   1.1       eeh 	bus_space_tag_t t = sc->sc_bustag;
    788  1.50    martin 	bus_space_handle_t h = sc->sc_h1, h2 = sc->sc_h2;
    789   1.1       eeh 
    790   1.1       eeh 	/*
    791   1.1       eeh 	 * Resetting while DMA is in progress can cause a bus hang, so we
    792   1.1       eeh 	 * disable DMA first.
    793   1.1       eeh 	 */
    794   1.1       eeh 	gem_disable_tx(sc);
    795   1.1       eeh 	bus_space_write_4(t, h, GEM_TX_CONFIG, 0);
    796  1.68       jdc 	bus_space_barrier(t, h, GEM_TX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE);
    797   1.1       eeh 	/* Wait till it finishes */
    798  1.50    martin 	if (!gem_bitwait(sc, h, GEM_TX_CONFIG, 1, 0))
    799  1.76    cegger 		aprint_error_dev(&sc->sc_dev, "cannot disable read dma\n");
    800   1.1       eeh 	/* Wait 5ms extra. */
    801   1.1       eeh 	delay(5000);
    802   1.1       eeh 
    803   1.1       eeh 	/* Finally, reset the ETX */
    804  1.50    martin 	bus_space_write_4(t, h2, GEM_RESET, GEM_RESET_TX);
    805  1.68       jdc 	bus_space_barrier(t, h, GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE);
    806   1.1       eeh 	/* Wait till it finishes */
    807  1.50    martin 	if (!gem_bitwait(sc, h2, GEM_RESET, GEM_RESET_TX, 0)) {
    808  1.76    cegger 		aprint_error_dev(&sc->sc_dev, "cannot reset receiver\n");
    809   1.1       eeh 		return (1);
    810   1.1       eeh 	}
    811   1.1       eeh 	return (0);
    812   1.1       eeh }
    813   1.1       eeh 
    814   1.1       eeh /*
    815   1.1       eeh  * disable receiver.
    816   1.1       eeh  */
    817   1.1       eeh int
    818   1.1       eeh gem_disable_rx(struct gem_softc *sc)
    819   1.1       eeh {
    820   1.1       eeh 	bus_space_tag_t t = sc->sc_bustag;
    821  1.50    martin 	bus_space_handle_t h = sc->sc_h1;
    822   1.1       eeh 	u_int32_t cfg;
    823   1.1       eeh 
    824   1.1       eeh 	/* Flip the enable bit */
    825   1.1       eeh 	cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG);
    826   1.1       eeh 	cfg &= ~GEM_MAC_RX_ENABLE;
    827   1.1       eeh 	bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg);
    828  1.68       jdc 	bus_space_barrier(t, h, GEM_MAC_RX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE);
    829   1.1       eeh 	/* Wait for it to finish */
    830  1.50    martin 	return (gem_bitwait(sc, h, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0));
    831   1.1       eeh }
    832   1.1       eeh 
    833   1.1       eeh /*
    834   1.1       eeh  * disable transmitter.
    835   1.1       eeh  */
    836   1.1       eeh int
    837   1.1       eeh gem_disable_tx(struct gem_softc *sc)
    838   1.1       eeh {
    839   1.1       eeh 	bus_space_tag_t t = sc->sc_bustag;
    840  1.50    martin 	bus_space_handle_t h = sc->sc_h1;
    841   1.1       eeh 	u_int32_t cfg;
    842   1.1       eeh 
    843   1.1       eeh 	/* Flip the enable bit */
    844   1.1       eeh 	cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG);
    845   1.1       eeh 	cfg &= ~GEM_MAC_TX_ENABLE;
    846   1.1       eeh 	bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg);
    847  1.68       jdc 	bus_space_barrier(t, h, GEM_MAC_TX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE);
    848   1.1       eeh 	/* Wait for it to finish */
    849  1.50    martin 	return (gem_bitwait(sc, h, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0));
    850   1.1       eeh }
    851   1.1       eeh 
    852   1.1       eeh /*
    853   1.1       eeh  * Initialize interface.
    854   1.1       eeh  */
    855   1.1       eeh int
    856   1.1       eeh gem_meminit(struct gem_softc *sc)
    857   1.1       eeh {
    858   1.1       eeh 	struct gem_rxsoft *rxs;
    859   1.1       eeh 	int i, error;
    860   1.1       eeh 
    861   1.1       eeh 	/*
    862   1.1       eeh 	 * Initialize the transmit descriptor ring.
    863   1.1       eeh 	 */
    864   1.1       eeh 	memset((void *)sc->sc_txdescs, 0, sizeof(sc->sc_txdescs));
    865   1.1       eeh 	for (i = 0; i < GEM_NTXDESC; i++) {
    866   1.1       eeh 		sc->sc_txdescs[i].gd_flags = 0;
    867   1.1       eeh 		sc->sc_txdescs[i].gd_addr = 0;
    868   1.1       eeh 	}
    869   1.1       eeh 	GEM_CDTXSYNC(sc, 0, GEM_NTXDESC,
    870   1.1       eeh 	    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
    871  1.14      matt 	sc->sc_txfree = GEM_NTXDESC-1;
    872   1.1       eeh 	sc->sc_txnext = 0;
    873  1.14      matt 	sc->sc_txwin = 0;
    874   1.1       eeh 
    875   1.1       eeh 	/*
    876   1.1       eeh 	 * Initialize the receive descriptor and receive job
    877   1.1       eeh 	 * descriptor rings.
    878   1.1       eeh 	 */
    879   1.1       eeh 	for (i = 0; i < GEM_NRXDESC; i++) {
    880   1.1       eeh 		rxs = &sc->sc_rxsoft[i];
    881   1.1       eeh 		if (rxs->rxs_mbuf == NULL) {
    882   1.1       eeh 			if ((error = gem_add_rxbuf(sc, i)) != 0) {
    883  1.76    cegger 				aprint_error_dev(&sc->sc_dev, "unable to allocate or map rx "
    884   1.1       eeh 				    "buffer %d, error = %d\n",
    885  1.76    cegger 				    i, error);
    886   1.1       eeh 				/*
    887   1.1       eeh 				 * XXX Should attempt to run with fewer receive
    888   1.1       eeh 				 * XXX buffers instead of just failing.
    889   1.1       eeh 				 */
    890   1.1       eeh 				gem_rxdrain(sc);
    891   1.1       eeh 				return (1);
    892   1.1       eeh 			}
    893   1.1       eeh 		} else
    894   1.1       eeh 			GEM_INIT_RXDESC(sc, i);
    895   1.1       eeh 	}
    896   1.1       eeh 	sc->sc_rxptr = 0;
    897  1.68       jdc 	sc->sc_meminited = 1;
    898  1.68       jdc 	GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE);
    899  1.68       jdc 	GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD);
    900   1.1       eeh 
    901   1.1       eeh 	return (0);
    902   1.1       eeh }
    903   1.1       eeh 
    904   1.1       eeh static int
    905   1.1       eeh gem_ringsize(int sz)
    906   1.1       eeh {
    907   1.1       eeh 	switch (sz) {
    908   1.1       eeh 	case 32:
    909  1.29  christos 		return GEM_RING_SZ_32;
    910   1.1       eeh 	case 64:
    911  1.29  christos 		return GEM_RING_SZ_64;
    912   1.1       eeh 	case 128:
    913  1.29  christos 		return GEM_RING_SZ_128;
    914   1.1       eeh 	case 256:
    915  1.29  christos 		return GEM_RING_SZ_256;
    916   1.1       eeh 	case 512:
    917  1.29  christos 		return GEM_RING_SZ_512;
    918   1.1       eeh 	case 1024:
    919  1.29  christos 		return GEM_RING_SZ_1024;
    920   1.1       eeh 	case 2048:
    921  1.29  christos 		return GEM_RING_SZ_2048;
    922   1.1       eeh 	case 4096:
    923  1.29  christos 		return GEM_RING_SZ_4096;
    924   1.1       eeh 	case 8192:
    925  1.29  christos 		return GEM_RING_SZ_8192;
    926   1.1       eeh 	default:
    927  1.29  christos 		printf("gem: invalid Receive Descriptor ring size %d\n", sz);
    928  1.29  christos 		return GEM_RING_SZ_32;
    929   1.1       eeh 	}
    930   1.1       eeh }
    931   1.1       eeh 
    932  1.68       jdc 
    933  1.68       jdc /*
    934  1.68       jdc  * Start PCS
    935  1.68       jdc  */
    936  1.68       jdc void
    937  1.68       jdc gem_pcs_start(struct gem_softc *sc)
    938  1.68       jdc {
    939  1.68       jdc 	bus_space_tag_t t = sc->sc_bustag;
    940  1.68       jdc 	bus_space_handle_t h = sc->sc_h1;
    941  1.68       jdc 	uint32_t v;
    942  1.68       jdc 
    943  1.68       jdc #ifdef GEM_DEBUG
    944  1.76    cegger 	aprint_debug_dev(&sc->sc_dev, "gem_pcs_start()\n");
    945  1.68       jdc #endif
    946  1.68       jdc 
    947  1.68       jdc 	/*
    948  1.68       jdc 	 * Set up.  We must disable the MII before modifying the
    949  1.68       jdc 	 * GEM_MII_ANAR register
    950  1.68       jdc 	 */
    951  1.68       jdc 	if (sc->sc_flags & GEM_SERDES) {
    952  1.68       jdc 		bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE,
    953  1.68       jdc 		    GEM_MII_DATAPATH_SERDES);
    954  1.68       jdc 		bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL,
    955  1.68       jdc 		    GEM_MII_SLINK_LOOPBACK);
    956  1.68       jdc 	} else {
    957  1.68       jdc 		bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE,
    958  1.68       jdc 		    GEM_MII_DATAPATH_SERIAL);
    959  1.68       jdc 		bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 0);
    960  1.68       jdc 	}
    961  1.68       jdc 	bus_space_write_4(t, h, GEM_MII_CONFIG, 0);
    962  1.68       jdc 	v = bus_space_read_4(t, h, GEM_MII_ANAR);
    963  1.68       jdc 	v |= (GEM_MII_ANEG_SYM_PAUSE | GEM_MII_ANEG_ASYM_PAUSE);
    964  1.68       jdc 	if (sc->sc_mii_media == IFM_AUTO)
    965  1.68       jdc 		v |= (GEM_MII_ANEG_FUL_DUPLX | GEM_MII_ANEG_HLF_DUPLX);
    966  1.68       jdc 	else if (sc->sc_mii_media == IFM_FDX) {
    967  1.68       jdc 		v |= GEM_MII_ANEG_FUL_DUPLX;
    968  1.68       jdc 		v &= ~GEM_MII_ANEG_HLF_DUPLX;
    969  1.68       jdc 	} else if (sc->sc_mii_media == IFM_HDX) {
    970  1.68       jdc 		v &= ~GEM_MII_ANEG_FUL_DUPLX;
    971  1.68       jdc 		v |= GEM_MII_ANEG_HLF_DUPLX;
    972  1.68       jdc 	}
    973  1.68       jdc 
    974  1.68       jdc 	/* Configure link. */
    975  1.68       jdc 	bus_space_write_4(t, h, GEM_MII_ANAR, v);
    976  1.68       jdc 	bus_space_write_4(t, h, GEM_MII_CONTROL,
    977  1.68       jdc 	    GEM_MII_CONTROL_AUTONEG | GEM_MII_CONTROL_RAN);
    978  1.68       jdc 	bus_space_write_4(t, h, GEM_MII_CONFIG, GEM_MII_CONFIG_ENABLE);
    979  1.68       jdc 	gem_bitwait(sc, h, GEM_MII_STATUS, 0, GEM_MII_STATUS_ANEG_CPT);
    980  1.68       jdc 
    981  1.68       jdc 	/* Start the 10 second timer */
    982  1.68       jdc 	callout_reset(&sc->sc_tick_ch, hz * 10, gem_tick, sc);
    983  1.68       jdc }
    984  1.68       jdc 
    985  1.68       jdc /*
    986  1.68       jdc  * Stop PCS
    987  1.68       jdc  */
    988  1.68       jdc void
    989  1.68       jdc gem_pcs_stop(struct gem_softc *sc, int disable)
    990  1.68       jdc {
    991  1.68       jdc 	bus_space_tag_t t = sc->sc_bustag;
    992  1.68       jdc 	bus_space_handle_t h = sc->sc_h1;
    993  1.68       jdc 
    994  1.68       jdc #ifdef GEM_DEBUG
    995  1.76    cegger 	aprint_debug_dev(&sc->sc_dev, "gem_pcs_stop()\n");
    996  1.68       jdc #endif
    997  1.68       jdc 
    998  1.68       jdc 	/* Tell link partner that we're going away */
    999  1.68       jdc 	bus_space_write_4(t, h, GEM_MII_ANAR, GEM_MII_ANEG_RF);
   1000  1.68       jdc 
   1001  1.68       jdc 	/*
   1002  1.68       jdc 	 * Disable PCS MII.  The documentation suggests that setting
   1003  1.68       jdc 	 * GEM_MII_CONFIG_ENABLE to zero and then restarting auto-
   1004  1.68       jdc 	 * negotiation will shut down the link.  However, it appears
   1005  1.68       jdc 	 * that we also need to unset the datapath mode.
   1006  1.68       jdc 	 */
   1007  1.68       jdc 	bus_space_write_4(t, h, GEM_MII_CONFIG, 0);
   1008  1.68       jdc 	bus_space_write_4(t, h, GEM_MII_CONTROL,
   1009  1.68       jdc 	    GEM_MII_CONTROL_AUTONEG | GEM_MII_CONTROL_RAN);
   1010  1.68       jdc 	bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, GEM_MII_DATAPATH_MII);
   1011  1.68       jdc 	bus_space_write_4(t, h, GEM_MII_CONFIG, 0);
   1012  1.68       jdc 
   1013  1.68       jdc 	if (disable) {
   1014  1.68       jdc 		if (sc->sc_flags & GEM_SERDES)
   1015  1.68       jdc 			bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL,
   1016  1.68       jdc 				GEM_MII_SLINK_POWER_OFF);
   1017  1.68       jdc 		else
   1018  1.68       jdc 			bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL,
   1019  1.68       jdc 			    GEM_MII_SLINK_LOOPBACK | GEM_MII_SLINK_POWER_OFF);
   1020  1.68       jdc 	}
   1021  1.68       jdc 
   1022  1.68       jdc 	sc->sc_flags &= ~GEM_LINK;
   1023  1.68       jdc 	sc->sc_mii.mii_media_active = IFM_ETHER | IFM_NONE;
   1024  1.68       jdc 	sc->sc_mii.mii_media_status = IFM_AVALID;
   1025  1.68       jdc }
   1026  1.68       jdc 
   1027  1.68       jdc 
   1028   1.1       eeh /*
   1029   1.1       eeh  * Initialization of interface; set up initialization block
   1030   1.1       eeh  * and transmit/receive descriptor rings.
   1031   1.1       eeh  */
   1032   1.1       eeh int
   1033   1.1       eeh gem_init(struct ifnet *ifp)
   1034   1.1       eeh {
   1035   1.1       eeh 	struct gem_softc *sc = (struct gem_softc *)ifp->if_softc;
   1036   1.1       eeh 	bus_space_tag_t t = sc->sc_bustag;
   1037  1.50    martin 	bus_space_handle_t h = sc->sc_h1;
   1038  1.69    dyoung 	int rc = 0, s;
   1039  1.15      matt 	u_int max_frame_size;
   1040   1.1       eeh 	u_int32_t v;
   1041   1.1       eeh 
   1042   1.1       eeh 	s = splnet();
   1043   1.1       eeh 
   1044  1.76    cegger 	DPRINTF(sc, ("%s: gem_init: calling stop\n", device_xname(&sc->sc_dev)));
   1045   1.1       eeh 	/*
   1046   1.1       eeh 	 * Initialization sequence. The numbered steps below correspond
   1047   1.1       eeh 	 * to the sequence outlined in section 6.3.5.1 in the Ethernet
   1048   1.1       eeh 	 * Channel Engine manual (part of the PCIO manual).
   1049   1.1       eeh 	 * See also the STP2002-STQ document from Sun Microsystems.
   1050   1.1       eeh 	 */
   1051   1.1       eeh 
   1052   1.1       eeh 	/* step 1 & 2. Reset the Ethernet Channel */
   1053   1.1       eeh 	gem_stop(ifp, 0);
   1054   1.1       eeh 	gem_reset(sc);
   1055  1.76    cegger 	DPRINTF(sc, ("%s: gem_init: restarting\n", device_xname(&sc->sc_dev)));
   1056   1.1       eeh 
   1057   1.1       eeh 	/* Re-initialize the MIF */
   1058   1.1       eeh 	gem_mifinit(sc);
   1059   1.1       eeh 
   1060  1.68       jdc 	/* Set up correct datapath for non-SERDES/Serialink */
   1061  1.68       jdc 	if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0 &&
   1062  1.68       jdc 	    sc->sc_variant != GEM_SUN_ERI)
   1063  1.68       jdc 		bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE,
   1064  1.68       jdc 		    GEM_MII_DATAPATH_MII);
   1065  1.68       jdc 
   1066   1.1       eeh 	/* Call MI reset function if any */
   1067   1.1       eeh 	if (sc->sc_hwreset)
   1068   1.1       eeh 		(*sc->sc_hwreset)(sc);
   1069   1.1       eeh 
   1070   1.1       eeh 	/* step 3. Setup data structures in host memory */
   1071  1.68       jdc 	if (gem_meminit(sc) != 0)
   1072  1.68       jdc 		return 1;
   1073   1.1       eeh 
   1074   1.1       eeh 	/* step 4. TX MAC registers & counters */
   1075   1.1       eeh 	gem_init_regs(sc);
   1076  1.15      matt 	max_frame_size = max(sc->sc_ethercom.ec_if.if_mtu, ETHERMTU);
   1077  1.15      matt 	max_frame_size += ETHER_HDR_LEN + ETHER_CRC_LEN;
   1078  1.15      matt 	if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU)
   1079  1.15      matt 		max_frame_size += ETHER_VLAN_ENCAP_LEN;
   1080   1.1       eeh 	bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME,
   1081  1.15      matt 	    max_frame_size|/* burst size */(0x2000<<16));
   1082   1.1       eeh 
   1083   1.1       eeh 	/* step 5. RX MAC registers & counters */
   1084   1.1       eeh 	gem_setladrf(sc);
   1085   1.1       eeh 
   1086   1.1       eeh 	/* step 6 & 7. Program Descriptor Ring Base Addresses */
   1087   1.4   thorpej 	/* NOTE: we use only 32-bit DMA addresses here. */
   1088   1.4   thorpej 	bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 0);
   1089   1.4   thorpej 	bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0));
   1090   1.4   thorpej 
   1091   1.4   thorpej 	bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0);
   1092   1.4   thorpej 	bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0));
   1093   1.1       eeh 
   1094   1.1       eeh 	/* step 8. Global Configuration & Interrupt Mask */
   1095  1.68       jdc 	if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0)
   1096  1.68       jdc 		v = GEM_INTR_PCS;
   1097  1.68       jdc 	else
   1098  1.68       jdc 		v = GEM_INTR_MIF;
   1099   1.1       eeh 	bus_space_write_4(t, h, GEM_INTMASK,
   1100  1.68       jdc 		      ~(GEM_INTR_TX_INTME |
   1101  1.68       jdc 			GEM_INTR_TX_EMPTY |
   1102  1.68       jdc 			GEM_INTR_TX_MAC |
   1103  1.68       jdc 			GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF|
   1104  1.68       jdc 			GEM_INTR_RX_TAG_ERR | GEM_INTR_MAC_CONTROL|
   1105  1.68       jdc 			GEM_INTR_BERR | v));
   1106  1.16      matt 	bus_space_write_4(t, h, GEM_MAC_RX_MASK,
   1107  1.68       jdc 			GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT);
   1108  1.68       jdc 	bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXX */
   1109  1.68       jdc 	bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK,
   1110  1.68       jdc 	    GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME);
   1111   1.5   thorpej 
   1112   1.1       eeh 	/* step 9. ETX Configuration: use mostly default values */
   1113   1.1       eeh 
   1114  1.68       jdc 	/* Enable TX DMA */
   1115   1.1       eeh 	v = gem_ringsize(GEM_NTXDESC /*XXX*/);
   1116  1.31      heas 	bus_space_write_4(t, h, GEM_TX_CONFIG,
   1117   1.1       eeh 		v|GEM_TX_CONFIG_TXDMA_EN|
   1118  1.68       jdc 		((0x4FF<<10)&GEM_TX_CONFIG_TXFIFO_TH));
   1119   1.1       eeh 	bus_space_write_4(t, h, GEM_TX_KICK, sc->sc_txnext);
   1120   1.1       eeh 
   1121   1.1       eeh 	/* step 10. ERX Configuration */
   1122  1.68       jdc 	gem_rx_common(sc);
   1123   1.1       eeh 
   1124   1.1       eeh 	/* step 11. Configure Media */
   1125  1.69    dyoung 	if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0 &&
   1126  1.69    dyoung 	    (rc = mii_ifmedia_change(&sc->sc_mii)) != 0)
   1127  1.69    dyoung 		goto out;
   1128   1.1       eeh 
   1129   1.1       eeh 	/* step 12. RX_MAC Configuration Register */
   1130   1.1       eeh 	v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG);
   1131  1.35      heas 	v |= GEM_MAC_RX_ENABLE | GEM_MAC_RX_STRIP_CRC;
   1132   1.1       eeh 	bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v);
   1133   1.1       eeh 
   1134   1.1       eeh 	/* step 14. Issue Transmit Pending command */
   1135   1.1       eeh 
   1136   1.1       eeh 	/* Call MI initialization function if any */
   1137   1.1       eeh 	if (sc->sc_hwinit)
   1138   1.1       eeh 		(*sc->sc_hwinit)(sc);
   1139   1.1       eeh 
   1140   1.1       eeh 
   1141   1.1       eeh 	/* step 15.  Give the reciever a swift kick */
   1142   1.1       eeh 	bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4);
   1143   1.1       eeh 
   1144  1.68       jdc 	if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0)
   1145  1.68       jdc 		/* Configure PCS */
   1146  1.68       jdc 		gem_pcs_start(sc);
   1147  1.68       jdc 	else
   1148  1.68       jdc 		/* Start the one second timer. */
   1149  1.68       jdc 		callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc);
   1150   1.1       eeh 
   1151  1.68       jdc 	sc->sc_flags &= ~GEM_LINK;
   1152   1.1       eeh 	ifp->if_flags |= IFF_RUNNING;
   1153   1.1       eeh 	ifp->if_flags &= ~IFF_OACTIVE;
   1154   1.1       eeh 	ifp->if_timer = 0;
   1155  1.41  christos 	sc->sc_if_flags = ifp->if_flags;
   1156  1.69    dyoung out:
   1157   1.1       eeh 	splx(s);
   1158   1.1       eeh 
   1159   1.1       eeh 	return (0);
   1160   1.1       eeh }
   1161   1.1       eeh 
   1162   1.1       eeh void
   1163   1.1       eeh gem_init_regs(struct gem_softc *sc)
   1164   1.1       eeh {
   1165   1.1       eeh 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   1166   1.1       eeh 	bus_space_tag_t t = sc->sc_bustag;
   1167  1.50    martin 	bus_space_handle_t h = sc->sc_h1;
   1168  1.58    dyoung 	const u_char *laddr = CLLADDR(ifp->if_sadl);
   1169  1.15      matt 	u_int32_t v;
   1170   1.1       eeh 
   1171   1.1       eeh 	/* These regs are not cleared on reset */
   1172   1.1       eeh 	if (!sc->sc_inited) {
   1173   1.1       eeh 
   1174  1.68       jdc 		/* Load recommended values */
   1175  1.68       jdc 		bus_space_write_4(t, h, GEM_MAC_IPG0, 0x00);
   1176  1.68       jdc 		bus_space_write_4(t, h, GEM_MAC_IPG1, 0x08);
   1177  1.68       jdc 		bus_space_write_4(t, h, GEM_MAC_IPG2, 0x04);
   1178   1.1       eeh 
   1179   1.1       eeh 		bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN);
   1180   1.1       eeh 		/* Max frame and max burst size */
   1181   1.1       eeh 		bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME,
   1182  1.68       jdc 		    ETHER_MAX_LEN | (0x2000<<16));
   1183  1.15      matt 
   1184  1.68       jdc 		bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x07);
   1185  1.68       jdc 		bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x04);
   1186   1.1       eeh 		bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10);
   1187   1.1       eeh 		bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088);
   1188   1.1       eeh 		bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED,
   1189  1.15      matt 		    ((laddr[5]<<8)|laddr[4])&0x3ff);
   1190  1.13      matt 
   1191   1.1       eeh 		/* Secondary MAC addr set to 0:0:0:0:0:0 */
   1192   1.1       eeh 		bus_space_write_4(t, h, GEM_MAC_ADDR3, 0);
   1193   1.1       eeh 		bus_space_write_4(t, h, GEM_MAC_ADDR4, 0);
   1194   1.1       eeh 		bus_space_write_4(t, h, GEM_MAC_ADDR5, 0);
   1195  1.13      matt 
   1196  1.13      matt 		/* MAC control addr set to 01:80:c2:00:00:01 */
   1197   1.1       eeh 		bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001);
   1198   1.1       eeh 		bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200);
   1199   1.1       eeh 		bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180);
   1200   1.1       eeh 
   1201   1.1       eeh 		/* MAC filter addr set to 0:0:0:0:0:0 */
   1202   1.1       eeh 		bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0);
   1203   1.1       eeh 		bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0);
   1204   1.1       eeh 		bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0);
   1205   1.1       eeh 
   1206   1.1       eeh 		bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0);
   1207   1.1       eeh 		bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0);
   1208   1.1       eeh 
   1209   1.1       eeh 		sc->sc_inited = 1;
   1210   1.1       eeh 	}
   1211   1.1       eeh 
   1212   1.1       eeh 	/* Counters need to be zeroed */
   1213   1.1       eeh 	bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0);
   1214   1.1       eeh 	bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0);
   1215   1.1       eeh 	bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0);
   1216   1.1       eeh 	bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0);
   1217   1.1       eeh 	bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0);
   1218   1.1       eeh 	bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0);
   1219   1.1       eeh 	bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0);
   1220   1.1       eeh 	bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0);
   1221   1.1       eeh 	bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0);
   1222   1.1       eeh 	bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0);
   1223   1.1       eeh 	bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0);
   1224   1.1       eeh 
   1225  1.68       jdc 	/* Set XOFF PAUSE time. */
   1226   1.1       eeh 	bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0);
   1227  1.68       jdc 
   1228  1.68       jdc 	/*
   1229  1.68       jdc 	 * Set the internal arbitration to "infinite" bursts of the
   1230  1.68       jdc 	 * maximum length of 31 * 64 bytes so DMA transfers aren't
   1231  1.68       jdc 	 * split up in cache line size chunks. This greatly improves
   1232  1.68       jdc 	 * especially RX performance.
   1233  1.68       jdc 	 * Enable silicon bug workarounds for the Apple variants.
   1234  1.68       jdc 	 */
   1235  1.68       jdc 	bus_space_write_4(t, h, GEM_CONFIG,
   1236  1.68       jdc 	    GEM_CONFIG_TXDMA_LIMIT | GEM_CONFIG_RXDMA_LIMIT |
   1237  1.68       jdc 	    GEM_CONFIG_BURST_INF | (GEM_IS_APPLE(sc) ?
   1238  1.68       jdc 	    GEM_CONFIG_RONPAULBIT | GEM_CONFIG_BUG2FIX : 0));
   1239   1.1       eeh 
   1240   1.1       eeh 	/*
   1241   1.1       eeh 	 * Set the station address.
   1242   1.1       eeh 	 */
   1243  1.13      matt 	bus_space_write_4(t, h, GEM_MAC_ADDR0, (laddr[4]<<8)|laddr[5]);
   1244  1.13      matt 	bus_space_write_4(t, h, GEM_MAC_ADDR1, (laddr[2]<<8)|laddr[3]);
   1245  1.13      matt 	bus_space_write_4(t, h, GEM_MAC_ADDR2, (laddr[0]<<8)|laddr[1]);
   1246   1.1       eeh 
   1247  1.15      matt 	/*
   1248  1.15      matt 	 * Enable MII outputs.  Enable GMII if there is a gigabit PHY.
   1249  1.15      matt 	 */
   1250  1.70       jdc 	sc->sc_mif_config = bus_space_read_4(t, h, GEM_MIF_CONFIG);
   1251  1.15      matt 	v = GEM_MAC_XIF_TX_MII_ENA;
   1252  1.70       jdc 	if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0)  {
   1253  1.70       jdc 		if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) {
   1254  1.70       jdc 			v |= GEM_MAC_XIF_FDPLX_LED;
   1255  1.70       jdc 				if (sc->sc_flags & GEM_GIGABIT)
   1256  1.70       jdc 					v |= GEM_MAC_XIF_GMII_MODE;
   1257  1.70       jdc 		}
   1258  1.70       jdc 	} else {
   1259  1.68       jdc 		v |= GEM_MAC_XIF_GMII_MODE;
   1260  1.70       jdc 	}
   1261  1.15      matt 	bus_space_write_4(t, h, GEM_MAC_XIF_CONFIG, v);
   1262   1.1       eeh }
   1263   1.1       eeh 
   1264  1.67    dyoung #ifdef GEM_DEBUG
   1265  1.67    dyoung static void
   1266  1.67    dyoung gem_txsoft_print(const struct gem_softc *sc, int firstdesc, int lastdesc)
   1267  1.67    dyoung {
   1268  1.67    dyoung 	int i;
   1269  1.67    dyoung 
   1270  1.67    dyoung 	for (i = firstdesc;; i = GEM_NEXTTX(i)) {
   1271  1.67    dyoung 		printf("descriptor %d:\t", i);
   1272  1.67    dyoung 		printf("gd_flags:   0x%016" PRIx64 "\t",
   1273  1.67    dyoung 			GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags));
   1274  1.67    dyoung 		printf("gd_addr: 0x%016" PRIx64 "\n",
   1275  1.67    dyoung 			GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr));
   1276  1.67    dyoung 		if (i == lastdesc)
   1277  1.67    dyoung 			break;
   1278  1.67    dyoung 	}
   1279  1.67    dyoung }
   1280  1.67    dyoung #endif
   1281  1.67    dyoung 
   1282  1.41  christos static void
   1283   1.1       eeh gem_start(ifp)
   1284   1.1       eeh 	struct ifnet *ifp;
   1285   1.1       eeh {
   1286   1.1       eeh 	struct gem_softc *sc = (struct gem_softc *)ifp->if_softc;
   1287   1.1       eeh 	struct mbuf *m0, *m;
   1288  1.64    dyoung 	struct gem_txsoft *txs;
   1289   1.1       eeh 	bus_dmamap_t dmamap;
   1290  1.49    martin 	int error, firsttx, nexttx = -1, lasttx = -1, ofree, seg;
   1291  1.40    bouyer 	uint64_t flags = 0;
   1292   1.1       eeh 
   1293   1.1       eeh 	if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
   1294   1.1       eeh 		return;
   1295   1.1       eeh 
   1296   1.1       eeh 	/*
   1297   1.1       eeh 	 * Remember the previous number of free descriptors and
   1298   1.1       eeh 	 * the first descriptor we'll use.
   1299   1.1       eeh 	 */
   1300   1.1       eeh 	ofree = sc->sc_txfree;
   1301   1.1       eeh 	firsttx = sc->sc_txnext;
   1302   1.1       eeh 
   1303   1.1       eeh 	DPRINTF(sc, ("%s: gem_start: txfree %d, txnext %d\n",
   1304  1.76    cegger 	    device_xname(&sc->sc_dev), ofree, firsttx));
   1305   1.1       eeh 
   1306   1.1       eeh 	/*
   1307   1.1       eeh 	 * Loop through the send queue, setting up transmit descriptors
   1308   1.1       eeh 	 * until we drain the queue, or use up all available transmit
   1309   1.1       eeh 	 * descriptors.
   1310   1.1       eeh 	 */
   1311  1.11   thorpej 	while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL &&
   1312  1.68       jdc 	    sc->sc_txfree != 0) {
   1313   1.1       eeh 		/*
   1314   1.1       eeh 		 * Grab a packet off the queue.
   1315   1.1       eeh 		 */
   1316   1.1       eeh 		IFQ_POLL(&ifp->if_snd, m0);
   1317   1.1       eeh 		if (m0 == NULL)
   1318   1.1       eeh 			break;
   1319   1.1       eeh 		m = NULL;
   1320   1.1       eeh 
   1321   1.1       eeh 		dmamap = txs->txs_dmamap;
   1322   1.1       eeh 
   1323   1.1       eeh 		/*
   1324   1.1       eeh 		 * Load the DMA map.  If this fails, the packet either
   1325   1.1       eeh 		 * didn't fit in the alloted number of segments, or we were
   1326   1.1       eeh 		 * short on resources.  In this case, we'll copy and try
   1327   1.1       eeh 		 * again.
   1328   1.1       eeh 		 */
   1329   1.1       eeh 		if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m0,
   1330  1.40    bouyer 		      BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0 ||
   1331  1.40    bouyer 		      (m0->m_pkthdr.len < ETHER_MIN_TX &&
   1332  1.40    bouyer 		       dmamap->dm_nsegs == GEM_NTXSEGS)) {
   1333  1.15      matt 			if (m0->m_pkthdr.len > MCLBYTES) {
   1334  1.76    cegger 				aprint_error_dev(&sc->sc_dev, "unable to allocate jumbo Tx "
   1335  1.76    cegger 				    "cluster\n");
   1336  1.15      matt 				IFQ_DEQUEUE(&ifp->if_snd, m0);
   1337  1.15      matt 				m_freem(m0);
   1338  1.15      matt 				continue;
   1339  1.15      matt 			}
   1340   1.1       eeh 			MGETHDR(m, M_DONTWAIT, MT_DATA);
   1341   1.1       eeh 			if (m == NULL) {
   1342  1.76    cegger 				aprint_error_dev(&sc->sc_dev, "unable to allocate Tx mbuf\n");
   1343   1.1       eeh 				break;
   1344   1.1       eeh 			}
   1345  1.26      matt 			MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner);
   1346   1.1       eeh 			if (m0->m_pkthdr.len > MHLEN) {
   1347   1.1       eeh 				MCLGET(m, M_DONTWAIT);
   1348   1.1       eeh 				if ((m->m_flags & M_EXT) == 0) {
   1349  1.76    cegger 					aprint_error_dev(&sc->sc_dev, "unable to allocate Tx "
   1350  1.76    cegger 					    "cluster\n");
   1351   1.1       eeh 					m_freem(m);
   1352   1.1       eeh 					break;
   1353   1.1       eeh 				}
   1354   1.1       eeh 			}
   1355  1.53  christos 			m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *));
   1356   1.1       eeh 			m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len;
   1357   1.1       eeh 			error = bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap,
   1358   1.1       eeh 			    m, BUS_DMA_WRITE|BUS_DMA_NOWAIT);
   1359   1.1       eeh 			if (error) {
   1360  1.76    cegger 				aprint_error_dev(&sc->sc_dev, "unable to load Tx buffer, "
   1361  1.76    cegger 				    "error = %d\n", error);
   1362   1.1       eeh 				break;
   1363   1.1       eeh 			}
   1364   1.1       eeh 		}
   1365   1.1       eeh 
   1366   1.1       eeh 		/*
   1367   1.1       eeh 		 * Ensure we have enough descriptors free to describe
   1368  1.11   thorpej 		 * the packet.
   1369   1.1       eeh 		 */
   1370  1.40    bouyer 		if (dmamap->dm_nsegs > ((m0->m_pkthdr.len < ETHER_MIN_TX) ?
   1371  1.40    bouyer 		     (sc->sc_txfree - 1) : sc->sc_txfree)) {
   1372   1.1       eeh 			/*
   1373   1.1       eeh 			 * Not enough free descriptors to transmit this
   1374   1.1       eeh 			 * packet.  We haven't committed to anything yet,
   1375   1.1       eeh 			 * so just unload the DMA map, put the packet
   1376   1.1       eeh 			 * back on the queue, and punt.  Notify the upper
   1377   1.1       eeh 			 * layer that there are no more slots left.
   1378   1.1       eeh 			 *
   1379   1.1       eeh 			 * XXX We could allocate an mbuf and copy, but
   1380   1.1       eeh 			 * XXX it is worth it?
   1381   1.1       eeh 			 */
   1382   1.1       eeh 			ifp->if_flags |= IFF_OACTIVE;
   1383  1.41  christos 			sc->sc_if_flags = ifp->if_flags;
   1384   1.1       eeh 			bus_dmamap_unload(sc->sc_dmatag, dmamap);
   1385   1.1       eeh 			if (m != NULL)
   1386   1.1       eeh 				m_freem(m);
   1387   1.1       eeh 			break;
   1388   1.1       eeh 		}
   1389   1.1       eeh 
   1390   1.1       eeh 		IFQ_DEQUEUE(&ifp->if_snd, m0);
   1391   1.1       eeh 		if (m != NULL) {
   1392   1.1       eeh 			m_freem(m0);
   1393   1.1       eeh 			m0 = m;
   1394   1.1       eeh 		}
   1395   1.1       eeh 
   1396   1.1       eeh 		/*
   1397   1.1       eeh 		 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET.
   1398   1.1       eeh 		 */
   1399   1.1       eeh 
   1400   1.1       eeh 		/* Sync the DMA map. */
   1401   1.1       eeh 		bus_dmamap_sync(sc->sc_dmatag, dmamap, 0, dmamap->dm_mapsize,
   1402   1.1       eeh 		    BUS_DMASYNC_PREWRITE);
   1403   1.1       eeh 
   1404   1.1       eeh 		/*
   1405   1.1       eeh 		 * Initialize the transmit descriptors.
   1406   1.1       eeh 		 */
   1407   1.1       eeh 		for (nexttx = sc->sc_txnext, seg = 0;
   1408   1.1       eeh 		     seg < dmamap->dm_nsegs;
   1409   1.1       eeh 		     seg++, nexttx = GEM_NEXTTX(nexttx)) {
   1410   1.1       eeh 
   1411   1.1       eeh 			/*
   1412   1.1       eeh 			 * If this is the first descriptor we're
   1413   1.1       eeh 			 * enqueueing, set the start of packet flag,
   1414   1.1       eeh 			 * and the checksum stuff if we want the hardware
   1415   1.1       eeh 			 * to do it.
   1416   1.1       eeh 			 */
   1417   1.1       eeh 			sc->sc_txdescs[nexttx].gd_addr =
   1418   1.2       eeh 			    GEM_DMA_WRITE(sc, dmamap->dm_segs[seg].ds_addr);
   1419   1.1       eeh 			flags = dmamap->dm_segs[seg].ds_len & GEM_TD_BUFSIZE;
   1420   1.1       eeh 			if (nexttx == firsttx) {
   1421   1.1       eeh 				flags |= GEM_TD_START_OF_PACKET;
   1422  1.14      matt 				if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) {
   1423  1.14      matt 					sc->sc_txwin = 0;
   1424  1.14      matt 					flags |= GEM_TD_INTERRUPT_ME;
   1425  1.14      matt 				}
   1426  1.35      heas 
   1427  1.35      heas #ifdef INET
   1428  1.35      heas 				/* h/w checksum */
   1429  1.68       jdc 				if (ifp->if_csum_flags_tx & M_CSUM_TCPv4 &&
   1430  1.68       jdc 				    m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) {
   1431  1.35      heas 					struct ether_header *eh;
   1432  1.35      heas 					uint16_t offset, start;
   1433  1.35      heas 
   1434  1.35      heas 					eh = mtod(m0, struct ether_header *);
   1435  1.35      heas 					switch (ntohs(eh->ether_type)) {
   1436  1.35      heas 					case ETHERTYPE_IP:
   1437  1.35      heas 						start = ETHER_HDR_LEN;
   1438  1.35      heas 						break;
   1439  1.35      heas 					case ETHERTYPE_VLAN:
   1440  1.35      heas 						start = ETHER_HDR_LEN +
   1441  1.35      heas 							ETHER_VLAN_ENCAP_LEN;
   1442  1.37     perry 						break;
   1443  1.35      heas 					default:
   1444  1.37     perry 						/* unsupported, drop it */
   1445  1.35      heas 						m_free(m0);
   1446  1.35      heas 						continue;
   1447  1.35      heas 					}
   1448  1.36   thorpej 					start += M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data);
   1449  1.36   thorpej 					offset = M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data) + start;
   1450  1.35      heas 					flags |= (start <<
   1451  1.35      heas 						  GEM_TD_CXSUM_STARTSHFT) |
   1452  1.35      heas 						 (offset <<
   1453  1.35      heas 						  GEM_TD_CXSUM_STUFFSHFT) |
   1454  1.35      heas 						 GEM_TD_CXSUM_ENABLE;
   1455  1.35      heas 				}
   1456  1.35      heas #endif
   1457   1.1       eeh 			}
   1458   1.1       eeh 			if (seg == dmamap->dm_nsegs - 1) {
   1459   1.1       eeh 				flags |= GEM_TD_END_OF_PACKET;
   1460  1.40    bouyer 			} else {
   1461  1.40    bouyer 				/* last flag set outside of loop */
   1462  1.40    bouyer 				sc->sc_txdescs[nexttx].gd_flags =
   1463  1.40    bouyer 					GEM_DMA_WRITE(sc, flags);
   1464   1.1       eeh 			}
   1465   1.1       eeh 			lasttx = nexttx;
   1466   1.1       eeh 		}
   1467  1.40    bouyer 		if (m0->m_pkthdr.len < ETHER_MIN_TX) {
   1468  1.40    bouyer 			/* add padding buffer at end of chain */
   1469  1.40    bouyer 			flags &= ~GEM_TD_END_OF_PACKET;
   1470  1.40    bouyer 			sc->sc_txdescs[lasttx].gd_flags =
   1471  1.40    bouyer 			    GEM_DMA_WRITE(sc, flags);
   1472  1.40    bouyer 
   1473  1.40    bouyer 			sc->sc_txdescs[nexttx].gd_addr =
   1474  1.40    bouyer 			    GEM_DMA_WRITE(sc,
   1475  1.40    bouyer 			    sc->sc_nulldmamap->dm_segs[0].ds_addr);
   1476  1.40    bouyer 			flags = ((ETHER_MIN_TX - m0->m_pkthdr.len) &
   1477  1.40    bouyer 			    GEM_TD_BUFSIZE) | GEM_TD_END_OF_PACKET;
   1478  1.40    bouyer 			lasttx = nexttx;
   1479  1.40    bouyer 			nexttx = GEM_NEXTTX(nexttx);
   1480  1.40    bouyer 			seg++;
   1481  1.40    bouyer 		}
   1482  1.40    bouyer 		sc->sc_txdescs[lasttx].gd_flags = GEM_DMA_WRITE(sc, flags);
   1483  1.30  christos 
   1484  1.30  christos 		KASSERT(lasttx != -1);
   1485   1.1       eeh 
   1486  1.40    bouyer 		/*
   1487  1.40    bouyer 		 * Store a pointer to the packet so we can free it later,
   1488  1.40    bouyer 		 * and remember what txdirty will be once the packet is
   1489  1.40    bouyer 		 * done.
   1490  1.40    bouyer 		 */
   1491  1.40    bouyer 		txs->txs_mbuf = m0;
   1492  1.40    bouyer 		txs->txs_firstdesc = sc->sc_txnext;
   1493  1.40    bouyer 		txs->txs_lastdesc = lasttx;
   1494  1.40    bouyer 		txs->txs_ndescs = seg;
   1495  1.40    bouyer 
   1496   1.1       eeh #ifdef GEM_DEBUG
   1497   1.1       eeh 		if (ifp->if_flags & IFF_DEBUG) {
   1498   1.1       eeh 			printf("     gem_start %p transmit chain:\n", txs);
   1499  1.67    dyoung 			gem_txsoft_print(sc, txs->txs_firstdesc,
   1500  1.67    dyoung 			    txs->txs_lastdesc);
   1501   1.1       eeh 		}
   1502   1.1       eeh #endif
   1503   1.1       eeh 
   1504   1.1       eeh 		/* Sync the descriptors we're using. */
   1505  1.65    dyoung 		GEM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndescs,
   1506   1.1       eeh 		    BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
   1507   1.1       eeh 
   1508   1.1       eeh 		/* Advance the tx pointer. */
   1509  1.40    bouyer 		sc->sc_txfree -= txs->txs_ndescs;
   1510   1.1       eeh 		sc->sc_txnext = nexttx;
   1511   1.1       eeh 
   1512  1.21     lukem 		SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q);
   1513   1.1       eeh 		SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q);
   1514   1.1       eeh 
   1515   1.1       eeh #if NBPFILTER > 0
   1516   1.1       eeh 		/*
   1517   1.1       eeh 		 * Pass the packet to any BPF listeners.
   1518   1.1       eeh 		 */
   1519   1.1       eeh 		if (ifp->if_bpf)
   1520   1.1       eeh 			bpf_mtap(ifp->if_bpf, m0);
   1521   1.1       eeh #endif /* NBPFILTER > 0 */
   1522   1.1       eeh 	}
   1523   1.1       eeh 
   1524   1.1       eeh 	if (txs == NULL || sc->sc_txfree == 0) {
   1525   1.1       eeh 		/* No more slots left; notify upper layer. */
   1526   1.1       eeh 		ifp->if_flags |= IFF_OACTIVE;
   1527  1.41  christos 		sc->sc_if_flags = ifp->if_flags;
   1528   1.1       eeh 	}
   1529   1.1       eeh 
   1530   1.1       eeh 	if (sc->sc_txfree != ofree) {
   1531   1.1       eeh 		DPRINTF(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n",
   1532  1.76    cegger 		    device_xname(&sc->sc_dev), lasttx, firsttx));
   1533   1.1       eeh 		/*
   1534  1.31      heas 		 * The entire packet chain is set up.
   1535   1.1       eeh 		 * Kick the transmitter.
   1536   1.1       eeh 		 */
   1537   1.1       eeh 		DPRINTF(sc, ("%s: gem_start: kicking tx %d\n",
   1538  1.76    cegger 			device_xname(&sc->sc_dev), nexttx));
   1539  1.50    martin 		bus_space_write_4(sc->sc_bustag, sc->sc_h1, GEM_TX_KICK,
   1540   1.1       eeh 			sc->sc_txnext);
   1541   1.1       eeh 
   1542   1.1       eeh 		/* Set a watchdog timer in case the chip flakes out. */
   1543   1.1       eeh 		ifp->if_timer = 5;
   1544   1.1       eeh 		DPRINTF(sc, ("%s: gem_start: watchdog %d\n",
   1545  1.76    cegger 			device_xname(&sc->sc_dev), ifp->if_timer));
   1546   1.1       eeh 	}
   1547   1.1       eeh }
   1548   1.1       eeh 
   1549   1.1       eeh /*
   1550   1.1       eeh  * Transmit interrupt.
   1551   1.1       eeh  */
   1552   1.1       eeh int
   1553   1.1       eeh gem_tint(sc)
   1554   1.1       eeh 	struct gem_softc *sc;
   1555   1.1       eeh {
   1556   1.1       eeh 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   1557   1.1       eeh 	bus_space_tag_t t = sc->sc_bustag;
   1558  1.50    martin 	bus_space_handle_t mac = sc->sc_h1;
   1559   1.1       eeh 	struct gem_txsoft *txs;
   1560   1.1       eeh 	int txlast;
   1561  1.14      matt 	int progress = 0;
   1562  1.71       jdc 	u_int32_t v;
   1563   1.1       eeh 
   1564  1.76    cegger 	DPRINTF(sc, ("%s: gem_tint\n", device_xname(&sc->sc_dev)));
   1565   1.1       eeh 
   1566  1.71       jdc 	/* Unload collision counters ... */
   1567  1.71       jdc 	v = bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) +
   1568  1.71       jdc 	    bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT);
   1569  1.71       jdc 	ifp->if_collisions += v +
   1570  1.71       jdc 	    bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) +
   1571  1.71       jdc 	    bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT);
   1572  1.71       jdc 	ifp->if_oerrors += v;
   1573   1.1       eeh 
   1574  1.71       jdc 	/* ... then clear the hardware counters. */
   1575   1.1       eeh 	bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0);
   1576   1.1       eeh 	bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0);
   1577   1.1       eeh 	bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0);
   1578   1.1       eeh 	bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0);
   1579   1.1       eeh 
   1580   1.1       eeh 	/*
   1581   1.1       eeh 	 * Go through our Tx list and free mbufs for those
   1582   1.1       eeh 	 * frames that have been transmitted.
   1583   1.1       eeh 	 */
   1584   1.1       eeh 	while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
   1585   1.1       eeh 		/*
   1586  1.68       jdc 		 * In theory, we could harvest some descriptors before
   1587   1.1       eeh 		 * the ring is empty, but that's a bit complicated.
   1588   1.1       eeh 		 *
   1589   1.1       eeh 		 * GEM_TX_COMPLETION points to the last descriptor
   1590   1.1       eeh 		 * processed +1.
   1591  1.62    dyoung 		 *
   1592  1.62    dyoung 		 * Let's assume that the NIC writes back to the Tx
   1593  1.62    dyoung 		 * descriptors before it updates the completion
   1594  1.62    dyoung 		 * register.  If the NIC has posted writes to the
   1595  1.62    dyoung 		 * Tx descriptors, PCI ordering requires that the
   1596  1.62    dyoung 		 * posted writes flush to RAM before the register-read
   1597  1.62    dyoung 		 * finishes.  So let's read the completion register,
   1598  1.62    dyoung 		 * before syncing the descriptors, so that we
   1599  1.62    dyoung 		 * examine Tx descriptors that are at least as
   1600  1.62    dyoung 		 * current as the completion register.
   1601   1.1       eeh 		 */
   1602   1.1       eeh 		txlast = bus_space_read_4(t, mac, GEM_TX_COMPLETION);
   1603   1.1       eeh 		DPRINTF(sc,
   1604   1.1       eeh 			("gem_tint: txs->txs_lastdesc = %d, txlast = %d\n",
   1605   1.1       eeh 				txs->txs_lastdesc, txlast));
   1606   1.1       eeh 		if (txs->txs_firstdesc <= txs->txs_lastdesc) {
   1607  1.63    dyoung 			if (txlast >= txs->txs_firstdesc &&
   1608  1.63    dyoung 			    txlast <= txs->txs_lastdesc)
   1609   1.1       eeh 				break;
   1610  1.63    dyoung 		} else if (txlast >= txs->txs_firstdesc ||
   1611  1.68       jdc 			   txlast <= txs->txs_lastdesc)
   1612  1.63    dyoung 			break;
   1613   1.1       eeh 
   1614  1.66    dyoung 		GEM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndescs,
   1615  1.62    dyoung 		    BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
   1616  1.62    dyoung 
   1617  1.62    dyoung #ifdef GEM_DEBUG	/* XXX DMA synchronization? */
   1618  1.62    dyoung 		if (ifp->if_flags & IFF_DEBUG) {
   1619  1.62    dyoung 			printf("    txsoft %p transmit chain:\n", txs);
   1620  1.67    dyoung 			gem_txsoft_print(sc, txs->txs_firstdesc,
   1621  1.67    dyoung 			    txs->txs_lastdesc);
   1622  1.62    dyoung 		}
   1623  1.62    dyoung #endif
   1624  1.62    dyoung 
   1625  1.62    dyoung 
   1626   1.1       eeh 		DPRINTF(sc, ("gem_tint: releasing a desc\n"));
   1627  1.21     lukem 		SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q);
   1628   1.1       eeh 
   1629   1.1       eeh 		sc->sc_txfree += txs->txs_ndescs;
   1630   1.1       eeh 
   1631   1.1       eeh 		bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap,
   1632   1.1       eeh 		    0, txs->txs_dmamap->dm_mapsize,
   1633   1.1       eeh 		    BUS_DMASYNC_POSTWRITE);
   1634   1.1       eeh 		bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap);
   1635  1.68       jdc 		if (txs->txs_mbuf != NULL) {
   1636  1.68       jdc 			m_freem(txs->txs_mbuf);
   1637  1.68       jdc 			txs->txs_mbuf = NULL;
   1638  1.68       jdc 		}
   1639   1.1       eeh 
   1640   1.1       eeh 		SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
   1641   1.1       eeh 
   1642   1.1       eeh 		ifp->if_opackets++;
   1643  1.14      matt 		progress = 1;
   1644   1.1       eeh 	}
   1645   1.1       eeh 
   1646  1.28       chs #if 0
   1647   1.1       eeh 	DPRINTF(sc, ("gem_tint: GEM_TX_STATE_MACHINE %x "
   1648  1.55    dyoung 		"GEM_TX_DATA_PTR %" PRIx64 "GEM_TX_COMPLETION %" PRIx32 "\n",
   1649  1.50    martin 		bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_TX_STATE_MACHINE),
   1650  1.55    dyoung 		((uint64_t)bus_space_read_4(sc->sc_bustag, sc->sc_h1,
   1651   1.4   thorpej 			GEM_TX_DATA_PTR_HI) << 32) |
   1652  1.50    martin 			     bus_space_read_4(sc->sc_bustag, sc->sc_h1,
   1653   1.4   thorpej 			GEM_TX_DATA_PTR_LO),
   1654  1.50    martin 		bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_TX_COMPLETION)));
   1655  1.28       chs #endif
   1656   1.1       eeh 
   1657  1.14      matt 	if (progress) {
   1658  1.14      matt 		if (sc->sc_txfree == GEM_NTXDESC - 1)
   1659  1.14      matt 			sc->sc_txwin = 0;
   1660  1.14      matt 
   1661  1.68       jdc 		/* Freed some descriptors, so reset IFF_OACTIVE and restart. */
   1662  1.14      matt 		ifp->if_flags &= ~IFF_OACTIVE;
   1663  1.41  christos 		sc->sc_if_flags = ifp->if_flags;
   1664  1.68       jdc 		ifp->if_timer = SIMPLEQ_EMPTY(&sc->sc_txdirtyq) ? 0 : 5;
   1665  1.14      matt 		gem_start(ifp);
   1666  1.14      matt 	}
   1667   1.1       eeh 	DPRINTF(sc, ("%s: gem_tint: watchdog %d\n",
   1668  1.76    cegger 		device_xname(&sc->sc_dev), ifp->if_timer));
   1669   1.1       eeh 
   1670   1.1       eeh 	return (1);
   1671   1.1       eeh }
   1672   1.1       eeh 
   1673   1.1       eeh /*
   1674   1.1       eeh  * Receive interrupt.
   1675   1.1       eeh  */
   1676   1.1       eeh int
   1677   1.1       eeh gem_rint(sc)
   1678   1.1       eeh 	struct gem_softc *sc;
   1679   1.1       eeh {
   1680   1.1       eeh 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   1681   1.1       eeh 	bus_space_tag_t t = sc->sc_bustag;
   1682  1.50    martin 	bus_space_handle_t h = sc->sc_h1;
   1683   1.1       eeh 	struct gem_rxsoft *rxs;
   1684   1.1       eeh 	struct mbuf *m;
   1685   1.1       eeh 	u_int64_t rxstat;
   1686  1.18      matt 	u_int32_t rxcomp;
   1687  1.18      matt 	int i, len, progress = 0;
   1688   1.1       eeh 
   1689  1.76    cegger 	DPRINTF(sc, ("%s: gem_rint\n", device_xname(&sc->sc_dev)));
   1690  1.18      matt 
   1691  1.18      matt 	/*
   1692  1.68       jdc 	 * Ignore spurious interrupt that sometimes occurs before
   1693  1.68       jdc 	 * we are set up when we network boot.
   1694  1.68       jdc 	 */
   1695  1.68       jdc 	if (!sc->sc_meminited)
   1696  1.68       jdc 		return 1;
   1697  1.68       jdc 
   1698  1.68       jdc 	/*
   1699  1.18      matt 	 * Read the completion register once.  This limits
   1700  1.18      matt 	 * how long the following loop can execute.
   1701  1.18      matt 	 */
   1702  1.18      matt 	rxcomp = bus_space_read_4(t, h, GEM_RX_COMPLETION);
   1703  1.18      matt 
   1704   1.1       eeh 	/*
   1705  1.68       jdc 	 * XXX Read the lastrx only once at the top for speed.
   1706   1.1       eeh 	 */
   1707   1.1       eeh 	DPRINTF(sc, ("gem_rint: sc->rxptr %d, complete %d\n",
   1708  1.18      matt 		sc->sc_rxptr, rxcomp));
   1709  1.18      matt 
   1710  1.18      matt 	/*
   1711  1.18      matt 	 * Go into the loop at least once.
   1712  1.18      matt 	 */
   1713  1.18      matt 	for (i = sc->sc_rxptr; i == sc->sc_rxptr || i != rxcomp;
   1714   1.1       eeh 	     i = GEM_NEXTRX(i)) {
   1715   1.1       eeh 		rxs = &sc->sc_rxsoft[i];
   1716   1.1       eeh 
   1717   1.1       eeh 		GEM_CDRXSYNC(sc, i,
   1718   1.1       eeh 		    BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
   1719   1.1       eeh 
   1720   1.2       eeh 		rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags);
   1721   1.1       eeh 
   1722   1.1       eeh 		if (rxstat & GEM_RD_OWN) {
   1723  1.56    dyoung 			GEM_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD);
   1724   1.1       eeh 			/*
   1725   1.1       eeh 			 * We have processed all of the receive buffers.
   1726   1.1       eeh 			 */
   1727   1.1       eeh 			break;
   1728   1.1       eeh 		}
   1729   1.1       eeh 
   1730  1.18      matt 		progress++;
   1731  1.18      matt 		ifp->if_ipackets++;
   1732  1.18      matt 
   1733   1.1       eeh 		if (rxstat & GEM_RD_BAD_CRC) {
   1734  1.18      matt 			ifp->if_ierrors++;
   1735  1.76    cegger 			aprint_error_dev(&sc->sc_dev, "receive error: CRC error\n");
   1736   1.1       eeh 			GEM_INIT_RXDESC(sc, i);
   1737   1.1       eeh 			continue;
   1738   1.1       eeh 		}
   1739   1.1       eeh 
   1740   1.1       eeh 		bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0,
   1741   1.1       eeh 		    rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
   1742   1.1       eeh #ifdef GEM_DEBUG
   1743   1.1       eeh 		if (ifp->if_flags & IFF_DEBUG) {
   1744   1.1       eeh 			printf("    rxsoft %p descriptor %d: ", rxs, i);
   1745   1.1       eeh 			printf("gd_flags: 0x%016llx\t", (long long)
   1746   1.2       eeh 				GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags));
   1747   1.1       eeh 			printf("gd_addr: 0x%016llx\n", (long long)
   1748   1.2       eeh 				GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr));
   1749   1.1       eeh 		}
   1750   1.1       eeh #endif
   1751   1.1       eeh 
   1752  1.35      heas 		/* No errors; receive the packet. */
   1753  1.35      heas 		len = GEM_RD_BUFLEN(rxstat);
   1754   1.1       eeh 
   1755   1.1       eeh 		/*
   1756   1.1       eeh 		 * Allocate a new mbuf cluster.  If that fails, we are
   1757   1.1       eeh 		 * out of memory, and must drop the packet and recycle
   1758   1.1       eeh 		 * the buffer that's already attached to this descriptor.
   1759   1.1       eeh 		 */
   1760   1.1       eeh 		m = rxs->rxs_mbuf;
   1761   1.1       eeh 		if (gem_add_rxbuf(sc, i) != 0) {
   1762  1.19      matt 			GEM_COUNTER_INCR(sc, sc_ev_rxnobuf);
   1763   1.1       eeh 			ifp->if_ierrors++;
   1764   1.1       eeh 			GEM_INIT_RXDESC(sc, i);
   1765   1.1       eeh 			bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0,
   1766   1.1       eeh 			    rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
   1767   1.1       eeh 			continue;
   1768   1.1       eeh 		}
   1769   1.1       eeh 		m->m_data += 2; /* We're already off by two */
   1770   1.1       eeh 
   1771   1.1       eeh 		m->m_pkthdr.rcvif = ifp;
   1772   1.1       eeh 		m->m_pkthdr.len = m->m_len = len;
   1773   1.1       eeh 
   1774   1.1       eeh #if NBPFILTER > 0
   1775   1.1       eeh 		/*
   1776   1.1       eeh 		 * Pass this up to any BPF listeners, but only
   1777  1.61   tsutsui 		 * pass it up the stack if it's for us.
   1778   1.1       eeh 		 */
   1779   1.1       eeh 		if (ifp->if_bpf)
   1780   1.1       eeh 			bpf_mtap(ifp->if_bpf, m);
   1781  1.59       scw #endif /* NBPFILTER > 0 */
   1782   1.1       eeh 
   1783  1.35      heas #ifdef INET
   1784  1.35      heas 		/* hardware checksum */
   1785  1.68       jdc 		if (ifp->if_csum_flags_rx & M_CSUM_TCPv4) {
   1786  1.35      heas 			struct ether_header *eh;
   1787  1.35      heas 			struct ip *ip;
   1788  1.35      heas 			int32_t hlen, pktlen;
   1789  1.35      heas 
   1790  1.35      heas 			if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) {
   1791  1.35      heas 				pktlen = m->m_pkthdr.len - ETHER_HDR_LEN -
   1792  1.35      heas 					 ETHER_VLAN_ENCAP_LEN;
   1793  1.72       jdc 				eh = (struct ether_header *) (mtod(m, char *) +
   1794  1.72       jdc 					ETHER_VLAN_ENCAP_LEN);
   1795  1.35      heas 			} else {
   1796  1.35      heas 				pktlen = m->m_pkthdr.len - ETHER_HDR_LEN;
   1797  1.35      heas 				eh = mtod(m, struct ether_header *);
   1798  1.35      heas 			}
   1799  1.35      heas 			if (ntohs(eh->ether_type) != ETHERTYPE_IP)
   1800  1.35      heas 				goto swcsum;
   1801  1.54  christos 			ip = (struct ip *) ((char *)eh + ETHER_HDR_LEN);
   1802  1.35      heas 
   1803  1.35      heas 			/* IPv4 only */
   1804  1.35      heas 			if (ip->ip_v != IPVERSION)
   1805  1.35      heas 				goto swcsum;
   1806  1.35      heas 
   1807  1.35      heas 			hlen = ip->ip_hl << 2;
   1808  1.35      heas 			if (hlen < sizeof(struct ip))
   1809  1.35      heas 				goto swcsum;
   1810  1.35      heas 
   1811  1.38      heas 			/*
   1812  1.38      heas 			 * bail if too short, has random trailing garbage,
   1813  1.38      heas 			 * truncated, fragment, or has ethernet pad.
   1814  1.38      heas 			 */
   1815  1.35      heas 			if ((ntohs(ip->ip_len) < hlen) ||
   1816  1.38      heas 			    (ntohs(ip->ip_len) != pktlen) ||
   1817  1.35      heas 			    (ntohs(ip->ip_off) & (IP_MF | IP_OFFMASK)))
   1818  1.35      heas 				goto swcsum;
   1819  1.35      heas 
   1820  1.35      heas 			switch (ip->ip_p) {
   1821  1.35      heas 			case IPPROTO_TCP:
   1822  1.35      heas 				if (! (ifp->if_csum_flags_rx & M_CSUM_TCPv4))
   1823  1.35      heas 					goto swcsum;
   1824  1.35      heas 				if (pktlen < (hlen + sizeof(struct tcphdr)))
   1825  1.35      heas 					goto swcsum;
   1826  1.35      heas 				m->m_pkthdr.csum_flags = M_CSUM_TCPv4;
   1827  1.35      heas 				break;
   1828  1.35      heas 			case IPPROTO_UDP:
   1829  1.68       jdc 				/* FALLTHROUGH */
   1830  1.35      heas 			default:
   1831  1.35      heas 				goto swcsum;
   1832  1.35      heas 			}
   1833  1.35      heas 
   1834  1.35      heas 			/* the uncomplemented sum is expected */
   1835  1.35      heas 			m->m_pkthdr.csum_data = (~rxstat) & GEM_RD_CHECKSUM;
   1836  1.35      heas 
   1837  1.35      heas 			/* if the pkt had ip options, we have to deduct them */
   1838  1.35      heas 			if (hlen > sizeof(struct ip)) {
   1839  1.35      heas 				uint16_t *opts;
   1840  1.35      heas 				uint32_t optsum, temp;
   1841  1.35      heas 
   1842  1.35      heas 				optsum = 0;
   1843  1.35      heas 				temp = hlen - sizeof(struct ip);
   1844  1.54  christos 				opts = (uint16_t *) ((char *) ip +
   1845  1.35      heas 					sizeof(struct ip));
   1846  1.35      heas 
   1847  1.35      heas 				while (temp > 1) {
   1848  1.35      heas 					optsum += ntohs(*opts++);
   1849  1.35      heas 					temp -= 2;
   1850  1.35      heas 				}
   1851  1.35      heas 				while (optsum >> 16)
   1852  1.35      heas 					optsum = (optsum >> 16) +
   1853  1.35      heas 						 (optsum & 0xffff);
   1854  1.35      heas 
   1855  1.35      heas 				/* Deduct ip opts sum from hwsum (rfc 1624). */
   1856  1.35      heas 				m->m_pkthdr.csum_data =
   1857  1.35      heas 					~((~m->m_pkthdr.csum_data) - ~optsum);
   1858  1.35      heas 
   1859  1.35      heas 				while (m->m_pkthdr.csum_data >> 16)
   1860  1.35      heas 					m->m_pkthdr.csum_data =
   1861  1.35      heas 						(m->m_pkthdr.csum_data >> 16) +
   1862  1.35      heas 						(m->m_pkthdr.csum_data &
   1863  1.35      heas 						 0xffff);
   1864  1.35      heas 			}
   1865  1.35      heas 
   1866  1.35      heas 			m->m_pkthdr.csum_flags |= M_CSUM_DATA |
   1867  1.35      heas 						  M_CSUM_NO_PSEUDOHDR;
   1868  1.35      heas 		} else
   1869  1.35      heas swcsum:
   1870  1.35      heas 			m->m_pkthdr.csum_flags = 0;
   1871  1.35      heas #endif
   1872   1.1       eeh 		/* Pass it on. */
   1873   1.1       eeh 		(*ifp->if_input)(ifp, m);
   1874   1.1       eeh 	}
   1875   1.1       eeh 
   1876  1.18      matt 	if (progress) {
   1877  1.18      matt 		/* Update the receive pointer. */
   1878  1.18      matt 		if (i == sc->sc_rxptr) {
   1879  1.19      matt 			GEM_COUNTER_INCR(sc, sc_ev_rxfull);
   1880  1.19      matt #ifdef GEM_DEBUG
   1881  1.28       chs 			if (ifp->if_flags & IFF_DEBUG)
   1882  1.19      matt 				printf("%s: rint: ring wrap\n",
   1883  1.76    cegger 				    device_xname(&sc->sc_dev));
   1884  1.19      matt #endif
   1885  1.18      matt 		}
   1886  1.18      matt 		sc->sc_rxptr = i;
   1887  1.18      matt 		bus_space_write_4(t, h, GEM_RX_KICK, GEM_PREVRX(i));
   1888  1.18      matt 	}
   1889  1.19      matt #ifdef GEM_COUNTERS
   1890  1.18      matt 	if (progress <= 4) {
   1891  1.19      matt 		GEM_COUNTER_INCR(sc, sc_ev_rxhist[progress]);
   1892  1.28       chs 	} else if (progress < 32) {
   1893  1.18      matt 		if (progress < 16)
   1894  1.19      matt 			GEM_COUNTER_INCR(sc, sc_ev_rxhist[5]);
   1895  1.18      matt 		else
   1896  1.19      matt 			GEM_COUNTER_INCR(sc, sc_ev_rxhist[6]);
   1897  1.31      heas 
   1898  1.18      matt 	} else {
   1899  1.18      matt 		if (progress < 64)
   1900  1.19      matt 			GEM_COUNTER_INCR(sc, sc_ev_rxhist[7]);
   1901  1.18      matt 		else
   1902  1.19      matt 			GEM_COUNTER_INCR(sc, sc_ev_rxhist[8]);
   1903  1.18      matt 	}
   1904  1.19      matt #endif
   1905   1.1       eeh 
   1906   1.1       eeh 	DPRINTF(sc, ("gem_rint: done sc->rxptr %d, complete %d\n",
   1907   1.1       eeh 		sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION)));
   1908   1.1       eeh 
   1909  1.71       jdc 	/* Read error counters ... */
   1910  1.71       jdc 	ifp->if_ierrors +=
   1911  1.71       jdc 	    bus_space_read_4(t, h, GEM_MAC_RX_LEN_ERR_CNT) +
   1912  1.71       jdc 	    bus_space_read_4(t, h, GEM_MAC_RX_ALIGN_ERR) +
   1913  1.71       jdc 	    bus_space_read_4(t, h, GEM_MAC_RX_CRC_ERR_CNT) +
   1914  1.71       jdc 	    bus_space_read_4(t, h, GEM_MAC_RX_CODE_VIOL);
   1915  1.71       jdc 
   1916  1.71       jdc 	/* ... then clear the hardware counters. */
   1917  1.71       jdc 	bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0);
   1918  1.71       jdc 	bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0);
   1919  1.71       jdc 	bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0);
   1920  1.71       jdc 	bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0);
   1921  1.71       jdc 
   1922   1.1       eeh 	return (1);
   1923   1.1       eeh }
   1924   1.1       eeh 
   1925   1.1       eeh 
   1926   1.1       eeh /*
   1927   1.1       eeh  * gem_add_rxbuf:
   1928   1.1       eeh  *
   1929   1.1       eeh  *	Add a receive buffer to the indicated descriptor.
   1930   1.1       eeh  */
   1931   1.1       eeh int
   1932   1.1       eeh gem_add_rxbuf(struct gem_softc *sc, int idx)
   1933   1.1       eeh {
   1934   1.1       eeh 	struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx];
   1935   1.1       eeh 	struct mbuf *m;
   1936   1.1       eeh 	int error;
   1937   1.1       eeh 
   1938   1.1       eeh 	MGETHDR(m, M_DONTWAIT, MT_DATA);
   1939   1.1       eeh 	if (m == NULL)
   1940   1.1       eeh 		return (ENOBUFS);
   1941   1.1       eeh 
   1942  1.26      matt 	MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner);
   1943   1.1       eeh 	MCLGET(m, M_DONTWAIT);
   1944   1.1       eeh 	if ((m->m_flags & M_EXT) == 0) {
   1945   1.1       eeh 		m_freem(m);
   1946   1.1       eeh 		return (ENOBUFS);
   1947   1.1       eeh 	}
   1948   1.1       eeh 
   1949   1.1       eeh #ifdef GEM_DEBUG
   1950  1.27       wiz /* bzero the packet to check DMA */
   1951   1.1       eeh 	memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size);
   1952   1.1       eeh #endif
   1953   1.1       eeh 
   1954   1.1       eeh 	if (rxs->rxs_mbuf != NULL)
   1955   1.1       eeh 		bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap);
   1956   1.1       eeh 
   1957   1.1       eeh 	rxs->rxs_mbuf = m;
   1958   1.1       eeh 
   1959   1.1       eeh 	error = bus_dmamap_load(sc->sc_dmatag, rxs->rxs_dmamap,
   1960   1.1       eeh 	    m->m_ext.ext_buf, m->m_ext.ext_size, NULL,
   1961   1.1       eeh 	    BUS_DMA_READ|BUS_DMA_NOWAIT);
   1962   1.1       eeh 	if (error) {
   1963  1.76    cegger 		aprint_error_dev(&sc->sc_dev, "can't load rx DMA map %d, error = %d\n",
   1964  1.76    cegger 		    idx, error);
   1965   1.1       eeh 		panic("gem_add_rxbuf");	/* XXX */
   1966   1.1       eeh 	}
   1967   1.1       eeh 
   1968   1.1       eeh 	bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0,
   1969   1.1       eeh 	    rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
   1970   1.1       eeh 
   1971   1.1       eeh 	GEM_INIT_RXDESC(sc, idx);
   1972   1.1       eeh 
   1973   1.1       eeh 	return (0);
   1974   1.1       eeh }
   1975   1.1       eeh 
   1976   1.1       eeh 
   1977   1.1       eeh int
   1978  1.68       jdc gem_eint(struct gem_softc *sc, u_int status)
   1979   1.1       eeh {
   1980   1.1       eeh 	char bits[128];
   1981  1.68       jdc 	u_int32_t v;
   1982   1.1       eeh 
   1983   1.1       eeh 	if ((status & GEM_INTR_MIF) != 0) {
   1984  1.76    cegger 		printf("%s: XXXlink status changed\n", device_xname(&sc->sc_dev));
   1985   1.1       eeh 		return (1);
   1986   1.1       eeh 	}
   1987   1.1       eeh 
   1988  1.68       jdc 	if ((status & GEM_INTR_RX_TAG_ERR) != 0) {
   1989  1.68       jdc 		gem_reset_rxdma(sc);
   1990  1.68       jdc 		return (1);
   1991  1.68       jdc 	}
   1992  1.68       jdc 
   1993  1.68       jdc 	if (status & GEM_INTR_BERR) {
   1994  1.68       jdc 		bus_space_read_4(sc->sc_bustag, sc->sc_h2, GEM_ERROR_STATUS);
   1995  1.68       jdc 		v = bus_space_read_4(sc->sc_bustag, sc->sc_h2,
   1996  1.68       jdc 		    GEM_ERROR_STATUS);
   1997  1.76    cegger 		aprint_error_dev(&sc->sc_dev, "bus error interrupt: 0x%02x\n",
   1998  1.76    cegger 		    v);
   1999  1.68       jdc 		return (1);
   2000  1.68       jdc 	}
   2001  1.68       jdc 
   2002  1.76    cegger 	printf("%s: status=%s\n", device_xname(&sc->sc_dev),
   2003   1.1       eeh 		bitmask_snprintf(status, GEM_INTR_BITS, bits, sizeof(bits)));
   2004   1.1       eeh 	return (1);
   2005   1.1       eeh }
   2006   1.1       eeh 
   2007   1.1       eeh 
   2008  1.68       jdc /*
   2009  1.68       jdc  * PCS interrupts.
   2010  1.68       jdc  * We should receive these when the link status changes, but sometimes
   2011  1.68       jdc  * we don't receive them for link up.  We compensate for this in the
   2012  1.68       jdc  * gem_tick() callout.
   2013  1.68       jdc  */
   2014  1.68       jdc int
   2015  1.68       jdc gem_pint(struct gem_softc *sc)
   2016  1.68       jdc {
   2017  1.68       jdc 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   2018  1.68       jdc 	bus_space_tag_t t = sc->sc_bustag;
   2019  1.68       jdc 	bus_space_handle_t h = sc->sc_h1;
   2020  1.68       jdc 	u_int32_t v, v2;
   2021  1.68       jdc 
   2022  1.68       jdc 	/*
   2023  1.68       jdc 	 * Clear the PCS interrupt from GEM_STATUS.  The PCS register is
   2024  1.68       jdc 	 * latched, so we have to read it twice.  There is only one bit in
   2025  1.68       jdc 	 * use, so the value is meaningless.
   2026  1.68       jdc 	 */
   2027  1.68       jdc 	bus_space_read_4(t, h, GEM_MII_INTERRUP_STATUS);
   2028  1.68       jdc 	bus_space_read_4(t, h, GEM_MII_INTERRUP_STATUS);
   2029  1.68       jdc 
   2030  1.68       jdc 	if ((ifp->if_flags & IFF_UP) == 0)
   2031  1.68       jdc 		return 1;
   2032  1.68       jdc 
   2033  1.68       jdc 	if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0)
   2034  1.68       jdc 		return 1;
   2035  1.68       jdc 
   2036  1.68       jdc 	v = bus_space_read_4(t, h, GEM_MII_STATUS);
   2037  1.68       jdc 	/* If we see remote fault, our link partner is probably going away */
   2038  1.68       jdc 	if ((v & GEM_MII_STATUS_REM_FLT) != 0) {
   2039  1.68       jdc 		gem_bitwait(sc, h, GEM_MII_STATUS, GEM_MII_STATUS_REM_FLT, 0);
   2040  1.68       jdc 		v = bus_space_read_4(t, h, GEM_MII_STATUS);
   2041  1.68       jdc 	/* Otherwise, we may need to wait after auto-negotiation completes */
   2042  1.68       jdc 	} else if ((v & (GEM_MII_STATUS_LINK_STS | GEM_MII_STATUS_ANEG_CPT)) ==
   2043  1.68       jdc 	    GEM_MII_STATUS_ANEG_CPT) {
   2044  1.68       jdc 		gem_bitwait(sc, h, GEM_MII_STATUS, 0, GEM_MII_STATUS_LINK_STS);
   2045  1.68       jdc 		v = bus_space_read_4(t, h, GEM_MII_STATUS);
   2046  1.68       jdc 	}
   2047  1.68       jdc 	if ((v & GEM_MII_STATUS_LINK_STS) != 0) {
   2048  1.68       jdc 		if (sc->sc_flags & GEM_LINK) {
   2049  1.68       jdc 			return 1;
   2050  1.68       jdc 		}
   2051  1.68       jdc 		callout_stop(&sc->sc_tick_ch);
   2052  1.68       jdc 		v = bus_space_read_4(t, h, GEM_MII_ANAR);
   2053  1.68       jdc 		v2 = bus_space_read_4(t, h, GEM_MII_ANLPAR);
   2054  1.68       jdc 		sc->sc_mii.mii_media_active = IFM_ETHER | IFM_1000_SX;
   2055  1.68       jdc 		sc->sc_mii.mii_media_status = IFM_AVALID | IFM_ACTIVE;
   2056  1.68       jdc 		v &= v2;
   2057  1.68       jdc 		if (v & GEM_MII_ANEG_FUL_DUPLX) {
   2058  1.68       jdc 			sc->sc_mii.mii_media_active |= IFM_FDX;
   2059  1.68       jdc #ifdef GEM_DEBUG
   2060  1.76    cegger 			aprint_debug_dev(&sc->sc_dev, "link up: full duplex\n");
   2061  1.68       jdc #endif
   2062  1.68       jdc 		} else if (v & GEM_MII_ANEG_HLF_DUPLX) {
   2063  1.68       jdc 			sc->sc_mii.mii_media_active |= IFM_HDX;
   2064  1.68       jdc #ifdef GEM_DEBUG
   2065  1.76    cegger 			aprint_debug_dev(&sc->sc_dev, "link up: half duplex\n");
   2066  1.68       jdc #endif
   2067  1.68       jdc 		} else {
   2068  1.68       jdc #ifdef GEM_DEBUG
   2069  1.76    cegger 			aprint_debug_dev(&sc->sc_dev, "duplex mismatch\n");
   2070  1.68       jdc #endif
   2071  1.68       jdc 		}
   2072  1.68       jdc 		gem_statuschange(sc);
   2073  1.68       jdc 	} else {
   2074  1.68       jdc 		if ((sc->sc_flags & GEM_LINK) == 0) {
   2075  1.68       jdc 			return 1;
   2076  1.68       jdc 		}
   2077  1.68       jdc 		sc->sc_mii.mii_media_active = IFM_ETHER | IFM_NONE;
   2078  1.68       jdc 		sc->sc_mii.mii_media_status = IFM_AVALID;
   2079  1.68       jdc #ifdef GEM_DEBUG
   2080  1.76    cegger 			aprint_debug_dev(&sc->sc_dev, "link down\n");
   2081  1.68       jdc #endif
   2082  1.68       jdc 		gem_statuschange(sc);
   2083  1.68       jdc 
   2084  1.68       jdc 		/* Start the 10 second timer */
   2085  1.68       jdc 		callout_reset(&sc->sc_tick_ch, hz * 10, gem_tick, sc);
   2086  1.68       jdc 	}
   2087  1.68       jdc 	return 1;
   2088  1.68       jdc }
   2089  1.68       jdc 
   2090  1.68       jdc 
   2091  1.68       jdc 
   2092   1.1       eeh int
   2093   1.1       eeh gem_intr(v)
   2094   1.1       eeh 	void *v;
   2095   1.1       eeh {
   2096   1.1       eeh 	struct gem_softc *sc = (struct gem_softc *)v;
   2097  1.41  christos 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   2098   1.1       eeh 	bus_space_tag_t t = sc->sc_bustag;
   2099  1.68       jdc 	bus_space_handle_t h = sc->sc_h1;
   2100   1.1       eeh 	u_int32_t status;
   2101   1.1       eeh 	int r = 0;
   2102   1.3       eeh #ifdef GEM_DEBUG
   2103   1.1       eeh 	char bits[128];
   2104   1.3       eeh #endif
   2105   1.1       eeh 
   2106  1.68       jdc 	/* XXX We should probably mask out interrupts until we're done */
   2107  1.68       jdc 
   2108  1.19      matt 	sc->sc_ev_intr.ev_count++;
   2109  1.19      matt 
   2110  1.68       jdc 	status = bus_space_read_4(t, h, GEM_STATUS);
   2111  1.28       chs 	DPRINTF(sc, ("%s: gem_intr: cplt 0x%x status %s\n",
   2112  1.76    cegger 		device_xname(&sc->sc_dev), (status >> 19),
   2113   1.1       eeh 		bitmask_snprintf(status, GEM_INTR_BITS, bits, sizeof(bits))));
   2114   1.1       eeh 
   2115   1.1       eeh 	if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0)
   2116   1.1       eeh 		r |= gem_eint(sc, status);
   2117   1.1       eeh 
   2118  1.68       jdc 	/* We don't bother with GEM_INTR_TX_DONE */
   2119  1.18      matt 	if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) {
   2120  1.19      matt 		GEM_COUNTER_INCR(sc, sc_ev_txint);
   2121   1.1       eeh 		r |= gem_tint(sc);
   2122  1.18      matt 	}
   2123   1.1       eeh 
   2124  1.18      matt 	if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) {
   2125  1.19      matt 		GEM_COUNTER_INCR(sc, sc_ev_rxint);
   2126   1.1       eeh 		r |= gem_rint(sc);
   2127  1.18      matt 	}
   2128   1.1       eeh 
   2129   1.1       eeh 	/* We should eventually do more than just print out error stats. */
   2130   1.1       eeh 	if (status & GEM_INTR_TX_MAC) {
   2131  1.68       jdc 		int txstat = bus_space_read_4(t, h, GEM_MAC_TX_STATUS);
   2132   1.1       eeh 		if (txstat & ~GEM_MAC_TX_XMIT_DONE)
   2133  1.14      matt 			printf("%s: MAC tx fault, status %x\n",
   2134  1.76    cegger 			    device_xname(&sc->sc_dev), txstat);
   2135  1.41  christos 		if (txstat & (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG))
   2136  1.41  christos 			gem_init(ifp);
   2137   1.1       eeh 	}
   2138   1.1       eeh 	if (status & GEM_INTR_RX_MAC) {
   2139  1.68       jdc 		int rxstat = bus_space_read_4(t, h, GEM_MAC_RX_STATUS);
   2140  1.41  christos 		/*
   2141  1.68       jdc 		 * At least with GEM_SUN_GEM and some GEM_SUN_ERI
   2142  1.68       jdc 		 * revisions GEM_MAC_RX_OVERFLOW happen often due to a
   2143  1.68       jdc 		 * silicon bug so handle them silently. Moreover, it's
   2144  1.68       jdc 		 * likely that the receiver has hung so we reset it.
   2145  1.41  christos 		 */
   2146  1.68       jdc 		if (rxstat & GEM_MAC_RX_OVERFLOW) {
   2147  1.68       jdc 			ifp->if_ierrors++;
   2148  1.68       jdc 			gem_reset_rxdma(sc);
   2149  1.68       jdc 		} else if (rxstat & ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT))
   2150  1.73       jdc 			printf("%s: MAC rx fault, status 0x%02x\n",
   2151  1.76    cegger 			    device_xname(&sc->sc_dev), rxstat);
   2152   1.1       eeh 	}
   2153  1.68       jdc 	if (status & GEM_INTR_PCS) {
   2154  1.68       jdc 		r |= gem_pint(sc);
   2155  1.68       jdc 	}
   2156  1.68       jdc 
   2157  1.68       jdc /* Do we need to do anything with these?
   2158  1.68       jdc 	if ((status & GEM_MAC_CONTROL_STATUS) != 0) {
   2159  1.68       jdc 		status2 = bus_read_4(sc->sc_res[0], GEM_MAC_CONTROL_STATUS);
   2160  1.68       jdc 		if ((status2 & GEM_MAC_PAUSED) != 0)
   2161  1.76    cegger 			aprintf_debug_dev(&sc->sc_dev, "PAUSE received (%d slots)\n",
   2162  1.76    cegger 			    GEM_MAC_PAUSE_TIME(status2));
   2163  1.68       jdc 		if ((status2 & GEM_MAC_PAUSE) != 0)
   2164  1.76    cegger 			aprintf_debug_dev(&sc->sc_dev, "transited to PAUSE state\n");
   2165  1.68       jdc 		if ((status2 & GEM_MAC_RESUME) != 0)
   2166  1.76    cegger 			aprintf_debug_dev(&sc->sc_dev, "transited to non-PAUSE state\n");
   2167  1.68       jdc 	}
   2168  1.68       jdc 	if ((status & GEM_INTR_MIF) != 0)
   2169  1.76    cegger 		aprintf_debug_dev(&sc->sc_dev, "MIF interrupt\n");
   2170  1.68       jdc */
   2171  1.45      heas #if NRND > 0
   2172  1.45      heas 	rnd_add_uint32(&sc->rnd_source, status);
   2173  1.45      heas #endif
   2174   1.1       eeh 	return (r);
   2175   1.1       eeh }
   2176   1.1       eeh 
   2177   1.1       eeh 
   2178   1.1       eeh void
   2179   1.1       eeh gem_watchdog(ifp)
   2180   1.1       eeh 	struct ifnet *ifp;
   2181   1.1       eeh {
   2182   1.1       eeh 	struct gem_softc *sc = ifp->if_softc;
   2183   1.1       eeh 
   2184   1.1       eeh 	DPRINTF(sc, ("gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x "
   2185   1.1       eeh 		"GEM_MAC_RX_CONFIG %x\n",
   2186  1.50    martin 		bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_RX_CONFIG),
   2187  1.50    martin 		bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_MAC_RX_STATUS),
   2188  1.50    martin 		bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_MAC_RX_CONFIG)));
   2189   1.1       eeh 
   2190  1.76    cegger 	log(LOG_ERR, "%s: device timeout\n", device_xname(&sc->sc_dev));
   2191   1.1       eeh 	++ifp->if_oerrors;
   2192   1.1       eeh 
   2193   1.1       eeh 	/* Try to get more packets going. */
   2194   1.1       eeh 	gem_start(ifp);
   2195   1.1       eeh }
   2196   1.1       eeh 
   2197   1.1       eeh /*
   2198   1.1       eeh  * Initialize the MII Management Interface
   2199   1.1       eeh  */
   2200   1.1       eeh void
   2201   1.1       eeh gem_mifinit(sc)
   2202   1.1       eeh 	struct gem_softc *sc;
   2203   1.1       eeh {
   2204   1.1       eeh 	bus_space_tag_t t = sc->sc_bustag;
   2205  1.50    martin 	bus_space_handle_t mif = sc->sc_h1;
   2206   1.1       eeh 
   2207   1.1       eeh 	/* Configure the MIF in frame mode */
   2208   1.1       eeh 	sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG);
   2209   1.1       eeh 	sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA;
   2210   1.1       eeh 	bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config);
   2211   1.1       eeh }
   2212   1.1       eeh 
   2213   1.1       eeh /*
   2214   1.1       eeh  * MII interface
   2215   1.1       eeh  *
   2216   1.1       eeh  * The GEM MII interface supports at least three different operating modes:
   2217   1.1       eeh  *
   2218   1.1       eeh  * Bitbang mode is implemented using data, clock and output enable registers.
   2219   1.1       eeh  *
   2220   1.1       eeh  * Frame mode is implemented by loading a complete frame into the frame
   2221   1.1       eeh  * register and polling the valid bit for completion.
   2222   1.1       eeh  *
   2223   1.1       eeh  * Polling mode uses the frame register but completion is indicated by
   2224   1.1       eeh  * an interrupt.
   2225   1.1       eeh  *
   2226   1.1       eeh  */
   2227   1.1       eeh static int
   2228   1.1       eeh gem_mii_readreg(self, phy, reg)
   2229   1.1       eeh 	struct device *self;
   2230   1.1       eeh 	int phy, reg;
   2231   1.1       eeh {
   2232   1.1       eeh 	struct gem_softc *sc = (void *)self;
   2233   1.1       eeh 	bus_space_tag_t t = sc->sc_bustag;
   2234  1.50    martin 	bus_space_handle_t mif = sc->sc_h1;
   2235   1.1       eeh 	int n;
   2236   1.1       eeh 	u_int32_t v;
   2237   1.1       eeh 
   2238   1.1       eeh #ifdef GEM_DEBUG1
   2239   1.1       eeh 	if (sc->sc_debug)
   2240  1.68       jdc 		printf("gem_mii_readreg: PHY %d reg %d\n", phy, reg);
   2241   1.1       eeh #endif
   2242   1.1       eeh 
   2243   1.1       eeh 	/* Construct the frame command */
   2244   1.1       eeh 	v = (reg << GEM_MIF_REG_SHIFT)	| (phy << GEM_MIF_PHY_SHIFT) |
   2245   1.1       eeh 		GEM_MIF_FRAME_READ;
   2246   1.1       eeh 
   2247   1.1       eeh 	bus_space_write_4(t, mif, GEM_MIF_FRAME, v);
   2248   1.1       eeh 	for (n = 0; n < 100; n++) {
   2249   1.1       eeh 		DELAY(1);
   2250   1.1       eeh 		v = bus_space_read_4(t, mif, GEM_MIF_FRAME);
   2251   1.1       eeh 		if (v & GEM_MIF_FRAME_TA0)
   2252   1.1       eeh 			return (v & GEM_MIF_FRAME_DATA);
   2253   1.1       eeh 	}
   2254   1.1       eeh 
   2255  1.76    cegger 	printf("%s: mii_read timeout\n", device_xname(&sc->sc_dev));
   2256   1.1       eeh 	return (0);
   2257   1.1       eeh }
   2258   1.1       eeh 
   2259   1.1       eeh static void
   2260   1.1       eeh gem_mii_writereg(self, phy, reg, val)
   2261   1.1       eeh 	struct device *self;
   2262   1.1       eeh 	int phy, reg, val;
   2263   1.1       eeh {
   2264   1.1       eeh 	struct gem_softc *sc = (void *)self;
   2265   1.1       eeh 	bus_space_tag_t t = sc->sc_bustag;
   2266  1.50    martin 	bus_space_handle_t mif = sc->sc_h1;
   2267   1.1       eeh 	int n;
   2268   1.1       eeh 	u_int32_t v;
   2269   1.1       eeh 
   2270   1.1       eeh #ifdef GEM_DEBUG1
   2271   1.1       eeh 	if (sc->sc_debug)
   2272  1.68       jdc 		printf("gem_mii_writereg: PHY %d reg %d val %x\n",
   2273   1.1       eeh 			phy, reg, val);
   2274   1.1       eeh #endif
   2275   1.1       eeh 
   2276   1.1       eeh 	/* Construct the frame command */
   2277   1.1       eeh 	v = GEM_MIF_FRAME_WRITE			|
   2278   1.1       eeh 	    (phy << GEM_MIF_PHY_SHIFT)		|
   2279   1.1       eeh 	    (reg << GEM_MIF_REG_SHIFT)		|
   2280   1.1       eeh 	    (val & GEM_MIF_FRAME_DATA);
   2281   1.1       eeh 
   2282   1.1       eeh 	bus_space_write_4(t, mif, GEM_MIF_FRAME, v);
   2283   1.1       eeh 	for (n = 0; n < 100; n++) {
   2284   1.1       eeh 		DELAY(1);
   2285   1.1       eeh 		v = bus_space_read_4(t, mif, GEM_MIF_FRAME);
   2286   1.1       eeh 		if (v & GEM_MIF_FRAME_TA0)
   2287   1.1       eeh 			return;
   2288   1.1       eeh 	}
   2289   1.1       eeh 
   2290  1.76    cegger 	printf("%s: mii_write timeout\n", device_xname(&sc->sc_dev));
   2291   1.1       eeh }
   2292   1.1       eeh 
   2293   1.1       eeh static void
   2294   1.1       eeh gem_mii_statchg(dev)
   2295   1.1       eeh 	struct device *dev;
   2296   1.1       eeh {
   2297   1.1       eeh 	struct gem_softc *sc = (void *)dev;
   2298   1.3       eeh #ifdef GEM_DEBUG
   2299   1.1       eeh 	int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media);
   2300   1.3       eeh #endif
   2301   1.1       eeh 
   2302   1.1       eeh #ifdef GEM_DEBUG
   2303   1.1       eeh 	if (sc->sc_debug)
   2304  1.31      heas 		printf("gem_mii_statchg: status change: phy = %d\n",
   2305  1.28       chs 			sc->sc_phys[instance]);
   2306   1.1       eeh #endif
   2307  1.68       jdc 	gem_statuschange(sc);
   2308  1.68       jdc }
   2309   1.1       eeh 
   2310  1.68       jdc /*
   2311  1.68       jdc  * Common status change for gem_mii_statchg() and gem_pint()
   2312  1.68       jdc  */
   2313  1.68       jdc void
   2314  1.68       jdc gem_statuschange(struct gem_softc* sc)
   2315  1.68       jdc {
   2316  1.68       jdc 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   2317  1.68       jdc 	bus_space_tag_t t = sc->sc_bustag;
   2318  1.68       jdc 	bus_space_handle_t mac = sc->sc_h1;
   2319  1.68       jdc 	int gigabit;
   2320  1.68       jdc 	u_int32_t rxcfg, txcfg, v;
   2321  1.68       jdc 
   2322  1.68       jdc 	if ((sc->sc_mii.mii_media_status & IFM_ACTIVE) != 0 &&
   2323  1.68       jdc 	    IFM_SUBTYPE(sc->sc_mii.mii_media_active) != IFM_NONE)
   2324  1.68       jdc 		sc->sc_flags |= GEM_LINK;
   2325  1.68       jdc 	else
   2326  1.68       jdc 		sc->sc_flags &= ~GEM_LINK;
   2327  1.68       jdc 
   2328  1.70       jdc 	if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000))
   2329  1.68       jdc 		gigabit = 1;
   2330  1.70       jdc 	else
   2331  1.68       jdc 		gigabit = 0;
   2332   1.1       eeh 
   2333  1.68       jdc 	/*
   2334  1.68       jdc 	 * The configuration done here corresponds to the steps F) and
   2335  1.68       jdc 	 * G) and as far as enabling of RX and TX MAC goes also step H)
   2336  1.68       jdc 	 * of the initialization sequence outlined in section 3.2.1 of
   2337  1.68       jdc 	 * the GEM Gigabit Ethernet ASIC Specification.
   2338  1.68       jdc 	 */
   2339  1.68       jdc 
   2340  1.68       jdc 	rxcfg = bus_space_read_4(t, mac, GEM_MAC_RX_CONFIG);
   2341  1.68       jdc 	rxcfg &= ~(GEM_MAC_RX_CARR_EXTEND | GEM_MAC_RX_ENABLE);
   2342  1.68       jdc 	txcfg = GEM_MAC_TX_ENA_IPG0 | GEM_MAC_TX_NGU | GEM_MAC_TX_NGU_LIMIT;
   2343  1.68       jdc 	if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0)
   2344  1.68       jdc 		txcfg |= GEM_MAC_TX_IGN_CARRIER | GEM_MAC_TX_IGN_COLLIS;
   2345  1.68       jdc 	else if (gigabit) {
   2346  1.68       jdc 		rxcfg |= GEM_MAC_RX_CARR_EXTEND;
   2347  1.68       jdc 		txcfg |= GEM_MAC_RX_CARR_EXTEND;
   2348  1.68       jdc 	}
   2349   1.1       eeh 	bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0);
   2350  1.68       jdc 	bus_space_barrier(t, mac, GEM_MAC_TX_CONFIG, 4,
   2351  1.68       jdc 	    BUS_SPACE_BARRIER_WRITE);
   2352  1.68       jdc 	if (!gem_bitwait(sc, mac, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0))
   2353  1.76    cegger 		aprint_normal_dev(&sc->sc_dev, "cannot disable TX MAC\n");
   2354  1.68       jdc 	bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, txcfg);
   2355  1.68       jdc 	bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, 0);
   2356  1.68       jdc 	bus_space_barrier(t, mac, GEM_MAC_RX_CONFIG, 4,
   2357  1.68       jdc 	    BUS_SPACE_BARRIER_WRITE);
   2358  1.68       jdc 	if (!gem_bitwait(sc, mac, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0))
   2359  1.76    cegger 		aprint_normal_dev(&sc->sc_dev, "cannot disable RX MAC\n");
   2360  1.68       jdc 	bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, rxcfg);
   2361  1.68       jdc 
   2362  1.68       jdc 	v = bus_space_read_4(t, mac, GEM_MAC_CONTROL_CONFIG) &
   2363  1.68       jdc 	    ~(GEM_MAC_CC_RX_PAUSE | GEM_MAC_CC_TX_PAUSE);
   2364  1.68       jdc 	bus_space_write_4(t, mac, GEM_MAC_CONTROL_CONFIG, v);
   2365  1.68       jdc 
   2366  1.68       jdc 	if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) == 0 &&
   2367  1.68       jdc 	    gigabit != 0)
   2368  1.68       jdc 		bus_space_write_4(t, mac, GEM_MAC_SLOT_TIME,
   2369  1.68       jdc 		    GEM_MAC_SLOT_TIME_CARR_EXTEND);
   2370  1.68       jdc 	else
   2371  1.68       jdc 		bus_space_write_4(t, mac, GEM_MAC_SLOT_TIME,
   2372  1.68       jdc 		    GEM_MAC_SLOT_TIME_NORMAL);
   2373   1.1       eeh 
   2374   1.1       eeh 	/* XIF Configuration */
   2375  1.68       jdc 	if (sc->sc_flags & GEM_LINK)
   2376  1.68       jdc 		v = GEM_MAC_XIF_LINK_LED;
   2377  1.68       jdc 	else
   2378  1.68       jdc 		v = 0;
   2379   1.1       eeh 	v |= GEM_MAC_XIF_TX_MII_ENA;
   2380  1.70       jdc 
   2381  1.70       jdc 	/* If an external transceiver is connected, enable its MII drivers */
   2382  1.70       jdc 	sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG);
   2383  1.70       jdc 	if ((sc->sc_flags &(GEM_SERDES | GEM_SERIAL)) == 0) {
   2384  1.70       jdc 		if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) {
   2385  1.70       jdc 			/* External MII needs echo disable if half duplex. */
   2386  1.70       jdc 			if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) &
   2387  1.70       jdc 			    IFM_FDX) != 0)
   2388  1.70       jdc 				/* turn on full duplex LED */
   2389  1.70       jdc 				v |= GEM_MAC_XIF_FDPLX_LED;
   2390  1.70       jdc 			else
   2391  1.70       jdc 				/* half duplex -- disable echo */
   2392  1.70       jdc 				v |= GEM_MAC_XIF_ECHO_DISABL;
   2393  1.70       jdc 			if (gigabit)
   2394  1.70       jdc 				v |= GEM_MAC_XIF_GMII_MODE;
   2395  1.70       jdc 			else
   2396  1.70       jdc 				v &= ~GEM_MAC_XIF_GMII_MODE;
   2397  1.70       jdc 		} else
   2398  1.70       jdc 			/* Internal MII needs buf enable */
   2399  1.70       jdc 			v |= GEM_MAC_XIF_MII_BUF_ENA;
   2400  1.68       jdc 	} else {
   2401  1.70       jdc 		if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0)
   2402  1.70       jdc 			v |= GEM_MAC_XIF_FDPLX_LED;
   2403  1.70       jdc 		v |= GEM_MAC_XIF_GMII_MODE;
   2404  1.68       jdc 	}
   2405  1.70       jdc 	bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v);
   2406  1.70       jdc 
   2407  1.68       jdc 	if ((ifp->if_flags & IFF_RUNNING) != 0 &&
   2408  1.68       jdc 	    (sc->sc_flags & GEM_LINK) != 0) {
   2409  1.68       jdc 		bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG,
   2410  1.68       jdc 		    txcfg | GEM_MAC_TX_ENABLE);
   2411  1.68       jdc 		bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG,
   2412  1.68       jdc 		    rxcfg | GEM_MAC_RX_ENABLE);
   2413  1.68       jdc 	}
   2414   1.1       eeh }
   2415   1.1       eeh 
   2416   1.1       eeh int
   2417  1.69    dyoung gem_ser_mediachange(struct ifnet *ifp)
   2418   1.1       eeh {
   2419   1.1       eeh 	struct gem_softc *sc = ifp->if_softc;
   2420  1.68       jdc 	u_int s, t;
   2421   1.1       eeh 
   2422  1.69    dyoung 	if (IFM_TYPE(sc->sc_mii.mii_media.ifm_media) != IFM_ETHER)
   2423  1.68       jdc 		return EINVAL;
   2424   1.1       eeh 
   2425  1.69    dyoung 	s = IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media);
   2426  1.69    dyoung 	if (s == IFM_AUTO) {
   2427  1.69    dyoung 		if (sc->sc_mii_media != s) {
   2428  1.69    dyoung #ifdef GEM_DEBUG
   2429  1.76    cegger 			aprint_debug_dev(&sc->sc_dev, "setting media to auto\n");
   2430  1.69    dyoung #endif
   2431  1.69    dyoung 			sc->sc_mii_media = s;
   2432  1.69    dyoung 			if (ifp->if_flags & IFF_UP) {
   2433  1.69    dyoung 				gem_pcs_stop(sc, 0);
   2434  1.69    dyoung 				gem_pcs_start(sc);
   2435  1.69    dyoung 			}
   2436  1.69    dyoung 		}
   2437  1.69    dyoung 		return 0;
   2438  1.69    dyoung 	}
   2439  1.69    dyoung 	if (s == IFM_1000_SX) {
   2440  1.69    dyoung 		t = IFM_OPTIONS(sc->sc_mii.mii_media.ifm_media);
   2441  1.69    dyoung 		if (t == IFM_FDX || t == IFM_HDX) {
   2442  1.69    dyoung 			if (sc->sc_mii_media != t) {
   2443  1.69    dyoung 				sc->sc_mii_media = t;
   2444  1.68       jdc #ifdef GEM_DEBUG
   2445  1.76    cegger 				aprint_debug_dev(&sc->sc_dev,
   2446  1.76    cegger 				    "setting media to 1000baseSX-%s\n",
   2447  1.69    dyoung 				    t == IFM_FDX ? "FDX" : "HDX");
   2448  1.68       jdc #endif
   2449  1.68       jdc 				if (ifp->if_flags & IFF_UP) {
   2450  1.68       jdc 					gem_pcs_stop(sc, 0);
   2451  1.68       jdc 					gem_pcs_start(sc);
   2452  1.68       jdc 				}
   2453  1.68       jdc 			}
   2454  1.68       jdc 			return 0;
   2455  1.68       jdc 		}
   2456  1.69    dyoung 	}
   2457  1.69    dyoung 	return EINVAL;
   2458   1.1       eeh }
   2459   1.1       eeh 
   2460   1.1       eeh void
   2461  1.69    dyoung gem_ser_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
   2462   1.1       eeh {
   2463   1.1       eeh 	struct gem_softc *sc = ifp->if_softc;
   2464   1.1       eeh 
   2465   1.1       eeh 	if ((ifp->if_flags & IFF_UP) == 0)
   2466   1.1       eeh 		return;
   2467   1.1       eeh 	ifmr->ifm_active = sc->sc_mii.mii_media_active;
   2468   1.1       eeh 	ifmr->ifm_status = sc->sc_mii.mii_media_status;
   2469   1.1       eeh }
   2470   1.1       eeh 
   2471   1.1       eeh /*
   2472   1.1       eeh  * Process an ioctl request.
   2473   1.1       eeh  */
   2474   1.1       eeh int
   2475   1.1       eeh gem_ioctl(ifp, cmd, data)
   2476   1.1       eeh 	struct ifnet *ifp;
   2477   1.1       eeh 	u_long cmd;
   2478  1.53  christos 	void *data;
   2479   1.1       eeh {
   2480   1.1       eeh 	struct gem_softc *sc = ifp->if_softc;
   2481   1.1       eeh 	int s, error = 0;
   2482   1.1       eeh 
   2483  1.20      matt 	s = splnet();
   2484   1.1       eeh 
   2485   1.1       eeh 	switch (cmd) {
   2486  1.41  christos 	case SIOCSIFFLAGS:
   2487  1.41  christos #define RESETIGN (IFF_CANTCHANGE|IFF_DEBUG)
   2488  1.41  christos 		if (((ifp->if_flags & (IFF_UP|IFF_RUNNING))
   2489  1.41  christos 		    == (IFF_UP|IFF_RUNNING))
   2490  1.41  christos 		    && ((ifp->if_flags & (~RESETIGN))
   2491  1.41  christos 		    == (sc->sc_if_flags & (~RESETIGN)))) {
   2492  1.41  christos 			gem_setladrf(sc);
   2493  1.41  christos 			break;
   2494  1.41  christos 		}
   2495  1.41  christos #undef RESETIGN
   2496  1.41  christos 		/*FALLTHROUGH*/
   2497   1.1       eeh 	default:
   2498  1.74    dyoung 		if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET)
   2499  1.74    dyoung 			break;
   2500  1.74    dyoung 
   2501  1.74    dyoung 		error = 0;
   2502  1.74    dyoung 
   2503  1.74    dyoung 		if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI)
   2504  1.74    dyoung 			;
   2505  1.74    dyoung 		else if (ifp->if_flags & IFF_RUNNING) {
   2506   1.1       eeh 			/*
   2507   1.1       eeh 			 * Multicast list has changed; set the hardware filter
   2508   1.1       eeh 			 * accordingly.
   2509   1.1       eeh 			 */
   2510  1.74    dyoung 			gem_setladrf(sc);
   2511   1.1       eeh 		}
   2512   1.1       eeh 		break;
   2513   1.1       eeh 	}
   2514   1.1       eeh 
   2515   1.1       eeh 	/* Try to get things going again */
   2516  1.43  christos 	if (ifp->if_flags & IFF_UP)
   2517   1.1       eeh 		gem_start(ifp);
   2518   1.1       eeh 	splx(s);
   2519   1.1       eeh 	return (error);
   2520   1.1       eeh }
   2521   1.1       eeh 
   2522   1.1       eeh 
   2523   1.1       eeh void
   2524   1.1       eeh gem_shutdown(arg)
   2525   1.1       eeh 	void *arg;
   2526   1.1       eeh {
   2527   1.1       eeh 	struct gem_softc *sc = (struct gem_softc *)arg;
   2528   1.1       eeh 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   2529   1.1       eeh 
   2530   1.1       eeh 	gem_stop(ifp, 1);
   2531   1.1       eeh }
   2532   1.1       eeh 
   2533   1.1       eeh /*
   2534   1.1       eeh  * Set up the logical address filter.
   2535   1.1       eeh  */
   2536   1.1       eeh void
   2537   1.1       eeh gem_setladrf(sc)
   2538   1.1       eeh 	struct gem_softc *sc;
   2539   1.1       eeh {
   2540  1.15      matt 	struct ethercom *ec = &sc->sc_ethercom;
   2541  1.15      matt 	struct ifnet *ifp = &ec->ec_if;
   2542   1.1       eeh 	struct ether_multi *enm;
   2543   1.1       eeh 	struct ether_multistep step;
   2544   1.1       eeh 	bus_space_tag_t t = sc->sc_bustag;
   2545  1.50    martin 	bus_space_handle_t h = sc->sc_h1;
   2546   1.1       eeh 	u_int32_t crc;
   2547   1.1       eeh 	u_int32_t hash[16];
   2548   1.1       eeh 	u_int32_t v;
   2549  1.15      matt 	int i;
   2550   1.1       eeh 
   2551   1.1       eeh 	/* Get current RX configuration */
   2552   1.1       eeh 	v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG);
   2553   1.1       eeh 
   2554  1.15      matt 	/*
   2555  1.15      matt 	 * Turn off promiscuous mode, promiscuous group mode (all multicast),
   2556  1.15      matt 	 * and hash filter.  Depending on the case, the right bit will be
   2557  1.15      matt 	 * enabled.
   2558  1.15      matt 	 */
   2559  1.15      matt 	v &= ~(GEM_MAC_RX_PROMISCUOUS|GEM_MAC_RX_HASH_FILTER|
   2560  1.15      matt 	    GEM_MAC_RX_PROMISC_GRP);
   2561  1.15      matt 
   2562   1.1       eeh 	if ((ifp->if_flags & IFF_PROMISC) != 0) {
   2563  1.15      matt 		/* Turn on promiscuous mode */
   2564   1.1       eeh 		v |= GEM_MAC_RX_PROMISCUOUS;
   2565   1.1       eeh 		ifp->if_flags |= IFF_ALLMULTI;
   2566   1.1       eeh 		goto chipit;
   2567   1.1       eeh 	}
   2568   1.1       eeh 
   2569   1.1       eeh 	/*
   2570   1.1       eeh 	 * Set up multicast address filter by passing all multicast addresses
   2571  1.15      matt 	 * through a crc generator, and then using the high order 8 bits as an
   2572  1.15      matt 	 * index into the 256 bit logical address filter.  The high order 4
   2573  1.41  christos 	 * bits selects the word, while the other 4 bits select the bit within
   2574  1.15      matt 	 * the word (where bit 0 is the MSB).
   2575   1.1       eeh 	 */
   2576   1.1       eeh 
   2577  1.15      matt 	/* Clear hash table */
   2578  1.15      matt 	memset(hash, 0, sizeof(hash));
   2579  1.15      matt 
   2580   1.1       eeh 	ETHER_FIRST_MULTI(step, ec, enm);
   2581   1.1       eeh 	while (enm != NULL) {
   2582   1.6   thorpej 		if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
   2583   1.1       eeh 			/*
   2584   1.1       eeh 			 * We must listen to a range of multicast addresses.
   2585   1.1       eeh 			 * For now, just accept all multicasts, rather than
   2586   1.1       eeh 			 * trying to set only those filter bits needed to match
   2587   1.1       eeh 			 * the range.  (At this time, the only use of address
   2588   1.1       eeh 			 * ranges is for IP multicast routing, for which the
   2589   1.1       eeh 			 * range is big enough to require all bits set.)
   2590  1.68       jdc 			 * XXX should use the address filters for this
   2591   1.1       eeh 			 */
   2592   1.1       eeh 			ifp->if_flags |= IFF_ALLMULTI;
   2593  1.15      matt 			v |= GEM_MAC_RX_PROMISC_GRP;
   2594   1.1       eeh 			goto chipit;
   2595   1.1       eeh 		}
   2596   1.1       eeh 
   2597  1.15      matt 		/* Get the LE CRC32 of the address */
   2598  1.15      matt 		crc = ether_crc32_le(enm->enm_addrlo, sizeof(enm->enm_addrlo));
   2599   1.1       eeh 
   2600   1.1       eeh 		/* Just want the 8 most significant bits. */
   2601   1.1       eeh 		crc >>= 24;
   2602   1.1       eeh 
   2603   1.1       eeh 		/* Set the corresponding bit in the filter. */
   2604  1.15      matt 		hash[crc >> 4] |= 1 << (15 - (crc & 15));
   2605   1.1       eeh 
   2606   1.1       eeh 		ETHER_NEXT_MULTI(step, enm);
   2607   1.1       eeh 	}
   2608   1.1       eeh 
   2609  1.15      matt 	v |= GEM_MAC_RX_HASH_FILTER;
   2610   1.1       eeh 	ifp->if_flags &= ~IFF_ALLMULTI;
   2611   1.1       eeh 
   2612  1.15      matt 	/* Now load the hash table into the chip (if we are using it) */
   2613  1.15      matt 	for (i = 0; i < 16; i++) {
   2614  1.15      matt 		bus_space_write_4(t, h,
   2615  1.15      matt 		    GEM_MAC_HASH0 + i * (GEM_MAC_HASH1-GEM_MAC_HASH0),
   2616  1.15      matt 		    hash[i]);
   2617  1.15      matt 	}
   2618  1.15      matt 
   2619   1.1       eeh chipit:
   2620  1.41  christos 	sc->sc_if_flags = ifp->if_flags;
   2621   1.1       eeh 	bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v);
   2622   1.1       eeh }
   2623   1.1       eeh 
   2624   1.1       eeh #if notyet
   2625   1.1       eeh 
   2626   1.1       eeh /*
   2627   1.1       eeh  * gem_power:
   2628   1.1       eeh  *
   2629   1.1       eeh  *	Power management (suspend/resume) hook.
   2630   1.1       eeh  */
   2631   1.1       eeh void
   2632   1.1       eeh gem_power(why, arg)
   2633   1.1       eeh 	int why;
   2634   1.1       eeh 	void *arg;
   2635   1.1       eeh {
   2636   1.1       eeh 	struct gem_softc *sc = arg;
   2637   1.1       eeh 	struct ifnet *ifp = &sc->sc_ethercom.ec_if;
   2638   1.1       eeh 	int s;
   2639   1.1       eeh 
   2640   1.1       eeh 	s = splnet();
   2641   1.1       eeh 	switch (why) {
   2642   1.1       eeh 	case PWR_SUSPEND:
   2643   1.1       eeh 	case PWR_STANDBY:
   2644   1.1       eeh 		gem_stop(ifp, 1);
   2645   1.1       eeh 		if (sc->sc_power != NULL)
   2646   1.1       eeh 			(*sc->sc_power)(sc, why);
   2647   1.1       eeh 		break;
   2648   1.1       eeh 	case PWR_RESUME:
   2649   1.1       eeh 		if (ifp->if_flags & IFF_UP) {
   2650   1.1       eeh 			if (sc->sc_power != NULL)
   2651   1.1       eeh 				(*sc->sc_power)(sc, why);
   2652   1.1       eeh 			gem_init(ifp);
   2653   1.1       eeh 		}
   2654   1.1       eeh 		break;
   2655   1.1       eeh 	case PWR_SOFTSUSPEND:
   2656   1.1       eeh 	case PWR_SOFTSTANDBY:
   2657   1.1       eeh 	case PWR_SOFTRESUME:
   2658   1.1       eeh 		break;
   2659   1.1       eeh 	}
   2660   1.1       eeh 	splx(s);
   2661   1.1       eeh }
   2662   1.1       eeh #endif
   2663