gem.c revision 1.1
1 /* $NetBSD: gem.c,v 1.1 2001/09/16 00:11:43 eeh Exp $ */ 2 3 /* 4 * 5 * Copyright (C) 2001 Eduardo Horvath. 6 * All rights reserved. 7 * 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 */ 31 32 /* 33 * Driver for Sun GEM ethernet controllers. 34 */ 35 36 #define GEM_DEBUG 37 int gem_opdebug = 0; 38 39 #include "bpfilter.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/callout.h> 44 #include <sys/mbuf.h> 45 #include <sys/syslog.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #include <sys/socket.h> 49 #include <sys/ioctl.h> 50 #include <sys/errno.h> 51 #include <sys/device.h> 52 53 #include <machine/endian.h> 54 55 #include <uvm/uvm_extern.h> 56 57 #include <net/if.h> 58 #include <net/if_dl.h> 59 #include <net/if_media.h> 60 #include <net/if_ether.h> 61 62 #if NBPFILTER > 0 63 #include <net/bpf.h> 64 #endif 65 66 #include <machine/bus.h> 67 #include <machine/intr.h> 68 69 #include <dev/mii/mii.h> 70 #include <dev/mii/miivar.h> 71 #include <dev/mii/mii_bitbang.h> 72 73 #include <dev/ic/gemreg.h> 74 #include <dev/ic/gemvar.h> 75 76 #define TRIES 10000 77 78 void gem_start __P((struct ifnet *)); 79 void gem_stop __P((struct ifnet *, int)); 80 int gem_ioctl __P((struct ifnet *, u_long, caddr_t)); 81 void gem_tick __P((void *)); 82 void gem_watchdog __P((struct ifnet *)); 83 void gem_shutdown __P((void *)); 84 int gem_init __P((struct ifnet *)); 85 void gem_init_regs(struct gem_softc *sc); 86 static int gem_ringsize(int sz); 87 int gem_meminit __P((struct gem_softc *)); 88 void gem_mifinit __P((struct gem_softc *)); 89 void gem_reset __P((struct gem_softc *)); 90 int gem_reset_rx(struct gem_softc *sc); 91 int gem_reset_tx(struct gem_softc *sc); 92 int gem_disable_rx(struct gem_softc *sc); 93 int gem_disable_tx(struct gem_softc *sc); 94 void gem_rxdrain(struct gem_softc *sc); 95 int gem_add_rxbuf(struct gem_softc *sc, int idx); 96 void gem_setladrf __P((struct gem_softc *)); 97 98 /* MII methods & callbacks */ 99 static int gem_mii_readreg __P((struct device *, int, int)); 100 static void gem_mii_writereg __P((struct device *, int, int, int)); 101 static void gem_mii_statchg __P((struct device *)); 102 103 int gem_mediachange __P((struct ifnet *)); 104 void gem_mediastatus __P((struct ifnet *, struct ifmediareq *)); 105 106 struct mbuf *gem_get __P((struct gem_softc *, int, int)); 107 int gem_put __P((struct gem_softc *, int, struct mbuf *)); 108 void gem_read __P((struct gem_softc *, int, int)); 109 int gem_eint __P((struct gem_softc *, u_int)); 110 int gem_rint __P((struct gem_softc *)); 111 int gem_tint __P((struct gem_softc *)); 112 void gem_power __P((int, void *)); 113 114 static int ether_cmp __P((u_char *, u_char *)); 115 116 /* Default buffer copy routines */ 117 void gem_copytobuf_contig __P((struct gem_softc *, void *, int, int)); 118 void gem_copyfrombuf_contig __P((struct gem_softc *, void *, int, int)); 119 void gem_zerobuf_contig __P((struct gem_softc *, int, int)); 120 121 122 #ifdef GEM_DEBUG 123 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 124 printf x 125 #else 126 #define DPRINTF(sc, x) /* nothing */ 127 #endif 128 129 130 /* 131 * gem_config: 132 * 133 * Attach a Gem interface to the system. 134 */ 135 void 136 gem_config(sc) 137 struct gem_softc *sc; 138 { 139 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 140 struct mii_data *mii = &sc->sc_mii; 141 struct mii_softc *child; 142 int i, error; 143 144 /* Make sure the chip is stopped. */ 145 ifp->if_softc = sc; 146 gem_reset(sc); 147 148 /* 149 * Allocate the control data structures, and create and load the 150 * DMA map for it. 151 */ 152 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 153 sizeof(struct gem_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 154 1, &sc->sc_cdnseg, 0)) != 0) { 155 printf("%s: unable to allocate control data, error = %d\n", 156 sc->sc_dev.dv_xname, error); 157 goto fail_0; 158 } 159 160 /* XXX should map this in with correct endianness */ 161 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg, 162 sizeof(struct gem_control_data), (caddr_t *)&sc->sc_control_data, 163 BUS_DMA_COHERENT)) != 0) { 164 printf("%s: unable to map control data, error = %d\n", 165 sc->sc_dev.dv_xname, error); 166 goto fail_1; 167 } 168 169 if ((error = bus_dmamap_create(sc->sc_dmatag, 170 sizeof(struct gem_control_data), 1, 171 sizeof(struct gem_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 172 printf("%s: unable to create control data DMA map, " 173 "error = %d\n", sc->sc_dev.dv_xname, error); 174 goto fail_2; 175 } 176 177 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 178 sc->sc_control_data, sizeof(struct gem_control_data), NULL, 179 0)) != 0) { 180 printf("%s: unable to load control data DMA map, error = %d\n", 181 sc->sc_dev.dv_xname, error); 182 goto fail_3; 183 } 184 185 /* 186 * Initialize the transmit job descriptors. 187 */ 188 SIMPLEQ_INIT(&sc->sc_txfreeq); 189 SIMPLEQ_INIT(&sc->sc_txdirtyq); 190 191 /* 192 * Create the transmit buffer DMA maps. 193 */ 194 for (i = 0; i < GEM_TXQUEUELEN; i++) { 195 struct gem_txsoft *txs; 196 197 txs = &sc->sc_txsoft[i]; 198 txs->txs_mbuf = NULL; 199 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 200 GEM_NTXSEGS, MCLBYTES, 0, 0, 201 &txs->txs_dmamap)) != 0) { 202 printf("%s: unable to create tx DMA map %d, " 203 "error = %d\n", sc->sc_dev.dv_xname, i, error); 204 goto fail_4; 205 } 206 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 207 } 208 209 /* 210 * Create the receive buffer DMA maps. 211 */ 212 for (i = 0; i < GEM_NRXDESC; i++) { 213 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, 214 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 215 printf("%s: unable to create rx DMA map %d, " 216 "error = %d\n", sc->sc_dev.dv_xname, i, error); 217 goto fail_5; 218 } 219 sc->sc_rxsoft[i].rxs_mbuf = NULL; 220 } 221 222 /* 223 * From this point forward, the attachment cannot fail. A failure 224 * before this point releases all resources that may have been 225 * allocated. 226 */ 227 sc->sc_flags |= GEMF_ATTACHED; 228 229 /* Announce ourselves. */ 230 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 231 ether_sprintf(sc->sc_enaddr)); 232 233 /* Initialize ifnet structure. */ 234 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 235 ifp->if_softc = sc; 236 ifp->if_flags = 237 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 238 ifp->if_start = gem_start; 239 ifp->if_ioctl = gem_ioctl; 240 ifp->if_watchdog = gem_watchdog; 241 ifp->if_stop = gem_stop; 242 ifp->if_init = gem_init; 243 IFQ_SET_READY(&ifp->if_snd); 244 245 /* Initialize ifmedia structures and MII info */ 246 mii->mii_ifp = ifp; 247 mii->mii_readreg = gem_mii_readreg; 248 mii->mii_writereg = gem_mii_writereg; 249 mii->mii_statchg = gem_mii_statchg; 250 251 ifmedia_init(&mii->mii_media, 0, gem_mediachange, gem_mediastatus); 252 253 gem_mifinit(sc); 254 255 mii_attach(&sc->sc_dev, mii, 0xffffffff, 256 MII_PHY_ANY, MII_OFFSET_ANY, 0); 257 258 child = LIST_FIRST(&mii->mii_phys); 259 if (child == NULL) { 260 /* No PHY attached */ 261 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 262 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 263 } else { 264 /* 265 * Walk along the list of attached MII devices and 266 * establish an `MII instance' to `phy number' 267 * mapping. We'll use this mapping in media change 268 * requests to determine which phy to use to program 269 * the MIF configuration register. 270 */ 271 for (; child != NULL; child = LIST_NEXT(child, mii_list)) { 272 /* 273 * Note: we support just two PHYs: the built-in 274 * internal device and an external on the MII 275 * connector. 276 */ 277 if (child->mii_phy > 1 || child->mii_inst > 1) { 278 printf("%s: cannot accomodate MII device %s" 279 " at phy %d, instance %d\n", 280 sc->sc_dev.dv_xname, 281 child->mii_dev.dv_xname, 282 child->mii_phy, child->mii_inst); 283 continue; 284 } 285 286 sc->sc_phys[child->mii_inst] = child->mii_phy; 287 } 288 289 /* 290 * Now select and activate the PHY we will use. 291 * 292 * The order of preference is External (MDI1), 293 * Internal (MDI0), Serial Link (no MII). 294 */ 295 if (sc->sc_phys[1]) { 296 #ifdef DEBUG 297 printf("using external phy\n"); 298 #endif 299 sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL; 300 } else { 301 #ifdef DEBUG 302 printf("using internal phy\n"); 303 #endif 304 sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL; 305 } 306 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_MIF_CONFIG, 307 sc->sc_mif_config); 308 309 /* 310 * XXX - we can really do the following ONLY if the 311 * phy indeed has the auto negotiation capability!! 312 */ 313 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO); 314 } 315 316 /* claim 802.1q capability */ 317 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 318 319 /* Attach the interface. */ 320 if_attach(ifp); 321 ether_ifattach(ifp, sc->sc_enaddr); 322 323 sc->sc_sh = shutdownhook_establish(gem_shutdown, sc); 324 if (sc->sc_sh == NULL) 325 panic("gem_config: can't establish shutdownhook"); 326 327 #if NRND > 0 328 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 329 RND_TYPE_NET, 0); 330 #endif 331 332 333 #if notyet 334 /* 335 * Add a suspend hook to make sure we come back up after a 336 * resume. 337 */ 338 sc->sc_powerhook = powerhook_establish(gem_power, sc); 339 if (sc->sc_powerhook == NULL) 340 printf("%s: WARNING: unable to establish power hook\n", 341 sc->sc_dev.dv_xname); 342 #endif 343 344 callout_init(&sc->sc_tick_ch); 345 return; 346 347 /* 348 * Free any resources we've allocated during the failed attach 349 * attempt. Do this in reverse order and fall through. 350 */ 351 fail_5: 352 for (i = 0; i < GEM_NRXDESC; i++) { 353 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 354 bus_dmamap_destroy(sc->sc_dmatag, 355 sc->sc_rxsoft[i].rxs_dmamap); 356 } 357 fail_4: 358 for (i = 0; i < GEM_TXQUEUELEN; i++) { 359 if (sc->sc_txsoft[i].txs_dmamap != NULL) 360 bus_dmamap_destroy(sc->sc_dmatag, 361 sc->sc_txsoft[i].txs_dmamap); 362 } 363 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 364 fail_3: 365 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 366 fail_2: 367 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)sc->sc_control_data, 368 sizeof(struct gem_control_data)); 369 fail_1: 370 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 371 fail_0: 372 return; 373 } 374 375 376 void 377 gem_tick(arg) 378 void *arg; 379 { 380 struct gem_softc *sc = arg; 381 int s; 382 383 s = splnet(); 384 mii_tick(&sc->sc_mii); 385 splx(s); 386 387 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 388 389 } 390 391 void 392 gem_reset(sc) 393 struct gem_softc *sc; 394 { 395 bus_space_tag_t t = sc->sc_bustag; 396 bus_space_handle_t h = sc->sc_h; 397 int i; 398 int s; 399 400 s = splnet(); 401 DPRINTF(sc, ("%s: gem_reset\n", sc->sc_dev.dv_xname)); 402 gem_reset_rx(sc); 403 gem_reset_tx(sc); 404 405 /* Do a full reset */ 406 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX|GEM_RESET_TX); 407 for (i=TRIES; i--; delay(100)) 408 if ((bus_space_read_4(t, h, GEM_RESET) & 409 (GEM_RESET_RX|GEM_RESET_TX)) == 0) 410 break; 411 if ((bus_space_read_4(t, h, GEM_RESET) & 412 (GEM_RESET_RX|GEM_RESET_TX)) != 0) { 413 printf("%s: cannot reset device\n", 414 sc->sc_dev.dv_xname); 415 } 416 splx(s); 417 } 418 419 420 /* 421 * gem_rxdrain: 422 * 423 * Drain the receive queue. 424 */ 425 void 426 gem_rxdrain(struct gem_softc *sc) 427 { 428 struct gem_rxsoft *rxs; 429 int i; 430 431 for (i = 0; i < GEM_NRXDESC; i++) { 432 rxs = &sc->sc_rxsoft[i]; 433 if (rxs->rxs_mbuf != NULL) { 434 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 435 m_freem(rxs->rxs_mbuf); 436 rxs->rxs_mbuf = NULL; 437 } 438 } 439 } 440 441 /* 442 * Reset the whole thing. 443 */ 444 void 445 gem_stop(struct ifnet *ifp, int disable) 446 { 447 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 448 struct gem_txsoft *txs; 449 450 if (gem_opdebug) printf("in stop %d\n", disable); 451 DPRINTF(sc, ("%s: gem_stop\n", sc->sc_dev.dv_xname)); 452 453 callout_stop(&sc->sc_tick_ch); 454 mii_down(&sc->sc_mii); 455 456 /* XXX - Should we reset these instead? */ 457 gem_disable_rx(sc); 458 gem_disable_rx(sc); 459 460 /* 461 * Release any queued transmit buffers. 462 */ 463 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 464 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs, txs_q); 465 if (txs->txs_mbuf != NULL) { 466 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 467 m_freem(txs->txs_mbuf); 468 txs->txs_mbuf = NULL; 469 } 470 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 471 } 472 473 if (disable) { 474 gem_rxdrain(sc); 475 } 476 477 /* 478 * Mark the interface down and cancel the watchdog timer. 479 */ 480 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 481 ifp->if_timer = 0; 482 } 483 484 485 /* 486 * Reset the receiver 487 */ 488 int 489 gem_reset_rx(struct gem_softc *sc) 490 { 491 bus_space_tag_t t = sc->sc_bustag; 492 bus_space_handle_t h = sc->sc_h; 493 int i; 494 495 496 /* 497 * Resetting while DMA is in progress can cause a bus hang, so we 498 * disable DMA first. 499 */ 500 gem_disable_rx(sc); 501 bus_space_write_4(t, h, GEM_RX_CONFIG, 0); 502 /* Wait till it finishes */ 503 for (i=TRIES; i--; delay(100)) 504 if ((bus_space_read_4(t, h, GEM_RX_CONFIG) & 1) == 0) 505 break; 506 if ((bus_space_read_4(t, h, GEM_RX_CONFIG) & 1) != 0) 507 printf("%s: cannot disable read dma\n", 508 sc->sc_dev.dv_xname); 509 510 /* Wait 5ms extra. */ 511 delay(5000); 512 513 /* Finally, reset the ERX */ 514 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX); 515 /* Wait till it finishes */ 516 for (i=TRIES; i--; delay(100)) 517 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_RX) == 0) 518 break; 519 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_RX) != 0) { 520 printf("%s: cannot reset receiver\n", 521 sc->sc_dev.dv_xname); 522 return (1); 523 } 524 return (0); 525 } 526 527 528 /* 529 * Reset the transmitter 530 */ 531 int 532 gem_reset_tx(struct gem_softc *sc) 533 { 534 bus_space_tag_t t = sc->sc_bustag; 535 bus_space_handle_t h = sc->sc_h; 536 int i; 537 538 /* 539 * Resetting while DMA is in progress can cause a bus hang, so we 540 * disable DMA first. 541 */ 542 gem_disable_tx(sc); 543 bus_space_write_4(t, h, GEM_TX_CONFIG, 0); 544 /* Wait till it finishes */ 545 for (i=TRIES; i--; delay(100)) 546 if ((bus_space_read_4(t, h, GEM_TX_CONFIG) & 1) == 0) 547 break; 548 if ((bus_space_read_4(t, h, GEM_TX_CONFIG) & 1) != 0) 549 printf("%s: cannot disable read dma\n", 550 sc->sc_dev.dv_xname); 551 552 /* Wait 5ms extra. */ 553 delay(5000); 554 555 /* Finally, reset the ETX */ 556 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_TX); 557 /* Wait till it finishes */ 558 for (i=TRIES; i--; delay(100)) 559 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_TX) == 0) 560 break; 561 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_TX) != 0) { 562 printf("%s: cannot reset receiver\n", 563 sc->sc_dev.dv_xname); 564 return (1); 565 } 566 return (0); 567 } 568 569 /* 570 * disable receiver. 571 */ 572 int 573 gem_disable_rx(struct gem_softc *sc) 574 { 575 bus_space_tag_t t = sc->sc_bustag; 576 bus_space_handle_t h = sc->sc_h; 577 int i; 578 u_int32_t cfg; 579 580 /* Flip the enable bit */ 581 cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 582 cfg &= ~GEM_MAC_RX_ENABLE; 583 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg); 584 585 /* Wait for it to finish */ 586 for (i=TRIES; i--; delay(100)) 587 if ((bus_space_read_4(t, h, GEM_MAC_RX_CONFIG) & 588 GEM_MAC_RX_ENABLE) == 0) 589 return (0); 590 return (1); 591 } 592 593 /* 594 * disable transmitter. 595 */ 596 int 597 gem_disable_tx(struct gem_softc *sc) 598 { 599 bus_space_tag_t t = sc->sc_bustag; 600 bus_space_handle_t h = sc->sc_h; 601 int i; 602 u_int32_t cfg; 603 604 /* Flip the enable bit */ 605 cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG); 606 cfg &= ~GEM_MAC_TX_ENABLE; 607 bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg); 608 609 /* Wait for it to finish */ 610 for (i=TRIES; i--; delay(100)) 611 if ((bus_space_read_4(t, h, GEM_MAC_TX_CONFIG) & 612 GEM_MAC_TX_ENABLE) == 0) 613 return (0); 614 return (1); 615 } 616 617 /* 618 * Initialize interface. 619 */ 620 int 621 gem_meminit(struct gem_softc *sc) 622 { 623 struct gem_rxsoft *rxs; 624 int i, error; 625 626 /* 627 * Initialize the transmit descriptor ring. 628 */ 629 memset((void *)sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 630 for (i = 0; i < GEM_NTXDESC; i++) { 631 sc->sc_txdescs[i].gd_flags = 0; 632 sc->sc_txdescs[i].gd_addr = 0; 633 } 634 GEM_CDTXSYNC(sc, 0, GEM_NTXDESC, 635 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 636 sc->sc_txfree = GEM_NTXDESC; 637 sc->sc_txnext = 0; 638 639 /* 640 * Initialize the receive descriptor and receive job 641 * descriptor rings. 642 */ 643 for (i = 0; i < GEM_NRXDESC; i++) { 644 rxs = &sc->sc_rxsoft[i]; 645 if (rxs->rxs_mbuf == NULL) { 646 if ((error = gem_add_rxbuf(sc, i)) != 0) { 647 printf("%s: unable to allocate or map rx " 648 "buffer %d, error = %d\n", 649 sc->sc_dev.dv_xname, i, error); 650 /* 651 * XXX Should attempt to run with fewer receive 652 * XXX buffers instead of just failing. 653 */ 654 gem_rxdrain(sc); 655 return (1); 656 } 657 } else 658 GEM_INIT_RXDESC(sc, i); 659 } 660 sc->sc_rxptr = 0; 661 662 return (0); 663 } 664 665 static int 666 gem_ringsize(int sz) 667 { 668 int v; 669 670 switch (sz) { 671 case 32: 672 v = GEM_RING_SZ_32; 673 break; 674 case 64: 675 v = GEM_RING_SZ_64; 676 break; 677 case 128: 678 v = GEM_RING_SZ_128; 679 break; 680 case 256: 681 v = GEM_RING_SZ_256; 682 break; 683 case 512: 684 v = GEM_RING_SZ_512; 685 break; 686 case 1024: 687 v = GEM_RING_SZ_1024; 688 break; 689 case 2048: 690 v = GEM_RING_SZ_2048; 691 break; 692 case 4096: 693 v = GEM_RING_SZ_4096; 694 break; 695 case 8192: 696 v = GEM_RING_SZ_8192; 697 break; 698 default: 699 printf("gem: invalid Receive Descriptor ring size\n"); 700 break; 701 } 702 return (v); 703 } 704 705 /* 706 * Initialization of interface; set up initialization block 707 * and transmit/receive descriptor rings. 708 */ 709 int 710 gem_init(struct ifnet *ifp) 711 { 712 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 713 bus_space_tag_t t = sc->sc_bustag; 714 bus_space_handle_t h = sc->sc_h; 715 int s; 716 u_int32_t v; 717 718 s = splnet(); 719 720 DPRINTF(sc, ("%s: gem_init: calling stop\n", sc->sc_dev.dv_xname)); 721 /* 722 * Initialization sequence. The numbered steps below correspond 723 * to the sequence outlined in section 6.3.5.1 in the Ethernet 724 * Channel Engine manual (part of the PCIO manual). 725 * See also the STP2002-STQ document from Sun Microsystems. 726 */ 727 728 /* step 1 & 2. Reset the Ethernet Channel */ 729 gem_stop(ifp, 0); 730 if (gem_opdebug) printf("in init\n"); 731 gem_reset(sc); 732 DPRINTF(sc, ("%s: gem_init: restarting\n", sc->sc_dev.dv_xname)); 733 734 /* Re-initialize the MIF */ 735 gem_mifinit(sc); 736 737 /* Call MI reset function if any */ 738 if (sc->sc_hwreset) 739 (*sc->sc_hwreset)(sc); 740 741 /* step 3. Setup data structures in host memory */ 742 gem_meminit(sc); 743 744 /* step 4. TX MAC registers & counters */ 745 gem_init_regs(sc); 746 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 747 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 748 ETHER_VLAN_ENCAP_LEN + ETHER_MAX_LEN + sizeof(struct ether_header): 749 ETHER_MAX_LEN + sizeof(struct ether_header)) | (0x2000<<16)); 750 751 /* step 5. RX MAC registers & counters */ 752 gem_setladrf(sc); 753 754 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 755 bus_space_write_8(t, h, GEM_TX_RING_PTR, 756 GEM_CDTXADDR(sc, 0)); 757 /* Yeeech. The following has endianness issues. */ 758 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 759 (((uint64_t)GEM_CDRXADDR(sc, 0))>>32)); 760 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, 761 GEM_CDRXADDR(sc, 0)); 762 763 /* step 8. Global Configuration & Interrupt Mask */ 764 bus_space_write_4(t, h, GEM_INTMASK, 765 ~(GEM_INTR_TX_INTME| 766 GEM_INTR_TX_EMPTY| 767 GEM_INTR_RX_DONE|GEM_INTR_RX_NOBUF| 768 GEM_INTR_RX_TAG_ERR|GEM_INTR_PCS| 769 GEM_INTR_MAC_CONTROL|GEM_INTR_MIF| 770 GEM_INTR_BERR)); 771 bus_space_write_4(t, h, GEM_MAC_RX_MASK, 0); /* XXXX */ 772 bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXXX */ 773 bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 0); /* XXXX */ 774 #if 0 775 if (!sc->sc_pci) { 776 /* Config SBus */ 777 switch (sc->sc_burst) { 778 default: 779 v = 0; 780 break; 781 case 16: 782 v = GEM_SEB_CFG_BURST16; 783 break; 784 case 32: 785 v = GEM_SEB_CFG_BURST32; 786 break; 787 case 64: 788 v = GEM_SEB_CFG_BURST64; 789 break; 790 } 791 bus_space_write_4(t, seb, GEM_SEBI_CFG, 792 v|GE_SIOCFG_PARITY|GE_SIOCFG_BMODE64); 793 } 794 #endif 795 /* step 9. ETX Configuration: use mostly default values */ 796 797 /* Enable DMA */ 798 v = gem_ringsize(GEM_NTXDESC /*XXX*/); 799 bus_space_write_4(t, h, GEM_TX_CONFIG, 800 v|GEM_TX_CONFIG_TXDMA_EN| 801 ((0x400<<10)&GEM_TX_CONFIG_TXFIFO_TH)); 802 bus_space_write_4(t, h, GEM_TX_KICK, sc->sc_txnext); 803 804 /* step 10. ERX Configuration */ 805 806 /* Encode Receive Descriptor ring size: four possible values */ 807 v = gem_ringsize(GEM_NRXDESC /*XXX*/); 808 809 /* Enable DMA */ 810 bus_space_write_4(t, h, GEM_RX_CONFIG, 811 v|(GEM_THRSH_1024<<GEM_RX_CONFIG_FIFO_THRS_SHIFT)| 812 (2<<GEM_RX_CONFIG_FBOFF_SHFT)|GEM_RX_CONFIG_RXDMA_EN| 813 (0<<GEM_RX_CONFIG_CXM_START_SHFT)); 814 /* 815 * The following value is for an OFF Threshold of about 15.5 Kbytes 816 * and an ON Threshold of 4K bytes. 817 */ 818 bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH, 0xf8 | (0x40 << 12)); 819 bus_space_write_4(t, h, GEM_RX_BLANKING, (2<<12)|6); 820 821 /* step 11. Configure Media */ 822 gem_mii_statchg(&sc->sc_dev); 823 824 /* XXXX Serial link needs a whole different setup. */ 825 826 827 /* step 12. RX_MAC Configuration Register */ 828 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 829 v |= GEM_MAC_RX_ENABLE; 830 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 831 832 /* step 14. Issue Transmit Pending command */ 833 834 /* Call MI initialization function if any */ 835 if (sc->sc_hwinit) 836 (*sc->sc_hwinit)(sc); 837 838 839 /* step 15. Give the reciever a swift kick */ 840 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4); 841 842 /* Start the one second timer. */ 843 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 844 845 ifp->if_flags |= IFF_RUNNING; 846 ifp->if_flags &= ~IFF_OACTIVE; 847 ifp->if_timer = 0; 848 splx(s); 849 850 return (0); 851 } 852 853 /* 854 * Compare two Ether/802 addresses for equality, inlined and unrolled for 855 * speed. 856 */ 857 static __inline__ int 858 ether_cmp(a, b) 859 u_char *a, *b; 860 { 861 862 if (a[5] != b[5] || a[4] != b[4] || a[3] != b[3] || 863 a[2] != b[2] || a[1] != b[1] || a[0] != b[0]) 864 return (0); 865 return (1); 866 } 867 868 869 void 870 gem_init_regs(struct gem_softc *sc) 871 { 872 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 873 bus_space_tag_t t = sc->sc_bustag; 874 bus_space_handle_t h = sc->sc_h; 875 876 /* These regs are not cleared on reset */ 877 sc->sc_inited = 0; 878 if (!sc->sc_inited) { 879 880 /* Wooo. Magic values. */ 881 bus_space_write_4(t, h, GEM_MAC_IPG0, 0); 882 bus_space_write_4(t, h, GEM_MAC_IPG1, 8); 883 bus_space_write_4(t, h, GEM_MAC_IPG2, 4); 884 885 bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 886 /* Max frame and max burst size */ 887 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 888 (ifp->if_mtu+18) | (0x2000<<16)/* Burst size */); 889 bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x7); 890 bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x4); 891 bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10); 892 /* Dunno.... */ 893 bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088); 894 bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED, 895 ((sc->sc_enaddr[5]<<8)|sc->sc_enaddr[4])&0x3ff); 896 /* Secondary MAC addr set to 0:0:0:0:0:0 */ 897 bus_space_write_4(t, h, GEM_MAC_ADDR3, 0); 898 bus_space_write_4(t, h, GEM_MAC_ADDR4, 0); 899 bus_space_write_4(t, h, GEM_MAC_ADDR5, 0); 900 /* MAC control addr set to 0:1:c2:0:1:80 */ 901 bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001); 902 bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200); 903 bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180); 904 905 /* MAC filter addr set to 0:0:0:0:0:0 */ 906 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0); 907 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0); 908 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0); 909 910 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0); 911 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0); 912 913 sc->sc_inited = 1; 914 } 915 916 /* Counters need to be zeroed */ 917 bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0); 918 bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0); 919 bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0); 920 bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0); 921 bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0); 922 bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0); 923 bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0); 924 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 925 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 926 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 927 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 928 929 /* Un-pause stuff */ 930 #if 0 931 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); 932 #else 933 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0); 934 #endif 935 936 /* 937 * Set the station address. 938 */ 939 bus_space_write_4(t, h, GEM_MAC_ADDR0, 940 (sc->sc_enaddr[4]<<8) | sc->sc_enaddr[5]); 941 bus_space_write_4(t, h, GEM_MAC_ADDR1, 942 (sc->sc_enaddr[2]<<8) | sc->sc_enaddr[3]); 943 bus_space_write_4(t, h, GEM_MAC_ADDR2, 944 (sc->sc_enaddr[0]<<8) | sc->sc_enaddr[1]); 945 946 } 947 948 949 950 void 951 gem_start(ifp) 952 struct ifnet *ifp; 953 { 954 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 955 struct mbuf *m0, *m; 956 struct gem_txsoft *txs, *last_txs; 957 bus_dmamap_t dmamap; 958 int error, firsttx, nexttx, lasttx, ofree, seg; 959 960 if (gem_opdebug) printf("in start free %x next %x kick %x\n", 961 sc->sc_txfree, sc->sc_txnext, 962 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_KICK)); 963 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 964 return; 965 966 /* 967 * Remember the previous number of free descriptors and 968 * the first descriptor we'll use. 969 */ 970 ofree = sc->sc_txfree; 971 firsttx = sc->sc_txnext; 972 973 DPRINTF(sc, ("%s: gem_start: txfree %d, txnext %d\n", 974 sc->sc_dev.dv_xname, ofree, firsttx)); 975 976 /* 977 * Loop through the send queue, setting up transmit descriptors 978 * until we drain the queue, or use up all available transmit 979 * descriptors. 980 */ 981 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 982 sc->sc_txfree != 0) { 983 /* 984 * Grab a packet off the queue. 985 */ 986 IFQ_POLL(&ifp->if_snd, m0); 987 if (m0 == NULL) 988 break; 989 m = NULL; 990 991 dmamap = txs->txs_dmamap; 992 993 /* 994 * Load the DMA map. If this fails, the packet either 995 * didn't fit in the alloted number of segments, or we were 996 * short on resources. In this case, we'll copy and try 997 * again. 998 */ 999 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m0, 1000 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1001 MGETHDR(m, M_DONTWAIT, MT_DATA); 1002 if (m == NULL) { 1003 printf("%s: unable to allocate Tx mbuf\n", 1004 sc->sc_dev.dv_xname); 1005 break; 1006 } 1007 if (m0->m_pkthdr.len > MHLEN) { 1008 MCLGET(m, M_DONTWAIT); 1009 if ((m->m_flags & M_EXT) == 0) { 1010 printf("%s: unable to allocate Tx " 1011 "cluster\n", sc->sc_dev.dv_xname); 1012 m_freem(m); 1013 break; 1014 } 1015 } 1016 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 1017 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1018 error = bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, 1019 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1020 if (error) { 1021 printf("%s: unable to load Tx buffer, " 1022 "error = %d\n", sc->sc_dev.dv_xname, error); 1023 break; 1024 } 1025 } 1026 1027 /* 1028 * Ensure we have enough descriptors free to describe 1029 * the packet. 1030 */ 1031 if (dmamap->dm_nsegs > sc->sc_txfree) { 1032 /* 1033 * Not enough free descriptors to transmit this 1034 * packet. We haven't committed to anything yet, 1035 * so just unload the DMA map, put the packet 1036 * back on the queue, and punt. Notify the upper 1037 * layer that there are no more slots left. 1038 * 1039 * XXX We could allocate an mbuf and copy, but 1040 * XXX it is worth it? 1041 */ 1042 ifp->if_flags |= IFF_OACTIVE; 1043 bus_dmamap_unload(sc->sc_dmatag, dmamap); 1044 if (m != NULL) 1045 m_freem(m); 1046 break; 1047 } 1048 1049 IFQ_DEQUEUE(&ifp->if_snd, m0); 1050 if (m != NULL) { 1051 m_freem(m0); 1052 m0 = m; 1053 } 1054 1055 /* 1056 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1057 */ 1058 1059 /* Sync the DMA map. */ 1060 bus_dmamap_sync(sc->sc_dmatag, dmamap, 0, dmamap->dm_mapsize, 1061 BUS_DMASYNC_PREWRITE); 1062 1063 /* 1064 * Initialize the transmit descriptors. 1065 */ 1066 for (nexttx = sc->sc_txnext, seg = 0; 1067 seg < dmamap->dm_nsegs; 1068 seg++, nexttx = GEM_NEXTTX(nexttx)) { 1069 uint64_t flags; 1070 1071 /* 1072 * If this is the first descriptor we're 1073 * enqueueing, set the start of packet flag, 1074 * and the checksum stuff if we want the hardware 1075 * to do it. 1076 */ 1077 sc->sc_txdescs[nexttx].gd_addr = 1078 htole64(dmamap->dm_segs[seg].ds_addr); 1079 flags = dmamap->dm_segs[seg].ds_len & GEM_TD_BUFSIZE; 1080 if (nexttx == firsttx) { 1081 flags |= GEM_TD_START_OF_PACKET; 1082 } 1083 if (seg == dmamap->dm_nsegs - 1) { 1084 flags |= GEM_TD_END_OF_PACKET; 1085 } 1086 sc->sc_txdescs[nexttx].gd_flags = 1087 htole64(flags); 1088 lasttx = nexttx; 1089 } 1090 1091 #ifdef GEM_DEBUG 1092 if (ifp->if_flags & IFF_DEBUG) { 1093 printf(" gem_start %p transmit chain:\n", txs); 1094 for (seg = sc->sc_txnext;; seg = GEM_NEXTTX(seg)) { 1095 printf("descriptor %d:\t", seg); 1096 printf("gd_flags: 0x%016llx\t", (long long) 1097 le64toh(sc->sc_txdescs[seg].gd_flags)); 1098 printf("gd_addr: 0x%016llx\n", (long long) 1099 le64toh(sc->sc_txdescs[seg].gd_addr)); 1100 if (seg == lasttx) 1101 break; 1102 } 1103 } 1104 #endif 1105 1106 /* Sync the descriptors we're using. */ 1107 GEM_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1108 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1109 1110 /* 1111 * Store a pointer to the packet so we can free it later, 1112 * and remember what txdirty will be once the packet is 1113 * done. 1114 */ 1115 txs->txs_mbuf = m0; 1116 txs->txs_firstdesc = sc->sc_txnext; 1117 txs->txs_lastdesc = lasttx; 1118 txs->txs_ndescs = dmamap->dm_nsegs; 1119 1120 /* Advance the tx pointer. */ 1121 sc->sc_txfree -= dmamap->dm_nsegs; 1122 sc->sc_txnext = nexttx; 1123 1124 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs, txs_q); 1125 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1126 1127 last_txs = txs; 1128 1129 #if NBPFILTER > 0 1130 /* 1131 * Pass the packet to any BPF listeners. 1132 */ 1133 if (ifp->if_bpf) 1134 bpf_mtap(ifp->if_bpf, m0); 1135 #endif /* NBPFILTER > 0 */ 1136 } 1137 1138 if (txs == NULL || sc->sc_txfree == 0) { 1139 /* No more slots left; notify upper layer. */ 1140 ifp->if_flags |= IFF_OACTIVE; 1141 } 1142 1143 if (sc->sc_txfree != ofree) { 1144 DPRINTF(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 1145 sc->sc_dev.dv_xname, lasttx, firsttx)); 1146 #if 0 1147 /* 1148 * Cause a transmit interrupt to happen on the 1149 * last packet we enqueued. 1150 */ 1151 sc->sc_txdescs[lasttx].gd_flags |= htole64(GEM_TD_INTERRUPT_ME); 1152 GEM_CDTXSYNC(sc, lasttx, 1, 1153 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1154 #endif 1155 /* 1156 * The entire packet chain is set up. 1157 * Kick the transmitter. 1158 */ 1159 DPRINTF(sc, ("%s: gem_start: kicking tx %d\n", 1160 sc->sc_dev.dv_xname, nexttx)); 1161 if (gem_opdebug) { 1162 int i; 1163 int64_t pa; 1164 i = bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_KICK); 1165 printf("GEM_TX_KICK %x GEM_TX_DATA_PTR %llx GEM_TX_RING_PTR %llx\n", 1166 i, 1167 (long long)bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_DATA_PTR), 1168 (long long)bus_space_read_8(sc->sc_bustag, sc->sc_h, GEM_TX_RING_PTR)); 1169 printf("descriptor %d: ", (i = lasttx)); 1170 printf("gd_flags: 0x%016llx\t", (long long) 1171 le64toh(sc->sc_txdescs[i].gd_flags)); 1172 pa = le64toh(sc->sc_txdescs[i].gd_addr); 1173 printf("gd_addr: 0x%016llx\n", (long long) pa); 1174 printf("GEM_TX_CONFIG %x GEM_MAC_XIF_CONFIG %x GEM_MAC_TX_CONFIG %x\n", 1175 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_CONFIG), 1176 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_XIF_CONFIG), 1177 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_TX_CONFIG)); 1178 } 1179 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_TX_KICK, 1180 sc->sc_txnext); 1181 if (gem_opdebug) printf("gem_start: txkick %x\n", 1182 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_KICK)); 1183 1184 /* Set a watchdog timer in case the chip flakes out. */ 1185 ifp->if_timer = 5; 1186 DPRINTF(sc, ("%s: gem_start: watchdog %d\n", 1187 sc->sc_dev.dv_xname, ifp->if_timer)); 1188 } 1189 } 1190 1191 /* 1192 * Transmit interrupt. 1193 */ 1194 int 1195 gem_tint(sc) 1196 struct gem_softc *sc; 1197 { 1198 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1199 bus_space_tag_t t = sc->sc_bustag; 1200 bus_space_handle_t mac = sc->sc_h; 1201 struct gem_txsoft *txs; 1202 int txlast; 1203 1204 1205 DPRINTF(sc, ("%s: gem_tint: sc_flags 0x%08x\n", 1206 sc->sc_dev.dv_xname, sc->sc_flags)); 1207 1208 /* 1209 * Unload collision counters 1210 */ 1211 ifp->if_collisions += 1212 bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) + 1213 bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT) + 1214 bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) + 1215 bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT); 1216 1217 /* 1218 * then clear the hardware counters. 1219 */ 1220 bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0); 1221 bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0); 1222 bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0); 1223 bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0); 1224 1225 /* 1226 * Go through our Tx list and free mbufs for those 1227 * frames that have been transmitted. 1228 */ 1229 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1230 GEM_CDTXSYNC(sc, txs->txs_lastdesc, 1231 txs->txs_ndescs, 1232 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1233 1234 #ifdef GEM_DEBUG 1235 if (ifp->if_flags & IFF_DEBUG) { 1236 int i; 1237 printf(" txsoft %p transmit chain:\n", txs); 1238 for (i = txs->txs_firstdesc;; i = GEM_NEXTTX(i)) { 1239 printf("descriptor %d: ", i); 1240 printf("gd_flags: 0x%016llx\t", (long long) 1241 le64toh(sc->sc_txdescs[i].gd_flags)); 1242 printf("gd_addr: 0x%016llx\n", (long long) 1243 le64toh(sc->sc_txdescs[i].gd_addr)); 1244 if (i == txs->txs_lastdesc) 1245 break; 1246 } 1247 } 1248 #endif 1249 1250 /* 1251 * In theory, we could harveast some descriptors before 1252 * the ring is empty, but that's a bit complicated. 1253 * 1254 * GEM_TX_COMPLETION points to the last descriptor 1255 * processed +1. 1256 */ 1257 txlast = bus_space_read_4(t, mac, GEM_TX_COMPLETION); 1258 DPRINTF(sc, 1259 ("gem_tint: txs->txs_lastdesc = %d, txlast = %d\n", 1260 txs->txs_lastdesc, txlast)); 1261 if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1262 if ((txlast >= txs->txs_firstdesc) && 1263 (txlast <= txs->txs_lastdesc)) 1264 break; 1265 } else { 1266 /* Ick -- this command wraps */ 1267 if ((txlast >= txs->txs_firstdesc) || 1268 (txlast <= txs->txs_lastdesc)) 1269 break; 1270 } 1271 1272 DPRINTF(sc, ("gem_tint: releasing a desc\n")); 1273 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs, txs_q); 1274 1275 sc->sc_txfree += txs->txs_ndescs; 1276 1277 if (txs->txs_mbuf == NULL) { 1278 #ifdef DIAGNOSTIC 1279 panic("gem_txintr: null mbuf"); 1280 #endif 1281 } 1282 1283 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 1284 0, txs->txs_dmamap->dm_mapsize, 1285 BUS_DMASYNC_POSTWRITE); 1286 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 1287 m_freem(txs->txs_mbuf); 1288 txs->txs_mbuf = NULL; 1289 1290 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1291 1292 ifp->if_opackets++; 1293 } 1294 1295 DPRINTF(sc, ("gem_tint: GEM_TX_STATE_MACHINE %x " 1296 "GEM_TX_DATA_PTR %llx " 1297 "GEM_TX_COMPLETION %x\n", 1298 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_STATE_MACHINE), 1299 (long long)bus_space_read_8(sc->sc_bustag, sc->sc_h, 1300 GEM_TX_DATA_PTR), 1301 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_COMPLETION))); 1302 1303 gem_start(ifp); 1304 1305 if (SIMPLEQ_FIRST(&sc->sc_txdirtyq) == NULL) 1306 ifp->if_timer = 0; 1307 DPRINTF(sc, ("%s: gem_tint: watchdog %d\n", 1308 sc->sc_dev.dv_xname, ifp->if_timer)); 1309 1310 return (1); 1311 } 1312 1313 /* 1314 * Receive interrupt. 1315 */ 1316 int 1317 gem_rint(sc) 1318 struct gem_softc *sc; 1319 { 1320 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1321 bus_space_tag_t t = sc->sc_bustag; 1322 bus_space_handle_t h = sc->sc_h; 1323 struct ether_header *eh; 1324 struct gem_rxsoft *rxs; 1325 struct mbuf *m; 1326 u_int64_t rxstat; 1327 int i, len; 1328 1329 DPRINTF(sc, ("%s: gem_rint: sc_flags 0x%08x\n", 1330 sc->sc_dev.dv_xname, sc->sc_flags)); 1331 /* 1332 * XXXX Read the lastrx only once at the top for speed. 1333 */ 1334 DPRINTF(sc, ("gem_rint: sc->rxptr %d, complete %d\n", 1335 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION))); 1336 for (i = sc->sc_rxptr; i != bus_space_read_4(t, h, GEM_RX_COMPLETION); 1337 i = GEM_NEXTRX(i)) { 1338 rxs = &sc->sc_rxsoft[i]; 1339 1340 GEM_CDRXSYNC(sc, i, 1341 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1342 1343 rxstat = le64toh(sc->sc_rxdescs[i].gd_flags); 1344 1345 if (rxstat & GEM_RD_OWN) { 1346 printf("gem_rint: completed descriptor " 1347 "still owned %d\n", i); 1348 /* 1349 * We have processed all of the receive buffers. 1350 */ 1351 break; 1352 } 1353 1354 if (rxstat & GEM_RD_BAD_CRC) { 1355 printf("%s: receive error: CRC error\n", 1356 sc->sc_dev.dv_xname); 1357 GEM_INIT_RXDESC(sc, i); 1358 continue; 1359 } 1360 1361 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1362 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1363 #ifdef GEM_DEBUG 1364 if (ifp->if_flags & IFF_DEBUG) { 1365 printf(" rxsoft %p descriptor %d: ", rxs, i); 1366 printf("gd_flags: 0x%016llx\t", (long long) 1367 le64toh(sc->sc_rxdescs[i].gd_flags)); 1368 printf("gd_addr: 0x%016llx\n", (long long) 1369 le64toh(sc->sc_rxdescs[i].gd_addr)); 1370 } 1371 #endif 1372 1373 /* 1374 * No errors; receive the packet. Note the Gem 1375 * includes the CRC with every packet. 1376 */ 1377 len = GEM_RD_BUFLEN(rxstat); 1378 1379 /* 1380 * We align the mbuf data in gem_add_rxbuf() so 1381 * we can use __NO_STRICT_ALIGNMENT here 1382 */ 1383 #define __NO_STRICT_ALIGNMENT 1384 #ifdef __NO_STRICT_ALIGNMENT 1385 /* 1386 * Allocate a new mbuf cluster. If that fails, we are 1387 * out of memory, and must drop the packet and recycle 1388 * the buffer that's already attached to this descriptor. 1389 */ 1390 m = rxs->rxs_mbuf; 1391 if (gem_add_rxbuf(sc, i) != 0) { 1392 ifp->if_ierrors++; 1393 GEM_INIT_RXDESC(sc, i); 1394 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1395 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1396 continue; 1397 } 1398 m->m_data += 2; /* We're already off by two */ 1399 #else 1400 /* 1401 * The Gem's receive buffers must be 4-byte aligned. 1402 * But this means that the data after the Ethernet header 1403 * is misaligned. We must allocate a new buffer and 1404 * copy the data, shifted forward 2 bytes. 1405 */ 1406 MGETHDR(m, M_DONTWAIT, MT_DATA); 1407 if (m == NULL) { 1408 dropit: 1409 ifp->if_ierrors++; 1410 GEM_INIT_RXDESC(sc, i); 1411 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1412 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1413 continue; 1414 } 1415 if (len > (MHLEN - 2)) { 1416 MCLGET(m, M_DONTWAIT); 1417 if ((m->m_flags & M_EXT) == 0) { 1418 m_freem(m); 1419 goto dropit; 1420 } 1421 } 1422 m->m_data += 2; 1423 1424 /* 1425 * Note that we use clusters for incoming frames, so the 1426 * buffer is virtually contiguous. 1427 */ 1428 memcpy(mtod(m, caddr_t), mtod(rxs->rxs_mbuf, caddr_t), len); 1429 1430 /* Allow the receive descriptor to continue using its mbuf. */ 1431 GEM_INIT_RXDESC(sc, i); 1432 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1433 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1434 #endif /* __NO_STRICT_ALIGNMENT */ 1435 1436 ifp->if_ipackets++; 1437 eh = mtod(m, struct ether_header *); 1438 m->m_flags |= M_HASFCS; 1439 m->m_pkthdr.rcvif = ifp; 1440 m->m_pkthdr.len = m->m_len = len; 1441 1442 #if NBPFILTER > 0 1443 /* 1444 * Pass this up to any BPF listeners, but only 1445 * pass it up the stack if its for us. 1446 */ 1447 if (ifp->if_bpf) 1448 bpf_mtap(ifp->if_bpf, m); 1449 #endif /* NPBFILTER > 0 */ 1450 1451 #if 0 1452 /* 1453 * We sometimes have to run the 21140 in Hash-Only 1454 * mode. If we're in that mode, and not in promiscuous 1455 * mode, and we have a unicast packet that isn't for 1456 * us, then drop it. 1457 */ 1458 if (sc->sc_filtmode == TDCTL_Tx_FT_HASHONLY && 1459 (ifp->if_flags & IFF_PROMISC) == 0 && 1460 ETHER_IS_MULTICAST(eh->ether_dhost) == 0 && 1461 memcmp(LLADDR(ifp->if_sadl), eh->ether_dhost, 1462 ETHER_ADDR_LEN) != 0) { 1463 m_freem(m); 1464 continue; 1465 } 1466 #endif 1467 1468 /* Pass it on. */ 1469 (*ifp->if_input)(ifp, m); 1470 } 1471 1472 /* Update the receive pointer. */ 1473 sc->sc_rxptr = i; 1474 bus_space_write_4(t, h, GEM_RX_KICK, i); 1475 1476 DPRINTF(sc, ("gem_rint: done sc->rxptr %d, complete %d\n", 1477 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION))); 1478 1479 return (1); 1480 } 1481 1482 1483 /* 1484 * gem_add_rxbuf: 1485 * 1486 * Add a receive buffer to the indicated descriptor. 1487 */ 1488 int 1489 gem_add_rxbuf(struct gem_softc *sc, int idx) 1490 { 1491 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1492 struct mbuf *m; 1493 int error; 1494 1495 MGETHDR(m, M_DONTWAIT, MT_DATA); 1496 if (m == NULL) 1497 return (ENOBUFS); 1498 1499 MCLGET(m, M_DONTWAIT); 1500 if ((m->m_flags & M_EXT) == 0) { 1501 m_freem(m); 1502 return (ENOBUFS); 1503 } 1504 1505 #ifdef GEM_DEBUG 1506 /* bzero the packet to check dma */ 1507 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 1508 #endif 1509 1510 if (rxs->rxs_mbuf != NULL) 1511 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 1512 1513 rxs->rxs_mbuf = m; 1514 1515 error = bus_dmamap_load(sc->sc_dmatag, rxs->rxs_dmamap, 1516 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1517 BUS_DMA_READ|BUS_DMA_NOWAIT); 1518 if (error) { 1519 printf("%s: can't load rx DMA map %d, error = %d\n", 1520 sc->sc_dev.dv_xname, idx, error); 1521 panic("gem_add_rxbuf"); /* XXX */ 1522 } 1523 1524 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1525 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1526 1527 GEM_INIT_RXDESC(sc, idx); 1528 1529 return (0); 1530 } 1531 1532 1533 int 1534 gem_eint(sc, status) 1535 struct gem_softc *sc; 1536 u_int status; 1537 { 1538 char bits[128]; 1539 1540 if ((status & GEM_INTR_MIF) != 0) { 1541 printf("%s: XXXlink status changed\n", sc->sc_dev.dv_xname); 1542 return (1); 1543 } 1544 1545 printf("%s: status=%s\n", sc->sc_dev.dv_xname, 1546 bitmask_snprintf(status, GEM_INTR_BITS, bits, sizeof(bits))); 1547 return (1); 1548 } 1549 1550 1551 int 1552 gem_intr(v) 1553 void *v; 1554 { 1555 struct gem_softc *sc = (struct gem_softc *)v; 1556 bus_space_tag_t t = sc->sc_bustag; 1557 bus_space_handle_t seb = sc->sc_h; 1558 u_int32_t status; 1559 int r = 0; 1560 1561 char bits[128]; 1562 1563 status = bus_space_read_4(t, seb, GEM_STATUS); 1564 DPRINTF(sc, ("%s: gem_intr: cplt %xstatus %s\n", 1565 sc->sc_dev.dv_xname, (status>>19), 1566 bitmask_snprintf(status, GEM_INTR_BITS, bits, sizeof(bits)))); 1567 if (gem_opdebug) printf("%s: gem_intr: cplt %x status %s\n", 1568 sc->sc_dev.dv_xname, (status>>19), 1569 bitmask_snprintf(status, GEM_INTR_BITS, bits, sizeof(bits))); 1570 if (gem_opdebug && (status & GEM_INTR_TX_DONE)) { 1571 int i; 1572 int64_t pa; 1573 i = bus_space_read_4(t, seb, GEM_TX_KICK); 1574 printf("GEM_TX_KICK %x GEM_TX_DATA_PTR %llx GEM_TX_RING_PTR %llx\n", 1575 i, (long long)bus_space_read_4(t, seb, GEM_TX_DATA_PTR), 1576 (long long)bus_space_read_8(t, seb, GEM_TX_RING_PTR)); 1577 printf("descriptor %d: ", --i); 1578 printf("gd_flags: 0x%016llx\t", (long long) 1579 le64toh(sc->sc_txdescs[i].gd_flags)); 1580 pa = le64toh(sc->sc_txdescs[i].gd_addr); 1581 printf("gd_addr: 0x%016llx\n", (long long) pa); 1582 printf("GEM_TX_CONFIG %x GEM_MAC_XIF_CONFIG %x GEM_MAC_TX_CONFIG %x " 1583 "GEM_MAC_TX_STATUS %x\n", 1584 bus_space_read_4(t, seb, GEM_TX_CONFIG), 1585 bus_space_read_4(t, seb, GEM_MAC_XIF_CONFIG), 1586 bus_space_read_4(t, seb, GEM_MAC_TX_CONFIG), 1587 bus_space_read_4(t, seb, GEM_MAC_TX_STATUS)); 1588 } 1589 1590 if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0) 1591 r |= gem_eint(sc, status); 1592 1593 if ((status & 1594 (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) 1595 != 0) 1596 r |= gem_tint(sc); 1597 1598 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) 1599 r |= gem_rint(sc); 1600 1601 /* We should eventually do more than just print out error stats. */ 1602 if (status & GEM_INTR_TX_MAC) { 1603 int txstat = bus_space_read_4(t, seb, GEM_MAC_TX_STATUS); 1604 if (txstat & ~GEM_MAC_TX_XMIT_DONE) 1605 printf("MAC tx fault, status %x\n", txstat); 1606 } 1607 if (status & GEM_INTR_RX_MAC) { 1608 int rxstat = bus_space_read_4(t, seb, GEM_MAC_RX_STATUS); 1609 if (rxstat & ~GEM_MAC_RX_DONE) 1610 printf("MAC rx fault, status %x\n", rxstat); 1611 } 1612 return (r); 1613 } 1614 1615 1616 void 1617 gem_watchdog(ifp) 1618 struct ifnet *ifp; 1619 { 1620 struct gem_softc *sc = ifp->if_softc; 1621 1622 DPRINTF(sc, ("gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x " 1623 "GEM_MAC_RX_CONFIG %x\n", 1624 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_CONFIG), 1625 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_STATUS), 1626 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_CONFIG))); 1627 1628 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1629 ++ifp->if_oerrors; 1630 1631 /* Try to get more packets going. */ 1632 // gem_reset(sc); 1633 gem_start(ifp); 1634 } 1635 1636 /* 1637 * Initialize the MII Management Interface 1638 */ 1639 void 1640 gem_mifinit(sc) 1641 struct gem_softc *sc; 1642 { 1643 bus_space_tag_t t = sc->sc_bustag; 1644 bus_space_handle_t mif = sc->sc_h; 1645 1646 /* Configure the MIF in frame mode */ 1647 sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1648 sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA; 1649 bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config); 1650 } 1651 1652 /* 1653 * MII interface 1654 * 1655 * The GEM MII interface supports at least three different operating modes: 1656 * 1657 * Bitbang mode is implemented using data, clock and output enable registers. 1658 * 1659 * Frame mode is implemented by loading a complete frame into the frame 1660 * register and polling the valid bit for completion. 1661 * 1662 * Polling mode uses the frame register but completion is indicated by 1663 * an interrupt. 1664 * 1665 */ 1666 static int 1667 gem_mii_readreg(self, phy, reg) 1668 struct device *self; 1669 int phy, reg; 1670 { 1671 struct gem_softc *sc = (void *)self; 1672 bus_space_tag_t t = sc->sc_bustag; 1673 bus_space_handle_t mif = sc->sc_h; 1674 int n; 1675 u_int32_t v; 1676 1677 #ifdef GEM_DEBUG1 1678 if (sc->sc_debug) 1679 printf("gem_mii_readreg: phy %d reg %d\n", phy, reg); 1680 #endif 1681 1682 #if 0 1683 /* Select the desired PHY in the MIF configuration register */ 1684 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1685 /* Clear PHY select bit */ 1686 v &= ~GEM_MIF_CONFIG_PHY_SEL; 1687 if (phy == GEM_PHYAD_EXTERNAL) 1688 /* Set PHY select bit to get at external device */ 1689 v |= GEM_MIF_CONFIG_PHY_SEL; 1690 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 1691 #endif 1692 1693 /* Construct the frame command */ 1694 v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) | 1695 GEM_MIF_FRAME_READ; 1696 1697 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1698 for (n = 0; n < 100; n++) { 1699 DELAY(1); 1700 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1701 if (v & GEM_MIF_FRAME_TA0) 1702 return (v & GEM_MIF_FRAME_DATA); 1703 } 1704 1705 printf("%s: mii_read timeout\n", sc->sc_dev.dv_xname); 1706 return (0); 1707 } 1708 1709 static void 1710 gem_mii_writereg(self, phy, reg, val) 1711 struct device *self; 1712 int phy, reg, val; 1713 { 1714 struct gem_softc *sc = (void *)self; 1715 bus_space_tag_t t = sc->sc_bustag; 1716 bus_space_handle_t mif = sc->sc_h; 1717 int n; 1718 u_int32_t v; 1719 1720 #ifdef GEM_DEBUG1 1721 if (sc->sc_debug) 1722 printf("gem_mii_writereg: phy %d reg %d val %x\n", 1723 phy, reg, val); 1724 #endif 1725 1726 #if 0 1727 /* Select the desired PHY in the MIF configuration register */ 1728 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1729 /* Clear PHY select bit */ 1730 v &= ~GEM_MIF_CONFIG_PHY_SEL; 1731 if (phy == GEM_PHYAD_EXTERNAL) 1732 /* Set PHY select bit to get at external device */ 1733 v |= GEM_MIF_CONFIG_PHY_SEL; 1734 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 1735 #endif 1736 /* Construct the frame command */ 1737 v = GEM_MIF_FRAME_WRITE | 1738 (phy << GEM_MIF_PHY_SHIFT) | 1739 (reg << GEM_MIF_REG_SHIFT) | 1740 (val & GEM_MIF_FRAME_DATA); 1741 1742 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1743 for (n = 0; n < 100; n++) { 1744 DELAY(1); 1745 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1746 if (v & GEM_MIF_FRAME_TA0) 1747 return; 1748 } 1749 1750 printf("%s: mii_write timeout\n", sc->sc_dev.dv_xname); 1751 } 1752 1753 static void 1754 gem_mii_statchg(dev) 1755 struct device *dev; 1756 { 1757 struct gem_softc *sc = (void *)dev; 1758 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1759 int phy = sc->sc_phys[instance]; 1760 bus_space_tag_t t = sc->sc_bustag; 1761 bus_space_handle_t mac = sc->sc_h; 1762 u_int32_t v; 1763 1764 #ifdef GEM_DEBUG 1765 if (sc->sc_debug) 1766 printf("gem_mii_statchg: status change: phy = %d\n", phy); 1767 #endif 1768 1769 1770 /* Set tx full duplex options */ 1771 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0); 1772 delay(10000); /* reg must be cleared and delay before changing. */ 1773 v = GEM_MAC_TX_ENA_IPG0|GEM_MAC_TX_NGU|GEM_MAC_TX_NGU_LIMIT| 1774 GEM_MAC_TX_ENABLE; 1775 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) { 1776 v |= GEM_MAC_TX_IGN_CARRIER|GEM_MAC_TX_IGN_COLLIS; 1777 } 1778 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, v); 1779 1780 /* XIF Configuration */ 1781 /* We should really calculate all this rather than rely on defaults */ 1782 v = bus_space_read_4(t, mac, GEM_MAC_XIF_CONFIG); 1783 v = GEM_MAC_XIF_LINK_LED; 1784 v |= GEM_MAC_XIF_TX_MII_ENA; 1785 /* If an external transceiver is connected, enable its MII drivers */ 1786 sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG); 1787 if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) { 1788 /* External MII needs echo disable if half duplex. */ 1789 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1790 /* turn on full duplex LED */ 1791 v |= GEM_MAC_XIF_FDPLX_LED; 1792 else 1793 /* half duplex -- disable echo */ 1794 v |= GEM_MAC_XIF_ECHO_DISABL; 1795 } else 1796 /* Internal MII needs buf enable */ 1797 v |= GEM_MAC_XIF_MII_BUF_ENA; 1798 bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v); 1799 } 1800 1801 int 1802 gem_mediachange(ifp) 1803 struct ifnet *ifp; 1804 { 1805 struct gem_softc *sc = ifp->if_softc; 1806 1807 if (IFM_TYPE(sc->sc_media.ifm_media) != IFM_ETHER) 1808 return (EINVAL); 1809 1810 return (mii_mediachg(&sc->sc_mii)); 1811 } 1812 1813 void 1814 gem_mediastatus(ifp, ifmr) 1815 struct ifnet *ifp; 1816 struct ifmediareq *ifmr; 1817 { 1818 struct gem_softc *sc = ifp->if_softc; 1819 1820 if ((ifp->if_flags & IFF_UP) == 0) 1821 return; 1822 1823 mii_pollstat(&sc->sc_mii); 1824 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1825 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1826 } 1827 1828 int gem_ioctldebug = 0; 1829 /* 1830 * Process an ioctl request. 1831 */ 1832 int 1833 gem_ioctl(ifp, cmd, data) 1834 struct ifnet *ifp; 1835 u_long cmd; 1836 caddr_t data; 1837 { 1838 struct gem_softc *sc = ifp->if_softc; 1839 struct ifreq *ifr = (struct ifreq *)data; 1840 int s, error = 0; 1841 1842 1843 switch (cmd) { 1844 case SIOCGIFMEDIA: 1845 case SIOCSIFMEDIA: 1846 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1847 break; 1848 1849 default: 1850 error = ether_ioctl(ifp, cmd, data); 1851 if (error == ENETRESET) { 1852 /* 1853 * Multicast list has changed; set the hardware filter 1854 * accordingly. 1855 */ 1856 if (gem_ioctldebug) printf("reset1\n"); 1857 gem_init(ifp); 1858 delay(50000); 1859 error = 0; 1860 } 1861 break; 1862 } 1863 1864 /* Try to get things going again */ 1865 if (ifp->if_flags & IFF_UP) { 1866 if (gem_ioctldebug) printf("start\n"); 1867 gem_start(ifp); 1868 } 1869 splx(s); 1870 return (error); 1871 } 1872 1873 1874 void 1875 gem_shutdown(arg) 1876 void *arg; 1877 { 1878 struct gem_softc *sc = (struct gem_softc *)arg; 1879 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1880 1881 gem_stop(ifp, 1); 1882 } 1883 1884 /* 1885 * Set up the logical address filter. 1886 */ 1887 void 1888 gem_setladrf(sc) 1889 struct gem_softc *sc; 1890 { 1891 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1892 struct ether_multi *enm; 1893 struct ether_multistep step; 1894 struct ethercom *ec = &sc->sc_ethercom; 1895 bus_space_tag_t t = sc->sc_bustag; 1896 bus_space_handle_t h = sc->sc_h; 1897 u_char *cp; 1898 u_int32_t crc; 1899 u_int32_t hash[16]; 1900 u_int32_t v; 1901 int len; 1902 1903 /* Clear hash table */ 1904 memset(hash, 0, sizeof(hash)); 1905 1906 /* Get current RX configuration */ 1907 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 1908 1909 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1910 /* Turn on promiscuous mode; turn off the hash filter */ 1911 v |= GEM_MAC_RX_PROMISCUOUS; 1912 v &= ~GEM_MAC_RX_HASH_FILTER; 1913 ifp->if_flags |= IFF_ALLMULTI; 1914 goto chipit; 1915 } 1916 1917 /* Turn off promiscuous mode; turn on the hash filter */ 1918 v &= ~GEM_MAC_RX_PROMISCUOUS; 1919 v |= GEM_MAC_RX_HASH_FILTER; 1920 1921 /* 1922 * Set up multicast address filter by passing all multicast addresses 1923 * through a crc generator, and then using the high order 6 bits as an 1924 * index into the 256 bit logical address filter. The high order bit 1925 * selects the word, while the rest of the bits select the bit within 1926 * the word. 1927 */ 1928 1929 ETHER_FIRST_MULTI(step, ec, enm); 1930 while (enm != NULL) { 1931 if (ether_cmp(enm->enm_addrlo, enm->enm_addrhi)) { 1932 /* 1933 * We must listen to a range of multicast addresses. 1934 * For now, just accept all multicasts, rather than 1935 * trying to set only those filter bits needed to match 1936 * the range. (At this time, the only use of address 1937 * ranges is for IP multicast routing, for which the 1938 * range is big enough to require all bits set.) 1939 */ 1940 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1941 ifp->if_flags |= IFF_ALLMULTI; 1942 goto chipit; 1943 } 1944 1945 cp = enm->enm_addrlo; 1946 crc = 0xffffffff; 1947 for (len = sizeof(enm->enm_addrlo); --len >= 0;) { 1948 int octet = *cp++; 1949 int i; 1950 1951 #define MC_POLY_LE 0xedb88320UL /* mcast crc, little endian */ 1952 for (i = 0; i < 8; i++) { 1953 if ((crc & 1) ^ (octet & 1)) { 1954 crc >>= 1; 1955 crc ^= MC_POLY_LE; 1956 } else { 1957 crc >>= 1; 1958 } 1959 octet >>= 1; 1960 } 1961 } 1962 /* Just want the 8 most significant bits. */ 1963 crc >>= 24; 1964 1965 /* Set the corresponding bit in the filter. */ 1966 hash[crc >> 4] |= 1 << (crc & 0xf); 1967 1968 ETHER_NEXT_MULTI(step, enm); 1969 } 1970 1971 ifp->if_flags &= ~IFF_ALLMULTI; 1972 1973 chipit: 1974 /* Now load the hash table into the chip */ 1975 bus_space_write_4(t, h, GEM_MAC_HASH0, hash[0]); 1976 bus_space_write_4(t, h, GEM_MAC_HASH1, hash[1]); 1977 bus_space_write_4(t, h, GEM_MAC_HASH2, hash[2]); 1978 bus_space_write_4(t, h, GEM_MAC_HASH3, hash[3]); 1979 bus_space_write_4(t, h, GEM_MAC_HASH4, hash[4]); 1980 bus_space_write_4(t, h, GEM_MAC_HASH5, hash[5]); 1981 bus_space_write_4(t, h, GEM_MAC_HASH6, hash[6]); 1982 bus_space_write_4(t, h, GEM_MAC_HASH7, hash[7]); 1983 bus_space_write_4(t, h, GEM_MAC_HASH8, hash[8]); 1984 bus_space_write_4(t, h, GEM_MAC_HASH9, hash[9]); 1985 bus_space_write_4(t, h, GEM_MAC_HASH10, hash[10]); 1986 bus_space_write_4(t, h, GEM_MAC_HASH11, hash[11]); 1987 bus_space_write_4(t, h, GEM_MAC_HASH12, hash[12]); 1988 bus_space_write_4(t, h, GEM_MAC_HASH13, hash[13]); 1989 bus_space_write_4(t, h, GEM_MAC_HASH14, hash[14]); 1990 bus_space_write_4(t, h, GEM_MAC_HASH15, hash[15]); 1991 1992 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 1993 } 1994 1995 #if notyet 1996 1997 /* 1998 * gem_power: 1999 * 2000 * Power management (suspend/resume) hook. 2001 */ 2002 void 2003 gem_power(why, arg) 2004 int why; 2005 void *arg; 2006 { 2007 struct gem_softc *sc = arg; 2008 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2009 int s; 2010 2011 s = splnet(); 2012 switch (why) { 2013 case PWR_SUSPEND: 2014 case PWR_STANDBY: 2015 gem_stop(ifp, 1); 2016 if (sc->sc_power != NULL) 2017 (*sc->sc_power)(sc, why); 2018 break; 2019 case PWR_RESUME: 2020 if (ifp->if_flags & IFF_UP) { 2021 if (sc->sc_power != NULL) 2022 (*sc->sc_power)(sc, why); 2023 gem_init(ifp); 2024 } 2025 break; 2026 case PWR_SOFTSUSPEND: 2027 case PWR_SOFTSTANDBY: 2028 case PWR_SOFTRESUME: 2029 break; 2030 } 2031 splx(s); 2032 } 2033 #endif 2034
Indexes created Tue Sep 23 07:09:52 GMT 2025