gem.c revision 1.10
1 /* $NetBSD: gem.c,v 1.10 2001/11/13 13:14:37 lukem Exp $ */ 2 3 /* 4 * 5 * Copyright (C) 2001 Eduardo Horvath. 6 * All rights reserved. 7 * 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 */ 31 32 /* 33 * Driver for Sun GEM ethernet controllers. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: gem.c,v 1.10 2001/11/13 13:14:37 lukem Exp $"); 38 39 #include "bpfilter.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/callout.h> 44 #include <sys/mbuf.h> 45 #include <sys/syslog.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #include <sys/socket.h> 49 #include <sys/ioctl.h> 50 #include <sys/errno.h> 51 #include <sys/device.h> 52 53 #include <machine/endian.h> 54 55 #include <uvm/uvm_extern.h> 56 57 #include <net/if.h> 58 #include <net/if_dl.h> 59 #include <net/if_media.h> 60 #include <net/if_ether.h> 61 62 #if NBPFILTER > 0 63 #include <net/bpf.h> 64 #endif 65 66 #include <machine/bus.h> 67 #include <machine/intr.h> 68 69 #include <dev/mii/mii.h> 70 #include <dev/mii/miivar.h> 71 #include <dev/mii/mii_bitbang.h> 72 73 #include <dev/ic/gemreg.h> 74 #include <dev/ic/gemvar.h> 75 76 #define TRIES 10000 77 78 void gem_start __P((struct ifnet *)); 79 void gem_stop __P((struct ifnet *, int)); 80 int gem_ioctl __P((struct ifnet *, u_long, caddr_t)); 81 void gem_tick __P((void *)); 82 void gem_watchdog __P((struct ifnet *)); 83 void gem_shutdown __P((void *)); 84 int gem_init __P((struct ifnet *)); 85 void gem_init_regs(struct gem_softc *sc); 86 static int gem_ringsize(int sz); 87 int gem_meminit __P((struct gem_softc *)); 88 void gem_mifinit __P((struct gem_softc *)); 89 void gem_reset __P((struct gem_softc *)); 90 int gem_reset_rx(struct gem_softc *sc); 91 int gem_reset_tx(struct gem_softc *sc); 92 int gem_disable_rx(struct gem_softc *sc); 93 int gem_disable_tx(struct gem_softc *sc); 94 void gem_rxdrain(struct gem_softc *sc); 95 int gem_add_rxbuf(struct gem_softc *sc, int idx); 96 void gem_setladrf __P((struct gem_softc *)); 97 98 /* MII methods & callbacks */ 99 static int gem_mii_readreg __P((struct device *, int, int)); 100 static void gem_mii_writereg __P((struct device *, int, int, int)); 101 static void gem_mii_statchg __P((struct device *)); 102 103 int gem_mediachange __P((struct ifnet *)); 104 void gem_mediastatus __P((struct ifnet *, struct ifmediareq *)); 105 106 struct mbuf *gem_get __P((struct gem_softc *, int, int)); 107 int gem_put __P((struct gem_softc *, int, struct mbuf *)); 108 void gem_read __P((struct gem_softc *, int, int)); 109 int gem_eint __P((struct gem_softc *, u_int)); 110 int gem_rint __P((struct gem_softc *)); 111 int gem_tint __P((struct gem_softc *)); 112 void gem_power __P((int, void *)); 113 114 #ifdef GEM_DEBUG 115 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 116 printf x 117 #else 118 #define DPRINTF(sc, x) /* nothing */ 119 #endif 120 121 122 /* 123 * gem_attach: 124 * 125 * Attach a Gem interface to the system. 126 */ 127 void 128 gem_attach(sc, enaddr) 129 struct gem_softc *sc; 130 const uint8_t *enaddr; 131 { 132 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 133 struct mii_data *mii = &sc->sc_mii; 134 struct mii_softc *child; 135 int i, error; 136 137 /* Make sure the chip is stopped. */ 138 ifp->if_softc = sc; 139 gem_reset(sc); 140 141 /* 142 * Allocate the control data structures, and create and load the 143 * DMA map for it. 144 */ 145 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 146 sizeof(struct gem_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 147 1, &sc->sc_cdnseg, 0)) != 0) { 148 printf("%s: unable to allocate control data, error = %d\n", 149 sc->sc_dev.dv_xname, error); 150 goto fail_0; 151 } 152 153 /* XXX should map this in with correct endianness */ 154 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg, 155 sizeof(struct gem_control_data), (caddr_t *)&sc->sc_control_data, 156 BUS_DMA_COHERENT)) != 0) { 157 printf("%s: unable to map control data, error = %d\n", 158 sc->sc_dev.dv_xname, error); 159 goto fail_1; 160 } 161 162 if ((error = bus_dmamap_create(sc->sc_dmatag, 163 sizeof(struct gem_control_data), 1, 164 sizeof(struct gem_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 165 printf("%s: unable to create control data DMA map, " 166 "error = %d\n", sc->sc_dev.dv_xname, error); 167 goto fail_2; 168 } 169 170 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 171 sc->sc_control_data, sizeof(struct gem_control_data), NULL, 172 0)) != 0) { 173 printf("%s: unable to load control data DMA map, error = %d\n", 174 sc->sc_dev.dv_xname, error); 175 goto fail_3; 176 } 177 178 /* 179 * Initialize the transmit job descriptors. 180 */ 181 SIMPLEQ_INIT(&sc->sc_txfreeq); 182 SIMPLEQ_INIT(&sc->sc_txdirtyq); 183 184 /* 185 * Create the transmit buffer DMA maps. 186 */ 187 for (i = 0; i < GEM_TXQUEUELEN; i++) { 188 struct gem_txsoft *txs; 189 190 txs = &sc->sc_txsoft[i]; 191 txs->txs_mbuf = NULL; 192 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 193 GEM_NTXSEGS, MCLBYTES, 0, 0, 194 &txs->txs_dmamap)) != 0) { 195 printf("%s: unable to create tx DMA map %d, " 196 "error = %d\n", sc->sc_dev.dv_xname, i, error); 197 goto fail_4; 198 } 199 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 200 } 201 202 /* 203 * Create the receive buffer DMA maps. 204 */ 205 for (i = 0; i < GEM_NRXDESC; i++) { 206 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, 207 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 208 printf("%s: unable to create rx DMA map %d, " 209 "error = %d\n", sc->sc_dev.dv_xname, i, error); 210 goto fail_5; 211 } 212 sc->sc_rxsoft[i].rxs_mbuf = NULL; 213 } 214 215 /* 216 * From this point forward, the attachment cannot fail. A failure 217 * before this point releases all resources that may have been 218 * allocated. 219 */ 220 221 /* Announce ourselves. */ 222 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 223 ether_sprintf(enaddr)); 224 225 /* Initialize ifnet structure. */ 226 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 227 ifp->if_softc = sc; 228 ifp->if_flags = 229 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 230 ifp->if_start = gem_start; 231 ifp->if_ioctl = gem_ioctl; 232 ifp->if_watchdog = gem_watchdog; 233 ifp->if_stop = gem_stop; 234 ifp->if_init = gem_init; 235 IFQ_SET_READY(&ifp->if_snd); 236 237 /* Initialize ifmedia structures and MII info */ 238 mii->mii_ifp = ifp; 239 mii->mii_readreg = gem_mii_readreg; 240 mii->mii_writereg = gem_mii_writereg; 241 mii->mii_statchg = gem_mii_statchg; 242 243 ifmedia_init(&mii->mii_media, 0, gem_mediachange, gem_mediastatus); 244 245 gem_mifinit(sc); 246 247 mii_attach(&sc->sc_dev, mii, 0xffffffff, 248 MII_PHY_ANY, MII_OFFSET_ANY, 0); 249 250 child = LIST_FIRST(&mii->mii_phys); 251 if (child == NULL) { 252 /* No PHY attached */ 253 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 254 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 255 } else { 256 /* 257 * Walk along the list of attached MII devices and 258 * establish an `MII instance' to `phy number' 259 * mapping. We'll use this mapping in media change 260 * requests to determine which phy to use to program 261 * the MIF configuration register. 262 */ 263 for (; child != NULL; child = LIST_NEXT(child, mii_list)) { 264 /* 265 * Note: we support just two PHYs: the built-in 266 * internal device and an external on the MII 267 * connector. 268 */ 269 if (child->mii_phy > 1 || child->mii_inst > 1) { 270 printf("%s: cannot accomodate MII device %s" 271 " at phy %d, instance %d\n", 272 sc->sc_dev.dv_xname, 273 child->mii_dev.dv_xname, 274 child->mii_phy, child->mii_inst); 275 continue; 276 } 277 278 sc->sc_phys[child->mii_inst] = child->mii_phy; 279 } 280 281 /* 282 * Now select and activate the PHY we will use. 283 * 284 * The order of preference is External (MDI1), 285 * Internal (MDI0), Serial Link (no MII). 286 */ 287 if (sc->sc_phys[1]) { 288 #ifdef DEBUG 289 printf("using external phy\n"); 290 #endif 291 sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL; 292 } else { 293 #ifdef DEBUG 294 printf("using internal phy\n"); 295 #endif 296 sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL; 297 } 298 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_MIF_CONFIG, 299 sc->sc_mif_config); 300 301 /* 302 * XXX - we can really do the following ONLY if the 303 * phy indeed has the auto negotiation capability!! 304 */ 305 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO); 306 } 307 308 /* claim 802.1q capability */ 309 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 310 311 /* Attach the interface. */ 312 if_attach(ifp); 313 ether_ifattach(ifp, enaddr); 314 315 sc->sc_sh = shutdownhook_establish(gem_shutdown, sc); 316 if (sc->sc_sh == NULL) 317 panic("gem_config: can't establish shutdownhook"); 318 319 #if NRND > 0 320 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 321 RND_TYPE_NET, 0); 322 #endif 323 324 325 #if notyet 326 /* 327 * Add a suspend hook to make sure we come back up after a 328 * resume. 329 */ 330 sc->sc_powerhook = powerhook_establish(gem_power, sc); 331 if (sc->sc_powerhook == NULL) 332 printf("%s: WARNING: unable to establish power hook\n", 333 sc->sc_dev.dv_xname); 334 #endif 335 336 callout_init(&sc->sc_tick_ch); 337 return; 338 339 /* 340 * Free any resources we've allocated during the failed attach 341 * attempt. Do this in reverse order and fall through. 342 */ 343 fail_5: 344 for (i = 0; i < GEM_NRXDESC; i++) { 345 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 346 bus_dmamap_destroy(sc->sc_dmatag, 347 sc->sc_rxsoft[i].rxs_dmamap); 348 } 349 fail_4: 350 for (i = 0; i < GEM_TXQUEUELEN; i++) { 351 if (sc->sc_txsoft[i].txs_dmamap != NULL) 352 bus_dmamap_destroy(sc->sc_dmatag, 353 sc->sc_txsoft[i].txs_dmamap); 354 } 355 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 356 fail_3: 357 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 358 fail_2: 359 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)sc->sc_control_data, 360 sizeof(struct gem_control_data)); 361 fail_1: 362 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 363 fail_0: 364 return; 365 } 366 367 368 void 369 gem_tick(arg) 370 void *arg; 371 { 372 struct gem_softc *sc = arg; 373 int s; 374 375 s = splnet(); 376 mii_tick(&sc->sc_mii); 377 splx(s); 378 379 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 380 381 } 382 383 void 384 gem_reset(sc) 385 struct gem_softc *sc; 386 { 387 bus_space_tag_t t = sc->sc_bustag; 388 bus_space_handle_t h = sc->sc_h; 389 int i; 390 int s; 391 392 s = splnet(); 393 DPRINTF(sc, ("%s: gem_reset\n", sc->sc_dev.dv_xname)); 394 gem_reset_rx(sc); 395 gem_reset_tx(sc); 396 397 /* Do a full reset */ 398 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX|GEM_RESET_TX); 399 for (i=TRIES; i--; delay(100)) 400 if ((bus_space_read_4(t, h, GEM_RESET) & 401 (GEM_RESET_RX|GEM_RESET_TX)) == 0) 402 break; 403 if ((bus_space_read_4(t, h, GEM_RESET) & 404 (GEM_RESET_RX|GEM_RESET_TX)) != 0) { 405 printf("%s: cannot reset device\n", 406 sc->sc_dev.dv_xname); 407 } 408 splx(s); 409 } 410 411 412 /* 413 * gem_rxdrain: 414 * 415 * Drain the receive queue. 416 */ 417 void 418 gem_rxdrain(struct gem_softc *sc) 419 { 420 struct gem_rxsoft *rxs; 421 int i; 422 423 for (i = 0; i < GEM_NRXDESC; i++) { 424 rxs = &sc->sc_rxsoft[i]; 425 if (rxs->rxs_mbuf != NULL) { 426 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 427 m_freem(rxs->rxs_mbuf); 428 rxs->rxs_mbuf = NULL; 429 } 430 } 431 } 432 433 /* 434 * Reset the whole thing. 435 */ 436 void 437 gem_stop(struct ifnet *ifp, int disable) 438 { 439 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 440 struct gem_txsoft *txs; 441 442 DPRINTF(sc, ("%s: gem_stop\n", sc->sc_dev.dv_xname)); 443 444 callout_stop(&sc->sc_tick_ch); 445 mii_down(&sc->sc_mii); 446 447 /* XXX - Should we reset these instead? */ 448 gem_disable_rx(sc); 449 gem_disable_rx(sc); 450 451 /* 452 * Release any queued transmit buffers. 453 */ 454 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 455 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs, txs_q); 456 if (txs->txs_mbuf != NULL) { 457 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 458 m_freem(txs->txs_mbuf); 459 txs->txs_mbuf = NULL; 460 } 461 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 462 } 463 464 if (disable) { 465 gem_rxdrain(sc); 466 } 467 468 /* 469 * Mark the interface down and cancel the watchdog timer. 470 */ 471 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 472 ifp->if_timer = 0; 473 } 474 475 476 /* 477 * Reset the receiver 478 */ 479 int 480 gem_reset_rx(struct gem_softc *sc) 481 { 482 bus_space_tag_t t = sc->sc_bustag; 483 bus_space_handle_t h = sc->sc_h; 484 int i; 485 486 487 /* 488 * Resetting while DMA is in progress can cause a bus hang, so we 489 * disable DMA first. 490 */ 491 gem_disable_rx(sc); 492 bus_space_write_4(t, h, GEM_RX_CONFIG, 0); 493 /* Wait till it finishes */ 494 for (i=TRIES; i--; delay(100)) 495 if ((bus_space_read_4(t, h, GEM_RX_CONFIG) & 1) == 0) 496 break; 497 if ((bus_space_read_4(t, h, GEM_RX_CONFIG) & 1) != 0) 498 printf("%s: cannot disable read dma\n", 499 sc->sc_dev.dv_xname); 500 501 /* Wait 5ms extra. */ 502 delay(5000); 503 504 /* Finally, reset the ERX */ 505 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX); 506 /* Wait till it finishes */ 507 for (i=TRIES; i--; delay(100)) 508 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_RX) == 0) 509 break; 510 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_RX) != 0) { 511 printf("%s: cannot reset receiver\n", 512 sc->sc_dev.dv_xname); 513 return (1); 514 } 515 return (0); 516 } 517 518 519 /* 520 * Reset the transmitter 521 */ 522 int 523 gem_reset_tx(struct gem_softc *sc) 524 { 525 bus_space_tag_t t = sc->sc_bustag; 526 bus_space_handle_t h = sc->sc_h; 527 int i; 528 529 /* 530 * Resetting while DMA is in progress can cause a bus hang, so we 531 * disable DMA first. 532 */ 533 gem_disable_tx(sc); 534 bus_space_write_4(t, h, GEM_TX_CONFIG, 0); 535 /* Wait till it finishes */ 536 for (i=TRIES; i--; delay(100)) 537 if ((bus_space_read_4(t, h, GEM_TX_CONFIG) & 1) == 0) 538 break; 539 if ((bus_space_read_4(t, h, GEM_TX_CONFIG) & 1) != 0) 540 printf("%s: cannot disable read dma\n", 541 sc->sc_dev.dv_xname); 542 543 /* Wait 5ms extra. */ 544 delay(5000); 545 546 /* Finally, reset the ETX */ 547 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_TX); 548 /* Wait till it finishes */ 549 for (i=TRIES; i--; delay(100)) 550 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_TX) == 0) 551 break; 552 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_TX) != 0) { 553 printf("%s: cannot reset receiver\n", 554 sc->sc_dev.dv_xname); 555 return (1); 556 } 557 return (0); 558 } 559 560 /* 561 * disable receiver. 562 */ 563 int 564 gem_disable_rx(struct gem_softc *sc) 565 { 566 bus_space_tag_t t = sc->sc_bustag; 567 bus_space_handle_t h = sc->sc_h; 568 int i; 569 u_int32_t cfg; 570 571 /* Flip the enable bit */ 572 cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 573 cfg &= ~GEM_MAC_RX_ENABLE; 574 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg); 575 576 /* Wait for it to finish */ 577 for (i=TRIES; i--; delay(100)) 578 if ((bus_space_read_4(t, h, GEM_MAC_RX_CONFIG) & 579 GEM_MAC_RX_ENABLE) == 0) 580 return (0); 581 return (1); 582 } 583 584 /* 585 * disable transmitter. 586 */ 587 int 588 gem_disable_tx(struct gem_softc *sc) 589 { 590 bus_space_tag_t t = sc->sc_bustag; 591 bus_space_handle_t h = sc->sc_h; 592 int i; 593 u_int32_t cfg; 594 595 /* Flip the enable bit */ 596 cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG); 597 cfg &= ~GEM_MAC_TX_ENABLE; 598 bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg); 599 600 /* Wait for it to finish */ 601 for (i=TRIES; i--; delay(100)) 602 if ((bus_space_read_4(t, h, GEM_MAC_TX_CONFIG) & 603 GEM_MAC_TX_ENABLE) == 0) 604 return (0); 605 return (1); 606 } 607 608 /* 609 * Initialize interface. 610 */ 611 int 612 gem_meminit(struct gem_softc *sc) 613 { 614 struct gem_rxsoft *rxs; 615 int i, error; 616 617 /* 618 * Initialize the transmit descriptor ring. 619 */ 620 memset((void *)sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 621 for (i = 0; i < GEM_NTXDESC; i++) { 622 sc->sc_txdescs[i].gd_flags = 0; 623 sc->sc_txdescs[i].gd_addr = 0; 624 } 625 GEM_CDTXSYNC(sc, 0, GEM_NTXDESC, 626 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 627 sc->sc_txfree = GEM_NTXDESC; 628 sc->sc_txnext = 0; 629 630 /* 631 * Initialize the receive descriptor and receive job 632 * descriptor rings. 633 */ 634 for (i = 0; i < GEM_NRXDESC; i++) { 635 rxs = &sc->sc_rxsoft[i]; 636 if (rxs->rxs_mbuf == NULL) { 637 if ((error = gem_add_rxbuf(sc, i)) != 0) { 638 printf("%s: unable to allocate or map rx " 639 "buffer %d, error = %d\n", 640 sc->sc_dev.dv_xname, i, error); 641 /* 642 * XXX Should attempt to run with fewer receive 643 * XXX buffers instead of just failing. 644 */ 645 gem_rxdrain(sc); 646 return (1); 647 } 648 } else 649 GEM_INIT_RXDESC(sc, i); 650 } 651 sc->sc_rxptr = 0; 652 653 return (0); 654 } 655 656 static int 657 gem_ringsize(int sz) 658 { 659 int v; 660 661 switch (sz) { 662 case 32: 663 v = GEM_RING_SZ_32; 664 break; 665 case 64: 666 v = GEM_RING_SZ_64; 667 break; 668 case 128: 669 v = GEM_RING_SZ_128; 670 break; 671 case 256: 672 v = GEM_RING_SZ_256; 673 break; 674 case 512: 675 v = GEM_RING_SZ_512; 676 break; 677 case 1024: 678 v = GEM_RING_SZ_1024; 679 break; 680 case 2048: 681 v = GEM_RING_SZ_2048; 682 break; 683 case 4096: 684 v = GEM_RING_SZ_4096; 685 break; 686 case 8192: 687 v = GEM_RING_SZ_8192; 688 break; 689 default: 690 printf("gem: invalid Receive Descriptor ring size\n"); 691 break; 692 } 693 return (v); 694 } 695 696 /* 697 * Initialization of interface; set up initialization block 698 * and transmit/receive descriptor rings. 699 */ 700 int 701 gem_init(struct ifnet *ifp) 702 { 703 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 704 bus_space_tag_t t = sc->sc_bustag; 705 bus_space_handle_t h = sc->sc_h; 706 int s; 707 u_int32_t v; 708 709 s = splnet(); 710 711 DPRINTF(sc, ("%s: gem_init: calling stop\n", sc->sc_dev.dv_xname)); 712 /* 713 * Initialization sequence. The numbered steps below correspond 714 * to the sequence outlined in section 6.3.5.1 in the Ethernet 715 * Channel Engine manual (part of the PCIO manual). 716 * See also the STP2002-STQ document from Sun Microsystems. 717 */ 718 719 /* step 1 & 2. Reset the Ethernet Channel */ 720 gem_stop(ifp, 0); 721 gem_reset(sc); 722 DPRINTF(sc, ("%s: gem_init: restarting\n", sc->sc_dev.dv_xname)); 723 724 /* Re-initialize the MIF */ 725 gem_mifinit(sc); 726 727 /* Call MI reset function if any */ 728 if (sc->sc_hwreset) 729 (*sc->sc_hwreset)(sc); 730 731 /* step 3. Setup data structures in host memory */ 732 gem_meminit(sc); 733 734 /* step 4. TX MAC registers & counters */ 735 gem_init_regs(sc); 736 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 737 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 738 ETHER_VLAN_ENCAP_LEN + ETHER_MAX_LEN + sizeof(struct ether_header): 739 ETHER_MAX_LEN + sizeof(struct ether_header)) | (0x2000<<16)); 740 741 /* step 5. RX MAC registers & counters */ 742 gem_setladrf(sc); 743 744 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 745 /* NOTE: we use only 32-bit DMA addresses here. */ 746 bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 0); 747 bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 748 749 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0); 750 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 751 752 /* step 8. Global Configuration & Interrupt Mask */ 753 bus_space_write_4(t, h, GEM_INTMASK, 754 ~(GEM_INTR_TX_INTME| 755 GEM_INTR_TX_EMPTY| 756 GEM_INTR_RX_DONE|GEM_INTR_RX_NOBUF| 757 GEM_INTR_RX_TAG_ERR|GEM_INTR_PCS| 758 GEM_INTR_MAC_CONTROL|GEM_INTR_MIF| 759 GEM_INTR_BERR)); 760 bus_space_write_4(t, h, GEM_MAC_RX_MASK, 0); /* XXXX */ 761 bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXXX */ 762 bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 0); /* XXXX */ 763 764 /* step 9. ETX Configuration: use mostly default values */ 765 766 /* Enable DMA */ 767 v = gem_ringsize(GEM_NTXDESC /*XXX*/); 768 bus_space_write_4(t, h, GEM_TX_CONFIG, 769 v|GEM_TX_CONFIG_TXDMA_EN| 770 ((0x400<<10)&GEM_TX_CONFIG_TXFIFO_TH)); 771 bus_space_write_4(t, h, GEM_TX_KICK, sc->sc_txnext); 772 773 /* step 10. ERX Configuration */ 774 775 /* Encode Receive Descriptor ring size: four possible values */ 776 v = gem_ringsize(GEM_NRXDESC /*XXX*/); 777 778 /* Enable DMA */ 779 bus_space_write_4(t, h, GEM_RX_CONFIG, 780 v|(GEM_THRSH_1024<<GEM_RX_CONFIG_FIFO_THRS_SHIFT)| 781 (2<<GEM_RX_CONFIG_FBOFF_SHFT)|GEM_RX_CONFIG_RXDMA_EN| 782 (0<<GEM_RX_CONFIG_CXM_START_SHFT)); 783 /* 784 * The following value is for an OFF Threshold of about 15.5 Kbytes 785 * and an ON Threshold of 4K bytes. 786 */ 787 bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH, 0xf8 | (0x40 << 12)); 788 bus_space_write_4(t, h, GEM_RX_BLANKING, (2<<12)|6); 789 790 /* step 11. Configure Media */ 791 (void) gem_mediachange(ifp); 792 793 /* step 12. RX_MAC Configuration Register */ 794 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 795 v |= GEM_MAC_RX_ENABLE; 796 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 797 798 /* step 14. Issue Transmit Pending command */ 799 800 /* Call MI initialization function if any */ 801 if (sc->sc_hwinit) 802 (*sc->sc_hwinit)(sc); 803 804 805 /* step 15. Give the reciever a swift kick */ 806 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4); 807 808 /* Start the one second timer. */ 809 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 810 811 ifp->if_flags |= IFF_RUNNING; 812 ifp->if_flags &= ~IFF_OACTIVE; 813 ifp->if_timer = 0; 814 splx(s); 815 816 return (0); 817 } 818 819 void 820 gem_init_regs(struct gem_softc *sc) 821 { 822 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 823 bus_space_tag_t t = sc->sc_bustag; 824 bus_space_handle_t h = sc->sc_h; 825 826 /* These regs are not cleared on reset */ 827 sc->sc_inited = 0; 828 if (!sc->sc_inited) { 829 830 /* Wooo. Magic values. */ 831 bus_space_write_4(t, h, GEM_MAC_IPG0, 0); 832 bus_space_write_4(t, h, GEM_MAC_IPG1, 8); 833 bus_space_write_4(t, h, GEM_MAC_IPG2, 4); 834 835 bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 836 /* Max frame and max burst size */ 837 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 838 (ifp->if_mtu+18) | (0x2000<<16)/* Burst size */); 839 bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x7); 840 bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x4); 841 bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10); 842 /* Dunno.... */ 843 bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088); 844 bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED, 845 ((LLADDR(ifp->if_sadl)[5]<<8)| 846 LLADDR(ifp->if_sadl)[4])&0x3ff); 847 /* Secondary MAC addr set to 0:0:0:0:0:0 */ 848 bus_space_write_4(t, h, GEM_MAC_ADDR3, 0); 849 bus_space_write_4(t, h, GEM_MAC_ADDR4, 0); 850 bus_space_write_4(t, h, GEM_MAC_ADDR5, 0); 851 /* MAC control addr set to 0:1:c2:0:1:80 */ 852 bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001); 853 bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200); 854 bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180); 855 856 /* MAC filter addr set to 0:0:0:0:0:0 */ 857 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0); 858 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0); 859 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0); 860 861 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0); 862 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0); 863 864 sc->sc_inited = 1; 865 } 866 867 /* Counters need to be zeroed */ 868 bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0); 869 bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0); 870 bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0); 871 bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0); 872 bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0); 873 bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0); 874 bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0); 875 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 876 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 877 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 878 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 879 880 /* Un-pause stuff */ 881 #if 0 882 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); 883 #else 884 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0); 885 #endif 886 887 /* 888 * Set the station address. 889 */ 890 bus_space_write_4(t, h, GEM_MAC_ADDR0, 891 (LLADDR(ifp->if_sadl)[4]<<8) | LLADDR(ifp->if_sadl)[5]); 892 bus_space_write_4(t, h, GEM_MAC_ADDR1, 893 (LLADDR(ifp->if_sadl)[2]<<8) | LLADDR(ifp->if_sadl)[3]); 894 bus_space_write_4(t, h, GEM_MAC_ADDR2, 895 (LLADDR(ifp->if_sadl)[0]<<8) | LLADDR(ifp->if_sadl)[1]); 896 897 } 898 899 900 901 void 902 gem_start(ifp) 903 struct ifnet *ifp; 904 { 905 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 906 struct mbuf *m0, *m; 907 struct gem_txsoft *txs, *last_txs; 908 bus_dmamap_t dmamap; 909 int error, firsttx, nexttx, lasttx, ofree, seg; 910 911 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 912 return; 913 914 /* 915 * Remember the previous number of free descriptors and 916 * the first descriptor we'll use. 917 */ 918 ofree = sc->sc_txfree; 919 firsttx = sc->sc_txnext; 920 921 DPRINTF(sc, ("%s: gem_start: txfree %d, txnext %d\n", 922 sc->sc_dev.dv_xname, ofree, firsttx)); 923 924 /* 925 * Loop through the send queue, setting up transmit descriptors 926 * until we drain the queue, or use up all available transmit 927 * descriptors. 928 */ 929 for (;;) { 930 /* 931 * Grab a packet off the queue. 932 */ 933 IFQ_POLL(&ifp->if_snd, m0); 934 if (m0 == NULL) 935 break; 936 m = NULL; 937 938 /* Get a work queue entry. */ 939 if ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) == NULL) { 940 /* We've run out. */ 941 break; 942 } 943 944 dmamap = txs->txs_dmamap; 945 946 /* 947 * Load the DMA map. If this fails, the packet either 948 * didn't fit in the alloted number of segments, or we were 949 * short on resources. In this case, we'll copy and try 950 * again. 951 */ 952 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m0, 953 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 954 MGETHDR(m, M_DONTWAIT, MT_DATA); 955 if (m == NULL) { 956 printf("%s: unable to allocate Tx mbuf\n", 957 sc->sc_dev.dv_xname); 958 break; 959 } 960 if (m0->m_pkthdr.len > MHLEN) { 961 MCLGET(m, M_DONTWAIT); 962 if ((m->m_flags & M_EXT) == 0) { 963 printf("%s: unable to allocate Tx " 964 "cluster\n", sc->sc_dev.dv_xname); 965 m_freem(m); 966 break; 967 } 968 } 969 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 970 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 971 error = bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, 972 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 973 if (error) { 974 printf("%s: unable to load Tx buffer, " 975 "error = %d\n", sc->sc_dev.dv_xname, error); 976 break; 977 } 978 } 979 980 /* 981 * Ensure we have enough descriptors free to describe 982 * the packet. Note, we always reserve one descriptor 983 * at the end of the ring as a termination point, to 984 * prevent wrap-around. 985 */ 986 if (dmamap->dm_nsegs > (sc->sc_txfree - 1)) { 987 /* 988 * Not enough free descriptors to transmit this 989 * packet. We haven't committed to anything yet, 990 * so just unload the DMA map, put the packet 991 * back on the queue, and punt. Notify the upper 992 * layer that there are no more slots left. 993 * 994 * XXX We could allocate an mbuf and copy, but 995 * XXX it is worth it? 996 */ 997 ifp->if_flags |= IFF_OACTIVE; 998 bus_dmamap_unload(sc->sc_dmatag, dmamap); 999 if (m != NULL) 1000 m_freem(m); 1001 break; 1002 } 1003 1004 IFQ_DEQUEUE(&ifp->if_snd, m0); 1005 if (m != NULL) { 1006 m_freem(m0); 1007 m0 = m; 1008 } 1009 1010 /* 1011 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1012 */ 1013 1014 /* Sync the DMA map. */ 1015 bus_dmamap_sync(sc->sc_dmatag, dmamap, 0, dmamap->dm_mapsize, 1016 BUS_DMASYNC_PREWRITE); 1017 1018 /* 1019 * Initialize the transmit descriptors. 1020 */ 1021 for (nexttx = sc->sc_txnext, seg = 0; 1022 seg < dmamap->dm_nsegs; 1023 seg++, nexttx = GEM_NEXTTX(nexttx)) { 1024 uint64_t flags; 1025 1026 /* 1027 * If this is the first descriptor we're 1028 * enqueueing, set the start of packet flag, 1029 * and the checksum stuff if we want the hardware 1030 * to do it. 1031 */ 1032 sc->sc_txdescs[nexttx].gd_addr = 1033 GEM_DMA_WRITE(sc, dmamap->dm_segs[seg].ds_addr); 1034 flags = dmamap->dm_segs[seg].ds_len & GEM_TD_BUFSIZE; 1035 if (nexttx == firsttx) { 1036 flags |= GEM_TD_START_OF_PACKET; 1037 } 1038 if (seg == dmamap->dm_nsegs - 1) { 1039 flags |= GEM_TD_END_OF_PACKET; 1040 } 1041 sc->sc_txdescs[nexttx].gd_flags = 1042 GEM_DMA_WRITE(sc, flags); 1043 lasttx = nexttx; 1044 } 1045 1046 #ifdef GEM_DEBUG 1047 if (ifp->if_flags & IFF_DEBUG) { 1048 printf(" gem_start %p transmit chain:\n", txs); 1049 for (seg = sc->sc_txnext;; seg = GEM_NEXTTX(seg)) { 1050 printf("descriptor %d:\t", seg); 1051 printf("gd_flags: 0x%016llx\t", (long long) 1052 GEM_DMA_READ(sc, sc->sc_txdescs[seg].gd_flags)); 1053 printf("gd_addr: 0x%016llx\n", (long long) 1054 GEM_DMA_READ(sc, sc->sc_txdescs[seg].gd_addr)); 1055 if (seg == lasttx) 1056 break; 1057 } 1058 } 1059 #endif 1060 1061 /* Sync the descriptors we're using. */ 1062 GEM_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1063 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1064 1065 /* 1066 * Store a pointer to the packet so we can free it later, 1067 * and remember what txdirty will be once the packet is 1068 * done. 1069 */ 1070 txs->txs_mbuf = m0; 1071 txs->txs_firstdesc = sc->sc_txnext; 1072 txs->txs_lastdesc = lasttx; 1073 txs->txs_ndescs = dmamap->dm_nsegs; 1074 1075 /* Advance the tx pointer. */ 1076 sc->sc_txfree -= dmamap->dm_nsegs; 1077 sc->sc_txnext = nexttx; 1078 1079 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs, txs_q); 1080 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1081 1082 last_txs = txs; 1083 1084 #if NBPFILTER > 0 1085 /* 1086 * Pass the packet to any BPF listeners. 1087 */ 1088 if (ifp->if_bpf) 1089 bpf_mtap(ifp->if_bpf, m0); 1090 #endif /* NBPFILTER > 0 */ 1091 } 1092 1093 if (txs == NULL || sc->sc_txfree == 0) { 1094 /* No more slots left; notify upper layer. */ 1095 ifp->if_flags |= IFF_OACTIVE; 1096 } 1097 1098 if (sc->sc_txfree != ofree) { 1099 DPRINTF(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 1100 sc->sc_dev.dv_xname, lasttx, firsttx)); 1101 /* 1102 * The entire packet chain is set up. 1103 * Kick the transmitter. 1104 */ 1105 DPRINTF(sc, ("%s: gem_start: kicking tx %d\n", 1106 sc->sc_dev.dv_xname, nexttx)); 1107 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_TX_KICK, 1108 sc->sc_txnext); 1109 1110 /* Set a watchdog timer in case the chip flakes out. */ 1111 ifp->if_timer = 5; 1112 DPRINTF(sc, ("%s: gem_start: watchdog %d\n", 1113 sc->sc_dev.dv_xname, ifp->if_timer)); 1114 } 1115 } 1116 1117 /* 1118 * Transmit interrupt. 1119 */ 1120 int 1121 gem_tint(sc) 1122 struct gem_softc *sc; 1123 { 1124 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1125 bus_space_tag_t t = sc->sc_bustag; 1126 bus_space_handle_t mac = sc->sc_h; 1127 struct gem_txsoft *txs; 1128 int txlast; 1129 1130 1131 DPRINTF(sc, ("%s: gem_tint\n", sc->sc_dev.dv_xname)); 1132 1133 /* 1134 * Unload collision counters 1135 */ 1136 ifp->if_collisions += 1137 bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) + 1138 bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT) + 1139 bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) + 1140 bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT); 1141 1142 /* 1143 * then clear the hardware counters. 1144 */ 1145 bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0); 1146 bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0); 1147 bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0); 1148 bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0); 1149 1150 /* 1151 * Go through our Tx list and free mbufs for those 1152 * frames that have been transmitted. 1153 */ 1154 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1155 GEM_CDTXSYNC(sc, txs->txs_lastdesc, 1156 txs->txs_ndescs, 1157 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1158 1159 #ifdef GEM_DEBUG 1160 if (ifp->if_flags & IFF_DEBUG) { 1161 int i; 1162 printf(" txsoft %p transmit chain:\n", txs); 1163 for (i = txs->txs_firstdesc;; i = GEM_NEXTTX(i)) { 1164 printf("descriptor %d: ", i); 1165 printf("gd_flags: 0x%016llx\t", (long long) 1166 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags)); 1167 printf("gd_addr: 0x%016llx\n", (long long) 1168 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr)); 1169 if (i == txs->txs_lastdesc) 1170 break; 1171 } 1172 } 1173 #endif 1174 1175 /* 1176 * In theory, we could harveast some descriptors before 1177 * the ring is empty, but that's a bit complicated. 1178 * 1179 * GEM_TX_COMPLETION points to the last descriptor 1180 * processed +1. 1181 */ 1182 txlast = bus_space_read_4(t, mac, GEM_TX_COMPLETION); 1183 DPRINTF(sc, 1184 ("gem_tint: txs->txs_lastdesc = %d, txlast = %d\n", 1185 txs->txs_lastdesc, txlast)); 1186 if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1187 if ((txlast >= txs->txs_firstdesc) && 1188 (txlast <= txs->txs_lastdesc)) 1189 break; 1190 } else { 1191 /* Ick -- this command wraps */ 1192 if ((txlast >= txs->txs_firstdesc) || 1193 (txlast <= txs->txs_lastdesc)) 1194 break; 1195 } 1196 1197 DPRINTF(sc, ("gem_tint: releasing a desc\n")); 1198 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs, txs_q); 1199 1200 sc->sc_txfree += txs->txs_ndescs; 1201 1202 if (txs->txs_mbuf == NULL) { 1203 #ifdef DIAGNOSTIC 1204 panic("gem_txintr: null mbuf"); 1205 #endif 1206 } 1207 1208 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 1209 0, txs->txs_dmamap->dm_mapsize, 1210 BUS_DMASYNC_POSTWRITE); 1211 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 1212 m_freem(txs->txs_mbuf); 1213 txs->txs_mbuf = NULL; 1214 1215 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1216 1217 ifp->if_opackets++; 1218 } 1219 1220 DPRINTF(sc, ("gem_tint: GEM_TX_STATE_MACHINE %x " 1221 "GEM_TX_DATA_PTR %llx " 1222 "GEM_TX_COMPLETION %x\n", 1223 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_STATE_MACHINE), 1224 ((long long) bus_space_read_4(sc->sc_bustag, sc->sc_h, 1225 GEM_TX_DATA_PTR_HI) << 32) | 1226 bus_space_read_4(sc->sc_bustag, sc->sc_h, 1227 GEM_TX_DATA_PTR_LO), 1228 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_COMPLETION))); 1229 1230 gem_start(ifp); 1231 1232 if (SIMPLEQ_FIRST(&sc->sc_txdirtyq) == NULL) 1233 ifp->if_timer = 0; 1234 DPRINTF(sc, ("%s: gem_tint: watchdog %d\n", 1235 sc->sc_dev.dv_xname, ifp->if_timer)); 1236 1237 return (1); 1238 } 1239 1240 /* 1241 * Receive interrupt. 1242 */ 1243 int 1244 gem_rint(sc) 1245 struct gem_softc *sc; 1246 { 1247 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1248 bus_space_tag_t t = sc->sc_bustag; 1249 bus_space_handle_t h = sc->sc_h; 1250 struct ether_header *eh; 1251 struct gem_rxsoft *rxs; 1252 struct mbuf *m; 1253 u_int64_t rxstat; 1254 int i, len; 1255 1256 DPRINTF(sc, ("%s: gem_rint\n", sc->sc_dev.dv_xname)); 1257 /* 1258 * XXXX Read the lastrx only once at the top for speed. 1259 */ 1260 DPRINTF(sc, ("gem_rint: sc->rxptr %d, complete %d\n", 1261 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION))); 1262 for (i = sc->sc_rxptr; i != bus_space_read_4(t, h, GEM_RX_COMPLETION); 1263 i = GEM_NEXTRX(i)) { 1264 rxs = &sc->sc_rxsoft[i]; 1265 1266 GEM_CDRXSYNC(sc, i, 1267 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1268 1269 rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags); 1270 1271 if (rxstat & GEM_RD_OWN) { 1272 printf("gem_rint: completed descriptor " 1273 "still owned %d\n", i); 1274 /* 1275 * We have processed all of the receive buffers. 1276 */ 1277 break; 1278 } 1279 1280 if (rxstat & GEM_RD_BAD_CRC) { 1281 printf("%s: receive error: CRC error\n", 1282 sc->sc_dev.dv_xname); 1283 GEM_INIT_RXDESC(sc, i); 1284 continue; 1285 } 1286 1287 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1288 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1289 #ifdef GEM_DEBUG 1290 if (ifp->if_flags & IFF_DEBUG) { 1291 printf(" rxsoft %p descriptor %d: ", rxs, i); 1292 printf("gd_flags: 0x%016llx\t", (long long) 1293 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags)); 1294 printf("gd_addr: 0x%016llx\n", (long long) 1295 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr)); 1296 } 1297 #endif 1298 1299 /* 1300 * No errors; receive the packet. Note the Gem 1301 * includes the CRC with every packet. 1302 */ 1303 len = GEM_RD_BUFLEN(rxstat); 1304 1305 /* 1306 * Allocate a new mbuf cluster. If that fails, we are 1307 * out of memory, and must drop the packet and recycle 1308 * the buffer that's already attached to this descriptor. 1309 */ 1310 m = rxs->rxs_mbuf; 1311 if (gem_add_rxbuf(sc, i) != 0) { 1312 ifp->if_ierrors++; 1313 GEM_INIT_RXDESC(sc, i); 1314 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1315 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1316 continue; 1317 } 1318 m->m_data += 2; /* We're already off by two */ 1319 1320 ifp->if_ipackets++; 1321 eh = mtod(m, struct ether_header *); 1322 m->m_flags |= M_HASFCS; 1323 m->m_pkthdr.rcvif = ifp; 1324 m->m_pkthdr.len = m->m_len = len; 1325 1326 #if NBPFILTER > 0 1327 /* 1328 * Pass this up to any BPF listeners, but only 1329 * pass it up the stack if its for us. 1330 */ 1331 if (ifp->if_bpf) 1332 bpf_mtap(ifp->if_bpf, m); 1333 #endif /* NPBFILTER > 0 */ 1334 1335 /* Pass it on. */ 1336 (*ifp->if_input)(ifp, m); 1337 } 1338 1339 /* Update the receive pointer. */ 1340 sc->sc_rxptr = i; 1341 bus_space_write_4(t, h, GEM_RX_KICK, i); 1342 1343 DPRINTF(sc, ("gem_rint: done sc->rxptr %d, complete %d\n", 1344 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION))); 1345 1346 return (1); 1347 } 1348 1349 1350 /* 1351 * gem_add_rxbuf: 1352 * 1353 * Add a receive buffer to the indicated descriptor. 1354 */ 1355 int 1356 gem_add_rxbuf(struct gem_softc *sc, int idx) 1357 { 1358 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1359 struct mbuf *m; 1360 int error; 1361 1362 MGETHDR(m, M_DONTWAIT, MT_DATA); 1363 if (m == NULL) 1364 return (ENOBUFS); 1365 1366 MCLGET(m, M_DONTWAIT); 1367 if ((m->m_flags & M_EXT) == 0) { 1368 m_freem(m); 1369 return (ENOBUFS); 1370 } 1371 1372 #ifdef GEM_DEBUG 1373 /* bzero the packet to check dma */ 1374 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 1375 #endif 1376 1377 if (rxs->rxs_mbuf != NULL) 1378 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 1379 1380 rxs->rxs_mbuf = m; 1381 1382 error = bus_dmamap_load(sc->sc_dmatag, rxs->rxs_dmamap, 1383 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1384 BUS_DMA_READ|BUS_DMA_NOWAIT); 1385 if (error) { 1386 printf("%s: can't load rx DMA map %d, error = %d\n", 1387 sc->sc_dev.dv_xname, idx, error); 1388 panic("gem_add_rxbuf"); /* XXX */ 1389 } 1390 1391 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1392 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1393 1394 GEM_INIT_RXDESC(sc, idx); 1395 1396 return (0); 1397 } 1398 1399 1400 int 1401 gem_eint(sc, status) 1402 struct gem_softc *sc; 1403 u_int status; 1404 { 1405 char bits[128]; 1406 1407 if ((status & GEM_INTR_MIF) != 0) { 1408 printf("%s: XXXlink status changed\n", sc->sc_dev.dv_xname); 1409 return (1); 1410 } 1411 1412 printf("%s: status=%s\n", sc->sc_dev.dv_xname, 1413 bitmask_snprintf(status, GEM_INTR_BITS, bits, sizeof(bits))); 1414 return (1); 1415 } 1416 1417 1418 int 1419 gem_intr(v) 1420 void *v; 1421 { 1422 struct gem_softc *sc = (struct gem_softc *)v; 1423 bus_space_tag_t t = sc->sc_bustag; 1424 bus_space_handle_t seb = sc->sc_h; 1425 u_int32_t status; 1426 int r = 0; 1427 #ifdef GEM_DEBUG 1428 char bits[128]; 1429 #endif 1430 1431 status = bus_space_read_4(t, seb, GEM_STATUS); 1432 DPRINTF(sc, ("%s: gem_intr: cplt %xstatus %s\n", 1433 sc->sc_dev.dv_xname, (status>>19), 1434 bitmask_snprintf(status, GEM_INTR_BITS, bits, sizeof(bits)))); 1435 1436 if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0) 1437 r |= gem_eint(sc, status); 1438 1439 if ((status & 1440 (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) 1441 != 0) 1442 r |= gem_tint(sc); 1443 1444 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) 1445 r |= gem_rint(sc); 1446 1447 /* We should eventually do more than just print out error stats. */ 1448 if (status & GEM_INTR_TX_MAC) { 1449 int txstat = bus_space_read_4(t, seb, GEM_MAC_TX_STATUS); 1450 if (txstat & ~GEM_MAC_TX_XMIT_DONE) 1451 printf("MAC tx fault, status %x\n", txstat); 1452 } 1453 if (status & GEM_INTR_RX_MAC) { 1454 int rxstat = bus_space_read_4(t, seb, GEM_MAC_RX_STATUS); 1455 if (rxstat & ~GEM_MAC_RX_DONE) 1456 printf("MAC rx fault, status %x\n", rxstat); 1457 } 1458 return (r); 1459 } 1460 1461 1462 void 1463 gem_watchdog(ifp) 1464 struct ifnet *ifp; 1465 { 1466 struct gem_softc *sc = ifp->if_softc; 1467 1468 DPRINTF(sc, ("gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x " 1469 "GEM_MAC_RX_CONFIG %x\n", 1470 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_CONFIG), 1471 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_STATUS), 1472 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_CONFIG))); 1473 1474 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1475 ++ifp->if_oerrors; 1476 1477 /* Try to get more packets going. */ 1478 gem_start(ifp); 1479 } 1480 1481 /* 1482 * Initialize the MII Management Interface 1483 */ 1484 void 1485 gem_mifinit(sc) 1486 struct gem_softc *sc; 1487 { 1488 bus_space_tag_t t = sc->sc_bustag; 1489 bus_space_handle_t mif = sc->sc_h; 1490 1491 /* Configure the MIF in frame mode */ 1492 sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1493 sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA; 1494 bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config); 1495 } 1496 1497 /* 1498 * MII interface 1499 * 1500 * The GEM MII interface supports at least three different operating modes: 1501 * 1502 * Bitbang mode is implemented using data, clock and output enable registers. 1503 * 1504 * Frame mode is implemented by loading a complete frame into the frame 1505 * register and polling the valid bit for completion. 1506 * 1507 * Polling mode uses the frame register but completion is indicated by 1508 * an interrupt. 1509 * 1510 */ 1511 static int 1512 gem_mii_readreg(self, phy, reg) 1513 struct device *self; 1514 int phy, reg; 1515 { 1516 struct gem_softc *sc = (void *)self; 1517 bus_space_tag_t t = sc->sc_bustag; 1518 bus_space_handle_t mif = sc->sc_h; 1519 int n; 1520 u_int32_t v; 1521 1522 #ifdef GEM_DEBUG1 1523 if (sc->sc_debug) 1524 printf("gem_mii_readreg: phy %d reg %d\n", phy, reg); 1525 #endif 1526 1527 #if 0 1528 /* Select the desired PHY in the MIF configuration register */ 1529 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1530 /* Clear PHY select bit */ 1531 v &= ~GEM_MIF_CONFIG_PHY_SEL; 1532 if (phy == GEM_PHYAD_EXTERNAL) 1533 /* Set PHY select bit to get at external device */ 1534 v |= GEM_MIF_CONFIG_PHY_SEL; 1535 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 1536 #endif 1537 1538 /* Construct the frame command */ 1539 v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) | 1540 GEM_MIF_FRAME_READ; 1541 1542 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1543 for (n = 0; n < 100; n++) { 1544 DELAY(1); 1545 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1546 if (v & GEM_MIF_FRAME_TA0) 1547 return (v & GEM_MIF_FRAME_DATA); 1548 } 1549 1550 printf("%s: mii_read timeout\n", sc->sc_dev.dv_xname); 1551 return (0); 1552 } 1553 1554 static void 1555 gem_mii_writereg(self, phy, reg, val) 1556 struct device *self; 1557 int phy, reg, val; 1558 { 1559 struct gem_softc *sc = (void *)self; 1560 bus_space_tag_t t = sc->sc_bustag; 1561 bus_space_handle_t mif = sc->sc_h; 1562 int n; 1563 u_int32_t v; 1564 1565 #ifdef GEM_DEBUG1 1566 if (sc->sc_debug) 1567 printf("gem_mii_writereg: phy %d reg %d val %x\n", 1568 phy, reg, val); 1569 #endif 1570 1571 #if 0 1572 /* Select the desired PHY in the MIF configuration register */ 1573 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1574 /* Clear PHY select bit */ 1575 v &= ~GEM_MIF_CONFIG_PHY_SEL; 1576 if (phy == GEM_PHYAD_EXTERNAL) 1577 /* Set PHY select bit to get at external device */ 1578 v |= GEM_MIF_CONFIG_PHY_SEL; 1579 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 1580 #endif 1581 /* Construct the frame command */ 1582 v = GEM_MIF_FRAME_WRITE | 1583 (phy << GEM_MIF_PHY_SHIFT) | 1584 (reg << GEM_MIF_REG_SHIFT) | 1585 (val & GEM_MIF_FRAME_DATA); 1586 1587 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1588 for (n = 0; n < 100; n++) { 1589 DELAY(1); 1590 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1591 if (v & GEM_MIF_FRAME_TA0) 1592 return; 1593 } 1594 1595 printf("%s: mii_write timeout\n", sc->sc_dev.dv_xname); 1596 } 1597 1598 static void 1599 gem_mii_statchg(dev) 1600 struct device *dev; 1601 { 1602 struct gem_softc *sc = (void *)dev; 1603 #ifdef GEM_DEBUG 1604 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1605 #endif 1606 bus_space_tag_t t = sc->sc_bustag; 1607 bus_space_handle_t mac = sc->sc_h; 1608 u_int32_t v; 1609 1610 #ifdef GEM_DEBUG 1611 if (sc->sc_debug) 1612 printf("gem_mii_statchg: status change: phy = %d\n", 1613 sc->sc_phys[instance];); 1614 #endif 1615 1616 1617 /* Set tx full duplex options */ 1618 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0); 1619 delay(10000); /* reg must be cleared and delay before changing. */ 1620 v = GEM_MAC_TX_ENA_IPG0|GEM_MAC_TX_NGU|GEM_MAC_TX_NGU_LIMIT| 1621 GEM_MAC_TX_ENABLE; 1622 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) { 1623 v |= GEM_MAC_TX_IGN_CARRIER|GEM_MAC_TX_IGN_COLLIS; 1624 } 1625 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, v); 1626 1627 /* XIF Configuration */ 1628 /* We should really calculate all this rather than rely on defaults */ 1629 v = bus_space_read_4(t, mac, GEM_MAC_XIF_CONFIG); 1630 v = GEM_MAC_XIF_LINK_LED; 1631 v |= GEM_MAC_XIF_TX_MII_ENA; 1632 /* If an external transceiver is connected, enable its MII drivers */ 1633 sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG); 1634 if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) { 1635 /* External MII needs echo disable if half duplex. */ 1636 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1637 /* turn on full duplex LED */ 1638 v |= GEM_MAC_XIF_FDPLX_LED; 1639 else 1640 /* half duplex -- disable echo */ 1641 v |= GEM_MAC_XIF_ECHO_DISABL; 1642 } else 1643 /* Internal MII needs buf enable */ 1644 v |= GEM_MAC_XIF_MII_BUF_ENA; 1645 bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v); 1646 } 1647 1648 int 1649 gem_mediachange(ifp) 1650 struct ifnet *ifp; 1651 { 1652 struct gem_softc *sc = ifp->if_softc; 1653 1654 /* XXX Add support for serial media. */ 1655 1656 return (mii_mediachg(&sc->sc_mii)); 1657 } 1658 1659 void 1660 gem_mediastatus(ifp, ifmr) 1661 struct ifnet *ifp; 1662 struct ifmediareq *ifmr; 1663 { 1664 struct gem_softc *sc = ifp->if_softc; 1665 1666 if ((ifp->if_flags & IFF_UP) == 0) 1667 return; 1668 1669 mii_pollstat(&sc->sc_mii); 1670 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1671 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1672 } 1673 1674 int gem_ioctldebug = 0; 1675 /* 1676 * Process an ioctl request. 1677 */ 1678 int 1679 gem_ioctl(ifp, cmd, data) 1680 struct ifnet *ifp; 1681 u_long cmd; 1682 caddr_t data; 1683 { 1684 struct gem_softc *sc = ifp->if_softc; 1685 struct ifreq *ifr = (struct ifreq *)data; 1686 int s, error = 0; 1687 1688 1689 switch (cmd) { 1690 case SIOCGIFMEDIA: 1691 case SIOCSIFMEDIA: 1692 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1693 break; 1694 1695 default: 1696 error = ether_ioctl(ifp, cmd, data); 1697 if (error == ENETRESET) { 1698 /* 1699 * Multicast list has changed; set the hardware filter 1700 * accordingly. 1701 */ 1702 if (gem_ioctldebug) printf("reset1\n"); 1703 gem_init(ifp); 1704 delay(50000); 1705 error = 0; 1706 } 1707 break; 1708 } 1709 1710 /* Try to get things going again */ 1711 if (ifp->if_flags & IFF_UP) { 1712 if (gem_ioctldebug) printf("start\n"); 1713 gem_start(ifp); 1714 } 1715 splx(s); 1716 return (error); 1717 } 1718 1719 1720 void 1721 gem_shutdown(arg) 1722 void *arg; 1723 { 1724 struct gem_softc *sc = (struct gem_softc *)arg; 1725 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1726 1727 gem_stop(ifp, 1); 1728 } 1729 1730 /* 1731 * Set up the logical address filter. 1732 */ 1733 void 1734 gem_setladrf(sc) 1735 struct gem_softc *sc; 1736 { 1737 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1738 struct ether_multi *enm; 1739 struct ether_multistep step; 1740 struct ethercom *ec = &sc->sc_ethercom; 1741 bus_space_tag_t t = sc->sc_bustag; 1742 bus_space_handle_t h = sc->sc_h; 1743 u_char *cp; 1744 u_int32_t crc; 1745 u_int32_t hash[16]; 1746 u_int32_t v; 1747 int len; 1748 1749 /* Clear hash table */ 1750 memset(hash, 0, sizeof(hash)); 1751 1752 /* Get current RX configuration */ 1753 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 1754 1755 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1756 /* Turn on promiscuous mode; turn off the hash filter */ 1757 v |= GEM_MAC_RX_PROMISCUOUS; 1758 v &= ~GEM_MAC_RX_HASH_FILTER; 1759 ifp->if_flags |= IFF_ALLMULTI; 1760 goto chipit; 1761 } 1762 1763 /* Turn off promiscuous mode; turn on the hash filter */ 1764 v &= ~GEM_MAC_RX_PROMISCUOUS; 1765 v |= GEM_MAC_RX_HASH_FILTER; 1766 1767 /* 1768 * Set up multicast address filter by passing all multicast addresses 1769 * through a crc generator, and then using the high order 6 bits as an 1770 * index into the 256 bit logical address filter. The high order bit 1771 * selects the word, while the rest of the bits select the bit within 1772 * the word. 1773 */ 1774 1775 ETHER_FIRST_MULTI(step, ec, enm); 1776 while (enm != NULL) { 1777 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1778 /* 1779 * We must listen to a range of multicast addresses. 1780 * For now, just accept all multicasts, rather than 1781 * trying to set only those filter bits needed to match 1782 * the range. (At this time, the only use of address 1783 * ranges is for IP multicast routing, for which the 1784 * range is big enough to require all bits set.) 1785 */ 1786 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1787 ifp->if_flags |= IFF_ALLMULTI; 1788 goto chipit; 1789 } 1790 1791 cp = enm->enm_addrlo; 1792 crc = 0xffffffff; 1793 for (len = sizeof(enm->enm_addrlo); --len >= 0;) { 1794 int octet = *cp++; 1795 int i; 1796 1797 #define MC_POLY_LE 0xedb88320UL /* mcast crc, little endian */ 1798 for (i = 0; i < 8; i++) { 1799 if ((crc & 1) ^ (octet & 1)) { 1800 crc >>= 1; 1801 crc ^= MC_POLY_LE; 1802 } else { 1803 crc >>= 1; 1804 } 1805 octet >>= 1; 1806 } 1807 } 1808 /* Just want the 8 most significant bits. */ 1809 crc >>= 24; 1810 1811 /* Set the corresponding bit in the filter. */ 1812 hash[crc >> 4] |= 1 << (crc & 0xf); 1813 1814 ETHER_NEXT_MULTI(step, enm); 1815 } 1816 1817 ifp->if_flags &= ~IFF_ALLMULTI; 1818 1819 chipit: 1820 /* Now load the hash table into the chip */ 1821 bus_space_write_4(t, h, GEM_MAC_HASH0, hash[0]); 1822 bus_space_write_4(t, h, GEM_MAC_HASH1, hash[1]); 1823 bus_space_write_4(t, h, GEM_MAC_HASH2, hash[2]); 1824 bus_space_write_4(t, h, GEM_MAC_HASH3, hash[3]); 1825 bus_space_write_4(t, h, GEM_MAC_HASH4, hash[4]); 1826 bus_space_write_4(t, h, GEM_MAC_HASH5, hash[5]); 1827 bus_space_write_4(t, h, GEM_MAC_HASH6, hash[6]); 1828 bus_space_write_4(t, h, GEM_MAC_HASH7, hash[7]); 1829 bus_space_write_4(t, h, GEM_MAC_HASH8, hash[8]); 1830 bus_space_write_4(t, h, GEM_MAC_HASH9, hash[9]); 1831 bus_space_write_4(t, h, GEM_MAC_HASH10, hash[10]); 1832 bus_space_write_4(t, h, GEM_MAC_HASH11, hash[11]); 1833 bus_space_write_4(t, h, GEM_MAC_HASH12, hash[12]); 1834 bus_space_write_4(t, h, GEM_MAC_HASH13, hash[13]); 1835 bus_space_write_4(t, h, GEM_MAC_HASH14, hash[14]); 1836 bus_space_write_4(t, h, GEM_MAC_HASH15, hash[15]); 1837 1838 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 1839 } 1840 1841 #if notyet 1842 1843 /* 1844 * gem_power: 1845 * 1846 * Power management (suspend/resume) hook. 1847 */ 1848 void 1849 gem_power(why, arg) 1850 int why; 1851 void *arg; 1852 { 1853 struct gem_softc *sc = arg; 1854 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1855 int s; 1856 1857 s = splnet(); 1858 switch (why) { 1859 case PWR_SUSPEND: 1860 case PWR_STANDBY: 1861 gem_stop(ifp, 1); 1862 if (sc->sc_power != NULL) 1863 (*sc->sc_power)(sc, why); 1864 break; 1865 case PWR_RESUME: 1866 if (ifp->if_flags & IFF_UP) { 1867 if (sc->sc_power != NULL) 1868 (*sc->sc_power)(sc, why); 1869 gem_init(ifp); 1870 } 1871 break; 1872 case PWR_SOFTSUSPEND: 1873 case PWR_SOFTSTANDBY: 1874 case PWR_SOFTRESUME: 1875 break; 1876 } 1877 splx(s); 1878 } 1879 #endif 1880
Indexes created Tue Sep 23 07:09:52 GMT 2025