gem.c revision 1.105
1 /* $NetBSD: gem.c,v 1.105 2016/05/17 14:44:53 jdc Exp $ */ 2 3 /* 4 * 5 * Copyright (C) 2001 Eduardo Horvath. 6 * Copyright (c) 2001-2003 Thomas Moestl 7 * All rights reserved. 8 * 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 */ 32 33 /* 34 * Driver for Apple GMAC, Sun ERI and Sun GEM Ethernet controllers 35 * See `GEM Gigabit Ethernet ASIC Specification' 36 * http://www.sun.com/processors/manuals/ge.pdf 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: gem.c,v 1.105 2016/05/17 14:44:53 jdc Exp $"); 41 42 #include "opt_inet.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/callout.h> 47 #include <sys/mbuf.h> 48 #include <sys/syslog.h> 49 #include <sys/malloc.h> 50 #include <sys/kernel.h> 51 #include <sys/socket.h> 52 #include <sys/ioctl.h> 53 #include <sys/errno.h> 54 #include <sys/device.h> 55 56 #include <machine/endian.h> 57 58 #include <net/if.h> 59 #include <net/if_dl.h> 60 #include <net/if_media.h> 61 #include <net/if_ether.h> 62 63 #ifdef INET 64 #include <netinet/in.h> 65 #include <netinet/in_systm.h> 66 #include <netinet/in_var.h> 67 #include <netinet/ip.h> 68 #include <netinet/tcp.h> 69 #include <netinet/udp.h> 70 #endif 71 72 #include <net/bpf.h> 73 74 #include <sys/bus.h> 75 #include <sys/intr.h> 76 77 #include <dev/mii/mii.h> 78 #include <dev/mii/miivar.h> 79 #include <dev/mii/mii_bitbang.h> 80 81 #include <dev/ic/gemreg.h> 82 #include <dev/ic/gemvar.h> 83 84 #define TRIES 10000 85 86 static void gem_inten(struct gem_softc *); 87 static void gem_start(struct ifnet *); 88 static void gem_stop(struct ifnet *, int); 89 int gem_ioctl(struct ifnet *, u_long, void *); 90 void gem_tick(void *); 91 void gem_watchdog(struct ifnet *); 92 void gem_rx_watchdog(void *); 93 void gem_pcs_start(struct gem_softc *sc); 94 void gem_pcs_stop(struct gem_softc *sc, int); 95 int gem_init(struct ifnet *); 96 void gem_init_regs(struct gem_softc *sc); 97 static int gem_ringsize(int sz); 98 static int gem_meminit(struct gem_softc *); 99 void gem_mifinit(struct gem_softc *); 100 static int gem_bitwait(struct gem_softc *sc, bus_space_handle_t, int, 101 u_int32_t, u_int32_t); 102 void gem_reset(struct gem_softc *); 103 int gem_reset_rx(struct gem_softc *sc); 104 static void gem_reset_rxdma(struct gem_softc *sc); 105 static void gem_rx_common(struct gem_softc *sc); 106 int gem_reset_tx(struct gem_softc *sc); 107 int gem_disable_rx(struct gem_softc *sc); 108 int gem_disable_tx(struct gem_softc *sc); 109 static void gem_rxdrain(struct gem_softc *sc); 110 int gem_add_rxbuf(struct gem_softc *sc, int idx); 111 void gem_setladrf(struct gem_softc *); 112 113 /* MII methods & callbacks */ 114 static int gem_mii_readreg(device_t, int, int); 115 static void gem_mii_writereg(device_t, int, int, int); 116 static void gem_mii_statchg(struct ifnet *); 117 118 static int gem_ifflags_cb(struct ethercom *); 119 120 void gem_statuschange(struct gem_softc *); 121 122 int gem_ser_mediachange(struct ifnet *); 123 void gem_ser_mediastatus(struct ifnet *, struct ifmediareq *); 124 125 static void gem_partial_detach(struct gem_softc *, enum gem_attach_stage); 126 127 struct mbuf *gem_get(struct gem_softc *, int, int); 128 int gem_put(struct gem_softc *, int, struct mbuf *); 129 void gem_read(struct gem_softc *, int, int); 130 int gem_pint(struct gem_softc *); 131 int gem_eint(struct gem_softc *, u_int); 132 int gem_rint(struct gem_softc *); 133 int gem_tint(struct gem_softc *); 134 void gem_power(int, void *); 135 136 #ifdef GEM_DEBUG 137 static void gem_txsoft_print(const struct gem_softc *, int, int); 138 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 139 printf x 140 #else 141 #define DPRINTF(sc, x) /* nothing */ 142 #endif 143 144 #define ETHER_MIN_TX (ETHERMIN + sizeof(struct ether_header)) 145 146 int 147 gem_detach(struct gem_softc *sc, int flags) 148 { 149 int i; 150 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 151 bus_space_tag_t t = sc->sc_bustag; 152 bus_space_handle_t h = sc->sc_h1; 153 154 /* 155 * Free any resources we've allocated during the attach. 156 * Do this in reverse order and fall through. 157 */ 158 switch (sc->sc_att_stage) { 159 case GEM_ATT_BACKEND_2: 160 case GEM_ATT_BACKEND_1: 161 case GEM_ATT_FINISHED: 162 bus_space_write_4(t, h, GEM_INTMASK, ~(uint32_t)0); 163 gem_stop(&sc->sc_ethercom.ec_if, 1); 164 165 #ifdef GEM_COUNTERS 166 for (i = __arraycount(sc->sc_ev_rxhist); --i >= 0; ) 167 evcnt_detach(&sc->sc_ev_rxhist[i]); 168 evcnt_detach(&sc->sc_ev_rxnobuf); 169 evcnt_detach(&sc->sc_ev_rxfull); 170 evcnt_detach(&sc->sc_ev_rxint); 171 evcnt_detach(&sc->sc_ev_txint); 172 #endif 173 evcnt_detach(&sc->sc_ev_intr); 174 175 rnd_detach_source(&sc->rnd_source); 176 ether_ifdetach(ifp); 177 if_detach(ifp); 178 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 179 180 callout_destroy(&sc->sc_tick_ch); 181 callout_destroy(&sc->sc_rx_watchdog); 182 183 /*FALLTHROUGH*/ 184 case GEM_ATT_MII: 185 sc->sc_att_stage = GEM_ATT_MII; 186 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 187 /*FALLTHROUGH*/ 188 case GEM_ATT_7: 189 for (i = 0; i < GEM_NRXDESC; i++) { 190 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 191 bus_dmamap_destroy(sc->sc_dmatag, 192 sc->sc_rxsoft[i].rxs_dmamap); 193 } 194 /*FALLTHROUGH*/ 195 case GEM_ATT_6: 196 for (i = 0; i < GEM_TXQUEUELEN; i++) { 197 if (sc->sc_txsoft[i].txs_dmamap != NULL) 198 bus_dmamap_destroy(sc->sc_dmatag, 199 sc->sc_txsoft[i].txs_dmamap); 200 } 201 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 202 /*FALLTHROUGH*/ 203 case GEM_ATT_5: 204 bus_dmamap_unload(sc->sc_dmatag, sc->sc_nulldmamap); 205 /*FALLTHROUGH*/ 206 case GEM_ATT_4: 207 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_nulldmamap); 208 /*FALLTHROUGH*/ 209 case GEM_ATT_3: 210 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 211 /*FALLTHROUGH*/ 212 case GEM_ATT_2: 213 bus_dmamem_unmap(sc->sc_dmatag, sc->sc_control_data, 214 sizeof(struct gem_control_data)); 215 /*FALLTHROUGH*/ 216 case GEM_ATT_1: 217 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 218 /*FALLTHROUGH*/ 219 case GEM_ATT_0: 220 sc->sc_att_stage = GEM_ATT_0; 221 /*FALLTHROUGH*/ 222 case GEM_ATT_BACKEND_0: 223 break; 224 } 225 return 0; 226 } 227 228 static void 229 gem_partial_detach(struct gem_softc *sc, enum gem_attach_stage stage) 230 { 231 cfattach_t ca = device_cfattach(sc->sc_dev); 232 233 sc->sc_att_stage = stage; 234 (*ca->ca_detach)(sc->sc_dev, 0); 235 } 236 237 /* 238 * gem_attach: 239 * 240 * Attach a Gem interface to the system. 241 */ 242 void 243 gem_attach(struct gem_softc *sc, const uint8_t *enaddr) 244 { 245 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 246 struct mii_data *mii = &sc->sc_mii; 247 bus_space_tag_t t = sc->sc_bustag; 248 bus_space_handle_t h = sc->sc_h1; 249 struct ifmedia_entry *ifm; 250 int i, error, phyaddr; 251 u_int32_t v; 252 char *nullbuf; 253 254 /* Make sure the chip is stopped. */ 255 ifp->if_softc = sc; 256 gem_reset(sc); 257 258 /* 259 * Allocate the control data structures, and create and load the 260 * DMA map for it. gem_control_data is 9216 bytes, we have space for 261 * the padding buffer in the bus_dmamem_alloc()'d memory. 262 */ 263 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 264 sizeof(struct gem_control_data) + ETHER_MIN_TX, PAGE_SIZE, 265 0, &sc->sc_cdseg, 1, &sc->sc_cdnseg, 0)) != 0) { 266 aprint_error_dev(sc->sc_dev, 267 "unable to allocate control data, error = %d\n", 268 error); 269 gem_partial_detach(sc, GEM_ATT_0); 270 return; 271 } 272 273 /* XXX should map this in with correct endianness */ 274 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg, 275 sizeof(struct gem_control_data), (void **)&sc->sc_control_data, 276 BUS_DMA_COHERENT)) != 0) { 277 aprint_error_dev(sc->sc_dev, 278 "unable to map control data, error = %d\n", error); 279 gem_partial_detach(sc, GEM_ATT_1); 280 return; 281 } 282 283 nullbuf = 284 (char *)sc->sc_control_data + sizeof(struct gem_control_data); 285 286 if ((error = bus_dmamap_create(sc->sc_dmatag, 287 sizeof(struct gem_control_data), 1, 288 sizeof(struct gem_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 289 aprint_error_dev(sc->sc_dev, 290 "unable to create control data DMA map, error = %d\n", 291 error); 292 gem_partial_detach(sc, GEM_ATT_2); 293 return; 294 } 295 296 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 297 sc->sc_control_data, sizeof(struct gem_control_data), NULL, 298 0)) != 0) { 299 aprint_error_dev(sc->sc_dev, 300 "unable to load control data DMA map, error = %d\n", 301 error); 302 gem_partial_detach(sc, GEM_ATT_3); 303 return; 304 } 305 306 memset(nullbuf, 0, ETHER_MIN_TX); 307 if ((error = bus_dmamap_create(sc->sc_dmatag, 308 ETHER_MIN_TX, 1, ETHER_MIN_TX, 0, 0, &sc->sc_nulldmamap)) != 0) { 309 aprint_error_dev(sc->sc_dev, 310 "unable to create padding DMA map, error = %d\n", error); 311 gem_partial_detach(sc, GEM_ATT_4); 312 return; 313 } 314 315 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_nulldmamap, 316 nullbuf, ETHER_MIN_TX, NULL, 0)) != 0) { 317 aprint_error_dev(sc->sc_dev, 318 "unable to load padding DMA map, error = %d\n", error); 319 gem_partial_detach(sc, GEM_ATT_5); 320 return; 321 } 322 323 bus_dmamap_sync(sc->sc_dmatag, sc->sc_nulldmamap, 0, ETHER_MIN_TX, 324 BUS_DMASYNC_PREWRITE); 325 326 /* 327 * Initialize the transmit job descriptors. 328 */ 329 SIMPLEQ_INIT(&sc->sc_txfreeq); 330 SIMPLEQ_INIT(&sc->sc_txdirtyq); 331 332 /* 333 * Create the transmit buffer DMA maps. 334 */ 335 for (i = 0; i < GEM_TXQUEUELEN; i++) { 336 struct gem_txsoft *txs; 337 338 txs = &sc->sc_txsoft[i]; 339 txs->txs_mbuf = NULL; 340 if ((error = bus_dmamap_create(sc->sc_dmatag, 341 ETHER_MAX_LEN_JUMBO, GEM_NTXSEGS, 342 ETHER_MAX_LEN_JUMBO, 0, 0, 343 &txs->txs_dmamap)) != 0) { 344 aprint_error_dev(sc->sc_dev, 345 "unable to create tx DMA map %d, error = %d\n", 346 i, error); 347 gem_partial_detach(sc, GEM_ATT_6); 348 return; 349 } 350 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 351 } 352 353 /* 354 * Create the receive buffer DMA maps. 355 */ 356 for (i = 0; i < GEM_NRXDESC; i++) { 357 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, 358 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 359 aprint_error_dev(sc->sc_dev, 360 "unable to create rx DMA map %d, error = %d\n", 361 i, error); 362 gem_partial_detach(sc, GEM_ATT_7); 363 return; 364 } 365 sc->sc_rxsoft[i].rxs_mbuf = NULL; 366 } 367 368 /* Initialize ifmedia structures and MII info */ 369 mii->mii_ifp = ifp; 370 mii->mii_readreg = gem_mii_readreg; 371 mii->mii_writereg = gem_mii_writereg; 372 mii->mii_statchg = gem_mii_statchg; 373 374 sc->sc_ethercom.ec_mii = mii; 375 376 /* 377 * Initialization based on `GEM Gigabit Ethernet ASIC Specification' 378 * Section 3.2.1 `Initialization Sequence'. 379 * However, we can't assume SERDES or Serialink if neither 380 * GEM_MIF_CONFIG_MDI0 nor GEM_MIF_CONFIG_MDI1 are set 381 * being set, as both are set on Sun X1141A (with SERDES). So, 382 * we rely on our bus attachment setting GEM_SERDES or GEM_SERIAL. 383 * Also, for variants that report 2 PHY's, we prefer the external 384 * PHY over the internal PHY, so we look for that first. 385 */ 386 gem_mifinit(sc); 387 388 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) { 389 ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange, 390 ether_mediastatus); 391 /* Look for external PHY */ 392 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) { 393 sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL; 394 bus_space_write_4(t, h, GEM_MIF_CONFIG, 395 sc->sc_mif_config); 396 switch (sc->sc_variant) { 397 case GEM_SUN_ERI: 398 phyaddr = GEM_PHYAD_EXTERNAL; 399 break; 400 default: 401 phyaddr = MII_PHY_ANY; 402 break; 403 } 404 mii_attach(sc->sc_dev, mii, 0xffffffff, phyaddr, 405 MII_OFFSET_ANY, MIIF_FORCEANEG); 406 } 407 #ifdef GEM_DEBUG 408 else 409 aprint_debug_dev(sc->sc_dev, "using external PHY\n"); 410 #endif 411 /* Look for internal PHY if no external PHY was found */ 412 if (LIST_EMPTY(&mii->mii_phys) && 413 sc->sc_mif_config & GEM_MIF_CONFIG_MDI0) { 414 sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL; 415 bus_space_write_4(t, h, GEM_MIF_CONFIG, 416 sc->sc_mif_config); 417 switch (sc->sc_variant) { 418 case GEM_SUN_ERI: 419 case GEM_APPLE_K2_GMAC: 420 phyaddr = GEM_PHYAD_INTERNAL; 421 break; 422 case GEM_APPLE_GMAC: 423 phyaddr = GEM_PHYAD_EXTERNAL; 424 break; 425 default: 426 phyaddr = MII_PHY_ANY; 427 break; 428 } 429 mii_attach(sc->sc_dev, mii, 0xffffffff, phyaddr, 430 MII_OFFSET_ANY, MIIF_FORCEANEG); 431 #ifdef GEM_DEBUG 432 if (!LIST_EMPTY(&mii->mii_phys)) 433 aprint_debug_dev(sc->sc_dev, 434 "using internal PHY\n"); 435 #endif 436 } 437 if (LIST_EMPTY(&mii->mii_phys)) { 438 /* No PHY attached */ 439 aprint_error_dev(sc->sc_dev, 440 "PHY probe failed\n"); 441 gem_partial_detach(sc, GEM_ATT_MII); 442 return; 443 } else { 444 struct mii_softc *child; 445 446 /* 447 * Walk along the list of attached MII devices and 448 * establish an `MII instance' to `PHY number' 449 * mapping. 450 */ 451 LIST_FOREACH(child, &mii->mii_phys, mii_list) { 452 /* 453 * Note: we support just one PHY: the internal 454 * or external MII is already selected for us 455 * by the GEM_MIF_CONFIG register. 456 */ 457 if (child->mii_phy > 1 || child->mii_inst > 0) { 458 aprint_error_dev(sc->sc_dev, 459 "cannot accommodate MII device" 460 " %s at PHY %d, instance %d\n", 461 device_xname(child->mii_dev), 462 child->mii_phy, child->mii_inst); 463 continue; 464 } 465 sc->sc_phys[child->mii_inst] = child->mii_phy; 466 } 467 468 if (sc->sc_variant != GEM_SUN_ERI) 469 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 470 GEM_MII_DATAPATH_MII); 471 472 /* 473 * XXX - we can really do the following ONLY if the 474 * PHY indeed has the auto negotiation capability!! 475 */ 476 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 477 } 478 } else { 479 ifmedia_init(&mii->mii_media, IFM_IMASK, gem_ser_mediachange, 480 gem_ser_mediastatus); 481 /* SERDES or Serialink */ 482 if (sc->sc_flags & GEM_SERDES) { 483 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 484 GEM_MII_DATAPATH_SERDES); 485 } else { 486 sc->sc_flags |= GEM_SERIAL; 487 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 488 GEM_MII_DATAPATH_SERIAL); 489 } 490 491 aprint_normal_dev(sc->sc_dev, "using external PCS %s: ", 492 sc->sc_flags & GEM_SERDES ? "SERDES" : "Serialink"); 493 494 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO, 0, NULL); 495 /* Check for FDX and HDX capabilities */ 496 sc->sc_mii_anar = bus_space_read_4(t, h, GEM_MII_ANAR); 497 if (sc->sc_mii_anar & GEM_MII_ANEG_FUL_DUPLX) { 498 ifmedia_add(&sc->sc_mii.mii_media, 499 IFM_ETHER|IFM_1000_SX|IFM_MANUAL|IFM_FDX, 0, NULL); 500 aprint_normal("1000baseSX-FDX, "); 501 } 502 if (sc->sc_mii_anar & GEM_MII_ANEG_HLF_DUPLX) { 503 ifmedia_add(&sc->sc_mii.mii_media, 504 IFM_ETHER|IFM_1000_SX|IFM_MANUAL|IFM_HDX, 0, NULL); 505 aprint_normal("1000baseSX-HDX, "); 506 } 507 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 508 sc->sc_mii_media = IFM_AUTO; 509 aprint_normal("auto\n"); 510 511 gem_pcs_stop(sc, 1); 512 } 513 514 /* 515 * From this point forward, the attachment cannot fail. A failure 516 * before this point releases all resources that may have been 517 * allocated. 518 */ 519 520 /* Announce ourselves. */ 521 aprint_normal_dev(sc->sc_dev, "Ethernet address %s", 522 ether_sprintf(enaddr)); 523 524 /* Get RX FIFO size */ 525 sc->sc_rxfifosize = 64 * 526 bus_space_read_4(t, h, GEM_RX_FIFO_SIZE); 527 aprint_normal(", %uKB RX fifo", sc->sc_rxfifosize / 1024); 528 529 /* Get TX FIFO size */ 530 v = bus_space_read_4(t, h, GEM_TX_FIFO_SIZE); 531 aprint_normal(", %uKB TX fifo\n", v / 16); 532 533 /* Initialize ifnet structure. */ 534 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 535 ifp->if_softc = sc; 536 ifp->if_flags = 537 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 538 sc->sc_if_flags = ifp->if_flags; 539 #if 0 540 /* 541 * The GEM hardware supports basic TCP checksum offloading only. 542 * Several (all?) revisions (Sun rev. 01 and Apple rev. 00 and 80) 543 * have bugs in the receive checksum, so don't enable it for now. 544 */ 545 if ((GEM_IS_SUN(sc) && sc->sc_chiprev != 1) || 546 (GEM_IS_APPLE(sc) && 547 (sc->sc_chiprev != 0 && sc->sc_chiprev != 0x80))) 548 ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Rx; 549 #endif 550 ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Tx; 551 ifp->if_start = gem_start; 552 ifp->if_ioctl = gem_ioctl; 553 ifp->if_watchdog = gem_watchdog; 554 ifp->if_stop = gem_stop; 555 ifp->if_init = gem_init; 556 IFQ_SET_READY(&ifp->if_snd); 557 558 /* 559 * If we support GigE media, we support jumbo frames too. 560 * Unless we are Apple. 561 */ 562 TAILQ_FOREACH(ifm, &sc->sc_mii.mii_media.ifm_list, ifm_list) { 563 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_T || 564 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_SX || 565 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_LX || 566 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_CX) { 567 if (!GEM_IS_APPLE(sc)) 568 sc->sc_ethercom.ec_capabilities 569 |= ETHERCAP_JUMBO_MTU; 570 sc->sc_flags |= GEM_GIGABIT; 571 break; 572 } 573 } 574 575 /* claim 802.1q capability */ 576 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 577 578 /* Attach the interface. */ 579 if_attach(ifp); 580 ether_ifattach(ifp, enaddr); 581 ether_set_ifflags_cb(&sc->sc_ethercom, gem_ifflags_cb); 582 583 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 584 RND_TYPE_NET, RND_FLAG_DEFAULT); 585 586 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, 587 NULL, device_xname(sc->sc_dev), "interrupts"); 588 #ifdef GEM_COUNTERS 589 evcnt_attach_dynamic(&sc->sc_ev_txint, EVCNT_TYPE_INTR, 590 &sc->sc_ev_intr, device_xname(sc->sc_dev), "tx interrupts"); 591 evcnt_attach_dynamic(&sc->sc_ev_rxint, EVCNT_TYPE_INTR, 592 &sc->sc_ev_intr, device_xname(sc->sc_dev), "rx interrupts"); 593 evcnt_attach_dynamic(&sc->sc_ev_rxfull, EVCNT_TYPE_INTR, 594 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx ring full"); 595 evcnt_attach_dynamic(&sc->sc_ev_rxnobuf, EVCNT_TYPE_INTR, 596 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx malloc failure"); 597 evcnt_attach_dynamic(&sc->sc_ev_rxhist[0], EVCNT_TYPE_INTR, 598 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 0desc"); 599 evcnt_attach_dynamic(&sc->sc_ev_rxhist[1], EVCNT_TYPE_INTR, 600 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 1desc"); 601 evcnt_attach_dynamic(&sc->sc_ev_rxhist[2], EVCNT_TYPE_INTR, 602 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 2desc"); 603 evcnt_attach_dynamic(&sc->sc_ev_rxhist[3], EVCNT_TYPE_INTR, 604 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 3desc"); 605 evcnt_attach_dynamic(&sc->sc_ev_rxhist[4], EVCNT_TYPE_INTR, 606 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >3desc"); 607 evcnt_attach_dynamic(&sc->sc_ev_rxhist[5], EVCNT_TYPE_INTR, 608 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >7desc"); 609 evcnt_attach_dynamic(&sc->sc_ev_rxhist[6], EVCNT_TYPE_INTR, 610 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >15desc"); 611 evcnt_attach_dynamic(&sc->sc_ev_rxhist[7], EVCNT_TYPE_INTR, 612 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >31desc"); 613 evcnt_attach_dynamic(&sc->sc_ev_rxhist[8], EVCNT_TYPE_INTR, 614 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >63desc"); 615 #endif 616 617 callout_init(&sc->sc_tick_ch, 0); 618 callout_init(&sc->sc_rx_watchdog, 0); 619 callout_setfunc(&sc->sc_rx_watchdog, gem_rx_watchdog, sc); 620 621 sc->sc_att_stage = GEM_ATT_FINISHED; 622 623 return; 624 } 625 626 void 627 gem_tick(void *arg) 628 { 629 struct gem_softc *sc = arg; 630 int s; 631 632 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) { 633 /* 634 * We have to reset everything if we failed to get a 635 * PCS interrupt. Restarting the callout is handled 636 * in gem_pcs_start(). 637 */ 638 gem_init(&sc->sc_ethercom.ec_if); 639 } else { 640 s = splnet(); 641 mii_tick(&sc->sc_mii); 642 splx(s); 643 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 644 } 645 } 646 647 static int 648 gem_bitwait(struct gem_softc *sc, bus_space_handle_t h, int r, u_int32_t clr, u_int32_t set) 649 { 650 int i; 651 u_int32_t reg; 652 653 for (i = TRIES; i--; DELAY(100)) { 654 reg = bus_space_read_4(sc->sc_bustag, h, r); 655 if ((reg & clr) == 0 && (reg & set) == set) 656 return (1); 657 } 658 return (0); 659 } 660 661 void 662 gem_reset(struct gem_softc *sc) 663 { 664 bus_space_tag_t t = sc->sc_bustag; 665 bus_space_handle_t h = sc->sc_h2; 666 int s; 667 668 s = splnet(); 669 DPRINTF(sc, ("%s: gem_reset\n", device_xname(sc->sc_dev))); 670 gem_reset_rx(sc); 671 gem_reset_tx(sc); 672 673 /* Do a full reset */ 674 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX|GEM_RESET_TX); 675 if (!gem_bitwait(sc, h, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0)) 676 aprint_error_dev(sc->sc_dev, "cannot reset device\n"); 677 splx(s); 678 } 679 680 681 /* 682 * gem_rxdrain: 683 * 684 * Drain the receive queue. 685 */ 686 static void 687 gem_rxdrain(struct gem_softc *sc) 688 { 689 struct gem_rxsoft *rxs; 690 int i; 691 692 for (i = 0; i < GEM_NRXDESC; i++) { 693 rxs = &sc->sc_rxsoft[i]; 694 if (rxs->rxs_mbuf != NULL) { 695 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 696 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 697 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 698 m_freem(rxs->rxs_mbuf); 699 rxs->rxs_mbuf = NULL; 700 } 701 } 702 } 703 704 /* 705 * Reset the whole thing. 706 */ 707 static void 708 gem_stop(struct ifnet *ifp, int disable) 709 { 710 struct gem_softc *sc = ifp->if_softc; 711 struct gem_txsoft *txs; 712 713 DPRINTF(sc, ("%s: gem_stop\n", device_xname(sc->sc_dev))); 714 715 callout_halt(&sc->sc_tick_ch, NULL); 716 callout_halt(&sc->sc_rx_watchdog, NULL); 717 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 718 gem_pcs_stop(sc, disable); 719 else 720 mii_down(&sc->sc_mii); 721 722 /* XXX - Should we reset these instead? */ 723 gem_disable_tx(sc); 724 gem_disable_rx(sc); 725 726 /* 727 * Release any queued transmit buffers. 728 */ 729 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 730 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 731 if (txs->txs_mbuf != NULL) { 732 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 0, 733 txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 734 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 735 m_freem(txs->txs_mbuf); 736 txs->txs_mbuf = NULL; 737 } 738 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 739 } 740 741 /* 742 * Mark the interface down and cancel the watchdog timer. 743 */ 744 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 745 sc->sc_if_flags = ifp->if_flags; 746 ifp->if_timer = 0; 747 748 if (disable) 749 gem_rxdrain(sc); 750 } 751 752 753 /* 754 * Reset the receiver 755 */ 756 int 757 gem_reset_rx(struct gem_softc *sc) 758 { 759 bus_space_tag_t t = sc->sc_bustag; 760 bus_space_handle_t h = sc->sc_h1, h2 = sc->sc_h2; 761 762 /* 763 * Resetting while DMA is in progress can cause a bus hang, so we 764 * disable DMA first. 765 */ 766 gem_disable_rx(sc); 767 bus_space_write_4(t, h, GEM_RX_CONFIG, 0); 768 bus_space_barrier(t, h, GEM_RX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 769 /* Wait till it finishes */ 770 if (!gem_bitwait(sc, h, GEM_RX_CONFIG, 1, 0)) 771 aprint_error_dev(sc->sc_dev, "cannot disable read dma\n"); 772 /* Wait 5ms extra. */ 773 delay(5000); 774 775 /* Finally, reset the ERX */ 776 bus_space_write_4(t, h2, GEM_RESET, GEM_RESET_RX); 777 bus_space_barrier(t, h, GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE); 778 /* Wait till it finishes */ 779 if (!gem_bitwait(sc, h2, GEM_RESET, GEM_RESET_RX, 0)) { 780 aprint_error_dev(sc->sc_dev, "cannot reset receiver\n"); 781 return (1); 782 } 783 return (0); 784 } 785 786 787 /* 788 * Reset the receiver DMA engine. 789 * 790 * Intended to be used in case of GEM_INTR_RX_TAG_ERR, GEM_MAC_RX_OVERFLOW 791 * etc in order to reset the receiver DMA engine only and not do a full 792 * reset which amongst others also downs the link and clears the FIFOs. 793 */ 794 static void 795 gem_reset_rxdma(struct gem_softc *sc) 796 { 797 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 798 bus_space_tag_t t = sc->sc_bustag; 799 bus_space_handle_t h = sc->sc_h1; 800 int i; 801 802 if (gem_reset_rx(sc) != 0) { 803 gem_init(ifp); 804 return; 805 } 806 for (i = 0; i < GEM_NRXDESC; i++) 807 if (sc->sc_rxsoft[i].rxs_mbuf != NULL) 808 GEM_UPDATE_RXDESC(sc, i); 809 sc->sc_rxptr = 0; 810 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE); 811 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD); 812 813 /* Reprogram Descriptor Ring Base Addresses */ 814 /* NOTE: we use only 32-bit DMA addresses here. */ 815 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0); 816 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 817 818 /* Redo ERX Configuration */ 819 gem_rx_common(sc); 820 821 /* Give the reciever a swift kick */ 822 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC - 4); 823 } 824 825 /* 826 * Common RX configuration for gem_init() and gem_reset_rxdma(). 827 */ 828 static void 829 gem_rx_common(struct gem_softc *sc) 830 { 831 bus_space_tag_t t = sc->sc_bustag; 832 bus_space_handle_t h = sc->sc_h1; 833 u_int32_t v; 834 835 /* Encode Receive Descriptor ring size: four possible values */ 836 v = gem_ringsize(GEM_NRXDESC /*XXX*/); 837 838 /* Set receive h/w checksum offset */ 839 #ifdef INET 840 v |= (ETHER_HDR_LEN + sizeof(struct ip) + 841 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 842 ETHER_VLAN_ENCAP_LEN : 0)) << GEM_RX_CONFIG_CXM_START_SHFT; 843 #endif 844 845 /* Enable RX DMA */ 846 bus_space_write_4(t, h, GEM_RX_CONFIG, 847 v | (GEM_THRSH_1024 << GEM_RX_CONFIG_FIFO_THRS_SHIFT) | 848 (2 << GEM_RX_CONFIG_FBOFF_SHFT) | GEM_RX_CONFIG_RXDMA_EN); 849 850 /* 851 * The following value is for an OFF Threshold of about 3/4 full 852 * and an ON Threshold of 1/4 full. 853 */ 854 bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH, 855 (3 * sc->sc_rxfifosize / 256) | 856 ((sc->sc_rxfifosize / 256) << 12)); 857 bus_space_write_4(t, h, GEM_RX_BLANKING, 858 (6 << GEM_RX_BLANKING_TIME_SHIFT) | 8); 859 } 860 861 /* 862 * Reset the transmitter 863 */ 864 int 865 gem_reset_tx(struct gem_softc *sc) 866 { 867 bus_space_tag_t t = sc->sc_bustag; 868 bus_space_handle_t h = sc->sc_h1, h2 = sc->sc_h2; 869 870 /* 871 * Resetting while DMA is in progress can cause a bus hang, so we 872 * disable DMA first. 873 */ 874 gem_disable_tx(sc); 875 bus_space_write_4(t, h, GEM_TX_CONFIG, 0); 876 bus_space_barrier(t, h, GEM_TX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 877 /* Wait till it finishes */ 878 if (!gem_bitwait(sc, h, GEM_TX_CONFIG, 1, 0)) 879 aprint_error_dev(sc->sc_dev, "cannot disable read dma\n"); 880 /* Wait 5ms extra. */ 881 delay(5000); 882 883 /* Finally, reset the ETX */ 884 bus_space_write_4(t, h2, GEM_RESET, GEM_RESET_TX); 885 bus_space_barrier(t, h, GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE); 886 /* Wait till it finishes */ 887 if (!gem_bitwait(sc, h2, GEM_RESET, GEM_RESET_TX, 0)) { 888 aprint_error_dev(sc->sc_dev, "cannot reset receiver\n"); 889 return (1); 890 } 891 return (0); 892 } 893 894 /* 895 * disable receiver. 896 */ 897 int 898 gem_disable_rx(struct gem_softc *sc) 899 { 900 bus_space_tag_t t = sc->sc_bustag; 901 bus_space_handle_t h = sc->sc_h1; 902 u_int32_t cfg; 903 904 /* Flip the enable bit */ 905 cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 906 cfg &= ~GEM_MAC_RX_ENABLE; 907 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg); 908 bus_space_barrier(t, h, GEM_MAC_RX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 909 /* Wait for it to finish */ 910 return (gem_bitwait(sc, h, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)); 911 } 912 913 /* 914 * disable transmitter. 915 */ 916 int 917 gem_disable_tx(struct gem_softc *sc) 918 { 919 bus_space_tag_t t = sc->sc_bustag; 920 bus_space_handle_t h = sc->sc_h1; 921 u_int32_t cfg; 922 923 /* Flip the enable bit */ 924 cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG); 925 cfg &= ~GEM_MAC_TX_ENABLE; 926 bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg); 927 bus_space_barrier(t, h, GEM_MAC_TX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 928 /* Wait for it to finish */ 929 return (gem_bitwait(sc, h, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)); 930 } 931 932 /* 933 * Initialize interface. 934 */ 935 int 936 gem_meminit(struct gem_softc *sc) 937 { 938 struct gem_rxsoft *rxs; 939 int i, error; 940 941 /* 942 * Initialize the transmit descriptor ring. 943 */ 944 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 945 for (i = 0; i < GEM_NTXDESC; i++) { 946 sc->sc_txdescs[i].gd_flags = 0; 947 sc->sc_txdescs[i].gd_addr = 0; 948 } 949 GEM_CDTXSYNC(sc, 0, GEM_NTXDESC, 950 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 951 sc->sc_txfree = GEM_NTXDESC-1; 952 sc->sc_txnext = 0; 953 sc->sc_txwin = 0; 954 955 /* 956 * Initialize the receive descriptor and receive job 957 * descriptor rings. 958 */ 959 for (i = 0; i < GEM_NRXDESC; i++) { 960 rxs = &sc->sc_rxsoft[i]; 961 if (rxs->rxs_mbuf == NULL) { 962 if ((error = gem_add_rxbuf(sc, i)) != 0) { 963 aprint_error_dev(sc->sc_dev, 964 "unable to allocate or map rx " 965 "buffer %d, error = %d\n", 966 i, error); 967 /* 968 * XXX Should attempt to run with fewer receive 969 * XXX buffers instead of just failing. 970 */ 971 gem_rxdrain(sc); 972 return (1); 973 } 974 } else 975 GEM_INIT_RXDESC(sc, i); 976 } 977 sc->sc_rxptr = 0; 978 sc->sc_meminited = 1; 979 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE); 980 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD); 981 982 return (0); 983 } 984 985 static int 986 gem_ringsize(int sz) 987 { 988 switch (sz) { 989 case 32: 990 return GEM_RING_SZ_32; 991 case 64: 992 return GEM_RING_SZ_64; 993 case 128: 994 return GEM_RING_SZ_128; 995 case 256: 996 return GEM_RING_SZ_256; 997 case 512: 998 return GEM_RING_SZ_512; 999 case 1024: 1000 return GEM_RING_SZ_1024; 1001 case 2048: 1002 return GEM_RING_SZ_2048; 1003 case 4096: 1004 return GEM_RING_SZ_4096; 1005 case 8192: 1006 return GEM_RING_SZ_8192; 1007 default: 1008 printf("gem: invalid Receive Descriptor ring size %d\n", sz); 1009 return GEM_RING_SZ_32; 1010 } 1011 } 1012 1013 1014 /* 1015 * Start PCS 1016 */ 1017 void 1018 gem_pcs_start(struct gem_softc *sc) 1019 { 1020 bus_space_tag_t t = sc->sc_bustag; 1021 bus_space_handle_t h = sc->sc_h1; 1022 uint32_t v; 1023 1024 #ifdef GEM_DEBUG 1025 aprint_debug_dev(sc->sc_dev, "gem_pcs_start()\n"); 1026 #endif 1027 1028 /* 1029 * Set up. We must disable the MII before modifying the 1030 * GEM_MII_ANAR register 1031 */ 1032 if (sc->sc_flags & GEM_SERDES) { 1033 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 1034 GEM_MII_DATAPATH_SERDES); 1035 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 1036 GEM_MII_SLINK_LOOPBACK); 1037 } else { 1038 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 1039 GEM_MII_DATAPATH_SERIAL); 1040 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 0); 1041 } 1042 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 1043 v = bus_space_read_4(t, h, GEM_MII_ANAR); 1044 v |= (GEM_MII_ANEG_SYM_PAUSE | GEM_MII_ANEG_ASYM_PAUSE); 1045 if (sc->sc_mii_media == IFM_AUTO) 1046 v |= (GEM_MII_ANEG_FUL_DUPLX | GEM_MII_ANEG_HLF_DUPLX); 1047 else if (sc->sc_mii_media == IFM_FDX) { 1048 v |= GEM_MII_ANEG_FUL_DUPLX; 1049 v &= ~GEM_MII_ANEG_HLF_DUPLX; 1050 } else if (sc->sc_mii_media == IFM_HDX) { 1051 v &= ~GEM_MII_ANEG_FUL_DUPLX; 1052 v |= GEM_MII_ANEG_HLF_DUPLX; 1053 } 1054 1055 /* Configure link. */ 1056 bus_space_write_4(t, h, GEM_MII_ANAR, v); 1057 bus_space_write_4(t, h, GEM_MII_CONTROL, 1058 GEM_MII_CONTROL_AUTONEG | GEM_MII_CONTROL_RAN); 1059 bus_space_write_4(t, h, GEM_MII_CONFIG, GEM_MII_CONFIG_ENABLE); 1060 gem_bitwait(sc, h, GEM_MII_STATUS, 0, GEM_MII_STATUS_ANEG_CPT); 1061 1062 /* Start the 10 second timer */ 1063 callout_reset(&sc->sc_tick_ch, hz * 10, gem_tick, sc); 1064 } 1065 1066 /* 1067 * Stop PCS 1068 */ 1069 void 1070 gem_pcs_stop(struct gem_softc *sc, int disable) 1071 { 1072 bus_space_tag_t t = sc->sc_bustag; 1073 bus_space_handle_t h = sc->sc_h1; 1074 1075 #ifdef GEM_DEBUG 1076 aprint_debug_dev(sc->sc_dev, "gem_pcs_stop()\n"); 1077 #endif 1078 1079 /* Tell link partner that we're going away */ 1080 bus_space_write_4(t, h, GEM_MII_ANAR, GEM_MII_ANEG_RF); 1081 1082 /* 1083 * Disable PCS MII. The documentation suggests that setting 1084 * GEM_MII_CONFIG_ENABLE to zero and then restarting auto- 1085 * negotiation will shut down the link. However, it appears 1086 * that we also need to unset the datapath mode. 1087 */ 1088 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 1089 bus_space_write_4(t, h, GEM_MII_CONTROL, 1090 GEM_MII_CONTROL_AUTONEG | GEM_MII_CONTROL_RAN); 1091 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, GEM_MII_DATAPATH_MII); 1092 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 1093 1094 if (disable) { 1095 if (sc->sc_flags & GEM_SERDES) 1096 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 1097 GEM_MII_SLINK_POWER_OFF); 1098 else 1099 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 1100 GEM_MII_SLINK_LOOPBACK | GEM_MII_SLINK_POWER_OFF); 1101 } 1102 1103 sc->sc_flags &= ~GEM_LINK; 1104 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_NONE; 1105 sc->sc_mii.mii_media_status = IFM_AVALID; 1106 } 1107 1108 1109 /* 1110 * Initialization of interface; set up initialization block 1111 * and transmit/receive descriptor rings. 1112 */ 1113 int 1114 gem_init(struct ifnet *ifp) 1115 { 1116 struct gem_softc *sc = ifp->if_softc; 1117 bus_space_tag_t t = sc->sc_bustag; 1118 bus_space_handle_t h = sc->sc_h1; 1119 int rc = 0, s; 1120 u_int max_frame_size; 1121 u_int32_t v; 1122 1123 s = splnet(); 1124 1125 DPRINTF(sc, ("%s: gem_init: calling stop\n", device_xname(sc->sc_dev))); 1126 /* 1127 * Initialization sequence. The numbered steps below correspond 1128 * to the sequence outlined in section 6.3.5.1 in the Ethernet 1129 * Channel Engine manual (part of the PCIO manual). 1130 * See also the STP2002-STQ document from Sun Microsystems. 1131 */ 1132 1133 /* step 1 & 2. Reset the Ethernet Channel */ 1134 gem_stop(ifp, 0); 1135 gem_reset(sc); 1136 DPRINTF(sc, ("%s: gem_init: restarting\n", device_xname(sc->sc_dev))); 1137 1138 /* Re-initialize the MIF */ 1139 gem_mifinit(sc); 1140 1141 /* Set up correct datapath for non-SERDES/Serialink */ 1142 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0 && 1143 sc->sc_variant != GEM_SUN_ERI) 1144 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 1145 GEM_MII_DATAPATH_MII); 1146 1147 /* Call MI reset function if any */ 1148 if (sc->sc_hwreset) 1149 (*sc->sc_hwreset)(sc); 1150 1151 /* step 3. Setup data structures in host memory */ 1152 if (gem_meminit(sc) != 0) { 1153 splx(s); 1154 return 1; 1155 } 1156 1157 /* step 4. TX MAC registers & counters */ 1158 gem_init_regs(sc); 1159 max_frame_size = max(sc->sc_ethercom.ec_if.if_mtu, ETHERMTU); 1160 max_frame_size += ETHER_HDR_LEN + ETHER_CRC_LEN; 1161 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1162 max_frame_size += ETHER_VLAN_ENCAP_LEN; 1163 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 1164 max_frame_size|/* burst size */(0x2000<<16)); 1165 1166 /* step 5. RX MAC registers & counters */ 1167 gem_setladrf(sc); 1168 1169 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 1170 /* NOTE: we use only 32-bit DMA addresses here. */ 1171 bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 0); 1172 bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 1173 1174 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0); 1175 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 1176 1177 /* step 8. Global Configuration & Interrupt Mask */ 1178 gem_inten(sc); 1179 bus_space_write_4(t, h, GEM_MAC_RX_MASK, 1180 GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT); 1181 bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXX */ 1182 bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 1183 GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME); 1184 1185 /* step 9. ETX Configuration: use mostly default values */ 1186 1187 /* Enable TX DMA */ 1188 v = gem_ringsize(GEM_NTXDESC /*XXX*/); 1189 bus_space_write_4(t, h, GEM_TX_CONFIG, 1190 v | GEM_TX_CONFIG_TXDMA_EN | 1191 (((sc->sc_flags & GEM_GIGABIT ? 0x4FF : 0x100) << 10) & 1192 GEM_TX_CONFIG_TXFIFO_TH)); 1193 bus_space_write_4(t, h, GEM_TX_KICK, sc->sc_txnext); 1194 1195 /* step 10. ERX Configuration */ 1196 gem_rx_common(sc); 1197 1198 /* step 11. Configure Media */ 1199 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0 && 1200 (rc = mii_ifmedia_change(&sc->sc_mii)) != 0) 1201 goto out; 1202 1203 /* step 12. RX_MAC Configuration Register */ 1204 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 1205 v |= GEM_MAC_RX_ENABLE | GEM_MAC_RX_STRIP_CRC; 1206 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 1207 1208 /* step 14. Issue Transmit Pending command */ 1209 1210 /* Call MI initialization function if any */ 1211 if (sc->sc_hwinit) 1212 (*sc->sc_hwinit)(sc); 1213 1214 1215 /* step 15. Give the reciever a swift kick */ 1216 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4); 1217 1218 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 1219 /* Configure PCS */ 1220 gem_pcs_start(sc); 1221 else 1222 /* Start the one second timer. */ 1223 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 1224 1225 sc->sc_flags &= ~GEM_LINK; 1226 ifp->if_flags |= IFF_RUNNING; 1227 ifp->if_flags &= ~IFF_OACTIVE; 1228 ifp->if_timer = 0; 1229 sc->sc_if_flags = ifp->if_flags; 1230 out: 1231 splx(s); 1232 1233 return (0); 1234 } 1235 1236 void 1237 gem_init_regs(struct gem_softc *sc) 1238 { 1239 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1240 bus_space_tag_t t = sc->sc_bustag; 1241 bus_space_handle_t h = sc->sc_h1; 1242 const u_char *laddr = CLLADDR(ifp->if_sadl); 1243 u_int32_t v; 1244 1245 /* These regs are not cleared on reset */ 1246 if (!sc->sc_inited) { 1247 1248 /* Load recommended values */ 1249 bus_space_write_4(t, h, GEM_MAC_IPG0, 0x00); 1250 bus_space_write_4(t, h, GEM_MAC_IPG1, 0x08); 1251 bus_space_write_4(t, h, GEM_MAC_IPG2, 0x04); 1252 1253 bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 1254 /* Max frame and max burst size */ 1255 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 1256 ETHER_MAX_LEN | (0x2000<<16)); 1257 1258 bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x07); 1259 bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x04); 1260 bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10); 1261 bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088); 1262 bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED, 1263 ((laddr[5]<<8)|laddr[4])&0x3ff); 1264 1265 /* Secondary MAC addr set to 0:0:0:0:0:0 */ 1266 bus_space_write_4(t, h, GEM_MAC_ADDR3, 0); 1267 bus_space_write_4(t, h, GEM_MAC_ADDR4, 0); 1268 bus_space_write_4(t, h, GEM_MAC_ADDR5, 0); 1269 1270 /* MAC control addr set to 01:80:c2:00:00:01 */ 1271 bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001); 1272 bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200); 1273 bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180); 1274 1275 /* MAC filter addr set to 0:0:0:0:0:0 */ 1276 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0); 1277 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0); 1278 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0); 1279 1280 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0); 1281 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0); 1282 1283 sc->sc_inited = 1; 1284 } 1285 1286 /* Counters need to be zeroed */ 1287 bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0); 1288 bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0); 1289 bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0); 1290 bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0); 1291 bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0); 1292 bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0); 1293 bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0); 1294 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 1295 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 1296 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 1297 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 1298 1299 /* Set XOFF PAUSE time. */ 1300 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); 1301 1302 /* 1303 * Set the internal arbitration to "infinite" bursts of the 1304 * maximum length of 31 * 64 bytes so DMA transfers aren't 1305 * split up in cache line size chunks. This greatly improves 1306 * especially RX performance. 1307 * Enable silicon bug workarounds for the Apple variants. 1308 */ 1309 bus_space_write_4(t, h, GEM_CONFIG, 1310 GEM_CONFIG_TXDMA_LIMIT | GEM_CONFIG_RXDMA_LIMIT | 1311 ((sc->sc_flags & GEM_PCI) ? 1312 GEM_CONFIG_BURST_INF : GEM_CONFIG_BURST_64) | (GEM_IS_APPLE(sc) ? 1313 GEM_CONFIG_RONPAULBIT | GEM_CONFIG_BUG2FIX : 0)); 1314 1315 /* 1316 * Set the station address. 1317 */ 1318 bus_space_write_4(t, h, GEM_MAC_ADDR0, (laddr[4]<<8)|laddr[5]); 1319 bus_space_write_4(t, h, GEM_MAC_ADDR1, (laddr[2]<<8)|laddr[3]); 1320 bus_space_write_4(t, h, GEM_MAC_ADDR2, (laddr[0]<<8)|laddr[1]); 1321 1322 /* 1323 * Enable MII outputs. Enable GMII if there is a gigabit PHY. 1324 */ 1325 sc->sc_mif_config = bus_space_read_4(t, h, GEM_MIF_CONFIG); 1326 v = GEM_MAC_XIF_TX_MII_ENA; 1327 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) { 1328 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) { 1329 v |= GEM_MAC_XIF_FDPLX_LED; 1330 if (sc->sc_flags & GEM_GIGABIT) 1331 v |= GEM_MAC_XIF_GMII_MODE; 1332 } 1333 } else { 1334 v |= GEM_MAC_XIF_GMII_MODE; 1335 } 1336 bus_space_write_4(t, h, GEM_MAC_XIF_CONFIG, v); 1337 } 1338 1339 #ifdef GEM_DEBUG 1340 static void 1341 gem_txsoft_print(const struct gem_softc *sc, int firstdesc, int lastdesc) 1342 { 1343 int i; 1344 1345 for (i = firstdesc;; i = GEM_NEXTTX(i)) { 1346 printf("descriptor %d:\t", i); 1347 printf("gd_flags: 0x%016" PRIx64 "\t", 1348 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags)); 1349 printf("gd_addr: 0x%016" PRIx64 "\n", 1350 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr)); 1351 if (i == lastdesc) 1352 break; 1353 } 1354 } 1355 #endif 1356 1357 static void 1358 gem_start(struct ifnet *ifp) 1359 { 1360 struct gem_softc *sc = ifp->if_softc; 1361 struct mbuf *m0, *m; 1362 struct gem_txsoft *txs; 1363 bus_dmamap_t dmamap; 1364 int error, firsttx, nexttx = -1, lasttx = -1, ofree, seg; 1365 #ifdef GEM_DEBUG 1366 int otxnext; 1367 #endif 1368 uint64_t flags = 0; 1369 1370 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1371 return; 1372 1373 /* 1374 * Remember the previous number of free descriptors and 1375 * the first descriptor we'll use. 1376 */ 1377 ofree = sc->sc_txfree; 1378 #ifdef GEM_DEBUG 1379 otxnext = sc->sc_txnext; 1380 #endif 1381 1382 DPRINTF(sc, ("%s: gem_start: txfree %d, txnext %d\n", 1383 device_xname(sc->sc_dev), ofree, otxnext)); 1384 1385 /* 1386 * Loop through the send queue, setting up transmit descriptors 1387 * until we drain the queue, or use up all available transmit 1388 * descriptors. 1389 */ 1390 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 1391 sc->sc_txfree != 0) { 1392 /* 1393 * Grab a packet off the queue. 1394 */ 1395 IFQ_POLL(&ifp->if_snd, m0); 1396 if (m0 == NULL) 1397 break; 1398 m = NULL; 1399 1400 dmamap = txs->txs_dmamap; 1401 1402 /* 1403 * Load the DMA map. If this fails, the packet either 1404 * didn't fit in the alloted number of segments, or we were 1405 * short on resources. In this case, we'll copy and try 1406 * again. 1407 */ 1408 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m0, 1409 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0 || 1410 (m0->m_pkthdr.len < ETHER_MIN_TX && 1411 dmamap->dm_nsegs == GEM_NTXSEGS)) { 1412 if (m0->m_pkthdr.len > MCLBYTES) { 1413 aprint_error_dev(sc->sc_dev, 1414 "unable to allocate jumbo Tx cluster\n"); 1415 IFQ_DEQUEUE(&ifp->if_snd, m0); 1416 m_freem(m0); 1417 continue; 1418 } 1419 MGETHDR(m, M_DONTWAIT, MT_DATA); 1420 if (m == NULL) { 1421 aprint_error_dev(sc->sc_dev, 1422 "unable to allocate Tx mbuf\n"); 1423 break; 1424 } 1425 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1426 if (m0->m_pkthdr.len > MHLEN) { 1427 MCLGET(m, M_DONTWAIT); 1428 if ((m->m_flags & M_EXT) == 0) { 1429 aprint_error_dev(sc->sc_dev, 1430 "unable to allocate Tx cluster\n"); 1431 m_freem(m); 1432 break; 1433 } 1434 } 1435 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1436 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1437 error = bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, 1438 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1439 if (error) { 1440 aprint_error_dev(sc->sc_dev, 1441 "unable to load Tx buffer, error = %d\n", 1442 error); 1443 break; 1444 } 1445 } 1446 1447 /* 1448 * Ensure we have enough descriptors free to describe 1449 * the packet. 1450 */ 1451 if (dmamap->dm_nsegs > ((m0->m_pkthdr.len < ETHER_MIN_TX) ? 1452 (sc->sc_txfree - 1) : sc->sc_txfree)) { 1453 /* 1454 * Not enough free descriptors to transmit this 1455 * packet. We haven't committed to anything yet, 1456 * so just unload the DMA map, put the packet 1457 * back on the queue, and punt. Notify the upper 1458 * layer that there are no more slots left. 1459 * 1460 * XXX We could allocate an mbuf and copy, but 1461 * XXX it is worth it? 1462 */ 1463 ifp->if_flags |= IFF_OACTIVE; 1464 sc->sc_if_flags = ifp->if_flags; 1465 bus_dmamap_unload(sc->sc_dmatag, dmamap); 1466 if (m != NULL) 1467 m_freem(m); 1468 break; 1469 } 1470 1471 IFQ_DEQUEUE(&ifp->if_snd, m0); 1472 if (m != NULL) { 1473 m_freem(m0); 1474 m0 = m; 1475 } 1476 1477 /* 1478 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1479 */ 1480 1481 /* Sync the DMA map. */ 1482 bus_dmamap_sync(sc->sc_dmatag, dmamap, 0, dmamap->dm_mapsize, 1483 BUS_DMASYNC_PREWRITE); 1484 1485 /* 1486 * Initialize the transmit descriptors. 1487 */ 1488 firsttx = sc->sc_txnext; 1489 for (nexttx = firsttx, seg = 0; 1490 seg < dmamap->dm_nsegs; 1491 seg++, nexttx = GEM_NEXTTX(nexttx)) { 1492 1493 /* 1494 * If this is the first descriptor we're 1495 * enqueueing, set the start of packet flag, 1496 * and the checksum stuff if we want the hardware 1497 * to do it. 1498 */ 1499 sc->sc_txdescs[nexttx].gd_addr = 1500 GEM_DMA_WRITE(sc, dmamap->dm_segs[seg].ds_addr); 1501 flags = dmamap->dm_segs[seg].ds_len & GEM_TD_BUFSIZE; 1502 if (nexttx == firsttx) { 1503 flags |= GEM_TD_START_OF_PACKET; 1504 if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) { 1505 sc->sc_txwin = 0; 1506 flags |= GEM_TD_INTERRUPT_ME; 1507 } 1508 1509 #ifdef INET 1510 /* h/w checksum */ 1511 if (ifp->if_csum_flags_tx & M_CSUM_TCPv4 && 1512 m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1513 struct ether_header *eh; 1514 uint16_t offset, start; 1515 1516 eh = mtod(m0, struct ether_header *); 1517 switch (ntohs(eh->ether_type)) { 1518 case ETHERTYPE_IP: 1519 start = ETHER_HDR_LEN; 1520 break; 1521 case ETHERTYPE_VLAN: 1522 start = ETHER_HDR_LEN + 1523 ETHER_VLAN_ENCAP_LEN; 1524 break; 1525 default: 1526 /* unsupported, drop it */ 1527 m_free(m0); 1528 continue; 1529 } 1530 start += M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 1531 offset = M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data) + start; 1532 flags |= (start << 1533 GEM_TD_CXSUM_STARTSHFT) | 1534 (offset << 1535 GEM_TD_CXSUM_STUFFSHFT) | 1536 GEM_TD_CXSUM_ENABLE; 1537 } 1538 #endif 1539 } 1540 if (seg == dmamap->dm_nsegs - 1) { 1541 flags |= GEM_TD_END_OF_PACKET; 1542 } else { 1543 /* last flag set outside of loop */ 1544 sc->sc_txdescs[nexttx].gd_flags = 1545 GEM_DMA_WRITE(sc, flags); 1546 } 1547 lasttx = nexttx; 1548 } 1549 if (m0->m_pkthdr.len < ETHER_MIN_TX) { 1550 /* add padding buffer at end of chain */ 1551 flags &= ~GEM_TD_END_OF_PACKET; 1552 sc->sc_txdescs[lasttx].gd_flags = 1553 GEM_DMA_WRITE(sc, flags); 1554 1555 sc->sc_txdescs[nexttx].gd_addr = 1556 GEM_DMA_WRITE(sc, 1557 sc->sc_nulldmamap->dm_segs[0].ds_addr); 1558 flags = ((ETHER_MIN_TX - m0->m_pkthdr.len) & 1559 GEM_TD_BUFSIZE) | GEM_TD_END_OF_PACKET; 1560 lasttx = nexttx; 1561 nexttx = GEM_NEXTTX(nexttx); 1562 seg++; 1563 } 1564 sc->sc_txdescs[lasttx].gd_flags = GEM_DMA_WRITE(sc, flags); 1565 1566 KASSERT(lasttx != -1); 1567 1568 /* 1569 * Store a pointer to the packet so we can free it later, 1570 * and remember what txdirty will be once the packet is 1571 * done. 1572 */ 1573 txs->txs_mbuf = m0; 1574 txs->txs_firstdesc = sc->sc_txnext; 1575 txs->txs_lastdesc = lasttx; 1576 txs->txs_ndescs = seg; 1577 1578 #ifdef GEM_DEBUG 1579 if (ifp->if_flags & IFF_DEBUG) { 1580 printf(" gem_start %p transmit chain:\n", txs); 1581 gem_txsoft_print(sc, txs->txs_firstdesc, 1582 txs->txs_lastdesc); 1583 } 1584 #endif 1585 1586 /* Sync the descriptors we're using. */ 1587 GEM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndescs, 1588 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1589 1590 /* Advance the tx pointer. */ 1591 sc->sc_txfree -= txs->txs_ndescs; 1592 sc->sc_txnext = nexttx; 1593 1594 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1595 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1596 1597 /* 1598 * Pass the packet to any BPF listeners. 1599 */ 1600 bpf_mtap(ifp, m0); 1601 } 1602 1603 if (txs == NULL || sc->sc_txfree == 0) { 1604 /* No more slots left; notify upper layer. */ 1605 ifp->if_flags |= IFF_OACTIVE; 1606 sc->sc_if_flags = ifp->if_flags; 1607 } 1608 1609 if (sc->sc_txfree != ofree) { 1610 DPRINTF(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 1611 device_xname(sc->sc_dev), lasttx, otxnext)); 1612 /* 1613 * The entire packet chain is set up. 1614 * Kick the transmitter. 1615 */ 1616 DPRINTF(sc, ("%s: gem_start: kicking tx %d\n", 1617 device_xname(sc->sc_dev), nexttx)); 1618 bus_space_write_4(sc->sc_bustag, sc->sc_h1, GEM_TX_KICK, 1619 sc->sc_txnext); 1620 1621 /* Set a watchdog timer in case the chip flakes out. */ 1622 ifp->if_timer = 5; 1623 DPRINTF(sc, ("%s: gem_start: watchdog %d\n", 1624 device_xname(sc->sc_dev), ifp->if_timer)); 1625 } 1626 } 1627 1628 /* 1629 * Transmit interrupt. 1630 */ 1631 int 1632 gem_tint(struct gem_softc *sc) 1633 { 1634 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1635 bus_space_tag_t t = sc->sc_bustag; 1636 bus_space_handle_t mac = sc->sc_h1; 1637 struct gem_txsoft *txs; 1638 int txlast; 1639 int progress = 0; 1640 u_int32_t v; 1641 1642 DPRINTF(sc, ("%s: gem_tint\n", device_xname(sc->sc_dev))); 1643 1644 /* Unload collision counters ... */ 1645 v = bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) + 1646 bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT); 1647 ifp->if_collisions += v + 1648 bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) + 1649 bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT); 1650 ifp->if_oerrors += v; 1651 1652 /* ... then clear the hardware counters. */ 1653 bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0); 1654 bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0); 1655 bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0); 1656 bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0); 1657 1658 /* 1659 * Go through our Tx list and free mbufs for those 1660 * frames that have been transmitted. 1661 */ 1662 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1663 /* 1664 * In theory, we could harvest some descriptors before 1665 * the ring is empty, but that's a bit complicated. 1666 * 1667 * GEM_TX_COMPLETION points to the last descriptor 1668 * processed +1. 1669 * 1670 * Let's assume that the NIC writes back to the Tx 1671 * descriptors before it updates the completion 1672 * register. If the NIC has posted writes to the 1673 * Tx descriptors, PCI ordering requires that the 1674 * posted writes flush to RAM before the register-read 1675 * finishes. So let's read the completion register, 1676 * before syncing the descriptors, so that we 1677 * examine Tx descriptors that are at least as 1678 * current as the completion register. 1679 */ 1680 txlast = bus_space_read_4(t, mac, GEM_TX_COMPLETION); 1681 DPRINTF(sc, 1682 ("gem_tint: txs->txs_lastdesc = %d, txlast = %d\n", 1683 txs->txs_lastdesc, txlast)); 1684 if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1685 if (txlast >= txs->txs_firstdesc && 1686 txlast <= txs->txs_lastdesc) 1687 break; 1688 } else if (txlast >= txs->txs_firstdesc || 1689 txlast <= txs->txs_lastdesc) 1690 break; 1691 1692 GEM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndescs, 1693 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1694 1695 #ifdef GEM_DEBUG /* XXX DMA synchronization? */ 1696 if (ifp->if_flags & IFF_DEBUG) { 1697 printf(" txsoft %p transmit chain:\n", txs); 1698 gem_txsoft_print(sc, txs->txs_firstdesc, 1699 txs->txs_lastdesc); 1700 } 1701 #endif 1702 1703 1704 DPRINTF(sc, ("gem_tint: releasing a desc\n")); 1705 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1706 1707 sc->sc_txfree += txs->txs_ndescs; 1708 1709 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 1710 0, txs->txs_dmamap->dm_mapsize, 1711 BUS_DMASYNC_POSTWRITE); 1712 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 1713 if (txs->txs_mbuf != NULL) { 1714 m_freem(txs->txs_mbuf); 1715 txs->txs_mbuf = NULL; 1716 } 1717 1718 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1719 1720 ifp->if_opackets++; 1721 progress = 1; 1722 } 1723 1724 #if 0 1725 DPRINTF(sc, ("gem_tint: GEM_TX_STATE_MACHINE %x " 1726 "GEM_TX_DATA_PTR %" PRIx64 "GEM_TX_COMPLETION %" PRIx32 "\n", 1727 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_TX_STATE_MACHINE), 1728 ((uint64_t)bus_space_read_4(sc->sc_bustag, sc->sc_h1, 1729 GEM_TX_DATA_PTR_HI) << 32) | 1730 bus_space_read_4(sc->sc_bustag, sc->sc_h1, 1731 GEM_TX_DATA_PTR_LO), 1732 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_TX_COMPLETION))); 1733 #endif 1734 1735 if (progress) { 1736 if (sc->sc_txfree == GEM_NTXDESC - 1) 1737 sc->sc_txwin = 0; 1738 1739 /* Freed some descriptors, so reset IFF_OACTIVE and restart. */ 1740 ifp->if_flags &= ~IFF_OACTIVE; 1741 sc->sc_if_flags = ifp->if_flags; 1742 ifp->if_timer = SIMPLEQ_EMPTY(&sc->sc_txdirtyq) ? 0 : 5; 1743 gem_start(ifp); 1744 } 1745 DPRINTF(sc, ("%s: gem_tint: watchdog %d\n", 1746 device_xname(sc->sc_dev), ifp->if_timer)); 1747 1748 return (1); 1749 } 1750 1751 /* 1752 * Receive interrupt. 1753 */ 1754 int 1755 gem_rint(struct gem_softc *sc) 1756 { 1757 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1758 bus_space_tag_t t = sc->sc_bustag; 1759 bus_space_handle_t h = sc->sc_h1; 1760 struct gem_rxsoft *rxs; 1761 struct mbuf *m; 1762 u_int64_t rxstat; 1763 u_int32_t rxcomp; 1764 int i, len, progress = 0; 1765 1766 DPRINTF(sc, ("%s: gem_rint\n", device_xname(sc->sc_dev))); 1767 1768 /* 1769 * Ignore spurious interrupt that sometimes occurs before 1770 * we are set up when we network boot. 1771 */ 1772 if (!sc->sc_meminited) 1773 return 1; 1774 1775 /* 1776 * Read the completion register once. This limits 1777 * how long the following loop can execute. 1778 */ 1779 rxcomp = bus_space_read_4(t, h, GEM_RX_COMPLETION); 1780 1781 /* 1782 * XXX Read the lastrx only once at the top for speed. 1783 */ 1784 DPRINTF(sc, ("gem_rint: sc->rxptr %d, complete %d\n", 1785 sc->sc_rxptr, rxcomp)); 1786 1787 /* 1788 * Go into the loop at least once. 1789 */ 1790 for (i = sc->sc_rxptr; i == sc->sc_rxptr || i != rxcomp; 1791 i = GEM_NEXTRX(i)) { 1792 rxs = &sc->sc_rxsoft[i]; 1793 1794 GEM_CDRXSYNC(sc, i, 1795 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1796 1797 rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags); 1798 1799 if (rxstat & GEM_RD_OWN) { 1800 GEM_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); 1801 /* 1802 * We have processed all of the receive buffers. 1803 */ 1804 break; 1805 } 1806 1807 progress++; 1808 ifp->if_ipackets++; 1809 1810 if (rxstat & GEM_RD_BAD_CRC) { 1811 ifp->if_ierrors++; 1812 aprint_error_dev(sc->sc_dev, 1813 "receive error: CRC error\n"); 1814 GEM_INIT_RXDESC(sc, i); 1815 continue; 1816 } 1817 1818 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1819 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1820 #ifdef GEM_DEBUG 1821 if (ifp->if_flags & IFF_DEBUG) { 1822 printf(" rxsoft %p descriptor %d: ", rxs, i); 1823 printf("gd_flags: 0x%016llx\t", (long long) 1824 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags)); 1825 printf("gd_addr: 0x%016llx\n", (long long) 1826 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr)); 1827 } 1828 #endif 1829 1830 /* No errors; receive the packet. */ 1831 len = GEM_RD_BUFLEN(rxstat); 1832 1833 /* 1834 * Allocate a new mbuf cluster. If that fails, we are 1835 * out of memory, and must drop the packet and recycle 1836 * the buffer that's already attached to this descriptor. 1837 */ 1838 m = rxs->rxs_mbuf; 1839 if (gem_add_rxbuf(sc, i) != 0) { 1840 GEM_COUNTER_INCR(sc, sc_ev_rxnobuf); 1841 ifp->if_ierrors++; 1842 aprint_error_dev(sc->sc_dev, 1843 "receive error: RX no buffer space\n"); 1844 GEM_INIT_RXDESC(sc, i); 1845 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1846 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1847 continue; 1848 } 1849 m->m_data += 2; /* We're already off by two */ 1850 1851 m->m_pkthdr.rcvif = ifp; 1852 m->m_pkthdr.len = m->m_len = len; 1853 1854 /* 1855 * Pass this up to any BPF listeners, but only 1856 * pass it up the stack if it's for us. 1857 */ 1858 bpf_mtap(ifp, m); 1859 1860 #ifdef INET 1861 /* hardware checksum */ 1862 if (ifp->if_csum_flags_rx & M_CSUM_TCPv4) { 1863 struct ether_header *eh; 1864 struct ip *ip; 1865 int32_t hlen, pktlen; 1866 1867 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1868 pktlen = m->m_pkthdr.len - ETHER_HDR_LEN - 1869 ETHER_VLAN_ENCAP_LEN; 1870 eh = (struct ether_header *) (mtod(m, char *) + 1871 ETHER_VLAN_ENCAP_LEN); 1872 } else { 1873 pktlen = m->m_pkthdr.len - ETHER_HDR_LEN; 1874 eh = mtod(m, struct ether_header *); 1875 } 1876 if (ntohs(eh->ether_type) != ETHERTYPE_IP) 1877 goto swcsum; 1878 ip = (struct ip *) ((char *)eh + ETHER_HDR_LEN); 1879 1880 /* IPv4 only */ 1881 if (ip->ip_v != IPVERSION) 1882 goto swcsum; 1883 1884 hlen = ip->ip_hl << 2; 1885 if (hlen < sizeof(struct ip)) 1886 goto swcsum; 1887 1888 /* 1889 * bail if too short, has random trailing garbage, 1890 * truncated, fragment, or has ethernet pad. 1891 */ 1892 if ((ntohs(ip->ip_len) < hlen) || 1893 (ntohs(ip->ip_len) != pktlen) || 1894 (ntohs(ip->ip_off) & (IP_MF | IP_OFFMASK))) 1895 goto swcsum; 1896 1897 switch (ip->ip_p) { 1898 case IPPROTO_TCP: 1899 if (! (ifp->if_csum_flags_rx & M_CSUM_TCPv4)) 1900 goto swcsum; 1901 if (pktlen < (hlen + sizeof(struct tcphdr))) 1902 goto swcsum; 1903 m->m_pkthdr.csum_flags = M_CSUM_TCPv4; 1904 break; 1905 case IPPROTO_UDP: 1906 /* FALLTHROUGH */ 1907 default: 1908 goto swcsum; 1909 } 1910 1911 /* the uncomplemented sum is expected */ 1912 m->m_pkthdr.csum_data = (~rxstat) & GEM_RD_CHECKSUM; 1913 1914 /* if the pkt had ip options, we have to deduct them */ 1915 if (hlen > sizeof(struct ip)) { 1916 uint16_t *opts; 1917 uint32_t optsum, temp; 1918 1919 optsum = 0; 1920 temp = hlen - sizeof(struct ip); 1921 opts = (uint16_t *) ((char *) ip + 1922 sizeof(struct ip)); 1923 1924 while (temp > 1) { 1925 optsum += ntohs(*opts++); 1926 temp -= 2; 1927 } 1928 while (optsum >> 16) 1929 optsum = (optsum >> 16) + 1930 (optsum & 0xffff); 1931 1932 /* Deduct ip opts sum from hwsum. */ 1933 m->m_pkthdr.csum_data += (uint16_t)~optsum; 1934 1935 while (m->m_pkthdr.csum_data >> 16) 1936 m->m_pkthdr.csum_data = 1937 (m->m_pkthdr.csum_data >> 16) + 1938 (m->m_pkthdr.csum_data & 1939 0xffff); 1940 } 1941 1942 m->m_pkthdr.csum_flags |= M_CSUM_DATA | 1943 M_CSUM_NO_PSEUDOHDR; 1944 } else 1945 swcsum: 1946 m->m_pkthdr.csum_flags = 0; 1947 #endif 1948 /* Pass it on. */ 1949 if_percpuq_enqueue(ifp->if_percpuq, m); 1950 } 1951 1952 if (progress) { 1953 /* Update the receive pointer. */ 1954 if (i == sc->sc_rxptr) { 1955 GEM_COUNTER_INCR(sc, sc_ev_rxfull); 1956 #ifdef GEM_DEBUG 1957 if (ifp->if_flags & IFF_DEBUG) 1958 printf("%s: rint: ring wrap\n", 1959 device_xname(sc->sc_dev)); 1960 #endif 1961 } 1962 sc->sc_rxptr = i; 1963 bus_space_write_4(t, h, GEM_RX_KICK, GEM_PREVRX(i)); 1964 } 1965 #ifdef GEM_COUNTERS 1966 if (progress <= 4) { 1967 GEM_COUNTER_INCR(sc, sc_ev_rxhist[progress]); 1968 } else if (progress < 32) { 1969 if (progress < 16) 1970 GEM_COUNTER_INCR(sc, sc_ev_rxhist[5]); 1971 else 1972 GEM_COUNTER_INCR(sc, sc_ev_rxhist[6]); 1973 1974 } else { 1975 if (progress < 64) 1976 GEM_COUNTER_INCR(sc, sc_ev_rxhist[7]); 1977 else 1978 GEM_COUNTER_INCR(sc, sc_ev_rxhist[8]); 1979 } 1980 #endif 1981 1982 DPRINTF(sc, ("gem_rint: done sc->rxptr %d, complete %d\n", 1983 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION))); 1984 1985 /* Read error counters ... */ 1986 ifp->if_ierrors += 1987 bus_space_read_4(t, h, GEM_MAC_RX_LEN_ERR_CNT) + 1988 bus_space_read_4(t, h, GEM_MAC_RX_ALIGN_ERR) + 1989 bus_space_read_4(t, h, GEM_MAC_RX_CRC_ERR_CNT) + 1990 bus_space_read_4(t, h, GEM_MAC_RX_CODE_VIOL); 1991 1992 /* ... then clear the hardware counters. */ 1993 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 1994 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 1995 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 1996 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 1997 1998 return (1); 1999 } 2000 2001 2002 /* 2003 * gem_add_rxbuf: 2004 * 2005 * Add a receive buffer to the indicated descriptor. 2006 */ 2007 int 2008 gem_add_rxbuf(struct gem_softc *sc, int idx) 2009 { 2010 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2011 struct mbuf *m; 2012 int error; 2013 2014 MGETHDR(m, M_DONTWAIT, MT_DATA); 2015 if (m == NULL) 2016 return (ENOBUFS); 2017 2018 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2019 MCLGET(m, M_DONTWAIT); 2020 if ((m->m_flags & M_EXT) == 0) { 2021 m_freem(m); 2022 return (ENOBUFS); 2023 } 2024 2025 #ifdef GEM_DEBUG 2026 /* bzero the packet to check DMA */ 2027 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 2028 #endif 2029 2030 if (rxs->rxs_mbuf != NULL) 2031 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 2032 2033 rxs->rxs_mbuf = m; 2034 2035 error = bus_dmamap_load(sc->sc_dmatag, rxs->rxs_dmamap, 2036 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2037 BUS_DMA_READ|BUS_DMA_NOWAIT); 2038 if (error) { 2039 aprint_error_dev(sc->sc_dev, 2040 "can't load rx DMA map %d, error = %d\n", idx, error); 2041 panic("gem_add_rxbuf"); /* XXX */ 2042 } 2043 2044 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 2045 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2046 2047 GEM_INIT_RXDESC(sc, idx); 2048 2049 return (0); 2050 } 2051 2052 2053 int 2054 gem_eint(struct gem_softc *sc, u_int status) 2055 { 2056 char bits[128]; 2057 u_int32_t r, v; 2058 2059 if ((status & GEM_INTR_MIF) != 0) { 2060 printf("%s: XXXlink status changed\n", device_xname(sc->sc_dev)); 2061 return (1); 2062 } 2063 2064 if ((status & GEM_INTR_RX_TAG_ERR) != 0) { 2065 gem_reset_rxdma(sc); 2066 return (1); 2067 } 2068 2069 if (status & GEM_INTR_BERR) { 2070 if (sc->sc_flags & GEM_PCI) 2071 r = GEM_ERROR_STATUS; 2072 else 2073 r = GEM_SBUS_ERROR_STATUS; 2074 bus_space_read_4(sc->sc_bustag, sc->sc_h2, r); 2075 v = bus_space_read_4(sc->sc_bustag, sc->sc_h2, r); 2076 aprint_error_dev(sc->sc_dev, "bus error interrupt: 0x%02x\n", 2077 v); 2078 return (1); 2079 } 2080 snprintb(bits, sizeof(bits), GEM_INTR_BITS, status); 2081 printf("%s: status=%s\n", device_xname(sc->sc_dev), bits); 2082 2083 return (1); 2084 } 2085 2086 2087 /* 2088 * PCS interrupts. 2089 * We should receive these when the link status changes, but sometimes 2090 * we don't receive them for link up. We compensate for this in the 2091 * gem_tick() callout. 2092 */ 2093 int 2094 gem_pint(struct gem_softc *sc) 2095 { 2096 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2097 bus_space_tag_t t = sc->sc_bustag; 2098 bus_space_handle_t h = sc->sc_h1; 2099 u_int32_t v, v2; 2100 2101 /* 2102 * Clear the PCS interrupt from GEM_STATUS. The PCS register is 2103 * latched, so we have to read it twice. There is only one bit in 2104 * use, so the value is meaningless. 2105 */ 2106 bus_space_read_4(t, h, GEM_MII_INTERRUP_STATUS); 2107 bus_space_read_4(t, h, GEM_MII_INTERRUP_STATUS); 2108 2109 if ((ifp->if_flags & IFF_UP) == 0) 2110 return 1; 2111 2112 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) 2113 return 1; 2114 2115 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2116 /* If we see remote fault, our link partner is probably going away */ 2117 if ((v & GEM_MII_STATUS_REM_FLT) != 0) { 2118 gem_bitwait(sc, h, GEM_MII_STATUS, GEM_MII_STATUS_REM_FLT, 0); 2119 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2120 /* Otherwise, we may need to wait after auto-negotiation completes */ 2121 } else if ((v & (GEM_MII_STATUS_LINK_STS | GEM_MII_STATUS_ANEG_CPT)) == 2122 GEM_MII_STATUS_ANEG_CPT) { 2123 gem_bitwait(sc, h, GEM_MII_STATUS, 0, GEM_MII_STATUS_LINK_STS); 2124 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2125 } 2126 if ((v & GEM_MII_STATUS_LINK_STS) != 0) { 2127 if (sc->sc_flags & GEM_LINK) { 2128 return 1; 2129 } 2130 callout_stop(&sc->sc_tick_ch); 2131 v = bus_space_read_4(t, h, GEM_MII_ANAR); 2132 v2 = bus_space_read_4(t, h, GEM_MII_ANLPAR); 2133 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_1000_SX; 2134 sc->sc_mii.mii_media_status = IFM_AVALID | IFM_ACTIVE; 2135 v &= v2; 2136 if (v & GEM_MII_ANEG_FUL_DUPLX) { 2137 sc->sc_mii.mii_media_active |= IFM_FDX; 2138 #ifdef GEM_DEBUG 2139 aprint_debug_dev(sc->sc_dev, "link up: full duplex\n"); 2140 #endif 2141 } else if (v & GEM_MII_ANEG_HLF_DUPLX) { 2142 sc->sc_mii.mii_media_active |= IFM_HDX; 2143 #ifdef GEM_DEBUG 2144 aprint_debug_dev(sc->sc_dev, "link up: half duplex\n"); 2145 #endif 2146 } else { 2147 #ifdef GEM_DEBUG 2148 aprint_debug_dev(sc->sc_dev, "duplex mismatch\n"); 2149 #endif 2150 } 2151 gem_statuschange(sc); 2152 } else { 2153 if ((sc->sc_flags & GEM_LINK) == 0) { 2154 return 1; 2155 } 2156 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_NONE; 2157 sc->sc_mii.mii_media_status = IFM_AVALID; 2158 #ifdef GEM_DEBUG 2159 aprint_debug_dev(sc->sc_dev, "link down\n"); 2160 #endif 2161 gem_statuschange(sc); 2162 2163 /* Start the 10 second timer */ 2164 callout_reset(&sc->sc_tick_ch, hz * 10, gem_tick, sc); 2165 } 2166 return 1; 2167 } 2168 2169 2170 2171 int 2172 gem_intr(void *v) 2173 { 2174 struct gem_softc *sc = v; 2175 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2176 bus_space_tag_t t = sc->sc_bustag; 2177 bus_space_handle_t h = sc->sc_h1; 2178 u_int32_t status; 2179 int r = 0; 2180 #ifdef GEM_DEBUG 2181 char bits[128]; 2182 #endif 2183 2184 /* XXX We should probably mask out interrupts until we're done */ 2185 2186 sc->sc_ev_intr.ev_count++; 2187 2188 status = bus_space_read_4(t, h, GEM_STATUS); 2189 #ifdef GEM_DEBUG 2190 snprintb(bits, sizeof(bits), GEM_INTR_BITS, status); 2191 #endif 2192 DPRINTF(sc, ("%s: gem_intr: cplt 0x%x status %s\n", 2193 device_xname(sc->sc_dev), (status >> 19), bits)); 2194 2195 2196 if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0) 2197 r |= gem_eint(sc, status); 2198 2199 /* We don't bother with GEM_INTR_TX_DONE */ 2200 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) { 2201 GEM_COUNTER_INCR(sc, sc_ev_txint); 2202 r |= gem_tint(sc); 2203 } 2204 2205 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) { 2206 GEM_COUNTER_INCR(sc, sc_ev_rxint); 2207 r |= gem_rint(sc); 2208 } 2209 2210 /* We should eventually do more than just print out error stats. */ 2211 if (status & GEM_INTR_TX_MAC) { 2212 int txstat = bus_space_read_4(t, h, GEM_MAC_TX_STATUS); 2213 if (txstat & ~GEM_MAC_TX_XMIT_DONE) 2214 printf("%s: MAC tx fault, status %x\n", 2215 device_xname(sc->sc_dev), txstat); 2216 if (txstat & (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG)) 2217 gem_init(ifp); 2218 } 2219 if (status & GEM_INTR_RX_MAC) { 2220 int rxstat = bus_space_read_4(t, h, GEM_MAC_RX_STATUS); 2221 /* 2222 * At least with GEM_SUN_GEM and some GEM_SUN_ERI 2223 * revisions GEM_MAC_RX_OVERFLOW happen often due to a 2224 * silicon bug so handle them silently. So if we detect 2225 * an RX FIFO overflow, we fire off a timer, and check 2226 * whether we're still making progress by looking at the 2227 * RX FIFO write and read pointers. 2228 */ 2229 if (rxstat & GEM_MAC_RX_OVERFLOW) { 2230 ifp->if_ierrors++; 2231 aprint_error_dev(sc->sc_dev, 2232 "receive error: RX overflow sc->rxptr %d, complete %d\n", sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION)); 2233 sc->sc_rx_fifo_wr_ptr = 2234 bus_space_read_4(t, h, GEM_RX_FIFO_WR_PTR); 2235 sc->sc_rx_fifo_rd_ptr = 2236 bus_space_read_4(t, h, GEM_RX_FIFO_RD_PTR); 2237 callout_schedule(&sc->sc_rx_watchdog, 400); 2238 } else if (rxstat & ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT)) 2239 printf("%s: MAC rx fault, status 0x%02x\n", 2240 device_xname(sc->sc_dev), rxstat); 2241 } 2242 if (status & GEM_INTR_PCS) { 2243 r |= gem_pint(sc); 2244 } 2245 2246 /* Do we need to do anything with these? 2247 if ((status & GEM_MAC_CONTROL_STATUS) != 0) { 2248 status2 = bus_read_4(sc->sc_res[0], GEM_MAC_CONTROL_STATUS); 2249 if ((status2 & GEM_MAC_PAUSED) != 0) 2250 aprintf_debug_dev(sc->sc_dev, "PAUSE received (%d slots)\n", 2251 GEM_MAC_PAUSE_TIME(status2)); 2252 if ((status2 & GEM_MAC_PAUSE) != 0) 2253 aprintf_debug_dev(sc->sc_dev, "transited to PAUSE state\n"); 2254 if ((status2 & GEM_MAC_RESUME) != 0) 2255 aprintf_debug_dev(sc->sc_dev, "transited to non-PAUSE state\n"); 2256 } 2257 if ((status & GEM_INTR_MIF) != 0) 2258 aprintf_debug_dev(sc->sc_dev, "MIF interrupt\n"); 2259 */ 2260 rnd_add_uint32(&sc->rnd_source, status); 2261 return (r); 2262 } 2263 2264 void 2265 gem_rx_watchdog(void *arg) 2266 { 2267 struct gem_softc *sc = arg; 2268 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2269 bus_space_tag_t t = sc->sc_bustag; 2270 bus_space_handle_t h = sc->sc_h1; 2271 u_int32_t rx_fifo_wr_ptr; 2272 u_int32_t rx_fifo_rd_ptr; 2273 u_int32_t state; 2274 2275 if ((ifp->if_flags & IFF_RUNNING) == 0) { 2276 aprint_error_dev(sc->sc_dev, "receiver not running\n"); 2277 return; 2278 } 2279 2280 rx_fifo_wr_ptr = bus_space_read_4(t, h, GEM_RX_FIFO_WR_PTR); 2281 rx_fifo_rd_ptr = bus_space_read_4(t, h, GEM_RX_FIFO_RD_PTR); 2282 state = bus_space_read_4(t, h, GEM_MAC_MAC_STATE); 2283 if ((state & GEM_MAC_STATE_OVERFLOW) == GEM_MAC_STATE_OVERFLOW && 2284 ((rx_fifo_wr_ptr == rx_fifo_rd_ptr) || 2285 ((sc->sc_rx_fifo_wr_ptr == rx_fifo_wr_ptr) && 2286 (sc->sc_rx_fifo_rd_ptr == rx_fifo_rd_ptr)))) 2287 { 2288 /* 2289 * The RX state machine is still in overflow state and 2290 * the RX FIFO write and read pointers seem to be 2291 * stuck. Whack the chip over the head to get things 2292 * going again. 2293 */ 2294 aprint_error_dev(sc->sc_dev, 2295 "receiver stuck in overflow, resetting\n"); 2296 gem_init(ifp); 2297 } else { 2298 if ((state & GEM_MAC_STATE_OVERFLOW) != GEM_MAC_STATE_OVERFLOW) { 2299 aprint_error_dev(sc->sc_dev, 2300 "rx_watchdog: not in overflow state: 0x%x\n", 2301 state); 2302 } 2303 if (rx_fifo_wr_ptr != rx_fifo_rd_ptr) { 2304 aprint_error_dev(sc->sc_dev, 2305 "rx_watchdog: wr & rd ptr different\n"); 2306 } 2307 if (sc->sc_rx_fifo_wr_ptr != rx_fifo_wr_ptr) { 2308 aprint_error_dev(sc->sc_dev, 2309 "rx_watchdog: wr pointer != saved\n"); 2310 } 2311 if (sc->sc_rx_fifo_rd_ptr != rx_fifo_rd_ptr) { 2312 aprint_error_dev(sc->sc_dev, 2313 "rx_watchdog: rd pointer != saved\n"); 2314 } 2315 aprint_error_dev(sc->sc_dev, "resetting anyway\n"); 2316 gem_init(ifp); 2317 } 2318 } 2319 2320 void 2321 gem_watchdog(struct ifnet *ifp) 2322 { 2323 struct gem_softc *sc = ifp->if_softc; 2324 2325 DPRINTF(sc, ("gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x " 2326 "GEM_MAC_RX_CONFIG %x\n", 2327 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_RX_CONFIG), 2328 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_MAC_RX_STATUS), 2329 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_MAC_RX_CONFIG))); 2330 2331 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 2332 ++ifp->if_oerrors; 2333 2334 /* Try to get more packets going. */ 2335 gem_init(ifp); 2336 gem_start(ifp); 2337 } 2338 2339 /* 2340 * Initialize the MII Management Interface 2341 */ 2342 void 2343 gem_mifinit(struct gem_softc *sc) 2344 { 2345 bus_space_tag_t t = sc->sc_bustag; 2346 bus_space_handle_t mif = sc->sc_h1; 2347 2348 /* Configure the MIF in frame mode */ 2349 sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 2350 sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA; 2351 bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config); 2352 } 2353 2354 /* 2355 * MII interface 2356 * 2357 * The GEM MII interface supports at least three different operating modes: 2358 * 2359 * Bitbang mode is implemented using data, clock and output enable registers. 2360 * 2361 * Frame mode is implemented by loading a complete frame into the frame 2362 * register and polling the valid bit for completion. 2363 * 2364 * Polling mode uses the frame register but completion is indicated by 2365 * an interrupt. 2366 * 2367 */ 2368 static int 2369 gem_mii_readreg(device_t self, int phy, int reg) 2370 { 2371 struct gem_softc *sc = device_private(self); 2372 bus_space_tag_t t = sc->sc_bustag; 2373 bus_space_handle_t mif = sc->sc_h1; 2374 int n; 2375 u_int32_t v; 2376 2377 #ifdef GEM_DEBUG1 2378 if (sc->sc_debug) 2379 printf("gem_mii_readreg: PHY %d reg %d\n", phy, reg); 2380 #endif 2381 2382 /* Construct the frame command */ 2383 v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) | 2384 GEM_MIF_FRAME_READ; 2385 2386 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 2387 for (n = 0; n < 100; n++) { 2388 DELAY(1); 2389 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 2390 if (v & GEM_MIF_FRAME_TA0) 2391 return (v & GEM_MIF_FRAME_DATA); 2392 } 2393 2394 printf("%s: mii_read timeout\n", device_xname(sc->sc_dev)); 2395 return (0); 2396 } 2397 2398 static void 2399 gem_mii_writereg(device_t self, int phy, int reg, int val) 2400 { 2401 struct gem_softc *sc = device_private(self); 2402 bus_space_tag_t t = sc->sc_bustag; 2403 bus_space_handle_t mif = sc->sc_h1; 2404 int n; 2405 u_int32_t v; 2406 2407 #ifdef GEM_DEBUG1 2408 if (sc->sc_debug) 2409 printf("gem_mii_writereg: PHY %d reg %d val %x\n", 2410 phy, reg, val); 2411 #endif 2412 2413 /* Construct the frame command */ 2414 v = GEM_MIF_FRAME_WRITE | 2415 (phy << GEM_MIF_PHY_SHIFT) | 2416 (reg << GEM_MIF_REG_SHIFT) | 2417 (val & GEM_MIF_FRAME_DATA); 2418 2419 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 2420 for (n = 0; n < 100; n++) { 2421 DELAY(1); 2422 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 2423 if (v & GEM_MIF_FRAME_TA0) 2424 return; 2425 } 2426 2427 printf("%s: mii_write timeout\n", device_xname(sc->sc_dev)); 2428 } 2429 2430 static void 2431 gem_mii_statchg(struct ifnet *ifp) 2432 { 2433 struct gem_softc *sc = ifp->if_softc; 2434 #ifdef GEM_DEBUG 2435 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 2436 #endif 2437 2438 #ifdef GEM_DEBUG 2439 if (sc->sc_debug) 2440 printf("gem_mii_statchg: status change: phy = %d\n", 2441 sc->sc_phys[instance]); 2442 #endif 2443 gem_statuschange(sc); 2444 } 2445 2446 /* 2447 * Common status change for gem_mii_statchg() and gem_pint() 2448 */ 2449 void 2450 gem_statuschange(struct gem_softc* sc) 2451 { 2452 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2453 bus_space_tag_t t = sc->sc_bustag; 2454 bus_space_handle_t mac = sc->sc_h1; 2455 int gigabit; 2456 u_int32_t rxcfg, txcfg, v; 2457 2458 if ((sc->sc_mii.mii_media_status & IFM_ACTIVE) != 0 && 2459 IFM_SUBTYPE(sc->sc_mii.mii_media_active) != IFM_NONE) 2460 sc->sc_flags |= GEM_LINK; 2461 else 2462 sc->sc_flags &= ~GEM_LINK; 2463 2464 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 2465 gigabit = 1; 2466 else 2467 gigabit = 0; 2468 2469 /* 2470 * The configuration done here corresponds to the steps F) and 2471 * G) and as far as enabling of RX and TX MAC goes also step H) 2472 * of the initialization sequence outlined in section 3.2.1 of 2473 * the GEM Gigabit Ethernet ASIC Specification. 2474 */ 2475 2476 rxcfg = bus_space_read_4(t, mac, GEM_MAC_RX_CONFIG); 2477 rxcfg &= ~(GEM_MAC_RX_CARR_EXTEND | GEM_MAC_RX_ENABLE); 2478 txcfg = GEM_MAC_TX_ENA_IPG0 | GEM_MAC_TX_NGU | GEM_MAC_TX_NGU_LIMIT; 2479 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 2480 txcfg |= GEM_MAC_TX_IGN_CARRIER | GEM_MAC_TX_IGN_COLLIS; 2481 else if (gigabit) { 2482 rxcfg |= GEM_MAC_RX_CARR_EXTEND; 2483 txcfg |= GEM_MAC_RX_CARR_EXTEND; 2484 } 2485 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0); 2486 bus_space_barrier(t, mac, GEM_MAC_TX_CONFIG, 4, 2487 BUS_SPACE_BARRIER_WRITE); 2488 if (!gem_bitwait(sc, mac, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)) 2489 aprint_normal_dev(sc->sc_dev, "cannot disable TX MAC\n"); 2490 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, txcfg); 2491 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, 0); 2492 bus_space_barrier(t, mac, GEM_MAC_RX_CONFIG, 4, 2493 BUS_SPACE_BARRIER_WRITE); 2494 if (!gem_bitwait(sc, mac, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)) 2495 aprint_normal_dev(sc->sc_dev, "cannot disable RX MAC\n"); 2496 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, rxcfg); 2497 2498 v = bus_space_read_4(t, mac, GEM_MAC_CONTROL_CONFIG) & 2499 ~(GEM_MAC_CC_RX_PAUSE | GEM_MAC_CC_TX_PAUSE); 2500 bus_space_write_4(t, mac, GEM_MAC_CONTROL_CONFIG, v); 2501 2502 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) == 0 && 2503 gigabit != 0) 2504 bus_space_write_4(t, mac, GEM_MAC_SLOT_TIME, 2505 GEM_MAC_SLOT_TIME_CARR_EXTEND); 2506 else 2507 bus_space_write_4(t, mac, GEM_MAC_SLOT_TIME, 2508 GEM_MAC_SLOT_TIME_NORMAL); 2509 2510 /* XIF Configuration */ 2511 if (sc->sc_flags & GEM_LINK) 2512 v = GEM_MAC_XIF_LINK_LED; 2513 else 2514 v = 0; 2515 v |= GEM_MAC_XIF_TX_MII_ENA; 2516 2517 /* If an external transceiver is connected, enable its MII drivers */ 2518 sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG); 2519 if ((sc->sc_flags &(GEM_SERDES | GEM_SERIAL)) == 0) { 2520 if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) { 2521 if (gigabit) 2522 v |= GEM_MAC_XIF_GMII_MODE; 2523 else 2524 v &= ~GEM_MAC_XIF_GMII_MODE; 2525 } else 2526 /* Internal MII needs buf enable */ 2527 v |= GEM_MAC_XIF_MII_BUF_ENA; 2528 /* MII needs echo disable if half duplex. */ 2529 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 2530 /* turn on full duplex LED */ 2531 v |= GEM_MAC_XIF_FDPLX_LED; 2532 else 2533 /* half duplex -- disable echo */ 2534 v |= GEM_MAC_XIF_ECHO_DISABL; 2535 } else { 2536 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 2537 v |= GEM_MAC_XIF_FDPLX_LED; 2538 v |= GEM_MAC_XIF_GMII_MODE; 2539 } 2540 bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v); 2541 2542 if ((ifp->if_flags & IFF_RUNNING) != 0 && 2543 (sc->sc_flags & GEM_LINK) != 0) { 2544 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 2545 txcfg | GEM_MAC_TX_ENABLE); 2546 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, 2547 rxcfg | GEM_MAC_RX_ENABLE); 2548 } 2549 } 2550 2551 int 2552 gem_ser_mediachange(struct ifnet *ifp) 2553 { 2554 struct gem_softc *sc = ifp->if_softc; 2555 u_int s, t; 2556 2557 if (IFM_TYPE(sc->sc_mii.mii_media.ifm_media) != IFM_ETHER) 2558 return EINVAL; 2559 2560 s = IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media); 2561 if (s == IFM_AUTO) { 2562 if (sc->sc_mii_media != s) { 2563 #ifdef GEM_DEBUG 2564 aprint_debug_dev(sc->sc_dev, "setting media to auto\n"); 2565 #endif 2566 sc->sc_mii_media = s; 2567 if (ifp->if_flags & IFF_UP) { 2568 gem_pcs_stop(sc, 0); 2569 gem_pcs_start(sc); 2570 } 2571 } 2572 return 0; 2573 } 2574 if (s == IFM_1000_SX) { 2575 t = IFM_OPTIONS(sc->sc_mii.mii_media.ifm_media); 2576 if (t == IFM_FDX || t == IFM_HDX) { 2577 if (sc->sc_mii_media != t) { 2578 sc->sc_mii_media = t; 2579 #ifdef GEM_DEBUG 2580 aprint_debug_dev(sc->sc_dev, 2581 "setting media to 1000baseSX-%s\n", 2582 t == IFM_FDX ? "FDX" : "HDX"); 2583 #endif 2584 if (ifp->if_flags & IFF_UP) { 2585 gem_pcs_stop(sc, 0); 2586 gem_pcs_start(sc); 2587 } 2588 } 2589 return 0; 2590 } 2591 } 2592 return EINVAL; 2593 } 2594 2595 void 2596 gem_ser_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2597 { 2598 struct gem_softc *sc = ifp->if_softc; 2599 2600 if ((ifp->if_flags & IFF_UP) == 0) 2601 return; 2602 ifmr->ifm_active = sc->sc_mii.mii_media_active; 2603 ifmr->ifm_status = sc->sc_mii.mii_media_status; 2604 } 2605 2606 static int 2607 gem_ifflags_cb(struct ethercom *ec) 2608 { 2609 struct ifnet *ifp = &ec->ec_if; 2610 struct gem_softc *sc = ifp->if_softc; 2611 int change = ifp->if_flags ^ sc->sc_if_flags; 2612 2613 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 2614 return ENETRESET; 2615 else if ((change & IFF_PROMISC) != 0) 2616 gem_setladrf(sc); 2617 return 0; 2618 } 2619 2620 /* 2621 * Process an ioctl request. 2622 */ 2623 int 2624 gem_ioctl(struct ifnet *ifp, unsigned long cmd, void *data) 2625 { 2626 struct gem_softc *sc = ifp->if_softc; 2627 int s, error = 0; 2628 2629 s = splnet(); 2630 2631 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2632 error = 0; 2633 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 2634 ; 2635 else if (ifp->if_flags & IFF_RUNNING) { 2636 /* 2637 * Multicast list has changed; set the hardware filter 2638 * accordingly. 2639 */ 2640 gem_setladrf(sc); 2641 } 2642 } 2643 2644 /* Try to get things going again */ 2645 if (ifp->if_flags & IFF_UP) 2646 gem_start(ifp); 2647 splx(s); 2648 return (error); 2649 } 2650 2651 static void 2652 gem_inten(struct gem_softc *sc) 2653 { 2654 bus_space_tag_t t = sc->sc_bustag; 2655 bus_space_handle_t h = sc->sc_h1; 2656 uint32_t v; 2657 2658 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 2659 v = GEM_INTR_PCS; 2660 else 2661 v = GEM_INTR_MIF; 2662 bus_space_write_4(t, h, GEM_INTMASK, 2663 ~(GEM_INTR_TX_INTME | 2664 GEM_INTR_TX_EMPTY | 2665 GEM_INTR_TX_MAC | 2666 GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF| 2667 GEM_INTR_RX_TAG_ERR | GEM_INTR_MAC_CONTROL| 2668 GEM_INTR_BERR | v)); 2669 } 2670 2671 bool 2672 gem_resume(device_t self, const pmf_qual_t *qual) 2673 { 2674 struct gem_softc *sc = device_private(self); 2675 2676 gem_inten(sc); 2677 2678 return true; 2679 } 2680 2681 bool 2682 gem_suspend(device_t self, const pmf_qual_t *qual) 2683 { 2684 struct gem_softc *sc = device_private(self); 2685 bus_space_tag_t t = sc->sc_bustag; 2686 bus_space_handle_t h = sc->sc_h1; 2687 2688 bus_space_write_4(t, h, GEM_INTMASK, ~(uint32_t)0); 2689 2690 return true; 2691 } 2692 2693 bool 2694 gem_shutdown(device_t self, int howto) 2695 { 2696 struct gem_softc *sc = device_private(self); 2697 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2698 2699 gem_stop(ifp, 1); 2700 2701 return true; 2702 } 2703 2704 /* 2705 * Set up the logical address filter. 2706 */ 2707 void 2708 gem_setladrf(struct gem_softc *sc) 2709 { 2710 struct ethercom *ec = &sc->sc_ethercom; 2711 struct ifnet *ifp = &ec->ec_if; 2712 struct ether_multi *enm; 2713 struct ether_multistep step; 2714 bus_space_tag_t t = sc->sc_bustag; 2715 bus_space_handle_t h = sc->sc_h1; 2716 u_int32_t crc; 2717 u_int32_t hash[16]; 2718 u_int32_t v; 2719 int i; 2720 2721 /* Get current RX configuration */ 2722 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 2723 2724 /* 2725 * Turn off promiscuous mode, promiscuous group mode (all multicast), 2726 * and hash filter. Depending on the case, the right bit will be 2727 * enabled. 2728 */ 2729 v &= ~(GEM_MAC_RX_PROMISCUOUS|GEM_MAC_RX_HASH_FILTER| 2730 GEM_MAC_RX_PROMISC_GRP); 2731 2732 if ((ifp->if_flags & IFF_PROMISC) != 0) { 2733 /* Turn on promiscuous mode */ 2734 v |= GEM_MAC_RX_PROMISCUOUS; 2735 ifp->if_flags |= IFF_ALLMULTI; 2736 goto chipit; 2737 } 2738 2739 /* 2740 * Set up multicast address filter by passing all multicast addresses 2741 * through a crc generator, and then using the high order 8 bits as an 2742 * index into the 256 bit logical address filter. The high order 4 2743 * bits selects the word, while the other 4 bits select the bit within 2744 * the word (where bit 0 is the MSB). 2745 */ 2746 2747 /* Clear hash table */ 2748 memset(hash, 0, sizeof(hash)); 2749 2750 ETHER_FIRST_MULTI(step, ec, enm); 2751 while (enm != NULL) { 2752 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2753 /* 2754 * We must listen to a range of multicast addresses. 2755 * For now, just accept all multicasts, rather than 2756 * trying to set only those filter bits needed to match 2757 * the range. (At this time, the only use of address 2758 * ranges is for IP multicast routing, for which the 2759 * range is big enough to require all bits set.) 2760 * XXX should use the address filters for this 2761 */ 2762 ifp->if_flags |= IFF_ALLMULTI; 2763 v |= GEM_MAC_RX_PROMISC_GRP; 2764 goto chipit; 2765 } 2766 2767 /* Get the LE CRC32 of the address */ 2768 crc = ether_crc32_le(enm->enm_addrlo, sizeof(enm->enm_addrlo)); 2769 2770 /* Just want the 8 most significant bits. */ 2771 crc >>= 24; 2772 2773 /* Set the corresponding bit in the filter. */ 2774 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 2775 2776 ETHER_NEXT_MULTI(step, enm); 2777 } 2778 2779 v |= GEM_MAC_RX_HASH_FILTER; 2780 ifp->if_flags &= ~IFF_ALLMULTI; 2781 2782 /* Now load the hash table into the chip (if we are using it) */ 2783 for (i = 0; i < 16; i++) { 2784 bus_space_write_4(t, h, 2785 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1-GEM_MAC_HASH0), 2786 hash[i]); 2787 } 2788 2789 chipit: 2790 sc->sc_if_flags = ifp->if_flags; 2791 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 2792 } 2793
Indexes created Mon Sep 22 21:09:42 GMT 2025