gem.c revision 1.11
1 /* $NetBSD: gem.c,v 1.11 2001/11/17 00:56:04 thorpej Exp $ */ 2 3 /* 4 * 5 * Copyright (C) 2001 Eduardo Horvath. 6 * All rights reserved. 7 * 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 */ 31 32 /* 33 * Driver for Sun GEM ethernet controllers. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: gem.c,v 1.11 2001/11/17 00:56:04 thorpej Exp $"); 38 39 #include "bpfilter.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/callout.h> 44 #include <sys/mbuf.h> 45 #include <sys/syslog.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #include <sys/socket.h> 49 #include <sys/ioctl.h> 50 #include <sys/errno.h> 51 #include <sys/device.h> 52 53 #include <machine/endian.h> 54 55 #include <uvm/uvm_extern.h> 56 57 #include <net/if.h> 58 #include <net/if_dl.h> 59 #include <net/if_media.h> 60 #include <net/if_ether.h> 61 62 #if NBPFILTER > 0 63 #include <net/bpf.h> 64 #endif 65 66 #include <machine/bus.h> 67 #include <machine/intr.h> 68 69 #include <dev/mii/mii.h> 70 #include <dev/mii/miivar.h> 71 #include <dev/mii/mii_bitbang.h> 72 73 #include <dev/ic/gemreg.h> 74 #include <dev/ic/gemvar.h> 75 76 #define TRIES 10000 77 78 void gem_start __P((struct ifnet *)); 79 void gem_stop __P((struct ifnet *, int)); 80 int gem_ioctl __P((struct ifnet *, u_long, caddr_t)); 81 void gem_tick __P((void *)); 82 void gem_watchdog __P((struct ifnet *)); 83 void gem_shutdown __P((void *)); 84 int gem_init __P((struct ifnet *)); 85 void gem_init_regs(struct gem_softc *sc); 86 static int gem_ringsize(int sz); 87 int gem_meminit __P((struct gem_softc *)); 88 void gem_mifinit __P((struct gem_softc *)); 89 void gem_reset __P((struct gem_softc *)); 90 int gem_reset_rx(struct gem_softc *sc); 91 int gem_reset_tx(struct gem_softc *sc); 92 int gem_disable_rx(struct gem_softc *sc); 93 int gem_disable_tx(struct gem_softc *sc); 94 void gem_rxdrain(struct gem_softc *sc); 95 int gem_add_rxbuf(struct gem_softc *sc, int idx); 96 void gem_setladrf __P((struct gem_softc *)); 97 98 /* MII methods & callbacks */ 99 static int gem_mii_readreg __P((struct device *, int, int)); 100 static void gem_mii_writereg __P((struct device *, int, int, int)); 101 static void gem_mii_statchg __P((struct device *)); 102 103 int gem_mediachange __P((struct ifnet *)); 104 void gem_mediastatus __P((struct ifnet *, struct ifmediareq *)); 105 106 struct mbuf *gem_get __P((struct gem_softc *, int, int)); 107 int gem_put __P((struct gem_softc *, int, struct mbuf *)); 108 void gem_read __P((struct gem_softc *, int, int)); 109 int gem_eint __P((struct gem_softc *, u_int)); 110 int gem_rint __P((struct gem_softc *)); 111 int gem_tint __P((struct gem_softc *)); 112 void gem_power __P((int, void *)); 113 114 #ifdef GEM_DEBUG 115 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 116 printf x 117 #else 118 #define DPRINTF(sc, x) /* nothing */ 119 #endif 120 121 122 /* 123 * gem_attach: 124 * 125 * Attach a Gem interface to the system. 126 */ 127 void 128 gem_attach(sc, enaddr) 129 struct gem_softc *sc; 130 const uint8_t *enaddr; 131 { 132 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 133 struct mii_data *mii = &sc->sc_mii; 134 struct mii_softc *child; 135 int i, error; 136 137 /* Make sure the chip is stopped. */ 138 ifp->if_softc = sc; 139 gem_reset(sc); 140 141 /* 142 * Allocate the control data structures, and create and load the 143 * DMA map for it. 144 */ 145 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 146 sizeof(struct gem_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 147 1, &sc->sc_cdnseg, 0)) != 0) { 148 printf("%s: unable to allocate control data, error = %d\n", 149 sc->sc_dev.dv_xname, error); 150 goto fail_0; 151 } 152 153 /* XXX should map this in with correct endianness */ 154 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg, 155 sizeof(struct gem_control_data), (caddr_t *)&sc->sc_control_data, 156 BUS_DMA_COHERENT)) != 0) { 157 printf("%s: unable to map control data, error = %d\n", 158 sc->sc_dev.dv_xname, error); 159 goto fail_1; 160 } 161 162 if ((error = bus_dmamap_create(sc->sc_dmatag, 163 sizeof(struct gem_control_data), 1, 164 sizeof(struct gem_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 165 printf("%s: unable to create control data DMA map, " 166 "error = %d\n", sc->sc_dev.dv_xname, error); 167 goto fail_2; 168 } 169 170 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 171 sc->sc_control_data, sizeof(struct gem_control_data), NULL, 172 0)) != 0) { 173 printf("%s: unable to load control data DMA map, error = %d\n", 174 sc->sc_dev.dv_xname, error); 175 goto fail_3; 176 } 177 178 /* 179 * Initialize the transmit job descriptors. 180 */ 181 SIMPLEQ_INIT(&sc->sc_txfreeq); 182 SIMPLEQ_INIT(&sc->sc_txdirtyq); 183 184 /* 185 * Create the transmit buffer DMA maps. 186 */ 187 for (i = 0; i < GEM_TXQUEUELEN; i++) { 188 struct gem_txsoft *txs; 189 190 txs = &sc->sc_txsoft[i]; 191 txs->txs_mbuf = NULL; 192 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 193 GEM_NTXSEGS, MCLBYTES, 0, 0, 194 &txs->txs_dmamap)) != 0) { 195 printf("%s: unable to create tx DMA map %d, " 196 "error = %d\n", sc->sc_dev.dv_xname, i, error); 197 goto fail_4; 198 } 199 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 200 } 201 202 /* 203 * Create the receive buffer DMA maps. 204 */ 205 for (i = 0; i < GEM_NRXDESC; i++) { 206 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, 207 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 208 printf("%s: unable to create rx DMA map %d, " 209 "error = %d\n", sc->sc_dev.dv_xname, i, error); 210 goto fail_5; 211 } 212 sc->sc_rxsoft[i].rxs_mbuf = NULL; 213 } 214 215 /* 216 * From this point forward, the attachment cannot fail. A failure 217 * before this point releases all resources that may have been 218 * allocated. 219 */ 220 221 /* Announce ourselves. */ 222 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 223 ether_sprintf(enaddr)); 224 225 /* Initialize ifnet structure. */ 226 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 227 ifp->if_softc = sc; 228 ifp->if_flags = 229 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 230 ifp->if_start = gem_start; 231 ifp->if_ioctl = gem_ioctl; 232 ifp->if_watchdog = gem_watchdog; 233 ifp->if_stop = gem_stop; 234 ifp->if_init = gem_init; 235 IFQ_SET_READY(&ifp->if_snd); 236 237 /* Initialize ifmedia structures and MII info */ 238 mii->mii_ifp = ifp; 239 mii->mii_readreg = gem_mii_readreg; 240 mii->mii_writereg = gem_mii_writereg; 241 mii->mii_statchg = gem_mii_statchg; 242 243 ifmedia_init(&mii->mii_media, 0, gem_mediachange, gem_mediastatus); 244 245 gem_mifinit(sc); 246 247 mii_attach(&sc->sc_dev, mii, 0xffffffff, 248 MII_PHY_ANY, MII_OFFSET_ANY, 0); 249 250 child = LIST_FIRST(&mii->mii_phys); 251 if (child == NULL) { 252 /* No PHY attached */ 253 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 254 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 255 } else { 256 /* 257 * Walk along the list of attached MII devices and 258 * establish an `MII instance' to `phy number' 259 * mapping. We'll use this mapping in media change 260 * requests to determine which phy to use to program 261 * the MIF configuration register. 262 */ 263 for (; child != NULL; child = LIST_NEXT(child, mii_list)) { 264 /* 265 * Note: we support just two PHYs: the built-in 266 * internal device and an external on the MII 267 * connector. 268 */ 269 if (child->mii_phy > 1 || child->mii_inst > 1) { 270 printf("%s: cannot accomodate MII device %s" 271 " at phy %d, instance %d\n", 272 sc->sc_dev.dv_xname, 273 child->mii_dev.dv_xname, 274 child->mii_phy, child->mii_inst); 275 continue; 276 } 277 278 sc->sc_phys[child->mii_inst] = child->mii_phy; 279 } 280 281 /* 282 * Now select and activate the PHY we will use. 283 * 284 * The order of preference is External (MDI1), 285 * Internal (MDI0), Serial Link (no MII). 286 */ 287 if (sc->sc_phys[1]) { 288 #ifdef DEBUG 289 printf("using external phy\n"); 290 #endif 291 sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL; 292 } else { 293 #ifdef DEBUG 294 printf("using internal phy\n"); 295 #endif 296 sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL; 297 } 298 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_MIF_CONFIG, 299 sc->sc_mif_config); 300 301 /* 302 * XXX - we can really do the following ONLY if the 303 * phy indeed has the auto negotiation capability!! 304 */ 305 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO); 306 } 307 308 /* claim 802.1q capability */ 309 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 310 311 /* Attach the interface. */ 312 if_attach(ifp); 313 ether_ifattach(ifp, enaddr); 314 315 sc->sc_sh = shutdownhook_establish(gem_shutdown, sc); 316 if (sc->sc_sh == NULL) 317 panic("gem_config: can't establish shutdownhook"); 318 319 #if NRND > 0 320 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 321 RND_TYPE_NET, 0); 322 #endif 323 324 325 #if notyet 326 /* 327 * Add a suspend hook to make sure we come back up after a 328 * resume. 329 */ 330 sc->sc_powerhook = powerhook_establish(gem_power, sc); 331 if (sc->sc_powerhook == NULL) 332 printf("%s: WARNING: unable to establish power hook\n", 333 sc->sc_dev.dv_xname); 334 #endif 335 336 callout_init(&sc->sc_tick_ch); 337 return; 338 339 /* 340 * Free any resources we've allocated during the failed attach 341 * attempt. Do this in reverse order and fall through. 342 */ 343 fail_5: 344 for (i = 0; i < GEM_NRXDESC; i++) { 345 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 346 bus_dmamap_destroy(sc->sc_dmatag, 347 sc->sc_rxsoft[i].rxs_dmamap); 348 } 349 fail_4: 350 for (i = 0; i < GEM_TXQUEUELEN; i++) { 351 if (sc->sc_txsoft[i].txs_dmamap != NULL) 352 bus_dmamap_destroy(sc->sc_dmatag, 353 sc->sc_txsoft[i].txs_dmamap); 354 } 355 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 356 fail_3: 357 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 358 fail_2: 359 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)sc->sc_control_data, 360 sizeof(struct gem_control_data)); 361 fail_1: 362 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 363 fail_0: 364 return; 365 } 366 367 368 void 369 gem_tick(arg) 370 void *arg; 371 { 372 struct gem_softc *sc = arg; 373 int s; 374 375 s = splnet(); 376 mii_tick(&sc->sc_mii); 377 splx(s); 378 379 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 380 381 } 382 383 void 384 gem_reset(sc) 385 struct gem_softc *sc; 386 { 387 bus_space_tag_t t = sc->sc_bustag; 388 bus_space_handle_t h = sc->sc_h; 389 int i; 390 int s; 391 392 s = splnet(); 393 DPRINTF(sc, ("%s: gem_reset\n", sc->sc_dev.dv_xname)); 394 gem_reset_rx(sc); 395 gem_reset_tx(sc); 396 397 /* Do a full reset */ 398 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX|GEM_RESET_TX); 399 for (i=TRIES; i--; delay(100)) 400 if ((bus_space_read_4(t, h, GEM_RESET) & 401 (GEM_RESET_RX|GEM_RESET_TX)) == 0) 402 break; 403 if ((bus_space_read_4(t, h, GEM_RESET) & 404 (GEM_RESET_RX|GEM_RESET_TX)) != 0) { 405 printf("%s: cannot reset device\n", 406 sc->sc_dev.dv_xname); 407 } 408 splx(s); 409 } 410 411 412 /* 413 * gem_rxdrain: 414 * 415 * Drain the receive queue. 416 */ 417 void 418 gem_rxdrain(struct gem_softc *sc) 419 { 420 struct gem_rxsoft *rxs; 421 int i; 422 423 for (i = 0; i < GEM_NRXDESC; i++) { 424 rxs = &sc->sc_rxsoft[i]; 425 if (rxs->rxs_mbuf != NULL) { 426 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 427 m_freem(rxs->rxs_mbuf); 428 rxs->rxs_mbuf = NULL; 429 } 430 } 431 } 432 433 /* 434 * Reset the whole thing. 435 */ 436 void 437 gem_stop(struct ifnet *ifp, int disable) 438 { 439 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 440 struct gem_txsoft *txs; 441 442 DPRINTF(sc, ("%s: gem_stop\n", sc->sc_dev.dv_xname)); 443 444 callout_stop(&sc->sc_tick_ch); 445 mii_down(&sc->sc_mii); 446 447 /* XXX - Should we reset these instead? */ 448 gem_disable_rx(sc); 449 gem_disable_rx(sc); 450 451 /* 452 * Release any queued transmit buffers. 453 */ 454 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 455 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs, txs_q); 456 if (txs->txs_mbuf != NULL) { 457 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 458 m_freem(txs->txs_mbuf); 459 txs->txs_mbuf = NULL; 460 } 461 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 462 } 463 464 if (disable) { 465 gem_rxdrain(sc); 466 } 467 468 /* 469 * Mark the interface down and cancel the watchdog timer. 470 */ 471 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 472 ifp->if_timer = 0; 473 } 474 475 476 /* 477 * Reset the receiver 478 */ 479 int 480 gem_reset_rx(struct gem_softc *sc) 481 { 482 bus_space_tag_t t = sc->sc_bustag; 483 bus_space_handle_t h = sc->sc_h; 484 int i; 485 486 487 /* 488 * Resetting while DMA is in progress can cause a bus hang, so we 489 * disable DMA first. 490 */ 491 gem_disable_rx(sc); 492 bus_space_write_4(t, h, GEM_RX_CONFIG, 0); 493 /* Wait till it finishes */ 494 for (i=TRIES; i--; delay(100)) 495 if ((bus_space_read_4(t, h, GEM_RX_CONFIG) & 1) == 0) 496 break; 497 if ((bus_space_read_4(t, h, GEM_RX_CONFIG) & 1) != 0) 498 printf("%s: cannot disable read dma\n", 499 sc->sc_dev.dv_xname); 500 501 /* Wait 5ms extra. */ 502 delay(5000); 503 504 /* Finally, reset the ERX */ 505 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX); 506 /* Wait till it finishes */ 507 for (i=TRIES; i--; delay(100)) 508 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_RX) == 0) 509 break; 510 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_RX) != 0) { 511 printf("%s: cannot reset receiver\n", 512 sc->sc_dev.dv_xname); 513 return (1); 514 } 515 return (0); 516 } 517 518 519 /* 520 * Reset the transmitter 521 */ 522 int 523 gem_reset_tx(struct gem_softc *sc) 524 { 525 bus_space_tag_t t = sc->sc_bustag; 526 bus_space_handle_t h = sc->sc_h; 527 int i; 528 529 /* 530 * Resetting while DMA is in progress can cause a bus hang, so we 531 * disable DMA first. 532 */ 533 gem_disable_tx(sc); 534 bus_space_write_4(t, h, GEM_TX_CONFIG, 0); 535 /* Wait till it finishes */ 536 for (i=TRIES; i--; delay(100)) 537 if ((bus_space_read_4(t, h, GEM_TX_CONFIG) & 1) == 0) 538 break; 539 if ((bus_space_read_4(t, h, GEM_TX_CONFIG) & 1) != 0) 540 printf("%s: cannot disable read dma\n", 541 sc->sc_dev.dv_xname); 542 543 /* Wait 5ms extra. */ 544 delay(5000); 545 546 /* Finally, reset the ETX */ 547 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_TX); 548 /* Wait till it finishes */ 549 for (i=TRIES; i--; delay(100)) 550 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_TX) == 0) 551 break; 552 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_TX) != 0) { 553 printf("%s: cannot reset receiver\n", 554 sc->sc_dev.dv_xname); 555 return (1); 556 } 557 return (0); 558 } 559 560 /* 561 * disable receiver. 562 */ 563 int 564 gem_disable_rx(struct gem_softc *sc) 565 { 566 bus_space_tag_t t = sc->sc_bustag; 567 bus_space_handle_t h = sc->sc_h; 568 int i; 569 u_int32_t cfg; 570 571 /* Flip the enable bit */ 572 cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 573 cfg &= ~GEM_MAC_RX_ENABLE; 574 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg); 575 576 /* Wait for it to finish */ 577 for (i=TRIES; i--; delay(100)) 578 if ((bus_space_read_4(t, h, GEM_MAC_RX_CONFIG) & 579 GEM_MAC_RX_ENABLE) == 0) 580 return (0); 581 return (1); 582 } 583 584 /* 585 * disable transmitter. 586 */ 587 int 588 gem_disable_tx(struct gem_softc *sc) 589 { 590 bus_space_tag_t t = sc->sc_bustag; 591 bus_space_handle_t h = sc->sc_h; 592 int i; 593 u_int32_t cfg; 594 595 /* Flip the enable bit */ 596 cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG); 597 cfg &= ~GEM_MAC_TX_ENABLE; 598 bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg); 599 600 /* Wait for it to finish */ 601 for (i=TRIES; i--; delay(100)) 602 if ((bus_space_read_4(t, h, GEM_MAC_TX_CONFIG) & 603 GEM_MAC_TX_ENABLE) == 0) 604 return (0); 605 return (1); 606 } 607 608 /* 609 * Initialize interface. 610 */ 611 int 612 gem_meminit(struct gem_softc *sc) 613 { 614 struct gem_rxsoft *rxs; 615 int i, error; 616 617 /* 618 * Initialize the transmit descriptor ring. 619 */ 620 memset((void *)sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 621 for (i = 0; i < GEM_NTXDESC; i++) { 622 sc->sc_txdescs[i].gd_flags = 0; 623 sc->sc_txdescs[i].gd_addr = 0; 624 } 625 GEM_CDTXSYNC(sc, 0, GEM_NTXDESC, 626 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 627 sc->sc_txfree = GEM_NTXDESC; 628 sc->sc_txnext = 0; 629 630 /* 631 * Initialize the receive descriptor and receive job 632 * descriptor rings. 633 */ 634 for (i = 0; i < GEM_NRXDESC; i++) { 635 rxs = &sc->sc_rxsoft[i]; 636 if (rxs->rxs_mbuf == NULL) { 637 if ((error = gem_add_rxbuf(sc, i)) != 0) { 638 printf("%s: unable to allocate or map rx " 639 "buffer %d, error = %d\n", 640 sc->sc_dev.dv_xname, i, error); 641 /* 642 * XXX Should attempt to run with fewer receive 643 * XXX buffers instead of just failing. 644 */ 645 gem_rxdrain(sc); 646 return (1); 647 } 648 } else 649 GEM_INIT_RXDESC(sc, i); 650 } 651 sc->sc_rxptr = 0; 652 653 return (0); 654 } 655 656 static int 657 gem_ringsize(int sz) 658 { 659 int v; 660 661 switch (sz) { 662 case 32: 663 v = GEM_RING_SZ_32; 664 break; 665 case 64: 666 v = GEM_RING_SZ_64; 667 break; 668 case 128: 669 v = GEM_RING_SZ_128; 670 break; 671 case 256: 672 v = GEM_RING_SZ_256; 673 break; 674 case 512: 675 v = GEM_RING_SZ_512; 676 break; 677 case 1024: 678 v = GEM_RING_SZ_1024; 679 break; 680 case 2048: 681 v = GEM_RING_SZ_2048; 682 break; 683 case 4096: 684 v = GEM_RING_SZ_4096; 685 break; 686 case 8192: 687 v = GEM_RING_SZ_8192; 688 break; 689 default: 690 printf("gem: invalid Receive Descriptor ring size\n"); 691 break; 692 } 693 return (v); 694 } 695 696 /* 697 * Initialization of interface; set up initialization block 698 * and transmit/receive descriptor rings. 699 */ 700 int 701 gem_init(struct ifnet *ifp) 702 { 703 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 704 bus_space_tag_t t = sc->sc_bustag; 705 bus_space_handle_t h = sc->sc_h; 706 int s; 707 u_int32_t v; 708 709 s = splnet(); 710 711 DPRINTF(sc, ("%s: gem_init: calling stop\n", sc->sc_dev.dv_xname)); 712 /* 713 * Initialization sequence. The numbered steps below correspond 714 * to the sequence outlined in section 6.3.5.1 in the Ethernet 715 * Channel Engine manual (part of the PCIO manual). 716 * See also the STP2002-STQ document from Sun Microsystems. 717 */ 718 719 /* step 1 & 2. Reset the Ethernet Channel */ 720 gem_stop(ifp, 0); 721 gem_reset(sc); 722 DPRINTF(sc, ("%s: gem_init: restarting\n", sc->sc_dev.dv_xname)); 723 724 /* Re-initialize the MIF */ 725 gem_mifinit(sc); 726 727 /* Call MI reset function if any */ 728 if (sc->sc_hwreset) 729 (*sc->sc_hwreset)(sc); 730 731 /* step 3. Setup data structures in host memory */ 732 gem_meminit(sc); 733 734 /* step 4. TX MAC registers & counters */ 735 gem_init_regs(sc); 736 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 737 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 738 ETHER_VLAN_ENCAP_LEN + ETHER_MAX_LEN + sizeof(struct ether_header): 739 ETHER_MAX_LEN + sizeof(struct ether_header)) | (0x2000<<16)); 740 741 /* step 5. RX MAC registers & counters */ 742 gem_setladrf(sc); 743 744 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 745 /* NOTE: we use only 32-bit DMA addresses here. */ 746 bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 0); 747 bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 748 749 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0); 750 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 751 752 /* step 8. Global Configuration & Interrupt Mask */ 753 bus_space_write_4(t, h, GEM_INTMASK, 754 ~(GEM_INTR_TX_INTME| 755 GEM_INTR_TX_EMPTY| 756 GEM_INTR_RX_DONE|GEM_INTR_RX_NOBUF| 757 GEM_INTR_RX_TAG_ERR|GEM_INTR_PCS| 758 GEM_INTR_MAC_CONTROL|GEM_INTR_MIF| 759 GEM_INTR_BERR)); 760 bus_space_write_4(t, h, GEM_MAC_RX_MASK, 0); /* XXXX */ 761 bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXXX */ 762 bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 0); /* XXXX */ 763 764 /* step 9. ETX Configuration: use mostly default values */ 765 766 /* Enable DMA */ 767 v = gem_ringsize(GEM_NTXDESC /*XXX*/); 768 bus_space_write_4(t, h, GEM_TX_CONFIG, 769 v|GEM_TX_CONFIG_TXDMA_EN| 770 ((0x400<<10)&GEM_TX_CONFIG_TXFIFO_TH)); 771 bus_space_write_4(t, h, GEM_TX_KICK, sc->sc_txnext); 772 773 /* step 10. ERX Configuration */ 774 775 /* Encode Receive Descriptor ring size: four possible values */ 776 v = gem_ringsize(GEM_NRXDESC /*XXX*/); 777 778 /* Enable DMA */ 779 bus_space_write_4(t, h, GEM_RX_CONFIG, 780 v|(GEM_THRSH_1024<<GEM_RX_CONFIG_FIFO_THRS_SHIFT)| 781 (2<<GEM_RX_CONFIG_FBOFF_SHFT)|GEM_RX_CONFIG_RXDMA_EN| 782 (0<<GEM_RX_CONFIG_CXM_START_SHFT)); 783 /* 784 * The following value is for an OFF Threshold of about 15.5 Kbytes 785 * and an ON Threshold of 4K bytes. 786 */ 787 bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH, 0xf8 | (0x40 << 12)); 788 bus_space_write_4(t, h, GEM_RX_BLANKING, (2<<12)|6); 789 790 /* step 11. Configure Media */ 791 gem_mii_statchg(&sc->sc_dev); 792 793 /* XXXX Serial link needs a whole different setup. */ 794 795 796 /* step 12. RX_MAC Configuration Register */ 797 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 798 v |= GEM_MAC_RX_ENABLE; 799 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 800 801 /* step 14. Issue Transmit Pending command */ 802 803 /* Call MI initialization function if any */ 804 if (sc->sc_hwinit) 805 (*sc->sc_hwinit)(sc); 806 807 808 /* step 15. Give the reciever a swift kick */ 809 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4); 810 811 /* Start the one second timer. */ 812 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 813 814 ifp->if_flags |= IFF_RUNNING; 815 ifp->if_flags &= ~IFF_OACTIVE; 816 ifp->if_timer = 0; 817 splx(s); 818 819 return (0); 820 } 821 822 void 823 gem_init_regs(struct gem_softc *sc) 824 { 825 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 826 bus_space_tag_t t = sc->sc_bustag; 827 bus_space_handle_t h = sc->sc_h; 828 829 /* These regs are not cleared on reset */ 830 sc->sc_inited = 0; 831 if (!sc->sc_inited) { 832 833 /* Wooo. Magic values. */ 834 bus_space_write_4(t, h, GEM_MAC_IPG0, 0); 835 bus_space_write_4(t, h, GEM_MAC_IPG1, 8); 836 bus_space_write_4(t, h, GEM_MAC_IPG2, 4); 837 838 bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 839 /* Max frame and max burst size */ 840 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 841 (ifp->if_mtu+18) | (0x2000<<16)/* Burst size */); 842 bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x7); 843 bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x4); 844 bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10); 845 /* Dunno.... */ 846 bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088); 847 bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED, 848 ((LLADDR(ifp->if_sadl)[5]<<8)| 849 LLADDR(ifp->if_sadl)[4])&0x3ff); 850 /* Secondary MAC addr set to 0:0:0:0:0:0 */ 851 bus_space_write_4(t, h, GEM_MAC_ADDR3, 0); 852 bus_space_write_4(t, h, GEM_MAC_ADDR4, 0); 853 bus_space_write_4(t, h, GEM_MAC_ADDR5, 0); 854 /* MAC control addr set to 0:1:c2:0:1:80 */ 855 bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001); 856 bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200); 857 bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180); 858 859 /* MAC filter addr set to 0:0:0:0:0:0 */ 860 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0); 861 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0); 862 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0); 863 864 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0); 865 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0); 866 867 sc->sc_inited = 1; 868 } 869 870 /* Counters need to be zeroed */ 871 bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0); 872 bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0); 873 bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0); 874 bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0); 875 bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0); 876 bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0); 877 bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0); 878 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 879 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 880 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 881 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 882 883 /* Un-pause stuff */ 884 #if 0 885 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); 886 #else 887 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0); 888 #endif 889 890 /* 891 * Set the station address. 892 */ 893 bus_space_write_4(t, h, GEM_MAC_ADDR0, 894 (LLADDR(ifp->if_sadl)[4]<<8) | LLADDR(ifp->if_sadl)[5]); 895 bus_space_write_4(t, h, GEM_MAC_ADDR1, 896 (LLADDR(ifp->if_sadl)[2]<<8) | LLADDR(ifp->if_sadl)[3]); 897 bus_space_write_4(t, h, GEM_MAC_ADDR2, 898 (LLADDR(ifp->if_sadl)[0]<<8) | LLADDR(ifp->if_sadl)[1]); 899 900 } 901 902 903 904 void 905 gem_start(ifp) 906 struct ifnet *ifp; 907 { 908 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 909 struct mbuf *m0, *m; 910 struct gem_txsoft *txs, *last_txs; 911 bus_dmamap_t dmamap; 912 int error, firsttx, nexttx, lasttx, ofree, seg; 913 914 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 915 return; 916 917 /* 918 * Remember the previous number of free descriptors and 919 * the first descriptor we'll use. 920 */ 921 ofree = sc->sc_txfree; 922 firsttx = sc->sc_txnext; 923 924 DPRINTF(sc, ("%s: gem_start: txfree %d, txnext %d\n", 925 sc->sc_dev.dv_xname, ofree, firsttx)); 926 927 /* 928 * Loop through the send queue, setting up transmit descriptors 929 * until we drain the queue, or use up all available transmit 930 * descriptors. 931 */ 932 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 933 sc->sc_txfree != 0) { 934 /* 935 * Grab a packet off the queue. 936 */ 937 IFQ_POLL(&ifp->if_snd, m0); 938 if (m0 == NULL) 939 break; 940 m = NULL; 941 942 dmamap = txs->txs_dmamap; 943 944 /* 945 * Load the DMA map. If this fails, the packet either 946 * didn't fit in the alloted number of segments, or we were 947 * short on resources. In this case, we'll copy and try 948 * again. 949 */ 950 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m0, 951 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 952 MGETHDR(m, M_DONTWAIT, MT_DATA); 953 if (m == NULL) { 954 printf("%s: unable to allocate Tx mbuf\n", 955 sc->sc_dev.dv_xname); 956 break; 957 } 958 if (m0->m_pkthdr.len > MHLEN) { 959 MCLGET(m, M_DONTWAIT); 960 if ((m->m_flags & M_EXT) == 0) { 961 printf("%s: unable to allocate Tx " 962 "cluster\n", sc->sc_dev.dv_xname); 963 m_freem(m); 964 break; 965 } 966 } 967 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 968 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 969 error = bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, 970 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 971 if (error) { 972 printf("%s: unable to load Tx buffer, " 973 "error = %d\n", sc->sc_dev.dv_xname, error); 974 break; 975 } 976 } 977 978 /* 979 * Ensure we have enough descriptors free to describe 980 * the packet. 981 */ 982 if (dmamap->dm_nsegs > sc->sc_txfree) { 983 /* 984 * Not enough free descriptors to transmit this 985 * packet. We haven't committed to anything yet, 986 * so just unload the DMA map, put the packet 987 * back on the queue, and punt. Notify the upper 988 * layer that there are no more slots left. 989 * 990 * XXX We could allocate an mbuf and copy, but 991 * XXX it is worth it? 992 */ 993 ifp->if_flags |= IFF_OACTIVE; 994 bus_dmamap_unload(sc->sc_dmatag, dmamap); 995 if (m != NULL) 996 m_freem(m); 997 break; 998 } 999 1000 IFQ_DEQUEUE(&ifp->if_snd, m0); 1001 if (m != NULL) { 1002 m_freem(m0); 1003 m0 = m; 1004 } 1005 1006 /* 1007 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1008 */ 1009 1010 /* Sync the DMA map. */ 1011 bus_dmamap_sync(sc->sc_dmatag, dmamap, 0, dmamap->dm_mapsize, 1012 BUS_DMASYNC_PREWRITE); 1013 1014 /* 1015 * Initialize the transmit descriptors. 1016 */ 1017 for (nexttx = sc->sc_txnext, seg = 0; 1018 seg < dmamap->dm_nsegs; 1019 seg++, nexttx = GEM_NEXTTX(nexttx)) { 1020 uint64_t flags; 1021 1022 /* 1023 * If this is the first descriptor we're 1024 * enqueueing, set the start of packet flag, 1025 * and the checksum stuff if we want the hardware 1026 * to do it. 1027 */ 1028 sc->sc_txdescs[nexttx].gd_addr = 1029 GEM_DMA_WRITE(sc, dmamap->dm_segs[seg].ds_addr); 1030 flags = dmamap->dm_segs[seg].ds_len & GEM_TD_BUFSIZE; 1031 if (nexttx == firsttx) { 1032 flags |= GEM_TD_START_OF_PACKET; 1033 } 1034 if (seg == dmamap->dm_nsegs - 1) { 1035 flags |= GEM_TD_END_OF_PACKET; 1036 } 1037 sc->sc_txdescs[nexttx].gd_flags = 1038 GEM_DMA_WRITE(sc, flags); 1039 lasttx = nexttx; 1040 } 1041 1042 #ifdef GEM_DEBUG 1043 if (ifp->if_flags & IFF_DEBUG) { 1044 printf(" gem_start %p transmit chain:\n", txs); 1045 for (seg = sc->sc_txnext;; seg = GEM_NEXTTX(seg)) { 1046 printf("descriptor %d:\t", seg); 1047 printf("gd_flags: 0x%016llx\t", (long long) 1048 GEM_DMA_READ(sc, sc->sc_txdescs[seg].gd_flags)); 1049 printf("gd_addr: 0x%016llx\n", (long long) 1050 GEM_DMA_READ(sc, sc->sc_txdescs[seg].gd_addr)); 1051 if (seg == lasttx) 1052 break; 1053 } 1054 } 1055 #endif 1056 1057 /* Sync the descriptors we're using. */ 1058 GEM_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1059 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1060 1061 /* 1062 * Store a pointer to the packet so we can free it later, 1063 * and remember what txdirty will be once the packet is 1064 * done. 1065 */ 1066 txs->txs_mbuf = m0; 1067 txs->txs_firstdesc = sc->sc_txnext; 1068 txs->txs_lastdesc = lasttx; 1069 txs->txs_ndescs = dmamap->dm_nsegs; 1070 1071 /* Advance the tx pointer. */ 1072 sc->sc_txfree -= dmamap->dm_nsegs; 1073 sc->sc_txnext = nexttx; 1074 1075 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs, txs_q); 1076 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1077 1078 last_txs = txs; 1079 1080 #if NBPFILTER > 0 1081 /* 1082 * Pass the packet to any BPF listeners. 1083 */ 1084 if (ifp->if_bpf) 1085 bpf_mtap(ifp->if_bpf, m0); 1086 #endif /* NBPFILTER > 0 */ 1087 } 1088 1089 if (txs == NULL || sc->sc_txfree == 0) { 1090 /* No more slots left; notify upper layer. */ 1091 ifp->if_flags |= IFF_OACTIVE; 1092 } 1093 1094 if (sc->sc_txfree != ofree) { 1095 DPRINTF(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 1096 sc->sc_dev.dv_xname, lasttx, firsttx)); 1097 /* 1098 * The entire packet chain is set up. 1099 * Kick the transmitter. 1100 */ 1101 DPRINTF(sc, ("%s: gem_start: kicking tx %d\n", 1102 sc->sc_dev.dv_xname, nexttx)); 1103 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_TX_KICK, 1104 sc->sc_txnext); 1105 1106 /* Set a watchdog timer in case the chip flakes out. */ 1107 ifp->if_timer = 5; 1108 DPRINTF(sc, ("%s: gem_start: watchdog %d\n", 1109 sc->sc_dev.dv_xname, ifp->if_timer)); 1110 } 1111 } 1112 1113 /* 1114 * Transmit interrupt. 1115 */ 1116 int 1117 gem_tint(sc) 1118 struct gem_softc *sc; 1119 { 1120 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1121 bus_space_tag_t t = sc->sc_bustag; 1122 bus_space_handle_t mac = sc->sc_h; 1123 struct gem_txsoft *txs; 1124 int txlast; 1125 1126 1127 DPRINTF(sc, ("%s: gem_tint\n", sc->sc_dev.dv_xname)); 1128 1129 /* 1130 * Unload collision counters 1131 */ 1132 ifp->if_collisions += 1133 bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) + 1134 bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT) + 1135 bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) + 1136 bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT); 1137 1138 /* 1139 * then clear the hardware counters. 1140 */ 1141 bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0); 1142 bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0); 1143 bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0); 1144 bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0); 1145 1146 /* 1147 * Go through our Tx list and free mbufs for those 1148 * frames that have been transmitted. 1149 */ 1150 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1151 GEM_CDTXSYNC(sc, txs->txs_lastdesc, 1152 txs->txs_ndescs, 1153 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1154 1155 #ifdef GEM_DEBUG 1156 if (ifp->if_flags & IFF_DEBUG) { 1157 int i; 1158 printf(" txsoft %p transmit chain:\n", txs); 1159 for (i = txs->txs_firstdesc;; i = GEM_NEXTTX(i)) { 1160 printf("descriptor %d: ", i); 1161 printf("gd_flags: 0x%016llx\t", (long long) 1162 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags)); 1163 printf("gd_addr: 0x%016llx\n", (long long) 1164 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr)); 1165 if (i == txs->txs_lastdesc) 1166 break; 1167 } 1168 } 1169 #endif 1170 1171 /* 1172 * In theory, we could harveast some descriptors before 1173 * the ring is empty, but that's a bit complicated. 1174 * 1175 * GEM_TX_COMPLETION points to the last descriptor 1176 * processed +1. 1177 */ 1178 txlast = bus_space_read_4(t, mac, GEM_TX_COMPLETION); 1179 DPRINTF(sc, 1180 ("gem_tint: txs->txs_lastdesc = %d, txlast = %d\n", 1181 txs->txs_lastdesc, txlast)); 1182 if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1183 if ((txlast >= txs->txs_firstdesc) && 1184 (txlast <= txs->txs_lastdesc)) 1185 break; 1186 } else { 1187 /* Ick -- this command wraps */ 1188 if ((txlast >= txs->txs_firstdesc) || 1189 (txlast <= txs->txs_lastdesc)) 1190 break; 1191 } 1192 1193 DPRINTF(sc, ("gem_tint: releasing a desc\n")); 1194 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs, txs_q); 1195 1196 sc->sc_txfree += txs->txs_ndescs; 1197 1198 if (txs->txs_mbuf == NULL) { 1199 #ifdef DIAGNOSTIC 1200 panic("gem_txintr: null mbuf"); 1201 #endif 1202 } 1203 1204 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 1205 0, txs->txs_dmamap->dm_mapsize, 1206 BUS_DMASYNC_POSTWRITE); 1207 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 1208 m_freem(txs->txs_mbuf); 1209 txs->txs_mbuf = NULL; 1210 1211 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1212 1213 ifp->if_opackets++; 1214 } 1215 1216 DPRINTF(sc, ("gem_tint: GEM_TX_STATE_MACHINE %x " 1217 "GEM_TX_DATA_PTR %llx " 1218 "GEM_TX_COMPLETION %x\n", 1219 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_STATE_MACHINE), 1220 ((long long) bus_space_read_4(sc->sc_bustag, sc->sc_h, 1221 GEM_TX_DATA_PTR_HI) << 32) | 1222 bus_space_read_4(sc->sc_bustag, sc->sc_h, 1223 GEM_TX_DATA_PTR_LO), 1224 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_COMPLETION))); 1225 1226 gem_start(ifp); 1227 1228 if (SIMPLEQ_FIRST(&sc->sc_txdirtyq) == NULL) 1229 ifp->if_timer = 0; 1230 DPRINTF(sc, ("%s: gem_tint: watchdog %d\n", 1231 sc->sc_dev.dv_xname, ifp->if_timer)); 1232 1233 return (1); 1234 } 1235 1236 /* 1237 * Receive interrupt. 1238 */ 1239 int 1240 gem_rint(sc) 1241 struct gem_softc *sc; 1242 { 1243 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1244 bus_space_tag_t t = sc->sc_bustag; 1245 bus_space_handle_t h = sc->sc_h; 1246 struct ether_header *eh; 1247 struct gem_rxsoft *rxs; 1248 struct mbuf *m; 1249 u_int64_t rxstat; 1250 int i, len; 1251 1252 DPRINTF(sc, ("%s: gem_rint\n", sc->sc_dev.dv_xname)); 1253 /* 1254 * XXXX Read the lastrx only once at the top for speed. 1255 */ 1256 DPRINTF(sc, ("gem_rint: sc->rxptr %d, complete %d\n", 1257 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION))); 1258 for (i = sc->sc_rxptr; i != bus_space_read_4(t, h, GEM_RX_COMPLETION); 1259 i = GEM_NEXTRX(i)) { 1260 rxs = &sc->sc_rxsoft[i]; 1261 1262 GEM_CDRXSYNC(sc, i, 1263 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1264 1265 rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags); 1266 1267 if (rxstat & GEM_RD_OWN) { 1268 printf("gem_rint: completed descriptor " 1269 "still owned %d\n", i); 1270 /* 1271 * We have processed all of the receive buffers. 1272 */ 1273 break; 1274 } 1275 1276 if (rxstat & GEM_RD_BAD_CRC) { 1277 printf("%s: receive error: CRC error\n", 1278 sc->sc_dev.dv_xname); 1279 GEM_INIT_RXDESC(sc, i); 1280 continue; 1281 } 1282 1283 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1284 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1285 #ifdef GEM_DEBUG 1286 if (ifp->if_flags & IFF_DEBUG) { 1287 printf(" rxsoft %p descriptor %d: ", rxs, i); 1288 printf("gd_flags: 0x%016llx\t", (long long) 1289 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags)); 1290 printf("gd_addr: 0x%016llx\n", (long long) 1291 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr)); 1292 } 1293 #endif 1294 1295 /* 1296 * No errors; receive the packet. Note the Gem 1297 * includes the CRC with every packet. 1298 */ 1299 len = GEM_RD_BUFLEN(rxstat); 1300 1301 /* 1302 * Allocate a new mbuf cluster. If that fails, we are 1303 * out of memory, and must drop the packet and recycle 1304 * the buffer that's already attached to this descriptor. 1305 */ 1306 m = rxs->rxs_mbuf; 1307 if (gem_add_rxbuf(sc, i) != 0) { 1308 ifp->if_ierrors++; 1309 GEM_INIT_RXDESC(sc, i); 1310 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1311 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1312 continue; 1313 } 1314 m->m_data += 2; /* We're already off by two */ 1315 1316 ifp->if_ipackets++; 1317 eh = mtod(m, struct ether_header *); 1318 m->m_flags |= M_HASFCS; 1319 m->m_pkthdr.rcvif = ifp; 1320 m->m_pkthdr.len = m->m_len = len; 1321 1322 #if NBPFILTER > 0 1323 /* 1324 * Pass this up to any BPF listeners, but only 1325 * pass it up the stack if its for us. 1326 */ 1327 if (ifp->if_bpf) 1328 bpf_mtap(ifp->if_bpf, m); 1329 #endif /* NPBFILTER > 0 */ 1330 1331 /* Pass it on. */ 1332 (*ifp->if_input)(ifp, m); 1333 } 1334 1335 /* Update the receive pointer. */ 1336 sc->sc_rxptr = i; 1337 bus_space_write_4(t, h, GEM_RX_KICK, i); 1338 1339 DPRINTF(sc, ("gem_rint: done sc->rxptr %d, complete %d\n", 1340 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION))); 1341 1342 return (1); 1343 } 1344 1345 1346 /* 1347 * gem_add_rxbuf: 1348 * 1349 * Add a receive buffer to the indicated descriptor. 1350 */ 1351 int 1352 gem_add_rxbuf(struct gem_softc *sc, int idx) 1353 { 1354 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1355 struct mbuf *m; 1356 int error; 1357 1358 MGETHDR(m, M_DONTWAIT, MT_DATA); 1359 if (m == NULL) 1360 return (ENOBUFS); 1361 1362 MCLGET(m, M_DONTWAIT); 1363 if ((m->m_flags & M_EXT) == 0) { 1364 m_freem(m); 1365 return (ENOBUFS); 1366 } 1367 1368 #ifdef GEM_DEBUG 1369 /* bzero the packet to check dma */ 1370 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 1371 #endif 1372 1373 if (rxs->rxs_mbuf != NULL) 1374 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 1375 1376 rxs->rxs_mbuf = m; 1377 1378 error = bus_dmamap_load(sc->sc_dmatag, rxs->rxs_dmamap, 1379 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1380 BUS_DMA_READ|BUS_DMA_NOWAIT); 1381 if (error) { 1382 printf("%s: can't load rx DMA map %d, error = %d\n", 1383 sc->sc_dev.dv_xname, idx, error); 1384 panic("gem_add_rxbuf"); /* XXX */ 1385 } 1386 1387 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1388 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1389 1390 GEM_INIT_RXDESC(sc, idx); 1391 1392 return (0); 1393 } 1394 1395 1396 int 1397 gem_eint(sc, status) 1398 struct gem_softc *sc; 1399 u_int status; 1400 { 1401 char bits[128]; 1402 1403 if ((status & GEM_INTR_MIF) != 0) { 1404 printf("%s: XXXlink status changed\n", sc->sc_dev.dv_xname); 1405 return (1); 1406 } 1407 1408 printf("%s: status=%s\n", sc->sc_dev.dv_xname, 1409 bitmask_snprintf(status, GEM_INTR_BITS, bits, sizeof(bits))); 1410 return (1); 1411 } 1412 1413 1414 int 1415 gem_intr(v) 1416 void *v; 1417 { 1418 struct gem_softc *sc = (struct gem_softc *)v; 1419 bus_space_tag_t t = sc->sc_bustag; 1420 bus_space_handle_t seb = sc->sc_h; 1421 u_int32_t status; 1422 int r = 0; 1423 #ifdef GEM_DEBUG 1424 char bits[128]; 1425 #endif 1426 1427 status = bus_space_read_4(t, seb, GEM_STATUS); 1428 DPRINTF(sc, ("%s: gem_intr: cplt %xstatus %s\n", 1429 sc->sc_dev.dv_xname, (status>>19), 1430 bitmask_snprintf(status, GEM_INTR_BITS, bits, sizeof(bits)))); 1431 1432 if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0) 1433 r |= gem_eint(sc, status); 1434 1435 if ((status & 1436 (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) 1437 != 0) 1438 r |= gem_tint(sc); 1439 1440 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) 1441 r |= gem_rint(sc); 1442 1443 /* We should eventually do more than just print out error stats. */ 1444 if (status & GEM_INTR_TX_MAC) { 1445 int txstat = bus_space_read_4(t, seb, GEM_MAC_TX_STATUS); 1446 if (txstat & ~GEM_MAC_TX_XMIT_DONE) 1447 printf("MAC tx fault, status %x\n", txstat); 1448 } 1449 if (status & GEM_INTR_RX_MAC) { 1450 int rxstat = bus_space_read_4(t, seb, GEM_MAC_RX_STATUS); 1451 if (rxstat & ~GEM_MAC_RX_DONE) 1452 printf("MAC rx fault, status %x\n", rxstat); 1453 } 1454 return (r); 1455 } 1456 1457 1458 void 1459 gem_watchdog(ifp) 1460 struct ifnet *ifp; 1461 { 1462 struct gem_softc *sc = ifp->if_softc; 1463 1464 DPRINTF(sc, ("gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x " 1465 "GEM_MAC_RX_CONFIG %x\n", 1466 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_CONFIG), 1467 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_STATUS), 1468 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_CONFIG))); 1469 1470 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1471 ++ifp->if_oerrors; 1472 1473 /* Try to get more packets going. */ 1474 gem_start(ifp); 1475 } 1476 1477 /* 1478 * Initialize the MII Management Interface 1479 */ 1480 void 1481 gem_mifinit(sc) 1482 struct gem_softc *sc; 1483 { 1484 bus_space_tag_t t = sc->sc_bustag; 1485 bus_space_handle_t mif = sc->sc_h; 1486 1487 /* Configure the MIF in frame mode */ 1488 sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1489 sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA; 1490 bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config); 1491 } 1492 1493 /* 1494 * MII interface 1495 * 1496 * The GEM MII interface supports at least three different operating modes: 1497 * 1498 * Bitbang mode is implemented using data, clock and output enable registers. 1499 * 1500 * Frame mode is implemented by loading a complete frame into the frame 1501 * register and polling the valid bit for completion. 1502 * 1503 * Polling mode uses the frame register but completion is indicated by 1504 * an interrupt. 1505 * 1506 */ 1507 static int 1508 gem_mii_readreg(self, phy, reg) 1509 struct device *self; 1510 int phy, reg; 1511 { 1512 struct gem_softc *sc = (void *)self; 1513 bus_space_tag_t t = sc->sc_bustag; 1514 bus_space_handle_t mif = sc->sc_h; 1515 int n; 1516 u_int32_t v; 1517 1518 #ifdef GEM_DEBUG1 1519 if (sc->sc_debug) 1520 printf("gem_mii_readreg: phy %d reg %d\n", phy, reg); 1521 #endif 1522 1523 #if 0 1524 /* Select the desired PHY in the MIF configuration register */ 1525 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1526 /* Clear PHY select bit */ 1527 v &= ~GEM_MIF_CONFIG_PHY_SEL; 1528 if (phy == GEM_PHYAD_EXTERNAL) 1529 /* Set PHY select bit to get at external device */ 1530 v |= GEM_MIF_CONFIG_PHY_SEL; 1531 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 1532 #endif 1533 1534 /* Construct the frame command */ 1535 v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) | 1536 GEM_MIF_FRAME_READ; 1537 1538 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1539 for (n = 0; n < 100; n++) { 1540 DELAY(1); 1541 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1542 if (v & GEM_MIF_FRAME_TA0) 1543 return (v & GEM_MIF_FRAME_DATA); 1544 } 1545 1546 printf("%s: mii_read timeout\n", sc->sc_dev.dv_xname); 1547 return (0); 1548 } 1549 1550 static void 1551 gem_mii_writereg(self, phy, reg, val) 1552 struct device *self; 1553 int phy, reg, val; 1554 { 1555 struct gem_softc *sc = (void *)self; 1556 bus_space_tag_t t = sc->sc_bustag; 1557 bus_space_handle_t mif = sc->sc_h; 1558 int n; 1559 u_int32_t v; 1560 1561 #ifdef GEM_DEBUG1 1562 if (sc->sc_debug) 1563 printf("gem_mii_writereg: phy %d reg %d val %x\n", 1564 phy, reg, val); 1565 #endif 1566 1567 #if 0 1568 /* Select the desired PHY in the MIF configuration register */ 1569 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1570 /* Clear PHY select bit */ 1571 v &= ~GEM_MIF_CONFIG_PHY_SEL; 1572 if (phy == GEM_PHYAD_EXTERNAL) 1573 /* Set PHY select bit to get at external device */ 1574 v |= GEM_MIF_CONFIG_PHY_SEL; 1575 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 1576 #endif 1577 /* Construct the frame command */ 1578 v = GEM_MIF_FRAME_WRITE | 1579 (phy << GEM_MIF_PHY_SHIFT) | 1580 (reg << GEM_MIF_REG_SHIFT) | 1581 (val & GEM_MIF_FRAME_DATA); 1582 1583 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1584 for (n = 0; n < 100; n++) { 1585 DELAY(1); 1586 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1587 if (v & GEM_MIF_FRAME_TA0) 1588 return; 1589 } 1590 1591 printf("%s: mii_write timeout\n", sc->sc_dev.dv_xname); 1592 } 1593 1594 static void 1595 gem_mii_statchg(dev) 1596 struct device *dev; 1597 { 1598 struct gem_softc *sc = (void *)dev; 1599 #ifdef GEM_DEBUG 1600 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1601 #endif 1602 bus_space_tag_t t = sc->sc_bustag; 1603 bus_space_handle_t mac = sc->sc_h; 1604 u_int32_t v; 1605 1606 #ifdef GEM_DEBUG 1607 if (sc->sc_debug) 1608 printf("gem_mii_statchg: status change: phy = %d\n", 1609 sc->sc_phys[instance];); 1610 #endif 1611 1612 1613 /* Set tx full duplex options */ 1614 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0); 1615 delay(10000); /* reg must be cleared and delay before changing. */ 1616 v = GEM_MAC_TX_ENA_IPG0|GEM_MAC_TX_NGU|GEM_MAC_TX_NGU_LIMIT| 1617 GEM_MAC_TX_ENABLE; 1618 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) { 1619 v |= GEM_MAC_TX_IGN_CARRIER|GEM_MAC_TX_IGN_COLLIS; 1620 } 1621 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, v); 1622 1623 /* XIF Configuration */ 1624 /* We should really calculate all this rather than rely on defaults */ 1625 v = bus_space_read_4(t, mac, GEM_MAC_XIF_CONFIG); 1626 v = GEM_MAC_XIF_LINK_LED; 1627 v |= GEM_MAC_XIF_TX_MII_ENA; 1628 /* If an external transceiver is connected, enable its MII drivers */ 1629 sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG); 1630 if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) { 1631 /* External MII needs echo disable if half duplex. */ 1632 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1633 /* turn on full duplex LED */ 1634 v |= GEM_MAC_XIF_FDPLX_LED; 1635 else 1636 /* half duplex -- disable echo */ 1637 v |= GEM_MAC_XIF_ECHO_DISABL; 1638 } else 1639 /* Internal MII needs buf enable */ 1640 v |= GEM_MAC_XIF_MII_BUF_ENA; 1641 bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v); 1642 } 1643 1644 int 1645 gem_mediachange(ifp) 1646 struct ifnet *ifp; 1647 { 1648 struct gem_softc *sc = ifp->if_softc; 1649 1650 if (IFM_TYPE(sc->sc_media.ifm_media) != IFM_ETHER) 1651 return (EINVAL); 1652 1653 return (mii_mediachg(&sc->sc_mii)); 1654 } 1655 1656 void 1657 gem_mediastatus(ifp, ifmr) 1658 struct ifnet *ifp; 1659 struct ifmediareq *ifmr; 1660 { 1661 struct gem_softc *sc = ifp->if_softc; 1662 1663 if ((ifp->if_flags & IFF_UP) == 0) 1664 return; 1665 1666 mii_pollstat(&sc->sc_mii); 1667 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1668 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1669 } 1670 1671 int gem_ioctldebug = 0; 1672 /* 1673 * Process an ioctl request. 1674 */ 1675 int 1676 gem_ioctl(ifp, cmd, data) 1677 struct ifnet *ifp; 1678 u_long cmd; 1679 caddr_t data; 1680 { 1681 struct gem_softc *sc = ifp->if_softc; 1682 struct ifreq *ifr = (struct ifreq *)data; 1683 int s, error = 0; 1684 1685 1686 switch (cmd) { 1687 case SIOCGIFMEDIA: 1688 case SIOCSIFMEDIA: 1689 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1690 break; 1691 1692 default: 1693 error = ether_ioctl(ifp, cmd, data); 1694 if (error == ENETRESET) { 1695 /* 1696 * Multicast list has changed; set the hardware filter 1697 * accordingly. 1698 */ 1699 if (gem_ioctldebug) printf("reset1\n"); 1700 gem_init(ifp); 1701 delay(50000); 1702 error = 0; 1703 } 1704 break; 1705 } 1706 1707 /* Try to get things going again */ 1708 if (ifp->if_flags & IFF_UP) { 1709 if (gem_ioctldebug) printf("start\n"); 1710 gem_start(ifp); 1711 } 1712 splx(s); 1713 return (error); 1714 } 1715 1716 1717 void 1718 gem_shutdown(arg) 1719 void *arg; 1720 { 1721 struct gem_softc *sc = (struct gem_softc *)arg; 1722 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1723 1724 gem_stop(ifp, 1); 1725 } 1726 1727 /* 1728 * Set up the logical address filter. 1729 */ 1730 void 1731 gem_setladrf(sc) 1732 struct gem_softc *sc; 1733 { 1734 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1735 struct ether_multi *enm; 1736 struct ether_multistep step; 1737 struct ethercom *ec = &sc->sc_ethercom; 1738 bus_space_tag_t t = sc->sc_bustag; 1739 bus_space_handle_t h = sc->sc_h; 1740 u_char *cp; 1741 u_int32_t crc; 1742 u_int32_t hash[16]; 1743 u_int32_t v; 1744 int len; 1745 1746 /* Clear hash table */ 1747 memset(hash, 0, sizeof(hash)); 1748 1749 /* Get current RX configuration */ 1750 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 1751 1752 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1753 /* Turn on promiscuous mode; turn off the hash filter */ 1754 v |= GEM_MAC_RX_PROMISCUOUS; 1755 v &= ~GEM_MAC_RX_HASH_FILTER; 1756 ifp->if_flags |= IFF_ALLMULTI; 1757 goto chipit; 1758 } 1759 1760 /* Turn off promiscuous mode; turn on the hash filter */ 1761 v &= ~GEM_MAC_RX_PROMISCUOUS; 1762 v |= GEM_MAC_RX_HASH_FILTER; 1763 1764 /* 1765 * Set up multicast address filter by passing all multicast addresses 1766 * through a crc generator, and then using the high order 6 bits as an 1767 * index into the 256 bit logical address filter. The high order bit 1768 * selects the word, while the rest of the bits select the bit within 1769 * the word. 1770 */ 1771 1772 ETHER_FIRST_MULTI(step, ec, enm); 1773 while (enm != NULL) { 1774 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1775 /* 1776 * We must listen to a range of multicast addresses. 1777 * For now, just accept all multicasts, rather than 1778 * trying to set only those filter bits needed to match 1779 * the range. (At this time, the only use of address 1780 * ranges is for IP multicast routing, for which the 1781 * range is big enough to require all bits set.) 1782 */ 1783 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1784 ifp->if_flags |= IFF_ALLMULTI; 1785 goto chipit; 1786 } 1787 1788 cp = enm->enm_addrlo; 1789 crc = 0xffffffff; 1790 for (len = sizeof(enm->enm_addrlo); --len >= 0;) { 1791 int octet = *cp++; 1792 int i; 1793 1794 #define MC_POLY_LE 0xedb88320UL /* mcast crc, little endian */ 1795 for (i = 0; i < 8; i++) { 1796 if ((crc & 1) ^ (octet & 1)) { 1797 crc >>= 1; 1798 crc ^= MC_POLY_LE; 1799 } else { 1800 crc >>= 1; 1801 } 1802 octet >>= 1; 1803 } 1804 } 1805 /* Just want the 8 most significant bits. */ 1806 crc >>= 24; 1807 1808 /* Set the corresponding bit in the filter. */ 1809 hash[crc >> 4] |= 1 << (crc & 0xf); 1810 1811 ETHER_NEXT_MULTI(step, enm); 1812 } 1813 1814 ifp->if_flags &= ~IFF_ALLMULTI; 1815 1816 chipit: 1817 /* Now load the hash table into the chip */ 1818 bus_space_write_4(t, h, GEM_MAC_HASH0, hash[0]); 1819 bus_space_write_4(t, h, GEM_MAC_HASH1, hash[1]); 1820 bus_space_write_4(t, h, GEM_MAC_HASH2, hash[2]); 1821 bus_space_write_4(t, h, GEM_MAC_HASH3, hash[3]); 1822 bus_space_write_4(t, h, GEM_MAC_HASH4, hash[4]); 1823 bus_space_write_4(t, h, GEM_MAC_HASH5, hash[5]); 1824 bus_space_write_4(t, h, GEM_MAC_HASH6, hash[6]); 1825 bus_space_write_4(t, h, GEM_MAC_HASH7, hash[7]); 1826 bus_space_write_4(t, h, GEM_MAC_HASH8, hash[8]); 1827 bus_space_write_4(t, h, GEM_MAC_HASH9, hash[9]); 1828 bus_space_write_4(t, h, GEM_MAC_HASH10, hash[10]); 1829 bus_space_write_4(t, h, GEM_MAC_HASH11, hash[11]); 1830 bus_space_write_4(t, h, GEM_MAC_HASH12, hash[12]); 1831 bus_space_write_4(t, h, GEM_MAC_HASH13, hash[13]); 1832 bus_space_write_4(t, h, GEM_MAC_HASH14, hash[14]); 1833 bus_space_write_4(t, h, GEM_MAC_HASH15, hash[15]); 1834 1835 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 1836 } 1837 1838 #if notyet 1839 1840 /* 1841 * gem_power: 1842 * 1843 * Power management (suspend/resume) hook. 1844 */ 1845 void 1846 gem_power(why, arg) 1847 int why; 1848 void *arg; 1849 { 1850 struct gem_softc *sc = arg; 1851 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1852 int s; 1853 1854 s = splnet(); 1855 switch (why) { 1856 case PWR_SUSPEND: 1857 case PWR_STANDBY: 1858 gem_stop(ifp, 1); 1859 if (sc->sc_power != NULL) 1860 (*sc->sc_power)(sc, why); 1861 break; 1862 case PWR_RESUME: 1863 if (ifp->if_flags & IFF_UP) { 1864 if (sc->sc_power != NULL) 1865 (*sc->sc_power)(sc, why); 1866 gem_init(ifp); 1867 } 1868 break; 1869 case PWR_SOFTSUSPEND: 1870 case PWR_SOFTSTANDBY: 1871 case PWR_SOFTRESUME: 1872 break; 1873 } 1874 splx(s); 1875 } 1876 #endif 1877
Indexes created Wed Sep 24 22:09:59 GMT 2025