gem.c revision 1.113
1 /* $NetBSD: gem.c,v 1.113 2019/01/22 03:42:26 msaitoh Exp $ */ 2 3 /* 4 * 5 * Copyright (C) 2001 Eduardo Horvath. 6 * Copyright (c) 2001-2003 Thomas Moestl 7 * All rights reserved. 8 * 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 */ 32 33 /* 34 * Driver for Apple GMAC, Sun ERI and Sun GEM Ethernet controllers 35 * See `GEM Gigabit Ethernet ASIC Specification' 36 * http://www.sun.com/processors/manuals/ge.pdf 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: gem.c,v 1.113 2019/01/22 03:42:26 msaitoh Exp $"); 41 42 #include "opt_inet.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/callout.h> 47 #include <sys/mbuf.h> 48 #include <sys/syslog.h> 49 #include <sys/malloc.h> 50 #include <sys/kernel.h> 51 #include <sys/socket.h> 52 #include <sys/ioctl.h> 53 #include <sys/errno.h> 54 #include <sys/device.h> 55 56 #include <machine/endian.h> 57 58 #include <net/if.h> 59 #include <net/if_dl.h> 60 #include <net/if_media.h> 61 #include <net/if_ether.h> 62 63 #ifdef INET 64 #include <netinet/in.h> 65 #include <netinet/in_systm.h> 66 #include <netinet/in_var.h> 67 #include <netinet/ip.h> 68 #include <netinet/tcp.h> 69 #include <netinet/udp.h> 70 #endif 71 72 #include <net/bpf.h> 73 74 #include <sys/bus.h> 75 #include <sys/intr.h> 76 77 #include <dev/mii/mii.h> 78 #include <dev/mii/miivar.h> 79 #include <dev/mii/mii_bitbang.h> 80 81 #include <dev/ic/gemreg.h> 82 #include <dev/ic/gemvar.h> 83 84 #define TRIES 10000 85 86 static void gem_inten(struct gem_softc *); 87 static void gem_start(struct ifnet *); 88 static void gem_stop(struct ifnet *, int); 89 int gem_ioctl(struct ifnet *, u_long, void *); 90 void gem_tick(void *); 91 void gem_watchdog(struct ifnet *); 92 void gem_rx_watchdog(void *); 93 void gem_pcs_start(struct gem_softc *sc); 94 void gem_pcs_stop(struct gem_softc *sc, int); 95 int gem_init(struct ifnet *); 96 void gem_init_regs(struct gem_softc *sc); 97 static int gem_ringsize(int sz); 98 static int gem_meminit(struct gem_softc *); 99 void gem_mifinit(struct gem_softc *); 100 static int gem_bitwait(struct gem_softc *sc, bus_space_handle_t, int, 101 uint32_t, uint32_t); 102 void gem_reset(struct gem_softc *); 103 int gem_reset_rx(struct gem_softc *sc); 104 static void gem_reset_rxdma(struct gem_softc *sc); 105 static void gem_rx_common(struct gem_softc *sc); 106 int gem_reset_tx(struct gem_softc *sc); 107 int gem_disable_rx(struct gem_softc *sc); 108 int gem_disable_tx(struct gem_softc *sc); 109 static void gem_rxdrain(struct gem_softc *sc); 110 int gem_add_rxbuf(struct gem_softc *sc, int idx); 111 void gem_setladrf(struct gem_softc *); 112 113 /* MII methods & callbacks */ 114 static int gem_mii_readreg(device_t, int, int, uint16_t *); 115 static int gem_mii_writereg(device_t, int, int, uint16_t); 116 static void gem_mii_statchg(struct ifnet *); 117 118 static int gem_ifflags_cb(struct ethercom *); 119 120 void gem_statuschange(struct gem_softc *); 121 122 int gem_ser_mediachange(struct ifnet *); 123 void gem_ser_mediastatus(struct ifnet *, struct ifmediareq *); 124 125 static void gem_partial_detach(struct gem_softc *, enum gem_attach_stage); 126 127 struct mbuf *gem_get(struct gem_softc *, int, int); 128 int gem_put(struct gem_softc *, int, struct mbuf *); 129 void gem_read(struct gem_softc *, int, int); 130 int gem_pint(struct gem_softc *); 131 int gem_eint(struct gem_softc *, u_int); 132 int gem_rint(struct gem_softc *); 133 int gem_tint(struct gem_softc *); 134 void gem_power(int, void *); 135 136 #ifdef GEM_DEBUG 137 static void gem_txsoft_print(const struct gem_softc *, int, int); 138 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 139 printf x 140 #else 141 #define DPRINTF(sc, x) /* nothing */ 142 #endif 143 144 #define ETHER_MIN_TX (ETHERMIN + sizeof(struct ether_header)) 145 146 int 147 gem_detach(struct gem_softc *sc, int flags) 148 { 149 int i; 150 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 151 bus_space_tag_t t = sc->sc_bustag; 152 bus_space_handle_t h = sc->sc_h1; 153 154 /* 155 * Free any resources we've allocated during the attach. 156 * Do this in reverse order and fall through. 157 */ 158 switch (sc->sc_att_stage) { 159 case GEM_ATT_BACKEND_2: 160 case GEM_ATT_BACKEND_1: 161 case GEM_ATT_FINISHED: 162 bus_space_write_4(t, h, GEM_INTMASK, ~(uint32_t)0); 163 gem_stop(&sc->sc_ethercom.ec_if, 1); 164 165 #ifdef GEM_COUNTERS 166 for (i = __arraycount(sc->sc_ev_rxhist); --i >= 0; ) 167 evcnt_detach(&sc->sc_ev_rxhist[i]); 168 evcnt_detach(&sc->sc_ev_rxnobuf); 169 evcnt_detach(&sc->sc_ev_rxfull); 170 evcnt_detach(&sc->sc_ev_rxint); 171 evcnt_detach(&sc->sc_ev_txint); 172 #endif 173 evcnt_detach(&sc->sc_ev_intr); 174 175 rnd_detach_source(&sc->rnd_source); 176 ether_ifdetach(ifp); 177 if_detach(ifp); 178 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 179 180 callout_destroy(&sc->sc_tick_ch); 181 callout_destroy(&sc->sc_rx_watchdog); 182 183 /*FALLTHROUGH*/ 184 case GEM_ATT_MII: 185 sc->sc_att_stage = GEM_ATT_MII; 186 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 187 /*FALLTHROUGH*/ 188 case GEM_ATT_7: 189 for (i = 0; i < GEM_NRXDESC; i++) { 190 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 191 bus_dmamap_destroy(sc->sc_dmatag, 192 sc->sc_rxsoft[i].rxs_dmamap); 193 } 194 /*FALLTHROUGH*/ 195 case GEM_ATT_6: 196 for (i = 0; i < GEM_TXQUEUELEN; i++) { 197 if (sc->sc_txsoft[i].txs_dmamap != NULL) 198 bus_dmamap_destroy(sc->sc_dmatag, 199 sc->sc_txsoft[i].txs_dmamap); 200 } 201 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 202 /*FALLTHROUGH*/ 203 case GEM_ATT_5: 204 bus_dmamap_unload(sc->sc_dmatag, sc->sc_nulldmamap); 205 /*FALLTHROUGH*/ 206 case GEM_ATT_4: 207 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_nulldmamap); 208 /*FALLTHROUGH*/ 209 case GEM_ATT_3: 210 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 211 /*FALLTHROUGH*/ 212 case GEM_ATT_2: 213 bus_dmamem_unmap(sc->sc_dmatag, sc->sc_control_data, 214 sizeof(struct gem_control_data)); 215 /*FALLTHROUGH*/ 216 case GEM_ATT_1: 217 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 218 /*FALLTHROUGH*/ 219 case GEM_ATT_0: 220 sc->sc_att_stage = GEM_ATT_0; 221 /*FALLTHROUGH*/ 222 case GEM_ATT_BACKEND_0: 223 break; 224 } 225 return 0; 226 } 227 228 static void 229 gem_partial_detach(struct gem_softc *sc, enum gem_attach_stage stage) 230 { 231 cfattach_t ca = device_cfattach(sc->sc_dev); 232 233 sc->sc_att_stage = stage; 234 (*ca->ca_detach)(sc->sc_dev, 0); 235 } 236 237 /* 238 * gem_attach: 239 * 240 * Attach a Gem interface to the system. 241 */ 242 void 243 gem_attach(struct gem_softc *sc, const uint8_t *enaddr) 244 { 245 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 246 struct mii_data *mii = &sc->sc_mii; 247 bus_space_tag_t t = sc->sc_bustag; 248 bus_space_handle_t h = sc->sc_h1; 249 struct ifmedia_entry *ifm; 250 int i, error, phyaddr; 251 uint32_t v; 252 char *nullbuf; 253 254 /* Make sure the chip is stopped. */ 255 ifp->if_softc = sc; 256 gem_reset(sc); 257 258 /* 259 * Allocate the control data structures, and create and load the 260 * DMA map for it. gem_control_data is 9216 bytes, we have space for 261 * the padding buffer in the bus_dmamem_alloc()'d memory. 262 */ 263 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 264 sizeof(struct gem_control_data) + ETHER_MIN_TX, PAGE_SIZE, 265 0, &sc->sc_cdseg, 1, &sc->sc_cdnseg, 0)) != 0) { 266 aprint_error_dev(sc->sc_dev, 267 "unable to allocate control data, error = %d\n", 268 error); 269 gem_partial_detach(sc, GEM_ATT_0); 270 return; 271 } 272 273 /* XXX should map this in with correct endianness */ 274 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg, 275 sizeof(struct gem_control_data), (void **)&sc->sc_control_data, 276 BUS_DMA_COHERENT)) != 0) { 277 aprint_error_dev(sc->sc_dev, 278 "unable to map control data, error = %d\n", error); 279 gem_partial_detach(sc, GEM_ATT_1); 280 return; 281 } 282 283 nullbuf = 284 (char *)sc->sc_control_data + sizeof(struct gem_control_data); 285 286 if ((error = bus_dmamap_create(sc->sc_dmatag, 287 sizeof(struct gem_control_data), 1, 288 sizeof(struct gem_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 289 aprint_error_dev(sc->sc_dev, 290 "unable to create control data DMA map, error = %d\n", 291 error); 292 gem_partial_detach(sc, GEM_ATT_2); 293 return; 294 } 295 296 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 297 sc->sc_control_data, sizeof(struct gem_control_data), NULL, 298 0)) != 0) { 299 aprint_error_dev(sc->sc_dev, 300 "unable to load control data DMA map, error = %d\n", 301 error); 302 gem_partial_detach(sc, GEM_ATT_3); 303 return; 304 } 305 306 memset(nullbuf, 0, ETHER_MIN_TX); 307 if ((error = bus_dmamap_create(sc->sc_dmatag, 308 ETHER_MIN_TX, 1, ETHER_MIN_TX, 0, 0, &sc->sc_nulldmamap)) != 0) { 309 aprint_error_dev(sc->sc_dev, 310 "unable to create padding DMA map, error = %d\n", error); 311 gem_partial_detach(sc, GEM_ATT_4); 312 return; 313 } 314 315 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_nulldmamap, 316 nullbuf, ETHER_MIN_TX, NULL, 0)) != 0) { 317 aprint_error_dev(sc->sc_dev, 318 "unable to load padding DMA map, error = %d\n", error); 319 gem_partial_detach(sc, GEM_ATT_5); 320 return; 321 } 322 323 bus_dmamap_sync(sc->sc_dmatag, sc->sc_nulldmamap, 0, ETHER_MIN_TX, 324 BUS_DMASYNC_PREWRITE); 325 326 /* 327 * Initialize the transmit job descriptors. 328 */ 329 SIMPLEQ_INIT(&sc->sc_txfreeq); 330 SIMPLEQ_INIT(&sc->sc_txdirtyq); 331 332 /* 333 * Create the transmit buffer DMA maps. 334 */ 335 for (i = 0; i < GEM_TXQUEUELEN; i++) { 336 struct gem_txsoft *txs; 337 338 txs = &sc->sc_txsoft[i]; 339 txs->txs_mbuf = NULL; 340 if ((error = bus_dmamap_create(sc->sc_dmatag, 341 ETHER_MAX_LEN_JUMBO, GEM_NTXSEGS, 342 ETHER_MAX_LEN_JUMBO, 0, 0, 343 &txs->txs_dmamap)) != 0) { 344 aprint_error_dev(sc->sc_dev, 345 "unable to create tx DMA map %d, error = %d\n", 346 i, error); 347 gem_partial_detach(sc, GEM_ATT_6); 348 return; 349 } 350 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 351 } 352 353 /* 354 * Create the receive buffer DMA maps. 355 */ 356 for (i = 0; i < GEM_NRXDESC; i++) { 357 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, 358 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 359 aprint_error_dev(sc->sc_dev, 360 "unable to create rx DMA map %d, error = %d\n", 361 i, error); 362 gem_partial_detach(sc, GEM_ATT_7); 363 return; 364 } 365 sc->sc_rxsoft[i].rxs_mbuf = NULL; 366 } 367 368 /* Initialize ifmedia structures and MII info */ 369 mii->mii_ifp = ifp; 370 mii->mii_readreg = gem_mii_readreg; 371 mii->mii_writereg = gem_mii_writereg; 372 mii->mii_statchg = gem_mii_statchg; 373 374 sc->sc_ethercom.ec_mii = mii; 375 376 /* 377 * Initialization based on `GEM Gigabit Ethernet ASIC Specification' 378 * Section 3.2.1 `Initialization Sequence'. 379 * However, we can't assume SERDES or Serialink if neither 380 * GEM_MIF_CONFIG_MDI0 nor GEM_MIF_CONFIG_MDI1 are set 381 * being set, as both are set on Sun X1141A (with SERDES). So, 382 * we rely on our bus attachment setting GEM_SERDES or GEM_SERIAL. 383 * Also, for variants that report 2 PHY's, we prefer the external 384 * PHY over the internal PHY, so we look for that first. 385 */ 386 gem_mifinit(sc); 387 388 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) { 389 ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange, 390 ether_mediastatus); 391 /* Look for external PHY */ 392 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) { 393 sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL; 394 bus_space_write_4(t, h, GEM_MIF_CONFIG, 395 sc->sc_mif_config); 396 switch (sc->sc_variant) { 397 case GEM_SUN_ERI: 398 phyaddr = GEM_PHYAD_EXTERNAL; 399 break; 400 default: 401 phyaddr = MII_PHY_ANY; 402 break; 403 } 404 mii_attach(sc->sc_dev, mii, 0xffffffff, phyaddr, 405 MII_OFFSET_ANY, MIIF_FORCEANEG); 406 } 407 #ifdef GEM_DEBUG 408 else 409 aprint_debug_dev(sc->sc_dev, "using external PHY\n"); 410 #endif 411 /* Look for internal PHY if no external PHY was found */ 412 if (LIST_EMPTY(&mii->mii_phys) && 413 ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI0) || 414 (sc->sc_variant == GEM_APPLE_K2_GMAC))) { 415 sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL; 416 bus_space_write_4(t, h, GEM_MIF_CONFIG, 417 sc->sc_mif_config); 418 switch (sc->sc_variant) { 419 case GEM_SUN_ERI: 420 case GEM_APPLE_K2_GMAC: 421 phyaddr = GEM_PHYAD_INTERNAL; 422 break; 423 case GEM_APPLE_GMAC: 424 phyaddr = GEM_PHYAD_EXTERNAL; 425 break; 426 default: 427 phyaddr = MII_PHY_ANY; 428 break; 429 } 430 mii_attach(sc->sc_dev, mii, 0xffffffff, phyaddr, 431 MII_OFFSET_ANY, MIIF_FORCEANEG); 432 #ifdef GEM_DEBUG 433 if (!LIST_EMPTY(&mii->mii_phys)) 434 aprint_debug_dev(sc->sc_dev, 435 "using internal PHY\n"); 436 #endif 437 } 438 if (LIST_EMPTY(&mii->mii_phys)) { 439 /* No PHY attached */ 440 aprint_error_dev(sc->sc_dev, 441 "PHY probe failed\n"); 442 gem_partial_detach(sc, GEM_ATT_MII); 443 return; 444 } else { 445 struct mii_softc *child; 446 447 /* 448 * Walk along the list of attached MII devices and 449 * establish an `MII instance' to `PHY number' 450 * mapping. 451 */ 452 LIST_FOREACH(child, &mii->mii_phys, mii_list) { 453 /* 454 * Note: we support just one PHY: the internal 455 * or external MII is already selected for us 456 * by the GEM_MIF_CONFIG register. 457 */ 458 if (child->mii_phy > 1 || child->mii_inst > 0) { 459 aprint_error_dev(sc->sc_dev, 460 "cannot accommodate MII device" 461 " %s at PHY %d, instance %d\n", 462 device_xname(child->mii_dev), 463 child->mii_phy, child->mii_inst); 464 continue; 465 } 466 sc->sc_phys[child->mii_inst] = child->mii_phy; 467 } 468 469 if (sc->sc_variant != GEM_SUN_ERI) 470 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 471 GEM_MII_DATAPATH_MII); 472 473 /* 474 * XXX - we can really do the following ONLY if the 475 * PHY indeed has the auto negotiation capability!! 476 */ 477 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 478 } 479 } else { 480 ifmedia_init(&mii->mii_media, IFM_IMASK, gem_ser_mediachange, 481 gem_ser_mediastatus); 482 /* SERDES or Serialink */ 483 if (sc->sc_flags & GEM_SERDES) { 484 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 485 GEM_MII_DATAPATH_SERDES); 486 } else { 487 sc->sc_flags |= GEM_SERIAL; 488 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 489 GEM_MII_DATAPATH_SERIAL); 490 } 491 492 aprint_normal_dev(sc->sc_dev, "using external PCS %s: ", 493 sc->sc_flags & GEM_SERDES ? "SERDES" : "Serialink"); 494 495 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO, 0, NULL); 496 /* Check for FDX and HDX capabilities */ 497 sc->sc_mii_anar = bus_space_read_4(t, h, GEM_MII_ANAR); 498 if (sc->sc_mii_anar & GEM_MII_ANEG_FUL_DUPLX) { 499 ifmedia_add(&sc->sc_mii.mii_media, 500 IFM_ETHER|IFM_1000_SX|IFM_MANUAL|IFM_FDX, 0, NULL); 501 aprint_normal("1000baseSX-FDX, "); 502 } 503 if (sc->sc_mii_anar & GEM_MII_ANEG_HLF_DUPLX) { 504 ifmedia_add(&sc->sc_mii.mii_media, 505 IFM_ETHER|IFM_1000_SX|IFM_MANUAL|IFM_HDX, 0, NULL); 506 aprint_normal("1000baseSX-HDX, "); 507 } 508 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 509 sc->sc_mii_media = IFM_AUTO; 510 aprint_normal("auto\n"); 511 512 gem_pcs_stop(sc, 1); 513 } 514 515 /* 516 * From this point forward, the attachment cannot fail. A failure 517 * before this point releases all resources that may have been 518 * allocated. 519 */ 520 521 /* Announce ourselves. */ 522 aprint_normal_dev(sc->sc_dev, "Ethernet address %s", 523 ether_sprintf(enaddr)); 524 525 /* Get RX FIFO size */ 526 sc->sc_rxfifosize = 64 * 527 bus_space_read_4(t, h, GEM_RX_FIFO_SIZE); 528 aprint_normal(", %uKB RX fifo", sc->sc_rxfifosize / 1024); 529 530 /* Get TX FIFO size */ 531 v = bus_space_read_4(t, h, GEM_TX_FIFO_SIZE); 532 aprint_normal(", %uKB TX fifo\n", v / 16); 533 534 /* Initialize ifnet structure. */ 535 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 536 ifp->if_softc = sc; 537 ifp->if_flags = 538 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 539 sc->sc_if_flags = ifp->if_flags; 540 #if 0 541 /* 542 * The GEM hardware supports basic TCP checksum offloading only. 543 * Several (all?) revisions (Sun rev. 01 and Apple rev. 00 and 80) 544 * have bugs in the receive checksum, so don't enable it for now. 545 */ 546 if ((GEM_IS_SUN(sc) && sc->sc_chiprev != 1) || 547 (GEM_IS_APPLE(sc) && 548 (sc->sc_chiprev != 0 && sc->sc_chiprev != 0x80))) 549 ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Rx; 550 #endif 551 ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Tx; 552 ifp->if_start = gem_start; 553 ifp->if_ioctl = gem_ioctl; 554 ifp->if_watchdog = gem_watchdog; 555 ifp->if_stop = gem_stop; 556 ifp->if_init = gem_init; 557 IFQ_SET_READY(&ifp->if_snd); 558 559 /* 560 * If we support GigE media, we support jumbo frames too. 561 * Unless we are Apple. 562 */ 563 TAILQ_FOREACH(ifm, &sc->sc_mii.mii_media.ifm_list, ifm_list) { 564 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_T || 565 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_SX || 566 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_LX || 567 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_CX) { 568 if (!GEM_IS_APPLE(sc)) 569 sc->sc_ethercom.ec_capabilities 570 |= ETHERCAP_JUMBO_MTU; 571 sc->sc_flags |= GEM_GIGABIT; 572 break; 573 } 574 } 575 576 /* claim 802.1q capability */ 577 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 578 579 /* Attach the interface. */ 580 if_attach(ifp); 581 if_deferred_start_init(ifp, NULL); 582 ether_ifattach(ifp, enaddr); 583 ether_set_ifflags_cb(&sc->sc_ethercom, gem_ifflags_cb); 584 585 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 586 RND_TYPE_NET, RND_FLAG_DEFAULT); 587 588 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, 589 NULL, device_xname(sc->sc_dev), "interrupts"); 590 #ifdef GEM_COUNTERS 591 evcnt_attach_dynamic(&sc->sc_ev_txint, EVCNT_TYPE_INTR, 592 &sc->sc_ev_intr, device_xname(sc->sc_dev), "tx interrupts"); 593 evcnt_attach_dynamic(&sc->sc_ev_rxint, EVCNT_TYPE_INTR, 594 &sc->sc_ev_intr, device_xname(sc->sc_dev), "rx interrupts"); 595 evcnt_attach_dynamic(&sc->sc_ev_rxfull, EVCNT_TYPE_INTR, 596 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx ring full"); 597 evcnt_attach_dynamic(&sc->sc_ev_rxnobuf, EVCNT_TYPE_INTR, 598 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx malloc failure"); 599 evcnt_attach_dynamic(&sc->sc_ev_rxhist[0], EVCNT_TYPE_INTR, 600 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 0desc"); 601 evcnt_attach_dynamic(&sc->sc_ev_rxhist[1], EVCNT_TYPE_INTR, 602 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 1desc"); 603 evcnt_attach_dynamic(&sc->sc_ev_rxhist[2], EVCNT_TYPE_INTR, 604 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 2desc"); 605 evcnt_attach_dynamic(&sc->sc_ev_rxhist[3], EVCNT_TYPE_INTR, 606 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 3desc"); 607 evcnt_attach_dynamic(&sc->sc_ev_rxhist[4], EVCNT_TYPE_INTR, 608 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >3desc"); 609 evcnt_attach_dynamic(&sc->sc_ev_rxhist[5], EVCNT_TYPE_INTR, 610 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >7desc"); 611 evcnt_attach_dynamic(&sc->sc_ev_rxhist[6], EVCNT_TYPE_INTR, 612 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >15desc"); 613 evcnt_attach_dynamic(&sc->sc_ev_rxhist[7], EVCNT_TYPE_INTR, 614 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >31desc"); 615 evcnt_attach_dynamic(&sc->sc_ev_rxhist[8], EVCNT_TYPE_INTR, 616 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >63desc"); 617 #endif 618 619 callout_init(&sc->sc_tick_ch, 0); 620 callout_init(&sc->sc_rx_watchdog, 0); 621 callout_setfunc(&sc->sc_rx_watchdog, gem_rx_watchdog, sc); 622 623 sc->sc_att_stage = GEM_ATT_FINISHED; 624 625 return; 626 } 627 628 void 629 gem_tick(void *arg) 630 { 631 struct gem_softc *sc = arg; 632 int s; 633 634 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) { 635 /* 636 * We have to reset everything if we failed to get a 637 * PCS interrupt. Restarting the callout is handled 638 * in gem_pcs_start(). 639 */ 640 gem_init(&sc->sc_ethercom.ec_if); 641 } else { 642 s = splnet(); 643 mii_tick(&sc->sc_mii); 644 splx(s); 645 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 646 } 647 } 648 649 static int 650 gem_bitwait(struct gem_softc *sc, bus_space_handle_t h, int r, uint32_t clr, 651 uint32_t set) 652 { 653 int i; 654 uint32_t reg; 655 656 for (i = TRIES; i--; DELAY(100)) { 657 reg = bus_space_read_4(sc->sc_bustag, h, r); 658 if ((reg & clr) == 0 && (reg & set) == set) 659 return (1); 660 } 661 return (0); 662 } 663 664 void 665 gem_reset(struct gem_softc *sc) 666 { 667 bus_space_tag_t t = sc->sc_bustag; 668 bus_space_handle_t h = sc->sc_h2; 669 int s; 670 671 s = splnet(); 672 DPRINTF(sc, ("%s: gem_reset\n", device_xname(sc->sc_dev))); 673 gem_reset_rx(sc); 674 gem_reset_tx(sc); 675 676 /* Do a full reset */ 677 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX|GEM_RESET_TX); 678 if (!gem_bitwait(sc, h, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0)) 679 aprint_error_dev(sc->sc_dev, "cannot reset device\n"); 680 splx(s); 681 } 682 683 684 /* 685 * gem_rxdrain: 686 * 687 * Drain the receive queue. 688 */ 689 static void 690 gem_rxdrain(struct gem_softc *sc) 691 { 692 struct gem_rxsoft *rxs; 693 int i; 694 695 for (i = 0; i < GEM_NRXDESC; i++) { 696 rxs = &sc->sc_rxsoft[i]; 697 if (rxs->rxs_mbuf != NULL) { 698 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 699 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 700 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 701 m_freem(rxs->rxs_mbuf); 702 rxs->rxs_mbuf = NULL; 703 } 704 } 705 } 706 707 /* 708 * Reset the whole thing. 709 */ 710 static void 711 gem_stop(struct ifnet *ifp, int disable) 712 { 713 struct gem_softc *sc = ifp->if_softc; 714 struct gem_txsoft *txs; 715 716 DPRINTF(sc, ("%s: gem_stop\n", device_xname(sc->sc_dev))); 717 718 callout_halt(&sc->sc_tick_ch, NULL); 719 callout_halt(&sc->sc_rx_watchdog, NULL); 720 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 721 gem_pcs_stop(sc, disable); 722 else 723 mii_down(&sc->sc_mii); 724 725 /* XXX - Should we reset these instead? */ 726 gem_disable_tx(sc); 727 gem_disable_rx(sc); 728 729 /* 730 * Release any queued transmit buffers. 731 */ 732 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 733 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 734 if (txs->txs_mbuf != NULL) { 735 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 0, 736 txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 737 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 738 m_freem(txs->txs_mbuf); 739 txs->txs_mbuf = NULL; 740 } 741 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 742 } 743 744 /* 745 * Mark the interface down and cancel the watchdog timer. 746 */ 747 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 748 sc->sc_if_flags = ifp->if_flags; 749 ifp->if_timer = 0; 750 751 if (disable) 752 gem_rxdrain(sc); 753 } 754 755 756 /* 757 * Reset the receiver 758 */ 759 int 760 gem_reset_rx(struct gem_softc *sc) 761 { 762 bus_space_tag_t t = sc->sc_bustag; 763 bus_space_handle_t h = sc->sc_h1, h2 = sc->sc_h2; 764 765 /* 766 * Resetting while DMA is in progress can cause a bus hang, so we 767 * disable DMA first. 768 */ 769 gem_disable_rx(sc); 770 bus_space_write_4(t, h, GEM_RX_CONFIG, 0); 771 bus_space_barrier(t, h, GEM_RX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 772 /* Wait till it finishes */ 773 if (!gem_bitwait(sc, h, GEM_RX_CONFIG, 1, 0)) 774 aprint_error_dev(sc->sc_dev, "cannot disable read dma\n"); 775 /* Wait 5ms extra. */ 776 delay(5000); 777 778 /* Finally, reset the ERX */ 779 bus_space_write_4(t, h2, GEM_RESET, GEM_RESET_RX); 780 bus_space_barrier(t, h, GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE); 781 /* Wait till it finishes */ 782 if (!gem_bitwait(sc, h2, GEM_RESET, GEM_RESET_RX, 0)) { 783 aprint_error_dev(sc->sc_dev, "cannot reset receiver\n"); 784 return (1); 785 } 786 return (0); 787 } 788 789 790 /* 791 * Reset the receiver DMA engine. 792 * 793 * Intended to be used in case of GEM_INTR_RX_TAG_ERR, GEM_MAC_RX_OVERFLOW 794 * etc in order to reset the receiver DMA engine only and not do a full 795 * reset which amongst others also downs the link and clears the FIFOs. 796 */ 797 static void 798 gem_reset_rxdma(struct gem_softc *sc) 799 { 800 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 801 bus_space_tag_t t = sc->sc_bustag; 802 bus_space_handle_t h = sc->sc_h1; 803 int i; 804 805 if (gem_reset_rx(sc) != 0) { 806 gem_init(ifp); 807 return; 808 } 809 for (i = 0; i < GEM_NRXDESC; i++) 810 if (sc->sc_rxsoft[i].rxs_mbuf != NULL) 811 GEM_UPDATE_RXDESC(sc, i); 812 sc->sc_rxptr = 0; 813 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE); 814 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD); 815 816 /* Reprogram Descriptor Ring Base Addresses */ 817 /* NOTE: we use only 32-bit DMA addresses here. */ 818 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0); 819 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 820 821 /* Redo ERX Configuration */ 822 gem_rx_common(sc); 823 824 /* Give the reciever a swift kick */ 825 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC - 4); 826 } 827 828 /* 829 * Common RX configuration for gem_init() and gem_reset_rxdma(). 830 */ 831 static void 832 gem_rx_common(struct gem_softc *sc) 833 { 834 bus_space_tag_t t = sc->sc_bustag; 835 bus_space_handle_t h = sc->sc_h1; 836 uint32_t v; 837 838 /* Encode Receive Descriptor ring size: four possible values */ 839 v = gem_ringsize(GEM_NRXDESC /*XXX*/); 840 841 /* Set receive h/w checksum offset */ 842 #ifdef INET 843 v |= (ETHER_HDR_LEN + sizeof(struct ip) + 844 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 845 ETHER_VLAN_ENCAP_LEN : 0)) << GEM_RX_CONFIG_CXM_START_SHFT; 846 #endif 847 848 /* Enable RX DMA */ 849 bus_space_write_4(t, h, GEM_RX_CONFIG, 850 v | (GEM_THRSH_1024 << GEM_RX_CONFIG_FIFO_THRS_SHIFT) | 851 (2 << GEM_RX_CONFIG_FBOFF_SHFT) | GEM_RX_CONFIG_RXDMA_EN); 852 853 /* 854 * The following value is for an OFF Threshold of about 3/4 full 855 * and an ON Threshold of 1/4 full. 856 */ 857 bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH, 858 (3 * sc->sc_rxfifosize / 256) | 859 ((sc->sc_rxfifosize / 256) << 12)); 860 bus_space_write_4(t, h, GEM_RX_BLANKING, 861 (6 << GEM_RX_BLANKING_TIME_SHIFT) | 8); 862 } 863 864 /* 865 * Reset the transmitter 866 */ 867 int 868 gem_reset_tx(struct gem_softc *sc) 869 { 870 bus_space_tag_t t = sc->sc_bustag; 871 bus_space_handle_t h = sc->sc_h1, h2 = sc->sc_h2; 872 873 /* 874 * Resetting while DMA is in progress can cause a bus hang, so we 875 * disable DMA first. 876 */ 877 gem_disable_tx(sc); 878 bus_space_write_4(t, h, GEM_TX_CONFIG, 0); 879 bus_space_barrier(t, h, GEM_TX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 880 /* Wait till it finishes */ 881 if (!gem_bitwait(sc, h, GEM_TX_CONFIG, 1, 0)) 882 aprint_error_dev(sc->sc_dev, "cannot disable read dma\n"); 883 /* Wait 5ms extra. */ 884 delay(5000); 885 886 /* Finally, reset the ETX */ 887 bus_space_write_4(t, h2, GEM_RESET, GEM_RESET_TX); 888 bus_space_barrier(t, h, GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE); 889 /* Wait till it finishes */ 890 if (!gem_bitwait(sc, h2, GEM_RESET, GEM_RESET_TX, 0)) { 891 aprint_error_dev(sc->sc_dev, "cannot reset receiver\n"); 892 return (1); 893 } 894 return (0); 895 } 896 897 /* 898 * disable receiver. 899 */ 900 int 901 gem_disable_rx(struct gem_softc *sc) 902 { 903 bus_space_tag_t t = sc->sc_bustag; 904 bus_space_handle_t h = sc->sc_h1; 905 uint32_t cfg; 906 907 /* Flip the enable bit */ 908 cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 909 cfg &= ~GEM_MAC_RX_ENABLE; 910 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg); 911 bus_space_barrier(t, h, GEM_MAC_RX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 912 /* Wait for it to finish */ 913 return (gem_bitwait(sc, h, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)); 914 } 915 916 /* 917 * disable transmitter. 918 */ 919 int 920 gem_disable_tx(struct gem_softc *sc) 921 { 922 bus_space_tag_t t = sc->sc_bustag; 923 bus_space_handle_t h = sc->sc_h1; 924 uint32_t cfg; 925 926 /* Flip the enable bit */ 927 cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG); 928 cfg &= ~GEM_MAC_TX_ENABLE; 929 bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg); 930 bus_space_barrier(t, h, GEM_MAC_TX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 931 /* Wait for it to finish */ 932 return (gem_bitwait(sc, h, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)); 933 } 934 935 /* 936 * Initialize interface. 937 */ 938 int 939 gem_meminit(struct gem_softc *sc) 940 { 941 struct gem_rxsoft *rxs; 942 int i, error; 943 944 /* 945 * Initialize the transmit descriptor ring. 946 */ 947 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 948 for (i = 0; i < GEM_NTXDESC; i++) { 949 sc->sc_txdescs[i].gd_flags = 0; 950 sc->sc_txdescs[i].gd_addr = 0; 951 } 952 GEM_CDTXSYNC(sc, 0, GEM_NTXDESC, 953 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 954 sc->sc_txfree = GEM_NTXDESC-1; 955 sc->sc_txnext = 0; 956 sc->sc_txwin = 0; 957 958 /* 959 * Initialize the receive descriptor and receive job 960 * descriptor rings. 961 */ 962 for (i = 0; i < GEM_NRXDESC; i++) { 963 rxs = &sc->sc_rxsoft[i]; 964 if (rxs->rxs_mbuf == NULL) { 965 if ((error = gem_add_rxbuf(sc, i)) != 0) { 966 aprint_error_dev(sc->sc_dev, 967 "unable to allocate or map rx " 968 "buffer %d, error = %d\n", 969 i, error); 970 /* 971 * XXX Should attempt to run with fewer receive 972 * XXX buffers instead of just failing. 973 */ 974 gem_rxdrain(sc); 975 return (1); 976 } 977 } else 978 GEM_INIT_RXDESC(sc, i); 979 } 980 sc->sc_rxptr = 0; 981 sc->sc_meminited = 1; 982 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE); 983 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD); 984 985 return (0); 986 } 987 988 static int 989 gem_ringsize(int sz) 990 { 991 switch (sz) { 992 case 32: 993 return GEM_RING_SZ_32; 994 case 64: 995 return GEM_RING_SZ_64; 996 case 128: 997 return GEM_RING_SZ_128; 998 case 256: 999 return GEM_RING_SZ_256; 1000 case 512: 1001 return GEM_RING_SZ_512; 1002 case 1024: 1003 return GEM_RING_SZ_1024; 1004 case 2048: 1005 return GEM_RING_SZ_2048; 1006 case 4096: 1007 return GEM_RING_SZ_4096; 1008 case 8192: 1009 return GEM_RING_SZ_8192; 1010 default: 1011 printf("gem: invalid Receive Descriptor ring size %d\n", sz); 1012 return GEM_RING_SZ_32; 1013 } 1014 } 1015 1016 1017 /* 1018 * Start PCS 1019 */ 1020 void 1021 gem_pcs_start(struct gem_softc *sc) 1022 { 1023 bus_space_tag_t t = sc->sc_bustag; 1024 bus_space_handle_t h = sc->sc_h1; 1025 uint32_t v; 1026 1027 #ifdef GEM_DEBUG 1028 aprint_debug_dev(sc->sc_dev, "gem_pcs_start()\n"); 1029 #endif 1030 1031 /* 1032 * Set up. We must disable the MII before modifying the 1033 * GEM_MII_ANAR register 1034 */ 1035 if (sc->sc_flags & GEM_SERDES) { 1036 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 1037 GEM_MII_DATAPATH_SERDES); 1038 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 1039 GEM_MII_SLINK_LOOPBACK); 1040 } else { 1041 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 1042 GEM_MII_DATAPATH_SERIAL); 1043 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 0); 1044 } 1045 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 1046 v = bus_space_read_4(t, h, GEM_MII_ANAR); 1047 v |= (GEM_MII_ANEG_SYM_PAUSE | GEM_MII_ANEG_ASYM_PAUSE); 1048 if (sc->sc_mii_media == IFM_AUTO) 1049 v |= (GEM_MII_ANEG_FUL_DUPLX | GEM_MII_ANEG_HLF_DUPLX); 1050 else if (sc->sc_mii_media == IFM_FDX) { 1051 v |= GEM_MII_ANEG_FUL_DUPLX; 1052 v &= ~GEM_MII_ANEG_HLF_DUPLX; 1053 } else if (sc->sc_mii_media == IFM_HDX) { 1054 v &= ~GEM_MII_ANEG_FUL_DUPLX; 1055 v |= GEM_MII_ANEG_HLF_DUPLX; 1056 } 1057 1058 /* Configure link. */ 1059 bus_space_write_4(t, h, GEM_MII_ANAR, v); 1060 bus_space_write_4(t, h, GEM_MII_CONTROL, 1061 GEM_MII_CONTROL_AUTONEG | GEM_MII_CONTROL_RAN); 1062 bus_space_write_4(t, h, GEM_MII_CONFIG, GEM_MII_CONFIG_ENABLE); 1063 gem_bitwait(sc, h, GEM_MII_STATUS, 0, GEM_MII_STATUS_ANEG_CPT); 1064 1065 /* Start the 10 second timer */ 1066 callout_reset(&sc->sc_tick_ch, hz * 10, gem_tick, sc); 1067 } 1068 1069 /* 1070 * Stop PCS 1071 */ 1072 void 1073 gem_pcs_stop(struct gem_softc *sc, int disable) 1074 { 1075 bus_space_tag_t t = sc->sc_bustag; 1076 bus_space_handle_t h = sc->sc_h1; 1077 1078 #ifdef GEM_DEBUG 1079 aprint_debug_dev(sc->sc_dev, "gem_pcs_stop()\n"); 1080 #endif 1081 1082 /* Tell link partner that we're going away */ 1083 bus_space_write_4(t, h, GEM_MII_ANAR, GEM_MII_ANEG_RF); 1084 1085 /* 1086 * Disable PCS MII. The documentation suggests that setting 1087 * GEM_MII_CONFIG_ENABLE to zero and then restarting auto- 1088 * negotiation will shut down the link. However, it appears 1089 * that we also need to unset the datapath mode. 1090 */ 1091 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 1092 bus_space_write_4(t, h, GEM_MII_CONTROL, 1093 GEM_MII_CONTROL_AUTONEG | GEM_MII_CONTROL_RAN); 1094 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, GEM_MII_DATAPATH_MII); 1095 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 1096 1097 if (disable) { 1098 if (sc->sc_flags & GEM_SERDES) 1099 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 1100 GEM_MII_SLINK_POWER_OFF); 1101 else 1102 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 1103 GEM_MII_SLINK_LOOPBACK | GEM_MII_SLINK_POWER_OFF); 1104 } 1105 1106 sc->sc_flags &= ~GEM_LINK; 1107 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_NONE; 1108 sc->sc_mii.mii_media_status = IFM_AVALID; 1109 } 1110 1111 1112 /* 1113 * Initialization of interface; set up initialization block 1114 * and transmit/receive descriptor rings. 1115 */ 1116 int 1117 gem_init(struct ifnet *ifp) 1118 { 1119 struct gem_softc *sc = ifp->if_softc; 1120 bus_space_tag_t t = sc->sc_bustag; 1121 bus_space_handle_t h = sc->sc_h1; 1122 int rc = 0, s; 1123 u_int max_frame_size; 1124 uint32_t v; 1125 1126 s = splnet(); 1127 1128 DPRINTF(sc, ("%s: gem_init: calling stop\n", device_xname(sc->sc_dev))); 1129 /* 1130 * Initialization sequence. The numbered steps below correspond 1131 * to the sequence outlined in section 6.3.5.1 in the Ethernet 1132 * Channel Engine manual (part of the PCIO manual). 1133 * See also the STP2002-STQ document from Sun Microsystems. 1134 */ 1135 1136 /* step 1 & 2. Reset the Ethernet Channel */ 1137 gem_stop(ifp, 0); 1138 gem_reset(sc); 1139 DPRINTF(sc, ("%s: gem_init: restarting\n", device_xname(sc->sc_dev))); 1140 1141 /* Re-initialize the MIF */ 1142 gem_mifinit(sc); 1143 1144 /* Set up correct datapath for non-SERDES/Serialink */ 1145 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0 && 1146 sc->sc_variant != GEM_SUN_ERI) 1147 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 1148 GEM_MII_DATAPATH_MII); 1149 1150 /* Call MI reset function if any */ 1151 if (sc->sc_hwreset) 1152 (*sc->sc_hwreset)(sc); 1153 1154 /* step 3. Setup data structures in host memory */ 1155 if (gem_meminit(sc) != 0) { 1156 splx(s); 1157 return 1; 1158 } 1159 1160 /* step 4. TX MAC registers & counters */ 1161 gem_init_regs(sc); 1162 max_frame_size = uimax(sc->sc_ethercom.ec_if.if_mtu, ETHERMTU); 1163 max_frame_size += ETHER_HDR_LEN + ETHER_CRC_LEN; 1164 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1165 max_frame_size += ETHER_VLAN_ENCAP_LEN; 1166 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 1167 max_frame_size|/* burst size */(0x2000<<16)); 1168 1169 /* step 5. RX MAC registers & counters */ 1170 gem_setladrf(sc); 1171 1172 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 1173 /* NOTE: we use only 32-bit DMA addresses here. */ 1174 bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 0); 1175 bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 1176 1177 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0); 1178 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 1179 1180 /* step 8. Global Configuration & Interrupt Mask */ 1181 gem_inten(sc); 1182 bus_space_write_4(t, h, GEM_MAC_RX_MASK, 1183 GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT); 1184 bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXX */ 1185 bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 1186 GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME); 1187 1188 /* step 9. ETX Configuration: use mostly default values */ 1189 1190 /* Enable TX DMA */ 1191 v = gem_ringsize(GEM_NTXDESC /*XXX*/); 1192 bus_space_write_4(t, h, GEM_TX_CONFIG, 1193 v | GEM_TX_CONFIG_TXDMA_EN | 1194 (((sc->sc_flags & GEM_GIGABIT ? 0x4FF : 0x100) << 10) & 1195 GEM_TX_CONFIG_TXFIFO_TH)); 1196 bus_space_write_4(t, h, GEM_TX_KICK, sc->sc_txnext); 1197 1198 /* step 10. ERX Configuration */ 1199 gem_rx_common(sc); 1200 1201 /* step 11. Configure Media */ 1202 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0 && 1203 (rc = mii_ifmedia_change(&sc->sc_mii)) != 0) 1204 goto out; 1205 1206 /* step 12. RX_MAC Configuration Register */ 1207 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 1208 v |= GEM_MAC_RX_ENABLE | GEM_MAC_RX_STRIP_CRC; 1209 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 1210 1211 /* step 14. Issue Transmit Pending command */ 1212 1213 /* Call MI initialization function if any */ 1214 if (sc->sc_hwinit) 1215 (*sc->sc_hwinit)(sc); 1216 1217 1218 /* step 15. Give the reciever a swift kick */ 1219 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4); 1220 1221 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 1222 /* Configure PCS */ 1223 gem_pcs_start(sc); 1224 else 1225 /* Start the one second timer. */ 1226 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 1227 1228 sc->sc_flags &= ~GEM_LINK; 1229 ifp->if_flags |= IFF_RUNNING; 1230 ifp->if_flags &= ~IFF_OACTIVE; 1231 ifp->if_timer = 0; 1232 sc->sc_if_flags = ifp->if_flags; 1233 out: 1234 splx(s); 1235 1236 return (0); 1237 } 1238 1239 void 1240 gem_init_regs(struct gem_softc *sc) 1241 { 1242 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1243 bus_space_tag_t t = sc->sc_bustag; 1244 bus_space_handle_t h = sc->sc_h1; 1245 const u_char *laddr = CLLADDR(ifp->if_sadl); 1246 uint32_t v; 1247 1248 /* These regs are not cleared on reset */ 1249 if (!sc->sc_inited) { 1250 1251 /* Load recommended values */ 1252 bus_space_write_4(t, h, GEM_MAC_IPG0, 0x00); 1253 bus_space_write_4(t, h, GEM_MAC_IPG1, 0x08); 1254 bus_space_write_4(t, h, GEM_MAC_IPG2, 0x04); 1255 1256 bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 1257 /* Max frame and max burst size */ 1258 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 1259 ETHER_MAX_LEN | (0x2000<<16)); 1260 1261 bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x07); 1262 bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x04); 1263 bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10); 1264 bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088); 1265 bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED, 1266 ((laddr[5]<<8)|laddr[4])&0x3ff); 1267 1268 /* Secondary MAC addr set to 0:0:0:0:0:0 */ 1269 bus_space_write_4(t, h, GEM_MAC_ADDR3, 0); 1270 bus_space_write_4(t, h, GEM_MAC_ADDR4, 0); 1271 bus_space_write_4(t, h, GEM_MAC_ADDR5, 0); 1272 1273 /* MAC control addr set to 01:80:c2:00:00:01 */ 1274 bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001); 1275 bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200); 1276 bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180); 1277 1278 /* MAC filter addr set to 0:0:0:0:0:0 */ 1279 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0); 1280 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0); 1281 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0); 1282 1283 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0); 1284 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0); 1285 1286 sc->sc_inited = 1; 1287 } 1288 1289 /* Counters need to be zeroed */ 1290 bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0); 1291 bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0); 1292 bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0); 1293 bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0); 1294 bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0); 1295 bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0); 1296 bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0); 1297 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 1298 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 1299 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 1300 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 1301 1302 /* Set XOFF PAUSE time. */ 1303 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); 1304 1305 /* 1306 * Set the internal arbitration to "infinite" bursts of the 1307 * maximum length of 31 * 64 bytes so DMA transfers aren't 1308 * split up in cache line size chunks. This greatly improves 1309 * especially RX performance. 1310 * Enable silicon bug workarounds for the Apple variants. 1311 */ 1312 bus_space_write_4(t, h, GEM_CONFIG, 1313 GEM_CONFIG_TXDMA_LIMIT | GEM_CONFIG_RXDMA_LIMIT | 1314 ((sc->sc_flags & GEM_PCI) ? 1315 GEM_CONFIG_BURST_INF : GEM_CONFIG_BURST_64) | (GEM_IS_APPLE(sc) ? 1316 GEM_CONFIG_RONPAULBIT | GEM_CONFIG_BUG2FIX : 0)); 1317 1318 /* 1319 * Set the station address. 1320 */ 1321 bus_space_write_4(t, h, GEM_MAC_ADDR0, (laddr[4]<<8)|laddr[5]); 1322 bus_space_write_4(t, h, GEM_MAC_ADDR1, (laddr[2]<<8)|laddr[3]); 1323 bus_space_write_4(t, h, GEM_MAC_ADDR2, (laddr[0]<<8)|laddr[1]); 1324 1325 /* 1326 * Enable MII outputs. Enable GMII if there is a gigabit PHY. 1327 */ 1328 sc->sc_mif_config = bus_space_read_4(t, h, GEM_MIF_CONFIG); 1329 v = GEM_MAC_XIF_TX_MII_ENA; 1330 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) { 1331 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) { 1332 v |= GEM_MAC_XIF_FDPLX_LED; 1333 if (sc->sc_flags & GEM_GIGABIT) 1334 v |= GEM_MAC_XIF_GMII_MODE; 1335 } 1336 } else { 1337 v |= GEM_MAC_XIF_GMII_MODE; 1338 } 1339 bus_space_write_4(t, h, GEM_MAC_XIF_CONFIG, v); 1340 } 1341 1342 #ifdef GEM_DEBUG 1343 static void 1344 gem_txsoft_print(const struct gem_softc *sc, int firstdesc, int lastdesc) 1345 { 1346 int i; 1347 1348 for (i = firstdesc;; i = GEM_NEXTTX(i)) { 1349 printf("descriptor %d:\t", i); 1350 printf("gd_flags: 0x%016" PRIx64 "\t", 1351 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags)); 1352 printf("gd_addr: 0x%016" PRIx64 "\n", 1353 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr)); 1354 if (i == lastdesc) 1355 break; 1356 } 1357 } 1358 #endif 1359 1360 static void 1361 gem_start(struct ifnet *ifp) 1362 { 1363 struct gem_softc *sc = ifp->if_softc; 1364 struct mbuf *m0, *m; 1365 struct gem_txsoft *txs; 1366 bus_dmamap_t dmamap; 1367 int error, firsttx, nexttx = -1, lasttx = -1, ofree, seg; 1368 #ifdef GEM_DEBUG 1369 int otxnext; 1370 #endif 1371 uint64_t flags = 0; 1372 1373 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1374 return; 1375 1376 /* 1377 * Remember the previous number of free descriptors and 1378 * the first descriptor we'll use. 1379 */ 1380 ofree = sc->sc_txfree; 1381 #ifdef GEM_DEBUG 1382 otxnext = sc->sc_txnext; 1383 #endif 1384 1385 DPRINTF(sc, ("%s: gem_start: txfree %d, txnext %d\n", 1386 device_xname(sc->sc_dev), ofree, otxnext)); 1387 1388 /* 1389 * Loop through the send queue, setting up transmit descriptors 1390 * until we drain the queue, or use up all available transmit 1391 * descriptors. 1392 */ 1393 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 1394 sc->sc_txfree != 0) { 1395 /* 1396 * Grab a packet off the queue. 1397 */ 1398 IFQ_POLL(&ifp->if_snd, m0); 1399 if (m0 == NULL) 1400 break; 1401 m = NULL; 1402 1403 dmamap = txs->txs_dmamap; 1404 1405 /* 1406 * Load the DMA map. If this fails, the packet either 1407 * didn't fit in the alloted number of segments, or we were 1408 * short on resources. In this case, we'll copy and try 1409 * again. 1410 */ 1411 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m0, 1412 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0 || 1413 (m0->m_pkthdr.len < ETHER_MIN_TX && 1414 dmamap->dm_nsegs == GEM_NTXSEGS)) { 1415 if (m0->m_pkthdr.len > MCLBYTES) { 1416 aprint_error_dev(sc->sc_dev, 1417 "unable to allocate jumbo Tx cluster\n"); 1418 IFQ_DEQUEUE(&ifp->if_snd, m0); 1419 m_freem(m0); 1420 continue; 1421 } 1422 MGETHDR(m, M_DONTWAIT, MT_DATA); 1423 if (m == NULL) { 1424 aprint_error_dev(sc->sc_dev, 1425 "unable to allocate Tx mbuf\n"); 1426 break; 1427 } 1428 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1429 if (m0->m_pkthdr.len > MHLEN) { 1430 MCLGET(m, M_DONTWAIT); 1431 if ((m->m_flags & M_EXT) == 0) { 1432 aprint_error_dev(sc->sc_dev, 1433 "unable to allocate Tx cluster\n"); 1434 m_freem(m); 1435 break; 1436 } 1437 } 1438 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1439 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1440 error = bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, 1441 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1442 if (error) { 1443 aprint_error_dev(sc->sc_dev, 1444 "unable to load Tx buffer, error = %d\n", 1445 error); 1446 break; 1447 } 1448 } 1449 1450 /* 1451 * Ensure we have enough descriptors free to describe 1452 * the packet. 1453 */ 1454 if (dmamap->dm_nsegs > ((m0->m_pkthdr.len < ETHER_MIN_TX) ? 1455 (sc->sc_txfree - 1) : sc->sc_txfree)) { 1456 /* 1457 * Not enough free descriptors to transmit this 1458 * packet. We haven't committed to anything yet, 1459 * so just unload the DMA map, put the packet 1460 * back on the queue, and punt. Notify the upper 1461 * layer that there are no more slots left. 1462 * 1463 * XXX We could allocate an mbuf and copy, but 1464 * XXX it is worth it? 1465 */ 1466 ifp->if_flags |= IFF_OACTIVE; 1467 sc->sc_if_flags = ifp->if_flags; 1468 bus_dmamap_unload(sc->sc_dmatag, dmamap); 1469 if (m != NULL) 1470 m_freem(m); 1471 break; 1472 } 1473 1474 IFQ_DEQUEUE(&ifp->if_snd, m0); 1475 if (m != NULL) { 1476 m_freem(m0); 1477 m0 = m; 1478 } 1479 1480 /* 1481 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1482 */ 1483 1484 /* Sync the DMA map. */ 1485 bus_dmamap_sync(sc->sc_dmatag, dmamap, 0, dmamap->dm_mapsize, 1486 BUS_DMASYNC_PREWRITE); 1487 1488 /* 1489 * Initialize the transmit descriptors. 1490 */ 1491 firsttx = sc->sc_txnext; 1492 for (nexttx = firsttx, seg = 0; 1493 seg < dmamap->dm_nsegs; 1494 seg++, nexttx = GEM_NEXTTX(nexttx)) { 1495 1496 /* 1497 * If this is the first descriptor we're 1498 * enqueueing, set the start of packet flag, 1499 * and the checksum stuff if we want the hardware 1500 * to do it. 1501 */ 1502 sc->sc_txdescs[nexttx].gd_addr = 1503 GEM_DMA_WRITE(sc, dmamap->dm_segs[seg].ds_addr); 1504 flags = dmamap->dm_segs[seg].ds_len & GEM_TD_BUFSIZE; 1505 if (nexttx == firsttx) { 1506 flags |= GEM_TD_START_OF_PACKET; 1507 if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) { 1508 sc->sc_txwin = 0; 1509 flags |= GEM_TD_INTERRUPT_ME; 1510 } 1511 1512 #ifdef INET 1513 /* h/w checksum */ 1514 if (ifp->if_csum_flags_tx & M_CSUM_TCPv4 && 1515 m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1516 struct ether_header *eh; 1517 uint16_t offset, start; 1518 1519 eh = mtod(m0, struct ether_header *); 1520 switch (ntohs(eh->ether_type)) { 1521 case ETHERTYPE_IP: 1522 start = ETHER_HDR_LEN; 1523 break; 1524 case ETHERTYPE_VLAN: 1525 start = ETHER_HDR_LEN + 1526 ETHER_VLAN_ENCAP_LEN; 1527 break; 1528 default: 1529 /* unsupported, drop it */ 1530 m_free(m0); 1531 continue; 1532 } 1533 start += M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 1534 offset = M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data) + start; 1535 flags |= (start << 1536 GEM_TD_CXSUM_STARTSHFT) | 1537 (offset << 1538 GEM_TD_CXSUM_STUFFSHFT) | 1539 GEM_TD_CXSUM_ENABLE; 1540 } 1541 #endif 1542 } 1543 if (seg == dmamap->dm_nsegs - 1) { 1544 flags |= GEM_TD_END_OF_PACKET; 1545 } else { 1546 /* last flag set outside of loop */ 1547 sc->sc_txdescs[nexttx].gd_flags = 1548 GEM_DMA_WRITE(sc, flags); 1549 } 1550 lasttx = nexttx; 1551 } 1552 if (m0->m_pkthdr.len < ETHER_MIN_TX) { 1553 /* add padding buffer at end of chain */ 1554 flags &= ~GEM_TD_END_OF_PACKET; 1555 sc->sc_txdescs[lasttx].gd_flags = 1556 GEM_DMA_WRITE(sc, flags); 1557 1558 sc->sc_txdescs[nexttx].gd_addr = 1559 GEM_DMA_WRITE(sc, 1560 sc->sc_nulldmamap->dm_segs[0].ds_addr); 1561 flags = ((ETHER_MIN_TX - m0->m_pkthdr.len) & 1562 GEM_TD_BUFSIZE) | GEM_TD_END_OF_PACKET; 1563 lasttx = nexttx; 1564 nexttx = GEM_NEXTTX(nexttx); 1565 seg++; 1566 } 1567 sc->sc_txdescs[lasttx].gd_flags = GEM_DMA_WRITE(sc, flags); 1568 1569 KASSERT(lasttx != -1); 1570 1571 /* 1572 * Store a pointer to the packet so we can free it later, 1573 * and remember what txdirty will be once the packet is 1574 * done. 1575 */ 1576 txs->txs_mbuf = m0; 1577 txs->txs_firstdesc = sc->sc_txnext; 1578 txs->txs_lastdesc = lasttx; 1579 txs->txs_ndescs = seg; 1580 1581 #ifdef GEM_DEBUG 1582 if (ifp->if_flags & IFF_DEBUG) { 1583 printf(" gem_start %p transmit chain:\n", txs); 1584 gem_txsoft_print(sc, txs->txs_firstdesc, 1585 txs->txs_lastdesc); 1586 } 1587 #endif 1588 1589 /* Sync the descriptors we're using. */ 1590 GEM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndescs, 1591 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1592 1593 /* Advance the tx pointer. */ 1594 sc->sc_txfree -= txs->txs_ndescs; 1595 sc->sc_txnext = nexttx; 1596 1597 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1598 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1599 1600 /* 1601 * Pass the packet to any BPF listeners. 1602 */ 1603 bpf_mtap(ifp, m0, BPF_D_OUT); 1604 } 1605 1606 if (txs == NULL || sc->sc_txfree == 0) { 1607 /* No more slots left; notify upper layer. */ 1608 ifp->if_flags |= IFF_OACTIVE; 1609 sc->sc_if_flags = ifp->if_flags; 1610 } 1611 1612 if (sc->sc_txfree != ofree) { 1613 DPRINTF(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 1614 device_xname(sc->sc_dev), lasttx, otxnext)); 1615 /* 1616 * The entire packet chain is set up. 1617 * Kick the transmitter. 1618 */ 1619 DPRINTF(sc, ("%s: gem_start: kicking tx %d\n", 1620 device_xname(sc->sc_dev), nexttx)); 1621 bus_space_write_4(sc->sc_bustag, sc->sc_h1, GEM_TX_KICK, 1622 sc->sc_txnext); 1623 1624 /* Set a watchdog timer in case the chip flakes out. */ 1625 ifp->if_timer = 5; 1626 DPRINTF(sc, ("%s: gem_start: watchdog %d\n", 1627 device_xname(sc->sc_dev), ifp->if_timer)); 1628 } 1629 } 1630 1631 /* 1632 * Transmit interrupt. 1633 */ 1634 int 1635 gem_tint(struct gem_softc *sc) 1636 { 1637 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1638 bus_space_tag_t t = sc->sc_bustag; 1639 bus_space_handle_t mac = sc->sc_h1; 1640 struct gem_txsoft *txs; 1641 int txlast; 1642 int progress = 0; 1643 uint32_t v; 1644 1645 DPRINTF(sc, ("%s: gem_tint\n", device_xname(sc->sc_dev))); 1646 1647 /* Unload collision counters ... */ 1648 v = bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) + 1649 bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT); 1650 ifp->if_collisions += v + 1651 bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) + 1652 bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT); 1653 ifp->if_oerrors += v; 1654 1655 /* ... then clear the hardware counters. */ 1656 bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0); 1657 bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0); 1658 bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0); 1659 bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0); 1660 1661 /* 1662 * Go through our Tx list and free mbufs for those 1663 * frames that have been transmitted. 1664 */ 1665 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1666 /* 1667 * In theory, we could harvest some descriptors before 1668 * the ring is empty, but that's a bit complicated. 1669 * 1670 * GEM_TX_COMPLETION points to the last descriptor 1671 * processed +1. 1672 * 1673 * Let's assume that the NIC writes back to the Tx 1674 * descriptors before it updates the completion 1675 * register. If the NIC has posted writes to the 1676 * Tx descriptors, PCI ordering requires that the 1677 * posted writes flush to RAM before the register-read 1678 * finishes. So let's read the completion register, 1679 * before syncing the descriptors, so that we 1680 * examine Tx descriptors that are at least as 1681 * current as the completion register. 1682 */ 1683 txlast = bus_space_read_4(t, mac, GEM_TX_COMPLETION); 1684 DPRINTF(sc, 1685 ("gem_tint: txs->txs_lastdesc = %d, txlast = %d\n", 1686 txs->txs_lastdesc, txlast)); 1687 if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1688 if (txlast >= txs->txs_firstdesc && 1689 txlast <= txs->txs_lastdesc) 1690 break; 1691 } else if (txlast >= txs->txs_firstdesc || 1692 txlast <= txs->txs_lastdesc) 1693 break; 1694 1695 GEM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndescs, 1696 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1697 1698 #ifdef GEM_DEBUG /* XXX DMA synchronization? */ 1699 if (ifp->if_flags & IFF_DEBUG) { 1700 printf(" txsoft %p transmit chain:\n", txs); 1701 gem_txsoft_print(sc, txs->txs_firstdesc, 1702 txs->txs_lastdesc); 1703 } 1704 #endif 1705 1706 1707 DPRINTF(sc, ("gem_tint: releasing a desc\n")); 1708 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1709 1710 sc->sc_txfree += txs->txs_ndescs; 1711 1712 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 1713 0, txs->txs_dmamap->dm_mapsize, 1714 BUS_DMASYNC_POSTWRITE); 1715 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 1716 if (txs->txs_mbuf != NULL) { 1717 m_freem(txs->txs_mbuf); 1718 txs->txs_mbuf = NULL; 1719 } 1720 1721 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1722 1723 ifp->if_opackets++; 1724 progress = 1; 1725 } 1726 1727 #if 0 1728 DPRINTF(sc, ("gem_tint: GEM_TX_STATE_MACHINE %x " 1729 "GEM_TX_DATA_PTR %" PRIx64 "GEM_TX_COMPLETION %" PRIx32 "\n", 1730 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_TX_STATE_MACHINE), 1731 ((uint64_t)bus_space_read_4(sc->sc_bustag, sc->sc_h1, 1732 GEM_TX_DATA_PTR_HI) << 32) | 1733 bus_space_read_4(sc->sc_bustag, sc->sc_h1, 1734 GEM_TX_DATA_PTR_LO), 1735 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_TX_COMPLETION))); 1736 #endif 1737 1738 if (progress) { 1739 if (sc->sc_txfree == GEM_NTXDESC - 1) 1740 sc->sc_txwin = 0; 1741 1742 /* Freed some descriptors, so reset IFF_OACTIVE and restart. */ 1743 ifp->if_flags &= ~IFF_OACTIVE; 1744 sc->sc_if_flags = ifp->if_flags; 1745 ifp->if_timer = SIMPLEQ_EMPTY(&sc->sc_txdirtyq) ? 0 : 5; 1746 if_schedule_deferred_start(ifp); 1747 } 1748 DPRINTF(sc, ("%s: gem_tint: watchdog %d\n", 1749 device_xname(sc->sc_dev), ifp->if_timer)); 1750 1751 return (1); 1752 } 1753 1754 /* 1755 * Receive interrupt. 1756 */ 1757 int 1758 gem_rint(struct gem_softc *sc) 1759 { 1760 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1761 bus_space_tag_t t = sc->sc_bustag; 1762 bus_space_handle_t h = sc->sc_h1; 1763 struct gem_rxsoft *rxs; 1764 struct mbuf *m; 1765 uint64_t rxstat; 1766 uint32_t rxcomp; 1767 int i, len, progress = 0; 1768 1769 DPRINTF(sc, ("%s: gem_rint\n", device_xname(sc->sc_dev))); 1770 1771 /* 1772 * Ignore spurious interrupt that sometimes occurs before 1773 * we are set up when we network boot. 1774 */ 1775 if (!sc->sc_meminited) 1776 return 1; 1777 1778 /* 1779 * Read the completion register once. This limits 1780 * how long the following loop can execute. 1781 */ 1782 rxcomp = bus_space_read_4(t, h, GEM_RX_COMPLETION); 1783 1784 /* 1785 * XXX Read the lastrx only once at the top for speed. 1786 */ 1787 DPRINTF(sc, ("gem_rint: sc->rxptr %d, complete %d\n", 1788 sc->sc_rxptr, rxcomp)); 1789 1790 /* 1791 * Go into the loop at least once. 1792 */ 1793 for (i = sc->sc_rxptr; i == sc->sc_rxptr || i != rxcomp; 1794 i = GEM_NEXTRX(i)) { 1795 rxs = &sc->sc_rxsoft[i]; 1796 1797 GEM_CDRXSYNC(sc, i, 1798 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1799 1800 rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags); 1801 1802 if (rxstat & GEM_RD_OWN) { 1803 GEM_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); 1804 /* 1805 * We have processed all of the receive buffers. 1806 */ 1807 break; 1808 } 1809 1810 progress++; 1811 1812 if (rxstat & GEM_RD_BAD_CRC) { 1813 ifp->if_ierrors++; 1814 aprint_error_dev(sc->sc_dev, 1815 "receive error: CRC error\n"); 1816 GEM_INIT_RXDESC(sc, i); 1817 continue; 1818 } 1819 1820 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1821 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1822 #ifdef GEM_DEBUG 1823 if (ifp->if_flags & IFF_DEBUG) { 1824 printf(" rxsoft %p descriptor %d: ", rxs, i); 1825 printf("gd_flags: 0x%016llx\t", (long long) 1826 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags)); 1827 printf("gd_addr: 0x%016llx\n", (long long) 1828 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr)); 1829 } 1830 #endif 1831 1832 /* No errors; receive the packet. */ 1833 len = GEM_RD_BUFLEN(rxstat); 1834 1835 /* 1836 * Allocate a new mbuf cluster. If that fails, we are 1837 * out of memory, and must drop the packet and recycle 1838 * the buffer that's already attached to this descriptor. 1839 */ 1840 m = rxs->rxs_mbuf; 1841 if (gem_add_rxbuf(sc, i) != 0) { 1842 GEM_COUNTER_INCR(sc, sc_ev_rxnobuf); 1843 ifp->if_ierrors++; 1844 aprint_error_dev(sc->sc_dev, 1845 "receive error: RX no buffer space\n"); 1846 GEM_INIT_RXDESC(sc, i); 1847 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1848 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1849 continue; 1850 } 1851 m->m_data += 2; /* We're already off by two */ 1852 1853 m_set_rcvif(m, ifp); 1854 m->m_pkthdr.len = m->m_len = len; 1855 1856 #ifdef INET 1857 /* hardware checksum */ 1858 if (ifp->if_csum_flags_rx & M_CSUM_TCPv4) { 1859 struct ether_header *eh; 1860 struct ip *ip; 1861 int32_t hlen, pktlen; 1862 1863 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1864 pktlen = m->m_pkthdr.len - ETHER_HDR_LEN - 1865 ETHER_VLAN_ENCAP_LEN; 1866 eh = (struct ether_header *) (mtod(m, char *) + 1867 ETHER_VLAN_ENCAP_LEN); 1868 } else { 1869 pktlen = m->m_pkthdr.len - ETHER_HDR_LEN; 1870 eh = mtod(m, struct ether_header *); 1871 } 1872 if (ntohs(eh->ether_type) != ETHERTYPE_IP) 1873 goto swcsum; 1874 ip = (struct ip *) ((char *)eh + ETHER_HDR_LEN); 1875 1876 /* IPv4 only */ 1877 if (ip->ip_v != IPVERSION) 1878 goto swcsum; 1879 1880 hlen = ip->ip_hl << 2; 1881 if (hlen < sizeof(struct ip)) 1882 goto swcsum; 1883 1884 /* 1885 * bail if too short, has random trailing garbage, 1886 * truncated, fragment, or has ethernet pad. 1887 */ 1888 if ((ntohs(ip->ip_len) < hlen) || 1889 (ntohs(ip->ip_len) != pktlen) || 1890 (ntohs(ip->ip_off) & (IP_MF | IP_OFFMASK))) 1891 goto swcsum; 1892 1893 switch (ip->ip_p) { 1894 case IPPROTO_TCP: 1895 if (! (ifp->if_csum_flags_rx & M_CSUM_TCPv4)) 1896 goto swcsum; 1897 if (pktlen < (hlen + sizeof(struct tcphdr))) 1898 goto swcsum; 1899 m->m_pkthdr.csum_flags = M_CSUM_TCPv4; 1900 break; 1901 case IPPROTO_UDP: 1902 /* FALLTHROUGH */ 1903 default: 1904 goto swcsum; 1905 } 1906 1907 /* the uncomplemented sum is expected */ 1908 m->m_pkthdr.csum_data = (~rxstat) & GEM_RD_CHECKSUM; 1909 1910 /* if the pkt had ip options, we have to deduct them */ 1911 if (hlen > sizeof(struct ip)) { 1912 uint16_t *opts; 1913 uint32_t optsum, temp; 1914 1915 optsum = 0; 1916 temp = hlen - sizeof(struct ip); 1917 opts = (uint16_t *) ((char *) ip + 1918 sizeof(struct ip)); 1919 1920 while (temp > 1) { 1921 optsum += ntohs(*opts++); 1922 temp -= 2; 1923 } 1924 while (optsum >> 16) 1925 optsum = (optsum >> 16) + 1926 (optsum & 0xffff); 1927 1928 /* Deduct ip opts sum from hwsum. */ 1929 m->m_pkthdr.csum_data += (uint16_t)~optsum; 1930 1931 while (m->m_pkthdr.csum_data >> 16) 1932 m->m_pkthdr.csum_data = 1933 (m->m_pkthdr.csum_data >> 16) + 1934 (m->m_pkthdr.csum_data & 1935 0xffff); 1936 } 1937 1938 m->m_pkthdr.csum_flags |= M_CSUM_DATA | 1939 M_CSUM_NO_PSEUDOHDR; 1940 } else 1941 swcsum: 1942 m->m_pkthdr.csum_flags = 0; 1943 #endif 1944 /* Pass it on. */ 1945 if_percpuq_enqueue(ifp->if_percpuq, m); 1946 } 1947 1948 if (progress) { 1949 /* Update the receive pointer. */ 1950 if (i == sc->sc_rxptr) { 1951 GEM_COUNTER_INCR(sc, sc_ev_rxfull); 1952 #ifdef GEM_DEBUG 1953 if (ifp->if_flags & IFF_DEBUG) 1954 printf("%s: rint: ring wrap\n", 1955 device_xname(sc->sc_dev)); 1956 #endif 1957 } 1958 sc->sc_rxptr = i; 1959 bus_space_write_4(t, h, GEM_RX_KICK, GEM_PREVRX(i)); 1960 } 1961 #ifdef GEM_COUNTERS 1962 if (progress <= 4) { 1963 GEM_COUNTER_INCR(sc, sc_ev_rxhist[progress]); 1964 } else if (progress < 32) { 1965 if (progress < 16) 1966 GEM_COUNTER_INCR(sc, sc_ev_rxhist[5]); 1967 else 1968 GEM_COUNTER_INCR(sc, sc_ev_rxhist[6]); 1969 1970 } else { 1971 if (progress < 64) 1972 GEM_COUNTER_INCR(sc, sc_ev_rxhist[7]); 1973 else 1974 GEM_COUNTER_INCR(sc, sc_ev_rxhist[8]); 1975 } 1976 #endif 1977 1978 DPRINTF(sc, ("gem_rint: done sc->rxptr %d, complete %d\n", 1979 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION))); 1980 1981 /* Read error counters ... */ 1982 ifp->if_ierrors += 1983 bus_space_read_4(t, h, GEM_MAC_RX_LEN_ERR_CNT) + 1984 bus_space_read_4(t, h, GEM_MAC_RX_ALIGN_ERR) + 1985 bus_space_read_4(t, h, GEM_MAC_RX_CRC_ERR_CNT) + 1986 bus_space_read_4(t, h, GEM_MAC_RX_CODE_VIOL); 1987 1988 /* ... then clear the hardware counters. */ 1989 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 1990 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 1991 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 1992 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 1993 1994 return (1); 1995 } 1996 1997 1998 /* 1999 * gem_add_rxbuf: 2000 * 2001 * Add a receive buffer to the indicated descriptor. 2002 */ 2003 int 2004 gem_add_rxbuf(struct gem_softc *sc, int idx) 2005 { 2006 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2007 struct mbuf *m; 2008 int error; 2009 2010 MGETHDR(m, M_DONTWAIT, MT_DATA); 2011 if (m == NULL) 2012 return (ENOBUFS); 2013 2014 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2015 MCLGET(m, M_DONTWAIT); 2016 if ((m->m_flags & M_EXT) == 0) { 2017 m_freem(m); 2018 return (ENOBUFS); 2019 } 2020 2021 #ifdef GEM_DEBUG 2022 /* bzero the packet to check DMA */ 2023 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 2024 #endif 2025 2026 if (rxs->rxs_mbuf != NULL) 2027 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 2028 2029 rxs->rxs_mbuf = m; 2030 2031 error = bus_dmamap_load(sc->sc_dmatag, rxs->rxs_dmamap, 2032 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2033 BUS_DMA_READ|BUS_DMA_NOWAIT); 2034 if (error) { 2035 aprint_error_dev(sc->sc_dev, 2036 "can't load rx DMA map %d, error = %d\n", idx, error); 2037 panic("gem_add_rxbuf"); /* XXX */ 2038 } 2039 2040 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 2041 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2042 2043 GEM_INIT_RXDESC(sc, idx); 2044 2045 return (0); 2046 } 2047 2048 2049 int 2050 gem_eint(struct gem_softc *sc, u_int status) 2051 { 2052 char bits[128]; 2053 uint32_t r, v; 2054 2055 if ((status & GEM_INTR_MIF) != 0) { 2056 printf("%s: XXXlink status changed\n", device_xname(sc->sc_dev)); 2057 return (1); 2058 } 2059 2060 if ((status & GEM_INTR_RX_TAG_ERR) != 0) { 2061 gem_reset_rxdma(sc); 2062 return (1); 2063 } 2064 2065 if (status & GEM_INTR_BERR) { 2066 if (sc->sc_flags & GEM_PCI) 2067 r = GEM_ERROR_STATUS; 2068 else 2069 r = GEM_SBUS_ERROR_STATUS; 2070 bus_space_read_4(sc->sc_bustag, sc->sc_h2, r); 2071 v = bus_space_read_4(sc->sc_bustag, sc->sc_h2, r); 2072 aprint_error_dev(sc->sc_dev, "bus error interrupt: 0x%02x\n", 2073 v); 2074 return (1); 2075 } 2076 snprintb(bits, sizeof(bits), GEM_INTR_BITS, status); 2077 printf("%s: status=%s\n", device_xname(sc->sc_dev), bits); 2078 2079 return (1); 2080 } 2081 2082 2083 /* 2084 * PCS interrupts. 2085 * We should receive these when the link status changes, but sometimes 2086 * we don't receive them for link up. We compensate for this in the 2087 * gem_tick() callout. 2088 */ 2089 int 2090 gem_pint(struct gem_softc *sc) 2091 { 2092 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2093 bus_space_tag_t t = sc->sc_bustag; 2094 bus_space_handle_t h = sc->sc_h1; 2095 uint32_t v, v2; 2096 2097 /* 2098 * Clear the PCS interrupt from GEM_STATUS. The PCS register is 2099 * latched, so we have to read it twice. There is only one bit in 2100 * use, so the value is meaningless. 2101 */ 2102 bus_space_read_4(t, h, GEM_MII_INTERRUP_STATUS); 2103 bus_space_read_4(t, h, GEM_MII_INTERRUP_STATUS); 2104 2105 if ((ifp->if_flags & IFF_UP) == 0) 2106 return 1; 2107 2108 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) 2109 return 1; 2110 2111 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2112 /* If we see remote fault, our link partner is probably going away */ 2113 if ((v & GEM_MII_STATUS_REM_FLT) != 0) { 2114 gem_bitwait(sc, h, GEM_MII_STATUS, GEM_MII_STATUS_REM_FLT, 0); 2115 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2116 /* Otherwise, we may need to wait after auto-negotiation completes */ 2117 } else if ((v & (GEM_MII_STATUS_LINK_STS | GEM_MII_STATUS_ANEG_CPT)) == 2118 GEM_MII_STATUS_ANEG_CPT) { 2119 gem_bitwait(sc, h, GEM_MII_STATUS, 0, GEM_MII_STATUS_LINK_STS); 2120 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2121 } 2122 if ((v & GEM_MII_STATUS_LINK_STS) != 0) { 2123 if (sc->sc_flags & GEM_LINK) { 2124 return 1; 2125 } 2126 callout_stop(&sc->sc_tick_ch); 2127 v = bus_space_read_4(t, h, GEM_MII_ANAR); 2128 v2 = bus_space_read_4(t, h, GEM_MII_ANLPAR); 2129 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_1000_SX; 2130 sc->sc_mii.mii_media_status = IFM_AVALID | IFM_ACTIVE; 2131 v &= v2; 2132 if (v & GEM_MII_ANEG_FUL_DUPLX) { 2133 sc->sc_mii.mii_media_active |= IFM_FDX; 2134 #ifdef GEM_DEBUG 2135 aprint_debug_dev(sc->sc_dev, "link up: full duplex\n"); 2136 #endif 2137 } else if (v & GEM_MII_ANEG_HLF_DUPLX) { 2138 sc->sc_mii.mii_media_active |= IFM_HDX; 2139 #ifdef GEM_DEBUG 2140 aprint_debug_dev(sc->sc_dev, "link up: half duplex\n"); 2141 #endif 2142 } else { 2143 #ifdef GEM_DEBUG 2144 aprint_debug_dev(sc->sc_dev, "duplex mismatch\n"); 2145 #endif 2146 } 2147 gem_statuschange(sc); 2148 } else { 2149 if ((sc->sc_flags & GEM_LINK) == 0) { 2150 return 1; 2151 } 2152 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_NONE; 2153 sc->sc_mii.mii_media_status = IFM_AVALID; 2154 #ifdef GEM_DEBUG 2155 aprint_debug_dev(sc->sc_dev, "link down\n"); 2156 #endif 2157 gem_statuschange(sc); 2158 2159 /* Start the 10 second timer */ 2160 callout_reset(&sc->sc_tick_ch, hz * 10, gem_tick, sc); 2161 } 2162 return 1; 2163 } 2164 2165 2166 2167 int 2168 gem_intr(void *v) 2169 { 2170 struct gem_softc *sc = v; 2171 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2172 bus_space_tag_t t = sc->sc_bustag; 2173 bus_space_handle_t h = sc->sc_h1; 2174 uint32_t status; 2175 int r = 0; 2176 #ifdef GEM_DEBUG 2177 char bits[128]; 2178 #endif 2179 2180 /* XXX We should probably mask out interrupts until we're done */ 2181 2182 sc->sc_ev_intr.ev_count++; 2183 2184 status = bus_space_read_4(t, h, GEM_STATUS); 2185 #ifdef GEM_DEBUG 2186 snprintb(bits, sizeof(bits), GEM_INTR_BITS, status); 2187 #endif 2188 DPRINTF(sc, ("%s: gem_intr: cplt 0x%x status %s\n", 2189 device_xname(sc->sc_dev), (status >> 19), bits)); 2190 2191 2192 if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0) 2193 r |= gem_eint(sc, status); 2194 2195 /* We don't bother with GEM_INTR_TX_DONE */ 2196 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) { 2197 GEM_COUNTER_INCR(sc, sc_ev_txint); 2198 r |= gem_tint(sc); 2199 } 2200 2201 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) { 2202 GEM_COUNTER_INCR(sc, sc_ev_rxint); 2203 r |= gem_rint(sc); 2204 } 2205 2206 /* We should eventually do more than just print out error stats. */ 2207 if (status & GEM_INTR_TX_MAC) { 2208 int txstat = bus_space_read_4(t, h, GEM_MAC_TX_STATUS); 2209 if (txstat & ~GEM_MAC_TX_XMIT_DONE) 2210 printf("%s: MAC tx fault, status %x\n", 2211 device_xname(sc->sc_dev), txstat); 2212 if (txstat & (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG)) 2213 gem_init(ifp); 2214 } 2215 if (status & GEM_INTR_RX_MAC) { 2216 int rxstat = bus_space_read_4(t, h, GEM_MAC_RX_STATUS); 2217 /* 2218 * At least with GEM_SUN_GEM and some GEM_SUN_ERI 2219 * revisions GEM_MAC_RX_OVERFLOW happen often due to a 2220 * silicon bug so handle them silently. So if we detect 2221 * an RX FIFO overflow, we fire off a timer, and check 2222 * whether we're still making progress by looking at the 2223 * RX FIFO write and read pointers. 2224 */ 2225 if (rxstat & GEM_MAC_RX_OVERFLOW) { 2226 ifp->if_ierrors++; 2227 aprint_error_dev(sc->sc_dev, 2228 "receive error: RX overflow sc->rxptr %d, complete %d\n", sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION)); 2229 sc->sc_rx_fifo_wr_ptr = 2230 bus_space_read_4(t, h, GEM_RX_FIFO_WR_PTR); 2231 sc->sc_rx_fifo_rd_ptr = 2232 bus_space_read_4(t, h, GEM_RX_FIFO_RD_PTR); 2233 callout_schedule(&sc->sc_rx_watchdog, 400); 2234 } else if (rxstat & ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT)) 2235 printf("%s: MAC rx fault, status 0x%02x\n", 2236 device_xname(sc->sc_dev), rxstat); 2237 } 2238 if (status & GEM_INTR_PCS) { 2239 r |= gem_pint(sc); 2240 } 2241 2242 /* Do we need to do anything with these? 2243 if ((status & GEM_MAC_CONTROL_STATUS) != 0) { 2244 status2 = bus_read_4(sc->sc_res[0], GEM_MAC_CONTROL_STATUS); 2245 if ((status2 & GEM_MAC_PAUSED) != 0) 2246 aprintf_debug_dev(sc->sc_dev, "PAUSE received (%d slots)\n", 2247 GEM_MAC_PAUSE_TIME(status2)); 2248 if ((status2 & GEM_MAC_PAUSE) != 0) 2249 aprintf_debug_dev(sc->sc_dev, "transited to PAUSE state\n"); 2250 if ((status2 & GEM_MAC_RESUME) != 0) 2251 aprintf_debug_dev(sc->sc_dev, "transited to non-PAUSE state\n"); 2252 } 2253 if ((status & GEM_INTR_MIF) != 0) 2254 aprintf_debug_dev(sc->sc_dev, "MIF interrupt\n"); 2255 */ 2256 rnd_add_uint32(&sc->rnd_source, status); 2257 return (r); 2258 } 2259 2260 void 2261 gem_rx_watchdog(void *arg) 2262 { 2263 struct gem_softc *sc = arg; 2264 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2265 bus_space_tag_t t = sc->sc_bustag; 2266 bus_space_handle_t h = sc->sc_h1; 2267 uint32_t rx_fifo_wr_ptr; 2268 uint32_t rx_fifo_rd_ptr; 2269 uint32_t state; 2270 2271 if ((ifp->if_flags & IFF_RUNNING) == 0) { 2272 aprint_error_dev(sc->sc_dev, "receiver not running\n"); 2273 return; 2274 } 2275 2276 rx_fifo_wr_ptr = bus_space_read_4(t, h, GEM_RX_FIFO_WR_PTR); 2277 rx_fifo_rd_ptr = bus_space_read_4(t, h, GEM_RX_FIFO_RD_PTR); 2278 state = bus_space_read_4(t, h, GEM_MAC_MAC_STATE); 2279 if ((state & GEM_MAC_STATE_OVERFLOW) == GEM_MAC_STATE_OVERFLOW && 2280 ((rx_fifo_wr_ptr == rx_fifo_rd_ptr) || 2281 ((sc->sc_rx_fifo_wr_ptr == rx_fifo_wr_ptr) && 2282 (sc->sc_rx_fifo_rd_ptr == rx_fifo_rd_ptr)))) 2283 { 2284 /* 2285 * The RX state machine is still in overflow state and 2286 * the RX FIFO write and read pointers seem to be 2287 * stuck. Whack the chip over the head to get things 2288 * going again. 2289 */ 2290 aprint_error_dev(sc->sc_dev, 2291 "receiver stuck in overflow, resetting\n"); 2292 gem_init(ifp); 2293 } else { 2294 if ((state & GEM_MAC_STATE_OVERFLOW) != GEM_MAC_STATE_OVERFLOW) { 2295 aprint_error_dev(sc->sc_dev, 2296 "rx_watchdog: not in overflow state: 0x%x\n", 2297 state); 2298 } 2299 if (rx_fifo_wr_ptr != rx_fifo_rd_ptr) { 2300 aprint_error_dev(sc->sc_dev, 2301 "rx_watchdog: wr & rd ptr different\n"); 2302 } 2303 if (sc->sc_rx_fifo_wr_ptr != rx_fifo_wr_ptr) { 2304 aprint_error_dev(sc->sc_dev, 2305 "rx_watchdog: wr pointer != saved\n"); 2306 } 2307 if (sc->sc_rx_fifo_rd_ptr != rx_fifo_rd_ptr) { 2308 aprint_error_dev(sc->sc_dev, 2309 "rx_watchdog: rd pointer != saved\n"); 2310 } 2311 aprint_error_dev(sc->sc_dev, "resetting anyway\n"); 2312 gem_init(ifp); 2313 } 2314 } 2315 2316 void 2317 gem_watchdog(struct ifnet *ifp) 2318 { 2319 struct gem_softc *sc = ifp->if_softc; 2320 2321 DPRINTF(sc, ("gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x " 2322 "GEM_MAC_RX_CONFIG %x\n", 2323 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_RX_CONFIG), 2324 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_MAC_RX_STATUS), 2325 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_MAC_RX_CONFIG))); 2326 2327 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 2328 ++ifp->if_oerrors; 2329 2330 /* Try to get more packets going. */ 2331 gem_init(ifp); 2332 gem_start(ifp); 2333 } 2334 2335 /* 2336 * Initialize the MII Management Interface 2337 */ 2338 void 2339 gem_mifinit(struct gem_softc *sc) 2340 { 2341 bus_space_tag_t t = sc->sc_bustag; 2342 bus_space_handle_t mif = sc->sc_h1; 2343 2344 /* Configure the MIF in frame mode */ 2345 sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 2346 sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA; 2347 bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config); 2348 } 2349 2350 /* 2351 * MII interface 2352 * 2353 * The GEM MII interface supports at least three different operating modes: 2354 * 2355 * Bitbang mode is implemented using data, clock and output enable registers. 2356 * 2357 * Frame mode is implemented by loading a complete frame into the frame 2358 * register and polling the valid bit for completion. 2359 * 2360 * Polling mode uses the frame register but completion is indicated by 2361 * an interrupt. 2362 * 2363 */ 2364 static int 2365 gem_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 2366 { 2367 struct gem_softc *sc = device_private(self); 2368 bus_space_tag_t t = sc->sc_bustag; 2369 bus_space_handle_t mif = sc->sc_h1; 2370 int n; 2371 uint32_t v; 2372 2373 #ifdef GEM_DEBUG1 2374 if (sc->sc_debug) 2375 printf("gem_mii_readreg: PHY %d reg %d\n", phy, reg); 2376 #endif 2377 2378 /* Construct the frame command */ 2379 v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) | 2380 GEM_MIF_FRAME_READ; 2381 2382 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 2383 for (n = 0; n < 100; n++) { 2384 DELAY(1); 2385 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 2386 if (v & GEM_MIF_FRAME_TA0) { 2387 *val = v & GEM_MIF_FRAME_DATA; 2388 return 0; 2389 } 2390 } 2391 2392 printf("%s: mii_read timeout\n", device_xname(sc->sc_dev)); 2393 return ETIMEDOUT; 2394 } 2395 2396 static int 2397 gem_mii_writereg(device_t self, int phy, int reg, uint16_t val) 2398 { 2399 struct gem_softc *sc = device_private(self); 2400 bus_space_tag_t t = sc->sc_bustag; 2401 bus_space_handle_t mif = sc->sc_h1; 2402 int n; 2403 uint32_t v; 2404 2405 #ifdef GEM_DEBUG1 2406 if (sc->sc_debug) 2407 printf("gem_mii_writereg: PHY %d reg %d val %x\n", 2408 phy, reg, val); 2409 #endif 2410 2411 /* Construct the frame command */ 2412 v = GEM_MIF_FRAME_WRITE | 2413 (phy << GEM_MIF_PHY_SHIFT) | 2414 (reg << GEM_MIF_REG_SHIFT) | 2415 (val & GEM_MIF_FRAME_DATA); 2416 2417 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 2418 for (n = 0; n < 100; n++) { 2419 DELAY(1); 2420 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 2421 if (v & GEM_MIF_FRAME_TA0) 2422 return 0; 2423 } 2424 2425 printf("%s: mii_write timeout\n", device_xname(sc->sc_dev)); 2426 return ETIMEDOUT; 2427 } 2428 2429 static void 2430 gem_mii_statchg(struct ifnet *ifp) 2431 { 2432 struct gem_softc *sc = ifp->if_softc; 2433 #ifdef GEM_DEBUG 2434 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 2435 #endif 2436 2437 #ifdef GEM_DEBUG 2438 if (sc->sc_debug) 2439 printf("gem_mii_statchg: status change: phy = %d\n", 2440 sc->sc_phys[instance]); 2441 #endif 2442 gem_statuschange(sc); 2443 } 2444 2445 /* 2446 * Common status change for gem_mii_statchg() and gem_pint() 2447 */ 2448 void 2449 gem_statuschange(struct gem_softc* sc) 2450 { 2451 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2452 bus_space_tag_t t = sc->sc_bustag; 2453 bus_space_handle_t mac = sc->sc_h1; 2454 int gigabit; 2455 uint32_t rxcfg, txcfg, v; 2456 2457 if ((sc->sc_mii.mii_media_status & IFM_ACTIVE) != 0 && 2458 IFM_SUBTYPE(sc->sc_mii.mii_media_active) != IFM_NONE) 2459 sc->sc_flags |= GEM_LINK; 2460 else 2461 sc->sc_flags &= ~GEM_LINK; 2462 2463 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 2464 gigabit = 1; 2465 else 2466 gigabit = 0; 2467 2468 /* 2469 * The configuration done here corresponds to the steps F) and 2470 * G) and as far as enabling of RX and TX MAC goes also step H) 2471 * of the initialization sequence outlined in section 3.2.1 of 2472 * the GEM Gigabit Ethernet ASIC Specification. 2473 */ 2474 2475 rxcfg = bus_space_read_4(t, mac, GEM_MAC_RX_CONFIG); 2476 rxcfg &= ~(GEM_MAC_RX_CARR_EXTEND | GEM_MAC_RX_ENABLE); 2477 txcfg = GEM_MAC_TX_ENA_IPG0 | GEM_MAC_TX_NGU | GEM_MAC_TX_NGU_LIMIT; 2478 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 2479 txcfg |= GEM_MAC_TX_IGN_CARRIER | GEM_MAC_TX_IGN_COLLIS; 2480 else if (gigabit) { 2481 rxcfg |= GEM_MAC_RX_CARR_EXTEND; 2482 txcfg |= GEM_MAC_RX_CARR_EXTEND; 2483 } 2484 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0); 2485 bus_space_barrier(t, mac, GEM_MAC_TX_CONFIG, 4, 2486 BUS_SPACE_BARRIER_WRITE); 2487 if (!gem_bitwait(sc, mac, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)) 2488 aprint_normal_dev(sc->sc_dev, "cannot disable TX MAC\n"); 2489 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, txcfg); 2490 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, 0); 2491 bus_space_barrier(t, mac, GEM_MAC_RX_CONFIG, 4, 2492 BUS_SPACE_BARRIER_WRITE); 2493 if (!gem_bitwait(sc, mac, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)) 2494 aprint_normal_dev(sc->sc_dev, "cannot disable RX MAC\n"); 2495 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, rxcfg); 2496 2497 v = bus_space_read_4(t, mac, GEM_MAC_CONTROL_CONFIG) & 2498 ~(GEM_MAC_CC_RX_PAUSE | GEM_MAC_CC_TX_PAUSE); 2499 bus_space_write_4(t, mac, GEM_MAC_CONTROL_CONFIG, v); 2500 2501 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) == 0 && 2502 gigabit != 0) 2503 bus_space_write_4(t, mac, GEM_MAC_SLOT_TIME, 2504 GEM_MAC_SLOT_TIME_CARR_EXTEND); 2505 else 2506 bus_space_write_4(t, mac, GEM_MAC_SLOT_TIME, 2507 GEM_MAC_SLOT_TIME_NORMAL); 2508 2509 /* XIF Configuration */ 2510 if (sc->sc_flags & GEM_LINK) 2511 v = GEM_MAC_XIF_LINK_LED; 2512 else 2513 v = 0; 2514 v |= GEM_MAC_XIF_TX_MII_ENA; 2515 2516 /* If an external transceiver is connected, enable its MII drivers */ 2517 sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG); 2518 if ((sc->sc_flags &(GEM_SERDES | GEM_SERIAL)) == 0) { 2519 if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) { 2520 if (gigabit) 2521 v |= GEM_MAC_XIF_GMII_MODE; 2522 else 2523 v &= ~GEM_MAC_XIF_GMII_MODE; 2524 } else 2525 /* Internal MII needs buf enable */ 2526 v |= GEM_MAC_XIF_MII_BUF_ENA; 2527 /* MII needs echo disable if half duplex. */ 2528 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 2529 /* turn on full duplex LED */ 2530 v |= GEM_MAC_XIF_FDPLX_LED; 2531 else 2532 /* half duplex -- disable echo */ 2533 v |= GEM_MAC_XIF_ECHO_DISABL; 2534 } else { 2535 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 2536 v |= GEM_MAC_XIF_FDPLX_LED; 2537 v |= GEM_MAC_XIF_GMII_MODE; 2538 } 2539 bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v); 2540 2541 if ((ifp->if_flags & IFF_RUNNING) != 0 && 2542 (sc->sc_flags & GEM_LINK) != 0) { 2543 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 2544 txcfg | GEM_MAC_TX_ENABLE); 2545 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, 2546 rxcfg | GEM_MAC_RX_ENABLE); 2547 } 2548 } 2549 2550 int 2551 gem_ser_mediachange(struct ifnet *ifp) 2552 { 2553 struct gem_softc *sc = ifp->if_softc; 2554 u_int s, t; 2555 2556 if (IFM_TYPE(sc->sc_mii.mii_media.ifm_media) != IFM_ETHER) 2557 return EINVAL; 2558 2559 s = IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media); 2560 if (s == IFM_AUTO) { 2561 if (sc->sc_mii_media != s) { 2562 #ifdef GEM_DEBUG 2563 aprint_debug_dev(sc->sc_dev, "setting media to auto\n"); 2564 #endif 2565 sc->sc_mii_media = s; 2566 if (ifp->if_flags & IFF_UP) { 2567 gem_pcs_stop(sc, 0); 2568 gem_pcs_start(sc); 2569 } 2570 } 2571 return 0; 2572 } 2573 if (s == IFM_1000_SX) { 2574 t = IFM_OPTIONS(sc->sc_mii.mii_media.ifm_media); 2575 if (t == IFM_FDX || t == IFM_HDX) { 2576 if (sc->sc_mii_media != t) { 2577 sc->sc_mii_media = t; 2578 #ifdef GEM_DEBUG 2579 aprint_debug_dev(sc->sc_dev, 2580 "setting media to 1000baseSX-%s\n", 2581 t == IFM_FDX ? "FDX" : "HDX"); 2582 #endif 2583 if (ifp->if_flags & IFF_UP) { 2584 gem_pcs_stop(sc, 0); 2585 gem_pcs_start(sc); 2586 } 2587 } 2588 return 0; 2589 } 2590 } 2591 return EINVAL; 2592 } 2593 2594 void 2595 gem_ser_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2596 { 2597 struct gem_softc *sc = ifp->if_softc; 2598 2599 if ((ifp->if_flags & IFF_UP) == 0) 2600 return; 2601 ifmr->ifm_active = sc->sc_mii.mii_media_active; 2602 ifmr->ifm_status = sc->sc_mii.mii_media_status; 2603 } 2604 2605 static int 2606 gem_ifflags_cb(struct ethercom *ec) 2607 { 2608 struct ifnet *ifp = &ec->ec_if; 2609 struct gem_softc *sc = ifp->if_softc; 2610 int change = ifp->if_flags ^ sc->sc_if_flags; 2611 2612 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 2613 return ENETRESET; 2614 else if ((change & IFF_PROMISC) != 0) 2615 gem_setladrf(sc); 2616 return 0; 2617 } 2618 2619 /* 2620 * Process an ioctl request. 2621 */ 2622 int 2623 gem_ioctl(struct ifnet *ifp, unsigned long cmd, void *data) 2624 { 2625 struct gem_softc *sc = ifp->if_softc; 2626 int s, error = 0; 2627 2628 s = splnet(); 2629 2630 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2631 error = 0; 2632 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 2633 ; 2634 else if (ifp->if_flags & IFF_RUNNING) { 2635 /* 2636 * Multicast list has changed; set the hardware filter 2637 * accordingly. 2638 */ 2639 gem_setladrf(sc); 2640 } 2641 } 2642 2643 /* Try to get things going again */ 2644 if (ifp->if_flags & IFF_UP) 2645 gem_start(ifp); 2646 splx(s); 2647 return (error); 2648 } 2649 2650 static void 2651 gem_inten(struct gem_softc *sc) 2652 { 2653 bus_space_tag_t t = sc->sc_bustag; 2654 bus_space_handle_t h = sc->sc_h1; 2655 uint32_t v; 2656 2657 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 2658 v = GEM_INTR_PCS; 2659 else 2660 v = GEM_INTR_MIF; 2661 bus_space_write_4(t, h, GEM_INTMASK, 2662 ~(GEM_INTR_TX_INTME | 2663 GEM_INTR_TX_EMPTY | 2664 GEM_INTR_TX_MAC | 2665 GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF| 2666 GEM_INTR_RX_TAG_ERR | GEM_INTR_MAC_CONTROL| 2667 GEM_INTR_BERR | v)); 2668 } 2669 2670 bool 2671 gem_resume(device_t self, const pmf_qual_t *qual) 2672 { 2673 struct gem_softc *sc = device_private(self); 2674 2675 gem_inten(sc); 2676 2677 return true; 2678 } 2679 2680 bool 2681 gem_suspend(device_t self, const pmf_qual_t *qual) 2682 { 2683 struct gem_softc *sc = device_private(self); 2684 bus_space_tag_t t = sc->sc_bustag; 2685 bus_space_handle_t h = sc->sc_h1; 2686 2687 bus_space_write_4(t, h, GEM_INTMASK, ~(uint32_t)0); 2688 2689 return true; 2690 } 2691 2692 bool 2693 gem_shutdown(device_t self, int howto) 2694 { 2695 struct gem_softc *sc = device_private(self); 2696 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2697 2698 gem_stop(ifp, 1); 2699 2700 return true; 2701 } 2702 2703 /* 2704 * Set up the logical address filter. 2705 */ 2706 void 2707 gem_setladrf(struct gem_softc *sc) 2708 { 2709 struct ethercom *ec = &sc->sc_ethercom; 2710 struct ifnet *ifp = &ec->ec_if; 2711 struct ether_multi *enm; 2712 struct ether_multistep step; 2713 bus_space_tag_t t = sc->sc_bustag; 2714 bus_space_handle_t h = sc->sc_h1; 2715 uint32_t crc; 2716 uint32_t hash[16]; 2717 uint32_t v; 2718 int i; 2719 2720 /* Get current RX configuration */ 2721 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 2722 2723 /* 2724 * Turn off promiscuous mode, promiscuous group mode (all multicast), 2725 * and hash filter. Depending on the case, the right bit will be 2726 * enabled. 2727 */ 2728 v &= ~(GEM_MAC_RX_PROMISCUOUS|GEM_MAC_RX_HASH_FILTER| 2729 GEM_MAC_RX_PROMISC_GRP); 2730 2731 if ((ifp->if_flags & IFF_PROMISC) != 0) { 2732 /* Turn on promiscuous mode */ 2733 v |= GEM_MAC_RX_PROMISCUOUS; 2734 ifp->if_flags |= IFF_ALLMULTI; 2735 goto chipit; 2736 } 2737 2738 /* 2739 * Set up multicast address filter by passing all multicast addresses 2740 * through a crc generator, and then using the high order 8 bits as an 2741 * index into the 256 bit logical address filter. The high order 4 2742 * bits selects the word, while the other 4 bits select the bit within 2743 * the word (where bit 0 is the MSB). 2744 */ 2745 2746 /* Clear hash table */ 2747 memset(hash, 0, sizeof(hash)); 2748 2749 ETHER_FIRST_MULTI(step, ec, enm); 2750 while (enm != NULL) { 2751 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2752 /* 2753 * We must listen to a range of multicast addresses. 2754 * For now, just accept all multicasts, rather than 2755 * trying to set only those filter bits needed to match 2756 * the range. (At this time, the only use of address 2757 * ranges is for IP multicast routing, for which the 2758 * range is big enough to require all bits set.) 2759 * XXX should use the address filters for this 2760 */ 2761 ifp->if_flags |= IFF_ALLMULTI; 2762 v |= GEM_MAC_RX_PROMISC_GRP; 2763 goto chipit; 2764 } 2765 2766 /* Get the LE CRC32 of the address */ 2767 crc = ether_crc32_le(enm->enm_addrlo, sizeof(enm->enm_addrlo)); 2768 2769 /* Just want the 8 most significant bits. */ 2770 crc >>= 24; 2771 2772 /* Set the corresponding bit in the filter. */ 2773 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 2774 2775 ETHER_NEXT_MULTI(step, enm); 2776 } 2777 2778 v |= GEM_MAC_RX_HASH_FILTER; 2779 ifp->if_flags &= ~IFF_ALLMULTI; 2780 2781 /* Now load the hash table into the chip (if we are using it) */ 2782 for (i = 0; i < 16; i++) { 2783 bus_space_write_4(t, h, 2784 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1-GEM_MAC_HASH0), 2785 hash[i]); 2786 } 2787 2788 chipit: 2789 sc->sc_if_flags = ifp->if_flags; 2790 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 2791 } 2792
Indexes created Mon Sep 22 21:09:42 GMT 2025