gem.c revision 1.117
1 /* $NetBSD: gem.c,v 1.117 2019/05/23 10:51:39 msaitoh Exp $ */ 2 3 /* 4 * 5 * Copyright (C) 2001 Eduardo Horvath. 6 * Copyright (c) 2001-2003 Thomas Moestl 7 * All rights reserved. 8 * 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 */ 32 33 /* 34 * Driver for Apple GMAC, Sun ERI and Sun GEM Ethernet controllers 35 * See `GEM Gigabit Ethernet ASIC Specification' 36 * http://www.sun.com/processors/manuals/ge.pdf 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: gem.c,v 1.117 2019/05/23 10:51:39 msaitoh Exp $"); 41 42 #include "opt_inet.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/callout.h> 47 #include <sys/mbuf.h> 48 #include <sys/syslog.h> 49 #include <sys/malloc.h> 50 #include <sys/kernel.h> 51 #include <sys/socket.h> 52 #include <sys/ioctl.h> 53 #include <sys/errno.h> 54 #include <sys/device.h> 55 56 #include <machine/endian.h> 57 58 #include <net/if.h> 59 #include <net/if_dl.h> 60 #include <net/if_media.h> 61 #include <net/if_ether.h> 62 63 #ifdef INET 64 #include <netinet/in.h> 65 #include <netinet/in_systm.h> 66 #include <netinet/in_var.h> 67 #include <netinet/ip.h> 68 #include <netinet/tcp.h> 69 #include <netinet/udp.h> 70 #endif 71 72 #include <net/bpf.h> 73 74 #include <sys/bus.h> 75 #include <sys/intr.h> 76 77 #include <dev/mii/mii.h> 78 #include <dev/mii/miivar.h> 79 #include <dev/mii/mii_bitbang.h> 80 81 #include <dev/ic/gemreg.h> 82 #include <dev/ic/gemvar.h> 83 84 #define TRIES 10000 85 86 static void gem_inten(struct gem_softc *); 87 static void gem_start(struct ifnet *); 88 static void gem_stop(struct ifnet *, int); 89 int gem_ioctl(struct ifnet *, u_long, void *); 90 void gem_tick(void *); 91 void gem_watchdog(struct ifnet *); 92 void gem_rx_watchdog(void *); 93 void gem_pcs_start(struct gem_softc *sc); 94 void gem_pcs_stop(struct gem_softc *sc, int); 95 int gem_init(struct ifnet *); 96 void gem_init_regs(struct gem_softc *sc); 97 static int gem_ringsize(int sz); 98 static int gem_meminit(struct gem_softc *); 99 void gem_mifinit(struct gem_softc *); 100 static int gem_bitwait(struct gem_softc *sc, bus_space_handle_t, int, 101 uint32_t, uint32_t); 102 void gem_reset(struct gem_softc *); 103 int gem_reset_rx(struct gem_softc *sc); 104 static void gem_reset_rxdma(struct gem_softc *sc); 105 static void gem_rx_common(struct gem_softc *sc); 106 int gem_reset_tx(struct gem_softc *sc); 107 int gem_disable_rx(struct gem_softc *sc); 108 int gem_disable_tx(struct gem_softc *sc); 109 static void gem_rxdrain(struct gem_softc *sc); 110 int gem_add_rxbuf(struct gem_softc *sc, int idx); 111 void gem_setladrf(struct gem_softc *); 112 113 /* MII methods & callbacks */ 114 static int gem_mii_readreg(device_t, int, int, uint16_t *); 115 static int gem_mii_writereg(device_t, int, int, uint16_t); 116 static void gem_mii_statchg(struct ifnet *); 117 118 static int gem_ifflags_cb(struct ethercom *); 119 120 void gem_statuschange(struct gem_softc *); 121 122 int gem_ser_mediachange(struct ifnet *); 123 void gem_ser_mediastatus(struct ifnet *, struct ifmediareq *); 124 125 static void gem_partial_detach(struct gem_softc *, enum gem_attach_stage); 126 127 struct mbuf *gem_get(struct gem_softc *, int, int); 128 int gem_put(struct gem_softc *, int, struct mbuf *); 129 void gem_read(struct gem_softc *, int, int); 130 int gem_pint(struct gem_softc *); 131 int gem_eint(struct gem_softc *, u_int); 132 int gem_rint(struct gem_softc *); 133 int gem_tint(struct gem_softc *); 134 void gem_power(int, void *); 135 136 #ifdef GEM_DEBUG 137 static void gem_txsoft_print(const struct gem_softc *, int, int); 138 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 139 printf x 140 #else 141 #define DPRINTF(sc, x) /* nothing */ 142 #endif 143 144 #define ETHER_MIN_TX (ETHERMIN + sizeof(struct ether_header)) 145 146 int 147 gem_detach(struct gem_softc *sc, int flags) 148 { 149 int i; 150 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 151 bus_space_tag_t t = sc->sc_bustag; 152 bus_space_handle_t h = sc->sc_h1; 153 154 /* 155 * Free any resources we've allocated during the attach. 156 * Do this in reverse order and fall through. 157 */ 158 switch (sc->sc_att_stage) { 159 case GEM_ATT_BACKEND_2: 160 case GEM_ATT_BACKEND_1: 161 case GEM_ATT_FINISHED: 162 bus_space_write_4(t, h, GEM_INTMASK, ~(uint32_t)0); 163 gem_stop(&sc->sc_ethercom.ec_if, 1); 164 165 #ifdef GEM_COUNTERS 166 for (i = __arraycount(sc->sc_ev_rxhist); --i >= 0; ) 167 evcnt_detach(&sc->sc_ev_rxhist[i]); 168 evcnt_detach(&sc->sc_ev_rxnobuf); 169 evcnt_detach(&sc->sc_ev_rxfull); 170 evcnt_detach(&sc->sc_ev_rxint); 171 evcnt_detach(&sc->sc_ev_txint); 172 #endif 173 evcnt_detach(&sc->sc_ev_intr); 174 175 rnd_detach_source(&sc->rnd_source); 176 ether_ifdetach(ifp); 177 if_detach(ifp); 178 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 179 180 callout_destroy(&sc->sc_tick_ch); 181 callout_destroy(&sc->sc_rx_watchdog); 182 183 /*FALLTHROUGH*/ 184 case GEM_ATT_MII: 185 sc->sc_att_stage = GEM_ATT_MII; 186 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 187 /*FALLTHROUGH*/ 188 case GEM_ATT_7: 189 for (i = 0; i < GEM_NRXDESC; i++) { 190 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 191 bus_dmamap_destroy(sc->sc_dmatag, 192 sc->sc_rxsoft[i].rxs_dmamap); 193 } 194 /*FALLTHROUGH*/ 195 case GEM_ATT_6: 196 for (i = 0; i < GEM_TXQUEUELEN; i++) { 197 if (sc->sc_txsoft[i].txs_dmamap != NULL) 198 bus_dmamap_destroy(sc->sc_dmatag, 199 sc->sc_txsoft[i].txs_dmamap); 200 } 201 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 202 /*FALLTHROUGH*/ 203 case GEM_ATT_5: 204 bus_dmamap_unload(sc->sc_dmatag, sc->sc_nulldmamap); 205 /*FALLTHROUGH*/ 206 case GEM_ATT_4: 207 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_nulldmamap); 208 /*FALLTHROUGH*/ 209 case GEM_ATT_3: 210 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 211 /*FALLTHROUGH*/ 212 case GEM_ATT_2: 213 bus_dmamem_unmap(sc->sc_dmatag, sc->sc_control_data, 214 sizeof(struct gem_control_data)); 215 /*FALLTHROUGH*/ 216 case GEM_ATT_1: 217 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 218 /*FALLTHROUGH*/ 219 case GEM_ATT_0: 220 sc->sc_att_stage = GEM_ATT_0; 221 /*FALLTHROUGH*/ 222 case GEM_ATT_BACKEND_0: 223 break; 224 } 225 return 0; 226 } 227 228 static void 229 gem_partial_detach(struct gem_softc *sc, enum gem_attach_stage stage) 230 { 231 cfattach_t ca = device_cfattach(sc->sc_dev); 232 233 sc->sc_att_stage = stage; 234 (*ca->ca_detach)(sc->sc_dev, 0); 235 } 236 237 /* 238 * gem_attach: 239 * 240 * Attach a Gem interface to the system. 241 */ 242 void 243 gem_attach(struct gem_softc *sc, const uint8_t *enaddr) 244 { 245 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 246 struct mii_data *mii = &sc->sc_mii; 247 bus_space_tag_t t = sc->sc_bustag; 248 bus_space_handle_t h = sc->sc_h1; 249 struct ifmedia_entry *ifm; 250 int i, error, phyaddr; 251 uint32_t v; 252 char *nullbuf; 253 254 /* Make sure the chip is stopped. */ 255 ifp->if_softc = sc; 256 gem_reset(sc); 257 258 /* 259 * Allocate the control data structures, and create and load the 260 * DMA map for it. gem_control_data is 9216 bytes, we have space for 261 * the padding buffer in the bus_dmamem_alloc()'d memory. 262 */ 263 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 264 sizeof(struct gem_control_data) + ETHER_MIN_TX, PAGE_SIZE, 265 0, &sc->sc_cdseg, 1, &sc->sc_cdnseg, 0)) != 0) { 266 aprint_error_dev(sc->sc_dev, 267 "unable to allocate control data, error = %d\n", 268 error); 269 gem_partial_detach(sc, GEM_ATT_0); 270 return; 271 } 272 273 /* XXX should map this in with correct endianness */ 274 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg, 275 sizeof(struct gem_control_data), (void **)&sc->sc_control_data, 276 BUS_DMA_COHERENT)) != 0) { 277 aprint_error_dev(sc->sc_dev, 278 "unable to map control data, error = %d\n", error); 279 gem_partial_detach(sc, GEM_ATT_1); 280 return; 281 } 282 283 nullbuf = 284 (char *)sc->sc_control_data + sizeof(struct gem_control_data); 285 286 if ((error = bus_dmamap_create(sc->sc_dmatag, 287 sizeof(struct gem_control_data), 1, 288 sizeof(struct gem_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 289 aprint_error_dev(sc->sc_dev, 290 "unable to create control data DMA map, error = %d\n", 291 error); 292 gem_partial_detach(sc, GEM_ATT_2); 293 return; 294 } 295 296 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 297 sc->sc_control_data, sizeof(struct gem_control_data), NULL, 298 0)) != 0) { 299 aprint_error_dev(sc->sc_dev, 300 "unable to load control data DMA map, error = %d\n", 301 error); 302 gem_partial_detach(sc, GEM_ATT_3); 303 return; 304 } 305 306 memset(nullbuf, 0, ETHER_MIN_TX); 307 if ((error = bus_dmamap_create(sc->sc_dmatag, 308 ETHER_MIN_TX, 1, ETHER_MIN_TX, 0, 0, &sc->sc_nulldmamap)) != 0) { 309 aprint_error_dev(sc->sc_dev, 310 "unable to create padding DMA map, error = %d\n", error); 311 gem_partial_detach(sc, GEM_ATT_4); 312 return; 313 } 314 315 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_nulldmamap, 316 nullbuf, ETHER_MIN_TX, NULL, 0)) != 0) { 317 aprint_error_dev(sc->sc_dev, 318 "unable to load padding DMA map, error = %d\n", error); 319 gem_partial_detach(sc, GEM_ATT_5); 320 return; 321 } 322 323 bus_dmamap_sync(sc->sc_dmatag, sc->sc_nulldmamap, 0, ETHER_MIN_TX, 324 BUS_DMASYNC_PREWRITE); 325 326 /* 327 * Initialize the transmit job descriptors. 328 */ 329 SIMPLEQ_INIT(&sc->sc_txfreeq); 330 SIMPLEQ_INIT(&sc->sc_txdirtyq); 331 332 /* 333 * Create the transmit buffer DMA maps. 334 */ 335 for (i = 0; i < GEM_TXQUEUELEN; i++) { 336 struct gem_txsoft *txs; 337 338 txs = &sc->sc_txsoft[i]; 339 txs->txs_mbuf = NULL; 340 if ((error = bus_dmamap_create(sc->sc_dmatag, 341 ETHER_MAX_LEN_JUMBO, GEM_NTXSEGS, 342 ETHER_MAX_LEN_JUMBO, 0, 0, 343 &txs->txs_dmamap)) != 0) { 344 aprint_error_dev(sc->sc_dev, 345 "unable to create tx DMA map %d, error = %d\n", 346 i, error); 347 gem_partial_detach(sc, GEM_ATT_6); 348 return; 349 } 350 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 351 } 352 353 /* 354 * Create the receive buffer DMA maps. 355 */ 356 for (i = 0; i < GEM_NRXDESC; i++) { 357 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, 358 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 359 aprint_error_dev(sc->sc_dev, 360 "unable to create rx DMA map %d, error = %d\n", 361 i, error); 362 gem_partial_detach(sc, GEM_ATT_7); 363 return; 364 } 365 sc->sc_rxsoft[i].rxs_mbuf = NULL; 366 } 367 368 /* Initialize ifmedia structures and MII info */ 369 mii->mii_ifp = ifp; 370 mii->mii_readreg = gem_mii_readreg; 371 mii->mii_writereg = gem_mii_writereg; 372 mii->mii_statchg = gem_mii_statchg; 373 374 sc->sc_ethercom.ec_mii = mii; 375 376 /* 377 * Initialization based on `GEM Gigabit Ethernet ASIC Specification' 378 * Section 3.2.1 `Initialization Sequence'. 379 * However, we can't assume SERDES or Serialink if neither 380 * GEM_MIF_CONFIG_MDI0 nor GEM_MIF_CONFIG_MDI1 are set 381 * being set, as both are set on Sun X1141A (with SERDES). So, 382 * we rely on our bus attachment setting GEM_SERDES or GEM_SERIAL. 383 * Also, for variants that report 2 PHY's, we prefer the external 384 * PHY over the internal PHY, so we look for that first. 385 */ 386 gem_mifinit(sc); 387 388 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) { 389 ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange, 390 ether_mediastatus); 391 /* Look for external PHY */ 392 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) { 393 sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL; 394 bus_space_write_4(t, h, GEM_MIF_CONFIG, 395 sc->sc_mif_config); 396 switch (sc->sc_variant) { 397 case GEM_SUN_ERI: 398 phyaddr = GEM_PHYAD_EXTERNAL; 399 break; 400 default: 401 phyaddr = MII_PHY_ANY; 402 break; 403 } 404 mii_attach(sc->sc_dev, mii, 0xffffffff, phyaddr, 405 MII_OFFSET_ANY, MIIF_FORCEANEG); 406 } 407 #ifdef GEM_DEBUG 408 else 409 aprint_debug_dev(sc->sc_dev, "using external PHY\n"); 410 #endif 411 /* Look for internal PHY if no external PHY was found */ 412 if (LIST_EMPTY(&mii->mii_phys) && 413 ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI0) || 414 (sc->sc_variant == GEM_APPLE_K2_GMAC))) { 415 sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL; 416 bus_space_write_4(t, h, GEM_MIF_CONFIG, 417 sc->sc_mif_config); 418 switch (sc->sc_variant) { 419 case GEM_SUN_ERI: 420 case GEM_APPLE_K2_GMAC: 421 phyaddr = GEM_PHYAD_INTERNAL; 422 break; 423 case GEM_APPLE_GMAC: 424 phyaddr = GEM_PHYAD_EXTERNAL; 425 break; 426 default: 427 phyaddr = MII_PHY_ANY; 428 break; 429 } 430 mii_attach(sc->sc_dev, mii, 0xffffffff, phyaddr, 431 MII_OFFSET_ANY, MIIF_FORCEANEG); 432 #ifdef GEM_DEBUG 433 if (!LIST_EMPTY(&mii->mii_phys)) 434 aprint_debug_dev(sc->sc_dev, 435 "using internal PHY\n"); 436 #endif 437 } 438 if (LIST_EMPTY(&mii->mii_phys)) { 439 /* No PHY attached */ 440 aprint_error_dev(sc->sc_dev, 441 "PHY probe failed\n"); 442 gem_partial_detach(sc, GEM_ATT_MII); 443 return; 444 } else { 445 struct mii_softc *child; 446 447 /* 448 * Walk along the list of attached MII devices and 449 * establish an `MII instance' to `PHY number' 450 * mapping. 451 */ 452 LIST_FOREACH(child, &mii->mii_phys, mii_list) { 453 /* 454 * Note: we support just one PHY: the internal 455 * or external MII is already selected for us 456 * by the GEM_MIF_CONFIG register. 457 */ 458 if (child->mii_phy > 1 || child->mii_inst > 0) { 459 aprint_error_dev(sc->sc_dev, 460 "cannot accommodate MII device" 461 " %s at PHY %d, instance %d\n", 462 device_xname(child->mii_dev), 463 child->mii_phy, child->mii_inst); 464 continue; 465 } 466 sc->sc_phys[child->mii_inst] = child->mii_phy; 467 } 468 469 if (sc->sc_variant != GEM_SUN_ERI) 470 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 471 GEM_MII_DATAPATH_MII); 472 473 /* 474 * XXX - we can really do the following ONLY if the 475 * PHY indeed has the auto negotiation capability!! 476 */ 477 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 478 } 479 } else { 480 ifmedia_init(&mii->mii_media, IFM_IMASK, gem_ser_mediachange, 481 gem_ser_mediastatus); 482 /* SERDES or Serialink */ 483 if (sc->sc_flags & GEM_SERDES) { 484 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 485 GEM_MII_DATAPATH_SERDES); 486 } else { 487 sc->sc_flags |= GEM_SERIAL; 488 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 489 GEM_MII_DATAPATH_SERIAL); 490 } 491 492 aprint_normal_dev(sc->sc_dev, "using external PCS %s: ", 493 sc->sc_flags & GEM_SERDES ? "SERDES" : "Serialink"); 494 495 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_AUTO, 0, NULL); 496 /* Check for FDX and HDX capabilities */ 497 sc->sc_mii_anar = bus_space_read_4(t, h, GEM_MII_ANAR); 498 if (sc->sc_mii_anar & GEM_MII_ANEG_FUL_DUPLX) { 499 ifmedia_add(&mii->mii_media, IFM_ETHER | 500 IFM_1000_SX | IFM_MANUAL | IFM_FDX, 0, NULL); 501 aprint_normal("1000baseSX-FDX, "); 502 } 503 if (sc->sc_mii_anar & GEM_MII_ANEG_HLF_DUPLX) { 504 ifmedia_add(&mii->mii_media, IFM_ETHER | 505 IFM_1000_SX | IFM_MANUAL | IFM_HDX, 0, NULL); 506 aprint_normal("1000baseSX-HDX, "); 507 } 508 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 509 sc->sc_mii_media = IFM_AUTO; 510 aprint_normal("auto\n"); 511 512 gem_pcs_stop(sc, 1); 513 } 514 515 /* 516 * From this point forward, the attachment cannot fail. A failure 517 * before this point releases all resources that may have been 518 * allocated. 519 */ 520 521 /* Announce ourselves. */ 522 aprint_normal_dev(sc->sc_dev, "Ethernet address %s", 523 ether_sprintf(enaddr)); 524 525 /* Get RX FIFO size */ 526 sc->sc_rxfifosize = 64 * 527 bus_space_read_4(t, h, GEM_RX_FIFO_SIZE); 528 aprint_normal(", %uKB RX fifo", sc->sc_rxfifosize / 1024); 529 530 /* Get TX FIFO size */ 531 v = bus_space_read_4(t, h, GEM_TX_FIFO_SIZE); 532 aprint_normal(", %uKB TX fifo\n", v / 16); 533 534 /* Initialize ifnet structure. */ 535 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 536 ifp->if_softc = sc; 537 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 538 sc->sc_if_flags = ifp->if_flags; 539 #if 0 540 /* 541 * The GEM hardware supports basic TCP checksum offloading only. 542 * Several (all?) revisions (Sun rev. 01 and Apple rev. 00 and 80) 543 * have bugs in the receive checksum, so don't enable it for now. 544 */ 545 if ((GEM_IS_SUN(sc) && sc->sc_chiprev != 1) || 546 (GEM_IS_APPLE(sc) && 547 (sc->sc_chiprev != 0 && sc->sc_chiprev != 0x80))) 548 ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Rx; 549 #endif 550 ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Tx; 551 ifp->if_start = gem_start; 552 ifp->if_ioctl = gem_ioctl; 553 ifp->if_watchdog = gem_watchdog; 554 ifp->if_stop = gem_stop; 555 ifp->if_init = gem_init; 556 IFQ_SET_READY(&ifp->if_snd); 557 558 /* 559 * If we support GigE media, we support jumbo frames too. 560 * Unless we are Apple. 561 */ 562 TAILQ_FOREACH(ifm, &mii->mii_media.ifm_list, ifm_list) { 563 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_T || 564 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_SX || 565 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_LX || 566 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_CX) { 567 if (!GEM_IS_APPLE(sc)) 568 sc->sc_ethercom.ec_capabilities 569 |= ETHERCAP_JUMBO_MTU; 570 sc->sc_flags |= GEM_GIGABIT; 571 break; 572 } 573 } 574 575 /* claim 802.1q capability */ 576 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 577 578 /* Attach the interface. */ 579 if_attach(ifp); 580 if_deferred_start_init(ifp, NULL); 581 ether_ifattach(ifp, enaddr); 582 ether_set_ifflags_cb(&sc->sc_ethercom, gem_ifflags_cb); 583 584 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 585 RND_TYPE_NET, RND_FLAG_DEFAULT); 586 587 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, 588 NULL, device_xname(sc->sc_dev), "interrupts"); 589 #ifdef GEM_COUNTERS 590 evcnt_attach_dynamic(&sc->sc_ev_txint, EVCNT_TYPE_INTR, 591 &sc->sc_ev_intr, device_xname(sc->sc_dev), "tx interrupts"); 592 evcnt_attach_dynamic(&sc->sc_ev_rxint, EVCNT_TYPE_INTR, 593 &sc->sc_ev_intr, device_xname(sc->sc_dev), "rx interrupts"); 594 evcnt_attach_dynamic(&sc->sc_ev_rxfull, EVCNT_TYPE_INTR, 595 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx ring full"); 596 evcnt_attach_dynamic(&sc->sc_ev_rxnobuf, EVCNT_TYPE_INTR, 597 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx malloc failure"); 598 evcnt_attach_dynamic(&sc->sc_ev_rxhist[0], EVCNT_TYPE_INTR, 599 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 0desc"); 600 evcnt_attach_dynamic(&sc->sc_ev_rxhist[1], EVCNT_TYPE_INTR, 601 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 1desc"); 602 evcnt_attach_dynamic(&sc->sc_ev_rxhist[2], EVCNT_TYPE_INTR, 603 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 2desc"); 604 evcnt_attach_dynamic(&sc->sc_ev_rxhist[3], EVCNT_TYPE_INTR, 605 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 3desc"); 606 evcnt_attach_dynamic(&sc->sc_ev_rxhist[4], EVCNT_TYPE_INTR, 607 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >3desc"); 608 evcnt_attach_dynamic(&sc->sc_ev_rxhist[5], EVCNT_TYPE_INTR, 609 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >7desc"); 610 evcnt_attach_dynamic(&sc->sc_ev_rxhist[6], EVCNT_TYPE_INTR, 611 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >15desc"); 612 evcnt_attach_dynamic(&sc->sc_ev_rxhist[7], EVCNT_TYPE_INTR, 613 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >31desc"); 614 evcnt_attach_dynamic(&sc->sc_ev_rxhist[8], EVCNT_TYPE_INTR, 615 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >63desc"); 616 #endif 617 618 callout_init(&sc->sc_tick_ch, 0); 619 callout_init(&sc->sc_rx_watchdog, 0); 620 callout_setfunc(&sc->sc_rx_watchdog, gem_rx_watchdog, sc); 621 622 sc->sc_att_stage = GEM_ATT_FINISHED; 623 624 return; 625 } 626 627 void 628 gem_tick(void *arg) 629 { 630 struct gem_softc *sc = arg; 631 int s; 632 633 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) { 634 /* 635 * We have to reset everything if we failed to get a 636 * PCS interrupt. Restarting the callout is handled 637 * in gem_pcs_start(). 638 */ 639 gem_init(&sc->sc_ethercom.ec_if); 640 } else { 641 s = splnet(); 642 mii_tick(&sc->sc_mii); 643 splx(s); 644 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 645 } 646 } 647 648 static int 649 gem_bitwait(struct gem_softc *sc, bus_space_handle_t h, int r, uint32_t clr, 650 uint32_t set) 651 { 652 int i; 653 uint32_t reg; 654 655 for (i = TRIES; i--; DELAY(100)) { 656 reg = bus_space_read_4(sc->sc_bustag, h, r); 657 if ((reg & clr) == 0 && (reg & set) == set) 658 return (1); 659 } 660 return (0); 661 } 662 663 void 664 gem_reset(struct gem_softc *sc) 665 { 666 bus_space_tag_t t = sc->sc_bustag; 667 bus_space_handle_t h = sc->sc_h2; 668 int s; 669 670 s = splnet(); 671 DPRINTF(sc, ("%s: gem_reset\n", device_xname(sc->sc_dev))); 672 gem_reset_rx(sc); 673 gem_reset_tx(sc); 674 675 /* Do a full reset */ 676 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX); 677 if (!gem_bitwait(sc, h, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0)) 678 aprint_error_dev(sc->sc_dev, "cannot reset device\n"); 679 splx(s); 680 } 681 682 683 /* 684 * gem_rxdrain: 685 * 686 * Drain the receive queue. 687 */ 688 static void 689 gem_rxdrain(struct gem_softc *sc) 690 { 691 struct gem_rxsoft *rxs; 692 int i; 693 694 for (i = 0; i < GEM_NRXDESC; i++) { 695 rxs = &sc->sc_rxsoft[i]; 696 if (rxs->rxs_mbuf != NULL) { 697 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 698 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 699 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 700 m_freem(rxs->rxs_mbuf); 701 rxs->rxs_mbuf = NULL; 702 } 703 } 704 } 705 706 /* 707 * Reset the whole thing. 708 */ 709 static void 710 gem_stop(struct ifnet *ifp, int disable) 711 { 712 struct gem_softc *sc = ifp->if_softc; 713 struct gem_txsoft *txs; 714 715 DPRINTF(sc, ("%s: gem_stop\n", device_xname(sc->sc_dev))); 716 717 callout_halt(&sc->sc_tick_ch, NULL); 718 callout_halt(&sc->sc_rx_watchdog, NULL); 719 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 720 gem_pcs_stop(sc, disable); 721 else 722 mii_down(&sc->sc_mii); 723 724 /* XXX - Should we reset these instead? */ 725 gem_disable_tx(sc); 726 gem_disable_rx(sc); 727 728 /* 729 * Release any queued transmit buffers. 730 */ 731 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 732 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 733 if (txs->txs_mbuf != NULL) { 734 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 0, 735 txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 736 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 737 m_freem(txs->txs_mbuf); 738 txs->txs_mbuf = NULL; 739 } 740 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 741 } 742 743 /* 744 * Mark the interface down and cancel the watchdog timer. 745 */ 746 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 747 sc->sc_if_flags = ifp->if_flags; 748 ifp->if_timer = 0; 749 750 if (disable) 751 gem_rxdrain(sc); 752 } 753 754 755 /* 756 * Reset the receiver 757 */ 758 int 759 gem_reset_rx(struct gem_softc *sc) 760 { 761 bus_space_tag_t t = sc->sc_bustag; 762 bus_space_handle_t h = sc->sc_h1, h2 = sc->sc_h2; 763 764 /* 765 * Resetting while DMA is in progress can cause a bus hang, so we 766 * disable DMA first. 767 */ 768 gem_disable_rx(sc); 769 bus_space_write_4(t, h, GEM_RX_CONFIG, 0); 770 bus_space_barrier(t, h, GEM_RX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 771 /* Wait till it finishes */ 772 if (!gem_bitwait(sc, h, GEM_RX_CONFIG, 1, 0)) 773 aprint_error_dev(sc->sc_dev, "cannot disable read dma\n"); 774 /* Wait 5ms extra. */ 775 delay(5000); 776 777 /* Finally, reset the ERX */ 778 bus_space_write_4(t, h2, GEM_RESET, GEM_RESET_RX); 779 bus_space_barrier(t, h, GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE); 780 /* Wait till it finishes */ 781 if (!gem_bitwait(sc, h2, GEM_RESET, GEM_RESET_RX, 0)) { 782 aprint_error_dev(sc->sc_dev, "cannot reset receiver\n"); 783 return (1); 784 } 785 return (0); 786 } 787 788 789 /* 790 * Reset the receiver DMA engine. 791 * 792 * Intended to be used in case of GEM_INTR_RX_TAG_ERR, GEM_MAC_RX_OVERFLOW 793 * etc in order to reset the receiver DMA engine only and not do a full 794 * reset which amongst others also downs the link and clears the FIFOs. 795 */ 796 static void 797 gem_reset_rxdma(struct gem_softc *sc) 798 { 799 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 800 bus_space_tag_t t = sc->sc_bustag; 801 bus_space_handle_t h = sc->sc_h1; 802 int i; 803 804 if (gem_reset_rx(sc) != 0) { 805 gem_init(ifp); 806 return; 807 } 808 for (i = 0; i < GEM_NRXDESC; i++) 809 if (sc->sc_rxsoft[i].rxs_mbuf != NULL) 810 GEM_UPDATE_RXDESC(sc, i); 811 sc->sc_rxptr = 0; 812 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE); 813 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD); 814 815 /* Reprogram Descriptor Ring Base Addresses */ 816 /* NOTE: we use only 32-bit DMA addresses here. */ 817 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0); 818 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 819 820 /* Redo ERX Configuration */ 821 gem_rx_common(sc); 822 823 /* Give the reciever a swift kick */ 824 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC - 4); 825 } 826 827 /* 828 * Common RX configuration for gem_init() and gem_reset_rxdma(). 829 */ 830 static void 831 gem_rx_common(struct gem_softc *sc) 832 { 833 bus_space_tag_t t = sc->sc_bustag; 834 bus_space_handle_t h = sc->sc_h1; 835 uint32_t v; 836 837 /* Encode Receive Descriptor ring size: four possible values */ 838 v = gem_ringsize(GEM_NRXDESC /*XXX*/); 839 840 /* Set receive h/w checksum offset */ 841 #ifdef INET 842 v |= (ETHER_HDR_LEN + sizeof(struct ip) + 843 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 844 ETHER_VLAN_ENCAP_LEN : 0)) << GEM_RX_CONFIG_CXM_START_SHFT; 845 #endif 846 847 /* Enable RX DMA */ 848 bus_space_write_4(t, h, GEM_RX_CONFIG, 849 v | (GEM_THRSH_1024 << GEM_RX_CONFIG_FIFO_THRS_SHIFT) | 850 (2 << GEM_RX_CONFIG_FBOFF_SHFT) | GEM_RX_CONFIG_RXDMA_EN); 851 852 /* 853 * The following value is for an OFF Threshold of about 3/4 full 854 * and an ON Threshold of 1/4 full. 855 */ 856 bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH, 857 (3 * sc->sc_rxfifosize / 256) | 858 ((sc->sc_rxfifosize / 256) << 12)); 859 bus_space_write_4(t, h, GEM_RX_BLANKING, 860 (6 << GEM_RX_BLANKING_TIME_SHIFT) | 8); 861 } 862 863 /* 864 * Reset the transmitter 865 */ 866 int 867 gem_reset_tx(struct gem_softc *sc) 868 { 869 bus_space_tag_t t = sc->sc_bustag; 870 bus_space_handle_t h = sc->sc_h1, h2 = sc->sc_h2; 871 872 /* 873 * Resetting while DMA is in progress can cause a bus hang, so we 874 * disable DMA first. 875 */ 876 gem_disable_tx(sc); 877 bus_space_write_4(t, h, GEM_TX_CONFIG, 0); 878 bus_space_barrier(t, h, GEM_TX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 879 /* Wait till it finishes */ 880 if (!gem_bitwait(sc, h, GEM_TX_CONFIG, 1, 0)) 881 aprint_error_dev(sc->sc_dev, "cannot disable read dma\n"); 882 /* Wait 5ms extra. */ 883 delay(5000); 884 885 /* Finally, reset the ETX */ 886 bus_space_write_4(t, h2, GEM_RESET, GEM_RESET_TX); 887 bus_space_barrier(t, h, GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE); 888 /* Wait till it finishes */ 889 if (!gem_bitwait(sc, h2, GEM_RESET, GEM_RESET_TX, 0)) { 890 aprint_error_dev(sc->sc_dev, "cannot reset receiver\n"); 891 return (1); 892 } 893 return (0); 894 } 895 896 /* 897 * disable receiver. 898 */ 899 int 900 gem_disable_rx(struct gem_softc *sc) 901 { 902 bus_space_tag_t t = sc->sc_bustag; 903 bus_space_handle_t h = sc->sc_h1; 904 uint32_t cfg; 905 906 /* Flip the enable bit */ 907 cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 908 cfg &= ~GEM_MAC_RX_ENABLE; 909 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg); 910 bus_space_barrier(t, h, GEM_MAC_RX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 911 /* Wait for it to finish */ 912 return (gem_bitwait(sc, h, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)); 913 } 914 915 /* 916 * disable transmitter. 917 */ 918 int 919 gem_disable_tx(struct gem_softc *sc) 920 { 921 bus_space_tag_t t = sc->sc_bustag; 922 bus_space_handle_t h = sc->sc_h1; 923 uint32_t cfg; 924 925 /* Flip the enable bit */ 926 cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG); 927 cfg &= ~GEM_MAC_TX_ENABLE; 928 bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg); 929 bus_space_barrier(t, h, GEM_MAC_TX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 930 /* Wait for it to finish */ 931 return (gem_bitwait(sc, h, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)); 932 } 933 934 /* 935 * Initialize interface. 936 */ 937 int 938 gem_meminit(struct gem_softc *sc) 939 { 940 struct gem_rxsoft *rxs; 941 int i, error; 942 943 /* 944 * Initialize the transmit descriptor ring. 945 */ 946 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 947 for (i = 0; i < GEM_NTXDESC; i++) { 948 sc->sc_txdescs[i].gd_flags = 0; 949 sc->sc_txdescs[i].gd_addr = 0; 950 } 951 GEM_CDTXSYNC(sc, 0, GEM_NTXDESC, 952 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 953 sc->sc_txfree = GEM_NTXDESC-1; 954 sc->sc_txnext = 0; 955 sc->sc_txwin = 0; 956 957 /* 958 * Initialize the receive descriptor and receive job 959 * descriptor rings. 960 */ 961 for (i = 0; i < GEM_NRXDESC; i++) { 962 rxs = &sc->sc_rxsoft[i]; 963 if (rxs->rxs_mbuf == NULL) { 964 if ((error = gem_add_rxbuf(sc, i)) != 0) { 965 aprint_error_dev(sc->sc_dev, 966 "unable to allocate or map rx " 967 "buffer %d, error = %d\n", 968 i, error); 969 /* 970 * XXX Should attempt to run with fewer receive 971 * XXX buffers instead of just failing. 972 */ 973 gem_rxdrain(sc); 974 return (1); 975 } 976 } else 977 GEM_INIT_RXDESC(sc, i); 978 } 979 sc->sc_rxptr = 0; 980 sc->sc_meminited = 1; 981 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE); 982 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD); 983 984 return (0); 985 } 986 987 static int 988 gem_ringsize(int sz) 989 { 990 switch (sz) { 991 case 32: 992 return GEM_RING_SZ_32; 993 case 64: 994 return GEM_RING_SZ_64; 995 case 128: 996 return GEM_RING_SZ_128; 997 case 256: 998 return GEM_RING_SZ_256; 999 case 512: 1000 return GEM_RING_SZ_512; 1001 case 1024: 1002 return GEM_RING_SZ_1024; 1003 case 2048: 1004 return GEM_RING_SZ_2048; 1005 case 4096: 1006 return GEM_RING_SZ_4096; 1007 case 8192: 1008 return GEM_RING_SZ_8192; 1009 default: 1010 printf("gem: invalid Receive Descriptor ring size %d\n", sz); 1011 return GEM_RING_SZ_32; 1012 } 1013 } 1014 1015 1016 /* 1017 * Start PCS 1018 */ 1019 void 1020 gem_pcs_start(struct gem_softc *sc) 1021 { 1022 bus_space_tag_t t = sc->sc_bustag; 1023 bus_space_handle_t h = sc->sc_h1; 1024 uint32_t v; 1025 1026 #ifdef GEM_DEBUG 1027 aprint_debug_dev(sc->sc_dev, "gem_pcs_start()\n"); 1028 #endif 1029 1030 /* 1031 * Set up. We must disable the MII before modifying the 1032 * GEM_MII_ANAR register 1033 */ 1034 if (sc->sc_flags & GEM_SERDES) { 1035 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 1036 GEM_MII_DATAPATH_SERDES); 1037 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 1038 GEM_MII_SLINK_LOOPBACK); 1039 } else { 1040 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 1041 GEM_MII_DATAPATH_SERIAL); 1042 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 0); 1043 } 1044 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 1045 v = bus_space_read_4(t, h, GEM_MII_ANAR); 1046 v |= (GEM_MII_ANEG_SYM_PAUSE | GEM_MII_ANEG_ASYM_PAUSE); 1047 if (IFM_SUBTYPE(sc->sc_mii_media) == IFM_AUTO) 1048 v |= (GEM_MII_ANEG_FUL_DUPLX | GEM_MII_ANEG_HLF_DUPLX); 1049 else if ((IFM_OPTIONS(sc->sc_mii_media) & IFM_FDX) != 0) { 1050 v |= GEM_MII_ANEG_FUL_DUPLX; 1051 v &= ~GEM_MII_ANEG_HLF_DUPLX; 1052 } else if ((IFM_OPTIONS(sc->sc_mii_media) & IFM_HDX) != 0) { 1053 v &= ~GEM_MII_ANEG_FUL_DUPLX; 1054 v |= GEM_MII_ANEG_HLF_DUPLX; 1055 } 1056 1057 /* Configure link. */ 1058 bus_space_write_4(t, h, GEM_MII_ANAR, v); 1059 bus_space_write_4(t, h, GEM_MII_CONTROL, 1060 GEM_MII_CONTROL_AUTONEG | GEM_MII_CONTROL_RAN); 1061 bus_space_write_4(t, h, GEM_MII_CONFIG, GEM_MII_CONFIG_ENABLE); 1062 gem_bitwait(sc, h, GEM_MII_STATUS, 0, GEM_MII_STATUS_ANEG_CPT); 1063 1064 /* Start the 10 second timer */ 1065 callout_reset(&sc->sc_tick_ch, hz * 10, gem_tick, sc); 1066 } 1067 1068 /* 1069 * Stop PCS 1070 */ 1071 void 1072 gem_pcs_stop(struct gem_softc *sc, int disable) 1073 { 1074 bus_space_tag_t t = sc->sc_bustag; 1075 bus_space_handle_t h = sc->sc_h1; 1076 1077 #ifdef GEM_DEBUG 1078 aprint_debug_dev(sc->sc_dev, "gem_pcs_stop()\n"); 1079 #endif 1080 1081 /* Tell link partner that we're going away */ 1082 bus_space_write_4(t, h, GEM_MII_ANAR, GEM_MII_ANEG_RF); 1083 1084 /* 1085 * Disable PCS MII. The documentation suggests that setting 1086 * GEM_MII_CONFIG_ENABLE to zero and then restarting auto- 1087 * negotiation will shut down the link. However, it appears 1088 * that we also need to unset the datapath mode. 1089 */ 1090 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 1091 bus_space_write_4(t, h, GEM_MII_CONTROL, 1092 GEM_MII_CONTROL_AUTONEG | GEM_MII_CONTROL_RAN); 1093 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, GEM_MII_DATAPATH_MII); 1094 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 1095 1096 if (disable) { 1097 if (sc->sc_flags & GEM_SERDES) 1098 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 1099 GEM_MII_SLINK_POWER_OFF); 1100 else 1101 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 1102 GEM_MII_SLINK_LOOPBACK | GEM_MII_SLINK_POWER_OFF); 1103 } 1104 1105 sc->sc_flags &= ~GEM_LINK; 1106 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_NONE; 1107 sc->sc_mii.mii_media_status = IFM_AVALID; 1108 } 1109 1110 1111 /* 1112 * Initialization of interface; set up initialization block 1113 * and transmit/receive descriptor rings. 1114 */ 1115 int 1116 gem_init(struct ifnet *ifp) 1117 { 1118 struct gem_softc *sc = ifp->if_softc; 1119 bus_space_tag_t t = sc->sc_bustag; 1120 bus_space_handle_t h = sc->sc_h1; 1121 int rc = 0, s; 1122 u_int max_frame_size; 1123 uint32_t v; 1124 1125 s = splnet(); 1126 1127 DPRINTF(sc, ("%s: gem_init: calling stop\n", device_xname(sc->sc_dev))); 1128 /* 1129 * Initialization sequence. The numbered steps below correspond 1130 * to the sequence outlined in section 6.3.5.1 in the Ethernet 1131 * Channel Engine manual (part of the PCIO manual). 1132 * See also the STP2002-STQ document from Sun Microsystems. 1133 */ 1134 1135 /* step 1 & 2. Reset the Ethernet Channel */ 1136 gem_stop(ifp, 0); 1137 gem_reset(sc); 1138 DPRINTF(sc, ("%s: gem_init: restarting\n", device_xname(sc->sc_dev))); 1139 1140 /* Re-initialize the MIF */ 1141 gem_mifinit(sc); 1142 1143 /* Set up correct datapath for non-SERDES/Serialink */ 1144 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0 && 1145 sc->sc_variant != GEM_SUN_ERI) 1146 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 1147 GEM_MII_DATAPATH_MII); 1148 1149 /* Call MI reset function if any */ 1150 if (sc->sc_hwreset) 1151 (*sc->sc_hwreset)(sc); 1152 1153 /* step 3. Setup data structures in host memory */ 1154 if (gem_meminit(sc) != 0) { 1155 splx(s); 1156 return 1; 1157 } 1158 1159 /* step 4. TX MAC registers & counters */ 1160 gem_init_regs(sc); 1161 max_frame_size = uimax(sc->sc_ethercom.ec_if.if_mtu, ETHERMTU); 1162 max_frame_size += ETHER_HDR_LEN + ETHER_CRC_LEN; 1163 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1164 max_frame_size += ETHER_VLAN_ENCAP_LEN; 1165 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 1166 max_frame_size|/* burst size */(0x2000<<16)); 1167 1168 /* step 5. RX MAC registers & counters */ 1169 gem_setladrf(sc); 1170 1171 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 1172 /* NOTE: we use only 32-bit DMA addresses here. */ 1173 bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 0); 1174 bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 1175 1176 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0); 1177 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 1178 1179 /* step 8. Global Configuration & Interrupt Mask */ 1180 gem_inten(sc); 1181 bus_space_write_4(t, h, GEM_MAC_RX_MASK, 1182 GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT); 1183 bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXX */ 1184 bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 1185 GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME); 1186 1187 /* step 9. ETX Configuration: use mostly default values */ 1188 1189 /* Enable TX DMA */ 1190 v = gem_ringsize(GEM_NTXDESC /*XXX*/); 1191 bus_space_write_4(t, h, GEM_TX_CONFIG, 1192 v | GEM_TX_CONFIG_TXDMA_EN | 1193 (((sc->sc_flags & GEM_GIGABIT ? 0x4FF : 0x100) << 10) & 1194 GEM_TX_CONFIG_TXFIFO_TH)); 1195 bus_space_write_4(t, h, GEM_TX_KICK, sc->sc_txnext); 1196 1197 /* step 10. ERX Configuration */ 1198 gem_rx_common(sc); 1199 1200 /* step 11. Configure Media */ 1201 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0 && 1202 (rc = mii_ifmedia_change(&sc->sc_mii)) != 0) 1203 goto out; 1204 1205 /* step 12. RX_MAC Configuration Register */ 1206 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 1207 v |= GEM_MAC_RX_ENABLE | GEM_MAC_RX_STRIP_CRC; 1208 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 1209 1210 /* step 14. Issue Transmit Pending command */ 1211 1212 /* Call MI initialization function if any */ 1213 if (sc->sc_hwinit) 1214 (*sc->sc_hwinit)(sc); 1215 1216 1217 /* step 15. Give the reciever a swift kick */ 1218 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4); 1219 1220 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 1221 /* Configure PCS */ 1222 gem_pcs_start(sc); 1223 else 1224 /* Start the one second timer. */ 1225 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 1226 1227 sc->sc_flags &= ~GEM_LINK; 1228 ifp->if_flags |= IFF_RUNNING; 1229 ifp->if_flags &= ~IFF_OACTIVE; 1230 ifp->if_timer = 0; 1231 sc->sc_if_flags = ifp->if_flags; 1232 out: 1233 splx(s); 1234 1235 return (0); 1236 } 1237 1238 void 1239 gem_init_regs(struct gem_softc *sc) 1240 { 1241 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1242 bus_space_tag_t t = sc->sc_bustag; 1243 bus_space_handle_t h = sc->sc_h1; 1244 const u_char *laddr = CLLADDR(ifp->if_sadl); 1245 uint32_t v; 1246 1247 /* These regs are not cleared on reset */ 1248 if (!sc->sc_inited) { 1249 1250 /* Load recommended values */ 1251 bus_space_write_4(t, h, GEM_MAC_IPG0, 0x00); 1252 bus_space_write_4(t, h, GEM_MAC_IPG1, 0x08); 1253 bus_space_write_4(t, h, GEM_MAC_IPG2, 0x04); 1254 1255 bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 1256 /* Max frame and max burst size */ 1257 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 1258 ETHER_MAX_LEN | (0x2000<<16)); 1259 1260 bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x07); 1261 bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x04); 1262 bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10); 1263 bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088); 1264 bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED, 1265 ((laddr[5]<<8)|laddr[4])&0x3ff); 1266 1267 /* Secondary MAC addr set to 0:0:0:0:0:0 */ 1268 bus_space_write_4(t, h, GEM_MAC_ADDR3, 0); 1269 bus_space_write_4(t, h, GEM_MAC_ADDR4, 0); 1270 bus_space_write_4(t, h, GEM_MAC_ADDR5, 0); 1271 1272 /* MAC control addr set to 01:80:c2:00:00:01 */ 1273 bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001); 1274 bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200); 1275 bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180); 1276 1277 /* MAC filter addr set to 0:0:0:0:0:0 */ 1278 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0); 1279 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0); 1280 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0); 1281 1282 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0); 1283 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0); 1284 1285 sc->sc_inited = 1; 1286 } 1287 1288 /* Counters need to be zeroed */ 1289 bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0); 1290 bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0); 1291 bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0); 1292 bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0); 1293 bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0); 1294 bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0); 1295 bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0); 1296 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 1297 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 1298 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 1299 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 1300 1301 /* Set XOFF PAUSE time. */ 1302 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); 1303 1304 /* 1305 * Set the internal arbitration to "infinite" bursts of the 1306 * maximum length of 31 * 64 bytes so DMA transfers aren't 1307 * split up in cache line size chunks. This greatly improves 1308 * especially RX performance. 1309 * Enable silicon bug workarounds for the Apple variants. 1310 */ 1311 bus_space_write_4(t, h, GEM_CONFIG, 1312 GEM_CONFIG_TXDMA_LIMIT | GEM_CONFIG_RXDMA_LIMIT | 1313 ((sc->sc_flags & GEM_PCI) ? 1314 GEM_CONFIG_BURST_INF : GEM_CONFIG_BURST_64) | (GEM_IS_APPLE(sc) ? 1315 GEM_CONFIG_RONPAULBIT | GEM_CONFIG_BUG2FIX : 0)); 1316 1317 /* 1318 * Set the station address. 1319 */ 1320 bus_space_write_4(t, h, GEM_MAC_ADDR0, (laddr[4]<<8)|laddr[5]); 1321 bus_space_write_4(t, h, GEM_MAC_ADDR1, (laddr[2]<<8)|laddr[3]); 1322 bus_space_write_4(t, h, GEM_MAC_ADDR2, (laddr[0]<<8)|laddr[1]); 1323 1324 /* 1325 * Enable MII outputs. Enable GMII if there is a gigabit PHY. 1326 */ 1327 sc->sc_mif_config = bus_space_read_4(t, h, GEM_MIF_CONFIG); 1328 v = GEM_MAC_XIF_TX_MII_ENA; 1329 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) { 1330 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) { 1331 v |= GEM_MAC_XIF_FDPLX_LED; 1332 if (sc->sc_flags & GEM_GIGABIT) 1333 v |= GEM_MAC_XIF_GMII_MODE; 1334 } 1335 } else { 1336 v |= GEM_MAC_XIF_GMII_MODE; 1337 } 1338 bus_space_write_4(t, h, GEM_MAC_XIF_CONFIG, v); 1339 } 1340 1341 #ifdef GEM_DEBUG 1342 static void 1343 gem_txsoft_print(const struct gem_softc *sc, int firstdesc, int lastdesc) 1344 { 1345 int i; 1346 1347 for (i = firstdesc;; i = GEM_NEXTTX(i)) { 1348 printf("descriptor %d:\t", i); 1349 printf("gd_flags: 0x%016" PRIx64 "\t", 1350 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags)); 1351 printf("gd_addr: 0x%016" PRIx64 "\n", 1352 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr)); 1353 if (i == lastdesc) 1354 break; 1355 } 1356 } 1357 #endif 1358 1359 static void 1360 gem_start(struct ifnet *ifp) 1361 { 1362 struct gem_softc *sc = ifp->if_softc; 1363 struct mbuf *m0, *m; 1364 struct gem_txsoft *txs; 1365 bus_dmamap_t dmamap; 1366 int error, firsttx, nexttx = -1, lasttx = -1, ofree, seg; 1367 #ifdef GEM_DEBUG 1368 int otxnext; 1369 #endif 1370 uint64_t flags = 0; 1371 1372 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1373 return; 1374 1375 /* 1376 * Remember the previous number of free descriptors and 1377 * the first descriptor we'll use. 1378 */ 1379 ofree = sc->sc_txfree; 1380 #ifdef GEM_DEBUG 1381 otxnext = sc->sc_txnext; 1382 #endif 1383 1384 DPRINTF(sc, ("%s: gem_start: txfree %d, txnext %d\n", 1385 device_xname(sc->sc_dev), ofree, otxnext)); 1386 1387 /* 1388 * Loop through the send queue, setting up transmit descriptors 1389 * until we drain the queue, or use up all available transmit 1390 * descriptors. 1391 */ 1392 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 1393 sc->sc_txfree != 0) { 1394 /* 1395 * Grab a packet off the queue. 1396 */ 1397 IFQ_POLL(&ifp->if_snd, m0); 1398 if (m0 == NULL) 1399 break; 1400 m = NULL; 1401 1402 dmamap = txs->txs_dmamap; 1403 1404 /* 1405 * Load the DMA map. If this fails, the packet either 1406 * didn't fit in the alloted number of segments, or we were 1407 * short on resources. In this case, we'll copy and try 1408 * again. 1409 */ 1410 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m0, 1411 BUS_DMA_WRITE | BUS_DMA_NOWAIT) != 0 || 1412 (m0->m_pkthdr.len < ETHER_MIN_TX && 1413 dmamap->dm_nsegs == GEM_NTXSEGS)) { 1414 if (m0->m_pkthdr.len > MCLBYTES) { 1415 aprint_error_dev(sc->sc_dev, 1416 "unable to allocate jumbo Tx cluster\n"); 1417 IFQ_DEQUEUE(&ifp->if_snd, m0); 1418 m_freem(m0); 1419 continue; 1420 } 1421 MGETHDR(m, M_DONTWAIT, MT_DATA); 1422 if (m == NULL) { 1423 aprint_error_dev(sc->sc_dev, 1424 "unable to allocate Tx mbuf\n"); 1425 break; 1426 } 1427 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1428 if (m0->m_pkthdr.len > MHLEN) { 1429 MCLGET(m, M_DONTWAIT); 1430 if ((m->m_flags & M_EXT) == 0) { 1431 aprint_error_dev(sc->sc_dev, 1432 "unable to allocate Tx cluster\n"); 1433 m_freem(m); 1434 break; 1435 } 1436 } 1437 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1438 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1439 error = bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, 1440 m, BUS_DMA_WRITE | BUS_DMA_NOWAIT); 1441 if (error) { 1442 aprint_error_dev(sc->sc_dev, 1443 "unable to load Tx buffer, error = %d\n", 1444 error); 1445 break; 1446 } 1447 } 1448 1449 /* 1450 * Ensure we have enough descriptors free to describe 1451 * the packet. 1452 */ 1453 if (dmamap->dm_nsegs > ((m0->m_pkthdr.len < ETHER_MIN_TX) ? 1454 (sc->sc_txfree - 1) : sc->sc_txfree)) { 1455 /* 1456 * Not enough free descriptors to transmit this 1457 * packet. We haven't committed to anything yet, 1458 * so just unload the DMA map, put the packet 1459 * back on the queue, and punt. Notify the upper 1460 * layer that there are no more slots left. 1461 * 1462 * XXX We could allocate an mbuf and copy, but 1463 * XXX it is worth it? 1464 */ 1465 ifp->if_flags |= IFF_OACTIVE; 1466 sc->sc_if_flags = ifp->if_flags; 1467 bus_dmamap_unload(sc->sc_dmatag, dmamap); 1468 if (m != NULL) 1469 m_freem(m); 1470 break; 1471 } 1472 1473 IFQ_DEQUEUE(&ifp->if_snd, m0); 1474 if (m != NULL) { 1475 m_freem(m0); 1476 m0 = m; 1477 } 1478 1479 /* 1480 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1481 */ 1482 1483 /* Sync the DMA map. */ 1484 bus_dmamap_sync(sc->sc_dmatag, dmamap, 0, dmamap->dm_mapsize, 1485 BUS_DMASYNC_PREWRITE); 1486 1487 /* 1488 * Initialize the transmit descriptors. 1489 */ 1490 firsttx = sc->sc_txnext; 1491 for (nexttx = firsttx, seg = 0; 1492 seg < dmamap->dm_nsegs; 1493 seg++, nexttx = GEM_NEXTTX(nexttx)) { 1494 1495 /* 1496 * If this is the first descriptor we're 1497 * enqueueing, set the start of packet flag, 1498 * and the checksum stuff if we want the hardware 1499 * to do it. 1500 */ 1501 sc->sc_txdescs[nexttx].gd_addr = 1502 GEM_DMA_WRITE(sc, dmamap->dm_segs[seg].ds_addr); 1503 flags = dmamap->dm_segs[seg].ds_len & GEM_TD_BUFSIZE; 1504 if (nexttx == firsttx) { 1505 flags |= GEM_TD_START_OF_PACKET; 1506 if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) { 1507 sc->sc_txwin = 0; 1508 flags |= GEM_TD_INTERRUPT_ME; 1509 } 1510 1511 #ifdef INET 1512 /* h/w checksum */ 1513 if (ifp->if_csum_flags_tx & M_CSUM_TCPv4 && 1514 m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1515 struct ether_header *eh; 1516 uint16_t offset, start; 1517 1518 eh = mtod(m0, struct ether_header *); 1519 switch (ntohs(eh->ether_type)) { 1520 case ETHERTYPE_IP: 1521 start = ETHER_HDR_LEN; 1522 break; 1523 case ETHERTYPE_VLAN: 1524 start = ETHER_HDR_LEN + 1525 ETHER_VLAN_ENCAP_LEN; 1526 break; 1527 default: 1528 /* unsupported, drop it */ 1529 m_free(m0); 1530 continue; 1531 } 1532 start += M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 1533 offset = M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data) + start; 1534 flags |= (start << 1535 GEM_TD_CXSUM_STARTSHFT) | 1536 (offset << 1537 GEM_TD_CXSUM_STUFFSHFT) | 1538 GEM_TD_CXSUM_ENABLE; 1539 } 1540 #endif 1541 } 1542 if (seg == dmamap->dm_nsegs - 1) { 1543 flags |= GEM_TD_END_OF_PACKET; 1544 } else { 1545 /* last flag set outside of loop */ 1546 sc->sc_txdescs[nexttx].gd_flags = 1547 GEM_DMA_WRITE(sc, flags); 1548 } 1549 lasttx = nexttx; 1550 } 1551 if (m0->m_pkthdr.len < ETHER_MIN_TX) { 1552 /* add padding buffer at end of chain */ 1553 flags &= ~GEM_TD_END_OF_PACKET; 1554 sc->sc_txdescs[lasttx].gd_flags = 1555 GEM_DMA_WRITE(sc, flags); 1556 1557 sc->sc_txdescs[nexttx].gd_addr = 1558 GEM_DMA_WRITE(sc, 1559 sc->sc_nulldmamap->dm_segs[0].ds_addr); 1560 flags = ((ETHER_MIN_TX - m0->m_pkthdr.len) & 1561 GEM_TD_BUFSIZE) | GEM_TD_END_OF_PACKET; 1562 lasttx = nexttx; 1563 nexttx = GEM_NEXTTX(nexttx); 1564 seg++; 1565 } 1566 sc->sc_txdescs[lasttx].gd_flags = GEM_DMA_WRITE(sc, flags); 1567 1568 KASSERT(lasttx != -1); 1569 1570 /* 1571 * Store a pointer to the packet so we can free it later, 1572 * and remember what txdirty will be once the packet is 1573 * done. 1574 */ 1575 txs->txs_mbuf = m0; 1576 txs->txs_firstdesc = sc->sc_txnext; 1577 txs->txs_lastdesc = lasttx; 1578 txs->txs_ndescs = seg; 1579 1580 #ifdef GEM_DEBUG 1581 if (ifp->if_flags & IFF_DEBUG) { 1582 printf(" gem_start %p transmit chain:\n", txs); 1583 gem_txsoft_print(sc, txs->txs_firstdesc, 1584 txs->txs_lastdesc); 1585 } 1586 #endif 1587 1588 /* Sync the descriptors we're using. */ 1589 GEM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndescs, 1590 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1591 1592 /* Advance the tx pointer. */ 1593 sc->sc_txfree -= txs->txs_ndescs; 1594 sc->sc_txnext = nexttx; 1595 1596 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1597 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1598 1599 /* 1600 * Pass the packet to any BPF listeners. 1601 */ 1602 bpf_mtap(ifp, m0, BPF_D_OUT); 1603 } 1604 1605 if (txs == NULL || sc->sc_txfree == 0) { 1606 /* No more slots left; notify upper layer. */ 1607 ifp->if_flags |= IFF_OACTIVE; 1608 sc->sc_if_flags = ifp->if_flags; 1609 } 1610 1611 if (sc->sc_txfree != ofree) { 1612 DPRINTF(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 1613 device_xname(sc->sc_dev), lasttx, otxnext)); 1614 /* 1615 * The entire packet chain is set up. 1616 * Kick the transmitter. 1617 */ 1618 DPRINTF(sc, ("%s: gem_start: kicking tx %d\n", 1619 device_xname(sc->sc_dev), nexttx)); 1620 bus_space_write_4(sc->sc_bustag, sc->sc_h1, GEM_TX_KICK, 1621 sc->sc_txnext); 1622 1623 /* Set a watchdog timer in case the chip flakes out. */ 1624 ifp->if_timer = 5; 1625 DPRINTF(sc, ("%s: gem_start: watchdog %d\n", 1626 device_xname(sc->sc_dev), ifp->if_timer)); 1627 } 1628 } 1629 1630 /* 1631 * Transmit interrupt. 1632 */ 1633 int 1634 gem_tint(struct gem_softc *sc) 1635 { 1636 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1637 bus_space_tag_t t = sc->sc_bustag; 1638 bus_space_handle_t mac = sc->sc_h1; 1639 struct gem_txsoft *txs; 1640 int txlast; 1641 int progress = 0; 1642 uint32_t v; 1643 1644 DPRINTF(sc, ("%s: gem_tint\n", device_xname(sc->sc_dev))); 1645 1646 /* Unload collision counters ... */ 1647 v = bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) + 1648 bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT); 1649 ifp->if_collisions += v + 1650 bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) + 1651 bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT); 1652 ifp->if_oerrors += v; 1653 1654 /* ... then clear the hardware counters. */ 1655 bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0); 1656 bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0); 1657 bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0); 1658 bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0); 1659 1660 /* 1661 * Go through our Tx list and free mbufs for those 1662 * frames that have been transmitted. 1663 */ 1664 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1665 /* 1666 * In theory, we could harvest some descriptors before 1667 * the ring is empty, but that's a bit complicated. 1668 * 1669 * GEM_TX_COMPLETION points to the last descriptor 1670 * processed +1. 1671 * 1672 * Let's assume that the NIC writes back to the Tx 1673 * descriptors before it updates the completion 1674 * register. If the NIC has posted writes to the 1675 * Tx descriptors, PCI ordering requires that the 1676 * posted writes flush to RAM before the register-read 1677 * finishes. So let's read the completion register, 1678 * before syncing the descriptors, so that we 1679 * examine Tx descriptors that are at least as 1680 * current as the completion register. 1681 */ 1682 txlast = bus_space_read_4(t, mac, GEM_TX_COMPLETION); 1683 DPRINTF(sc, 1684 ("gem_tint: txs->txs_lastdesc = %d, txlast = %d\n", 1685 txs->txs_lastdesc, txlast)); 1686 if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1687 if (txlast >= txs->txs_firstdesc && 1688 txlast <= txs->txs_lastdesc) 1689 break; 1690 } else if (txlast >= txs->txs_firstdesc || 1691 txlast <= txs->txs_lastdesc) 1692 break; 1693 1694 GEM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndescs, 1695 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1696 1697 #ifdef GEM_DEBUG /* XXX DMA synchronization? */ 1698 if (ifp->if_flags & IFF_DEBUG) { 1699 printf(" txsoft %p transmit chain:\n", txs); 1700 gem_txsoft_print(sc, txs->txs_firstdesc, 1701 txs->txs_lastdesc); 1702 } 1703 #endif 1704 1705 1706 DPRINTF(sc, ("gem_tint: releasing a desc\n")); 1707 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1708 1709 sc->sc_txfree += txs->txs_ndescs; 1710 1711 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 1712 0, txs->txs_dmamap->dm_mapsize, 1713 BUS_DMASYNC_POSTWRITE); 1714 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 1715 if (txs->txs_mbuf != NULL) { 1716 m_freem(txs->txs_mbuf); 1717 txs->txs_mbuf = NULL; 1718 } 1719 1720 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1721 1722 ifp->if_opackets++; 1723 progress = 1; 1724 } 1725 1726 #if 0 1727 DPRINTF(sc, ("gem_tint: GEM_TX_STATE_MACHINE %x " 1728 "GEM_TX_DATA_PTR %" PRIx64 "GEM_TX_COMPLETION %" PRIx32 "\n", 1729 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_TX_STATE_MACHINE), 1730 ((uint64_t)bus_space_read_4(sc->sc_bustag, sc->sc_h1, 1731 GEM_TX_DATA_PTR_HI) << 32) | 1732 bus_space_read_4(sc->sc_bustag, sc->sc_h1, 1733 GEM_TX_DATA_PTR_LO), 1734 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_TX_COMPLETION))); 1735 #endif 1736 1737 if (progress) { 1738 if (sc->sc_txfree == GEM_NTXDESC - 1) 1739 sc->sc_txwin = 0; 1740 1741 /* Freed some descriptors, so reset IFF_OACTIVE and restart. */ 1742 ifp->if_flags &= ~IFF_OACTIVE; 1743 sc->sc_if_flags = ifp->if_flags; 1744 ifp->if_timer = SIMPLEQ_EMPTY(&sc->sc_txdirtyq) ? 0 : 5; 1745 if_schedule_deferred_start(ifp); 1746 } 1747 DPRINTF(sc, ("%s: gem_tint: watchdog %d\n", 1748 device_xname(sc->sc_dev), ifp->if_timer)); 1749 1750 return (1); 1751 } 1752 1753 /* 1754 * Receive interrupt. 1755 */ 1756 int 1757 gem_rint(struct gem_softc *sc) 1758 { 1759 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1760 bus_space_tag_t t = sc->sc_bustag; 1761 bus_space_handle_t h = sc->sc_h1; 1762 struct gem_rxsoft *rxs; 1763 struct mbuf *m; 1764 uint64_t rxstat; 1765 uint32_t rxcomp; 1766 int i, len, progress = 0; 1767 1768 DPRINTF(sc, ("%s: gem_rint\n", device_xname(sc->sc_dev))); 1769 1770 /* 1771 * Ignore spurious interrupt that sometimes occurs before 1772 * we are set up when we network boot. 1773 */ 1774 if (!sc->sc_meminited) 1775 return 1; 1776 1777 /* 1778 * Read the completion register once. This limits 1779 * how long the following loop can execute. 1780 */ 1781 rxcomp = bus_space_read_4(t, h, GEM_RX_COMPLETION); 1782 1783 /* 1784 * XXX Read the lastrx only once at the top for speed. 1785 */ 1786 DPRINTF(sc, ("gem_rint: sc->rxptr %d, complete %d\n", 1787 sc->sc_rxptr, rxcomp)); 1788 1789 /* 1790 * Go into the loop at least once. 1791 */ 1792 for (i = sc->sc_rxptr; i == sc->sc_rxptr || i != rxcomp; 1793 i = GEM_NEXTRX(i)) { 1794 rxs = &sc->sc_rxsoft[i]; 1795 1796 GEM_CDRXSYNC(sc, i, 1797 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1798 1799 rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags); 1800 1801 if (rxstat & GEM_RD_OWN) { 1802 GEM_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); 1803 /* 1804 * We have processed all of the receive buffers. 1805 */ 1806 break; 1807 } 1808 1809 progress++; 1810 1811 if (rxstat & GEM_RD_BAD_CRC) { 1812 ifp->if_ierrors++; 1813 aprint_error_dev(sc->sc_dev, 1814 "receive error: CRC error\n"); 1815 GEM_INIT_RXDESC(sc, i); 1816 continue; 1817 } 1818 1819 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1820 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1821 #ifdef GEM_DEBUG 1822 if (ifp->if_flags & IFF_DEBUG) { 1823 printf(" rxsoft %p descriptor %d: ", rxs, i); 1824 printf("gd_flags: 0x%016llx\t", (long long) 1825 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags)); 1826 printf("gd_addr: 0x%016llx\n", (long long) 1827 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr)); 1828 } 1829 #endif 1830 1831 /* No errors; receive the packet. */ 1832 len = GEM_RD_BUFLEN(rxstat); 1833 1834 /* 1835 * Allocate a new mbuf cluster. If that fails, we are 1836 * out of memory, and must drop the packet and recycle 1837 * the buffer that's already attached to this descriptor. 1838 */ 1839 m = rxs->rxs_mbuf; 1840 if (gem_add_rxbuf(sc, i) != 0) { 1841 GEM_COUNTER_INCR(sc, sc_ev_rxnobuf); 1842 ifp->if_ierrors++; 1843 aprint_error_dev(sc->sc_dev, 1844 "receive error: RX no buffer space\n"); 1845 GEM_INIT_RXDESC(sc, i); 1846 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1847 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1848 continue; 1849 } 1850 m->m_data += 2; /* We're already off by two */ 1851 1852 m_set_rcvif(m, ifp); 1853 m->m_pkthdr.len = m->m_len = len; 1854 1855 #ifdef INET 1856 /* hardware checksum */ 1857 if (ifp->if_csum_flags_rx & M_CSUM_TCPv4) { 1858 struct ether_header *eh; 1859 struct ip *ip; 1860 int32_t hlen, pktlen; 1861 1862 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1863 pktlen = m->m_pkthdr.len - ETHER_HDR_LEN - 1864 ETHER_VLAN_ENCAP_LEN; 1865 eh = (struct ether_header *) (mtod(m, char *) + 1866 ETHER_VLAN_ENCAP_LEN); 1867 } else { 1868 pktlen = m->m_pkthdr.len - ETHER_HDR_LEN; 1869 eh = mtod(m, struct ether_header *); 1870 } 1871 if (ntohs(eh->ether_type) != ETHERTYPE_IP) 1872 goto swcsum; 1873 ip = (struct ip *) ((char *)eh + ETHER_HDR_LEN); 1874 1875 /* IPv4 only */ 1876 if (ip->ip_v != IPVERSION) 1877 goto swcsum; 1878 1879 hlen = ip->ip_hl << 2; 1880 if (hlen < sizeof(struct ip)) 1881 goto swcsum; 1882 1883 /* 1884 * bail if too short, has random trailing garbage, 1885 * truncated, fragment, or has ethernet pad. 1886 */ 1887 if ((ntohs(ip->ip_len) < hlen) || 1888 (ntohs(ip->ip_len) != pktlen) || 1889 (ntohs(ip->ip_off) & (IP_MF | IP_OFFMASK))) 1890 goto swcsum; 1891 1892 switch (ip->ip_p) { 1893 case IPPROTO_TCP: 1894 if (! (ifp->if_csum_flags_rx & M_CSUM_TCPv4)) 1895 goto swcsum; 1896 if (pktlen < (hlen + sizeof(struct tcphdr))) 1897 goto swcsum; 1898 m->m_pkthdr.csum_flags = M_CSUM_TCPv4; 1899 break; 1900 case IPPROTO_UDP: 1901 /* FALLTHROUGH */ 1902 default: 1903 goto swcsum; 1904 } 1905 1906 /* the uncomplemented sum is expected */ 1907 m->m_pkthdr.csum_data = (~rxstat) & GEM_RD_CHECKSUM; 1908 1909 /* if the pkt had ip options, we have to deduct them */ 1910 if (hlen > sizeof(struct ip)) { 1911 uint16_t *opts; 1912 uint32_t optsum, temp; 1913 1914 optsum = 0; 1915 temp = hlen - sizeof(struct ip); 1916 opts = (uint16_t *) ((char *) ip + 1917 sizeof(struct ip)); 1918 1919 while (temp > 1) { 1920 optsum += ntohs(*opts++); 1921 temp -= 2; 1922 } 1923 while (optsum >> 16) 1924 optsum = (optsum >> 16) + 1925 (optsum & 0xffff); 1926 1927 /* Deduct ip opts sum from hwsum. */ 1928 m->m_pkthdr.csum_data += (uint16_t)~optsum; 1929 1930 while (m->m_pkthdr.csum_data >> 16) 1931 m->m_pkthdr.csum_data = 1932 (m->m_pkthdr.csum_data >> 16) + 1933 (m->m_pkthdr.csum_data & 1934 0xffff); 1935 } 1936 1937 m->m_pkthdr.csum_flags |= M_CSUM_DATA | 1938 M_CSUM_NO_PSEUDOHDR; 1939 } else 1940 swcsum: 1941 m->m_pkthdr.csum_flags = 0; 1942 #endif 1943 /* Pass it on. */ 1944 if_percpuq_enqueue(ifp->if_percpuq, m); 1945 } 1946 1947 if (progress) { 1948 /* Update the receive pointer. */ 1949 if (i == sc->sc_rxptr) { 1950 GEM_COUNTER_INCR(sc, sc_ev_rxfull); 1951 #ifdef GEM_DEBUG 1952 if (ifp->if_flags & IFF_DEBUG) 1953 printf("%s: rint: ring wrap\n", 1954 device_xname(sc->sc_dev)); 1955 #endif 1956 } 1957 sc->sc_rxptr = i; 1958 bus_space_write_4(t, h, GEM_RX_KICK, GEM_PREVRX(i)); 1959 } 1960 #ifdef GEM_COUNTERS 1961 if (progress <= 4) { 1962 GEM_COUNTER_INCR(sc, sc_ev_rxhist[progress]); 1963 } else if (progress < 32) { 1964 if (progress < 16) 1965 GEM_COUNTER_INCR(sc, sc_ev_rxhist[5]); 1966 else 1967 GEM_COUNTER_INCR(sc, sc_ev_rxhist[6]); 1968 1969 } else { 1970 if (progress < 64) 1971 GEM_COUNTER_INCR(sc, sc_ev_rxhist[7]); 1972 else 1973 GEM_COUNTER_INCR(sc, sc_ev_rxhist[8]); 1974 } 1975 #endif 1976 1977 DPRINTF(sc, ("gem_rint: done sc->rxptr %d, complete %d\n", 1978 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION))); 1979 1980 /* Read error counters ... */ 1981 ifp->if_ierrors += 1982 bus_space_read_4(t, h, GEM_MAC_RX_LEN_ERR_CNT) + 1983 bus_space_read_4(t, h, GEM_MAC_RX_ALIGN_ERR) + 1984 bus_space_read_4(t, h, GEM_MAC_RX_CRC_ERR_CNT) + 1985 bus_space_read_4(t, h, GEM_MAC_RX_CODE_VIOL); 1986 1987 /* ... then clear the hardware counters. */ 1988 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 1989 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 1990 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 1991 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 1992 1993 return (1); 1994 } 1995 1996 1997 /* 1998 * gem_add_rxbuf: 1999 * 2000 * Add a receive buffer to the indicated descriptor. 2001 */ 2002 int 2003 gem_add_rxbuf(struct gem_softc *sc, int idx) 2004 { 2005 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2006 struct mbuf *m; 2007 int error; 2008 2009 MGETHDR(m, M_DONTWAIT, MT_DATA); 2010 if (m == NULL) 2011 return (ENOBUFS); 2012 2013 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2014 MCLGET(m, M_DONTWAIT); 2015 if ((m->m_flags & M_EXT) == 0) { 2016 m_freem(m); 2017 return (ENOBUFS); 2018 } 2019 2020 #ifdef GEM_DEBUG 2021 /* bzero the packet to check DMA */ 2022 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 2023 #endif 2024 2025 if (rxs->rxs_mbuf != NULL) 2026 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 2027 2028 rxs->rxs_mbuf = m; 2029 2030 error = bus_dmamap_load(sc->sc_dmatag, rxs->rxs_dmamap, 2031 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2032 BUS_DMA_READ | BUS_DMA_NOWAIT); 2033 if (error) { 2034 aprint_error_dev(sc->sc_dev, 2035 "can't load rx DMA map %d, error = %d\n", idx, error); 2036 panic("gem_add_rxbuf"); /* XXX */ 2037 } 2038 2039 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 2040 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2041 2042 GEM_INIT_RXDESC(sc, idx); 2043 2044 return (0); 2045 } 2046 2047 2048 int 2049 gem_eint(struct gem_softc *sc, u_int status) 2050 { 2051 char bits[128]; 2052 uint32_t r, v; 2053 2054 if ((status & GEM_INTR_MIF) != 0) { 2055 printf("%s: XXXlink status changed\n", device_xname(sc->sc_dev)); 2056 return (1); 2057 } 2058 2059 if ((status & GEM_INTR_RX_TAG_ERR) != 0) { 2060 gem_reset_rxdma(sc); 2061 return (1); 2062 } 2063 2064 if (status & GEM_INTR_BERR) { 2065 if (sc->sc_flags & GEM_PCI) 2066 r = GEM_ERROR_STATUS; 2067 else 2068 r = GEM_SBUS_ERROR_STATUS; 2069 bus_space_read_4(sc->sc_bustag, sc->sc_h2, r); 2070 v = bus_space_read_4(sc->sc_bustag, sc->sc_h2, r); 2071 aprint_error_dev(sc->sc_dev, "bus error interrupt: 0x%02x\n", 2072 v); 2073 return (1); 2074 } 2075 snprintb(bits, sizeof(bits), GEM_INTR_BITS, status); 2076 printf("%s: status=%s\n", device_xname(sc->sc_dev), bits); 2077 2078 return (1); 2079 } 2080 2081 2082 /* 2083 * PCS interrupts. 2084 * We should receive these when the link status changes, but sometimes 2085 * we don't receive them for link up. We compensate for this in the 2086 * gem_tick() callout. 2087 */ 2088 int 2089 gem_pint(struct gem_softc *sc) 2090 { 2091 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2092 bus_space_tag_t t = sc->sc_bustag; 2093 bus_space_handle_t h = sc->sc_h1; 2094 uint32_t v, v2; 2095 2096 /* 2097 * Clear the PCS interrupt from GEM_STATUS. The PCS register is 2098 * latched, so we have to read it twice. There is only one bit in 2099 * use, so the value is meaningless. 2100 */ 2101 bus_space_read_4(t, h, GEM_MII_INTERRUP_STATUS); 2102 bus_space_read_4(t, h, GEM_MII_INTERRUP_STATUS); 2103 2104 if ((ifp->if_flags & IFF_UP) == 0) 2105 return 1; 2106 2107 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) 2108 return 1; 2109 2110 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2111 /* If we see remote fault, our link partner is probably going away */ 2112 if ((v & GEM_MII_STATUS_REM_FLT) != 0) { 2113 gem_bitwait(sc, h, GEM_MII_STATUS, GEM_MII_STATUS_REM_FLT, 0); 2114 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2115 /* Otherwise, we may need to wait after auto-negotiation completes */ 2116 } else if ((v & (GEM_MII_STATUS_LINK_STS | GEM_MII_STATUS_ANEG_CPT)) == 2117 GEM_MII_STATUS_ANEG_CPT) { 2118 gem_bitwait(sc, h, GEM_MII_STATUS, 0, GEM_MII_STATUS_LINK_STS); 2119 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2120 } 2121 if ((v & GEM_MII_STATUS_LINK_STS) != 0) { 2122 if (sc->sc_flags & GEM_LINK) { 2123 return 1; 2124 } 2125 callout_stop(&sc->sc_tick_ch); 2126 v = bus_space_read_4(t, h, GEM_MII_ANAR); 2127 v2 = bus_space_read_4(t, h, GEM_MII_ANLPAR); 2128 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_1000_SX; 2129 sc->sc_mii.mii_media_status = IFM_AVALID | IFM_ACTIVE; 2130 v &= v2; 2131 if (v & GEM_MII_ANEG_FUL_DUPLX) { 2132 sc->sc_mii.mii_media_active |= IFM_FDX; 2133 #ifdef GEM_DEBUG 2134 aprint_debug_dev(sc->sc_dev, "link up: full duplex\n"); 2135 #endif 2136 } else if (v & GEM_MII_ANEG_HLF_DUPLX) { 2137 sc->sc_mii.mii_media_active |= IFM_HDX; 2138 #ifdef GEM_DEBUG 2139 aprint_debug_dev(sc->sc_dev, "link up: half duplex\n"); 2140 #endif 2141 } else { 2142 #ifdef GEM_DEBUG 2143 aprint_debug_dev(sc->sc_dev, "duplex mismatch\n"); 2144 #endif 2145 } 2146 gem_statuschange(sc); 2147 } else { 2148 if ((sc->sc_flags & GEM_LINK) == 0) { 2149 return 1; 2150 } 2151 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_NONE; 2152 sc->sc_mii.mii_media_status = IFM_AVALID; 2153 #ifdef GEM_DEBUG 2154 aprint_debug_dev(sc->sc_dev, "link down\n"); 2155 #endif 2156 gem_statuschange(sc); 2157 2158 /* Start the 10 second timer */ 2159 callout_reset(&sc->sc_tick_ch, hz * 10, gem_tick, sc); 2160 } 2161 return 1; 2162 } 2163 2164 2165 2166 int 2167 gem_intr(void *v) 2168 { 2169 struct gem_softc *sc = v; 2170 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2171 bus_space_tag_t t = sc->sc_bustag; 2172 bus_space_handle_t h = sc->sc_h1; 2173 uint32_t status; 2174 int r = 0; 2175 #ifdef GEM_DEBUG 2176 char bits[128]; 2177 #endif 2178 2179 /* XXX We should probably mask out interrupts until we're done */ 2180 2181 sc->sc_ev_intr.ev_count++; 2182 2183 status = bus_space_read_4(t, h, GEM_STATUS); 2184 #ifdef GEM_DEBUG 2185 snprintb(bits, sizeof(bits), GEM_INTR_BITS, status); 2186 #endif 2187 DPRINTF(sc, ("%s: gem_intr: cplt 0x%x status %s\n", 2188 device_xname(sc->sc_dev), (status >> 19), bits)); 2189 2190 if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0) 2191 r |= gem_eint(sc, status); 2192 2193 /* We don't bother with GEM_INTR_TX_DONE */ 2194 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) { 2195 GEM_COUNTER_INCR(sc, sc_ev_txint); 2196 r |= gem_tint(sc); 2197 } 2198 2199 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) { 2200 GEM_COUNTER_INCR(sc, sc_ev_rxint); 2201 r |= gem_rint(sc); 2202 } 2203 2204 /* We should eventually do more than just print out error stats. */ 2205 if (status & GEM_INTR_TX_MAC) { 2206 int txstat = bus_space_read_4(t, h, GEM_MAC_TX_STATUS); 2207 if (txstat & ~GEM_MAC_TX_XMIT_DONE) 2208 printf("%s: MAC tx fault, status %x\n", 2209 device_xname(sc->sc_dev), txstat); 2210 if (txstat & (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG)) 2211 gem_init(ifp); 2212 } 2213 if (status & GEM_INTR_RX_MAC) { 2214 int rxstat = bus_space_read_4(t, h, GEM_MAC_RX_STATUS); 2215 /* 2216 * At least with GEM_SUN_GEM and some GEM_SUN_ERI 2217 * revisions GEM_MAC_RX_OVERFLOW happen often due to a 2218 * silicon bug so handle them silently. So if we detect 2219 * an RX FIFO overflow, we fire off a timer, and check 2220 * whether we're still making progress by looking at the 2221 * RX FIFO write and read pointers. 2222 */ 2223 if (rxstat & GEM_MAC_RX_OVERFLOW) { 2224 ifp->if_ierrors++; 2225 aprint_error_dev(sc->sc_dev, 2226 "receive error: RX overflow sc->rxptr %d, complete %d\n", sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION)); 2227 sc->sc_rx_fifo_wr_ptr = 2228 bus_space_read_4(t, h, GEM_RX_FIFO_WR_PTR); 2229 sc->sc_rx_fifo_rd_ptr = 2230 bus_space_read_4(t, h, GEM_RX_FIFO_RD_PTR); 2231 callout_schedule(&sc->sc_rx_watchdog, 400); 2232 } else if (rxstat & ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT)) 2233 printf("%s: MAC rx fault, status 0x%02x\n", 2234 device_xname(sc->sc_dev), rxstat); 2235 } 2236 if (status & GEM_INTR_PCS) { 2237 r |= gem_pint(sc); 2238 } 2239 2240 /* Do we need to do anything with these? 2241 if ((status & GEM_MAC_CONTROL_STATUS) != 0) { 2242 status2 = bus_read_4(sc->sc_res[0], GEM_MAC_CONTROL_STATUS); 2243 if ((status2 & GEM_MAC_PAUSED) != 0) 2244 aprintf_debug_dev(sc->sc_dev, "PAUSE received (%d slots)\n", 2245 GEM_MAC_PAUSE_TIME(status2)); 2246 if ((status2 & GEM_MAC_PAUSE) != 0) 2247 aprintf_debug_dev(sc->sc_dev, "transited to PAUSE state\n"); 2248 if ((status2 & GEM_MAC_RESUME) != 0) 2249 aprintf_debug_dev(sc->sc_dev, "transited to non-PAUSE state\n"); 2250 } 2251 if ((status & GEM_INTR_MIF) != 0) 2252 aprintf_debug_dev(sc->sc_dev, "MIF interrupt\n"); 2253 */ 2254 rnd_add_uint32(&sc->rnd_source, status); 2255 return (r); 2256 } 2257 2258 void 2259 gem_rx_watchdog(void *arg) 2260 { 2261 struct gem_softc *sc = arg; 2262 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2263 bus_space_tag_t t = sc->sc_bustag; 2264 bus_space_handle_t h = sc->sc_h1; 2265 uint32_t rx_fifo_wr_ptr; 2266 uint32_t rx_fifo_rd_ptr; 2267 uint32_t state; 2268 2269 if ((ifp->if_flags & IFF_RUNNING) == 0) { 2270 aprint_error_dev(sc->sc_dev, "receiver not running\n"); 2271 return; 2272 } 2273 2274 rx_fifo_wr_ptr = bus_space_read_4(t, h, GEM_RX_FIFO_WR_PTR); 2275 rx_fifo_rd_ptr = bus_space_read_4(t, h, GEM_RX_FIFO_RD_PTR); 2276 state = bus_space_read_4(t, h, GEM_MAC_MAC_STATE); 2277 if ((state & GEM_MAC_STATE_OVERFLOW) == GEM_MAC_STATE_OVERFLOW && 2278 ((rx_fifo_wr_ptr == rx_fifo_rd_ptr) || 2279 ((sc->sc_rx_fifo_wr_ptr == rx_fifo_wr_ptr) && 2280 (sc->sc_rx_fifo_rd_ptr == rx_fifo_rd_ptr)))) 2281 { 2282 /* 2283 * The RX state machine is still in overflow state and 2284 * the RX FIFO write and read pointers seem to be 2285 * stuck. Whack the chip over the head to get things 2286 * going again. 2287 */ 2288 aprint_error_dev(sc->sc_dev, 2289 "receiver stuck in overflow, resetting\n"); 2290 gem_init(ifp); 2291 } else { 2292 if ((state & GEM_MAC_STATE_OVERFLOW) != GEM_MAC_STATE_OVERFLOW) { 2293 aprint_error_dev(sc->sc_dev, 2294 "rx_watchdog: not in overflow state: 0x%x\n", 2295 state); 2296 } 2297 if (rx_fifo_wr_ptr != rx_fifo_rd_ptr) { 2298 aprint_error_dev(sc->sc_dev, 2299 "rx_watchdog: wr & rd ptr different\n"); 2300 } 2301 if (sc->sc_rx_fifo_wr_ptr != rx_fifo_wr_ptr) { 2302 aprint_error_dev(sc->sc_dev, 2303 "rx_watchdog: wr pointer != saved\n"); 2304 } 2305 if (sc->sc_rx_fifo_rd_ptr != rx_fifo_rd_ptr) { 2306 aprint_error_dev(sc->sc_dev, 2307 "rx_watchdog: rd pointer != saved\n"); 2308 } 2309 aprint_error_dev(sc->sc_dev, "resetting anyway\n"); 2310 gem_init(ifp); 2311 } 2312 } 2313 2314 void 2315 gem_watchdog(struct ifnet *ifp) 2316 { 2317 struct gem_softc *sc = ifp->if_softc; 2318 2319 DPRINTF(sc, ("gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x " 2320 "GEM_MAC_RX_CONFIG %x\n", 2321 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_RX_CONFIG), 2322 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_MAC_RX_STATUS), 2323 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_MAC_RX_CONFIG))); 2324 2325 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 2326 ++ifp->if_oerrors; 2327 2328 /* Try to get more packets going. */ 2329 gem_init(ifp); 2330 gem_start(ifp); 2331 } 2332 2333 /* 2334 * Initialize the MII Management Interface 2335 */ 2336 void 2337 gem_mifinit(struct gem_softc *sc) 2338 { 2339 bus_space_tag_t t = sc->sc_bustag; 2340 bus_space_handle_t mif = sc->sc_h1; 2341 2342 /* Configure the MIF in frame mode */ 2343 sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 2344 sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA; 2345 bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config); 2346 } 2347 2348 /* 2349 * MII interface 2350 * 2351 * The GEM MII interface supports at least three different operating modes: 2352 * 2353 * Bitbang mode is implemented using data, clock and output enable registers. 2354 * 2355 * Frame mode is implemented by loading a complete frame into the frame 2356 * register and polling the valid bit for completion. 2357 * 2358 * Polling mode uses the frame register but completion is indicated by 2359 * an interrupt. 2360 * 2361 */ 2362 static int 2363 gem_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 2364 { 2365 struct gem_softc *sc = device_private(self); 2366 bus_space_tag_t t = sc->sc_bustag; 2367 bus_space_handle_t mif = sc->sc_h1; 2368 int n; 2369 uint32_t v; 2370 2371 #ifdef GEM_DEBUG1 2372 if (sc->sc_debug) 2373 printf("gem_mii_readreg: PHY %d reg %d\n", phy, reg); 2374 #endif 2375 2376 /* Construct the frame command */ 2377 v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) | 2378 GEM_MIF_FRAME_READ; 2379 2380 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 2381 for (n = 0; n < 100; n++) { 2382 DELAY(1); 2383 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 2384 if (v & GEM_MIF_FRAME_TA0) { 2385 *val = v & GEM_MIF_FRAME_DATA; 2386 return 0; 2387 } 2388 } 2389 2390 printf("%s: mii_read timeout\n", device_xname(sc->sc_dev)); 2391 return ETIMEDOUT; 2392 } 2393 2394 static int 2395 gem_mii_writereg(device_t self, int phy, int reg, uint16_t val) 2396 { 2397 struct gem_softc *sc = device_private(self); 2398 bus_space_tag_t t = sc->sc_bustag; 2399 bus_space_handle_t mif = sc->sc_h1; 2400 int n; 2401 uint32_t v; 2402 2403 #ifdef GEM_DEBUG1 2404 if (sc->sc_debug) 2405 printf("gem_mii_writereg: PHY %d reg %d val %x\n", 2406 phy, reg, val); 2407 #endif 2408 2409 /* Construct the frame command */ 2410 v = GEM_MIF_FRAME_WRITE | 2411 (phy << GEM_MIF_PHY_SHIFT) | 2412 (reg << GEM_MIF_REG_SHIFT) | 2413 (val & GEM_MIF_FRAME_DATA); 2414 2415 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 2416 for (n = 0; n < 100; n++) { 2417 DELAY(1); 2418 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 2419 if (v & GEM_MIF_FRAME_TA0) 2420 return 0; 2421 } 2422 2423 printf("%s: mii_write timeout\n", device_xname(sc->sc_dev)); 2424 return ETIMEDOUT; 2425 } 2426 2427 static void 2428 gem_mii_statchg(struct ifnet *ifp) 2429 { 2430 struct gem_softc *sc = ifp->if_softc; 2431 #ifdef GEM_DEBUG 2432 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 2433 #endif 2434 2435 #ifdef GEM_DEBUG 2436 if (sc->sc_debug) 2437 printf("gem_mii_statchg: status change: phy = %d\n", 2438 sc->sc_phys[instance]); 2439 #endif 2440 gem_statuschange(sc); 2441 } 2442 2443 /* 2444 * Common status change for gem_mii_statchg() and gem_pint() 2445 */ 2446 void 2447 gem_statuschange(struct gem_softc* sc) 2448 { 2449 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2450 bus_space_tag_t t = sc->sc_bustag; 2451 bus_space_handle_t mac = sc->sc_h1; 2452 int gigabit; 2453 uint32_t rxcfg, txcfg, v; 2454 2455 if ((sc->sc_mii.mii_media_status & IFM_ACTIVE) != 0 && 2456 IFM_SUBTYPE(sc->sc_mii.mii_media_active) != IFM_NONE) 2457 sc->sc_flags |= GEM_LINK; 2458 else 2459 sc->sc_flags &= ~GEM_LINK; 2460 2461 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 2462 gigabit = 1; 2463 else 2464 gigabit = 0; 2465 2466 /* 2467 * The configuration done here corresponds to the steps F) and 2468 * G) and as far as enabling of RX and TX MAC goes also step H) 2469 * of the initialization sequence outlined in section 3.2.1 of 2470 * the GEM Gigabit Ethernet ASIC Specification. 2471 */ 2472 2473 rxcfg = bus_space_read_4(t, mac, GEM_MAC_RX_CONFIG); 2474 rxcfg &= ~(GEM_MAC_RX_CARR_EXTEND | GEM_MAC_RX_ENABLE); 2475 txcfg = GEM_MAC_TX_ENA_IPG0 | GEM_MAC_TX_NGU | GEM_MAC_TX_NGU_LIMIT; 2476 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 2477 txcfg |= GEM_MAC_TX_IGN_CARRIER | GEM_MAC_TX_IGN_COLLIS; 2478 else if (gigabit) { 2479 rxcfg |= GEM_MAC_RX_CARR_EXTEND; 2480 txcfg |= GEM_MAC_RX_CARR_EXTEND; 2481 } 2482 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0); 2483 bus_space_barrier(t, mac, GEM_MAC_TX_CONFIG, 4, 2484 BUS_SPACE_BARRIER_WRITE); 2485 if (!gem_bitwait(sc, mac, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)) 2486 aprint_normal_dev(sc->sc_dev, "cannot disable TX MAC\n"); 2487 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, txcfg); 2488 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, 0); 2489 bus_space_barrier(t, mac, GEM_MAC_RX_CONFIG, 4, 2490 BUS_SPACE_BARRIER_WRITE); 2491 if (!gem_bitwait(sc, mac, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)) 2492 aprint_normal_dev(sc->sc_dev, "cannot disable RX MAC\n"); 2493 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, rxcfg); 2494 2495 v = bus_space_read_4(t, mac, GEM_MAC_CONTROL_CONFIG) & 2496 ~(GEM_MAC_CC_RX_PAUSE | GEM_MAC_CC_TX_PAUSE); 2497 bus_space_write_4(t, mac, GEM_MAC_CONTROL_CONFIG, v); 2498 2499 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) == 0 && 2500 gigabit != 0) 2501 bus_space_write_4(t, mac, GEM_MAC_SLOT_TIME, 2502 GEM_MAC_SLOT_TIME_CARR_EXTEND); 2503 else 2504 bus_space_write_4(t, mac, GEM_MAC_SLOT_TIME, 2505 GEM_MAC_SLOT_TIME_NORMAL); 2506 2507 /* XIF Configuration */ 2508 if (sc->sc_flags & GEM_LINK) 2509 v = GEM_MAC_XIF_LINK_LED; 2510 else 2511 v = 0; 2512 v |= GEM_MAC_XIF_TX_MII_ENA; 2513 2514 /* If an external transceiver is connected, enable its MII drivers */ 2515 sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG); 2516 if ((sc->sc_flags &(GEM_SERDES | GEM_SERIAL)) == 0) { 2517 if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) { 2518 if (gigabit) 2519 v |= GEM_MAC_XIF_GMII_MODE; 2520 else 2521 v &= ~GEM_MAC_XIF_GMII_MODE; 2522 } else 2523 /* Internal MII needs buf enable */ 2524 v |= GEM_MAC_XIF_MII_BUF_ENA; 2525 /* MII needs echo disable if half duplex. */ 2526 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 2527 /* turn on full duplex LED */ 2528 v |= GEM_MAC_XIF_FDPLX_LED; 2529 else 2530 /* half duplex -- disable echo */ 2531 v |= GEM_MAC_XIF_ECHO_DISABL; 2532 } else { 2533 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 2534 v |= GEM_MAC_XIF_FDPLX_LED; 2535 v |= GEM_MAC_XIF_GMII_MODE; 2536 } 2537 bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v); 2538 2539 if ((ifp->if_flags & IFF_RUNNING) != 0 && 2540 (sc->sc_flags & GEM_LINK) != 0) { 2541 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 2542 txcfg | GEM_MAC_TX_ENABLE); 2543 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, 2544 rxcfg | GEM_MAC_RX_ENABLE); 2545 } 2546 } 2547 2548 int 2549 gem_ser_mediachange(struct ifnet *ifp) 2550 { 2551 struct gem_softc *sc = ifp->if_softc; 2552 u_int s, t; 2553 2554 if (IFM_TYPE(sc->sc_mii.mii_media.ifm_media) != IFM_ETHER) 2555 return EINVAL; 2556 2557 s = IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media); 2558 if (s == IFM_AUTO) { 2559 if (sc->sc_mii_media != s) { 2560 #ifdef GEM_DEBUG 2561 aprint_debug_dev(sc->sc_dev, "setting media to auto\n"); 2562 #endif 2563 sc->sc_mii_media = s; 2564 if (ifp->if_flags & IFF_UP) { 2565 gem_pcs_stop(sc, 0); 2566 gem_pcs_start(sc); 2567 } 2568 } 2569 return 0; 2570 } 2571 if (s == IFM_1000_SX) { 2572 t = IFM_OPTIONS(sc->sc_mii.mii_media.ifm_media) 2573 & (IFM_FDX | IFM_HDX); 2574 if ((sc->sc_mii_media & (IFM_FDX | IFM_HDX)) != t) { 2575 sc->sc_mii_media &= ~(IFM_FDX | IFM_HDX); 2576 sc->sc_mii_media |= t; 2577 #ifdef GEM_DEBUG 2578 aprint_debug_dev(sc->sc_dev, 2579 "setting media to 1000baseSX-%s\n", 2580 t == IFM_FDX ? "FDX" : "HDX"); 2581 #endif 2582 if (ifp->if_flags & IFF_UP) { 2583 gem_pcs_stop(sc, 0); 2584 gem_pcs_start(sc); 2585 } 2586 } 2587 return 0; 2588 } 2589 return EINVAL; 2590 } 2591 2592 void 2593 gem_ser_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2594 { 2595 struct gem_softc *sc = ifp->if_softc; 2596 2597 if ((ifp->if_flags & IFF_UP) == 0) 2598 return; 2599 ifmr->ifm_active = sc->sc_mii.mii_media_active; 2600 ifmr->ifm_status = sc->sc_mii.mii_media_status; 2601 } 2602 2603 static int 2604 gem_ifflags_cb(struct ethercom *ec) 2605 { 2606 struct ifnet *ifp = &ec->ec_if; 2607 struct gem_softc *sc = ifp->if_softc; 2608 int change = ifp->if_flags ^ sc->sc_if_flags; 2609 2610 if ((change & ~(IFF_CANTCHANGE | IFF_DEBUG)) != 0) 2611 return ENETRESET; 2612 else if ((change & IFF_PROMISC) != 0) 2613 gem_setladrf(sc); 2614 return 0; 2615 } 2616 2617 /* 2618 * Process an ioctl request. 2619 */ 2620 int 2621 gem_ioctl(struct ifnet *ifp, unsigned long cmd, void *data) 2622 { 2623 struct gem_softc *sc = ifp->if_softc; 2624 int s, error = 0; 2625 2626 s = splnet(); 2627 2628 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2629 error = 0; 2630 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 2631 ; 2632 else if (ifp->if_flags & IFF_RUNNING) { 2633 /* 2634 * Multicast list has changed; set the hardware filter 2635 * accordingly. 2636 */ 2637 gem_setladrf(sc); 2638 } 2639 } 2640 2641 /* Try to get things going again */ 2642 if (ifp->if_flags & IFF_UP) 2643 gem_start(ifp); 2644 splx(s); 2645 return (error); 2646 } 2647 2648 static void 2649 gem_inten(struct gem_softc *sc) 2650 { 2651 bus_space_tag_t t = sc->sc_bustag; 2652 bus_space_handle_t h = sc->sc_h1; 2653 uint32_t v; 2654 2655 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 2656 v = GEM_INTR_PCS; 2657 else 2658 v = GEM_INTR_MIF; 2659 bus_space_write_4(t, h, GEM_INTMASK, 2660 ~(GEM_INTR_TX_INTME | 2661 GEM_INTR_TX_EMPTY | 2662 GEM_INTR_TX_MAC | 2663 GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF | 2664 GEM_INTR_RX_TAG_ERR | GEM_INTR_MAC_CONTROL | 2665 GEM_INTR_BERR | v)); 2666 } 2667 2668 bool 2669 gem_resume(device_t self, const pmf_qual_t *qual) 2670 { 2671 struct gem_softc *sc = device_private(self); 2672 2673 gem_inten(sc); 2674 2675 return true; 2676 } 2677 2678 bool 2679 gem_suspend(device_t self, const pmf_qual_t *qual) 2680 { 2681 struct gem_softc *sc = device_private(self); 2682 bus_space_tag_t t = sc->sc_bustag; 2683 bus_space_handle_t h = sc->sc_h1; 2684 2685 bus_space_write_4(t, h, GEM_INTMASK, ~(uint32_t)0); 2686 2687 return true; 2688 } 2689 2690 bool 2691 gem_shutdown(device_t self, int howto) 2692 { 2693 struct gem_softc *sc = device_private(self); 2694 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2695 2696 gem_stop(ifp, 1); 2697 2698 return true; 2699 } 2700 2701 /* 2702 * Set up the logical address filter. 2703 */ 2704 void 2705 gem_setladrf(struct gem_softc *sc) 2706 { 2707 struct ethercom *ec = &sc->sc_ethercom; 2708 struct ifnet *ifp = &ec->ec_if; 2709 struct ether_multi *enm; 2710 struct ether_multistep step; 2711 bus_space_tag_t t = sc->sc_bustag; 2712 bus_space_handle_t h = sc->sc_h1; 2713 uint32_t crc; 2714 uint32_t hash[16]; 2715 uint32_t v; 2716 int i; 2717 2718 /* Get current RX configuration */ 2719 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 2720 2721 /* 2722 * Turn off promiscuous mode, promiscuous group mode (all multicast), 2723 * and hash filter. Depending on the case, the right bit will be 2724 * enabled. 2725 */ 2726 v &= ~(GEM_MAC_RX_PROMISCUOUS | GEM_MAC_RX_HASH_FILTER | 2727 GEM_MAC_RX_PROMISC_GRP); 2728 2729 if ((ifp->if_flags & IFF_PROMISC) != 0) { 2730 /* Turn on promiscuous mode */ 2731 v |= GEM_MAC_RX_PROMISCUOUS; 2732 ifp->if_flags |= IFF_ALLMULTI; 2733 goto chipit; 2734 } 2735 2736 /* 2737 * Set up multicast address filter by passing all multicast addresses 2738 * through a crc generator, and then using the high order 8 bits as an 2739 * index into the 256 bit logical address filter. The high order 4 2740 * bits selects the word, while the other 4 bits select the bit within 2741 * the word (where bit 0 is the MSB). 2742 */ 2743 2744 /* Clear hash table */ 2745 memset(hash, 0, sizeof(hash)); 2746 2747 ETHER_FIRST_MULTI(step, ec, enm); 2748 while (enm != NULL) { 2749 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2750 /* 2751 * We must listen to a range of multicast addresses. 2752 * For now, just accept all multicasts, rather than 2753 * trying to set only those filter bits needed to match 2754 * the range. (At this time, the only use of address 2755 * ranges is for IP multicast routing, for which the 2756 * range is big enough to require all bits set.) 2757 * XXX should use the address filters for this 2758 */ 2759 ifp->if_flags |= IFF_ALLMULTI; 2760 v |= GEM_MAC_RX_PROMISC_GRP; 2761 goto chipit; 2762 } 2763 2764 /* Get the LE CRC32 of the address */ 2765 crc = ether_crc32_le(enm->enm_addrlo, sizeof(enm->enm_addrlo)); 2766 2767 /* Just want the 8 most significant bits. */ 2768 crc >>= 24; 2769 2770 /* Set the corresponding bit in the filter. */ 2771 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 2772 2773 ETHER_NEXT_MULTI(step, enm); 2774 } 2775 2776 v |= GEM_MAC_RX_HASH_FILTER; 2777 ifp->if_flags &= ~IFF_ALLMULTI; 2778 2779 /* Now load the hash table into the chip (if we are using it) */ 2780 for (i = 0; i < 16; i++) { 2781 bus_space_write_4(t, h, 2782 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1-GEM_MAC_HASH0), 2783 hash[i]); 2784 } 2785 2786 chipit: 2787 sc->sc_if_flags = ifp->if_flags; 2788 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 2789 } 2790
Indexes created Mon Sep 22 10:09:38 GMT 2025