gem.c revision 1.15
1 /* $NetBSD: gem.c,v 1.15 2002/05/11 00:36:02 matt Exp $ */ 2 3 /* 4 * 5 * Copyright (C) 2001 Eduardo Horvath. 6 * All rights reserved. 7 * 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 */ 31 32 /* 33 * Driver for Sun GEM ethernet controllers. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: gem.c,v 1.15 2002/05/11 00:36:02 matt Exp $"); 38 39 #include "bpfilter.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/callout.h> 44 #include <sys/mbuf.h> 45 #include <sys/syslog.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #include <sys/socket.h> 49 #include <sys/ioctl.h> 50 #include <sys/errno.h> 51 #include <sys/device.h> 52 53 #include <machine/endian.h> 54 55 #include <uvm/uvm_extern.h> 56 57 #include <net/if.h> 58 #include <net/if_dl.h> 59 #include <net/if_media.h> 60 #include <net/if_ether.h> 61 62 #if NBPFILTER > 0 63 #include <net/bpf.h> 64 #endif 65 66 #include <machine/bus.h> 67 #include <machine/intr.h> 68 69 #include <dev/mii/mii.h> 70 #include <dev/mii/miivar.h> 71 #include <dev/mii/mii_bitbang.h> 72 73 #include <dev/ic/gemreg.h> 74 #include <dev/ic/gemvar.h> 75 76 #define TRIES 10000 77 78 void gem_start __P((struct ifnet *)); 79 void gem_stop __P((struct ifnet *, int)); 80 int gem_ioctl __P((struct ifnet *, u_long, caddr_t)); 81 void gem_tick __P((void *)); 82 void gem_watchdog __P((struct ifnet *)); 83 void gem_shutdown __P((void *)); 84 int gem_init __P((struct ifnet *)); 85 void gem_init_regs(struct gem_softc *sc); 86 static int gem_ringsize(int sz); 87 int gem_meminit __P((struct gem_softc *)); 88 void gem_mifinit __P((struct gem_softc *)); 89 void gem_reset __P((struct gem_softc *)); 90 int gem_reset_rx(struct gem_softc *sc); 91 int gem_reset_tx(struct gem_softc *sc); 92 int gem_disable_rx(struct gem_softc *sc); 93 int gem_disable_tx(struct gem_softc *sc); 94 void gem_rxdrain(struct gem_softc *sc); 95 int gem_add_rxbuf(struct gem_softc *sc, int idx); 96 void gem_setladrf __P((struct gem_softc *)); 97 98 /* MII methods & callbacks */ 99 static int gem_mii_readreg __P((struct device *, int, int)); 100 static void gem_mii_writereg __P((struct device *, int, int, int)); 101 static void gem_mii_statchg __P((struct device *)); 102 103 int gem_mediachange __P((struct ifnet *)); 104 void gem_mediastatus __P((struct ifnet *, struct ifmediareq *)); 105 106 struct mbuf *gem_get __P((struct gem_softc *, int, int)); 107 int gem_put __P((struct gem_softc *, int, struct mbuf *)); 108 void gem_read __P((struct gem_softc *, int, int)); 109 int gem_eint __P((struct gem_softc *, u_int)); 110 int gem_rint __P((struct gem_softc *)); 111 int gem_tint __P((struct gem_softc *)); 112 void gem_power __P((int, void *)); 113 114 #ifdef GEM_DEBUG 115 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 116 printf x 117 #else 118 #define DPRINTF(sc, x) /* nothing */ 119 #endif 120 121 122 /* 123 * gem_attach: 124 * 125 * Attach a Gem interface to the system. 126 */ 127 void 128 gem_attach(sc, enaddr) 129 struct gem_softc *sc; 130 const uint8_t *enaddr; 131 { 132 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 133 struct mii_data *mii = &sc->sc_mii; 134 struct mii_softc *child; 135 struct ifmedia_entry *ifm; 136 int i, error; 137 u_int32_t v; 138 139 /* Make sure the chip is stopped. */ 140 ifp->if_softc = sc; 141 gem_reset(sc); 142 143 /* 144 * Allocate the control data structures, and create and load the 145 * DMA map for it. 146 */ 147 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 148 sizeof(struct gem_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 149 1, &sc->sc_cdnseg, 0)) != 0) { 150 printf("%s: unable to allocate control data, error = %d\n", 151 sc->sc_dev.dv_xname, error); 152 goto fail_0; 153 } 154 155 /* XXX should map this in with correct endianness */ 156 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg, 157 sizeof(struct gem_control_data), (caddr_t *)&sc->sc_control_data, 158 BUS_DMA_COHERENT)) != 0) { 159 printf("%s: unable to map control data, error = %d\n", 160 sc->sc_dev.dv_xname, error); 161 goto fail_1; 162 } 163 164 if ((error = bus_dmamap_create(sc->sc_dmatag, 165 sizeof(struct gem_control_data), 1, 166 sizeof(struct gem_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 167 printf("%s: unable to create control data DMA map, " 168 "error = %d\n", sc->sc_dev.dv_xname, error); 169 goto fail_2; 170 } 171 172 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 173 sc->sc_control_data, sizeof(struct gem_control_data), NULL, 174 0)) != 0) { 175 printf("%s: unable to load control data DMA map, error = %d\n", 176 sc->sc_dev.dv_xname, error); 177 goto fail_3; 178 } 179 180 /* 181 * Initialize the transmit job descriptors. 182 */ 183 SIMPLEQ_INIT(&sc->sc_txfreeq); 184 SIMPLEQ_INIT(&sc->sc_txdirtyq); 185 186 /* 187 * Create the transmit buffer DMA maps. 188 */ 189 for (i = 0; i < GEM_TXQUEUELEN; i++) { 190 struct gem_txsoft *txs; 191 192 txs = &sc->sc_txsoft[i]; 193 txs->txs_mbuf = NULL; 194 if ((error = bus_dmamap_create(sc->sc_dmatag, 195 ETHER_MAX_LEN_JUMBO, GEM_NTXSEGS, 196 ETHER_MAX_LEN_JUMBO, 0, 0, 197 &txs->txs_dmamap)) != 0) { 198 printf("%s: unable to create tx DMA map %d, " 199 "error = %d\n", sc->sc_dev.dv_xname, i, error); 200 goto fail_4; 201 } 202 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 203 } 204 205 /* 206 * Create the receive buffer DMA maps. 207 */ 208 for (i = 0; i < GEM_NRXDESC; i++) { 209 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, 210 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 211 printf("%s: unable to create rx DMA map %d, " 212 "error = %d\n", sc->sc_dev.dv_xname, i, error); 213 goto fail_5; 214 } 215 sc->sc_rxsoft[i].rxs_mbuf = NULL; 216 } 217 218 /* 219 * From this point forward, the attachment cannot fail. A failure 220 * before this point releases all resources that may have been 221 * allocated. 222 */ 223 224 /* Announce ourselves. */ 225 printf("%s: Ethernet address %s", sc->sc_dev.dv_xname, 226 ether_sprintf(enaddr)); 227 228 /* Get RX FIFO size */ 229 sc->sc_rxfifosize = 64 * 230 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_FIFO_SIZE); 231 printf(", %uKB RX fifo", sc->sc_rxfifosize / 1024); 232 233 /* Get TX FIFO size */ 234 v = bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_FIFO_SIZE); 235 printf(", %uKB TX fifo\n", v / 16); 236 237 /* Initialize ifnet structure. */ 238 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 239 ifp->if_softc = sc; 240 ifp->if_flags = 241 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 242 ifp->if_start = gem_start; 243 ifp->if_ioctl = gem_ioctl; 244 ifp->if_watchdog = gem_watchdog; 245 ifp->if_stop = gem_stop; 246 ifp->if_init = gem_init; 247 IFQ_SET_READY(&ifp->if_snd); 248 249 /* Initialize ifmedia structures and MII info */ 250 mii->mii_ifp = ifp; 251 mii->mii_readreg = gem_mii_readreg; 252 mii->mii_writereg = gem_mii_writereg; 253 mii->mii_statchg = gem_mii_statchg; 254 255 ifmedia_init(&mii->mii_media, 0, gem_mediachange, gem_mediastatus); 256 257 gem_mifinit(sc); 258 259 mii_attach(&sc->sc_dev, mii, 0xffffffff, 260 MII_PHY_ANY, MII_OFFSET_ANY, 0); 261 262 child = LIST_FIRST(&mii->mii_phys); 263 if (child == NULL) { 264 /* No PHY attached */ 265 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 266 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 267 } else { 268 /* 269 * Walk along the list of attached MII devices and 270 * establish an `MII instance' to `phy number' 271 * mapping. We'll use this mapping in media change 272 * requests to determine which phy to use to program 273 * the MIF configuration register. 274 */ 275 for (; child != NULL; child = LIST_NEXT(child, mii_list)) { 276 /* 277 * Note: we support just two PHYs: the built-in 278 * internal device and an external on the MII 279 * connector. 280 */ 281 if (child->mii_phy > 1 || child->mii_inst > 1) { 282 printf("%s: cannot accomodate MII device %s" 283 " at phy %d, instance %d\n", 284 sc->sc_dev.dv_xname, 285 child->mii_dev.dv_xname, 286 child->mii_phy, child->mii_inst); 287 continue; 288 } 289 290 sc->sc_phys[child->mii_inst] = child->mii_phy; 291 292 } 293 294 /* 295 * Now select and activate the PHY we will use. 296 * 297 * The order of preference is External (MDI1), 298 * Internal (MDI0), Serial Link (no MII). 299 */ 300 if (sc->sc_phys[1]) { 301 #ifdef DEBUG 302 printf("using external phy\n"); 303 #endif 304 sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL; 305 } else { 306 #ifdef DEBUG 307 printf("using internal phy\n"); 308 #endif 309 sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL; 310 } 311 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_MIF_CONFIG, 312 sc->sc_mif_config); 313 314 /* 315 * XXX - we can really do the following ONLY if the 316 * phy indeed has the auto negotiation capability!! 317 */ 318 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO); 319 } 320 321 /* 322 * If we support GigE media, we support jumbo frames too. 323 * Unless we are Apple. 324 */ 325 TAILQ_FOREACH(ifm, &sc->sc_media.ifm_list, ifm_list) { 326 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_T || 327 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_SX || 328 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_LX || 329 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_CX) { 330 if (sc->sc_variant != GEM_APPLE_GMAC) 331 sc->sc_ethercom.ec_capabilities 332 |= ETHERCAP_JUMBO_MTU; 333 334 sc->sc_flags |= GEM_GIGABIT; 335 break; 336 } 337 } 338 339 /* claim 802.1q capability */ 340 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 341 342 /* Attach the interface. */ 343 if_attach(ifp); 344 ether_ifattach(ifp, enaddr); 345 346 sc->sc_sh = shutdownhook_establish(gem_shutdown, sc); 347 if (sc->sc_sh == NULL) 348 panic("gem_config: can't establish shutdownhook"); 349 350 #if NRND > 0 351 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 352 RND_TYPE_NET, 0); 353 #endif 354 355 356 #if notyet 357 /* 358 * Add a suspend hook to make sure we come back up after a 359 * resume. 360 */ 361 sc->sc_powerhook = powerhook_establish(gem_power, sc); 362 if (sc->sc_powerhook == NULL) 363 printf("%s: WARNING: unable to establish power hook\n", 364 sc->sc_dev.dv_xname); 365 #endif 366 367 callout_init(&sc->sc_tick_ch); 368 return; 369 370 /* 371 * Free any resources we've allocated during the failed attach 372 * attempt. Do this in reverse order and fall through. 373 */ 374 fail_5: 375 for (i = 0; i < GEM_NRXDESC; i++) { 376 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 377 bus_dmamap_destroy(sc->sc_dmatag, 378 sc->sc_rxsoft[i].rxs_dmamap); 379 } 380 fail_4: 381 for (i = 0; i < GEM_TXQUEUELEN; i++) { 382 if (sc->sc_txsoft[i].txs_dmamap != NULL) 383 bus_dmamap_destroy(sc->sc_dmatag, 384 sc->sc_txsoft[i].txs_dmamap); 385 } 386 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 387 fail_3: 388 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 389 fail_2: 390 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)sc->sc_control_data, 391 sizeof(struct gem_control_data)); 392 fail_1: 393 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 394 fail_0: 395 return; 396 } 397 398 399 void 400 gem_tick(arg) 401 void *arg; 402 { 403 struct gem_softc *sc = arg; 404 int s; 405 406 s = splnet(); 407 mii_tick(&sc->sc_mii); 408 splx(s); 409 410 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 411 412 } 413 414 void 415 gem_reset(sc) 416 struct gem_softc *sc; 417 { 418 bus_space_tag_t t = sc->sc_bustag; 419 bus_space_handle_t h = sc->sc_h; 420 int i; 421 int s; 422 423 s = splnet(); 424 DPRINTF(sc, ("%s: gem_reset\n", sc->sc_dev.dv_xname)); 425 gem_reset_rx(sc); 426 gem_reset_tx(sc); 427 428 /* Do a full reset */ 429 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX|GEM_RESET_TX); 430 for (i=TRIES; i--; delay(100)) 431 if ((bus_space_read_4(t, h, GEM_RESET) & 432 (GEM_RESET_RX|GEM_RESET_TX)) == 0) 433 break; 434 if ((bus_space_read_4(t, h, GEM_RESET) & 435 (GEM_RESET_RX|GEM_RESET_TX)) != 0) { 436 printf("%s: cannot reset device\n", 437 sc->sc_dev.dv_xname); 438 } 439 splx(s); 440 } 441 442 443 /* 444 * gem_rxdrain: 445 * 446 * Drain the receive queue. 447 */ 448 void 449 gem_rxdrain(struct gem_softc *sc) 450 { 451 struct gem_rxsoft *rxs; 452 int i; 453 454 for (i = 0; i < GEM_NRXDESC; i++) { 455 rxs = &sc->sc_rxsoft[i]; 456 if (rxs->rxs_mbuf != NULL) { 457 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 458 m_freem(rxs->rxs_mbuf); 459 rxs->rxs_mbuf = NULL; 460 } 461 } 462 } 463 464 /* 465 * Reset the whole thing. 466 */ 467 void 468 gem_stop(struct ifnet *ifp, int disable) 469 { 470 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 471 struct gem_txsoft *txs; 472 473 DPRINTF(sc, ("%s: gem_stop\n", sc->sc_dev.dv_xname)); 474 475 callout_stop(&sc->sc_tick_ch); 476 mii_down(&sc->sc_mii); 477 478 /* XXX - Should we reset these instead? */ 479 gem_disable_rx(sc); 480 gem_disable_rx(sc); 481 482 /* 483 * Release any queued transmit buffers. 484 */ 485 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 486 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs, txs_q); 487 if (txs->txs_mbuf != NULL) { 488 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 489 m_freem(txs->txs_mbuf); 490 txs->txs_mbuf = NULL; 491 } 492 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 493 } 494 495 if (disable) { 496 gem_rxdrain(sc); 497 } 498 499 /* 500 * Mark the interface down and cancel the watchdog timer. 501 */ 502 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 503 ifp->if_timer = 0; 504 } 505 506 507 /* 508 * Reset the receiver 509 */ 510 int 511 gem_reset_rx(struct gem_softc *sc) 512 { 513 bus_space_tag_t t = sc->sc_bustag; 514 bus_space_handle_t h = sc->sc_h; 515 int i; 516 517 518 /* 519 * Resetting while DMA is in progress can cause a bus hang, so we 520 * disable DMA first. 521 */ 522 gem_disable_rx(sc); 523 bus_space_write_4(t, h, GEM_RX_CONFIG, 0); 524 /* Wait till it finishes */ 525 for (i=TRIES; i--; delay(100)) 526 if ((bus_space_read_4(t, h, GEM_RX_CONFIG) & 1) == 0) 527 break; 528 if ((bus_space_read_4(t, h, GEM_RX_CONFIG) & 1) != 0) 529 printf("%s: cannot disable read dma\n", 530 sc->sc_dev.dv_xname); 531 532 /* Wait 5ms extra. */ 533 delay(5000); 534 535 /* Finally, reset the ERX */ 536 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX); 537 /* Wait till it finishes */ 538 for (i=TRIES; i--; delay(100)) 539 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_RX) == 0) 540 break; 541 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_RX) != 0) { 542 printf("%s: cannot reset receiver\n", 543 sc->sc_dev.dv_xname); 544 return (1); 545 } 546 return (0); 547 } 548 549 550 /* 551 * Reset the transmitter 552 */ 553 int 554 gem_reset_tx(struct gem_softc *sc) 555 { 556 bus_space_tag_t t = sc->sc_bustag; 557 bus_space_handle_t h = sc->sc_h; 558 int i; 559 560 /* 561 * Resetting while DMA is in progress can cause a bus hang, so we 562 * disable DMA first. 563 */ 564 gem_disable_tx(sc); 565 bus_space_write_4(t, h, GEM_TX_CONFIG, 0); 566 /* Wait till it finishes */ 567 for (i=TRIES; i--; delay(100)) 568 if ((bus_space_read_4(t, h, GEM_TX_CONFIG) & 1) == 0) 569 break; 570 if ((bus_space_read_4(t, h, GEM_TX_CONFIG) & 1) != 0) 571 printf("%s: cannot disable read dma\n", 572 sc->sc_dev.dv_xname); 573 574 /* Wait 5ms extra. */ 575 delay(5000); 576 577 /* Finally, reset the ETX */ 578 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_TX); 579 /* Wait till it finishes */ 580 for (i=TRIES; i--; delay(100)) 581 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_TX) == 0) 582 break; 583 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_TX) != 0) { 584 printf("%s: cannot reset receiver\n", 585 sc->sc_dev.dv_xname); 586 return (1); 587 } 588 return (0); 589 } 590 591 /* 592 * disable receiver. 593 */ 594 int 595 gem_disable_rx(struct gem_softc *sc) 596 { 597 bus_space_tag_t t = sc->sc_bustag; 598 bus_space_handle_t h = sc->sc_h; 599 int i; 600 u_int32_t cfg; 601 602 /* Flip the enable bit */ 603 cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 604 cfg &= ~GEM_MAC_RX_ENABLE; 605 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg); 606 607 /* Wait for it to finish */ 608 for (i=TRIES; i--; delay(100)) 609 if ((bus_space_read_4(t, h, GEM_MAC_RX_CONFIG) & 610 GEM_MAC_RX_ENABLE) == 0) 611 return (0); 612 return (1); 613 } 614 615 /* 616 * disable transmitter. 617 */ 618 int 619 gem_disable_tx(struct gem_softc *sc) 620 { 621 bus_space_tag_t t = sc->sc_bustag; 622 bus_space_handle_t h = sc->sc_h; 623 int i; 624 u_int32_t cfg; 625 626 /* Flip the enable bit */ 627 cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG); 628 cfg &= ~GEM_MAC_TX_ENABLE; 629 bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg); 630 631 /* Wait for it to finish */ 632 for (i=TRIES; i--; delay(100)) 633 if ((bus_space_read_4(t, h, GEM_MAC_TX_CONFIG) & 634 GEM_MAC_TX_ENABLE) == 0) 635 return (0); 636 return (1); 637 } 638 639 /* 640 * Initialize interface. 641 */ 642 int 643 gem_meminit(struct gem_softc *sc) 644 { 645 struct gem_rxsoft *rxs; 646 int i, error; 647 648 /* 649 * Initialize the transmit descriptor ring. 650 */ 651 memset((void *)sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 652 for (i = 0; i < GEM_NTXDESC; i++) { 653 sc->sc_txdescs[i].gd_flags = 0; 654 sc->sc_txdescs[i].gd_addr = 0; 655 } 656 GEM_CDTXSYNC(sc, 0, GEM_NTXDESC, 657 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 658 sc->sc_txfree = GEM_NTXDESC-1; 659 sc->sc_txnext = 0; 660 sc->sc_txwin = 0; 661 662 /* 663 * Initialize the receive descriptor and receive job 664 * descriptor rings. 665 */ 666 for (i = 0; i < GEM_NRXDESC; i++) { 667 rxs = &sc->sc_rxsoft[i]; 668 if (rxs->rxs_mbuf == NULL) { 669 if ((error = gem_add_rxbuf(sc, i)) != 0) { 670 printf("%s: unable to allocate or map rx " 671 "buffer %d, error = %d\n", 672 sc->sc_dev.dv_xname, i, error); 673 /* 674 * XXX Should attempt to run with fewer receive 675 * XXX buffers instead of just failing. 676 */ 677 gem_rxdrain(sc); 678 return (1); 679 } 680 } else 681 GEM_INIT_RXDESC(sc, i); 682 } 683 sc->sc_rxptr = 0; 684 685 return (0); 686 } 687 688 static int 689 gem_ringsize(int sz) 690 { 691 int v; 692 693 switch (sz) { 694 case 32: 695 v = GEM_RING_SZ_32; 696 break; 697 case 64: 698 v = GEM_RING_SZ_64; 699 break; 700 case 128: 701 v = GEM_RING_SZ_128; 702 break; 703 case 256: 704 v = GEM_RING_SZ_256; 705 break; 706 case 512: 707 v = GEM_RING_SZ_512; 708 break; 709 case 1024: 710 v = GEM_RING_SZ_1024; 711 break; 712 case 2048: 713 v = GEM_RING_SZ_2048; 714 break; 715 case 4096: 716 v = GEM_RING_SZ_4096; 717 break; 718 case 8192: 719 v = GEM_RING_SZ_8192; 720 break; 721 default: 722 printf("gem: invalid Receive Descriptor ring size\n"); 723 break; 724 } 725 return (v); 726 } 727 728 /* 729 * Initialization of interface; set up initialization block 730 * and transmit/receive descriptor rings. 731 */ 732 int 733 gem_init(struct ifnet *ifp) 734 { 735 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 736 bus_space_tag_t t = sc->sc_bustag; 737 bus_space_handle_t h = sc->sc_h; 738 int s; 739 u_int max_frame_size; 740 u_int32_t v; 741 742 s = splnet(); 743 744 DPRINTF(sc, ("%s: gem_init: calling stop\n", sc->sc_dev.dv_xname)); 745 /* 746 * Initialization sequence. The numbered steps below correspond 747 * to the sequence outlined in section 6.3.5.1 in the Ethernet 748 * Channel Engine manual (part of the PCIO manual). 749 * See also the STP2002-STQ document from Sun Microsystems. 750 */ 751 752 /* step 1 & 2. Reset the Ethernet Channel */ 753 gem_stop(ifp, 0); 754 gem_reset(sc); 755 DPRINTF(sc, ("%s: gem_init: restarting\n", sc->sc_dev.dv_xname)); 756 757 /* Re-initialize the MIF */ 758 gem_mifinit(sc); 759 760 /* Call MI reset function if any */ 761 if (sc->sc_hwreset) 762 (*sc->sc_hwreset)(sc); 763 764 /* step 3. Setup data structures in host memory */ 765 gem_meminit(sc); 766 767 /* step 4. TX MAC registers & counters */ 768 gem_init_regs(sc); 769 max_frame_size = max(sc->sc_ethercom.ec_if.if_mtu, ETHERMTU); 770 max_frame_size += ETHER_HDR_LEN + ETHER_CRC_LEN; 771 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 772 max_frame_size += ETHER_VLAN_ENCAP_LEN; 773 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 774 max_frame_size|/* burst size */(0x2000<<16)); 775 776 /* step 5. RX MAC registers & counters */ 777 gem_setladrf(sc); 778 779 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 780 /* NOTE: we use only 32-bit DMA addresses here. */ 781 bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 0); 782 bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 783 784 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0); 785 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 786 787 /* step 8. Global Configuration & Interrupt Mask */ 788 bus_space_write_4(t, h, GEM_INTMASK, 789 ~(GEM_INTR_TX_INTME| 790 GEM_INTR_TX_EMPTY| 791 GEM_INTR_RX_DONE|GEM_INTR_RX_NOBUF| 792 GEM_INTR_RX_TAG_ERR|GEM_INTR_PCS| 793 GEM_INTR_MAC_CONTROL|GEM_INTR_MIF| 794 GEM_INTR_BERR)); 795 bus_space_write_4(t, h, GEM_MAC_RX_MASK, 0); /* XXXX */ 796 bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXXX */ 797 bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 0); /* XXXX */ 798 799 /* step 9. ETX Configuration: use mostly default values */ 800 801 /* Enable DMA */ 802 v = gem_ringsize(GEM_NTXDESC /*XXX*/); 803 bus_space_write_4(t, h, GEM_TX_CONFIG, 804 v|GEM_TX_CONFIG_TXDMA_EN| 805 ((0x400<<10)&GEM_TX_CONFIG_TXFIFO_TH)); 806 bus_space_write_4(t, h, GEM_TX_KICK, sc->sc_txnext); 807 808 /* step 10. ERX Configuration */ 809 810 /* Encode Receive Descriptor ring size: four possible values */ 811 v = gem_ringsize(GEM_NRXDESC /*XXX*/); 812 813 /* Enable DMA */ 814 bus_space_write_4(t, h, GEM_RX_CONFIG, 815 v|(GEM_THRSH_1024<<GEM_RX_CONFIG_FIFO_THRS_SHIFT)| 816 (2<<GEM_RX_CONFIG_FBOFF_SHFT)|GEM_RX_CONFIG_RXDMA_EN| 817 (0<<GEM_RX_CONFIG_CXM_START_SHFT)); 818 /* 819 * The following value is for an OFF Threshold of about 3/4 full 820 * and an ON Threshold of 1/4 full. 821 */ 822 bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH, 823 (3 * sc->sc_rxfifosize / 256) | 824 ( (sc->sc_rxfifosize / 256) << 12)); 825 bus_space_write_4(t, h, GEM_RX_BLANKING, (6<<12)|6); 826 827 /* step 11. Configure Media */ 828 mii_mediachg(&sc->sc_mii); 829 830 /* XXXX Serial link needs a whole different setup. */ 831 832 833 /* step 12. RX_MAC Configuration Register */ 834 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 835 v |= GEM_MAC_RX_ENABLE; 836 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 837 838 /* step 14. Issue Transmit Pending command */ 839 840 /* Call MI initialization function if any */ 841 if (sc->sc_hwinit) 842 (*sc->sc_hwinit)(sc); 843 844 845 /* step 15. Give the reciever a swift kick */ 846 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4); 847 848 /* Start the one second timer. */ 849 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 850 851 ifp->if_flags |= IFF_RUNNING; 852 ifp->if_flags &= ~IFF_OACTIVE; 853 ifp->if_timer = 0; 854 splx(s); 855 856 return (0); 857 } 858 859 void 860 gem_init_regs(struct gem_softc *sc) 861 { 862 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 863 bus_space_tag_t t = sc->sc_bustag; 864 bus_space_handle_t h = sc->sc_h; 865 const u_char *laddr = LLADDR(ifp->if_sadl); 866 u_int32_t v; 867 868 /* These regs are not cleared on reset */ 869 if (!sc->sc_inited) { 870 871 /* Wooo. Magic values. */ 872 bus_space_write_4(t, h, GEM_MAC_IPG0, 0); 873 bus_space_write_4(t, h, GEM_MAC_IPG1, 8); 874 bus_space_write_4(t, h, GEM_MAC_IPG2, 4); 875 876 bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 877 /* Max frame and max burst size */ 878 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 879 ETHER_MAX_LEN | (0x2000<<16)); 880 881 bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x7); 882 bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x4); 883 bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10); 884 /* Dunno.... */ 885 bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088); 886 bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED, 887 ((laddr[5]<<8)|laddr[4])&0x3ff); 888 889 /* Secondary MAC addr set to 0:0:0:0:0:0 */ 890 bus_space_write_4(t, h, GEM_MAC_ADDR3, 0); 891 bus_space_write_4(t, h, GEM_MAC_ADDR4, 0); 892 bus_space_write_4(t, h, GEM_MAC_ADDR5, 0); 893 894 /* MAC control addr set to 01:80:c2:00:00:01 */ 895 bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001); 896 bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200); 897 bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180); 898 899 /* MAC filter addr set to 0:0:0:0:0:0 */ 900 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0); 901 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0); 902 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0); 903 904 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0); 905 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0); 906 907 sc->sc_inited = 1; 908 } 909 910 /* Counters need to be zeroed */ 911 bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0); 912 bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0); 913 bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0); 914 bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0); 915 bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0); 916 bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0); 917 bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0); 918 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 919 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 920 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 921 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 922 923 /* Un-pause stuff */ 924 #if 0 925 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); 926 #else 927 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0); 928 #endif 929 930 /* 931 * Set the station address. 932 */ 933 bus_space_write_4(t, h, GEM_MAC_ADDR0, (laddr[4]<<8)|laddr[5]); 934 bus_space_write_4(t, h, GEM_MAC_ADDR1, (laddr[2]<<8)|laddr[3]); 935 bus_space_write_4(t, h, GEM_MAC_ADDR2, (laddr[0]<<8)|laddr[1]); 936 937 #if 0 938 if (sc->sc_variant != APPLE_GMAC) 939 return; 940 #endif 941 942 /* 943 * Enable MII outputs. Enable GMII if there is a gigabit PHY. 944 */ 945 sc->sc_mif_config = bus_space_read_4(t, h, GEM_MIF_CONFIG); 946 v = GEM_MAC_XIF_TX_MII_ENA; 947 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) { 948 v |= GEM_MAC_XIF_FDPLX_LED; 949 if (sc->sc_flags & GEM_GIGABIT) 950 v |= GEM_MAC_XIF_GMII_MODE; 951 } 952 bus_space_write_4(t, h, GEM_MAC_XIF_CONFIG, v); 953 } 954 955 void 956 gem_start(ifp) 957 struct ifnet *ifp; 958 { 959 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 960 struct mbuf *m0, *m; 961 struct gem_txsoft *txs, *last_txs; 962 bus_dmamap_t dmamap; 963 int error, firsttx, nexttx, lasttx, ofree, seg; 964 965 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 966 return; 967 968 /* 969 * Remember the previous number of free descriptors and 970 * the first descriptor we'll use. 971 */ 972 ofree = sc->sc_txfree; 973 firsttx = sc->sc_txnext; 974 975 DPRINTF(sc, ("%s: gem_start: txfree %d, txnext %d\n", 976 sc->sc_dev.dv_xname, ofree, firsttx)); 977 978 /* 979 * Loop through the send queue, setting up transmit descriptors 980 * until we drain the queue, or use up all available transmit 981 * descriptors. 982 */ 983 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 984 sc->sc_txfree != 0) { 985 /* 986 * Grab a packet off the queue. 987 */ 988 IFQ_POLL(&ifp->if_snd, m0); 989 if (m0 == NULL) 990 break; 991 m = NULL; 992 993 dmamap = txs->txs_dmamap; 994 995 /* 996 * Load the DMA map. If this fails, the packet either 997 * didn't fit in the alloted number of segments, or we were 998 * short on resources. In this case, we'll copy and try 999 * again. 1000 */ 1001 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m0, 1002 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1003 if (m0->m_pkthdr.len > MCLBYTES) { 1004 printf("%s: unable to allocate jumbo Tx " 1005 "cluster\n", sc->sc_dev.dv_xname); 1006 IFQ_DEQUEUE(&ifp->if_snd, m0); 1007 m_freem(m0); 1008 continue; 1009 } 1010 MGETHDR(m, M_DONTWAIT, MT_DATA); 1011 if (m == NULL) { 1012 printf("%s: unable to allocate Tx mbuf\n", 1013 sc->sc_dev.dv_xname); 1014 break; 1015 } 1016 if (m0->m_pkthdr.len > MHLEN) { 1017 MCLGET(m, M_DONTWAIT); 1018 if ((m->m_flags & M_EXT) == 0) { 1019 printf("%s: unable to allocate Tx " 1020 "cluster\n", sc->sc_dev.dv_xname); 1021 m_freem(m); 1022 break; 1023 } 1024 } 1025 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 1026 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1027 error = bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, 1028 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1029 if (error) { 1030 printf("%s: unable to load Tx buffer, " 1031 "error = %d\n", sc->sc_dev.dv_xname, error); 1032 break; 1033 } 1034 } 1035 1036 /* 1037 * Ensure we have enough descriptors free to describe 1038 * the packet. 1039 */ 1040 if (dmamap->dm_nsegs > sc->sc_txfree) { 1041 /* 1042 * Not enough free descriptors to transmit this 1043 * packet. We haven't committed to anything yet, 1044 * so just unload the DMA map, put the packet 1045 * back on the queue, and punt. Notify the upper 1046 * layer that there are no more slots left. 1047 * 1048 * XXX We could allocate an mbuf and copy, but 1049 * XXX it is worth it? 1050 */ 1051 ifp->if_flags |= IFF_OACTIVE; 1052 bus_dmamap_unload(sc->sc_dmatag, dmamap); 1053 if (m != NULL) 1054 m_freem(m); 1055 break; 1056 } 1057 1058 IFQ_DEQUEUE(&ifp->if_snd, m0); 1059 if (m != NULL) { 1060 m_freem(m0); 1061 m0 = m; 1062 } 1063 1064 /* 1065 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1066 */ 1067 1068 /* Sync the DMA map. */ 1069 bus_dmamap_sync(sc->sc_dmatag, dmamap, 0, dmamap->dm_mapsize, 1070 BUS_DMASYNC_PREWRITE); 1071 1072 /* 1073 * Initialize the transmit descriptors. 1074 */ 1075 for (nexttx = sc->sc_txnext, seg = 0; 1076 seg < dmamap->dm_nsegs; 1077 seg++, nexttx = GEM_NEXTTX(nexttx)) { 1078 uint64_t flags; 1079 1080 /* 1081 * If this is the first descriptor we're 1082 * enqueueing, set the start of packet flag, 1083 * and the checksum stuff if we want the hardware 1084 * to do it. 1085 */ 1086 sc->sc_txdescs[nexttx].gd_addr = 1087 GEM_DMA_WRITE(sc, dmamap->dm_segs[seg].ds_addr); 1088 flags = dmamap->dm_segs[seg].ds_len & GEM_TD_BUFSIZE; 1089 if (nexttx == firsttx) { 1090 flags |= GEM_TD_START_OF_PACKET; 1091 if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) { 1092 sc->sc_txwin = 0; 1093 flags |= GEM_TD_INTERRUPT_ME; 1094 } 1095 } 1096 if (seg == dmamap->dm_nsegs - 1) { 1097 flags |= GEM_TD_END_OF_PACKET; 1098 } 1099 sc->sc_txdescs[nexttx].gd_flags = 1100 GEM_DMA_WRITE(sc, flags); 1101 lasttx = nexttx; 1102 } 1103 1104 #ifdef GEM_DEBUG 1105 if (ifp->if_flags & IFF_DEBUG) { 1106 printf(" gem_start %p transmit chain:\n", txs); 1107 for (seg = sc->sc_txnext;; seg = GEM_NEXTTX(seg)) { 1108 printf("descriptor %d:\t", seg); 1109 printf("gd_flags: 0x%016llx\t", (long long) 1110 GEM_DMA_READ(sc, sc->sc_txdescs[seg].gd_flags)); 1111 printf("gd_addr: 0x%016llx\n", (long long) 1112 GEM_DMA_READ(sc, sc->sc_txdescs[seg].gd_addr)); 1113 if (seg == lasttx) 1114 break; 1115 } 1116 } 1117 #endif 1118 1119 /* Sync the descriptors we're using. */ 1120 GEM_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1121 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1122 1123 /* 1124 * Store a pointer to the packet so we can free it later, 1125 * and remember what txdirty will be once the packet is 1126 * done. 1127 */ 1128 txs->txs_mbuf = m0; 1129 txs->txs_firstdesc = sc->sc_txnext; 1130 txs->txs_lastdesc = lasttx; 1131 txs->txs_ndescs = dmamap->dm_nsegs; 1132 1133 /* Advance the tx pointer. */ 1134 sc->sc_txfree -= dmamap->dm_nsegs; 1135 sc->sc_txnext = nexttx; 1136 1137 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs, txs_q); 1138 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1139 1140 last_txs = txs; 1141 1142 #if NBPFILTER > 0 1143 /* 1144 * Pass the packet to any BPF listeners. 1145 */ 1146 if (ifp->if_bpf) 1147 bpf_mtap(ifp->if_bpf, m0); 1148 #endif /* NBPFILTER > 0 */ 1149 } 1150 1151 if (txs == NULL || sc->sc_txfree == 0) { 1152 /* No more slots left; notify upper layer. */ 1153 ifp->if_flags |= IFF_OACTIVE; 1154 } 1155 1156 if (sc->sc_txfree != ofree) { 1157 DPRINTF(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 1158 sc->sc_dev.dv_xname, lasttx, firsttx)); 1159 /* 1160 * The entire packet chain is set up. 1161 * Kick the transmitter. 1162 */ 1163 DPRINTF(sc, ("%s: gem_start: kicking tx %d\n", 1164 sc->sc_dev.dv_xname, nexttx)); 1165 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_TX_KICK, 1166 sc->sc_txnext); 1167 1168 /* Set a watchdog timer in case the chip flakes out. */ 1169 ifp->if_timer = 5; 1170 DPRINTF(sc, ("%s: gem_start: watchdog %d\n", 1171 sc->sc_dev.dv_xname, ifp->if_timer)); 1172 } 1173 } 1174 1175 /* 1176 * Transmit interrupt. 1177 */ 1178 int 1179 gem_tint(sc) 1180 struct gem_softc *sc; 1181 { 1182 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1183 bus_space_tag_t t = sc->sc_bustag; 1184 bus_space_handle_t mac = sc->sc_h; 1185 struct gem_txsoft *txs; 1186 int txlast; 1187 int progress = 0; 1188 1189 1190 DPRINTF(sc, ("%s: gem_tint\n", sc->sc_dev.dv_xname)); 1191 1192 /* 1193 * Unload collision counters 1194 */ 1195 ifp->if_collisions += 1196 bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) + 1197 bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT) + 1198 bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) + 1199 bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT); 1200 1201 /* 1202 * then clear the hardware counters. 1203 */ 1204 bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0); 1205 bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0); 1206 bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0); 1207 bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0); 1208 1209 /* 1210 * Go through our Tx list and free mbufs for those 1211 * frames that have been transmitted. 1212 */ 1213 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1214 GEM_CDTXSYNC(sc, txs->txs_lastdesc, 1215 txs->txs_ndescs, 1216 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1217 1218 #ifdef GEM_DEBUG 1219 if (ifp->if_flags & IFF_DEBUG) { 1220 int i; 1221 printf(" txsoft %p transmit chain:\n", txs); 1222 for (i = txs->txs_firstdesc;; i = GEM_NEXTTX(i)) { 1223 printf("descriptor %d: ", i); 1224 printf("gd_flags: 0x%016llx\t", (long long) 1225 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags)); 1226 printf("gd_addr: 0x%016llx\n", (long long) 1227 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr)); 1228 if (i == txs->txs_lastdesc) 1229 break; 1230 } 1231 } 1232 #endif 1233 1234 /* 1235 * In theory, we could harveast some descriptors before 1236 * the ring is empty, but that's a bit complicated. 1237 * 1238 * GEM_TX_COMPLETION points to the last descriptor 1239 * processed +1. 1240 */ 1241 txlast = bus_space_read_4(t, mac, GEM_TX_COMPLETION); 1242 DPRINTF(sc, 1243 ("gem_tint: txs->txs_lastdesc = %d, txlast = %d\n", 1244 txs->txs_lastdesc, txlast)); 1245 if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1246 if ((txlast >= txs->txs_firstdesc) && 1247 (txlast <= txs->txs_lastdesc)) 1248 break; 1249 } else { 1250 /* Ick -- this command wraps */ 1251 if ((txlast >= txs->txs_firstdesc) || 1252 (txlast <= txs->txs_lastdesc)) 1253 break; 1254 } 1255 1256 DPRINTF(sc, ("gem_tint: releasing a desc\n")); 1257 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs, txs_q); 1258 1259 sc->sc_txfree += txs->txs_ndescs; 1260 1261 if (txs->txs_mbuf == NULL) { 1262 #ifdef DIAGNOSTIC 1263 panic("gem_txintr: null mbuf"); 1264 #endif 1265 } 1266 1267 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 1268 0, txs->txs_dmamap->dm_mapsize, 1269 BUS_DMASYNC_POSTWRITE); 1270 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 1271 m_freem(txs->txs_mbuf); 1272 txs->txs_mbuf = NULL; 1273 1274 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1275 1276 ifp->if_opackets++; 1277 progress = 1; 1278 } 1279 1280 DPRINTF(sc, ("gem_tint: GEM_TX_STATE_MACHINE %x " 1281 "GEM_TX_DATA_PTR %llx " 1282 "GEM_TX_COMPLETION %x\n", 1283 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_STATE_MACHINE), 1284 ((long long) bus_space_read_4(sc->sc_bustag, sc->sc_h, 1285 GEM_TX_DATA_PTR_HI) << 32) | 1286 bus_space_read_4(sc->sc_bustag, sc->sc_h, 1287 GEM_TX_DATA_PTR_LO), 1288 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_COMPLETION))); 1289 1290 if (progress) { 1291 if (sc->sc_txfree == GEM_NTXDESC - 1) 1292 sc->sc_txwin = 0; 1293 1294 ifp->if_flags &= ~IFF_OACTIVE; 1295 gem_start(ifp); 1296 1297 if (SIMPLEQ_FIRST(&sc->sc_txdirtyq) == NULL) 1298 ifp->if_timer = 0; 1299 } 1300 DPRINTF(sc, ("%s: gem_tint: watchdog %d\n", 1301 sc->sc_dev.dv_xname, ifp->if_timer)); 1302 1303 return (1); 1304 } 1305 1306 /* 1307 * Receive interrupt. 1308 */ 1309 int 1310 gem_rint(sc) 1311 struct gem_softc *sc; 1312 { 1313 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1314 bus_space_tag_t t = sc->sc_bustag; 1315 bus_space_handle_t h = sc->sc_h; 1316 struct ether_header *eh; 1317 struct gem_rxsoft *rxs; 1318 struct mbuf *m; 1319 u_int64_t rxstat; 1320 int i, len; 1321 1322 DPRINTF(sc, ("%s: gem_rint\n", sc->sc_dev.dv_xname)); 1323 /* 1324 * XXXX Read the lastrx only once at the top for speed. 1325 */ 1326 DPRINTF(sc, ("gem_rint: sc->rxptr %d, complete %d\n", 1327 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION))); 1328 for (i = sc->sc_rxptr; i != bus_space_read_4(t, h, GEM_RX_COMPLETION); 1329 i = GEM_NEXTRX(i)) { 1330 rxs = &sc->sc_rxsoft[i]; 1331 1332 GEM_CDRXSYNC(sc, i, 1333 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1334 1335 rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags); 1336 1337 if (rxstat & GEM_RD_OWN) { 1338 printf("gem_rint: completed descriptor " 1339 "still owned %d\n", i); 1340 /* 1341 * We have processed all of the receive buffers. 1342 */ 1343 break; 1344 } 1345 1346 if (rxstat & GEM_RD_BAD_CRC) { 1347 printf("%s: receive error: CRC error\n", 1348 sc->sc_dev.dv_xname); 1349 GEM_INIT_RXDESC(sc, i); 1350 continue; 1351 } 1352 1353 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1354 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1355 #ifdef GEM_DEBUG 1356 if (ifp->if_flags & IFF_DEBUG) { 1357 printf(" rxsoft %p descriptor %d: ", rxs, i); 1358 printf("gd_flags: 0x%016llx\t", (long long) 1359 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags)); 1360 printf("gd_addr: 0x%016llx\n", (long long) 1361 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr)); 1362 } 1363 #endif 1364 1365 /* 1366 * No errors; receive the packet. Note the Gem 1367 * includes the CRC with every packet. 1368 */ 1369 len = GEM_RD_BUFLEN(rxstat); 1370 1371 /* 1372 * Allocate a new mbuf cluster. If that fails, we are 1373 * out of memory, and must drop the packet and recycle 1374 * the buffer that's already attached to this descriptor. 1375 */ 1376 m = rxs->rxs_mbuf; 1377 if (gem_add_rxbuf(sc, i) != 0) { 1378 ifp->if_ierrors++; 1379 GEM_INIT_RXDESC(sc, i); 1380 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1381 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1382 continue; 1383 } 1384 m->m_data += 2; /* We're already off by two */ 1385 1386 ifp->if_ipackets++; 1387 eh = mtod(m, struct ether_header *); 1388 m->m_flags |= M_HASFCS; 1389 m->m_pkthdr.rcvif = ifp; 1390 m->m_pkthdr.len = m->m_len = len; 1391 1392 #if NBPFILTER > 0 1393 /* 1394 * Pass this up to any BPF listeners, but only 1395 * pass it up the stack if its for us. 1396 */ 1397 if (ifp->if_bpf) 1398 bpf_mtap(ifp->if_bpf, m); 1399 #endif /* NPBFILTER > 0 */ 1400 1401 /* Pass it on. */ 1402 (*ifp->if_input)(ifp, m); 1403 } 1404 1405 /* Update the receive pointer. */ 1406 sc->sc_rxptr = i; 1407 bus_space_write_4(t, h, GEM_RX_KICK, i); 1408 1409 DPRINTF(sc, ("gem_rint: done sc->rxptr %d, complete %d\n", 1410 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION))); 1411 1412 return (1); 1413 } 1414 1415 1416 /* 1417 * gem_add_rxbuf: 1418 * 1419 * Add a receive buffer to the indicated descriptor. 1420 */ 1421 int 1422 gem_add_rxbuf(struct gem_softc *sc, int idx) 1423 { 1424 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1425 struct mbuf *m; 1426 int error; 1427 1428 MGETHDR(m, M_DONTWAIT, MT_DATA); 1429 if (m == NULL) 1430 return (ENOBUFS); 1431 1432 MCLGET(m, M_DONTWAIT); 1433 if ((m->m_flags & M_EXT) == 0) { 1434 m_freem(m); 1435 return (ENOBUFS); 1436 } 1437 1438 #ifdef GEM_DEBUG 1439 /* bzero the packet to check dma */ 1440 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 1441 #endif 1442 1443 if (rxs->rxs_mbuf != NULL) 1444 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 1445 1446 rxs->rxs_mbuf = m; 1447 1448 error = bus_dmamap_load(sc->sc_dmatag, rxs->rxs_dmamap, 1449 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1450 BUS_DMA_READ|BUS_DMA_NOWAIT); 1451 if (error) { 1452 printf("%s: can't load rx DMA map %d, error = %d\n", 1453 sc->sc_dev.dv_xname, idx, error); 1454 panic("gem_add_rxbuf"); /* XXX */ 1455 } 1456 1457 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1458 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1459 1460 GEM_INIT_RXDESC(sc, idx); 1461 1462 return (0); 1463 } 1464 1465 1466 int 1467 gem_eint(sc, status) 1468 struct gem_softc *sc; 1469 u_int status; 1470 { 1471 char bits[128]; 1472 1473 if ((status & GEM_INTR_MIF) != 0) { 1474 printf("%s: XXXlink status changed\n", sc->sc_dev.dv_xname); 1475 return (1); 1476 } 1477 1478 printf("%s: status=%s\n", sc->sc_dev.dv_xname, 1479 bitmask_snprintf(status, GEM_INTR_BITS, bits, sizeof(bits))); 1480 return (1); 1481 } 1482 1483 1484 int 1485 gem_intr(v) 1486 void *v; 1487 { 1488 struct gem_softc *sc = (struct gem_softc *)v; 1489 bus_space_tag_t t = sc->sc_bustag; 1490 bus_space_handle_t seb = sc->sc_h; 1491 u_int32_t status; 1492 int r = 0; 1493 #ifdef GEM_DEBUG 1494 char bits[128]; 1495 #endif 1496 1497 status = bus_space_read_4(t, seb, GEM_STATUS); 1498 DPRINTF(sc, ("%s: gem_intr: cplt %xstatus %s\n", 1499 sc->sc_dev.dv_xname, (status>>19), 1500 bitmask_snprintf(status, GEM_INTR_BITS, bits, sizeof(bits)))); 1501 1502 if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0) 1503 r |= gem_eint(sc, status); 1504 1505 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) 1506 r |= gem_tint(sc); 1507 1508 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) 1509 r |= gem_rint(sc); 1510 1511 /* We should eventually do more than just print out error stats. */ 1512 if (status & GEM_INTR_TX_MAC) { 1513 int txstat = bus_space_read_4(t, seb, GEM_MAC_TX_STATUS); 1514 if (txstat & ~GEM_MAC_TX_XMIT_DONE) 1515 printf("%s: MAC tx fault, status %x\n", 1516 sc->sc_dev.dv_xname, txstat); 1517 } 1518 if (status & GEM_INTR_RX_MAC) { 1519 int rxstat = bus_space_read_4(t, seb, GEM_MAC_RX_STATUS); 1520 if (rxstat & ~GEM_MAC_RX_DONE) 1521 printf("%s: MAC rx fault, status %x\n", 1522 sc->sc_dev.dv_xname, rxstat); 1523 } 1524 return (r); 1525 } 1526 1527 1528 void 1529 gem_watchdog(ifp) 1530 struct ifnet *ifp; 1531 { 1532 struct gem_softc *sc = ifp->if_softc; 1533 1534 DPRINTF(sc, ("gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x " 1535 "GEM_MAC_RX_CONFIG %x\n", 1536 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_CONFIG), 1537 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_STATUS), 1538 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_CONFIG))); 1539 1540 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1541 ++ifp->if_oerrors; 1542 1543 /* Try to get more packets going. */ 1544 gem_start(ifp); 1545 } 1546 1547 /* 1548 * Initialize the MII Management Interface 1549 */ 1550 void 1551 gem_mifinit(sc) 1552 struct gem_softc *sc; 1553 { 1554 bus_space_tag_t t = sc->sc_bustag; 1555 bus_space_handle_t mif = sc->sc_h; 1556 1557 /* Configure the MIF in frame mode */ 1558 sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1559 sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA; 1560 bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config); 1561 } 1562 1563 /* 1564 * MII interface 1565 * 1566 * The GEM MII interface supports at least three different operating modes: 1567 * 1568 * Bitbang mode is implemented using data, clock and output enable registers. 1569 * 1570 * Frame mode is implemented by loading a complete frame into the frame 1571 * register and polling the valid bit for completion. 1572 * 1573 * Polling mode uses the frame register but completion is indicated by 1574 * an interrupt. 1575 * 1576 */ 1577 static int 1578 gem_mii_readreg(self, phy, reg) 1579 struct device *self; 1580 int phy, reg; 1581 { 1582 struct gem_softc *sc = (void *)self; 1583 bus_space_tag_t t = sc->sc_bustag; 1584 bus_space_handle_t mif = sc->sc_h; 1585 int n; 1586 u_int32_t v; 1587 1588 #ifdef GEM_DEBUG1 1589 if (sc->sc_debug) 1590 printf("gem_mii_readreg: phy %d reg %d\n", phy, reg); 1591 #endif 1592 1593 #if 0 1594 /* Select the desired PHY in the MIF configuration register */ 1595 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1596 /* Clear PHY select bit */ 1597 v &= ~GEM_MIF_CONFIG_PHY_SEL; 1598 if (phy == GEM_PHYAD_EXTERNAL) 1599 /* Set PHY select bit to get at external device */ 1600 v |= GEM_MIF_CONFIG_PHY_SEL; 1601 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 1602 #endif 1603 1604 /* Construct the frame command */ 1605 v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) | 1606 GEM_MIF_FRAME_READ; 1607 1608 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1609 for (n = 0; n < 100; n++) { 1610 DELAY(1); 1611 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1612 if (v & GEM_MIF_FRAME_TA0) 1613 return (v & GEM_MIF_FRAME_DATA); 1614 } 1615 1616 printf("%s: mii_read timeout\n", sc->sc_dev.dv_xname); 1617 return (0); 1618 } 1619 1620 static void 1621 gem_mii_writereg(self, phy, reg, val) 1622 struct device *self; 1623 int phy, reg, val; 1624 { 1625 struct gem_softc *sc = (void *)self; 1626 bus_space_tag_t t = sc->sc_bustag; 1627 bus_space_handle_t mif = sc->sc_h; 1628 int n; 1629 u_int32_t v; 1630 1631 #ifdef GEM_DEBUG1 1632 if (sc->sc_debug) 1633 printf("gem_mii_writereg: phy %d reg %d val %x\n", 1634 phy, reg, val); 1635 #endif 1636 1637 #if 0 1638 /* Select the desired PHY in the MIF configuration register */ 1639 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1640 /* Clear PHY select bit */ 1641 v &= ~GEM_MIF_CONFIG_PHY_SEL; 1642 if (phy == GEM_PHYAD_EXTERNAL) 1643 /* Set PHY select bit to get at external device */ 1644 v |= GEM_MIF_CONFIG_PHY_SEL; 1645 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 1646 #endif 1647 /* Construct the frame command */ 1648 v = GEM_MIF_FRAME_WRITE | 1649 (phy << GEM_MIF_PHY_SHIFT) | 1650 (reg << GEM_MIF_REG_SHIFT) | 1651 (val & GEM_MIF_FRAME_DATA); 1652 1653 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1654 for (n = 0; n < 100; n++) { 1655 DELAY(1); 1656 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1657 if (v & GEM_MIF_FRAME_TA0) 1658 return; 1659 } 1660 1661 printf("%s: mii_write timeout\n", sc->sc_dev.dv_xname); 1662 } 1663 1664 static void 1665 gem_mii_statchg(dev) 1666 struct device *dev; 1667 { 1668 struct gem_softc *sc = (void *)dev; 1669 #ifdef GEM_DEBUG 1670 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1671 #endif 1672 bus_space_tag_t t = sc->sc_bustag; 1673 bus_space_handle_t mac = sc->sc_h; 1674 u_int32_t v; 1675 1676 #ifdef GEM_DEBUG 1677 if (sc->sc_debug) 1678 printf("gem_mii_statchg: status change: phy = %d\n", 1679 sc->sc_phys[instance];); 1680 #endif 1681 1682 1683 /* Set tx full duplex options */ 1684 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0); 1685 delay(10000); /* reg must be cleared and delay before changing. */ 1686 v = GEM_MAC_TX_ENA_IPG0|GEM_MAC_TX_NGU|GEM_MAC_TX_NGU_LIMIT| 1687 GEM_MAC_TX_ENABLE; 1688 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) { 1689 v |= GEM_MAC_TX_IGN_CARRIER|GEM_MAC_TX_IGN_COLLIS; 1690 } 1691 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, v); 1692 1693 /* XIF Configuration */ 1694 /* We should really calculate all this rather than rely on defaults */ 1695 v = bus_space_read_4(t, mac, GEM_MAC_XIF_CONFIG); 1696 v = GEM_MAC_XIF_LINK_LED; 1697 v |= GEM_MAC_XIF_TX_MII_ENA; 1698 1699 /* If an external transceiver is connected, enable its MII drivers */ 1700 sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG); 1701 if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) { 1702 /* External MII needs echo disable if half duplex. */ 1703 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1704 /* turn on full duplex LED */ 1705 v |= GEM_MAC_XIF_FDPLX_LED; 1706 else 1707 /* half duplex -- disable echo */ 1708 v |= GEM_MAC_XIF_ECHO_DISABL; 1709 1710 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 1711 v |= GEM_MAC_XIF_GMII_MODE; 1712 else 1713 v &= ~GEM_MAC_XIF_GMII_MODE; 1714 } else 1715 /* Internal MII needs buf enable */ 1716 v |= GEM_MAC_XIF_MII_BUF_ENA; 1717 bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v); 1718 } 1719 1720 int 1721 gem_mediachange(ifp) 1722 struct ifnet *ifp; 1723 { 1724 struct gem_softc *sc = ifp->if_softc; 1725 1726 if (IFM_TYPE(sc->sc_media.ifm_media) != IFM_ETHER) 1727 return (EINVAL); 1728 1729 return (mii_mediachg(&sc->sc_mii)); 1730 } 1731 1732 void 1733 gem_mediastatus(ifp, ifmr) 1734 struct ifnet *ifp; 1735 struct ifmediareq *ifmr; 1736 { 1737 struct gem_softc *sc = ifp->if_softc; 1738 1739 if ((ifp->if_flags & IFF_UP) == 0) 1740 return; 1741 1742 mii_pollstat(&sc->sc_mii); 1743 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1744 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1745 } 1746 1747 int gem_ioctldebug = 0; 1748 /* 1749 * Process an ioctl request. 1750 */ 1751 int 1752 gem_ioctl(ifp, cmd, data) 1753 struct ifnet *ifp; 1754 u_long cmd; 1755 caddr_t data; 1756 { 1757 struct gem_softc *sc = ifp->if_softc; 1758 struct ifreq *ifr = (struct ifreq *)data; 1759 int s, error = 0; 1760 1761 1762 switch (cmd) { 1763 case SIOCGIFMEDIA: 1764 case SIOCSIFMEDIA: 1765 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1766 break; 1767 1768 default: 1769 error = ether_ioctl(ifp, cmd, data); 1770 if (error == ENETRESET) { 1771 /* 1772 * Multicast list has changed; set the hardware filter 1773 * accordingly. 1774 */ 1775 if (gem_ioctldebug) printf("reset1\n"); 1776 gem_init(ifp); 1777 delay(50000); 1778 error = 0; 1779 } 1780 break; 1781 } 1782 1783 /* Try to get things going again */ 1784 if (ifp->if_flags & IFF_UP) { 1785 if (gem_ioctldebug) printf("start\n"); 1786 gem_start(ifp); 1787 } 1788 splx(s); 1789 return (error); 1790 } 1791 1792 1793 void 1794 gem_shutdown(arg) 1795 void *arg; 1796 { 1797 struct gem_softc *sc = (struct gem_softc *)arg; 1798 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1799 1800 gem_stop(ifp, 1); 1801 } 1802 1803 /* 1804 * Set up the logical address filter. 1805 */ 1806 void 1807 gem_setladrf(sc) 1808 struct gem_softc *sc; 1809 { 1810 struct ethercom *ec = &sc->sc_ethercom; 1811 struct ifnet *ifp = &ec->ec_if; 1812 struct ether_multi *enm; 1813 struct ether_multistep step; 1814 bus_space_tag_t t = sc->sc_bustag; 1815 bus_space_handle_t h = sc->sc_h; 1816 u_int32_t crc; 1817 u_int32_t hash[16]; 1818 u_int32_t v; 1819 int i; 1820 1821 /* Get current RX configuration */ 1822 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 1823 1824 /* 1825 * Turn off promiscuous mode, promiscuous group mode (all multicast), 1826 * and hash filter. Depending on the case, the right bit will be 1827 * enabled. 1828 */ 1829 v &= ~(GEM_MAC_RX_PROMISCUOUS|GEM_MAC_RX_HASH_FILTER| 1830 GEM_MAC_RX_PROMISC_GRP); 1831 1832 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1833 /* Turn on promiscuous mode */ 1834 v |= GEM_MAC_RX_PROMISCUOUS; 1835 ifp->if_flags |= IFF_ALLMULTI; 1836 goto chipit; 1837 } 1838 1839 /* 1840 * Set up multicast address filter by passing all multicast addresses 1841 * through a crc generator, and then using the high order 8 bits as an 1842 * index into the 256 bit logical address filter. The high order 4 1843 * bits select the word, while the other 4 bits select the bit within 1844 * the word (where bit 0 is the MSB). 1845 */ 1846 1847 /* Clear hash table */ 1848 memset(hash, 0, sizeof(hash)); 1849 1850 ETHER_FIRST_MULTI(step, ec, enm); 1851 while (enm != NULL) { 1852 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1853 /* 1854 * We must listen to a range of multicast addresses. 1855 * For now, just accept all multicasts, rather than 1856 * trying to set only those filter bits needed to match 1857 * the range. (At this time, the only use of address 1858 * ranges is for IP multicast routing, for which the 1859 * range is big enough to require all bits set.) 1860 * XXX use the addr filter for this 1861 */ 1862 ifp->if_flags |= IFF_ALLMULTI; 1863 v |= GEM_MAC_RX_PROMISC_GRP; 1864 goto chipit; 1865 } 1866 1867 /* Get the LE CRC32 of the address */ 1868 crc = ether_crc32_le(enm->enm_addrlo, sizeof(enm->enm_addrlo)); 1869 1870 /* Just want the 8 most significant bits. */ 1871 crc >>= 24; 1872 1873 /* Set the corresponding bit in the filter. */ 1874 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 1875 1876 ETHER_NEXT_MULTI(step, enm); 1877 } 1878 1879 v |= GEM_MAC_RX_HASH_FILTER; 1880 ifp->if_flags &= ~IFF_ALLMULTI; 1881 1882 /* Now load the hash table into the chip (if we are using it) */ 1883 for (i = 0; i < 16; i++) { 1884 bus_space_write_4(t, h, 1885 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1-GEM_MAC_HASH0), 1886 hash[i]); 1887 } 1888 1889 chipit: 1890 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 1891 } 1892 1893 #if notyet 1894 1895 /* 1896 * gem_power: 1897 * 1898 * Power management (suspend/resume) hook. 1899 */ 1900 void 1901 gem_power(why, arg) 1902 int why; 1903 void *arg; 1904 { 1905 struct gem_softc *sc = arg; 1906 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1907 int s; 1908 1909 s = splnet(); 1910 switch (why) { 1911 case PWR_SUSPEND: 1912 case PWR_STANDBY: 1913 gem_stop(ifp, 1); 1914 if (sc->sc_power != NULL) 1915 (*sc->sc_power)(sc, why); 1916 break; 1917 case PWR_RESUME: 1918 if (ifp->if_flags & IFF_UP) { 1919 if (sc->sc_power != NULL) 1920 (*sc->sc_power)(sc, why); 1921 gem_init(ifp); 1922 } 1923 break; 1924 case PWR_SOFTSUSPEND: 1925 case PWR_SOFTSTANDBY: 1926 case PWR_SOFTRESUME: 1927 break; 1928 } 1929 splx(s); 1930 } 1931 #endif 1932
Indexes created Tue Sep 23 07:09:52 GMT 2025