gem.c revision 1.16
1 /* $NetBSD: gem.c,v 1.16 2002/05/11 20:53:52 matt Exp $ */ 2 3 /* 4 * 5 * Copyright (C) 2001 Eduardo Horvath. 6 * All rights reserved. 7 * 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 */ 31 32 /* 33 * Driver for Sun GEM ethernet controllers. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: gem.c,v 1.16 2002/05/11 20:53:52 matt Exp $"); 38 39 #include "bpfilter.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/callout.h> 44 #include <sys/mbuf.h> 45 #include <sys/syslog.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #include <sys/socket.h> 49 #include <sys/ioctl.h> 50 #include <sys/errno.h> 51 #include <sys/device.h> 52 53 #include <machine/endian.h> 54 55 #include <uvm/uvm_extern.h> 56 57 #include <net/if.h> 58 #include <net/if_dl.h> 59 #include <net/if_media.h> 60 #include <net/if_ether.h> 61 62 #if NBPFILTER > 0 63 #include <net/bpf.h> 64 #endif 65 66 #include <machine/bus.h> 67 #include <machine/intr.h> 68 69 #include <dev/mii/mii.h> 70 #include <dev/mii/miivar.h> 71 #include <dev/mii/mii_bitbang.h> 72 73 #include <dev/ic/gemreg.h> 74 #include <dev/ic/gemvar.h> 75 76 #define TRIES 10000 77 78 void gem_start __P((struct ifnet *)); 79 void gem_stop __P((struct ifnet *, int)); 80 int gem_ioctl __P((struct ifnet *, u_long, caddr_t)); 81 void gem_tick __P((void *)); 82 void gem_watchdog __P((struct ifnet *)); 83 void gem_shutdown __P((void *)); 84 int gem_init __P((struct ifnet *)); 85 void gem_init_regs(struct gem_softc *sc); 86 static int gem_ringsize(int sz); 87 int gem_meminit __P((struct gem_softc *)); 88 void gem_mifinit __P((struct gem_softc *)); 89 void gem_reset __P((struct gem_softc *)); 90 int gem_reset_rx(struct gem_softc *sc); 91 int gem_reset_tx(struct gem_softc *sc); 92 int gem_disable_rx(struct gem_softc *sc); 93 int gem_disable_tx(struct gem_softc *sc); 94 void gem_rxdrain(struct gem_softc *sc); 95 int gem_add_rxbuf(struct gem_softc *sc, int idx); 96 void gem_setladrf __P((struct gem_softc *)); 97 98 /* MII methods & callbacks */ 99 static int gem_mii_readreg __P((struct device *, int, int)); 100 static void gem_mii_writereg __P((struct device *, int, int, int)); 101 static void gem_mii_statchg __P((struct device *)); 102 103 int gem_mediachange __P((struct ifnet *)); 104 void gem_mediastatus __P((struct ifnet *, struct ifmediareq *)); 105 106 struct mbuf *gem_get __P((struct gem_softc *, int, int)); 107 int gem_put __P((struct gem_softc *, int, struct mbuf *)); 108 void gem_read __P((struct gem_softc *, int, int)); 109 int gem_eint __P((struct gem_softc *, u_int)); 110 int gem_rint __P((struct gem_softc *)); 111 int gem_tint __P((struct gem_softc *)); 112 void gem_power __P((int, void *)); 113 114 #ifdef GEM_DEBUG 115 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 116 printf x 117 #else 118 #define DPRINTF(sc, x) /* nothing */ 119 #endif 120 121 122 /* 123 * gem_attach: 124 * 125 * Attach a Gem interface to the system. 126 */ 127 void 128 gem_attach(sc, enaddr) 129 struct gem_softc *sc; 130 const uint8_t *enaddr; 131 { 132 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 133 struct mii_data *mii = &sc->sc_mii; 134 struct mii_softc *child; 135 struct ifmedia_entry *ifm; 136 int i, error; 137 u_int32_t v; 138 139 /* Make sure the chip is stopped. */ 140 ifp->if_softc = sc; 141 gem_reset(sc); 142 143 /* 144 * Allocate the control data structures, and create and load the 145 * DMA map for it. 146 */ 147 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 148 sizeof(struct gem_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 149 1, &sc->sc_cdnseg, 0)) != 0) { 150 printf("%s: unable to allocate control data, error = %d\n", 151 sc->sc_dev.dv_xname, error); 152 goto fail_0; 153 } 154 155 /* XXX should map this in with correct endianness */ 156 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg, 157 sizeof(struct gem_control_data), (caddr_t *)&sc->sc_control_data, 158 BUS_DMA_COHERENT)) != 0) { 159 printf("%s: unable to map control data, error = %d\n", 160 sc->sc_dev.dv_xname, error); 161 goto fail_1; 162 } 163 164 if ((error = bus_dmamap_create(sc->sc_dmatag, 165 sizeof(struct gem_control_data), 1, 166 sizeof(struct gem_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 167 printf("%s: unable to create control data DMA map, " 168 "error = %d\n", sc->sc_dev.dv_xname, error); 169 goto fail_2; 170 } 171 172 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 173 sc->sc_control_data, sizeof(struct gem_control_data), NULL, 174 0)) != 0) { 175 printf("%s: unable to load control data DMA map, error = %d\n", 176 sc->sc_dev.dv_xname, error); 177 goto fail_3; 178 } 179 180 /* 181 * Initialize the transmit job descriptors. 182 */ 183 SIMPLEQ_INIT(&sc->sc_txfreeq); 184 SIMPLEQ_INIT(&sc->sc_txdirtyq); 185 186 /* 187 * Create the transmit buffer DMA maps. 188 */ 189 for (i = 0; i < GEM_TXQUEUELEN; i++) { 190 struct gem_txsoft *txs; 191 192 txs = &sc->sc_txsoft[i]; 193 txs->txs_mbuf = NULL; 194 if ((error = bus_dmamap_create(sc->sc_dmatag, 195 ETHER_MAX_LEN_JUMBO, GEM_NTXSEGS, 196 ETHER_MAX_LEN_JUMBO, 0, 0, 197 &txs->txs_dmamap)) != 0) { 198 printf("%s: unable to create tx DMA map %d, " 199 "error = %d\n", sc->sc_dev.dv_xname, i, error); 200 goto fail_4; 201 } 202 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 203 } 204 205 /* 206 * Create the receive buffer DMA maps. 207 */ 208 for (i = 0; i < GEM_NRXDESC; i++) { 209 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, 210 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 211 printf("%s: unable to create rx DMA map %d, " 212 "error = %d\n", sc->sc_dev.dv_xname, i, error); 213 goto fail_5; 214 } 215 sc->sc_rxsoft[i].rxs_mbuf = NULL; 216 } 217 218 /* 219 * From this point forward, the attachment cannot fail. A failure 220 * before this point releases all resources that may have been 221 * allocated. 222 */ 223 224 /* Announce ourselves. */ 225 printf("%s: Ethernet address %s", sc->sc_dev.dv_xname, 226 ether_sprintf(enaddr)); 227 228 /* Get RX FIFO size */ 229 sc->sc_rxfifosize = 64 * 230 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_FIFO_SIZE); 231 printf(", %uKB RX fifo", sc->sc_rxfifosize / 1024); 232 233 /* Get TX FIFO size */ 234 v = bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_FIFO_SIZE); 235 printf(", %uKB TX fifo\n", v / 16); 236 237 /* Initialize ifnet structure. */ 238 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 239 ifp->if_softc = sc; 240 ifp->if_flags = 241 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 242 ifp->if_start = gem_start; 243 ifp->if_ioctl = gem_ioctl; 244 ifp->if_watchdog = gem_watchdog; 245 ifp->if_stop = gem_stop; 246 ifp->if_init = gem_init; 247 IFQ_SET_READY(&ifp->if_snd); 248 249 /* Initialize ifmedia structures and MII info */ 250 mii->mii_ifp = ifp; 251 mii->mii_readreg = gem_mii_readreg; 252 mii->mii_writereg = gem_mii_writereg; 253 mii->mii_statchg = gem_mii_statchg; 254 255 ifmedia_init(&mii->mii_media, 0, gem_mediachange, gem_mediastatus); 256 257 gem_mifinit(sc); 258 259 mii_attach(&sc->sc_dev, mii, 0xffffffff, 260 MII_PHY_ANY, MII_OFFSET_ANY, 0); 261 262 child = LIST_FIRST(&mii->mii_phys); 263 if (child == NULL) { 264 /* No PHY attached */ 265 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 266 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 267 } else { 268 /* 269 * Walk along the list of attached MII devices and 270 * establish an `MII instance' to `phy number' 271 * mapping. We'll use this mapping in media change 272 * requests to determine which phy to use to program 273 * the MIF configuration register. 274 */ 275 for (; child != NULL; child = LIST_NEXT(child, mii_list)) { 276 /* 277 * Note: we support just two PHYs: the built-in 278 * internal device and an external on the MII 279 * connector. 280 */ 281 if (child->mii_phy > 1 || child->mii_inst > 1) { 282 printf("%s: cannot accomodate MII device %s" 283 " at phy %d, instance %d\n", 284 sc->sc_dev.dv_xname, 285 child->mii_dev.dv_xname, 286 child->mii_phy, child->mii_inst); 287 continue; 288 } 289 290 sc->sc_phys[child->mii_inst] = child->mii_phy; 291 292 } 293 294 /* 295 * Now select and activate the PHY we will use. 296 * 297 * The order of preference is External (MDI1), 298 * Internal (MDI0), Serial Link (no MII). 299 */ 300 if (sc->sc_phys[1]) { 301 #ifdef DEBUG 302 printf("using external phy\n"); 303 #endif 304 sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL; 305 } else { 306 #ifdef DEBUG 307 printf("using internal phy\n"); 308 #endif 309 sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL; 310 } 311 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_MIF_CONFIG, 312 sc->sc_mif_config); 313 314 /* 315 * XXX - we can really do the following ONLY if the 316 * phy indeed has the auto negotiation capability!! 317 */ 318 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO); 319 } 320 321 /* 322 * If we support GigE media, we support jumbo frames too. 323 * Unless we are Apple. 324 */ 325 TAILQ_FOREACH(ifm, &sc->sc_media.ifm_list, ifm_list) { 326 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_T || 327 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_SX || 328 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_LX || 329 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_CX) { 330 if (sc->sc_variant != GEM_APPLE_GMAC) 331 sc->sc_ethercom.ec_capabilities 332 |= ETHERCAP_JUMBO_MTU; 333 334 sc->sc_flags |= GEM_GIGABIT; 335 break; 336 } 337 } 338 339 /* claim 802.1q capability */ 340 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 341 342 /* Attach the interface. */ 343 if_attach(ifp); 344 ether_ifattach(ifp, enaddr); 345 346 sc->sc_sh = shutdownhook_establish(gem_shutdown, sc); 347 if (sc->sc_sh == NULL) 348 panic("gem_config: can't establish shutdownhook"); 349 350 #if NRND > 0 351 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 352 RND_TYPE_NET, 0); 353 #endif 354 355 356 #if notyet 357 /* 358 * Add a suspend hook to make sure we come back up after a 359 * resume. 360 */ 361 sc->sc_powerhook = powerhook_establish(gem_power, sc); 362 if (sc->sc_powerhook == NULL) 363 printf("%s: WARNING: unable to establish power hook\n", 364 sc->sc_dev.dv_xname); 365 #endif 366 367 callout_init(&sc->sc_tick_ch); 368 return; 369 370 /* 371 * Free any resources we've allocated during the failed attach 372 * attempt. Do this in reverse order and fall through. 373 */ 374 fail_5: 375 for (i = 0; i < GEM_NRXDESC; i++) { 376 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 377 bus_dmamap_destroy(sc->sc_dmatag, 378 sc->sc_rxsoft[i].rxs_dmamap); 379 } 380 fail_4: 381 for (i = 0; i < GEM_TXQUEUELEN; i++) { 382 if (sc->sc_txsoft[i].txs_dmamap != NULL) 383 bus_dmamap_destroy(sc->sc_dmatag, 384 sc->sc_txsoft[i].txs_dmamap); 385 } 386 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 387 fail_3: 388 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 389 fail_2: 390 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)sc->sc_control_data, 391 sizeof(struct gem_control_data)); 392 fail_1: 393 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 394 fail_0: 395 return; 396 } 397 398 399 void 400 gem_tick(arg) 401 void *arg; 402 { 403 struct gem_softc *sc = arg; 404 int s; 405 406 s = splnet(); 407 mii_tick(&sc->sc_mii); 408 splx(s); 409 410 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 411 412 } 413 414 void 415 gem_reset(sc) 416 struct gem_softc *sc; 417 { 418 bus_space_tag_t t = sc->sc_bustag; 419 bus_space_handle_t h = sc->sc_h; 420 int i; 421 int s; 422 423 s = splnet(); 424 DPRINTF(sc, ("%s: gem_reset\n", sc->sc_dev.dv_xname)); 425 gem_reset_rx(sc); 426 gem_reset_tx(sc); 427 428 /* Do a full reset */ 429 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX|GEM_RESET_TX); 430 for (i=TRIES; i--; delay(100)) 431 if ((bus_space_read_4(t, h, GEM_RESET) & 432 (GEM_RESET_RX|GEM_RESET_TX)) == 0) 433 break; 434 if ((bus_space_read_4(t, h, GEM_RESET) & 435 (GEM_RESET_RX|GEM_RESET_TX)) != 0) { 436 printf("%s: cannot reset device\n", 437 sc->sc_dev.dv_xname); 438 } 439 splx(s); 440 } 441 442 443 /* 444 * gem_rxdrain: 445 * 446 * Drain the receive queue. 447 */ 448 void 449 gem_rxdrain(struct gem_softc *sc) 450 { 451 struct gem_rxsoft *rxs; 452 int i; 453 454 for (i = 0; i < GEM_NRXDESC; i++) { 455 rxs = &sc->sc_rxsoft[i]; 456 if (rxs->rxs_mbuf != NULL) { 457 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 458 m_freem(rxs->rxs_mbuf); 459 rxs->rxs_mbuf = NULL; 460 } 461 } 462 } 463 464 /* 465 * Reset the whole thing. 466 */ 467 void 468 gem_stop(struct ifnet *ifp, int disable) 469 { 470 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 471 struct gem_txsoft *txs; 472 473 DPRINTF(sc, ("%s: gem_stop\n", sc->sc_dev.dv_xname)); 474 475 callout_stop(&sc->sc_tick_ch); 476 mii_down(&sc->sc_mii); 477 478 /* XXX - Should we reset these instead? */ 479 gem_disable_rx(sc); 480 gem_disable_rx(sc); 481 482 /* 483 * Release any queued transmit buffers. 484 */ 485 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 486 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs, txs_q); 487 if (txs->txs_mbuf != NULL) { 488 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 489 m_freem(txs->txs_mbuf); 490 txs->txs_mbuf = NULL; 491 } 492 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 493 } 494 495 if (disable) { 496 gem_rxdrain(sc); 497 } 498 499 /* 500 * Mark the interface down and cancel the watchdog timer. 501 */ 502 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 503 ifp->if_timer = 0; 504 } 505 506 507 /* 508 * Reset the receiver 509 */ 510 int 511 gem_reset_rx(struct gem_softc *sc) 512 { 513 bus_space_tag_t t = sc->sc_bustag; 514 bus_space_handle_t h = sc->sc_h; 515 int i; 516 517 518 /* 519 * Resetting while DMA is in progress can cause a bus hang, so we 520 * disable DMA first. 521 */ 522 gem_disable_rx(sc); 523 bus_space_write_4(t, h, GEM_RX_CONFIG, 0); 524 /* Wait till it finishes */ 525 for (i=TRIES; i--; delay(100)) 526 if ((bus_space_read_4(t, h, GEM_RX_CONFIG) & 1) == 0) 527 break; 528 if ((bus_space_read_4(t, h, GEM_RX_CONFIG) & 1) != 0) 529 printf("%s: cannot disable read dma\n", 530 sc->sc_dev.dv_xname); 531 532 /* Wait 5ms extra. */ 533 delay(5000); 534 535 /* Finally, reset the ERX */ 536 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX); 537 /* Wait till it finishes */ 538 for (i=TRIES; i--; delay(100)) 539 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_RX) == 0) 540 break; 541 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_RX) != 0) { 542 printf("%s: cannot reset receiver\n", 543 sc->sc_dev.dv_xname); 544 return (1); 545 } 546 return (0); 547 } 548 549 550 /* 551 * Reset the transmitter 552 */ 553 int 554 gem_reset_tx(struct gem_softc *sc) 555 { 556 bus_space_tag_t t = sc->sc_bustag; 557 bus_space_handle_t h = sc->sc_h; 558 int i; 559 560 /* 561 * Resetting while DMA is in progress can cause a bus hang, so we 562 * disable DMA first. 563 */ 564 gem_disable_tx(sc); 565 bus_space_write_4(t, h, GEM_TX_CONFIG, 0); 566 /* Wait till it finishes */ 567 for (i=TRIES; i--; delay(100)) 568 if ((bus_space_read_4(t, h, GEM_TX_CONFIG) & 1) == 0) 569 break; 570 if ((bus_space_read_4(t, h, GEM_TX_CONFIG) & 1) != 0) 571 printf("%s: cannot disable read dma\n", 572 sc->sc_dev.dv_xname); 573 574 /* Wait 5ms extra. */ 575 delay(5000); 576 577 /* Finally, reset the ETX */ 578 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_TX); 579 /* Wait till it finishes */ 580 for (i=TRIES; i--; delay(100)) 581 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_TX) == 0) 582 break; 583 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_TX) != 0) { 584 printf("%s: cannot reset receiver\n", 585 sc->sc_dev.dv_xname); 586 return (1); 587 } 588 return (0); 589 } 590 591 /* 592 * disable receiver. 593 */ 594 int 595 gem_disable_rx(struct gem_softc *sc) 596 { 597 bus_space_tag_t t = sc->sc_bustag; 598 bus_space_handle_t h = sc->sc_h; 599 int i; 600 u_int32_t cfg; 601 602 /* Flip the enable bit */ 603 cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 604 cfg &= ~GEM_MAC_RX_ENABLE; 605 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg); 606 607 /* Wait for it to finish */ 608 for (i=TRIES; i--; delay(100)) 609 if ((bus_space_read_4(t, h, GEM_MAC_RX_CONFIG) & 610 GEM_MAC_RX_ENABLE) == 0) 611 return (0); 612 return (1); 613 } 614 615 /* 616 * disable transmitter. 617 */ 618 int 619 gem_disable_tx(struct gem_softc *sc) 620 { 621 bus_space_tag_t t = sc->sc_bustag; 622 bus_space_handle_t h = sc->sc_h; 623 int i; 624 u_int32_t cfg; 625 626 /* Flip the enable bit */ 627 cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG); 628 cfg &= ~GEM_MAC_TX_ENABLE; 629 bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg); 630 631 /* Wait for it to finish */ 632 for (i=TRIES; i--; delay(100)) 633 if ((bus_space_read_4(t, h, GEM_MAC_TX_CONFIG) & 634 GEM_MAC_TX_ENABLE) == 0) 635 return (0); 636 return (1); 637 } 638 639 /* 640 * Initialize interface. 641 */ 642 int 643 gem_meminit(struct gem_softc *sc) 644 { 645 struct gem_rxsoft *rxs; 646 int i, error; 647 648 /* 649 * Initialize the transmit descriptor ring. 650 */ 651 memset((void *)sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 652 for (i = 0; i < GEM_NTXDESC; i++) { 653 sc->sc_txdescs[i].gd_flags = 0; 654 sc->sc_txdescs[i].gd_addr = 0; 655 } 656 GEM_CDTXSYNC(sc, 0, GEM_NTXDESC, 657 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 658 sc->sc_txfree = GEM_NTXDESC-1; 659 sc->sc_txnext = 0; 660 sc->sc_txwin = 0; 661 662 /* 663 * Initialize the receive descriptor and receive job 664 * descriptor rings. 665 */ 666 for (i = 0; i < GEM_NRXDESC; i++) { 667 rxs = &sc->sc_rxsoft[i]; 668 if (rxs->rxs_mbuf == NULL) { 669 if ((error = gem_add_rxbuf(sc, i)) != 0) { 670 printf("%s: unable to allocate or map rx " 671 "buffer %d, error = %d\n", 672 sc->sc_dev.dv_xname, i, error); 673 /* 674 * XXX Should attempt to run with fewer receive 675 * XXX buffers instead of just failing. 676 */ 677 gem_rxdrain(sc); 678 return (1); 679 } 680 } else 681 GEM_INIT_RXDESC(sc, i); 682 } 683 sc->sc_rxptr = 0; 684 685 return (0); 686 } 687 688 static int 689 gem_ringsize(int sz) 690 { 691 int v; 692 693 switch (sz) { 694 case 32: 695 v = GEM_RING_SZ_32; 696 break; 697 case 64: 698 v = GEM_RING_SZ_64; 699 break; 700 case 128: 701 v = GEM_RING_SZ_128; 702 break; 703 case 256: 704 v = GEM_RING_SZ_256; 705 break; 706 case 512: 707 v = GEM_RING_SZ_512; 708 break; 709 case 1024: 710 v = GEM_RING_SZ_1024; 711 break; 712 case 2048: 713 v = GEM_RING_SZ_2048; 714 break; 715 case 4096: 716 v = GEM_RING_SZ_4096; 717 break; 718 case 8192: 719 v = GEM_RING_SZ_8192; 720 break; 721 default: 722 printf("gem: invalid Receive Descriptor ring size\n"); 723 break; 724 } 725 return (v); 726 } 727 728 /* 729 * Initialization of interface; set up initialization block 730 * and transmit/receive descriptor rings. 731 */ 732 int 733 gem_init(struct ifnet *ifp) 734 { 735 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 736 bus_space_tag_t t = sc->sc_bustag; 737 bus_space_handle_t h = sc->sc_h; 738 int s; 739 u_int max_frame_size; 740 u_int32_t v; 741 742 s = splnet(); 743 744 DPRINTF(sc, ("%s: gem_init: calling stop\n", sc->sc_dev.dv_xname)); 745 /* 746 * Initialization sequence. The numbered steps below correspond 747 * to the sequence outlined in section 6.3.5.1 in the Ethernet 748 * Channel Engine manual (part of the PCIO manual). 749 * See also the STP2002-STQ document from Sun Microsystems. 750 */ 751 752 /* step 1 & 2. Reset the Ethernet Channel */ 753 gem_stop(ifp, 0); 754 gem_reset(sc); 755 DPRINTF(sc, ("%s: gem_init: restarting\n", sc->sc_dev.dv_xname)); 756 757 /* Re-initialize the MIF */ 758 gem_mifinit(sc); 759 760 /* Call MI reset function if any */ 761 if (sc->sc_hwreset) 762 (*sc->sc_hwreset)(sc); 763 764 /* step 3. Setup data structures in host memory */ 765 gem_meminit(sc); 766 767 /* step 4. TX MAC registers & counters */ 768 gem_init_regs(sc); 769 max_frame_size = max(sc->sc_ethercom.ec_if.if_mtu, ETHERMTU); 770 max_frame_size += ETHER_HDR_LEN + ETHER_CRC_LEN; 771 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 772 max_frame_size += ETHER_VLAN_ENCAP_LEN; 773 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 774 max_frame_size|/* burst size */(0x2000<<16)); 775 776 /* step 5. RX MAC registers & counters */ 777 gem_setladrf(sc); 778 779 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 780 /* NOTE: we use only 32-bit DMA addresses here. */ 781 bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 0); 782 bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 783 784 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0); 785 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 786 787 /* step 8. Global Configuration & Interrupt Mask */ 788 bus_space_write_4(t, h, GEM_INTMASK, 789 ~(GEM_INTR_TX_INTME| 790 GEM_INTR_TX_EMPTY| 791 GEM_INTR_RX_DONE|GEM_INTR_RX_NOBUF| 792 GEM_INTR_RX_TAG_ERR|GEM_INTR_PCS| 793 GEM_INTR_MAC_CONTROL|GEM_INTR_MIF| 794 GEM_INTR_BERR)); 795 bus_space_write_4(t, h, GEM_MAC_RX_MASK, 796 ~(GEM_MAC_RX_DONE|GEM_MAC_RX_FRAME_CNT)); 797 bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXXX */ 798 bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 0); /* XXXX */ 799 800 /* step 9. ETX Configuration: use mostly default values */ 801 802 /* Enable DMA */ 803 v = gem_ringsize(GEM_NTXDESC /*XXX*/); 804 bus_space_write_4(t, h, GEM_TX_CONFIG, 805 v|GEM_TX_CONFIG_TXDMA_EN| 806 ((0x400<<10)&GEM_TX_CONFIG_TXFIFO_TH)); 807 bus_space_write_4(t, h, GEM_TX_KICK, sc->sc_txnext); 808 809 /* step 10. ERX Configuration */ 810 811 /* Encode Receive Descriptor ring size: four possible values */ 812 v = gem_ringsize(GEM_NRXDESC /*XXX*/); 813 814 /* Enable DMA */ 815 bus_space_write_4(t, h, GEM_RX_CONFIG, 816 v|(GEM_THRSH_1024<<GEM_RX_CONFIG_FIFO_THRS_SHIFT)| 817 (2<<GEM_RX_CONFIG_FBOFF_SHFT)|GEM_RX_CONFIG_RXDMA_EN| 818 (0<<GEM_RX_CONFIG_CXM_START_SHFT)); 819 /* 820 * The following value is for an OFF Threshold of about 3/4 full 821 * and an ON Threshold of 1/4 full. 822 */ 823 bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH, 824 (3 * sc->sc_rxfifosize / 256) | 825 ( (sc->sc_rxfifosize / 256) << 12)); 826 bus_space_write_4(t, h, GEM_RX_BLANKING, (6<<12)|6); 827 828 /* step 11. Configure Media */ 829 mii_mediachg(&sc->sc_mii); 830 831 /* XXXX Serial link needs a whole different setup. */ 832 833 834 /* step 12. RX_MAC Configuration Register */ 835 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 836 v |= GEM_MAC_RX_ENABLE; 837 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 838 839 /* step 14. Issue Transmit Pending command */ 840 841 /* Call MI initialization function if any */ 842 if (sc->sc_hwinit) 843 (*sc->sc_hwinit)(sc); 844 845 846 /* step 15. Give the reciever a swift kick */ 847 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4); 848 849 /* Start the one second timer. */ 850 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 851 852 ifp->if_flags |= IFF_RUNNING; 853 ifp->if_flags &= ~IFF_OACTIVE; 854 ifp->if_timer = 0; 855 splx(s); 856 857 return (0); 858 } 859 860 void 861 gem_init_regs(struct gem_softc *sc) 862 { 863 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 864 bus_space_tag_t t = sc->sc_bustag; 865 bus_space_handle_t h = sc->sc_h; 866 const u_char *laddr = LLADDR(ifp->if_sadl); 867 u_int32_t v; 868 869 /* These regs are not cleared on reset */ 870 if (!sc->sc_inited) { 871 872 /* Wooo. Magic values. */ 873 bus_space_write_4(t, h, GEM_MAC_IPG0, 0); 874 bus_space_write_4(t, h, GEM_MAC_IPG1, 8); 875 bus_space_write_4(t, h, GEM_MAC_IPG2, 4); 876 877 bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 878 /* Max frame and max burst size */ 879 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 880 ETHER_MAX_LEN | (0x2000<<16)); 881 882 bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x7); 883 bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x4); 884 bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10); 885 /* Dunno.... */ 886 bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088); 887 bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED, 888 ((laddr[5]<<8)|laddr[4])&0x3ff); 889 890 /* Secondary MAC addr set to 0:0:0:0:0:0 */ 891 bus_space_write_4(t, h, GEM_MAC_ADDR3, 0); 892 bus_space_write_4(t, h, GEM_MAC_ADDR4, 0); 893 bus_space_write_4(t, h, GEM_MAC_ADDR5, 0); 894 895 /* MAC control addr set to 01:80:c2:00:00:01 */ 896 bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001); 897 bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200); 898 bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180); 899 900 /* MAC filter addr set to 0:0:0:0:0:0 */ 901 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0); 902 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0); 903 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0); 904 905 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0); 906 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0); 907 908 sc->sc_inited = 1; 909 } 910 911 /* Counters need to be zeroed */ 912 bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0); 913 bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0); 914 bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0); 915 bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0); 916 bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0); 917 bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0); 918 bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0); 919 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 920 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 921 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 922 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 923 924 /* Un-pause stuff */ 925 #if 0 926 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); 927 #else 928 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0); 929 #endif 930 931 /* 932 * Set the station address. 933 */ 934 bus_space_write_4(t, h, GEM_MAC_ADDR0, (laddr[4]<<8)|laddr[5]); 935 bus_space_write_4(t, h, GEM_MAC_ADDR1, (laddr[2]<<8)|laddr[3]); 936 bus_space_write_4(t, h, GEM_MAC_ADDR2, (laddr[0]<<8)|laddr[1]); 937 938 #if 0 939 if (sc->sc_variant != APPLE_GMAC) 940 return; 941 #endif 942 943 /* 944 * Enable MII outputs. Enable GMII if there is a gigabit PHY. 945 */ 946 sc->sc_mif_config = bus_space_read_4(t, h, GEM_MIF_CONFIG); 947 v = GEM_MAC_XIF_TX_MII_ENA; 948 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) { 949 v |= GEM_MAC_XIF_FDPLX_LED; 950 if (sc->sc_flags & GEM_GIGABIT) 951 v |= GEM_MAC_XIF_GMII_MODE; 952 } 953 bus_space_write_4(t, h, GEM_MAC_XIF_CONFIG, v); 954 } 955 956 void 957 gem_start(ifp) 958 struct ifnet *ifp; 959 { 960 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 961 struct mbuf *m0, *m; 962 struct gem_txsoft *txs, *last_txs; 963 bus_dmamap_t dmamap; 964 int error, firsttx, nexttx, lasttx, ofree, seg; 965 966 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 967 return; 968 969 /* 970 * Remember the previous number of free descriptors and 971 * the first descriptor we'll use. 972 */ 973 ofree = sc->sc_txfree; 974 firsttx = sc->sc_txnext; 975 976 DPRINTF(sc, ("%s: gem_start: txfree %d, txnext %d\n", 977 sc->sc_dev.dv_xname, ofree, firsttx)); 978 979 /* 980 * Loop through the send queue, setting up transmit descriptors 981 * until we drain the queue, or use up all available transmit 982 * descriptors. 983 */ 984 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 985 sc->sc_txfree != 0) { 986 /* 987 * Grab a packet off the queue. 988 */ 989 IFQ_POLL(&ifp->if_snd, m0); 990 if (m0 == NULL) 991 break; 992 m = NULL; 993 994 dmamap = txs->txs_dmamap; 995 996 /* 997 * Load the DMA map. If this fails, the packet either 998 * didn't fit in the alloted number of segments, or we were 999 * short on resources. In this case, we'll copy and try 1000 * again. 1001 */ 1002 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m0, 1003 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1004 if (m0->m_pkthdr.len > MCLBYTES) { 1005 printf("%s: unable to allocate jumbo Tx " 1006 "cluster\n", sc->sc_dev.dv_xname); 1007 IFQ_DEQUEUE(&ifp->if_snd, m0); 1008 m_freem(m0); 1009 continue; 1010 } 1011 MGETHDR(m, M_DONTWAIT, MT_DATA); 1012 if (m == NULL) { 1013 printf("%s: unable to allocate Tx mbuf\n", 1014 sc->sc_dev.dv_xname); 1015 break; 1016 } 1017 if (m0->m_pkthdr.len > MHLEN) { 1018 MCLGET(m, M_DONTWAIT); 1019 if ((m->m_flags & M_EXT) == 0) { 1020 printf("%s: unable to allocate Tx " 1021 "cluster\n", sc->sc_dev.dv_xname); 1022 m_freem(m); 1023 break; 1024 } 1025 } 1026 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 1027 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1028 error = bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, 1029 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1030 if (error) { 1031 printf("%s: unable to load Tx buffer, " 1032 "error = %d\n", sc->sc_dev.dv_xname, error); 1033 break; 1034 } 1035 } 1036 1037 /* 1038 * Ensure we have enough descriptors free to describe 1039 * the packet. 1040 */ 1041 if (dmamap->dm_nsegs > sc->sc_txfree) { 1042 /* 1043 * Not enough free descriptors to transmit this 1044 * packet. We haven't committed to anything yet, 1045 * so just unload the DMA map, put the packet 1046 * back on the queue, and punt. Notify the upper 1047 * layer that there are no more slots left. 1048 * 1049 * XXX We could allocate an mbuf and copy, but 1050 * XXX it is worth it? 1051 */ 1052 ifp->if_flags |= IFF_OACTIVE; 1053 bus_dmamap_unload(sc->sc_dmatag, dmamap); 1054 if (m != NULL) 1055 m_freem(m); 1056 break; 1057 } 1058 1059 IFQ_DEQUEUE(&ifp->if_snd, m0); 1060 if (m != NULL) { 1061 m_freem(m0); 1062 m0 = m; 1063 } 1064 1065 /* 1066 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1067 */ 1068 1069 /* Sync the DMA map. */ 1070 bus_dmamap_sync(sc->sc_dmatag, dmamap, 0, dmamap->dm_mapsize, 1071 BUS_DMASYNC_PREWRITE); 1072 1073 /* 1074 * Initialize the transmit descriptors. 1075 */ 1076 for (nexttx = sc->sc_txnext, seg = 0; 1077 seg < dmamap->dm_nsegs; 1078 seg++, nexttx = GEM_NEXTTX(nexttx)) { 1079 uint64_t flags; 1080 1081 /* 1082 * If this is the first descriptor we're 1083 * enqueueing, set the start of packet flag, 1084 * and the checksum stuff if we want the hardware 1085 * to do it. 1086 */ 1087 sc->sc_txdescs[nexttx].gd_addr = 1088 GEM_DMA_WRITE(sc, dmamap->dm_segs[seg].ds_addr); 1089 flags = dmamap->dm_segs[seg].ds_len & GEM_TD_BUFSIZE; 1090 if (nexttx == firsttx) { 1091 flags |= GEM_TD_START_OF_PACKET; 1092 if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) { 1093 sc->sc_txwin = 0; 1094 flags |= GEM_TD_INTERRUPT_ME; 1095 } 1096 } 1097 if (seg == dmamap->dm_nsegs - 1) { 1098 flags |= GEM_TD_END_OF_PACKET; 1099 } 1100 sc->sc_txdescs[nexttx].gd_flags = 1101 GEM_DMA_WRITE(sc, flags); 1102 lasttx = nexttx; 1103 } 1104 1105 #ifdef GEM_DEBUG 1106 if (ifp->if_flags & IFF_DEBUG) { 1107 printf(" gem_start %p transmit chain:\n", txs); 1108 for (seg = sc->sc_txnext;; seg = GEM_NEXTTX(seg)) { 1109 printf("descriptor %d:\t", seg); 1110 printf("gd_flags: 0x%016llx\t", (long long) 1111 GEM_DMA_READ(sc, sc->sc_txdescs[seg].gd_flags)); 1112 printf("gd_addr: 0x%016llx\n", (long long) 1113 GEM_DMA_READ(sc, sc->sc_txdescs[seg].gd_addr)); 1114 if (seg == lasttx) 1115 break; 1116 } 1117 } 1118 #endif 1119 1120 /* Sync the descriptors we're using. */ 1121 GEM_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1122 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1123 1124 /* 1125 * Store a pointer to the packet so we can free it later, 1126 * and remember what txdirty will be once the packet is 1127 * done. 1128 */ 1129 txs->txs_mbuf = m0; 1130 txs->txs_firstdesc = sc->sc_txnext; 1131 txs->txs_lastdesc = lasttx; 1132 txs->txs_ndescs = dmamap->dm_nsegs; 1133 1134 /* Advance the tx pointer. */ 1135 sc->sc_txfree -= dmamap->dm_nsegs; 1136 sc->sc_txnext = nexttx; 1137 1138 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs, txs_q); 1139 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1140 1141 last_txs = txs; 1142 1143 #if NBPFILTER > 0 1144 /* 1145 * Pass the packet to any BPF listeners. 1146 */ 1147 if (ifp->if_bpf) 1148 bpf_mtap(ifp->if_bpf, m0); 1149 #endif /* NBPFILTER > 0 */ 1150 } 1151 1152 if (txs == NULL || sc->sc_txfree == 0) { 1153 /* No more slots left; notify upper layer. */ 1154 ifp->if_flags |= IFF_OACTIVE; 1155 } 1156 1157 if (sc->sc_txfree != ofree) { 1158 DPRINTF(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 1159 sc->sc_dev.dv_xname, lasttx, firsttx)); 1160 /* 1161 * The entire packet chain is set up. 1162 * Kick the transmitter. 1163 */ 1164 DPRINTF(sc, ("%s: gem_start: kicking tx %d\n", 1165 sc->sc_dev.dv_xname, nexttx)); 1166 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_TX_KICK, 1167 sc->sc_txnext); 1168 1169 /* Set a watchdog timer in case the chip flakes out. */ 1170 ifp->if_timer = 5; 1171 DPRINTF(sc, ("%s: gem_start: watchdog %d\n", 1172 sc->sc_dev.dv_xname, ifp->if_timer)); 1173 } 1174 } 1175 1176 /* 1177 * Transmit interrupt. 1178 */ 1179 int 1180 gem_tint(sc) 1181 struct gem_softc *sc; 1182 { 1183 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1184 bus_space_tag_t t = sc->sc_bustag; 1185 bus_space_handle_t mac = sc->sc_h; 1186 struct gem_txsoft *txs; 1187 int txlast; 1188 int progress = 0; 1189 1190 1191 DPRINTF(sc, ("%s: gem_tint\n", sc->sc_dev.dv_xname)); 1192 1193 /* 1194 * Unload collision counters 1195 */ 1196 ifp->if_collisions += 1197 bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) + 1198 bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT) + 1199 bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) + 1200 bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT); 1201 1202 /* 1203 * then clear the hardware counters. 1204 */ 1205 bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0); 1206 bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0); 1207 bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0); 1208 bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0); 1209 1210 /* 1211 * Go through our Tx list and free mbufs for those 1212 * frames that have been transmitted. 1213 */ 1214 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1215 GEM_CDTXSYNC(sc, txs->txs_lastdesc, 1216 txs->txs_ndescs, 1217 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1218 1219 #ifdef GEM_DEBUG 1220 if (ifp->if_flags & IFF_DEBUG) { 1221 int i; 1222 printf(" txsoft %p transmit chain:\n", txs); 1223 for (i = txs->txs_firstdesc;; i = GEM_NEXTTX(i)) { 1224 printf("descriptor %d: ", i); 1225 printf("gd_flags: 0x%016llx\t", (long long) 1226 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags)); 1227 printf("gd_addr: 0x%016llx\n", (long long) 1228 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr)); 1229 if (i == txs->txs_lastdesc) 1230 break; 1231 } 1232 } 1233 #endif 1234 1235 /* 1236 * In theory, we could harveast some descriptors before 1237 * the ring is empty, but that's a bit complicated. 1238 * 1239 * GEM_TX_COMPLETION points to the last descriptor 1240 * processed +1. 1241 */ 1242 txlast = bus_space_read_4(t, mac, GEM_TX_COMPLETION); 1243 DPRINTF(sc, 1244 ("gem_tint: txs->txs_lastdesc = %d, txlast = %d\n", 1245 txs->txs_lastdesc, txlast)); 1246 if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1247 if ((txlast >= txs->txs_firstdesc) && 1248 (txlast <= txs->txs_lastdesc)) 1249 break; 1250 } else { 1251 /* Ick -- this command wraps */ 1252 if ((txlast >= txs->txs_firstdesc) || 1253 (txlast <= txs->txs_lastdesc)) 1254 break; 1255 } 1256 1257 DPRINTF(sc, ("gem_tint: releasing a desc\n")); 1258 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs, txs_q); 1259 1260 sc->sc_txfree += txs->txs_ndescs; 1261 1262 if (txs->txs_mbuf == NULL) { 1263 #ifdef DIAGNOSTIC 1264 panic("gem_txintr: null mbuf"); 1265 #endif 1266 } 1267 1268 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 1269 0, txs->txs_dmamap->dm_mapsize, 1270 BUS_DMASYNC_POSTWRITE); 1271 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 1272 m_freem(txs->txs_mbuf); 1273 txs->txs_mbuf = NULL; 1274 1275 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1276 1277 ifp->if_opackets++; 1278 progress = 1; 1279 } 1280 1281 DPRINTF(sc, ("gem_tint: GEM_TX_STATE_MACHINE %x " 1282 "GEM_TX_DATA_PTR %llx " 1283 "GEM_TX_COMPLETION %x\n", 1284 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_STATE_MACHINE), 1285 ((long long) bus_space_read_4(sc->sc_bustag, sc->sc_h, 1286 GEM_TX_DATA_PTR_HI) << 32) | 1287 bus_space_read_4(sc->sc_bustag, sc->sc_h, 1288 GEM_TX_DATA_PTR_LO), 1289 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_COMPLETION))); 1290 1291 if (progress) { 1292 if (sc->sc_txfree == GEM_NTXDESC - 1) 1293 sc->sc_txwin = 0; 1294 1295 ifp->if_flags &= ~IFF_OACTIVE; 1296 gem_start(ifp); 1297 1298 if (SIMPLEQ_FIRST(&sc->sc_txdirtyq) == NULL) 1299 ifp->if_timer = 0; 1300 } 1301 DPRINTF(sc, ("%s: gem_tint: watchdog %d\n", 1302 sc->sc_dev.dv_xname, ifp->if_timer)); 1303 1304 return (1); 1305 } 1306 1307 /* 1308 * Receive interrupt. 1309 */ 1310 int 1311 gem_rint(sc) 1312 struct gem_softc *sc; 1313 { 1314 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1315 bus_space_tag_t t = sc->sc_bustag; 1316 bus_space_handle_t h = sc->sc_h; 1317 struct ether_header *eh; 1318 struct gem_rxsoft *rxs; 1319 struct mbuf *m; 1320 u_int64_t rxstat; 1321 int i, len; 1322 1323 DPRINTF(sc, ("%s: gem_rint\n", sc->sc_dev.dv_xname)); 1324 /* 1325 * XXXX Read the lastrx only once at the top for speed. 1326 */ 1327 DPRINTF(sc, ("gem_rint: sc->rxptr %d, complete %d\n", 1328 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION))); 1329 for (i = sc->sc_rxptr; i != bus_space_read_4(t, h, GEM_RX_COMPLETION); 1330 i = GEM_NEXTRX(i)) { 1331 rxs = &sc->sc_rxsoft[i]; 1332 1333 GEM_CDRXSYNC(sc, i, 1334 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1335 1336 rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags); 1337 1338 if (rxstat & GEM_RD_OWN) { 1339 printf("gem_rint: completed descriptor " 1340 "still owned %d\n", i); 1341 /* 1342 * We have processed all of the receive buffers. 1343 */ 1344 break; 1345 } 1346 1347 if (rxstat & GEM_RD_BAD_CRC) { 1348 printf("%s: receive error: CRC error\n", 1349 sc->sc_dev.dv_xname); 1350 GEM_INIT_RXDESC(sc, i); 1351 continue; 1352 } 1353 1354 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1355 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1356 #ifdef GEM_DEBUG 1357 if (ifp->if_flags & IFF_DEBUG) { 1358 printf(" rxsoft %p descriptor %d: ", rxs, i); 1359 printf("gd_flags: 0x%016llx\t", (long long) 1360 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags)); 1361 printf("gd_addr: 0x%016llx\n", (long long) 1362 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr)); 1363 } 1364 #endif 1365 1366 /* 1367 * No errors; receive the packet. Note the Gem 1368 * includes the CRC with every packet. 1369 */ 1370 len = GEM_RD_BUFLEN(rxstat); 1371 1372 /* 1373 * Allocate a new mbuf cluster. If that fails, we are 1374 * out of memory, and must drop the packet and recycle 1375 * the buffer that's already attached to this descriptor. 1376 */ 1377 m = rxs->rxs_mbuf; 1378 if (gem_add_rxbuf(sc, i) != 0) { 1379 ifp->if_ierrors++; 1380 GEM_INIT_RXDESC(sc, i); 1381 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1382 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1383 continue; 1384 } 1385 m->m_data += 2; /* We're already off by two */ 1386 1387 ifp->if_ipackets++; 1388 eh = mtod(m, struct ether_header *); 1389 m->m_flags |= M_HASFCS; 1390 m->m_pkthdr.rcvif = ifp; 1391 m->m_pkthdr.len = m->m_len = len; 1392 1393 #if NBPFILTER > 0 1394 /* 1395 * Pass this up to any BPF listeners, but only 1396 * pass it up the stack if its for us. 1397 */ 1398 if (ifp->if_bpf) 1399 bpf_mtap(ifp->if_bpf, m); 1400 #endif /* NPBFILTER > 0 */ 1401 1402 /* Pass it on. */ 1403 (*ifp->if_input)(ifp, m); 1404 } 1405 1406 /* Update the receive pointer. */ 1407 sc->sc_rxptr = i; 1408 bus_space_write_4(t, h, GEM_RX_KICK, i); 1409 1410 DPRINTF(sc, ("gem_rint: done sc->rxptr %d, complete %d\n", 1411 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION))); 1412 1413 return (1); 1414 } 1415 1416 1417 /* 1418 * gem_add_rxbuf: 1419 * 1420 * Add a receive buffer to the indicated descriptor. 1421 */ 1422 int 1423 gem_add_rxbuf(struct gem_softc *sc, int idx) 1424 { 1425 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1426 struct mbuf *m; 1427 int error; 1428 1429 MGETHDR(m, M_DONTWAIT, MT_DATA); 1430 if (m == NULL) 1431 return (ENOBUFS); 1432 1433 MCLGET(m, M_DONTWAIT); 1434 if ((m->m_flags & M_EXT) == 0) { 1435 m_freem(m); 1436 return (ENOBUFS); 1437 } 1438 1439 #ifdef GEM_DEBUG 1440 /* bzero the packet to check dma */ 1441 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 1442 #endif 1443 1444 if (rxs->rxs_mbuf != NULL) 1445 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 1446 1447 rxs->rxs_mbuf = m; 1448 1449 error = bus_dmamap_load(sc->sc_dmatag, rxs->rxs_dmamap, 1450 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1451 BUS_DMA_READ|BUS_DMA_NOWAIT); 1452 if (error) { 1453 printf("%s: can't load rx DMA map %d, error = %d\n", 1454 sc->sc_dev.dv_xname, idx, error); 1455 panic("gem_add_rxbuf"); /* XXX */ 1456 } 1457 1458 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1459 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1460 1461 GEM_INIT_RXDESC(sc, idx); 1462 1463 return (0); 1464 } 1465 1466 1467 int 1468 gem_eint(sc, status) 1469 struct gem_softc *sc; 1470 u_int status; 1471 { 1472 char bits[128]; 1473 1474 if ((status & GEM_INTR_MIF) != 0) { 1475 printf("%s: XXXlink status changed\n", sc->sc_dev.dv_xname); 1476 return (1); 1477 } 1478 1479 printf("%s: status=%s\n", sc->sc_dev.dv_xname, 1480 bitmask_snprintf(status, GEM_INTR_BITS, bits, sizeof(bits))); 1481 return (1); 1482 } 1483 1484 1485 int 1486 gem_intr(v) 1487 void *v; 1488 { 1489 struct gem_softc *sc = (struct gem_softc *)v; 1490 bus_space_tag_t t = sc->sc_bustag; 1491 bus_space_handle_t seb = sc->sc_h; 1492 u_int32_t status; 1493 int r = 0; 1494 #ifdef GEM_DEBUG 1495 char bits[128]; 1496 #endif 1497 1498 status = bus_space_read_4(t, seb, GEM_STATUS); 1499 DPRINTF(sc, ("%s: gem_intr: cplt %xstatus %s\n", 1500 sc->sc_dev.dv_xname, (status>>19), 1501 bitmask_snprintf(status, GEM_INTR_BITS, bits, sizeof(bits)))); 1502 1503 if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0) 1504 r |= gem_eint(sc, status); 1505 1506 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) 1507 r |= gem_tint(sc); 1508 1509 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) 1510 r |= gem_rint(sc); 1511 1512 /* We should eventually do more than just print out error stats. */ 1513 if (status & GEM_INTR_TX_MAC) { 1514 int txstat = bus_space_read_4(t, seb, GEM_MAC_TX_STATUS); 1515 if (txstat & ~GEM_MAC_TX_XMIT_DONE) 1516 printf("%s: MAC tx fault, status %x\n", 1517 sc->sc_dev.dv_xname, txstat); 1518 } 1519 if (status & GEM_INTR_RX_MAC) { 1520 int rxstat = bus_space_read_4(t, seb, GEM_MAC_RX_STATUS); 1521 if (rxstat & ~GEM_MAC_RX_DONE) 1522 printf("%s: MAC rx fault, status %x\n", 1523 sc->sc_dev.dv_xname, rxstat); 1524 } 1525 return (r); 1526 } 1527 1528 1529 void 1530 gem_watchdog(ifp) 1531 struct ifnet *ifp; 1532 { 1533 struct gem_softc *sc = ifp->if_softc; 1534 1535 DPRINTF(sc, ("gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x " 1536 "GEM_MAC_RX_CONFIG %x\n", 1537 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_CONFIG), 1538 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_STATUS), 1539 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_CONFIG))); 1540 1541 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1542 ++ifp->if_oerrors; 1543 1544 /* Try to get more packets going. */ 1545 gem_start(ifp); 1546 } 1547 1548 /* 1549 * Initialize the MII Management Interface 1550 */ 1551 void 1552 gem_mifinit(sc) 1553 struct gem_softc *sc; 1554 { 1555 bus_space_tag_t t = sc->sc_bustag; 1556 bus_space_handle_t mif = sc->sc_h; 1557 1558 /* Configure the MIF in frame mode */ 1559 sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1560 sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA; 1561 bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config); 1562 } 1563 1564 /* 1565 * MII interface 1566 * 1567 * The GEM MII interface supports at least three different operating modes: 1568 * 1569 * Bitbang mode is implemented using data, clock and output enable registers. 1570 * 1571 * Frame mode is implemented by loading a complete frame into the frame 1572 * register and polling the valid bit for completion. 1573 * 1574 * Polling mode uses the frame register but completion is indicated by 1575 * an interrupt. 1576 * 1577 */ 1578 static int 1579 gem_mii_readreg(self, phy, reg) 1580 struct device *self; 1581 int phy, reg; 1582 { 1583 struct gem_softc *sc = (void *)self; 1584 bus_space_tag_t t = sc->sc_bustag; 1585 bus_space_handle_t mif = sc->sc_h; 1586 int n; 1587 u_int32_t v; 1588 1589 #ifdef GEM_DEBUG1 1590 if (sc->sc_debug) 1591 printf("gem_mii_readreg: phy %d reg %d\n", phy, reg); 1592 #endif 1593 1594 #if 0 1595 /* Select the desired PHY in the MIF configuration register */ 1596 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1597 /* Clear PHY select bit */ 1598 v &= ~GEM_MIF_CONFIG_PHY_SEL; 1599 if (phy == GEM_PHYAD_EXTERNAL) 1600 /* Set PHY select bit to get at external device */ 1601 v |= GEM_MIF_CONFIG_PHY_SEL; 1602 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 1603 #endif 1604 1605 /* Construct the frame command */ 1606 v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) | 1607 GEM_MIF_FRAME_READ; 1608 1609 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1610 for (n = 0; n < 100; n++) { 1611 DELAY(1); 1612 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1613 if (v & GEM_MIF_FRAME_TA0) 1614 return (v & GEM_MIF_FRAME_DATA); 1615 } 1616 1617 printf("%s: mii_read timeout\n", sc->sc_dev.dv_xname); 1618 return (0); 1619 } 1620 1621 static void 1622 gem_mii_writereg(self, phy, reg, val) 1623 struct device *self; 1624 int phy, reg, val; 1625 { 1626 struct gem_softc *sc = (void *)self; 1627 bus_space_tag_t t = sc->sc_bustag; 1628 bus_space_handle_t mif = sc->sc_h; 1629 int n; 1630 u_int32_t v; 1631 1632 #ifdef GEM_DEBUG1 1633 if (sc->sc_debug) 1634 printf("gem_mii_writereg: phy %d reg %d val %x\n", 1635 phy, reg, val); 1636 #endif 1637 1638 #if 0 1639 /* Select the desired PHY in the MIF configuration register */ 1640 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1641 /* Clear PHY select bit */ 1642 v &= ~GEM_MIF_CONFIG_PHY_SEL; 1643 if (phy == GEM_PHYAD_EXTERNAL) 1644 /* Set PHY select bit to get at external device */ 1645 v |= GEM_MIF_CONFIG_PHY_SEL; 1646 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 1647 #endif 1648 /* Construct the frame command */ 1649 v = GEM_MIF_FRAME_WRITE | 1650 (phy << GEM_MIF_PHY_SHIFT) | 1651 (reg << GEM_MIF_REG_SHIFT) | 1652 (val & GEM_MIF_FRAME_DATA); 1653 1654 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1655 for (n = 0; n < 100; n++) { 1656 DELAY(1); 1657 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1658 if (v & GEM_MIF_FRAME_TA0) 1659 return; 1660 } 1661 1662 printf("%s: mii_write timeout\n", sc->sc_dev.dv_xname); 1663 } 1664 1665 static void 1666 gem_mii_statchg(dev) 1667 struct device *dev; 1668 { 1669 struct gem_softc *sc = (void *)dev; 1670 #ifdef GEM_DEBUG 1671 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1672 #endif 1673 bus_space_tag_t t = sc->sc_bustag; 1674 bus_space_handle_t mac = sc->sc_h; 1675 u_int32_t v; 1676 1677 #ifdef GEM_DEBUG 1678 if (sc->sc_debug) 1679 printf("gem_mii_statchg: status change: phy = %d\n", 1680 sc->sc_phys[instance];); 1681 #endif 1682 1683 1684 /* Set tx full duplex options */ 1685 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0); 1686 delay(10000); /* reg must be cleared and delay before changing. */ 1687 v = GEM_MAC_TX_ENA_IPG0|GEM_MAC_TX_NGU|GEM_MAC_TX_NGU_LIMIT| 1688 GEM_MAC_TX_ENABLE; 1689 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) { 1690 v |= GEM_MAC_TX_IGN_CARRIER|GEM_MAC_TX_IGN_COLLIS; 1691 } 1692 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, v); 1693 1694 /* XIF Configuration */ 1695 /* We should really calculate all this rather than rely on defaults */ 1696 v = bus_space_read_4(t, mac, GEM_MAC_XIF_CONFIG); 1697 v = GEM_MAC_XIF_LINK_LED; 1698 v |= GEM_MAC_XIF_TX_MII_ENA; 1699 1700 /* If an external transceiver is connected, enable its MII drivers */ 1701 sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG); 1702 if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) { 1703 /* External MII needs echo disable if half duplex. */ 1704 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1705 /* turn on full duplex LED */ 1706 v |= GEM_MAC_XIF_FDPLX_LED; 1707 else 1708 /* half duplex -- disable echo */ 1709 v |= GEM_MAC_XIF_ECHO_DISABL; 1710 1711 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 1712 v |= GEM_MAC_XIF_GMII_MODE; 1713 else 1714 v &= ~GEM_MAC_XIF_GMII_MODE; 1715 } else 1716 /* Internal MII needs buf enable */ 1717 v |= GEM_MAC_XIF_MII_BUF_ENA; 1718 bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v); 1719 } 1720 1721 int 1722 gem_mediachange(ifp) 1723 struct ifnet *ifp; 1724 { 1725 struct gem_softc *sc = ifp->if_softc; 1726 1727 if (IFM_TYPE(sc->sc_media.ifm_media) != IFM_ETHER) 1728 return (EINVAL); 1729 1730 return (mii_mediachg(&sc->sc_mii)); 1731 } 1732 1733 void 1734 gem_mediastatus(ifp, ifmr) 1735 struct ifnet *ifp; 1736 struct ifmediareq *ifmr; 1737 { 1738 struct gem_softc *sc = ifp->if_softc; 1739 1740 if ((ifp->if_flags & IFF_UP) == 0) 1741 return; 1742 1743 mii_pollstat(&sc->sc_mii); 1744 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1745 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1746 } 1747 1748 int gem_ioctldebug = 0; 1749 /* 1750 * Process an ioctl request. 1751 */ 1752 int 1753 gem_ioctl(ifp, cmd, data) 1754 struct ifnet *ifp; 1755 u_long cmd; 1756 caddr_t data; 1757 { 1758 struct gem_softc *sc = ifp->if_softc; 1759 struct ifreq *ifr = (struct ifreq *)data; 1760 int s, error = 0; 1761 1762 1763 switch (cmd) { 1764 case SIOCGIFMEDIA: 1765 case SIOCSIFMEDIA: 1766 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1767 break; 1768 1769 default: 1770 error = ether_ioctl(ifp, cmd, data); 1771 if (error == ENETRESET) { 1772 /* 1773 * Multicast list has changed; set the hardware filter 1774 * accordingly. 1775 */ 1776 if (gem_ioctldebug) printf("reset1\n"); 1777 gem_init(ifp); 1778 delay(50000); 1779 error = 0; 1780 } 1781 break; 1782 } 1783 1784 /* Try to get things going again */ 1785 if (ifp->if_flags & IFF_UP) { 1786 if (gem_ioctldebug) printf("start\n"); 1787 gem_start(ifp); 1788 } 1789 splx(s); 1790 return (error); 1791 } 1792 1793 1794 void 1795 gem_shutdown(arg) 1796 void *arg; 1797 { 1798 struct gem_softc *sc = (struct gem_softc *)arg; 1799 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1800 1801 gem_stop(ifp, 1); 1802 } 1803 1804 /* 1805 * Set up the logical address filter. 1806 */ 1807 void 1808 gem_setladrf(sc) 1809 struct gem_softc *sc; 1810 { 1811 struct ethercom *ec = &sc->sc_ethercom; 1812 struct ifnet *ifp = &ec->ec_if; 1813 struct ether_multi *enm; 1814 struct ether_multistep step; 1815 bus_space_tag_t t = sc->sc_bustag; 1816 bus_space_handle_t h = sc->sc_h; 1817 u_int32_t crc; 1818 u_int32_t hash[16]; 1819 u_int32_t v; 1820 int i; 1821 1822 /* Get current RX configuration */ 1823 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 1824 1825 /* 1826 * Turn off promiscuous mode, promiscuous group mode (all multicast), 1827 * and hash filter. Depending on the case, the right bit will be 1828 * enabled. 1829 */ 1830 v &= ~(GEM_MAC_RX_PROMISCUOUS|GEM_MAC_RX_HASH_FILTER| 1831 GEM_MAC_RX_PROMISC_GRP); 1832 1833 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1834 /* Turn on promiscuous mode */ 1835 v |= GEM_MAC_RX_PROMISCUOUS; 1836 ifp->if_flags |= IFF_ALLMULTI; 1837 goto chipit; 1838 } 1839 1840 /* 1841 * Set up multicast address filter by passing all multicast addresses 1842 * through a crc generator, and then using the high order 8 bits as an 1843 * index into the 256 bit logical address filter. The high order 4 1844 * bits select the word, while the other 4 bits select the bit within 1845 * the word (where bit 0 is the MSB). 1846 */ 1847 1848 /* Clear hash table */ 1849 memset(hash, 0, sizeof(hash)); 1850 1851 ETHER_FIRST_MULTI(step, ec, enm); 1852 while (enm != NULL) { 1853 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1854 /* 1855 * We must listen to a range of multicast addresses. 1856 * For now, just accept all multicasts, rather than 1857 * trying to set only those filter bits needed to match 1858 * the range. (At this time, the only use of address 1859 * ranges is for IP multicast routing, for which the 1860 * range is big enough to require all bits set.) 1861 * XXX use the addr filter for this 1862 */ 1863 ifp->if_flags |= IFF_ALLMULTI; 1864 v |= GEM_MAC_RX_PROMISC_GRP; 1865 goto chipit; 1866 } 1867 1868 /* Get the LE CRC32 of the address */ 1869 crc = ether_crc32_le(enm->enm_addrlo, sizeof(enm->enm_addrlo)); 1870 1871 /* Just want the 8 most significant bits. */ 1872 crc >>= 24; 1873 1874 /* Set the corresponding bit in the filter. */ 1875 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 1876 1877 ETHER_NEXT_MULTI(step, enm); 1878 } 1879 1880 v |= GEM_MAC_RX_HASH_FILTER; 1881 ifp->if_flags &= ~IFF_ALLMULTI; 1882 1883 /* Now load the hash table into the chip (if we are using it) */ 1884 for (i = 0; i < 16; i++) { 1885 bus_space_write_4(t, h, 1886 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1-GEM_MAC_HASH0), 1887 hash[i]); 1888 } 1889 1890 chipit: 1891 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 1892 } 1893 1894 #if notyet 1895 1896 /* 1897 * gem_power: 1898 * 1899 * Power management (suspend/resume) hook. 1900 */ 1901 void 1902 gem_power(why, arg) 1903 int why; 1904 void *arg; 1905 { 1906 struct gem_softc *sc = arg; 1907 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1908 int s; 1909 1910 s = splnet(); 1911 switch (why) { 1912 case PWR_SUSPEND: 1913 case PWR_STANDBY: 1914 gem_stop(ifp, 1); 1915 if (sc->sc_power != NULL) 1916 (*sc->sc_power)(sc, why); 1917 break; 1918 case PWR_RESUME: 1919 if (ifp->if_flags & IFF_UP) { 1920 if (sc->sc_power != NULL) 1921 (*sc->sc_power)(sc, why); 1922 gem_init(ifp); 1923 } 1924 break; 1925 case PWR_SOFTSUSPEND: 1926 case PWR_SOFTSTANDBY: 1927 case PWR_SOFTRESUME: 1928 break; 1929 } 1930 splx(s); 1931 } 1932 #endif 1933
Indexes created Tue Sep 23 07:09:52 GMT 2025