gem.c revision 1.23
1 /* $NetBSD: gem.c,v 1.23 2002/10/22 00:01:56 fair Exp $ */ 2 3 /* 4 * 5 * Copyright (C) 2001 Eduardo Horvath. 6 * All rights reserved. 7 * 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 */ 31 32 /* 33 * Driver for Sun GEM ethernet controllers. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: gem.c,v 1.23 2002/10/22 00:01:56 fair Exp $"); 38 39 #include "bpfilter.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/callout.h> 44 #include <sys/mbuf.h> 45 #include <sys/syslog.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #include <sys/socket.h> 49 #include <sys/ioctl.h> 50 #include <sys/errno.h> 51 #include <sys/device.h> 52 53 #include <machine/endian.h> 54 55 #include <uvm/uvm_extern.h> 56 57 #include <net/if.h> 58 #include <net/if_dl.h> 59 #include <net/if_media.h> 60 #include <net/if_ether.h> 61 62 #if NBPFILTER > 0 63 #include <net/bpf.h> 64 #endif 65 66 #include <machine/bus.h> 67 #include <machine/intr.h> 68 69 #include <dev/mii/mii.h> 70 #include <dev/mii/miivar.h> 71 #include <dev/mii/mii_bitbang.h> 72 73 #include <dev/ic/gemreg.h> 74 #include <dev/ic/gemvar.h> 75 76 #define TRIES 10000 77 78 void gem_start __P((struct ifnet *)); 79 void gem_stop __P((struct ifnet *, int)); 80 int gem_ioctl __P((struct ifnet *, u_long, caddr_t)); 81 void gem_tick __P((void *)); 82 void gem_watchdog __P((struct ifnet *)); 83 void gem_shutdown __P((void *)); 84 int gem_init __P((struct ifnet *)); 85 void gem_init_regs(struct gem_softc *sc); 86 static int gem_ringsize(int sz); 87 int gem_meminit __P((struct gem_softc *)); 88 void gem_mifinit __P((struct gem_softc *)); 89 void gem_reset __P((struct gem_softc *)); 90 int gem_reset_rx(struct gem_softc *sc); 91 int gem_reset_tx(struct gem_softc *sc); 92 int gem_disable_rx(struct gem_softc *sc); 93 int gem_disable_tx(struct gem_softc *sc); 94 void gem_rxdrain(struct gem_softc *sc); 95 int gem_add_rxbuf(struct gem_softc *sc, int idx); 96 void gem_setladrf __P((struct gem_softc *)); 97 98 /* MII methods & callbacks */ 99 static int gem_mii_readreg __P((struct device *, int, int)); 100 static void gem_mii_writereg __P((struct device *, int, int, int)); 101 static void gem_mii_statchg __P((struct device *)); 102 103 int gem_mediachange __P((struct ifnet *)); 104 void gem_mediastatus __P((struct ifnet *, struct ifmediareq *)); 105 106 struct mbuf *gem_get __P((struct gem_softc *, int, int)); 107 int gem_put __P((struct gem_softc *, int, struct mbuf *)); 108 void gem_read __P((struct gem_softc *, int, int)); 109 int gem_eint __P((struct gem_softc *, u_int)); 110 int gem_rint __P((struct gem_softc *)); 111 int gem_tint __P((struct gem_softc *)); 112 void gem_power __P((int, void *)); 113 114 #ifdef GEM_DEBUG 115 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 116 printf x 117 #else 118 #define DPRINTF(sc, x) /* nothing */ 119 #endif 120 121 122 /* 123 * gem_attach: 124 * 125 * Attach a Gem interface to the system. 126 */ 127 void 128 gem_attach(sc, enaddr) 129 struct gem_softc *sc; 130 const uint8_t *enaddr; 131 { 132 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 133 struct mii_data *mii = &sc->sc_mii; 134 struct mii_softc *child; 135 struct ifmedia_entry *ifm; 136 int i, error; 137 u_int32_t v; 138 139 /* Make sure the chip is stopped. */ 140 ifp->if_softc = sc; 141 gem_reset(sc); 142 143 /* 144 * Allocate the control data structures, and create and load the 145 * DMA map for it. 146 */ 147 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 148 sizeof(struct gem_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 149 1, &sc->sc_cdnseg, 0)) != 0) { 150 printf("%s: unable to allocate control data, error = %d\n", 151 sc->sc_dev.dv_xname, error); 152 goto fail_0; 153 } 154 155 /* XXX should map this in with correct endianness */ 156 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg, 157 sizeof(struct gem_control_data), (caddr_t *)&sc->sc_control_data, 158 BUS_DMA_COHERENT)) != 0) { 159 printf("%s: unable to map control data, error = %d\n", 160 sc->sc_dev.dv_xname, error); 161 goto fail_1; 162 } 163 164 if ((error = bus_dmamap_create(sc->sc_dmatag, 165 sizeof(struct gem_control_data), 1, 166 sizeof(struct gem_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 167 printf("%s: unable to create control data DMA map, " 168 "error = %d\n", sc->sc_dev.dv_xname, error); 169 goto fail_2; 170 } 171 172 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 173 sc->sc_control_data, sizeof(struct gem_control_data), NULL, 174 0)) != 0) { 175 printf("%s: unable to load control data DMA map, error = %d\n", 176 sc->sc_dev.dv_xname, error); 177 goto fail_3; 178 } 179 180 /* 181 * Initialize the transmit job descriptors. 182 */ 183 SIMPLEQ_INIT(&sc->sc_txfreeq); 184 SIMPLEQ_INIT(&sc->sc_txdirtyq); 185 186 /* 187 * Create the transmit buffer DMA maps. 188 */ 189 for (i = 0; i < GEM_TXQUEUELEN; i++) { 190 struct gem_txsoft *txs; 191 192 txs = &sc->sc_txsoft[i]; 193 txs->txs_mbuf = NULL; 194 if ((error = bus_dmamap_create(sc->sc_dmatag, 195 ETHER_MAX_LEN_JUMBO, GEM_NTXSEGS, 196 ETHER_MAX_LEN_JUMBO, 0, 0, 197 &txs->txs_dmamap)) != 0) { 198 printf("%s: unable to create tx DMA map %d, " 199 "error = %d\n", sc->sc_dev.dv_xname, i, error); 200 goto fail_4; 201 } 202 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 203 } 204 205 /* 206 * Create the receive buffer DMA maps. 207 */ 208 for (i = 0; i < GEM_NRXDESC; i++) { 209 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, 210 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 211 printf("%s: unable to create rx DMA map %d, " 212 "error = %d\n", sc->sc_dev.dv_xname, i, error); 213 goto fail_5; 214 } 215 sc->sc_rxsoft[i].rxs_mbuf = NULL; 216 } 217 218 /* 219 * From this point forward, the attachment cannot fail. A failure 220 * before this point releases all resources that may have been 221 * allocated. 222 */ 223 224 /* Announce ourselves. */ 225 printf("%s: Ethernet address %s", sc->sc_dev.dv_xname, 226 ether_sprintf(enaddr)); 227 228 /* Get RX FIFO size */ 229 sc->sc_rxfifosize = 64 * 230 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_FIFO_SIZE); 231 printf(", %uKB RX fifo", sc->sc_rxfifosize / 1024); 232 233 /* Get TX FIFO size */ 234 v = bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_FIFO_SIZE); 235 printf(", %uKB TX fifo\n", v / 16); 236 237 /* Initialize ifnet structure. */ 238 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 239 ifp->if_softc = sc; 240 ifp->if_flags = 241 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 242 ifp->if_start = gem_start; 243 ifp->if_ioctl = gem_ioctl; 244 ifp->if_watchdog = gem_watchdog; 245 ifp->if_stop = gem_stop; 246 ifp->if_init = gem_init; 247 IFQ_SET_READY(&ifp->if_snd); 248 249 /* Initialize ifmedia structures and MII info */ 250 mii->mii_ifp = ifp; 251 mii->mii_readreg = gem_mii_readreg; 252 mii->mii_writereg = gem_mii_writereg; 253 mii->mii_statchg = gem_mii_statchg; 254 255 ifmedia_init(&mii->mii_media, IFM_IMASK, gem_mediachange, gem_mediastatus); 256 257 gem_mifinit(sc); 258 259 mii_attach(&sc->sc_dev, mii, 0xffffffff, 260 MII_PHY_ANY, MII_OFFSET_ANY, 0); 261 262 child = LIST_FIRST(&mii->mii_phys); 263 if (child == NULL) { 264 /* No PHY attached */ 265 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 266 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 267 } else { 268 /* 269 * Walk along the list of attached MII devices and 270 * establish an `MII instance' to `phy number' 271 * mapping. We'll use this mapping in media change 272 * requests to determine which phy to use to program 273 * the MIF configuration register. 274 */ 275 for (; child != NULL; child = LIST_NEXT(child, mii_list)) { 276 /* 277 * Note: we support just two PHYs: the built-in 278 * internal device and an external on the MII 279 * connector. 280 */ 281 if (child->mii_phy > 1 || child->mii_inst > 1) { 282 printf("%s: cannot accomodate MII device %s" 283 " at phy %d, instance %d\n", 284 sc->sc_dev.dv_xname, 285 child->mii_dev.dv_xname, 286 child->mii_phy, child->mii_inst); 287 continue; 288 } 289 290 sc->sc_phys[child->mii_inst] = child->mii_phy; 291 292 } 293 294 /* 295 * Now select and activate the PHY we will use. 296 * 297 * The order of preference is External (MDI1), 298 * Internal (MDI0), Serial Link (no MII). 299 */ 300 if (sc->sc_phys[1]) { 301 #ifdef DEBUG 302 printf("using external phy\n"); 303 #endif 304 sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL; 305 } else { 306 #ifdef DEBUG 307 printf("using internal phy\n"); 308 #endif 309 sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL; 310 } 311 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_MIF_CONFIG, 312 sc->sc_mif_config); 313 314 /* 315 * XXX - we can really do the following ONLY if the 316 * phy indeed has the auto negotiation capability!! 317 */ 318 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO); 319 } 320 321 /* 322 * If we support GigE media, we support jumbo frames too. 323 * Unless we are Apple. 324 */ 325 TAILQ_FOREACH(ifm, &sc->sc_media.ifm_list, ifm_list) { 326 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_T || 327 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_SX || 328 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_LX || 329 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_CX) { 330 if (sc->sc_variant != GEM_APPLE_GMAC) 331 sc->sc_ethercom.ec_capabilities 332 |= ETHERCAP_JUMBO_MTU; 333 334 sc->sc_flags |= GEM_GIGABIT; 335 break; 336 } 337 } 338 339 /* claim 802.1q capability */ 340 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 341 342 /* Attach the interface. */ 343 if_attach(ifp); 344 ether_ifattach(ifp, enaddr); 345 346 sc->sc_sh = shutdownhook_establish(gem_shutdown, sc); 347 if (sc->sc_sh == NULL) 348 panic("gem_config: can't establish shutdownhook"); 349 350 #if NRND > 0 351 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 352 RND_TYPE_NET, 0); 353 #endif 354 355 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, 356 NULL, sc->sc_dev.dv_xname, "interrupts"); 357 #ifdef GEM_COUNTERS 358 evcnt_attach_dynamic(&sc->sc_ev_txint, EVCNT_TYPE_INTR, 359 &sc->sc_ev_intr, sc->sc_dev.dv_xname, "tx interrupts"); 360 evcnt_attach_dynamic(&sc->sc_ev_rxint, EVCNT_TYPE_INTR, 361 &sc->sc_ev_intr, sc->sc_dev.dv_xname, "rx interrupts"); 362 evcnt_attach_dynamic(&sc->sc_ev_rxfull, EVCNT_TYPE_INTR, 363 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx ring full"); 364 evcnt_attach_dynamic(&sc->sc_ev_rxnobuf, EVCNT_TYPE_INTR, 365 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx malloc failure"); 366 evcnt_attach_dynamic(&sc->sc_ev_rxhist[0], EVCNT_TYPE_INTR, 367 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 0desc"); 368 evcnt_attach_dynamic(&sc->sc_ev_rxhist[1], EVCNT_TYPE_INTR, 369 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 1desc"); 370 evcnt_attach_dynamic(&sc->sc_ev_rxhist[2], EVCNT_TYPE_INTR, 371 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 2desc"); 372 evcnt_attach_dynamic(&sc->sc_ev_rxhist[3], EVCNT_TYPE_INTR, 373 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 3desc"); 374 evcnt_attach_dynamic(&sc->sc_ev_rxhist[4], EVCNT_TYPE_INTR, 375 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >3desc"); 376 evcnt_attach_dynamic(&sc->sc_ev_rxhist[5], EVCNT_TYPE_INTR, 377 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >7desc"); 378 evcnt_attach_dynamic(&sc->sc_ev_rxhist[6], EVCNT_TYPE_INTR, 379 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >15desc"); 380 evcnt_attach_dynamic(&sc->sc_ev_rxhist[7], EVCNT_TYPE_INTR, 381 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >31desc"); 382 evcnt_attach_dynamic(&sc->sc_ev_rxhist[8], EVCNT_TYPE_INTR, 383 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >63desc"); 384 #endif 385 386 #if notyet 387 /* 388 * Add a suspend hook to make sure we come back up after a 389 * resume. 390 */ 391 sc->sc_powerhook = powerhook_establish(gem_power, sc); 392 if (sc->sc_powerhook == NULL) 393 printf("%s: WARNING: unable to establish power hook\n", 394 sc->sc_dev.dv_xname); 395 #endif 396 397 callout_init(&sc->sc_tick_ch); 398 return; 399 400 /* 401 * Free any resources we've allocated during the failed attach 402 * attempt. Do this in reverse order and fall through. 403 */ 404 fail_5: 405 for (i = 0; i < GEM_NRXDESC; i++) { 406 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 407 bus_dmamap_destroy(sc->sc_dmatag, 408 sc->sc_rxsoft[i].rxs_dmamap); 409 } 410 fail_4: 411 for (i = 0; i < GEM_TXQUEUELEN; i++) { 412 if (sc->sc_txsoft[i].txs_dmamap != NULL) 413 bus_dmamap_destroy(sc->sc_dmatag, 414 sc->sc_txsoft[i].txs_dmamap); 415 } 416 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 417 fail_3: 418 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 419 fail_2: 420 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)sc->sc_control_data, 421 sizeof(struct gem_control_data)); 422 fail_1: 423 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 424 fail_0: 425 return; 426 } 427 428 429 void 430 gem_tick(arg) 431 void *arg; 432 { 433 struct gem_softc *sc = arg; 434 int s; 435 436 s = splnet(); 437 mii_tick(&sc->sc_mii); 438 splx(s); 439 440 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 441 442 } 443 444 void 445 gem_reset(sc) 446 struct gem_softc *sc; 447 { 448 bus_space_tag_t t = sc->sc_bustag; 449 bus_space_handle_t h = sc->sc_h; 450 int i; 451 int s; 452 453 s = splnet(); 454 DPRINTF(sc, ("%s: gem_reset\n", sc->sc_dev.dv_xname)); 455 gem_reset_rx(sc); 456 gem_reset_tx(sc); 457 458 /* Do a full reset */ 459 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX|GEM_RESET_TX); 460 for (i=TRIES; i--; delay(100)) 461 if ((bus_space_read_4(t, h, GEM_RESET) & 462 (GEM_RESET_RX|GEM_RESET_TX)) == 0) 463 break; 464 if ((bus_space_read_4(t, h, GEM_RESET) & 465 (GEM_RESET_RX|GEM_RESET_TX)) != 0) { 466 printf("%s: cannot reset device\n", 467 sc->sc_dev.dv_xname); 468 } 469 splx(s); 470 } 471 472 473 /* 474 * gem_rxdrain: 475 * 476 * Drain the receive queue. 477 */ 478 void 479 gem_rxdrain(struct gem_softc *sc) 480 { 481 struct gem_rxsoft *rxs; 482 int i; 483 484 for (i = 0; i < GEM_NRXDESC; i++) { 485 rxs = &sc->sc_rxsoft[i]; 486 if (rxs->rxs_mbuf != NULL) { 487 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 488 m_freem(rxs->rxs_mbuf); 489 rxs->rxs_mbuf = NULL; 490 } 491 } 492 } 493 494 /* 495 * Reset the whole thing. 496 */ 497 void 498 gem_stop(struct ifnet *ifp, int disable) 499 { 500 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 501 struct gem_txsoft *txs; 502 503 DPRINTF(sc, ("%s: gem_stop\n", sc->sc_dev.dv_xname)); 504 505 callout_stop(&sc->sc_tick_ch); 506 mii_down(&sc->sc_mii); 507 508 /* XXX - Should we reset these instead? */ 509 gem_disable_rx(sc); 510 gem_disable_tx(sc); 511 512 /* 513 * Release any queued transmit buffers. 514 */ 515 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 516 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 517 if (txs->txs_mbuf != NULL) { 518 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 519 m_freem(txs->txs_mbuf); 520 txs->txs_mbuf = NULL; 521 } 522 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 523 } 524 525 if (disable) { 526 gem_rxdrain(sc); 527 } 528 529 /* 530 * Mark the interface down and cancel the watchdog timer. 531 */ 532 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 533 ifp->if_timer = 0; 534 } 535 536 537 /* 538 * Reset the receiver 539 */ 540 int 541 gem_reset_rx(struct gem_softc *sc) 542 { 543 bus_space_tag_t t = sc->sc_bustag; 544 bus_space_handle_t h = sc->sc_h; 545 int i; 546 547 548 /* 549 * Resetting while DMA is in progress can cause a bus hang, so we 550 * disable DMA first. 551 */ 552 gem_disable_rx(sc); 553 bus_space_write_4(t, h, GEM_RX_CONFIG, 0); 554 /* Wait till it finishes */ 555 for (i=TRIES; i--; delay(100)) 556 if ((bus_space_read_4(t, h, GEM_RX_CONFIG) & 1) == 0) 557 break; 558 if ((bus_space_read_4(t, h, GEM_RX_CONFIG) & 1) != 0) 559 printf("%s: cannot disable read dma\n", 560 sc->sc_dev.dv_xname); 561 562 /* Wait 5ms extra. */ 563 delay(5000); 564 565 /* Finally, reset the ERX */ 566 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX); 567 /* Wait till it finishes */ 568 for (i=TRIES; i--; delay(100)) 569 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_RX) == 0) 570 break; 571 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_RX) != 0) { 572 printf("%s: cannot reset receiver\n", 573 sc->sc_dev.dv_xname); 574 return (1); 575 } 576 return (0); 577 } 578 579 580 /* 581 * Reset the transmitter 582 */ 583 int 584 gem_reset_tx(struct gem_softc *sc) 585 { 586 bus_space_tag_t t = sc->sc_bustag; 587 bus_space_handle_t h = sc->sc_h; 588 int i; 589 590 /* 591 * Resetting while DMA is in progress can cause a bus hang, so we 592 * disable DMA first. 593 */ 594 gem_disable_tx(sc); 595 bus_space_write_4(t, h, GEM_TX_CONFIG, 0); 596 /* Wait till it finishes */ 597 for (i=TRIES; i--; delay(100)) 598 if ((bus_space_read_4(t, h, GEM_TX_CONFIG) & 1) == 0) 599 break; 600 if ((bus_space_read_4(t, h, GEM_TX_CONFIG) & 1) != 0) 601 printf("%s: cannot disable read dma\n", 602 sc->sc_dev.dv_xname); 603 604 /* Wait 5ms extra. */ 605 delay(5000); 606 607 /* Finally, reset the ETX */ 608 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_TX); 609 /* Wait till it finishes */ 610 for (i=TRIES; i--; delay(100)) 611 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_TX) == 0) 612 break; 613 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_TX) != 0) { 614 printf("%s: cannot reset receiver\n", 615 sc->sc_dev.dv_xname); 616 return (1); 617 } 618 return (0); 619 } 620 621 /* 622 * disable receiver. 623 */ 624 int 625 gem_disable_rx(struct gem_softc *sc) 626 { 627 bus_space_tag_t t = sc->sc_bustag; 628 bus_space_handle_t h = sc->sc_h; 629 int i; 630 u_int32_t cfg; 631 632 /* Flip the enable bit */ 633 cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 634 cfg &= ~GEM_MAC_RX_ENABLE; 635 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg); 636 637 /* Wait for it to finish */ 638 for (i=TRIES; i--; delay(100)) 639 if ((bus_space_read_4(t, h, GEM_MAC_RX_CONFIG) & 640 GEM_MAC_RX_ENABLE) == 0) 641 return (0); 642 return (1); 643 } 644 645 /* 646 * disable transmitter. 647 */ 648 int 649 gem_disable_tx(struct gem_softc *sc) 650 { 651 bus_space_tag_t t = sc->sc_bustag; 652 bus_space_handle_t h = sc->sc_h; 653 int i; 654 u_int32_t cfg; 655 656 /* Flip the enable bit */ 657 cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG); 658 cfg &= ~GEM_MAC_TX_ENABLE; 659 bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg); 660 661 /* Wait for it to finish */ 662 for (i=TRIES; i--; delay(100)) 663 if ((bus_space_read_4(t, h, GEM_MAC_TX_CONFIG) & 664 GEM_MAC_TX_ENABLE) == 0) 665 return (0); 666 return (1); 667 } 668 669 /* 670 * Initialize interface. 671 */ 672 int 673 gem_meminit(struct gem_softc *sc) 674 { 675 struct gem_rxsoft *rxs; 676 int i, error; 677 678 /* 679 * Initialize the transmit descriptor ring. 680 */ 681 memset((void *)sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 682 for (i = 0; i < GEM_NTXDESC; i++) { 683 sc->sc_txdescs[i].gd_flags = 0; 684 sc->sc_txdescs[i].gd_addr = 0; 685 } 686 GEM_CDTXSYNC(sc, 0, GEM_NTXDESC, 687 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 688 sc->sc_txfree = GEM_NTXDESC-1; 689 sc->sc_txnext = 0; 690 sc->sc_txwin = 0; 691 692 /* 693 * Initialize the receive descriptor and receive job 694 * descriptor rings. 695 */ 696 for (i = 0; i < GEM_NRXDESC; i++) { 697 rxs = &sc->sc_rxsoft[i]; 698 if (rxs->rxs_mbuf == NULL) { 699 if ((error = gem_add_rxbuf(sc, i)) != 0) { 700 printf("%s: unable to allocate or map rx " 701 "buffer %d, error = %d\n", 702 sc->sc_dev.dv_xname, i, error); 703 /* 704 * XXX Should attempt to run with fewer receive 705 * XXX buffers instead of just failing. 706 */ 707 gem_rxdrain(sc); 708 return (1); 709 } 710 } else 711 GEM_INIT_RXDESC(sc, i); 712 } 713 sc->sc_rxptr = 0; 714 715 return (0); 716 } 717 718 static int 719 gem_ringsize(int sz) 720 { 721 int v; 722 723 switch (sz) { 724 case 32: 725 v = GEM_RING_SZ_32; 726 break; 727 case 64: 728 v = GEM_RING_SZ_64; 729 break; 730 case 128: 731 v = GEM_RING_SZ_128; 732 break; 733 case 256: 734 v = GEM_RING_SZ_256; 735 break; 736 case 512: 737 v = GEM_RING_SZ_512; 738 break; 739 case 1024: 740 v = GEM_RING_SZ_1024; 741 break; 742 case 2048: 743 v = GEM_RING_SZ_2048; 744 break; 745 case 4096: 746 v = GEM_RING_SZ_4096; 747 break; 748 case 8192: 749 v = GEM_RING_SZ_8192; 750 break; 751 default: 752 printf("gem: invalid Receive Descriptor ring size\n"); 753 break; 754 } 755 return (v); 756 } 757 758 /* 759 * Initialization of interface; set up initialization block 760 * and transmit/receive descriptor rings. 761 */ 762 int 763 gem_init(struct ifnet *ifp) 764 { 765 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 766 bus_space_tag_t t = sc->sc_bustag; 767 bus_space_handle_t h = sc->sc_h; 768 int s; 769 u_int max_frame_size; 770 u_int32_t v; 771 772 s = splnet(); 773 774 DPRINTF(sc, ("%s: gem_init: calling stop\n", sc->sc_dev.dv_xname)); 775 /* 776 * Initialization sequence. The numbered steps below correspond 777 * to the sequence outlined in section 6.3.5.1 in the Ethernet 778 * Channel Engine manual (part of the PCIO manual). 779 * See also the STP2002-STQ document from Sun Microsystems. 780 */ 781 782 /* step 1 & 2. Reset the Ethernet Channel */ 783 gem_stop(ifp, 0); 784 gem_reset(sc); 785 DPRINTF(sc, ("%s: gem_init: restarting\n", sc->sc_dev.dv_xname)); 786 787 /* Re-initialize the MIF */ 788 gem_mifinit(sc); 789 790 /* Call MI reset function if any */ 791 if (sc->sc_hwreset) 792 (*sc->sc_hwreset)(sc); 793 794 /* step 3. Setup data structures in host memory */ 795 gem_meminit(sc); 796 797 /* step 4. TX MAC registers & counters */ 798 gem_init_regs(sc); 799 max_frame_size = max(sc->sc_ethercom.ec_if.if_mtu, ETHERMTU); 800 max_frame_size += ETHER_HDR_LEN + ETHER_CRC_LEN; 801 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 802 max_frame_size += ETHER_VLAN_ENCAP_LEN; 803 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 804 max_frame_size|/* burst size */(0x2000<<16)); 805 806 /* step 5. RX MAC registers & counters */ 807 gem_setladrf(sc); 808 809 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 810 /* NOTE: we use only 32-bit DMA addresses here. */ 811 bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 0); 812 bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 813 814 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0); 815 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 816 817 /* step 8. Global Configuration & Interrupt Mask */ 818 bus_space_write_4(t, h, GEM_INTMASK, 819 ~(GEM_INTR_TX_INTME| 820 GEM_INTR_TX_EMPTY| 821 GEM_INTR_RX_DONE|GEM_INTR_RX_NOBUF| 822 GEM_INTR_RX_TAG_ERR|GEM_INTR_PCS| 823 GEM_INTR_MAC_CONTROL|GEM_INTR_MIF| 824 GEM_INTR_BERR)); 825 bus_space_write_4(t, h, GEM_MAC_RX_MASK, 826 GEM_MAC_RX_DONE|GEM_MAC_RX_FRAME_CNT); 827 bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXXX */ 828 bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 0); /* XXXX */ 829 830 /* step 9. ETX Configuration: use mostly default values */ 831 832 /* Enable DMA */ 833 v = gem_ringsize(GEM_NTXDESC /*XXX*/); 834 bus_space_write_4(t, h, GEM_TX_CONFIG, 835 v|GEM_TX_CONFIG_TXDMA_EN| 836 ((0x400<<10)&GEM_TX_CONFIG_TXFIFO_TH)); 837 bus_space_write_4(t, h, GEM_TX_KICK, sc->sc_txnext); 838 839 /* step 10. ERX Configuration */ 840 841 /* Encode Receive Descriptor ring size: four possible values */ 842 v = gem_ringsize(GEM_NRXDESC /*XXX*/); 843 844 /* Enable DMA */ 845 bus_space_write_4(t, h, GEM_RX_CONFIG, 846 v|(GEM_THRSH_1024<<GEM_RX_CONFIG_FIFO_THRS_SHIFT)| 847 (2<<GEM_RX_CONFIG_FBOFF_SHFT)|GEM_RX_CONFIG_RXDMA_EN| 848 (0<<GEM_RX_CONFIG_CXM_START_SHFT)); 849 /* 850 * The following value is for an OFF Threshold of about 3/4 full 851 * and an ON Threshold of 1/4 full. 852 */ 853 bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH, 854 (3 * sc->sc_rxfifosize / 256) | 855 ( (sc->sc_rxfifosize / 256) << 12)); 856 bus_space_write_4(t, h, GEM_RX_BLANKING, (6<<12)|6); 857 858 /* step 11. Configure Media */ 859 mii_mediachg(&sc->sc_mii); 860 861 /* XXXX Serial link needs a whole different setup. */ 862 863 864 /* step 12. RX_MAC Configuration Register */ 865 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 866 v |= GEM_MAC_RX_ENABLE; 867 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 868 869 /* step 14. Issue Transmit Pending command */ 870 871 /* Call MI initialization function if any */ 872 if (sc->sc_hwinit) 873 (*sc->sc_hwinit)(sc); 874 875 876 /* step 15. Give the reciever a swift kick */ 877 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4); 878 879 /* Start the one second timer. */ 880 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 881 882 ifp->if_flags |= IFF_RUNNING; 883 ifp->if_flags &= ~IFF_OACTIVE; 884 ifp->if_timer = 0; 885 splx(s); 886 887 return (0); 888 } 889 890 void 891 gem_init_regs(struct gem_softc *sc) 892 { 893 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 894 bus_space_tag_t t = sc->sc_bustag; 895 bus_space_handle_t h = sc->sc_h; 896 const u_char *laddr = LLADDR(ifp->if_sadl); 897 u_int32_t v; 898 899 /* These regs are not cleared on reset */ 900 if (!sc->sc_inited) { 901 902 /* Wooo. Magic values. */ 903 bus_space_write_4(t, h, GEM_MAC_IPG0, 0); 904 bus_space_write_4(t, h, GEM_MAC_IPG1, 8); 905 bus_space_write_4(t, h, GEM_MAC_IPG2, 4); 906 907 bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 908 /* Max frame and max burst size */ 909 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 910 ETHER_MAX_LEN | (0x2000<<16)); 911 912 bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x7); 913 bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x4); 914 bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10); 915 /* Dunno.... */ 916 bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088); 917 bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED, 918 ((laddr[5]<<8)|laddr[4])&0x3ff); 919 920 /* Secondary MAC addr set to 0:0:0:0:0:0 */ 921 bus_space_write_4(t, h, GEM_MAC_ADDR3, 0); 922 bus_space_write_4(t, h, GEM_MAC_ADDR4, 0); 923 bus_space_write_4(t, h, GEM_MAC_ADDR5, 0); 924 925 /* MAC control addr set to 01:80:c2:00:00:01 */ 926 bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001); 927 bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200); 928 bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180); 929 930 /* MAC filter addr set to 0:0:0:0:0:0 */ 931 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0); 932 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0); 933 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0); 934 935 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0); 936 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0); 937 938 sc->sc_inited = 1; 939 } 940 941 /* Counters need to be zeroed */ 942 bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0); 943 bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0); 944 bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0); 945 bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0); 946 bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0); 947 bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0); 948 bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0); 949 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 950 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 951 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 952 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 953 954 /* Un-pause stuff */ 955 #if 0 956 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); 957 #else 958 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0); 959 #endif 960 961 /* 962 * Set the station address. 963 */ 964 bus_space_write_4(t, h, GEM_MAC_ADDR0, (laddr[4]<<8)|laddr[5]); 965 bus_space_write_4(t, h, GEM_MAC_ADDR1, (laddr[2]<<8)|laddr[3]); 966 bus_space_write_4(t, h, GEM_MAC_ADDR2, (laddr[0]<<8)|laddr[1]); 967 968 #if 0 969 if (sc->sc_variant != APPLE_GMAC) 970 return; 971 #endif 972 973 /* 974 * Enable MII outputs. Enable GMII if there is a gigabit PHY. 975 */ 976 sc->sc_mif_config = bus_space_read_4(t, h, GEM_MIF_CONFIG); 977 v = GEM_MAC_XIF_TX_MII_ENA; 978 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) { 979 v |= GEM_MAC_XIF_FDPLX_LED; 980 if (sc->sc_flags & GEM_GIGABIT) 981 v |= GEM_MAC_XIF_GMII_MODE; 982 } 983 bus_space_write_4(t, h, GEM_MAC_XIF_CONFIG, v); 984 } 985 986 void 987 gem_start(ifp) 988 struct ifnet *ifp; 989 { 990 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 991 struct mbuf *m0, *m; 992 struct gem_txsoft *txs, *last_txs; 993 bus_dmamap_t dmamap; 994 int error, firsttx, nexttx, lasttx, ofree, seg; 995 996 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 997 return; 998 999 /* 1000 * Remember the previous number of free descriptors and 1001 * the first descriptor we'll use. 1002 */ 1003 ofree = sc->sc_txfree; 1004 firsttx = sc->sc_txnext; 1005 1006 DPRINTF(sc, ("%s: gem_start: txfree %d, txnext %d\n", 1007 sc->sc_dev.dv_xname, ofree, firsttx)); 1008 1009 /* 1010 * Loop through the send queue, setting up transmit descriptors 1011 * until we drain the queue, or use up all available transmit 1012 * descriptors. 1013 */ 1014 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 1015 sc->sc_txfree != 0) { 1016 /* 1017 * Grab a packet off the queue. 1018 */ 1019 IFQ_POLL(&ifp->if_snd, m0); 1020 if (m0 == NULL) 1021 break; 1022 m = NULL; 1023 1024 dmamap = txs->txs_dmamap; 1025 1026 /* 1027 * Load the DMA map. If this fails, the packet either 1028 * didn't fit in the alloted number of segments, or we were 1029 * short on resources. In this case, we'll copy and try 1030 * again. 1031 */ 1032 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m0, 1033 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1034 if (m0->m_pkthdr.len > MCLBYTES) { 1035 printf("%s: unable to allocate jumbo Tx " 1036 "cluster\n", sc->sc_dev.dv_xname); 1037 IFQ_DEQUEUE(&ifp->if_snd, m0); 1038 m_freem(m0); 1039 continue; 1040 } 1041 MGETHDR(m, M_DONTWAIT, MT_DATA); 1042 if (m == NULL) { 1043 printf("%s: unable to allocate Tx mbuf\n", 1044 sc->sc_dev.dv_xname); 1045 break; 1046 } 1047 if (m0->m_pkthdr.len > MHLEN) { 1048 MCLGET(m, M_DONTWAIT); 1049 if ((m->m_flags & M_EXT) == 0) { 1050 printf("%s: unable to allocate Tx " 1051 "cluster\n", sc->sc_dev.dv_xname); 1052 m_freem(m); 1053 break; 1054 } 1055 } 1056 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 1057 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1058 error = bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, 1059 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1060 if (error) { 1061 printf("%s: unable to load Tx buffer, " 1062 "error = %d\n", sc->sc_dev.dv_xname, error); 1063 break; 1064 } 1065 } 1066 1067 /* 1068 * Ensure we have enough descriptors free to describe 1069 * the packet. 1070 */ 1071 if (dmamap->dm_nsegs > sc->sc_txfree) { 1072 /* 1073 * Not enough free descriptors to transmit this 1074 * packet. We haven't committed to anything yet, 1075 * so just unload the DMA map, put the packet 1076 * back on the queue, and punt. Notify the upper 1077 * layer that there are no more slots left. 1078 * 1079 * XXX We could allocate an mbuf and copy, but 1080 * XXX it is worth it? 1081 */ 1082 ifp->if_flags |= IFF_OACTIVE; 1083 bus_dmamap_unload(sc->sc_dmatag, dmamap); 1084 if (m != NULL) 1085 m_freem(m); 1086 break; 1087 } 1088 1089 IFQ_DEQUEUE(&ifp->if_snd, m0); 1090 if (m != NULL) { 1091 m_freem(m0); 1092 m0 = m; 1093 } 1094 1095 /* 1096 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1097 */ 1098 1099 /* Sync the DMA map. */ 1100 bus_dmamap_sync(sc->sc_dmatag, dmamap, 0, dmamap->dm_mapsize, 1101 BUS_DMASYNC_PREWRITE); 1102 1103 /* 1104 * Initialize the transmit descriptors. 1105 */ 1106 for (nexttx = sc->sc_txnext, seg = 0; 1107 seg < dmamap->dm_nsegs; 1108 seg++, nexttx = GEM_NEXTTX(nexttx)) { 1109 uint64_t flags; 1110 1111 /* 1112 * If this is the first descriptor we're 1113 * enqueueing, set the start of packet flag, 1114 * and the checksum stuff if we want the hardware 1115 * to do it. 1116 */ 1117 sc->sc_txdescs[nexttx].gd_addr = 1118 GEM_DMA_WRITE(sc, dmamap->dm_segs[seg].ds_addr); 1119 flags = dmamap->dm_segs[seg].ds_len & GEM_TD_BUFSIZE; 1120 if (nexttx == firsttx) { 1121 flags |= GEM_TD_START_OF_PACKET; 1122 if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) { 1123 sc->sc_txwin = 0; 1124 flags |= GEM_TD_INTERRUPT_ME; 1125 } 1126 } 1127 if (seg == dmamap->dm_nsegs - 1) { 1128 flags |= GEM_TD_END_OF_PACKET; 1129 } 1130 sc->sc_txdescs[nexttx].gd_flags = 1131 GEM_DMA_WRITE(sc, flags); 1132 lasttx = nexttx; 1133 } 1134 1135 #ifdef GEM_DEBUG 1136 if (ifp->if_flags & IFF_DEBUG) { 1137 printf(" gem_start %p transmit chain:\n", txs); 1138 for (seg = sc->sc_txnext;; seg = GEM_NEXTTX(seg)) { 1139 printf("descriptor %d:\t", seg); 1140 printf("gd_flags: 0x%016llx\t", (long long) 1141 GEM_DMA_READ(sc, sc->sc_txdescs[seg].gd_flags)); 1142 printf("gd_addr: 0x%016llx\n", (long long) 1143 GEM_DMA_READ(sc, sc->sc_txdescs[seg].gd_addr)); 1144 if (seg == lasttx) 1145 break; 1146 } 1147 } 1148 #endif 1149 1150 /* Sync the descriptors we're using. */ 1151 GEM_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1152 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1153 1154 /* 1155 * Store a pointer to the packet so we can free it later, 1156 * and remember what txdirty will be once the packet is 1157 * done. 1158 */ 1159 txs->txs_mbuf = m0; 1160 txs->txs_firstdesc = sc->sc_txnext; 1161 txs->txs_lastdesc = lasttx; 1162 txs->txs_ndescs = dmamap->dm_nsegs; 1163 1164 /* Advance the tx pointer. */ 1165 sc->sc_txfree -= dmamap->dm_nsegs; 1166 sc->sc_txnext = nexttx; 1167 1168 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1169 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1170 1171 last_txs = txs; 1172 1173 #if NBPFILTER > 0 1174 /* 1175 * Pass the packet to any BPF listeners. 1176 */ 1177 if (ifp->if_bpf) 1178 bpf_mtap(ifp->if_bpf, m0); 1179 #endif /* NBPFILTER > 0 */ 1180 } 1181 1182 if (txs == NULL || sc->sc_txfree == 0) { 1183 /* No more slots left; notify upper layer. */ 1184 ifp->if_flags |= IFF_OACTIVE; 1185 } 1186 1187 if (sc->sc_txfree != ofree) { 1188 DPRINTF(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 1189 sc->sc_dev.dv_xname, lasttx, firsttx)); 1190 /* 1191 * The entire packet chain is set up. 1192 * Kick the transmitter. 1193 */ 1194 DPRINTF(sc, ("%s: gem_start: kicking tx %d\n", 1195 sc->sc_dev.dv_xname, nexttx)); 1196 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_TX_KICK, 1197 sc->sc_txnext); 1198 1199 /* Set a watchdog timer in case the chip flakes out. */ 1200 ifp->if_timer = 5; 1201 DPRINTF(sc, ("%s: gem_start: watchdog %d\n", 1202 sc->sc_dev.dv_xname, ifp->if_timer)); 1203 } 1204 } 1205 1206 /* 1207 * Transmit interrupt. 1208 */ 1209 int 1210 gem_tint(sc) 1211 struct gem_softc *sc; 1212 { 1213 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1214 bus_space_tag_t t = sc->sc_bustag; 1215 bus_space_handle_t mac = sc->sc_h; 1216 struct gem_txsoft *txs; 1217 int txlast; 1218 int progress = 0; 1219 1220 1221 DPRINTF(sc, ("%s: gem_tint\n", sc->sc_dev.dv_xname)); 1222 1223 /* 1224 * Unload collision counters 1225 */ 1226 ifp->if_collisions += 1227 bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) + 1228 bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT) + 1229 bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) + 1230 bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT); 1231 1232 /* 1233 * then clear the hardware counters. 1234 */ 1235 bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0); 1236 bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0); 1237 bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0); 1238 bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0); 1239 1240 /* 1241 * Go through our Tx list and free mbufs for those 1242 * frames that have been transmitted. 1243 */ 1244 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1245 GEM_CDTXSYNC(sc, txs->txs_lastdesc, 1246 txs->txs_ndescs, 1247 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1248 1249 #ifdef GEM_DEBUG 1250 if (ifp->if_flags & IFF_DEBUG) { 1251 int i; 1252 printf(" txsoft %p transmit chain:\n", txs); 1253 for (i = txs->txs_firstdesc;; i = GEM_NEXTTX(i)) { 1254 printf("descriptor %d: ", i); 1255 printf("gd_flags: 0x%016llx\t", (long long) 1256 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags)); 1257 printf("gd_addr: 0x%016llx\n", (long long) 1258 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr)); 1259 if (i == txs->txs_lastdesc) 1260 break; 1261 } 1262 } 1263 #endif 1264 1265 /* 1266 * In theory, we could harveast some descriptors before 1267 * the ring is empty, but that's a bit complicated. 1268 * 1269 * GEM_TX_COMPLETION points to the last descriptor 1270 * processed +1. 1271 */ 1272 txlast = bus_space_read_4(t, mac, GEM_TX_COMPLETION); 1273 DPRINTF(sc, 1274 ("gem_tint: txs->txs_lastdesc = %d, txlast = %d\n", 1275 txs->txs_lastdesc, txlast)); 1276 if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1277 if ((txlast >= txs->txs_firstdesc) && 1278 (txlast <= txs->txs_lastdesc)) 1279 break; 1280 } else { 1281 /* Ick -- this command wraps */ 1282 if ((txlast >= txs->txs_firstdesc) || 1283 (txlast <= txs->txs_lastdesc)) 1284 break; 1285 } 1286 1287 DPRINTF(sc, ("gem_tint: releasing a desc\n")); 1288 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1289 1290 sc->sc_txfree += txs->txs_ndescs; 1291 1292 if (txs->txs_mbuf == NULL) { 1293 #ifdef DIAGNOSTIC 1294 panic("gem_txintr: null mbuf"); 1295 #endif 1296 } 1297 1298 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 1299 0, txs->txs_dmamap->dm_mapsize, 1300 BUS_DMASYNC_POSTWRITE); 1301 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 1302 m_freem(txs->txs_mbuf); 1303 txs->txs_mbuf = NULL; 1304 1305 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1306 1307 ifp->if_opackets++; 1308 progress = 1; 1309 } 1310 1311 DPRINTF(sc, ("gem_tint: GEM_TX_STATE_MACHINE %x " 1312 "GEM_TX_DATA_PTR %llx " 1313 "GEM_TX_COMPLETION %x\n", 1314 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_STATE_MACHINE), 1315 ((long long) bus_space_read_4(sc->sc_bustag, sc->sc_h, 1316 GEM_TX_DATA_PTR_HI) << 32) | 1317 bus_space_read_4(sc->sc_bustag, sc->sc_h, 1318 GEM_TX_DATA_PTR_LO), 1319 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_COMPLETION))); 1320 1321 if (progress) { 1322 if (sc->sc_txfree == GEM_NTXDESC - 1) 1323 sc->sc_txwin = 0; 1324 1325 ifp->if_flags &= ~IFF_OACTIVE; 1326 gem_start(ifp); 1327 1328 if (SIMPLEQ_EMPTY(&sc->sc_txdirtyq)) 1329 ifp->if_timer = 0; 1330 } 1331 DPRINTF(sc, ("%s: gem_tint: watchdog %d\n", 1332 sc->sc_dev.dv_xname, ifp->if_timer)); 1333 1334 return (1); 1335 } 1336 1337 /* 1338 * Receive interrupt. 1339 */ 1340 int 1341 gem_rint(sc) 1342 struct gem_softc *sc; 1343 { 1344 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1345 bus_space_tag_t t = sc->sc_bustag; 1346 bus_space_handle_t h = sc->sc_h; 1347 struct ether_header *eh; 1348 struct gem_rxsoft *rxs; 1349 struct mbuf *m; 1350 u_int64_t rxstat; 1351 u_int32_t rxcomp; 1352 int i, len, progress = 0; 1353 1354 DPRINTF(sc, ("%s: gem_rint\n", sc->sc_dev.dv_xname)); 1355 1356 /* 1357 * Read the completion register once. This limits 1358 * how long the following loop can execute. 1359 */ 1360 rxcomp = bus_space_read_4(t, h, GEM_RX_COMPLETION); 1361 1362 /* 1363 * XXXX Read the lastrx only once at the top for speed. 1364 */ 1365 DPRINTF(sc, ("gem_rint: sc->rxptr %d, complete %d\n", 1366 sc->sc_rxptr, rxcomp)); 1367 1368 /* 1369 * Go into the loop at least once. 1370 */ 1371 for (i = sc->sc_rxptr; i == sc->sc_rxptr || i != rxcomp; 1372 i = GEM_NEXTRX(i)) { 1373 rxs = &sc->sc_rxsoft[i]; 1374 1375 GEM_CDRXSYNC(sc, i, 1376 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1377 1378 rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags); 1379 1380 if (rxstat & GEM_RD_OWN) { 1381 /* 1382 * We have processed all of the receive buffers. 1383 */ 1384 break; 1385 } 1386 1387 progress++; 1388 ifp->if_ipackets++; 1389 1390 if (rxstat & GEM_RD_BAD_CRC) { 1391 ifp->if_ierrors++; 1392 printf("%s: receive error: CRC error\n", 1393 sc->sc_dev.dv_xname); 1394 GEM_INIT_RXDESC(sc, i); 1395 continue; 1396 } 1397 1398 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1399 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1400 #ifdef GEM_DEBUG 1401 if (ifp->if_flags & IFF_DEBUG) { 1402 printf(" rxsoft %p descriptor %d: ", rxs, i); 1403 printf("gd_flags: 0x%016llx\t", (long long) 1404 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags)); 1405 printf("gd_addr: 0x%016llx\n", (long long) 1406 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr)); 1407 } 1408 #endif 1409 1410 /* 1411 * No errors; receive the packet. Note the Gem 1412 * includes the CRC with every packet. 1413 */ 1414 len = GEM_RD_BUFLEN(rxstat); 1415 1416 /* 1417 * Allocate a new mbuf cluster. If that fails, we are 1418 * out of memory, and must drop the packet and recycle 1419 * the buffer that's already attached to this descriptor. 1420 */ 1421 m = rxs->rxs_mbuf; 1422 if (gem_add_rxbuf(sc, i) != 0) { 1423 GEM_COUNTER_INCR(sc, sc_ev_rxnobuf); 1424 ifp->if_ierrors++; 1425 GEM_INIT_RXDESC(sc, i); 1426 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1427 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1428 continue; 1429 } 1430 m->m_data += 2; /* We're already off by two */ 1431 1432 eh = mtod(m, struct ether_header *); 1433 m->m_flags |= M_HASFCS; 1434 m->m_pkthdr.rcvif = ifp; 1435 m->m_pkthdr.len = m->m_len = len; 1436 1437 #if NBPFILTER > 0 1438 /* 1439 * Pass this up to any BPF listeners, but only 1440 * pass it up the stack if its for us. 1441 */ 1442 if (ifp->if_bpf) 1443 bpf_mtap(ifp->if_bpf, m); 1444 #endif /* NPBFILTER > 0 */ 1445 1446 /* Pass it on. */ 1447 (*ifp->if_input)(ifp, m); 1448 } 1449 1450 if (progress) { 1451 /* Update the receive pointer. */ 1452 if (i == sc->sc_rxptr) { 1453 GEM_COUNTER_INCR(sc, sc_ev_rxfull); 1454 #ifdef GEM_DEBUG 1455 if (ifp->if_flags & GEM_DEBUG) 1456 printf("%s: rint: ring wrap\n", 1457 sc->sc_dev.dv_xname); 1458 #endif 1459 } 1460 sc->sc_rxptr = i; 1461 bus_space_write_4(t, h, GEM_RX_KICK, GEM_PREVRX(i)); 1462 } 1463 #ifdef GEM_COUNTERS 1464 if (progress <= 4) { 1465 GEM_COUNTER_INCR(sc, sc_ev_rxhist[progress]); 1466 } else if (progress > 31) { 1467 if (progress < 16) 1468 GEM_COUNTER_INCR(sc, sc_ev_rxhist[5]); 1469 else 1470 GEM_COUNTER_INCR(sc, sc_ev_rxhist[6]); 1471 1472 } else { 1473 if (progress < 64) 1474 GEM_COUNTER_INCR(sc, sc_ev_rxhist[7]); 1475 else 1476 GEM_COUNTER_INCR(sc, sc_ev_rxhist[8]); 1477 } 1478 #endif 1479 1480 DPRINTF(sc, ("gem_rint: done sc->rxptr %d, complete %d\n", 1481 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION))); 1482 1483 return (1); 1484 } 1485 1486 1487 /* 1488 * gem_add_rxbuf: 1489 * 1490 * Add a receive buffer to the indicated descriptor. 1491 */ 1492 int 1493 gem_add_rxbuf(struct gem_softc *sc, int idx) 1494 { 1495 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1496 struct mbuf *m; 1497 int error; 1498 1499 MGETHDR(m, M_DONTWAIT, MT_DATA); 1500 if (m == NULL) 1501 return (ENOBUFS); 1502 1503 MCLGET(m, M_DONTWAIT); 1504 if ((m->m_flags & M_EXT) == 0) { 1505 m_freem(m); 1506 return (ENOBUFS); 1507 } 1508 1509 #ifdef GEM_DEBUG 1510 /* bzero the packet to check dma */ 1511 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 1512 #endif 1513 1514 if (rxs->rxs_mbuf != NULL) 1515 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 1516 1517 rxs->rxs_mbuf = m; 1518 1519 error = bus_dmamap_load(sc->sc_dmatag, rxs->rxs_dmamap, 1520 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1521 BUS_DMA_READ|BUS_DMA_NOWAIT); 1522 if (error) { 1523 printf("%s: can't load rx DMA map %d, error = %d\n", 1524 sc->sc_dev.dv_xname, idx, error); 1525 panic("gem_add_rxbuf"); /* XXX */ 1526 } 1527 1528 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1529 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1530 1531 GEM_INIT_RXDESC(sc, idx); 1532 1533 return (0); 1534 } 1535 1536 1537 int 1538 gem_eint(sc, status) 1539 struct gem_softc *sc; 1540 u_int status; 1541 { 1542 char bits[128]; 1543 1544 if ((status & GEM_INTR_MIF) != 0) { 1545 printf("%s: XXXlink status changed\n", sc->sc_dev.dv_xname); 1546 return (1); 1547 } 1548 1549 printf("%s: status=%s\n", sc->sc_dev.dv_xname, 1550 bitmask_snprintf(status, GEM_INTR_BITS, bits, sizeof(bits))); 1551 return (1); 1552 } 1553 1554 1555 int 1556 gem_intr(v) 1557 void *v; 1558 { 1559 struct gem_softc *sc = (struct gem_softc *)v; 1560 bus_space_tag_t t = sc->sc_bustag; 1561 bus_space_handle_t seb = sc->sc_h; 1562 u_int32_t status; 1563 int r = 0; 1564 #ifdef GEM_DEBUG 1565 char bits[128]; 1566 #endif 1567 1568 sc->sc_ev_intr.ev_count++; 1569 1570 status = bus_space_read_4(t, seb, GEM_STATUS); 1571 DPRINTF(sc, ("%s: gem_intr: cplt %xstatus %s\n", 1572 sc->sc_dev.dv_xname, (status>>19), 1573 bitmask_snprintf(status, GEM_INTR_BITS, bits, sizeof(bits)))); 1574 1575 if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0) 1576 r |= gem_eint(sc, status); 1577 1578 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) { 1579 GEM_COUNTER_INCR(sc, sc_ev_txint); 1580 r |= gem_tint(sc); 1581 } 1582 1583 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) { 1584 GEM_COUNTER_INCR(sc, sc_ev_rxint); 1585 r |= gem_rint(sc); 1586 } 1587 1588 /* We should eventually do more than just print out error stats. */ 1589 if (status & GEM_INTR_TX_MAC) { 1590 int txstat = bus_space_read_4(t, seb, GEM_MAC_TX_STATUS); 1591 if (txstat & ~GEM_MAC_TX_XMIT_DONE) 1592 printf("%s: MAC tx fault, status %x\n", 1593 sc->sc_dev.dv_xname, txstat); 1594 } 1595 if (status & GEM_INTR_RX_MAC) { 1596 int rxstat = bus_space_read_4(t, seb, GEM_MAC_RX_STATUS); 1597 if (rxstat & ~GEM_MAC_RX_DONE) 1598 printf("%s: MAC rx fault, status %x\n", 1599 sc->sc_dev.dv_xname, rxstat); 1600 } 1601 return (r); 1602 } 1603 1604 1605 void 1606 gem_watchdog(ifp) 1607 struct ifnet *ifp; 1608 { 1609 struct gem_softc *sc = ifp->if_softc; 1610 1611 DPRINTF(sc, ("gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x " 1612 "GEM_MAC_RX_CONFIG %x\n", 1613 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_CONFIG), 1614 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_STATUS), 1615 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_CONFIG))); 1616 1617 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1618 ++ifp->if_oerrors; 1619 1620 /* Try to get more packets going. */ 1621 gem_start(ifp); 1622 } 1623 1624 /* 1625 * Initialize the MII Management Interface 1626 */ 1627 void 1628 gem_mifinit(sc) 1629 struct gem_softc *sc; 1630 { 1631 bus_space_tag_t t = sc->sc_bustag; 1632 bus_space_handle_t mif = sc->sc_h; 1633 1634 /* Configure the MIF in frame mode */ 1635 sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1636 sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA; 1637 bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config); 1638 } 1639 1640 /* 1641 * MII interface 1642 * 1643 * The GEM MII interface supports at least three different operating modes: 1644 * 1645 * Bitbang mode is implemented using data, clock and output enable registers. 1646 * 1647 * Frame mode is implemented by loading a complete frame into the frame 1648 * register and polling the valid bit for completion. 1649 * 1650 * Polling mode uses the frame register but completion is indicated by 1651 * an interrupt. 1652 * 1653 */ 1654 static int 1655 gem_mii_readreg(self, phy, reg) 1656 struct device *self; 1657 int phy, reg; 1658 { 1659 struct gem_softc *sc = (void *)self; 1660 bus_space_tag_t t = sc->sc_bustag; 1661 bus_space_handle_t mif = sc->sc_h; 1662 int n; 1663 u_int32_t v; 1664 1665 #ifdef GEM_DEBUG1 1666 if (sc->sc_debug) 1667 printf("gem_mii_readreg: phy %d reg %d\n", phy, reg); 1668 #endif 1669 1670 #if 0 1671 /* Select the desired PHY in the MIF configuration register */ 1672 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1673 /* Clear PHY select bit */ 1674 v &= ~GEM_MIF_CONFIG_PHY_SEL; 1675 if (phy == GEM_PHYAD_EXTERNAL) 1676 /* Set PHY select bit to get at external device */ 1677 v |= GEM_MIF_CONFIG_PHY_SEL; 1678 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 1679 #endif 1680 1681 /* Construct the frame command */ 1682 v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) | 1683 GEM_MIF_FRAME_READ; 1684 1685 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1686 for (n = 0; n < 100; n++) { 1687 DELAY(1); 1688 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1689 if (v & GEM_MIF_FRAME_TA0) 1690 return (v & GEM_MIF_FRAME_DATA); 1691 } 1692 1693 printf("%s: mii_read timeout\n", sc->sc_dev.dv_xname); 1694 return (0); 1695 } 1696 1697 static void 1698 gem_mii_writereg(self, phy, reg, val) 1699 struct device *self; 1700 int phy, reg, val; 1701 { 1702 struct gem_softc *sc = (void *)self; 1703 bus_space_tag_t t = sc->sc_bustag; 1704 bus_space_handle_t mif = sc->sc_h; 1705 int n; 1706 u_int32_t v; 1707 1708 #ifdef GEM_DEBUG1 1709 if (sc->sc_debug) 1710 printf("gem_mii_writereg: phy %d reg %d val %x\n", 1711 phy, reg, val); 1712 #endif 1713 1714 #if 0 1715 /* Select the desired PHY in the MIF configuration register */ 1716 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1717 /* Clear PHY select bit */ 1718 v &= ~GEM_MIF_CONFIG_PHY_SEL; 1719 if (phy == GEM_PHYAD_EXTERNAL) 1720 /* Set PHY select bit to get at external device */ 1721 v |= GEM_MIF_CONFIG_PHY_SEL; 1722 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 1723 #endif 1724 /* Construct the frame command */ 1725 v = GEM_MIF_FRAME_WRITE | 1726 (phy << GEM_MIF_PHY_SHIFT) | 1727 (reg << GEM_MIF_REG_SHIFT) | 1728 (val & GEM_MIF_FRAME_DATA); 1729 1730 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1731 for (n = 0; n < 100; n++) { 1732 DELAY(1); 1733 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1734 if (v & GEM_MIF_FRAME_TA0) 1735 return; 1736 } 1737 1738 printf("%s: mii_write timeout\n", sc->sc_dev.dv_xname); 1739 } 1740 1741 static void 1742 gem_mii_statchg(dev) 1743 struct device *dev; 1744 { 1745 struct gem_softc *sc = (void *)dev; 1746 #ifdef GEM_DEBUG 1747 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1748 #endif 1749 bus_space_tag_t t = sc->sc_bustag; 1750 bus_space_handle_t mac = sc->sc_h; 1751 u_int32_t v; 1752 1753 #ifdef GEM_DEBUG 1754 if (sc->sc_debug) 1755 printf("gem_mii_statchg: status change: phy = %d\n", 1756 sc->sc_phys[instance];); 1757 #endif 1758 1759 1760 /* Set tx full duplex options */ 1761 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0); 1762 delay(10000); /* reg must be cleared and delay before changing. */ 1763 v = GEM_MAC_TX_ENA_IPG0|GEM_MAC_TX_NGU|GEM_MAC_TX_NGU_LIMIT| 1764 GEM_MAC_TX_ENABLE; 1765 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) { 1766 v |= GEM_MAC_TX_IGN_CARRIER|GEM_MAC_TX_IGN_COLLIS; 1767 } 1768 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, v); 1769 1770 /* XIF Configuration */ 1771 /* We should really calculate all this rather than rely on defaults */ 1772 v = bus_space_read_4(t, mac, GEM_MAC_XIF_CONFIG); 1773 v = GEM_MAC_XIF_LINK_LED; 1774 v |= GEM_MAC_XIF_TX_MII_ENA; 1775 1776 /* If an external transceiver is connected, enable its MII drivers */ 1777 sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG); 1778 if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) { 1779 /* External MII needs echo disable if half duplex. */ 1780 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1781 /* turn on full duplex LED */ 1782 v |= GEM_MAC_XIF_FDPLX_LED; 1783 else 1784 /* half duplex -- disable echo */ 1785 v |= GEM_MAC_XIF_ECHO_DISABL; 1786 1787 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 1788 v |= GEM_MAC_XIF_GMII_MODE; 1789 else 1790 v &= ~GEM_MAC_XIF_GMII_MODE; 1791 } else 1792 /* Internal MII needs buf enable */ 1793 v |= GEM_MAC_XIF_MII_BUF_ENA; 1794 bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v); 1795 } 1796 1797 int 1798 gem_mediachange(ifp) 1799 struct ifnet *ifp; 1800 { 1801 struct gem_softc *sc = ifp->if_softc; 1802 1803 if (IFM_TYPE(sc->sc_media.ifm_media) != IFM_ETHER) 1804 return (EINVAL); 1805 1806 return (mii_mediachg(&sc->sc_mii)); 1807 } 1808 1809 void 1810 gem_mediastatus(ifp, ifmr) 1811 struct ifnet *ifp; 1812 struct ifmediareq *ifmr; 1813 { 1814 struct gem_softc *sc = ifp->if_softc; 1815 1816 if ((ifp->if_flags & IFF_UP) == 0) 1817 return; 1818 1819 mii_pollstat(&sc->sc_mii); 1820 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1821 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1822 } 1823 1824 int gem_ioctldebug = 0; 1825 /* 1826 * Process an ioctl request. 1827 */ 1828 int 1829 gem_ioctl(ifp, cmd, data) 1830 struct ifnet *ifp; 1831 u_long cmd; 1832 caddr_t data; 1833 { 1834 struct gem_softc *sc = ifp->if_softc; 1835 struct ifreq *ifr = (struct ifreq *)data; 1836 int s, error = 0; 1837 1838 s = splnet(); 1839 1840 switch (cmd) { 1841 case SIOCGIFMEDIA: 1842 case SIOCSIFMEDIA: 1843 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1844 break; 1845 1846 default: 1847 error = ether_ioctl(ifp, cmd, data); 1848 if (error == ENETRESET) { 1849 /* 1850 * Multicast list has changed; set the hardware filter 1851 * accordingly. 1852 */ 1853 if (gem_ioctldebug) printf("reset1\n"); 1854 gem_init(ifp); 1855 delay(50000); 1856 error = 0; 1857 } 1858 break; 1859 } 1860 1861 /* Try to get things going again */ 1862 if (ifp->if_flags & IFF_UP) { 1863 if (gem_ioctldebug) printf("start\n"); 1864 gem_start(ifp); 1865 } 1866 splx(s); 1867 return (error); 1868 } 1869 1870 1871 void 1872 gem_shutdown(arg) 1873 void *arg; 1874 { 1875 struct gem_softc *sc = (struct gem_softc *)arg; 1876 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1877 1878 gem_stop(ifp, 1); 1879 } 1880 1881 /* 1882 * Set up the logical address filter. 1883 */ 1884 void 1885 gem_setladrf(sc) 1886 struct gem_softc *sc; 1887 { 1888 struct ethercom *ec = &sc->sc_ethercom; 1889 struct ifnet *ifp = &ec->ec_if; 1890 struct ether_multi *enm; 1891 struct ether_multistep step; 1892 bus_space_tag_t t = sc->sc_bustag; 1893 bus_space_handle_t h = sc->sc_h; 1894 u_int32_t crc; 1895 u_int32_t hash[16]; 1896 u_int32_t v; 1897 int i; 1898 1899 /* Get current RX configuration */ 1900 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 1901 1902 /* 1903 * Turn off promiscuous mode, promiscuous group mode (all multicast), 1904 * and hash filter. Depending on the case, the right bit will be 1905 * enabled. 1906 */ 1907 v &= ~(GEM_MAC_RX_PROMISCUOUS|GEM_MAC_RX_HASH_FILTER| 1908 GEM_MAC_RX_PROMISC_GRP); 1909 1910 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1911 /* Turn on promiscuous mode */ 1912 v |= GEM_MAC_RX_PROMISCUOUS; 1913 ifp->if_flags |= IFF_ALLMULTI; 1914 goto chipit; 1915 } 1916 1917 /* 1918 * Set up multicast address filter by passing all multicast addresses 1919 * through a crc generator, and then using the high order 8 bits as an 1920 * index into the 256 bit logical address filter. The high order 4 1921 * bits select the word, while the other 4 bits select the bit within 1922 * the word (where bit 0 is the MSB). 1923 */ 1924 1925 /* Clear hash table */ 1926 memset(hash, 0, sizeof(hash)); 1927 1928 ETHER_FIRST_MULTI(step, ec, enm); 1929 while (enm != NULL) { 1930 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1931 /* 1932 * We must listen to a range of multicast addresses. 1933 * For now, just accept all multicasts, rather than 1934 * trying to set only those filter bits needed to match 1935 * the range. (At this time, the only use of address 1936 * ranges is for IP multicast routing, for which the 1937 * range is big enough to require all bits set.) 1938 * XXX use the addr filter for this 1939 */ 1940 ifp->if_flags |= IFF_ALLMULTI; 1941 v |= GEM_MAC_RX_PROMISC_GRP; 1942 goto chipit; 1943 } 1944 1945 /* Get the LE CRC32 of the address */ 1946 crc = ether_crc32_le(enm->enm_addrlo, sizeof(enm->enm_addrlo)); 1947 1948 /* Just want the 8 most significant bits. */ 1949 crc >>= 24; 1950 1951 /* Set the corresponding bit in the filter. */ 1952 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 1953 1954 ETHER_NEXT_MULTI(step, enm); 1955 } 1956 1957 v |= GEM_MAC_RX_HASH_FILTER; 1958 ifp->if_flags &= ~IFF_ALLMULTI; 1959 1960 /* Now load the hash table into the chip (if we are using it) */ 1961 for (i = 0; i < 16; i++) { 1962 bus_space_write_4(t, h, 1963 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1-GEM_MAC_HASH0), 1964 hash[i]); 1965 } 1966 1967 chipit: 1968 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 1969 } 1970 1971 #if notyet 1972 1973 /* 1974 * gem_power: 1975 * 1976 * Power management (suspend/resume) hook. 1977 */ 1978 void 1979 gem_power(why, arg) 1980 int why; 1981 void *arg; 1982 { 1983 struct gem_softc *sc = arg; 1984 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1985 int s; 1986 1987 s = splnet(); 1988 switch (why) { 1989 case PWR_SUSPEND: 1990 case PWR_STANDBY: 1991 gem_stop(ifp, 1); 1992 if (sc->sc_power != NULL) 1993 (*sc->sc_power)(sc, why); 1994 break; 1995 case PWR_RESUME: 1996 if (ifp->if_flags & IFF_UP) { 1997 if (sc->sc_power != NULL) 1998 (*sc->sc_power)(sc, why); 1999 gem_init(ifp); 2000 } 2001 break; 2002 case PWR_SOFTSUSPEND: 2003 case PWR_SOFTSTANDBY: 2004 case PWR_SOFTRESUME: 2005 break; 2006 } 2007 splx(s); 2008 } 2009 #endif 2010
Indexes created Tue Sep 23 02:09:52 GMT 2025