gem.c revision 1.25
1 /* $NetBSD: gem.c,v 1.25 2003/02/20 00:55:21 matt Exp $ */ 2 3 /* 4 * 5 * Copyright (C) 2001 Eduardo Horvath. 6 * All rights reserved. 7 * 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 */ 31 32 /* 33 * Driver for Sun GEM ethernet controllers. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: gem.c,v 1.25 2003/02/20 00:55:21 matt Exp $"); 38 39 #include "bpfilter.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/callout.h> 44 #include <sys/mbuf.h> 45 #include <sys/syslog.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #include <sys/socket.h> 49 #include <sys/ioctl.h> 50 #include <sys/errno.h> 51 #include <sys/device.h> 52 53 #include <machine/endian.h> 54 55 #include <uvm/uvm_extern.h> 56 57 #include <net/if.h> 58 #include <net/if_dl.h> 59 #include <net/if_media.h> 60 #include <net/if_ether.h> 61 62 #if NBPFILTER > 0 63 #include <net/bpf.h> 64 #endif 65 66 #include <machine/bus.h> 67 #include <machine/intr.h> 68 69 #include <dev/mii/mii.h> 70 #include <dev/mii/miivar.h> 71 #include <dev/mii/mii_bitbang.h> 72 73 #include <dev/ic/gemreg.h> 74 #include <dev/ic/gemvar.h> 75 76 #define TRIES 10000 77 78 void gem_start __P((struct ifnet *)); 79 void gem_stop __P((struct ifnet *, int)); 80 int gem_ioctl __P((struct ifnet *, u_long, caddr_t)); 81 void gem_tick __P((void *)); 82 void gem_watchdog __P((struct ifnet *)); 83 void gem_shutdown __P((void *)); 84 int gem_init __P((struct ifnet *)); 85 void gem_init_regs(struct gem_softc *sc); 86 static int gem_ringsize(int sz); 87 int gem_meminit __P((struct gem_softc *)); 88 void gem_mifinit __P((struct gem_softc *)); 89 void gem_reset __P((struct gem_softc *)); 90 int gem_reset_rx(struct gem_softc *sc); 91 int gem_reset_tx(struct gem_softc *sc); 92 int gem_disable_rx(struct gem_softc *sc); 93 int gem_disable_tx(struct gem_softc *sc); 94 void gem_rxdrain(struct gem_softc *sc); 95 int gem_add_rxbuf(struct gem_softc *sc, int idx); 96 void gem_setladrf __P((struct gem_softc *)); 97 98 /* MII methods & callbacks */ 99 static int gem_mii_readreg __P((struct device *, int, int)); 100 static void gem_mii_writereg __P((struct device *, int, int, int)); 101 static void gem_mii_statchg __P((struct device *)); 102 103 int gem_mediachange __P((struct ifnet *)); 104 void gem_mediastatus __P((struct ifnet *, struct ifmediareq *)); 105 106 struct mbuf *gem_get __P((struct gem_softc *, int, int)); 107 int gem_put __P((struct gem_softc *, int, struct mbuf *)); 108 void gem_read __P((struct gem_softc *, int, int)); 109 int gem_eint __P((struct gem_softc *, u_int)); 110 int gem_rint __P((struct gem_softc *)); 111 int gem_tint __P((struct gem_softc *)); 112 void gem_power __P((int, void *)); 113 114 #ifdef GEM_DEBUG 115 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 116 printf x 117 #else 118 #define DPRINTF(sc, x) /* nothing */ 119 #endif 120 121 122 /* 123 * gem_attach: 124 * 125 * Attach a Gem interface to the system. 126 */ 127 void 128 gem_attach(sc, enaddr) 129 struct gem_softc *sc; 130 const uint8_t *enaddr; 131 { 132 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 133 struct mii_data *mii = &sc->sc_mii; 134 struct mii_softc *child; 135 struct ifmedia_entry *ifm; 136 int i, error; 137 u_int32_t v; 138 139 /* Make sure the chip is stopped. */ 140 ifp->if_softc = sc; 141 gem_reset(sc); 142 143 /* 144 * Allocate the control data structures, and create and load the 145 * DMA map for it. 146 */ 147 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 148 sizeof(struct gem_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 149 1, &sc->sc_cdnseg, 0)) != 0) { 150 aprint_error( 151 "%s: unable to allocate control data, error = %d\n", 152 sc->sc_dev.dv_xname, error); 153 goto fail_0; 154 } 155 156 /* XXX should map this in with correct endianness */ 157 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg, 158 sizeof(struct gem_control_data), (caddr_t *)&sc->sc_control_data, 159 BUS_DMA_COHERENT)) != 0) { 160 aprint_error("%s: unable to map control data, error = %d\n", 161 sc->sc_dev.dv_xname, error); 162 goto fail_1; 163 } 164 165 if ((error = bus_dmamap_create(sc->sc_dmatag, 166 sizeof(struct gem_control_data), 1, 167 sizeof(struct gem_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 168 aprint_error("%s: unable to create control data DMA map, " 169 "error = %d\n", sc->sc_dev.dv_xname, error); 170 goto fail_2; 171 } 172 173 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 174 sc->sc_control_data, sizeof(struct gem_control_data), NULL, 175 0)) != 0) { 176 aprint_error( 177 "%s: unable to load control data DMA map, error = %d\n", 178 sc->sc_dev.dv_xname, error); 179 goto fail_3; 180 } 181 182 /* 183 * Initialize the transmit job descriptors. 184 */ 185 SIMPLEQ_INIT(&sc->sc_txfreeq); 186 SIMPLEQ_INIT(&sc->sc_txdirtyq); 187 188 /* 189 * Create the transmit buffer DMA maps. 190 */ 191 for (i = 0; i < GEM_TXQUEUELEN; i++) { 192 struct gem_txsoft *txs; 193 194 txs = &sc->sc_txsoft[i]; 195 txs->txs_mbuf = NULL; 196 if ((error = bus_dmamap_create(sc->sc_dmatag, 197 ETHER_MAX_LEN_JUMBO, GEM_NTXSEGS, 198 ETHER_MAX_LEN_JUMBO, 0, 0, 199 &txs->txs_dmamap)) != 0) { 200 aprint_error("%s: unable to create tx DMA map %d, " 201 "error = %d\n", sc->sc_dev.dv_xname, i, error); 202 goto fail_4; 203 } 204 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 205 } 206 207 /* 208 * Create the receive buffer DMA maps. 209 */ 210 for (i = 0; i < GEM_NRXDESC; i++) { 211 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, 212 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 213 aprint_error("%s: unable to create rx DMA map %d, " 214 "error = %d\n", sc->sc_dev.dv_xname, i, error); 215 goto fail_5; 216 } 217 sc->sc_rxsoft[i].rxs_mbuf = NULL; 218 } 219 220 /* 221 * From this point forward, the attachment cannot fail. A failure 222 * before this point releases all resources that may have been 223 * allocated. 224 */ 225 226 /* Announce ourselves. */ 227 aprint_normal("%s: Ethernet address %s", sc->sc_dev.dv_xname, 228 ether_sprintf(enaddr)); 229 230 /* Get RX FIFO size */ 231 sc->sc_rxfifosize = 64 * 232 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_FIFO_SIZE); 233 aprint_normal(", %uKB RX fifo", sc->sc_rxfifosize / 1024); 234 235 /* Get TX FIFO size */ 236 v = bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_FIFO_SIZE); 237 aprint_normal(", %uKB TX fifo\n", v / 16); 238 239 /* Initialize ifnet structure. */ 240 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 241 ifp->if_softc = sc; 242 ifp->if_flags = 243 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 244 ifp->if_start = gem_start; 245 ifp->if_ioctl = gem_ioctl; 246 ifp->if_watchdog = gem_watchdog; 247 ifp->if_stop = gem_stop; 248 ifp->if_init = gem_init; 249 IFQ_SET_READY(&ifp->if_snd); 250 251 /* Initialize ifmedia structures and MII info */ 252 mii->mii_ifp = ifp; 253 mii->mii_readreg = gem_mii_readreg; 254 mii->mii_writereg = gem_mii_writereg; 255 mii->mii_statchg = gem_mii_statchg; 256 257 ifmedia_init(&mii->mii_media, IFM_IMASK, gem_mediachange, gem_mediastatus); 258 259 gem_mifinit(sc); 260 261 mii_attach(&sc->sc_dev, mii, 0xffffffff, 262 MII_PHY_ANY, MII_OFFSET_ANY, MIIF_FORCEANEG); 263 264 child = LIST_FIRST(&mii->mii_phys); 265 if (child == NULL) { 266 /* No PHY attached */ 267 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 268 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 269 } else { 270 /* 271 * Walk along the list of attached MII devices and 272 * establish an `MII instance' to `phy number' 273 * mapping. We'll use this mapping in media change 274 * requests to determine which phy to use to program 275 * the MIF configuration register. 276 */ 277 for (; child != NULL; child = LIST_NEXT(child, mii_list)) { 278 /* 279 * Note: we support just two PHYs: the built-in 280 * internal device and an external on the MII 281 * connector. 282 */ 283 if (child->mii_phy > 1 || child->mii_inst > 1) { 284 aprint_error( 285 "%s: cannot accomodate MII device %s" 286 " at phy %d, instance %d\n", 287 sc->sc_dev.dv_xname, 288 child->mii_dev.dv_xname, 289 child->mii_phy, child->mii_inst); 290 continue; 291 } 292 293 sc->sc_phys[child->mii_inst] = child->mii_phy; 294 295 } 296 297 /* 298 * Now select and activate the PHY we will use. 299 * 300 * The order of preference is External (MDI1), 301 * Internal (MDI0), Serial Link (no MII). 302 */ 303 if (sc->sc_phys[1]) { 304 #ifdef DEBUG 305 aprint_debug("using external phy\n"); 306 #endif 307 sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL; 308 } else { 309 #ifdef DEBUG 310 aprint_debug("using internal phy\n"); 311 #endif 312 sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL; 313 } 314 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_MIF_CONFIG, 315 sc->sc_mif_config); 316 317 /* 318 * XXX - we can really do the following ONLY if the 319 * phy indeed has the auto negotiation capability!! 320 */ 321 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO); 322 } 323 324 /* 325 * If we support GigE media, we support jumbo frames too. 326 * Unless we are Apple. 327 */ 328 TAILQ_FOREACH(ifm, &sc->sc_media.ifm_list, ifm_list) { 329 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_T || 330 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_SX || 331 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_LX || 332 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_CX) { 333 if (sc->sc_variant != GEM_APPLE_GMAC) 334 sc->sc_ethercom.ec_capabilities 335 |= ETHERCAP_JUMBO_MTU; 336 337 sc->sc_flags |= GEM_GIGABIT; 338 break; 339 } 340 } 341 342 /* claim 802.1q capability */ 343 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 344 345 /* Attach the interface. */ 346 if_attach(ifp); 347 ether_ifattach(ifp, enaddr); 348 349 sc->sc_sh = shutdownhook_establish(gem_shutdown, sc); 350 if (sc->sc_sh == NULL) 351 panic("gem_config: can't establish shutdownhook"); 352 353 #if NRND > 0 354 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 355 RND_TYPE_NET, 0); 356 #endif 357 358 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, 359 NULL, sc->sc_dev.dv_xname, "interrupts"); 360 #ifdef GEM_COUNTERS 361 evcnt_attach_dynamic(&sc->sc_ev_txint, EVCNT_TYPE_INTR, 362 &sc->sc_ev_intr, sc->sc_dev.dv_xname, "tx interrupts"); 363 evcnt_attach_dynamic(&sc->sc_ev_rxint, EVCNT_TYPE_INTR, 364 &sc->sc_ev_intr, sc->sc_dev.dv_xname, "rx interrupts"); 365 evcnt_attach_dynamic(&sc->sc_ev_rxfull, EVCNT_TYPE_INTR, 366 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx ring full"); 367 evcnt_attach_dynamic(&sc->sc_ev_rxnobuf, EVCNT_TYPE_INTR, 368 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx malloc failure"); 369 evcnt_attach_dynamic(&sc->sc_ev_rxhist[0], EVCNT_TYPE_INTR, 370 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 0desc"); 371 evcnt_attach_dynamic(&sc->sc_ev_rxhist[1], EVCNT_TYPE_INTR, 372 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 1desc"); 373 evcnt_attach_dynamic(&sc->sc_ev_rxhist[2], EVCNT_TYPE_INTR, 374 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 2desc"); 375 evcnt_attach_dynamic(&sc->sc_ev_rxhist[3], EVCNT_TYPE_INTR, 376 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 3desc"); 377 evcnt_attach_dynamic(&sc->sc_ev_rxhist[4], EVCNT_TYPE_INTR, 378 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >3desc"); 379 evcnt_attach_dynamic(&sc->sc_ev_rxhist[5], EVCNT_TYPE_INTR, 380 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >7desc"); 381 evcnt_attach_dynamic(&sc->sc_ev_rxhist[6], EVCNT_TYPE_INTR, 382 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >15desc"); 383 evcnt_attach_dynamic(&sc->sc_ev_rxhist[7], EVCNT_TYPE_INTR, 384 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >31desc"); 385 evcnt_attach_dynamic(&sc->sc_ev_rxhist[8], EVCNT_TYPE_INTR, 386 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >63desc"); 387 #endif 388 389 #if notyet 390 /* 391 * Add a suspend hook to make sure we come back up after a 392 * resume. 393 */ 394 sc->sc_powerhook = powerhook_establish(gem_power, sc); 395 if (sc->sc_powerhook == NULL) 396 aprint_error("%s: WARNING: unable to establish power hook\n", 397 sc->sc_dev.dv_xname); 398 #endif 399 400 callout_init(&sc->sc_tick_ch); 401 return; 402 403 /* 404 * Free any resources we've allocated during the failed attach 405 * attempt. Do this in reverse order and fall through. 406 */ 407 fail_5: 408 for (i = 0; i < GEM_NRXDESC; i++) { 409 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 410 bus_dmamap_destroy(sc->sc_dmatag, 411 sc->sc_rxsoft[i].rxs_dmamap); 412 } 413 fail_4: 414 for (i = 0; i < GEM_TXQUEUELEN; i++) { 415 if (sc->sc_txsoft[i].txs_dmamap != NULL) 416 bus_dmamap_destroy(sc->sc_dmatag, 417 sc->sc_txsoft[i].txs_dmamap); 418 } 419 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 420 fail_3: 421 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 422 fail_2: 423 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)sc->sc_control_data, 424 sizeof(struct gem_control_data)); 425 fail_1: 426 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 427 fail_0: 428 return; 429 } 430 431 432 void 433 gem_tick(arg) 434 void *arg; 435 { 436 struct gem_softc *sc = arg; 437 int s; 438 439 s = splnet(); 440 mii_tick(&sc->sc_mii); 441 splx(s); 442 443 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 444 445 } 446 447 void 448 gem_reset(sc) 449 struct gem_softc *sc; 450 { 451 bus_space_tag_t t = sc->sc_bustag; 452 bus_space_handle_t h = sc->sc_h; 453 int i; 454 int s; 455 456 s = splnet(); 457 DPRINTF(sc, ("%s: gem_reset\n", sc->sc_dev.dv_xname)); 458 gem_reset_rx(sc); 459 gem_reset_tx(sc); 460 461 /* Do a full reset */ 462 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX|GEM_RESET_TX); 463 for (i=TRIES; i--; delay(100)) 464 if ((bus_space_read_4(t, h, GEM_RESET) & 465 (GEM_RESET_RX|GEM_RESET_TX)) == 0) 466 break; 467 if ((bus_space_read_4(t, h, GEM_RESET) & 468 (GEM_RESET_RX|GEM_RESET_TX)) != 0) { 469 printf("%s: cannot reset device\n", 470 sc->sc_dev.dv_xname); 471 } 472 splx(s); 473 } 474 475 476 /* 477 * gem_rxdrain: 478 * 479 * Drain the receive queue. 480 */ 481 void 482 gem_rxdrain(struct gem_softc *sc) 483 { 484 struct gem_rxsoft *rxs; 485 int i; 486 487 for (i = 0; i < GEM_NRXDESC; i++) { 488 rxs = &sc->sc_rxsoft[i]; 489 if (rxs->rxs_mbuf != NULL) { 490 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 491 m_freem(rxs->rxs_mbuf); 492 rxs->rxs_mbuf = NULL; 493 } 494 } 495 } 496 497 /* 498 * Reset the whole thing. 499 */ 500 void 501 gem_stop(struct ifnet *ifp, int disable) 502 { 503 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 504 struct gem_txsoft *txs; 505 506 DPRINTF(sc, ("%s: gem_stop\n", sc->sc_dev.dv_xname)); 507 508 callout_stop(&sc->sc_tick_ch); 509 mii_down(&sc->sc_mii); 510 511 /* XXX - Should we reset these instead? */ 512 gem_disable_rx(sc); 513 gem_disable_tx(sc); 514 515 /* 516 * Release any queued transmit buffers. 517 */ 518 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 519 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 520 if (txs->txs_mbuf != NULL) { 521 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 522 m_freem(txs->txs_mbuf); 523 txs->txs_mbuf = NULL; 524 } 525 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 526 } 527 528 if (disable) { 529 gem_rxdrain(sc); 530 } 531 532 /* 533 * Mark the interface down and cancel the watchdog timer. 534 */ 535 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 536 ifp->if_timer = 0; 537 } 538 539 540 /* 541 * Reset the receiver 542 */ 543 int 544 gem_reset_rx(struct gem_softc *sc) 545 { 546 bus_space_tag_t t = sc->sc_bustag; 547 bus_space_handle_t h = sc->sc_h; 548 int i; 549 550 551 /* 552 * Resetting while DMA is in progress can cause a bus hang, so we 553 * disable DMA first. 554 */ 555 gem_disable_rx(sc); 556 bus_space_write_4(t, h, GEM_RX_CONFIG, 0); 557 /* Wait till it finishes */ 558 for (i=TRIES; i--; delay(100)) 559 if ((bus_space_read_4(t, h, GEM_RX_CONFIG) & 1) == 0) 560 break; 561 if ((bus_space_read_4(t, h, GEM_RX_CONFIG) & 1) != 0) 562 printf("%s: cannot disable read dma\n", 563 sc->sc_dev.dv_xname); 564 565 /* Wait 5ms extra. */ 566 delay(5000); 567 568 /* Finally, reset the ERX */ 569 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX); 570 /* Wait till it finishes */ 571 for (i=TRIES; i--; delay(100)) 572 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_RX) == 0) 573 break; 574 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_RX) != 0) { 575 printf("%s: cannot reset receiver\n", 576 sc->sc_dev.dv_xname); 577 return (1); 578 } 579 return (0); 580 } 581 582 583 /* 584 * Reset the transmitter 585 */ 586 int 587 gem_reset_tx(struct gem_softc *sc) 588 { 589 bus_space_tag_t t = sc->sc_bustag; 590 bus_space_handle_t h = sc->sc_h; 591 int i; 592 593 /* 594 * Resetting while DMA is in progress can cause a bus hang, so we 595 * disable DMA first. 596 */ 597 gem_disable_tx(sc); 598 bus_space_write_4(t, h, GEM_TX_CONFIG, 0); 599 /* Wait till it finishes */ 600 for (i=TRIES; i--; delay(100)) 601 if ((bus_space_read_4(t, h, GEM_TX_CONFIG) & 1) == 0) 602 break; 603 if ((bus_space_read_4(t, h, GEM_TX_CONFIG) & 1) != 0) 604 printf("%s: cannot disable read dma\n", 605 sc->sc_dev.dv_xname); 606 607 /* Wait 5ms extra. */ 608 delay(5000); 609 610 /* Finally, reset the ETX */ 611 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_TX); 612 /* Wait till it finishes */ 613 for (i=TRIES; i--; delay(100)) 614 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_TX) == 0) 615 break; 616 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_TX) != 0) { 617 printf("%s: cannot reset receiver\n", 618 sc->sc_dev.dv_xname); 619 return (1); 620 } 621 return (0); 622 } 623 624 /* 625 * disable receiver. 626 */ 627 int 628 gem_disable_rx(struct gem_softc *sc) 629 { 630 bus_space_tag_t t = sc->sc_bustag; 631 bus_space_handle_t h = sc->sc_h; 632 int i; 633 u_int32_t cfg; 634 635 /* Flip the enable bit */ 636 cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 637 cfg &= ~GEM_MAC_RX_ENABLE; 638 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg); 639 640 /* Wait for it to finish */ 641 for (i=TRIES; i--; delay(100)) 642 if ((bus_space_read_4(t, h, GEM_MAC_RX_CONFIG) & 643 GEM_MAC_RX_ENABLE) == 0) 644 return (0); 645 return (1); 646 } 647 648 /* 649 * disable transmitter. 650 */ 651 int 652 gem_disable_tx(struct gem_softc *sc) 653 { 654 bus_space_tag_t t = sc->sc_bustag; 655 bus_space_handle_t h = sc->sc_h; 656 int i; 657 u_int32_t cfg; 658 659 /* Flip the enable bit */ 660 cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG); 661 cfg &= ~GEM_MAC_TX_ENABLE; 662 bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg); 663 664 /* Wait for it to finish */ 665 for (i=TRIES; i--; delay(100)) 666 if ((bus_space_read_4(t, h, GEM_MAC_TX_CONFIG) & 667 GEM_MAC_TX_ENABLE) == 0) 668 return (0); 669 return (1); 670 } 671 672 /* 673 * Initialize interface. 674 */ 675 int 676 gem_meminit(struct gem_softc *sc) 677 { 678 struct gem_rxsoft *rxs; 679 int i, error; 680 681 /* 682 * Initialize the transmit descriptor ring. 683 */ 684 memset((void *)sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 685 for (i = 0; i < GEM_NTXDESC; i++) { 686 sc->sc_txdescs[i].gd_flags = 0; 687 sc->sc_txdescs[i].gd_addr = 0; 688 } 689 GEM_CDTXSYNC(sc, 0, GEM_NTXDESC, 690 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 691 sc->sc_txfree = GEM_NTXDESC-1; 692 sc->sc_txnext = 0; 693 sc->sc_txwin = 0; 694 695 /* 696 * Initialize the receive descriptor and receive job 697 * descriptor rings. 698 */ 699 for (i = 0; i < GEM_NRXDESC; i++) { 700 rxs = &sc->sc_rxsoft[i]; 701 if (rxs->rxs_mbuf == NULL) { 702 if ((error = gem_add_rxbuf(sc, i)) != 0) { 703 printf("%s: unable to allocate or map rx " 704 "buffer %d, error = %d\n", 705 sc->sc_dev.dv_xname, i, error); 706 /* 707 * XXX Should attempt to run with fewer receive 708 * XXX buffers instead of just failing. 709 */ 710 gem_rxdrain(sc); 711 return (1); 712 } 713 } else 714 GEM_INIT_RXDESC(sc, i); 715 } 716 sc->sc_rxptr = 0; 717 718 return (0); 719 } 720 721 static int 722 gem_ringsize(int sz) 723 { 724 int v; 725 726 switch (sz) { 727 case 32: 728 v = GEM_RING_SZ_32; 729 break; 730 case 64: 731 v = GEM_RING_SZ_64; 732 break; 733 case 128: 734 v = GEM_RING_SZ_128; 735 break; 736 case 256: 737 v = GEM_RING_SZ_256; 738 break; 739 case 512: 740 v = GEM_RING_SZ_512; 741 break; 742 case 1024: 743 v = GEM_RING_SZ_1024; 744 break; 745 case 2048: 746 v = GEM_RING_SZ_2048; 747 break; 748 case 4096: 749 v = GEM_RING_SZ_4096; 750 break; 751 case 8192: 752 v = GEM_RING_SZ_8192; 753 break; 754 default: 755 printf("gem: invalid Receive Descriptor ring size\n"); 756 break; 757 } 758 return (v); 759 } 760 761 /* 762 * Initialization of interface; set up initialization block 763 * and transmit/receive descriptor rings. 764 */ 765 int 766 gem_init(struct ifnet *ifp) 767 { 768 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 769 bus_space_tag_t t = sc->sc_bustag; 770 bus_space_handle_t h = sc->sc_h; 771 int s; 772 u_int max_frame_size; 773 u_int32_t v; 774 775 s = splnet(); 776 777 DPRINTF(sc, ("%s: gem_init: calling stop\n", sc->sc_dev.dv_xname)); 778 /* 779 * Initialization sequence. The numbered steps below correspond 780 * to the sequence outlined in section 6.3.5.1 in the Ethernet 781 * Channel Engine manual (part of the PCIO manual). 782 * See also the STP2002-STQ document from Sun Microsystems. 783 */ 784 785 /* step 1 & 2. Reset the Ethernet Channel */ 786 gem_stop(ifp, 0); 787 gem_reset(sc); 788 DPRINTF(sc, ("%s: gem_init: restarting\n", sc->sc_dev.dv_xname)); 789 790 /* Re-initialize the MIF */ 791 gem_mifinit(sc); 792 793 /* Call MI reset function if any */ 794 if (sc->sc_hwreset) 795 (*sc->sc_hwreset)(sc); 796 797 /* step 3. Setup data structures in host memory */ 798 gem_meminit(sc); 799 800 /* step 4. TX MAC registers & counters */ 801 gem_init_regs(sc); 802 max_frame_size = max(sc->sc_ethercom.ec_if.if_mtu, ETHERMTU); 803 max_frame_size += ETHER_HDR_LEN + ETHER_CRC_LEN; 804 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 805 max_frame_size += ETHER_VLAN_ENCAP_LEN; 806 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 807 max_frame_size|/* burst size */(0x2000<<16)); 808 809 /* step 5. RX MAC registers & counters */ 810 gem_setladrf(sc); 811 812 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 813 /* NOTE: we use only 32-bit DMA addresses here. */ 814 bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 0); 815 bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 816 817 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0); 818 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 819 820 /* step 8. Global Configuration & Interrupt Mask */ 821 bus_space_write_4(t, h, GEM_INTMASK, 822 ~(GEM_INTR_TX_INTME| 823 GEM_INTR_TX_EMPTY| 824 GEM_INTR_RX_DONE|GEM_INTR_RX_NOBUF| 825 GEM_INTR_RX_TAG_ERR|GEM_INTR_PCS| 826 GEM_INTR_MAC_CONTROL|GEM_INTR_MIF| 827 GEM_INTR_BERR)); 828 bus_space_write_4(t, h, GEM_MAC_RX_MASK, 829 GEM_MAC_RX_DONE|GEM_MAC_RX_FRAME_CNT); 830 bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXXX */ 831 bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 0); /* XXXX */ 832 833 /* step 9. ETX Configuration: use mostly default values */ 834 835 /* Enable DMA */ 836 v = gem_ringsize(GEM_NTXDESC /*XXX*/); 837 bus_space_write_4(t, h, GEM_TX_CONFIG, 838 v|GEM_TX_CONFIG_TXDMA_EN| 839 ((0x400<<10)&GEM_TX_CONFIG_TXFIFO_TH)); 840 bus_space_write_4(t, h, GEM_TX_KICK, sc->sc_txnext); 841 842 /* step 10. ERX Configuration */ 843 844 /* Encode Receive Descriptor ring size: four possible values */ 845 v = gem_ringsize(GEM_NRXDESC /*XXX*/); 846 847 /* Enable DMA */ 848 bus_space_write_4(t, h, GEM_RX_CONFIG, 849 v|(GEM_THRSH_1024<<GEM_RX_CONFIG_FIFO_THRS_SHIFT)| 850 (2<<GEM_RX_CONFIG_FBOFF_SHFT)|GEM_RX_CONFIG_RXDMA_EN| 851 (0<<GEM_RX_CONFIG_CXM_START_SHFT)); 852 /* 853 * The following value is for an OFF Threshold of about 3/4 full 854 * and an ON Threshold of 1/4 full. 855 */ 856 bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH, 857 (3 * sc->sc_rxfifosize / 256) | 858 ( (sc->sc_rxfifosize / 256) << 12)); 859 bus_space_write_4(t, h, GEM_RX_BLANKING, (6<<12)|6); 860 861 /* step 11. Configure Media */ 862 mii_mediachg(&sc->sc_mii); 863 864 /* XXXX Serial link needs a whole different setup. */ 865 866 867 /* step 12. RX_MAC Configuration Register */ 868 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 869 v |= GEM_MAC_RX_ENABLE; 870 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 871 872 /* step 14. Issue Transmit Pending command */ 873 874 /* Call MI initialization function if any */ 875 if (sc->sc_hwinit) 876 (*sc->sc_hwinit)(sc); 877 878 879 /* step 15. Give the reciever a swift kick */ 880 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4); 881 882 /* Start the one second timer. */ 883 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 884 885 ifp->if_flags |= IFF_RUNNING; 886 ifp->if_flags &= ~IFF_OACTIVE; 887 ifp->if_timer = 0; 888 splx(s); 889 890 return (0); 891 } 892 893 void 894 gem_init_regs(struct gem_softc *sc) 895 { 896 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 897 bus_space_tag_t t = sc->sc_bustag; 898 bus_space_handle_t h = sc->sc_h; 899 const u_char *laddr = LLADDR(ifp->if_sadl); 900 u_int32_t v; 901 902 /* These regs are not cleared on reset */ 903 if (!sc->sc_inited) { 904 905 /* Wooo. Magic values. */ 906 bus_space_write_4(t, h, GEM_MAC_IPG0, 0); 907 bus_space_write_4(t, h, GEM_MAC_IPG1, 8); 908 bus_space_write_4(t, h, GEM_MAC_IPG2, 4); 909 910 bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 911 /* Max frame and max burst size */ 912 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 913 ETHER_MAX_LEN | (0x2000<<16)); 914 915 bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x7); 916 bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x4); 917 bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10); 918 /* Dunno.... */ 919 bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088); 920 bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED, 921 ((laddr[5]<<8)|laddr[4])&0x3ff); 922 923 /* Secondary MAC addr set to 0:0:0:0:0:0 */ 924 bus_space_write_4(t, h, GEM_MAC_ADDR3, 0); 925 bus_space_write_4(t, h, GEM_MAC_ADDR4, 0); 926 bus_space_write_4(t, h, GEM_MAC_ADDR5, 0); 927 928 /* MAC control addr set to 01:80:c2:00:00:01 */ 929 bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001); 930 bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200); 931 bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180); 932 933 /* MAC filter addr set to 0:0:0:0:0:0 */ 934 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0); 935 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0); 936 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0); 937 938 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0); 939 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0); 940 941 sc->sc_inited = 1; 942 } 943 944 /* Counters need to be zeroed */ 945 bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0); 946 bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0); 947 bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0); 948 bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0); 949 bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0); 950 bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0); 951 bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0); 952 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 953 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 954 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 955 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 956 957 /* Un-pause stuff */ 958 #if 0 959 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); 960 #else 961 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0); 962 #endif 963 964 /* 965 * Set the station address. 966 */ 967 bus_space_write_4(t, h, GEM_MAC_ADDR0, (laddr[4]<<8)|laddr[5]); 968 bus_space_write_4(t, h, GEM_MAC_ADDR1, (laddr[2]<<8)|laddr[3]); 969 bus_space_write_4(t, h, GEM_MAC_ADDR2, (laddr[0]<<8)|laddr[1]); 970 971 #if 0 972 if (sc->sc_variant != APPLE_GMAC) 973 return; 974 #endif 975 976 /* 977 * Enable MII outputs. Enable GMII if there is a gigabit PHY. 978 */ 979 sc->sc_mif_config = bus_space_read_4(t, h, GEM_MIF_CONFIG); 980 v = GEM_MAC_XIF_TX_MII_ENA; 981 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) { 982 v |= GEM_MAC_XIF_FDPLX_LED; 983 if (sc->sc_flags & GEM_GIGABIT) 984 v |= GEM_MAC_XIF_GMII_MODE; 985 } 986 bus_space_write_4(t, h, GEM_MAC_XIF_CONFIG, v); 987 } 988 989 void 990 gem_start(ifp) 991 struct ifnet *ifp; 992 { 993 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 994 struct mbuf *m0, *m; 995 struct gem_txsoft *txs, *last_txs; 996 bus_dmamap_t dmamap; 997 int error, firsttx, nexttx, lasttx, ofree, seg; 998 999 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1000 return; 1001 1002 /* 1003 * Remember the previous number of free descriptors and 1004 * the first descriptor we'll use. 1005 */ 1006 ofree = sc->sc_txfree; 1007 firsttx = sc->sc_txnext; 1008 1009 DPRINTF(sc, ("%s: gem_start: txfree %d, txnext %d\n", 1010 sc->sc_dev.dv_xname, ofree, firsttx)); 1011 1012 /* 1013 * Loop through the send queue, setting up transmit descriptors 1014 * until we drain the queue, or use up all available transmit 1015 * descriptors. 1016 */ 1017 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 1018 sc->sc_txfree != 0) { 1019 /* 1020 * Grab a packet off the queue. 1021 */ 1022 IFQ_POLL(&ifp->if_snd, m0); 1023 if (m0 == NULL) 1024 break; 1025 m = NULL; 1026 1027 dmamap = txs->txs_dmamap; 1028 1029 /* 1030 * Load the DMA map. If this fails, the packet either 1031 * didn't fit in the alloted number of segments, or we were 1032 * short on resources. In this case, we'll copy and try 1033 * again. 1034 */ 1035 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m0, 1036 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1037 if (m0->m_pkthdr.len > MCLBYTES) { 1038 printf("%s: unable to allocate jumbo Tx " 1039 "cluster\n", sc->sc_dev.dv_xname); 1040 IFQ_DEQUEUE(&ifp->if_snd, m0); 1041 m_freem(m0); 1042 continue; 1043 } 1044 MGETHDR(m, M_DONTWAIT, MT_DATA); 1045 if (m == NULL) { 1046 printf("%s: unable to allocate Tx mbuf\n", 1047 sc->sc_dev.dv_xname); 1048 break; 1049 } 1050 if (m0->m_pkthdr.len > MHLEN) { 1051 MCLGET(m, M_DONTWAIT); 1052 if ((m->m_flags & M_EXT) == 0) { 1053 printf("%s: unable to allocate Tx " 1054 "cluster\n", sc->sc_dev.dv_xname); 1055 m_freem(m); 1056 break; 1057 } 1058 } 1059 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 1060 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1061 error = bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, 1062 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1063 if (error) { 1064 printf("%s: unable to load Tx buffer, " 1065 "error = %d\n", sc->sc_dev.dv_xname, error); 1066 break; 1067 } 1068 } 1069 1070 /* 1071 * Ensure we have enough descriptors free to describe 1072 * the packet. 1073 */ 1074 if (dmamap->dm_nsegs > sc->sc_txfree) { 1075 /* 1076 * Not enough free descriptors to transmit this 1077 * packet. We haven't committed to anything yet, 1078 * so just unload the DMA map, put the packet 1079 * back on the queue, and punt. Notify the upper 1080 * layer that there are no more slots left. 1081 * 1082 * XXX We could allocate an mbuf and copy, but 1083 * XXX it is worth it? 1084 */ 1085 ifp->if_flags |= IFF_OACTIVE; 1086 bus_dmamap_unload(sc->sc_dmatag, dmamap); 1087 if (m != NULL) 1088 m_freem(m); 1089 break; 1090 } 1091 1092 IFQ_DEQUEUE(&ifp->if_snd, m0); 1093 if (m != NULL) { 1094 m_freem(m0); 1095 m0 = m; 1096 } 1097 1098 /* 1099 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1100 */ 1101 1102 /* Sync the DMA map. */ 1103 bus_dmamap_sync(sc->sc_dmatag, dmamap, 0, dmamap->dm_mapsize, 1104 BUS_DMASYNC_PREWRITE); 1105 1106 /* 1107 * Initialize the transmit descriptors. 1108 */ 1109 for (nexttx = sc->sc_txnext, seg = 0; 1110 seg < dmamap->dm_nsegs; 1111 seg++, nexttx = GEM_NEXTTX(nexttx)) { 1112 uint64_t flags; 1113 1114 /* 1115 * If this is the first descriptor we're 1116 * enqueueing, set the start of packet flag, 1117 * and the checksum stuff if we want the hardware 1118 * to do it. 1119 */ 1120 sc->sc_txdescs[nexttx].gd_addr = 1121 GEM_DMA_WRITE(sc, dmamap->dm_segs[seg].ds_addr); 1122 flags = dmamap->dm_segs[seg].ds_len & GEM_TD_BUFSIZE; 1123 if (nexttx == firsttx) { 1124 flags |= GEM_TD_START_OF_PACKET; 1125 if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) { 1126 sc->sc_txwin = 0; 1127 flags |= GEM_TD_INTERRUPT_ME; 1128 } 1129 } 1130 if (seg == dmamap->dm_nsegs - 1) { 1131 flags |= GEM_TD_END_OF_PACKET; 1132 } 1133 sc->sc_txdescs[nexttx].gd_flags = 1134 GEM_DMA_WRITE(sc, flags); 1135 lasttx = nexttx; 1136 } 1137 1138 #ifdef GEM_DEBUG 1139 if (ifp->if_flags & IFF_DEBUG) { 1140 printf(" gem_start %p transmit chain:\n", txs); 1141 for (seg = sc->sc_txnext;; seg = GEM_NEXTTX(seg)) { 1142 printf("descriptor %d:\t", seg); 1143 printf("gd_flags: 0x%016llx\t", (long long) 1144 GEM_DMA_READ(sc, sc->sc_txdescs[seg].gd_flags)); 1145 printf("gd_addr: 0x%016llx\n", (long long) 1146 GEM_DMA_READ(sc, sc->sc_txdescs[seg].gd_addr)); 1147 if (seg == lasttx) 1148 break; 1149 } 1150 } 1151 #endif 1152 1153 /* Sync the descriptors we're using. */ 1154 GEM_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1155 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1156 1157 /* 1158 * Store a pointer to the packet so we can free it later, 1159 * and remember what txdirty will be once the packet is 1160 * done. 1161 */ 1162 txs->txs_mbuf = m0; 1163 txs->txs_firstdesc = sc->sc_txnext; 1164 txs->txs_lastdesc = lasttx; 1165 txs->txs_ndescs = dmamap->dm_nsegs; 1166 1167 /* Advance the tx pointer. */ 1168 sc->sc_txfree -= dmamap->dm_nsegs; 1169 sc->sc_txnext = nexttx; 1170 1171 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1172 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1173 1174 last_txs = txs; 1175 1176 #if NBPFILTER > 0 1177 /* 1178 * Pass the packet to any BPF listeners. 1179 */ 1180 if (ifp->if_bpf) 1181 bpf_mtap(ifp->if_bpf, m0); 1182 #endif /* NBPFILTER > 0 */ 1183 } 1184 1185 if (txs == NULL || sc->sc_txfree == 0) { 1186 /* No more slots left; notify upper layer. */ 1187 ifp->if_flags |= IFF_OACTIVE; 1188 } 1189 1190 if (sc->sc_txfree != ofree) { 1191 DPRINTF(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 1192 sc->sc_dev.dv_xname, lasttx, firsttx)); 1193 /* 1194 * The entire packet chain is set up. 1195 * Kick the transmitter. 1196 */ 1197 DPRINTF(sc, ("%s: gem_start: kicking tx %d\n", 1198 sc->sc_dev.dv_xname, nexttx)); 1199 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_TX_KICK, 1200 sc->sc_txnext); 1201 1202 /* Set a watchdog timer in case the chip flakes out. */ 1203 ifp->if_timer = 5; 1204 DPRINTF(sc, ("%s: gem_start: watchdog %d\n", 1205 sc->sc_dev.dv_xname, ifp->if_timer)); 1206 } 1207 } 1208 1209 /* 1210 * Transmit interrupt. 1211 */ 1212 int 1213 gem_tint(sc) 1214 struct gem_softc *sc; 1215 { 1216 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1217 bus_space_tag_t t = sc->sc_bustag; 1218 bus_space_handle_t mac = sc->sc_h; 1219 struct gem_txsoft *txs; 1220 int txlast; 1221 int progress = 0; 1222 1223 1224 DPRINTF(sc, ("%s: gem_tint\n", sc->sc_dev.dv_xname)); 1225 1226 /* 1227 * Unload collision counters 1228 */ 1229 ifp->if_collisions += 1230 bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) + 1231 bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT) + 1232 bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) + 1233 bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT); 1234 1235 /* 1236 * then clear the hardware counters. 1237 */ 1238 bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0); 1239 bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0); 1240 bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0); 1241 bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0); 1242 1243 /* 1244 * Go through our Tx list and free mbufs for those 1245 * frames that have been transmitted. 1246 */ 1247 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1248 GEM_CDTXSYNC(sc, txs->txs_lastdesc, 1249 txs->txs_ndescs, 1250 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1251 1252 #ifdef GEM_DEBUG 1253 if (ifp->if_flags & IFF_DEBUG) { 1254 int i; 1255 printf(" txsoft %p transmit chain:\n", txs); 1256 for (i = txs->txs_firstdesc;; i = GEM_NEXTTX(i)) { 1257 printf("descriptor %d: ", i); 1258 printf("gd_flags: 0x%016llx\t", (long long) 1259 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags)); 1260 printf("gd_addr: 0x%016llx\n", (long long) 1261 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr)); 1262 if (i == txs->txs_lastdesc) 1263 break; 1264 } 1265 } 1266 #endif 1267 1268 /* 1269 * In theory, we could harveast some descriptors before 1270 * the ring is empty, but that's a bit complicated. 1271 * 1272 * GEM_TX_COMPLETION points to the last descriptor 1273 * processed +1. 1274 */ 1275 txlast = bus_space_read_4(t, mac, GEM_TX_COMPLETION); 1276 DPRINTF(sc, 1277 ("gem_tint: txs->txs_lastdesc = %d, txlast = %d\n", 1278 txs->txs_lastdesc, txlast)); 1279 if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1280 if ((txlast >= txs->txs_firstdesc) && 1281 (txlast <= txs->txs_lastdesc)) 1282 break; 1283 } else { 1284 /* Ick -- this command wraps */ 1285 if ((txlast >= txs->txs_firstdesc) || 1286 (txlast <= txs->txs_lastdesc)) 1287 break; 1288 } 1289 1290 DPRINTF(sc, ("gem_tint: releasing a desc\n")); 1291 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1292 1293 sc->sc_txfree += txs->txs_ndescs; 1294 1295 if (txs->txs_mbuf == NULL) { 1296 #ifdef DIAGNOSTIC 1297 panic("gem_txintr: null mbuf"); 1298 #endif 1299 } 1300 1301 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 1302 0, txs->txs_dmamap->dm_mapsize, 1303 BUS_DMASYNC_POSTWRITE); 1304 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 1305 m_freem(txs->txs_mbuf); 1306 txs->txs_mbuf = NULL; 1307 1308 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1309 1310 ifp->if_opackets++; 1311 progress = 1; 1312 } 1313 1314 DPRINTF(sc, ("gem_tint: GEM_TX_STATE_MACHINE %x " 1315 "GEM_TX_DATA_PTR %llx " 1316 "GEM_TX_COMPLETION %x\n", 1317 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_STATE_MACHINE), 1318 ((long long) bus_space_read_4(sc->sc_bustag, sc->sc_h, 1319 GEM_TX_DATA_PTR_HI) << 32) | 1320 bus_space_read_4(sc->sc_bustag, sc->sc_h, 1321 GEM_TX_DATA_PTR_LO), 1322 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_COMPLETION))); 1323 1324 if (progress) { 1325 if (sc->sc_txfree == GEM_NTXDESC - 1) 1326 sc->sc_txwin = 0; 1327 1328 ifp->if_flags &= ~IFF_OACTIVE; 1329 gem_start(ifp); 1330 1331 if (SIMPLEQ_EMPTY(&sc->sc_txdirtyq)) 1332 ifp->if_timer = 0; 1333 } 1334 DPRINTF(sc, ("%s: gem_tint: watchdog %d\n", 1335 sc->sc_dev.dv_xname, ifp->if_timer)); 1336 1337 return (1); 1338 } 1339 1340 /* 1341 * Receive interrupt. 1342 */ 1343 int 1344 gem_rint(sc) 1345 struct gem_softc *sc; 1346 { 1347 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1348 bus_space_tag_t t = sc->sc_bustag; 1349 bus_space_handle_t h = sc->sc_h; 1350 struct ether_header *eh; 1351 struct gem_rxsoft *rxs; 1352 struct mbuf *m; 1353 u_int64_t rxstat; 1354 u_int32_t rxcomp; 1355 int i, len, progress = 0; 1356 1357 DPRINTF(sc, ("%s: gem_rint\n", sc->sc_dev.dv_xname)); 1358 1359 /* 1360 * Read the completion register once. This limits 1361 * how long the following loop can execute. 1362 */ 1363 rxcomp = bus_space_read_4(t, h, GEM_RX_COMPLETION); 1364 1365 /* 1366 * XXXX Read the lastrx only once at the top for speed. 1367 */ 1368 DPRINTF(sc, ("gem_rint: sc->rxptr %d, complete %d\n", 1369 sc->sc_rxptr, rxcomp)); 1370 1371 /* 1372 * Go into the loop at least once. 1373 */ 1374 for (i = sc->sc_rxptr; i == sc->sc_rxptr || i != rxcomp; 1375 i = GEM_NEXTRX(i)) { 1376 rxs = &sc->sc_rxsoft[i]; 1377 1378 GEM_CDRXSYNC(sc, i, 1379 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1380 1381 rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags); 1382 1383 if (rxstat & GEM_RD_OWN) { 1384 /* 1385 * We have processed all of the receive buffers. 1386 */ 1387 break; 1388 } 1389 1390 progress++; 1391 ifp->if_ipackets++; 1392 1393 if (rxstat & GEM_RD_BAD_CRC) { 1394 ifp->if_ierrors++; 1395 printf("%s: receive error: CRC error\n", 1396 sc->sc_dev.dv_xname); 1397 GEM_INIT_RXDESC(sc, i); 1398 continue; 1399 } 1400 1401 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1402 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1403 #ifdef GEM_DEBUG 1404 if (ifp->if_flags & IFF_DEBUG) { 1405 printf(" rxsoft %p descriptor %d: ", rxs, i); 1406 printf("gd_flags: 0x%016llx\t", (long long) 1407 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags)); 1408 printf("gd_addr: 0x%016llx\n", (long long) 1409 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr)); 1410 } 1411 #endif 1412 1413 /* 1414 * No errors; receive the packet. Note the Gem 1415 * includes the CRC with every packet. 1416 */ 1417 len = GEM_RD_BUFLEN(rxstat); 1418 1419 /* 1420 * Allocate a new mbuf cluster. If that fails, we are 1421 * out of memory, and must drop the packet and recycle 1422 * the buffer that's already attached to this descriptor. 1423 */ 1424 m = rxs->rxs_mbuf; 1425 if (gem_add_rxbuf(sc, i) != 0) { 1426 GEM_COUNTER_INCR(sc, sc_ev_rxnobuf); 1427 ifp->if_ierrors++; 1428 GEM_INIT_RXDESC(sc, i); 1429 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1430 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1431 continue; 1432 } 1433 m->m_data += 2; /* We're already off by two */ 1434 1435 eh = mtod(m, struct ether_header *); 1436 m->m_flags |= M_HASFCS; 1437 m->m_pkthdr.rcvif = ifp; 1438 m->m_pkthdr.len = m->m_len = len; 1439 1440 #if NBPFILTER > 0 1441 /* 1442 * Pass this up to any BPF listeners, but only 1443 * pass it up the stack if its for us. 1444 */ 1445 if (ifp->if_bpf) 1446 bpf_mtap(ifp->if_bpf, m); 1447 #endif /* NPBFILTER > 0 */ 1448 1449 /* Pass it on. */ 1450 (*ifp->if_input)(ifp, m); 1451 } 1452 1453 if (progress) { 1454 /* Update the receive pointer. */ 1455 if (i == sc->sc_rxptr) { 1456 GEM_COUNTER_INCR(sc, sc_ev_rxfull); 1457 #ifdef GEM_DEBUG 1458 if (ifp->if_flags & GEM_DEBUG) 1459 printf("%s: rint: ring wrap\n", 1460 sc->sc_dev.dv_xname); 1461 #endif 1462 } 1463 sc->sc_rxptr = i; 1464 bus_space_write_4(t, h, GEM_RX_KICK, GEM_PREVRX(i)); 1465 } 1466 #ifdef GEM_COUNTERS 1467 if (progress <= 4) { 1468 GEM_COUNTER_INCR(sc, sc_ev_rxhist[progress]); 1469 } else if (progress > 31) { 1470 if (progress < 16) 1471 GEM_COUNTER_INCR(sc, sc_ev_rxhist[5]); 1472 else 1473 GEM_COUNTER_INCR(sc, sc_ev_rxhist[6]); 1474 1475 } else { 1476 if (progress < 64) 1477 GEM_COUNTER_INCR(sc, sc_ev_rxhist[7]); 1478 else 1479 GEM_COUNTER_INCR(sc, sc_ev_rxhist[8]); 1480 } 1481 #endif 1482 1483 DPRINTF(sc, ("gem_rint: done sc->rxptr %d, complete %d\n", 1484 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION))); 1485 1486 return (1); 1487 } 1488 1489 1490 /* 1491 * gem_add_rxbuf: 1492 * 1493 * Add a receive buffer to the indicated descriptor. 1494 */ 1495 int 1496 gem_add_rxbuf(struct gem_softc *sc, int idx) 1497 { 1498 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1499 struct mbuf *m; 1500 int error; 1501 1502 MGETHDR(m, M_DONTWAIT, MT_DATA); 1503 if (m == NULL) 1504 return (ENOBUFS); 1505 1506 MCLGET(m, M_DONTWAIT); 1507 if ((m->m_flags & M_EXT) == 0) { 1508 m_freem(m); 1509 return (ENOBUFS); 1510 } 1511 1512 #ifdef GEM_DEBUG 1513 /* bzero the packet to check dma */ 1514 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 1515 #endif 1516 1517 if (rxs->rxs_mbuf != NULL) 1518 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 1519 1520 rxs->rxs_mbuf = m; 1521 1522 error = bus_dmamap_load(sc->sc_dmatag, rxs->rxs_dmamap, 1523 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1524 BUS_DMA_READ|BUS_DMA_NOWAIT); 1525 if (error) { 1526 printf("%s: can't load rx DMA map %d, error = %d\n", 1527 sc->sc_dev.dv_xname, idx, error); 1528 panic("gem_add_rxbuf"); /* XXX */ 1529 } 1530 1531 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1532 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1533 1534 GEM_INIT_RXDESC(sc, idx); 1535 1536 return (0); 1537 } 1538 1539 1540 int 1541 gem_eint(sc, status) 1542 struct gem_softc *sc; 1543 u_int status; 1544 { 1545 char bits[128]; 1546 1547 if ((status & GEM_INTR_MIF) != 0) { 1548 printf("%s: XXXlink status changed\n", sc->sc_dev.dv_xname); 1549 return (1); 1550 } 1551 1552 printf("%s: status=%s\n", sc->sc_dev.dv_xname, 1553 bitmask_snprintf(status, GEM_INTR_BITS, bits, sizeof(bits))); 1554 return (1); 1555 } 1556 1557 1558 int 1559 gem_intr(v) 1560 void *v; 1561 { 1562 struct gem_softc *sc = (struct gem_softc *)v; 1563 bus_space_tag_t t = sc->sc_bustag; 1564 bus_space_handle_t seb = sc->sc_h; 1565 u_int32_t status; 1566 int r = 0; 1567 #ifdef GEM_DEBUG 1568 char bits[128]; 1569 #endif 1570 1571 sc->sc_ev_intr.ev_count++; 1572 1573 status = bus_space_read_4(t, seb, GEM_STATUS); 1574 DPRINTF(sc, ("%s: gem_intr: cplt %xstatus %s\n", 1575 sc->sc_dev.dv_xname, (status>>19), 1576 bitmask_snprintf(status, GEM_INTR_BITS, bits, sizeof(bits)))); 1577 1578 if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0) 1579 r |= gem_eint(sc, status); 1580 1581 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) { 1582 GEM_COUNTER_INCR(sc, sc_ev_txint); 1583 r |= gem_tint(sc); 1584 } 1585 1586 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) { 1587 GEM_COUNTER_INCR(sc, sc_ev_rxint); 1588 r |= gem_rint(sc); 1589 } 1590 1591 /* We should eventually do more than just print out error stats. */ 1592 if (status & GEM_INTR_TX_MAC) { 1593 int txstat = bus_space_read_4(t, seb, GEM_MAC_TX_STATUS); 1594 if (txstat & ~GEM_MAC_TX_XMIT_DONE) 1595 printf("%s: MAC tx fault, status %x\n", 1596 sc->sc_dev.dv_xname, txstat); 1597 } 1598 if (status & GEM_INTR_RX_MAC) { 1599 int rxstat = bus_space_read_4(t, seb, GEM_MAC_RX_STATUS); 1600 if (rxstat & ~GEM_MAC_RX_DONE) 1601 printf("%s: MAC rx fault, status %x\n", 1602 sc->sc_dev.dv_xname, rxstat); 1603 } 1604 return (r); 1605 } 1606 1607 1608 void 1609 gem_watchdog(ifp) 1610 struct ifnet *ifp; 1611 { 1612 struct gem_softc *sc = ifp->if_softc; 1613 1614 DPRINTF(sc, ("gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x " 1615 "GEM_MAC_RX_CONFIG %x\n", 1616 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_CONFIG), 1617 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_STATUS), 1618 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_CONFIG))); 1619 1620 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1621 ++ifp->if_oerrors; 1622 1623 /* Try to get more packets going. */ 1624 gem_start(ifp); 1625 } 1626 1627 /* 1628 * Initialize the MII Management Interface 1629 */ 1630 void 1631 gem_mifinit(sc) 1632 struct gem_softc *sc; 1633 { 1634 bus_space_tag_t t = sc->sc_bustag; 1635 bus_space_handle_t mif = sc->sc_h; 1636 1637 /* Configure the MIF in frame mode */ 1638 sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1639 sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA; 1640 bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config); 1641 } 1642 1643 /* 1644 * MII interface 1645 * 1646 * The GEM MII interface supports at least three different operating modes: 1647 * 1648 * Bitbang mode is implemented using data, clock and output enable registers. 1649 * 1650 * Frame mode is implemented by loading a complete frame into the frame 1651 * register and polling the valid bit for completion. 1652 * 1653 * Polling mode uses the frame register but completion is indicated by 1654 * an interrupt. 1655 * 1656 */ 1657 static int 1658 gem_mii_readreg(self, phy, reg) 1659 struct device *self; 1660 int phy, reg; 1661 { 1662 struct gem_softc *sc = (void *)self; 1663 bus_space_tag_t t = sc->sc_bustag; 1664 bus_space_handle_t mif = sc->sc_h; 1665 int n; 1666 u_int32_t v; 1667 1668 #ifdef GEM_DEBUG1 1669 if (sc->sc_debug) 1670 printf("gem_mii_readreg: phy %d reg %d\n", phy, reg); 1671 #endif 1672 1673 #if 0 1674 /* Select the desired PHY in the MIF configuration register */ 1675 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1676 /* Clear PHY select bit */ 1677 v &= ~GEM_MIF_CONFIG_PHY_SEL; 1678 if (phy == GEM_PHYAD_EXTERNAL) 1679 /* Set PHY select bit to get at external device */ 1680 v |= GEM_MIF_CONFIG_PHY_SEL; 1681 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 1682 #endif 1683 1684 /* Construct the frame command */ 1685 v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) | 1686 GEM_MIF_FRAME_READ; 1687 1688 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1689 for (n = 0; n < 100; n++) { 1690 DELAY(1); 1691 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1692 if (v & GEM_MIF_FRAME_TA0) 1693 return (v & GEM_MIF_FRAME_DATA); 1694 } 1695 1696 printf("%s: mii_read timeout\n", sc->sc_dev.dv_xname); 1697 return (0); 1698 } 1699 1700 static void 1701 gem_mii_writereg(self, phy, reg, val) 1702 struct device *self; 1703 int phy, reg, val; 1704 { 1705 struct gem_softc *sc = (void *)self; 1706 bus_space_tag_t t = sc->sc_bustag; 1707 bus_space_handle_t mif = sc->sc_h; 1708 int n; 1709 u_int32_t v; 1710 1711 #ifdef GEM_DEBUG1 1712 if (sc->sc_debug) 1713 printf("gem_mii_writereg: phy %d reg %d val %x\n", 1714 phy, reg, val); 1715 #endif 1716 1717 #if 0 1718 /* Select the desired PHY in the MIF configuration register */ 1719 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1720 /* Clear PHY select bit */ 1721 v &= ~GEM_MIF_CONFIG_PHY_SEL; 1722 if (phy == GEM_PHYAD_EXTERNAL) 1723 /* Set PHY select bit to get at external device */ 1724 v |= GEM_MIF_CONFIG_PHY_SEL; 1725 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 1726 #endif 1727 /* Construct the frame command */ 1728 v = GEM_MIF_FRAME_WRITE | 1729 (phy << GEM_MIF_PHY_SHIFT) | 1730 (reg << GEM_MIF_REG_SHIFT) | 1731 (val & GEM_MIF_FRAME_DATA); 1732 1733 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1734 for (n = 0; n < 100; n++) { 1735 DELAY(1); 1736 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1737 if (v & GEM_MIF_FRAME_TA0) 1738 return; 1739 } 1740 1741 printf("%s: mii_write timeout\n", sc->sc_dev.dv_xname); 1742 } 1743 1744 static void 1745 gem_mii_statchg(dev) 1746 struct device *dev; 1747 { 1748 struct gem_softc *sc = (void *)dev; 1749 #ifdef GEM_DEBUG 1750 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1751 #endif 1752 bus_space_tag_t t = sc->sc_bustag; 1753 bus_space_handle_t mac = sc->sc_h; 1754 u_int32_t v; 1755 1756 #ifdef GEM_DEBUG 1757 if (sc->sc_debug) 1758 printf("gem_mii_statchg: status change: phy = %d\n", 1759 sc->sc_phys[instance];); 1760 #endif 1761 1762 1763 /* Set tx full duplex options */ 1764 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0); 1765 delay(10000); /* reg must be cleared and delay before changing. */ 1766 v = GEM_MAC_TX_ENA_IPG0|GEM_MAC_TX_NGU|GEM_MAC_TX_NGU_LIMIT| 1767 GEM_MAC_TX_ENABLE; 1768 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) { 1769 v |= GEM_MAC_TX_IGN_CARRIER|GEM_MAC_TX_IGN_COLLIS; 1770 } 1771 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, v); 1772 1773 /* XIF Configuration */ 1774 /* We should really calculate all this rather than rely on defaults */ 1775 v = bus_space_read_4(t, mac, GEM_MAC_XIF_CONFIG); 1776 v = GEM_MAC_XIF_LINK_LED; 1777 v |= GEM_MAC_XIF_TX_MII_ENA; 1778 1779 /* If an external transceiver is connected, enable its MII drivers */ 1780 sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG); 1781 if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) { 1782 /* External MII needs echo disable if half duplex. */ 1783 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1784 /* turn on full duplex LED */ 1785 v |= GEM_MAC_XIF_FDPLX_LED; 1786 else 1787 /* half duplex -- disable echo */ 1788 v |= GEM_MAC_XIF_ECHO_DISABL; 1789 1790 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 1791 v |= GEM_MAC_XIF_GMII_MODE; 1792 else 1793 v &= ~GEM_MAC_XIF_GMII_MODE; 1794 } else 1795 /* Internal MII needs buf enable */ 1796 v |= GEM_MAC_XIF_MII_BUF_ENA; 1797 bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v); 1798 } 1799 1800 int 1801 gem_mediachange(ifp) 1802 struct ifnet *ifp; 1803 { 1804 struct gem_softc *sc = ifp->if_softc; 1805 1806 if (IFM_TYPE(sc->sc_media.ifm_media) != IFM_ETHER) 1807 return (EINVAL); 1808 1809 return (mii_mediachg(&sc->sc_mii)); 1810 } 1811 1812 void 1813 gem_mediastatus(ifp, ifmr) 1814 struct ifnet *ifp; 1815 struct ifmediareq *ifmr; 1816 { 1817 struct gem_softc *sc = ifp->if_softc; 1818 1819 if ((ifp->if_flags & IFF_UP) == 0) 1820 return; 1821 1822 mii_pollstat(&sc->sc_mii); 1823 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1824 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1825 } 1826 1827 int gem_ioctldebug = 0; 1828 /* 1829 * Process an ioctl request. 1830 */ 1831 int 1832 gem_ioctl(ifp, cmd, data) 1833 struct ifnet *ifp; 1834 u_long cmd; 1835 caddr_t data; 1836 { 1837 struct gem_softc *sc = ifp->if_softc; 1838 struct ifreq *ifr = (struct ifreq *)data; 1839 int s, error = 0; 1840 1841 s = splnet(); 1842 1843 switch (cmd) { 1844 case SIOCGIFMEDIA: 1845 case SIOCSIFMEDIA: 1846 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1847 break; 1848 1849 default: 1850 error = ether_ioctl(ifp, cmd, data); 1851 if (error == ENETRESET) { 1852 /* 1853 * Multicast list has changed; set the hardware filter 1854 * accordingly. 1855 */ 1856 if (gem_ioctldebug) printf("reset1\n"); 1857 gem_init(ifp); 1858 delay(50000); 1859 error = 0; 1860 } 1861 break; 1862 } 1863 1864 /* Try to get things going again */ 1865 if (ifp->if_flags & IFF_UP) { 1866 if (gem_ioctldebug) printf("start\n"); 1867 gem_start(ifp); 1868 } 1869 splx(s); 1870 return (error); 1871 } 1872 1873 1874 void 1875 gem_shutdown(arg) 1876 void *arg; 1877 { 1878 struct gem_softc *sc = (struct gem_softc *)arg; 1879 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1880 1881 gem_stop(ifp, 1); 1882 } 1883 1884 /* 1885 * Set up the logical address filter. 1886 */ 1887 void 1888 gem_setladrf(sc) 1889 struct gem_softc *sc; 1890 { 1891 struct ethercom *ec = &sc->sc_ethercom; 1892 struct ifnet *ifp = &ec->ec_if; 1893 struct ether_multi *enm; 1894 struct ether_multistep step; 1895 bus_space_tag_t t = sc->sc_bustag; 1896 bus_space_handle_t h = sc->sc_h; 1897 u_int32_t crc; 1898 u_int32_t hash[16]; 1899 u_int32_t v; 1900 int i; 1901 1902 /* Get current RX configuration */ 1903 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 1904 1905 /* 1906 * Turn off promiscuous mode, promiscuous group mode (all multicast), 1907 * and hash filter. Depending on the case, the right bit will be 1908 * enabled. 1909 */ 1910 v &= ~(GEM_MAC_RX_PROMISCUOUS|GEM_MAC_RX_HASH_FILTER| 1911 GEM_MAC_RX_PROMISC_GRP); 1912 1913 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1914 /* Turn on promiscuous mode */ 1915 v |= GEM_MAC_RX_PROMISCUOUS; 1916 ifp->if_flags |= IFF_ALLMULTI; 1917 goto chipit; 1918 } 1919 1920 /* 1921 * Set up multicast address filter by passing all multicast addresses 1922 * through a crc generator, and then using the high order 8 bits as an 1923 * index into the 256 bit logical address filter. The high order 4 1924 * bits select the word, while the other 4 bits select the bit within 1925 * the word (where bit 0 is the MSB). 1926 */ 1927 1928 /* Clear hash table */ 1929 memset(hash, 0, sizeof(hash)); 1930 1931 ETHER_FIRST_MULTI(step, ec, enm); 1932 while (enm != NULL) { 1933 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1934 /* 1935 * We must listen to a range of multicast addresses. 1936 * For now, just accept all multicasts, rather than 1937 * trying to set only those filter bits needed to match 1938 * the range. (At this time, the only use of address 1939 * ranges is for IP multicast routing, for which the 1940 * range is big enough to require all bits set.) 1941 * XXX use the addr filter for this 1942 */ 1943 ifp->if_flags |= IFF_ALLMULTI; 1944 v |= GEM_MAC_RX_PROMISC_GRP; 1945 goto chipit; 1946 } 1947 1948 /* Get the LE CRC32 of the address */ 1949 crc = ether_crc32_le(enm->enm_addrlo, sizeof(enm->enm_addrlo)); 1950 1951 /* Just want the 8 most significant bits. */ 1952 crc >>= 24; 1953 1954 /* Set the corresponding bit in the filter. */ 1955 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 1956 1957 ETHER_NEXT_MULTI(step, enm); 1958 } 1959 1960 v |= GEM_MAC_RX_HASH_FILTER; 1961 ifp->if_flags &= ~IFF_ALLMULTI; 1962 1963 /* Now load the hash table into the chip (if we are using it) */ 1964 for (i = 0; i < 16; i++) { 1965 bus_space_write_4(t, h, 1966 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1-GEM_MAC_HASH0), 1967 hash[i]); 1968 } 1969 1970 chipit: 1971 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 1972 } 1973 1974 #if notyet 1975 1976 /* 1977 * gem_power: 1978 * 1979 * Power management (suspend/resume) hook. 1980 */ 1981 void 1982 gem_power(why, arg) 1983 int why; 1984 void *arg; 1985 { 1986 struct gem_softc *sc = arg; 1987 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1988 int s; 1989 1990 s = splnet(); 1991 switch (why) { 1992 case PWR_SUSPEND: 1993 case PWR_STANDBY: 1994 gem_stop(ifp, 1); 1995 if (sc->sc_power != NULL) 1996 (*sc->sc_power)(sc, why); 1997 break; 1998 case PWR_RESUME: 1999 if (ifp->if_flags & IFF_UP) { 2000 if (sc->sc_power != NULL) 2001 (*sc->sc_power)(sc, why); 2002 gem_init(ifp); 2003 } 2004 break; 2005 case PWR_SOFTSUSPEND: 2006 case PWR_SOFTSTANDBY: 2007 case PWR_SOFTRESUME: 2008 break; 2009 } 2010 splx(s); 2011 } 2012 #endif 2013
Indexes created Tue Sep 23 07:09:52 GMT 2025