gem.c revision 1.28
1 /* $NetBSD: gem.c,v 1.28 2003/08/24 18:07:03 chs Exp $ */ 2 3 /* 4 * 5 * Copyright (C) 2001 Eduardo Horvath. 6 * All rights reserved. 7 * 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 */ 31 32 /* 33 * Driver for Sun GEM ethernet controllers. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: gem.c,v 1.28 2003/08/24 18:07:03 chs Exp $"); 38 39 #include "bpfilter.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/callout.h> 44 #include <sys/mbuf.h> 45 #include <sys/syslog.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #include <sys/socket.h> 49 #include <sys/ioctl.h> 50 #include <sys/errno.h> 51 #include <sys/device.h> 52 53 #include <machine/endian.h> 54 55 #include <uvm/uvm_extern.h> 56 57 #include <net/if.h> 58 #include <net/if_dl.h> 59 #include <net/if_media.h> 60 #include <net/if_ether.h> 61 62 #if NBPFILTER > 0 63 #include <net/bpf.h> 64 #endif 65 66 #include <machine/bus.h> 67 #include <machine/intr.h> 68 69 #include <dev/mii/mii.h> 70 #include <dev/mii/miivar.h> 71 #include <dev/mii/mii_bitbang.h> 72 73 #include <dev/ic/gemreg.h> 74 #include <dev/ic/gemvar.h> 75 76 #define TRIES 10000 77 78 void gem_start __P((struct ifnet *)); 79 void gem_stop __P((struct ifnet *, int)); 80 int gem_ioctl __P((struct ifnet *, u_long, caddr_t)); 81 void gem_tick __P((void *)); 82 void gem_watchdog __P((struct ifnet *)); 83 void gem_shutdown __P((void *)); 84 int gem_init __P((struct ifnet *)); 85 void gem_init_regs(struct gem_softc *sc); 86 static int gem_ringsize(int sz); 87 int gem_meminit __P((struct gem_softc *)); 88 void gem_mifinit __P((struct gem_softc *)); 89 void gem_reset __P((struct gem_softc *)); 90 int gem_reset_rx(struct gem_softc *sc); 91 int gem_reset_tx(struct gem_softc *sc); 92 int gem_disable_rx(struct gem_softc *sc); 93 int gem_disable_tx(struct gem_softc *sc); 94 void gem_rxdrain(struct gem_softc *sc); 95 int gem_add_rxbuf(struct gem_softc *sc, int idx); 96 void gem_setladrf __P((struct gem_softc *)); 97 98 /* MII methods & callbacks */ 99 static int gem_mii_readreg __P((struct device *, int, int)); 100 static void gem_mii_writereg __P((struct device *, int, int, int)); 101 static void gem_mii_statchg __P((struct device *)); 102 103 int gem_mediachange __P((struct ifnet *)); 104 void gem_mediastatus __P((struct ifnet *, struct ifmediareq *)); 105 106 struct mbuf *gem_get __P((struct gem_softc *, int, int)); 107 int gem_put __P((struct gem_softc *, int, struct mbuf *)); 108 void gem_read __P((struct gem_softc *, int, int)); 109 int gem_eint __P((struct gem_softc *, u_int)); 110 int gem_rint __P((struct gem_softc *)); 111 int gem_tint __P((struct gem_softc *)); 112 void gem_power __P((int, void *)); 113 114 #ifdef GEM_DEBUG 115 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 116 printf x 117 #else 118 #define DPRINTF(sc, x) /* nothing */ 119 #endif 120 121 122 /* 123 * gem_attach: 124 * 125 * Attach a Gem interface to the system. 126 */ 127 void 128 gem_attach(sc, enaddr) 129 struct gem_softc *sc; 130 const uint8_t *enaddr; 131 { 132 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 133 struct mii_data *mii = &sc->sc_mii; 134 struct mii_softc *child; 135 struct ifmedia_entry *ifm; 136 int i, error; 137 u_int32_t v; 138 139 /* Make sure the chip is stopped. */ 140 ifp->if_softc = sc; 141 gem_reset(sc); 142 143 /* 144 * Allocate the control data structures, and create and load the 145 * DMA map for it. 146 */ 147 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 148 sizeof(struct gem_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 149 1, &sc->sc_cdnseg, 0)) != 0) { 150 aprint_error( 151 "%s: unable to allocate control data, error = %d\n", 152 sc->sc_dev.dv_xname, error); 153 goto fail_0; 154 } 155 156 /* XXX should map this in with correct endianness */ 157 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg, 158 sizeof(struct gem_control_data), (caddr_t *)&sc->sc_control_data, 159 BUS_DMA_COHERENT)) != 0) { 160 aprint_error("%s: unable to map control data, error = %d\n", 161 sc->sc_dev.dv_xname, error); 162 goto fail_1; 163 } 164 165 if ((error = bus_dmamap_create(sc->sc_dmatag, 166 sizeof(struct gem_control_data), 1, 167 sizeof(struct gem_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 168 aprint_error("%s: unable to create control data DMA map, " 169 "error = %d\n", sc->sc_dev.dv_xname, error); 170 goto fail_2; 171 } 172 173 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 174 sc->sc_control_data, sizeof(struct gem_control_data), NULL, 175 0)) != 0) { 176 aprint_error( 177 "%s: unable to load control data DMA map, error = %d\n", 178 sc->sc_dev.dv_xname, error); 179 goto fail_3; 180 } 181 182 /* 183 * Initialize the transmit job descriptors. 184 */ 185 SIMPLEQ_INIT(&sc->sc_txfreeq); 186 SIMPLEQ_INIT(&sc->sc_txdirtyq); 187 188 /* 189 * Create the transmit buffer DMA maps. 190 */ 191 for (i = 0; i < GEM_TXQUEUELEN; i++) { 192 struct gem_txsoft *txs; 193 194 txs = &sc->sc_txsoft[i]; 195 txs->txs_mbuf = NULL; 196 if ((error = bus_dmamap_create(sc->sc_dmatag, 197 ETHER_MAX_LEN_JUMBO, GEM_NTXSEGS, 198 ETHER_MAX_LEN_JUMBO, 0, 0, 199 &txs->txs_dmamap)) != 0) { 200 aprint_error("%s: unable to create tx DMA map %d, " 201 "error = %d\n", sc->sc_dev.dv_xname, i, error); 202 goto fail_4; 203 } 204 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 205 } 206 207 /* 208 * Create the receive buffer DMA maps. 209 */ 210 for (i = 0; i < GEM_NRXDESC; i++) { 211 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, 212 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 213 aprint_error("%s: unable to create rx DMA map %d, " 214 "error = %d\n", sc->sc_dev.dv_xname, i, error); 215 goto fail_5; 216 } 217 sc->sc_rxsoft[i].rxs_mbuf = NULL; 218 } 219 220 /* 221 * From this point forward, the attachment cannot fail. A failure 222 * before this point releases all resources that may have been 223 * allocated. 224 */ 225 226 /* Announce ourselves. */ 227 aprint_normal("%s: Ethernet address %s", sc->sc_dev.dv_xname, 228 ether_sprintf(enaddr)); 229 230 /* Get RX FIFO size */ 231 sc->sc_rxfifosize = 64 * 232 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_FIFO_SIZE); 233 aprint_normal(", %uKB RX fifo", sc->sc_rxfifosize / 1024); 234 235 /* Get TX FIFO size */ 236 v = bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_FIFO_SIZE); 237 aprint_normal(", %uKB TX fifo\n", v / 16); 238 239 /* Initialize ifnet structure. */ 240 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 241 ifp->if_softc = sc; 242 ifp->if_flags = 243 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 244 ifp->if_start = gem_start; 245 ifp->if_ioctl = gem_ioctl; 246 ifp->if_watchdog = gem_watchdog; 247 ifp->if_stop = gem_stop; 248 ifp->if_init = gem_init; 249 IFQ_SET_READY(&ifp->if_snd); 250 251 /* Initialize ifmedia structures and MII info */ 252 mii->mii_ifp = ifp; 253 mii->mii_readreg = gem_mii_readreg; 254 mii->mii_writereg = gem_mii_writereg; 255 mii->mii_statchg = gem_mii_statchg; 256 257 ifmedia_init(&mii->mii_media, IFM_IMASK, gem_mediachange, gem_mediastatus); 258 259 gem_mifinit(sc); 260 261 mii_attach(&sc->sc_dev, mii, 0xffffffff, 262 MII_PHY_ANY, MII_OFFSET_ANY, MIIF_FORCEANEG); 263 264 child = LIST_FIRST(&mii->mii_phys); 265 if (child == NULL) { 266 /* No PHY attached */ 267 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 268 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 269 } else { 270 /* 271 * Walk along the list of attached MII devices and 272 * establish an `MII instance' to `phy number' 273 * mapping. We'll use this mapping in media change 274 * requests to determine which phy to use to program 275 * the MIF configuration register. 276 */ 277 for (; child != NULL; child = LIST_NEXT(child, mii_list)) { 278 /* 279 * Note: we support just two PHYs: the built-in 280 * internal device and an external on the MII 281 * connector. 282 */ 283 if (child->mii_phy > 1 || child->mii_inst > 1) { 284 aprint_error( 285 "%s: cannot accomodate MII device %s" 286 " at phy %d, instance %d\n", 287 sc->sc_dev.dv_xname, 288 child->mii_dev.dv_xname, 289 child->mii_phy, child->mii_inst); 290 continue; 291 } 292 293 sc->sc_phys[child->mii_inst] = child->mii_phy; 294 295 } 296 297 /* 298 * Now select and activate the PHY we will use. 299 * 300 * The order of preference is External (MDI1), 301 * Internal (MDI0), Serial Link (no MII). 302 */ 303 if (sc->sc_phys[1]) { 304 #ifdef DEBUG 305 aprint_debug("using external phy\n"); 306 #endif 307 sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL; 308 } else { 309 #ifdef DEBUG 310 aprint_debug("using internal phy\n"); 311 #endif 312 sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL; 313 } 314 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_MIF_CONFIG, 315 sc->sc_mif_config); 316 317 /* 318 * XXX - we can really do the following ONLY if the 319 * phy indeed has the auto negotiation capability!! 320 */ 321 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO); 322 } 323 324 /* 325 * If we support GigE media, we support jumbo frames too. 326 * Unless we are Apple. 327 */ 328 TAILQ_FOREACH(ifm, &sc->sc_media.ifm_list, ifm_list) { 329 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_T || 330 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_SX || 331 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_LX || 332 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_CX) { 333 if (sc->sc_variant != GEM_APPLE_GMAC) 334 sc->sc_ethercom.ec_capabilities 335 |= ETHERCAP_JUMBO_MTU; 336 337 sc->sc_flags |= GEM_GIGABIT; 338 break; 339 } 340 } 341 342 /* claim 802.1q capability */ 343 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 344 345 /* Attach the interface. */ 346 if_attach(ifp); 347 ether_ifattach(ifp, enaddr); 348 349 sc->sc_sh = shutdownhook_establish(gem_shutdown, sc); 350 if (sc->sc_sh == NULL) 351 panic("gem_config: can't establish shutdownhook"); 352 353 #if NRND > 0 354 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 355 RND_TYPE_NET, 0); 356 #endif 357 358 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, 359 NULL, sc->sc_dev.dv_xname, "interrupts"); 360 #ifdef GEM_COUNTERS 361 evcnt_attach_dynamic(&sc->sc_ev_txint, EVCNT_TYPE_INTR, 362 &sc->sc_ev_intr, sc->sc_dev.dv_xname, "tx interrupts"); 363 evcnt_attach_dynamic(&sc->sc_ev_rxint, EVCNT_TYPE_INTR, 364 &sc->sc_ev_intr, sc->sc_dev.dv_xname, "rx interrupts"); 365 evcnt_attach_dynamic(&sc->sc_ev_rxfull, EVCNT_TYPE_INTR, 366 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx ring full"); 367 evcnt_attach_dynamic(&sc->sc_ev_rxnobuf, EVCNT_TYPE_INTR, 368 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx malloc failure"); 369 evcnt_attach_dynamic(&sc->sc_ev_rxhist[0], EVCNT_TYPE_INTR, 370 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 0desc"); 371 evcnt_attach_dynamic(&sc->sc_ev_rxhist[1], EVCNT_TYPE_INTR, 372 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 1desc"); 373 evcnt_attach_dynamic(&sc->sc_ev_rxhist[2], EVCNT_TYPE_INTR, 374 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 2desc"); 375 evcnt_attach_dynamic(&sc->sc_ev_rxhist[3], EVCNT_TYPE_INTR, 376 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 3desc"); 377 evcnt_attach_dynamic(&sc->sc_ev_rxhist[4], EVCNT_TYPE_INTR, 378 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >3desc"); 379 evcnt_attach_dynamic(&sc->sc_ev_rxhist[5], EVCNT_TYPE_INTR, 380 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >7desc"); 381 evcnt_attach_dynamic(&sc->sc_ev_rxhist[6], EVCNT_TYPE_INTR, 382 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >15desc"); 383 evcnt_attach_dynamic(&sc->sc_ev_rxhist[7], EVCNT_TYPE_INTR, 384 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >31desc"); 385 evcnt_attach_dynamic(&sc->sc_ev_rxhist[8], EVCNT_TYPE_INTR, 386 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >63desc"); 387 #endif 388 389 #if notyet 390 /* 391 * Add a suspend hook to make sure we come back up after a 392 * resume. 393 */ 394 sc->sc_powerhook = powerhook_establish(gem_power, sc); 395 if (sc->sc_powerhook == NULL) 396 aprint_error("%s: WARNING: unable to establish power hook\n", 397 sc->sc_dev.dv_xname); 398 #endif 399 400 callout_init(&sc->sc_tick_ch); 401 return; 402 403 /* 404 * Free any resources we've allocated during the failed attach 405 * attempt. Do this in reverse order and fall through. 406 */ 407 fail_5: 408 for (i = 0; i < GEM_NRXDESC; i++) { 409 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 410 bus_dmamap_destroy(sc->sc_dmatag, 411 sc->sc_rxsoft[i].rxs_dmamap); 412 } 413 fail_4: 414 for (i = 0; i < GEM_TXQUEUELEN; i++) { 415 if (sc->sc_txsoft[i].txs_dmamap != NULL) 416 bus_dmamap_destroy(sc->sc_dmatag, 417 sc->sc_txsoft[i].txs_dmamap); 418 } 419 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 420 fail_3: 421 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 422 fail_2: 423 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)sc->sc_control_data, 424 sizeof(struct gem_control_data)); 425 fail_1: 426 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 427 fail_0: 428 return; 429 } 430 431 432 void 433 gem_tick(arg) 434 void *arg; 435 { 436 struct gem_softc *sc = arg; 437 int s; 438 439 s = splnet(); 440 mii_tick(&sc->sc_mii); 441 splx(s); 442 443 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 444 445 } 446 447 void 448 gem_reset(sc) 449 struct gem_softc *sc; 450 { 451 bus_space_tag_t t = sc->sc_bustag; 452 bus_space_handle_t h = sc->sc_h; 453 int i; 454 int s; 455 456 s = splnet(); 457 DPRINTF(sc, ("%s: gem_reset\n", sc->sc_dev.dv_xname)); 458 gem_reset_rx(sc); 459 gem_reset_tx(sc); 460 461 /* Do a full reset */ 462 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX|GEM_RESET_TX); 463 for (i=TRIES; i--; delay(100)) 464 if ((bus_space_read_4(t, h, GEM_RESET) & 465 (GEM_RESET_RX|GEM_RESET_TX)) == 0) 466 break; 467 if ((bus_space_read_4(t, h, GEM_RESET) & 468 (GEM_RESET_RX|GEM_RESET_TX)) != 0) { 469 printf("%s: cannot reset device\n", 470 sc->sc_dev.dv_xname); 471 } 472 splx(s); 473 } 474 475 476 /* 477 * gem_rxdrain: 478 * 479 * Drain the receive queue. 480 */ 481 void 482 gem_rxdrain(struct gem_softc *sc) 483 { 484 struct gem_rxsoft *rxs; 485 int i; 486 487 for (i = 0; i < GEM_NRXDESC; i++) { 488 rxs = &sc->sc_rxsoft[i]; 489 if (rxs->rxs_mbuf != NULL) { 490 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 491 m_freem(rxs->rxs_mbuf); 492 rxs->rxs_mbuf = NULL; 493 } 494 } 495 } 496 497 /* 498 * Reset the whole thing. 499 */ 500 void 501 gem_stop(struct ifnet *ifp, int disable) 502 { 503 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 504 struct gem_txsoft *txs; 505 506 DPRINTF(sc, ("%s: gem_stop\n", sc->sc_dev.dv_xname)); 507 508 callout_stop(&sc->sc_tick_ch); 509 mii_down(&sc->sc_mii); 510 511 /* XXX - Should we reset these instead? */ 512 gem_disable_rx(sc); 513 gem_disable_tx(sc); 514 515 /* 516 * Release any queued transmit buffers. 517 */ 518 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 519 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 520 if (txs->txs_mbuf != NULL) { 521 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 522 m_freem(txs->txs_mbuf); 523 txs->txs_mbuf = NULL; 524 } 525 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 526 } 527 528 if (disable) { 529 gem_rxdrain(sc); 530 } 531 532 /* 533 * Mark the interface down and cancel the watchdog timer. 534 */ 535 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 536 ifp->if_timer = 0; 537 } 538 539 540 /* 541 * Reset the receiver 542 */ 543 int 544 gem_reset_rx(struct gem_softc *sc) 545 { 546 bus_space_tag_t t = sc->sc_bustag; 547 bus_space_handle_t h = sc->sc_h; 548 int i; 549 550 551 /* 552 * Resetting while DMA is in progress can cause a bus hang, so we 553 * disable DMA first. 554 */ 555 gem_disable_rx(sc); 556 bus_space_write_4(t, h, GEM_RX_CONFIG, 0); 557 /* Wait till it finishes */ 558 for (i=TRIES; i--; delay(100)) 559 if ((bus_space_read_4(t, h, GEM_RX_CONFIG) & 1) == 0) 560 break; 561 if ((bus_space_read_4(t, h, GEM_RX_CONFIG) & 1) != 0) 562 printf("%s: cannot disable read DMA\n", 563 sc->sc_dev.dv_xname); 564 565 /* Wait 5ms extra. */ 566 delay(5000); 567 568 /* Finally, reset the ERX */ 569 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX); 570 /* Wait till it finishes */ 571 for (i=TRIES; i--; delay(100)) 572 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_RX) == 0) 573 break; 574 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_RX) != 0) { 575 printf("%s: cannot reset receiver\n", 576 sc->sc_dev.dv_xname); 577 return (1); 578 } 579 return (0); 580 } 581 582 583 /* 584 * Reset the transmitter 585 */ 586 int 587 gem_reset_tx(struct gem_softc *sc) 588 { 589 bus_space_tag_t t = sc->sc_bustag; 590 bus_space_handle_t h = sc->sc_h; 591 int i; 592 593 /* 594 * Resetting while DMA is in progress can cause a bus hang, so we 595 * disable DMA first. 596 */ 597 gem_disable_tx(sc); 598 bus_space_write_4(t, h, GEM_TX_CONFIG, 0); 599 /* Wait till it finishes */ 600 for (i=TRIES; i--; delay(100)) 601 if ((bus_space_read_4(t, h, GEM_TX_CONFIG) & 1) == 0) 602 break; 603 if ((bus_space_read_4(t, h, GEM_TX_CONFIG) & 1) != 0) 604 printf("%s: cannot disable read DMA\n", 605 sc->sc_dev.dv_xname); 606 607 /* Wait 5ms extra. */ 608 delay(5000); 609 610 /* Finally, reset the ETX */ 611 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_TX); 612 /* Wait till it finishes */ 613 for (i=TRIES; i--; delay(100)) 614 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_TX) == 0) 615 break; 616 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_TX) != 0) { 617 printf("%s: cannot reset receiver\n", 618 sc->sc_dev.dv_xname); 619 return (1); 620 } 621 return (0); 622 } 623 624 /* 625 * disable receiver. 626 */ 627 int 628 gem_disable_rx(struct gem_softc *sc) 629 { 630 bus_space_tag_t t = sc->sc_bustag; 631 bus_space_handle_t h = sc->sc_h; 632 int i; 633 u_int32_t cfg; 634 635 /* Flip the enable bit */ 636 cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 637 cfg &= ~GEM_MAC_RX_ENABLE; 638 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg); 639 640 /* Wait for it to finish */ 641 for (i=TRIES; i--; delay(100)) 642 if ((bus_space_read_4(t, h, GEM_MAC_RX_CONFIG) & 643 GEM_MAC_RX_ENABLE) == 0) 644 return (0); 645 return (1); 646 } 647 648 /* 649 * disable transmitter. 650 */ 651 int 652 gem_disable_tx(struct gem_softc *sc) 653 { 654 bus_space_tag_t t = sc->sc_bustag; 655 bus_space_handle_t h = sc->sc_h; 656 int i; 657 u_int32_t cfg; 658 659 /* Flip the enable bit */ 660 cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG); 661 cfg &= ~GEM_MAC_TX_ENABLE; 662 bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg); 663 664 /* Wait for it to finish */ 665 for (i=TRIES; i--; delay(100)) 666 if ((bus_space_read_4(t, h, GEM_MAC_TX_CONFIG) & 667 GEM_MAC_TX_ENABLE) == 0) 668 return (0); 669 return (1); 670 } 671 672 /* 673 * Initialize interface. 674 */ 675 int 676 gem_meminit(struct gem_softc *sc) 677 { 678 struct gem_rxsoft *rxs; 679 int i, error; 680 681 /* 682 * Initialize the transmit descriptor ring. 683 */ 684 memset((void *)sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 685 for (i = 0; i < GEM_NTXDESC; i++) { 686 sc->sc_txdescs[i].gd_flags = 0; 687 sc->sc_txdescs[i].gd_addr = 0; 688 } 689 GEM_CDTXSYNC(sc, 0, GEM_NTXDESC, 690 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 691 sc->sc_txfree = GEM_NTXDESC-1; 692 sc->sc_txnext = 0; 693 sc->sc_txwin = 0; 694 695 /* 696 * Initialize the receive descriptor and receive job 697 * descriptor rings. 698 */ 699 for (i = 0; i < GEM_NRXDESC; i++) { 700 rxs = &sc->sc_rxsoft[i]; 701 if (rxs->rxs_mbuf == NULL) { 702 if ((error = gem_add_rxbuf(sc, i)) != 0) { 703 printf("%s: unable to allocate or map rx " 704 "buffer %d, error = %d\n", 705 sc->sc_dev.dv_xname, i, error); 706 /* 707 * XXX Should attempt to run with fewer receive 708 * XXX buffers instead of just failing. 709 */ 710 gem_rxdrain(sc); 711 return (1); 712 } 713 } else 714 GEM_INIT_RXDESC(sc, i); 715 } 716 sc->sc_rxptr = 0; 717 718 return (0); 719 } 720 721 static int 722 gem_ringsize(int sz) 723 { 724 int v; 725 726 switch (sz) { 727 case 32: 728 v = GEM_RING_SZ_32; 729 break; 730 case 64: 731 v = GEM_RING_SZ_64; 732 break; 733 case 128: 734 v = GEM_RING_SZ_128; 735 break; 736 case 256: 737 v = GEM_RING_SZ_256; 738 break; 739 case 512: 740 v = GEM_RING_SZ_512; 741 break; 742 case 1024: 743 v = GEM_RING_SZ_1024; 744 break; 745 case 2048: 746 v = GEM_RING_SZ_2048; 747 break; 748 case 4096: 749 v = GEM_RING_SZ_4096; 750 break; 751 case 8192: 752 v = GEM_RING_SZ_8192; 753 break; 754 default: 755 printf("gem: invalid Receive Descriptor ring size\n"); 756 break; 757 } 758 return (v); 759 } 760 761 /* 762 * Initialization of interface; set up initialization block 763 * and transmit/receive descriptor rings. 764 */ 765 int 766 gem_init(struct ifnet *ifp) 767 { 768 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 769 bus_space_tag_t t = sc->sc_bustag; 770 bus_space_handle_t h = sc->sc_h; 771 int s; 772 u_int max_frame_size; 773 u_int32_t v; 774 775 s = splnet(); 776 777 DPRINTF(sc, ("%s: gem_init: calling stop\n", sc->sc_dev.dv_xname)); 778 /* 779 * Initialization sequence. The numbered steps below correspond 780 * to the sequence outlined in section 6.3.5.1 in the Ethernet 781 * Channel Engine manual (part of the PCIO manual). 782 * See also the STP2002-STQ document from Sun Microsystems. 783 */ 784 785 /* step 1 & 2. Reset the Ethernet Channel */ 786 gem_stop(ifp, 0); 787 gem_reset(sc); 788 DPRINTF(sc, ("%s: gem_init: restarting\n", sc->sc_dev.dv_xname)); 789 790 /* Re-initialize the MIF */ 791 gem_mifinit(sc); 792 793 /* Call MI reset function if any */ 794 if (sc->sc_hwreset) 795 (*sc->sc_hwreset)(sc); 796 797 /* step 3. Setup data structures in host memory */ 798 gem_meminit(sc); 799 800 /* step 4. TX MAC registers & counters */ 801 gem_init_regs(sc); 802 max_frame_size = max(sc->sc_ethercom.ec_if.if_mtu, ETHERMTU); 803 max_frame_size += ETHER_HDR_LEN + ETHER_CRC_LEN; 804 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 805 max_frame_size += ETHER_VLAN_ENCAP_LEN; 806 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 807 max_frame_size|/* burst size */(0x2000<<16)); 808 809 /* step 5. RX MAC registers & counters */ 810 gem_setladrf(sc); 811 812 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 813 /* NOTE: we use only 32-bit DMA addresses here. */ 814 bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 0); 815 bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 816 817 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0); 818 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 819 820 /* step 8. Global Configuration & Interrupt Mask */ 821 bus_space_write_4(t, h, GEM_INTMASK, 822 ~(GEM_INTR_TX_INTME| 823 GEM_INTR_TX_EMPTY| 824 GEM_INTR_RX_DONE|GEM_INTR_RX_NOBUF| 825 GEM_INTR_RX_TAG_ERR|GEM_INTR_PCS| 826 GEM_INTR_MAC_CONTROL|GEM_INTR_MIF| 827 GEM_INTR_BERR)); 828 bus_space_write_4(t, h, GEM_MAC_RX_MASK, 829 GEM_MAC_RX_DONE|GEM_MAC_RX_FRAME_CNT); 830 bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXXX */ 831 bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 0); /* XXXX */ 832 833 /* step 9. ETX Configuration: use mostly default values */ 834 835 /* Enable DMA */ 836 v = gem_ringsize(GEM_NTXDESC /*XXX*/); 837 bus_space_write_4(t, h, GEM_TX_CONFIG, 838 v|GEM_TX_CONFIG_TXDMA_EN| 839 ((0x400<<10)&GEM_TX_CONFIG_TXFIFO_TH)); 840 bus_space_write_4(t, h, GEM_TX_KICK, sc->sc_txnext); 841 842 /* step 10. ERX Configuration */ 843 844 /* Encode Receive Descriptor ring size: four possible values */ 845 v = gem_ringsize(GEM_NRXDESC /*XXX*/); 846 847 /* Enable DMA */ 848 bus_space_write_4(t, h, GEM_RX_CONFIG, 849 v|(GEM_THRSH_1024<<GEM_RX_CONFIG_FIFO_THRS_SHIFT)| 850 (2<<GEM_RX_CONFIG_FBOFF_SHFT)|GEM_RX_CONFIG_RXDMA_EN| 851 (0<<GEM_RX_CONFIG_CXM_START_SHFT)); 852 /* 853 * The following value is for an OFF Threshold of about 3/4 full 854 * and an ON Threshold of 1/4 full. 855 */ 856 bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH, 857 (3 * sc->sc_rxfifosize / 256) | 858 ( (sc->sc_rxfifosize / 256) << 12)); 859 bus_space_write_4(t, h, GEM_RX_BLANKING, (6<<12)|6); 860 861 /* step 11. Configure Media */ 862 mii_mediachg(&sc->sc_mii); 863 864 /* XXXX Serial link needs a whole different setup. */ 865 866 867 /* step 12. RX_MAC Configuration Register */ 868 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 869 v |= GEM_MAC_RX_ENABLE; 870 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 871 872 /* step 14. Issue Transmit Pending command */ 873 874 /* Call MI initialization function if any */ 875 if (sc->sc_hwinit) 876 (*sc->sc_hwinit)(sc); 877 878 879 /* step 15. Give the reciever a swift kick */ 880 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4); 881 882 /* Start the one second timer. */ 883 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 884 885 ifp->if_flags |= IFF_RUNNING; 886 ifp->if_flags &= ~IFF_OACTIVE; 887 ifp->if_timer = 0; 888 splx(s); 889 890 return (0); 891 } 892 893 void 894 gem_init_regs(struct gem_softc *sc) 895 { 896 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 897 bus_space_tag_t t = sc->sc_bustag; 898 bus_space_handle_t h = sc->sc_h; 899 const u_char *laddr = LLADDR(ifp->if_sadl); 900 u_int32_t v; 901 902 /* These regs are not cleared on reset */ 903 if (!sc->sc_inited) { 904 905 /* Wooo. Magic values. */ 906 bus_space_write_4(t, h, GEM_MAC_IPG0, 0); 907 bus_space_write_4(t, h, GEM_MAC_IPG1, 8); 908 bus_space_write_4(t, h, GEM_MAC_IPG2, 4); 909 910 bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 911 /* Max frame and max burst size */ 912 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 913 ETHER_MAX_LEN | (0x2000<<16)); 914 915 bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x7); 916 bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x4); 917 bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10); 918 /* Dunno.... */ 919 bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088); 920 bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED, 921 ((laddr[5]<<8)|laddr[4])&0x3ff); 922 923 /* Secondary MAC addr set to 0:0:0:0:0:0 */ 924 bus_space_write_4(t, h, GEM_MAC_ADDR3, 0); 925 bus_space_write_4(t, h, GEM_MAC_ADDR4, 0); 926 bus_space_write_4(t, h, GEM_MAC_ADDR5, 0); 927 928 /* MAC control addr set to 01:80:c2:00:00:01 */ 929 bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001); 930 bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200); 931 bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180); 932 933 /* MAC filter addr set to 0:0:0:0:0:0 */ 934 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0); 935 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0); 936 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0); 937 938 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0); 939 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0); 940 941 sc->sc_inited = 1; 942 } 943 944 /* Counters need to be zeroed */ 945 bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0); 946 bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0); 947 bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0); 948 bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0); 949 bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0); 950 bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0); 951 bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0); 952 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 953 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 954 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 955 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 956 957 /* Un-pause stuff */ 958 #if 0 959 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); 960 #else 961 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0); 962 #endif 963 964 /* 965 * Set the station address. 966 */ 967 bus_space_write_4(t, h, GEM_MAC_ADDR0, (laddr[4]<<8)|laddr[5]); 968 bus_space_write_4(t, h, GEM_MAC_ADDR1, (laddr[2]<<8)|laddr[3]); 969 bus_space_write_4(t, h, GEM_MAC_ADDR2, (laddr[0]<<8)|laddr[1]); 970 971 #if 0 972 if (sc->sc_variant != APPLE_GMAC) 973 return; 974 #endif 975 976 /* 977 * Enable MII outputs. Enable GMII if there is a gigabit PHY. 978 */ 979 sc->sc_mif_config = bus_space_read_4(t, h, GEM_MIF_CONFIG); 980 v = GEM_MAC_XIF_TX_MII_ENA; 981 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) { 982 v |= GEM_MAC_XIF_FDPLX_LED; 983 if (sc->sc_flags & GEM_GIGABIT) 984 v |= GEM_MAC_XIF_GMII_MODE; 985 } 986 bus_space_write_4(t, h, GEM_MAC_XIF_CONFIG, v); 987 } 988 989 void 990 gem_start(ifp) 991 struct ifnet *ifp; 992 { 993 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 994 struct mbuf *m0, *m; 995 struct gem_txsoft *txs, *last_txs; 996 bus_dmamap_t dmamap; 997 int error, firsttx, nexttx, lasttx, ofree, seg; 998 999 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1000 return; 1001 1002 /* 1003 * Remember the previous number of free descriptors and 1004 * the first descriptor we'll use. 1005 */ 1006 ofree = sc->sc_txfree; 1007 firsttx = sc->sc_txnext; 1008 1009 DPRINTF(sc, ("%s: gem_start: txfree %d, txnext %d\n", 1010 sc->sc_dev.dv_xname, ofree, firsttx)); 1011 1012 /* 1013 * Loop through the send queue, setting up transmit descriptors 1014 * until we drain the queue, or use up all available transmit 1015 * descriptors. 1016 */ 1017 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 1018 sc->sc_txfree != 0) { 1019 /* 1020 * Grab a packet off the queue. 1021 */ 1022 IFQ_POLL(&ifp->if_snd, m0); 1023 if (m0 == NULL) 1024 break; 1025 m = NULL; 1026 1027 dmamap = txs->txs_dmamap; 1028 1029 /* 1030 * Load the DMA map. If this fails, the packet either 1031 * didn't fit in the alloted number of segments, or we were 1032 * short on resources. In this case, we'll copy and try 1033 * again. 1034 */ 1035 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m0, 1036 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1037 if (m0->m_pkthdr.len > MCLBYTES) { 1038 printf("%s: unable to allocate jumbo Tx " 1039 "cluster\n", sc->sc_dev.dv_xname); 1040 IFQ_DEQUEUE(&ifp->if_snd, m0); 1041 m_freem(m0); 1042 continue; 1043 } 1044 MGETHDR(m, M_DONTWAIT, MT_DATA); 1045 if (m == NULL) { 1046 printf("%s: unable to allocate Tx mbuf\n", 1047 sc->sc_dev.dv_xname); 1048 break; 1049 } 1050 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1051 if (m0->m_pkthdr.len > MHLEN) { 1052 MCLGET(m, M_DONTWAIT); 1053 if ((m->m_flags & M_EXT) == 0) { 1054 printf("%s: unable to allocate Tx " 1055 "cluster\n", sc->sc_dev.dv_xname); 1056 m_freem(m); 1057 break; 1058 } 1059 } 1060 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 1061 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1062 error = bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, 1063 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1064 if (error) { 1065 printf("%s: unable to load Tx buffer, " 1066 "error = %d\n", sc->sc_dev.dv_xname, error); 1067 break; 1068 } 1069 } 1070 1071 /* 1072 * Ensure we have enough descriptors free to describe 1073 * the packet. 1074 */ 1075 if (dmamap->dm_nsegs > sc->sc_txfree) { 1076 /* 1077 * Not enough free descriptors to transmit this 1078 * packet. We haven't committed to anything yet, 1079 * so just unload the DMA map, put the packet 1080 * back on the queue, and punt. Notify the upper 1081 * layer that there are no more slots left. 1082 * 1083 * XXX We could allocate an mbuf and copy, but 1084 * XXX it is worth it? 1085 */ 1086 ifp->if_flags |= IFF_OACTIVE; 1087 bus_dmamap_unload(sc->sc_dmatag, dmamap); 1088 if (m != NULL) 1089 m_freem(m); 1090 break; 1091 } 1092 1093 IFQ_DEQUEUE(&ifp->if_snd, m0); 1094 if (m != NULL) { 1095 m_freem(m0); 1096 m0 = m; 1097 } 1098 1099 /* 1100 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1101 */ 1102 1103 /* Sync the DMA map. */ 1104 bus_dmamap_sync(sc->sc_dmatag, dmamap, 0, dmamap->dm_mapsize, 1105 BUS_DMASYNC_PREWRITE); 1106 1107 /* 1108 * Initialize the transmit descriptors. 1109 */ 1110 for (nexttx = sc->sc_txnext, seg = 0; 1111 seg < dmamap->dm_nsegs; 1112 seg++, nexttx = GEM_NEXTTX(nexttx)) { 1113 uint64_t flags; 1114 1115 /* 1116 * If this is the first descriptor we're 1117 * enqueueing, set the start of packet flag, 1118 * and the checksum stuff if we want the hardware 1119 * to do it. 1120 */ 1121 sc->sc_txdescs[nexttx].gd_addr = 1122 GEM_DMA_WRITE(sc, dmamap->dm_segs[seg].ds_addr); 1123 flags = dmamap->dm_segs[seg].ds_len & GEM_TD_BUFSIZE; 1124 if (nexttx == firsttx) { 1125 flags |= GEM_TD_START_OF_PACKET; 1126 if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) { 1127 sc->sc_txwin = 0; 1128 flags |= GEM_TD_INTERRUPT_ME; 1129 } 1130 } 1131 if (seg == dmamap->dm_nsegs - 1) { 1132 flags |= GEM_TD_END_OF_PACKET; 1133 } 1134 sc->sc_txdescs[nexttx].gd_flags = 1135 GEM_DMA_WRITE(sc, flags); 1136 lasttx = nexttx; 1137 } 1138 1139 #ifdef GEM_DEBUG 1140 if (ifp->if_flags & IFF_DEBUG) { 1141 printf(" gem_start %p transmit chain:\n", txs); 1142 for (seg = sc->sc_txnext;; seg = GEM_NEXTTX(seg)) { 1143 printf("descriptor %d:\t", seg); 1144 printf("gd_flags: 0x%016llx\t", (long long) 1145 GEM_DMA_READ(sc, sc->sc_txdescs[seg].gd_flags)); 1146 printf("gd_addr: 0x%016llx\n", (long long) 1147 GEM_DMA_READ(sc, sc->sc_txdescs[seg].gd_addr)); 1148 if (seg == lasttx) 1149 break; 1150 } 1151 } 1152 #endif 1153 1154 /* Sync the descriptors we're using. */ 1155 GEM_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1156 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1157 1158 /* 1159 * Store a pointer to the packet so we can free it later, 1160 * and remember what txdirty will be once the packet is 1161 * done. 1162 */ 1163 txs->txs_mbuf = m0; 1164 txs->txs_firstdesc = sc->sc_txnext; 1165 txs->txs_lastdesc = lasttx; 1166 txs->txs_ndescs = dmamap->dm_nsegs; 1167 1168 /* Advance the tx pointer. */ 1169 sc->sc_txfree -= dmamap->dm_nsegs; 1170 sc->sc_txnext = nexttx; 1171 1172 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1173 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1174 1175 last_txs = txs; 1176 1177 #if NBPFILTER > 0 1178 /* 1179 * Pass the packet to any BPF listeners. 1180 */ 1181 if (ifp->if_bpf) 1182 bpf_mtap(ifp->if_bpf, m0); 1183 #endif /* NBPFILTER > 0 */ 1184 } 1185 1186 if (txs == NULL || sc->sc_txfree == 0) { 1187 /* No more slots left; notify upper layer. */ 1188 ifp->if_flags |= IFF_OACTIVE; 1189 } 1190 1191 if (sc->sc_txfree != ofree) { 1192 DPRINTF(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 1193 sc->sc_dev.dv_xname, lasttx, firsttx)); 1194 /* 1195 * The entire packet chain is set up. 1196 * Kick the transmitter. 1197 */ 1198 DPRINTF(sc, ("%s: gem_start: kicking tx %d\n", 1199 sc->sc_dev.dv_xname, nexttx)); 1200 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_TX_KICK, 1201 sc->sc_txnext); 1202 1203 /* Set a watchdog timer in case the chip flakes out. */ 1204 ifp->if_timer = 5; 1205 DPRINTF(sc, ("%s: gem_start: watchdog %d\n", 1206 sc->sc_dev.dv_xname, ifp->if_timer)); 1207 } 1208 } 1209 1210 /* 1211 * Transmit interrupt. 1212 */ 1213 int 1214 gem_tint(sc) 1215 struct gem_softc *sc; 1216 { 1217 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1218 bus_space_tag_t t = sc->sc_bustag; 1219 bus_space_handle_t mac = sc->sc_h; 1220 struct gem_txsoft *txs; 1221 int txlast; 1222 int progress = 0; 1223 1224 1225 DPRINTF(sc, ("%s: gem_tint\n", sc->sc_dev.dv_xname)); 1226 1227 /* 1228 * Unload collision counters 1229 */ 1230 ifp->if_collisions += 1231 bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) + 1232 bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT) + 1233 bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) + 1234 bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT); 1235 1236 /* 1237 * then clear the hardware counters. 1238 */ 1239 bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0); 1240 bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0); 1241 bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0); 1242 bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0); 1243 1244 /* 1245 * Go through our Tx list and free mbufs for those 1246 * frames that have been transmitted. 1247 */ 1248 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1249 GEM_CDTXSYNC(sc, txs->txs_lastdesc, 1250 txs->txs_ndescs, 1251 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1252 1253 #ifdef GEM_DEBUG 1254 if (ifp->if_flags & IFF_DEBUG) { 1255 int i; 1256 printf(" txsoft %p transmit chain:\n", txs); 1257 for (i = txs->txs_firstdesc;; i = GEM_NEXTTX(i)) { 1258 printf("descriptor %d: ", i); 1259 printf("gd_flags: 0x%016llx\t", (long long) 1260 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags)); 1261 printf("gd_addr: 0x%016llx\n", (long long) 1262 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr)); 1263 if (i == txs->txs_lastdesc) 1264 break; 1265 } 1266 } 1267 #endif 1268 1269 /* 1270 * In theory, we could harveast some descriptors before 1271 * the ring is empty, but that's a bit complicated. 1272 * 1273 * GEM_TX_COMPLETION points to the last descriptor 1274 * processed +1. 1275 */ 1276 txlast = bus_space_read_4(t, mac, GEM_TX_COMPLETION); 1277 DPRINTF(sc, 1278 ("gem_tint: txs->txs_lastdesc = %d, txlast = %d\n", 1279 txs->txs_lastdesc, txlast)); 1280 if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1281 if ((txlast >= txs->txs_firstdesc) && 1282 (txlast <= txs->txs_lastdesc)) 1283 break; 1284 } else { 1285 /* Ick -- this command wraps */ 1286 if ((txlast >= txs->txs_firstdesc) || 1287 (txlast <= txs->txs_lastdesc)) 1288 break; 1289 } 1290 1291 DPRINTF(sc, ("gem_tint: releasing a desc\n")); 1292 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1293 1294 sc->sc_txfree += txs->txs_ndescs; 1295 1296 if (txs->txs_mbuf == NULL) { 1297 #ifdef DIAGNOSTIC 1298 panic("gem_txintr: null mbuf"); 1299 #endif 1300 } 1301 1302 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 1303 0, txs->txs_dmamap->dm_mapsize, 1304 BUS_DMASYNC_POSTWRITE); 1305 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 1306 m_freem(txs->txs_mbuf); 1307 txs->txs_mbuf = NULL; 1308 1309 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1310 1311 ifp->if_opackets++; 1312 progress = 1; 1313 } 1314 1315 #if 0 1316 DPRINTF(sc, ("gem_tint: GEM_TX_STATE_MACHINE %x " 1317 "GEM_TX_DATA_PTR %llx " 1318 "GEM_TX_COMPLETION %x\n", 1319 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_STATE_MACHINE), 1320 ((long long) bus_space_read_4(sc->sc_bustag, sc->sc_h, 1321 GEM_TX_DATA_PTR_HI) << 32) | 1322 bus_space_read_4(sc->sc_bustag, sc->sc_h, 1323 GEM_TX_DATA_PTR_LO), 1324 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_COMPLETION))); 1325 #endif 1326 1327 if (progress) { 1328 if (sc->sc_txfree == GEM_NTXDESC - 1) 1329 sc->sc_txwin = 0; 1330 1331 ifp->if_flags &= ~IFF_OACTIVE; 1332 gem_start(ifp); 1333 1334 if (SIMPLEQ_EMPTY(&sc->sc_txdirtyq)) 1335 ifp->if_timer = 0; 1336 } 1337 DPRINTF(sc, ("%s: gem_tint: watchdog %d\n", 1338 sc->sc_dev.dv_xname, ifp->if_timer)); 1339 1340 return (1); 1341 } 1342 1343 /* 1344 * Receive interrupt. 1345 */ 1346 int 1347 gem_rint(sc) 1348 struct gem_softc *sc; 1349 { 1350 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1351 bus_space_tag_t t = sc->sc_bustag; 1352 bus_space_handle_t h = sc->sc_h; 1353 struct ether_header *eh; 1354 struct gem_rxsoft *rxs; 1355 struct mbuf *m; 1356 u_int64_t rxstat; 1357 u_int32_t rxcomp; 1358 int i, len, progress = 0; 1359 1360 DPRINTF(sc, ("%s: gem_rint\n", sc->sc_dev.dv_xname)); 1361 1362 /* 1363 * Read the completion register once. This limits 1364 * how long the following loop can execute. 1365 */ 1366 rxcomp = bus_space_read_4(t, h, GEM_RX_COMPLETION); 1367 1368 /* 1369 * XXXX Read the lastrx only once at the top for speed. 1370 */ 1371 DPRINTF(sc, ("gem_rint: sc->rxptr %d, complete %d\n", 1372 sc->sc_rxptr, rxcomp)); 1373 1374 /* 1375 * Go into the loop at least once. 1376 */ 1377 for (i = sc->sc_rxptr; i == sc->sc_rxptr || i != rxcomp; 1378 i = GEM_NEXTRX(i)) { 1379 rxs = &sc->sc_rxsoft[i]; 1380 1381 GEM_CDRXSYNC(sc, i, 1382 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1383 1384 rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags); 1385 1386 if (rxstat & GEM_RD_OWN) { 1387 /* 1388 * We have processed all of the receive buffers. 1389 */ 1390 break; 1391 } 1392 1393 progress++; 1394 ifp->if_ipackets++; 1395 1396 if (rxstat & GEM_RD_BAD_CRC) { 1397 ifp->if_ierrors++; 1398 printf("%s: receive error: CRC error\n", 1399 sc->sc_dev.dv_xname); 1400 GEM_INIT_RXDESC(sc, i); 1401 continue; 1402 } 1403 1404 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1405 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1406 #ifdef GEM_DEBUG 1407 if (ifp->if_flags & IFF_DEBUG) { 1408 printf(" rxsoft %p descriptor %d: ", rxs, i); 1409 printf("gd_flags: 0x%016llx\t", (long long) 1410 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags)); 1411 printf("gd_addr: 0x%016llx\n", (long long) 1412 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr)); 1413 } 1414 #endif 1415 1416 /* 1417 * No errors; receive the packet. Note the Gem 1418 * includes the CRC with every packet. 1419 */ 1420 len = GEM_RD_BUFLEN(rxstat); 1421 1422 /* 1423 * Allocate a new mbuf cluster. If that fails, we are 1424 * out of memory, and must drop the packet and recycle 1425 * the buffer that's already attached to this descriptor. 1426 */ 1427 m = rxs->rxs_mbuf; 1428 if (gem_add_rxbuf(sc, i) != 0) { 1429 GEM_COUNTER_INCR(sc, sc_ev_rxnobuf); 1430 ifp->if_ierrors++; 1431 GEM_INIT_RXDESC(sc, i); 1432 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1433 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1434 continue; 1435 } 1436 m->m_data += 2; /* We're already off by two */ 1437 1438 eh = mtod(m, struct ether_header *); 1439 m->m_flags |= M_HASFCS; 1440 m->m_pkthdr.rcvif = ifp; 1441 m->m_pkthdr.len = m->m_len = len; 1442 1443 #if NBPFILTER > 0 1444 /* 1445 * Pass this up to any BPF listeners, but only 1446 * pass it up the stack if its for us. 1447 */ 1448 if (ifp->if_bpf) 1449 bpf_mtap(ifp->if_bpf, m); 1450 #endif /* NPBFILTER > 0 */ 1451 1452 /* Pass it on. */ 1453 (*ifp->if_input)(ifp, m); 1454 } 1455 1456 if (progress) { 1457 /* Update the receive pointer. */ 1458 if (i == sc->sc_rxptr) { 1459 GEM_COUNTER_INCR(sc, sc_ev_rxfull); 1460 #ifdef GEM_DEBUG 1461 if (ifp->if_flags & IFF_DEBUG) 1462 printf("%s: rint: ring wrap\n", 1463 sc->sc_dev.dv_xname); 1464 #endif 1465 } 1466 sc->sc_rxptr = i; 1467 bus_space_write_4(t, h, GEM_RX_KICK, GEM_PREVRX(i)); 1468 } 1469 #ifdef GEM_COUNTERS 1470 if (progress <= 4) { 1471 GEM_COUNTER_INCR(sc, sc_ev_rxhist[progress]); 1472 } else if (progress < 32) { 1473 if (progress < 16) 1474 GEM_COUNTER_INCR(sc, sc_ev_rxhist[5]); 1475 else 1476 GEM_COUNTER_INCR(sc, sc_ev_rxhist[6]); 1477 1478 } else { 1479 if (progress < 64) 1480 GEM_COUNTER_INCR(sc, sc_ev_rxhist[7]); 1481 else 1482 GEM_COUNTER_INCR(sc, sc_ev_rxhist[8]); 1483 } 1484 #endif 1485 1486 DPRINTF(sc, ("gem_rint: done sc->rxptr %d, complete %d\n", 1487 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION))); 1488 1489 return (1); 1490 } 1491 1492 1493 /* 1494 * gem_add_rxbuf: 1495 * 1496 * Add a receive buffer to the indicated descriptor. 1497 */ 1498 int 1499 gem_add_rxbuf(struct gem_softc *sc, int idx) 1500 { 1501 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1502 struct mbuf *m; 1503 int error; 1504 1505 MGETHDR(m, M_DONTWAIT, MT_DATA); 1506 if (m == NULL) 1507 return (ENOBUFS); 1508 1509 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1510 MCLGET(m, M_DONTWAIT); 1511 if ((m->m_flags & M_EXT) == 0) { 1512 m_freem(m); 1513 return (ENOBUFS); 1514 } 1515 1516 #ifdef GEM_DEBUG 1517 /* bzero the packet to check DMA */ 1518 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 1519 #endif 1520 1521 if (rxs->rxs_mbuf != NULL) 1522 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 1523 1524 rxs->rxs_mbuf = m; 1525 1526 error = bus_dmamap_load(sc->sc_dmatag, rxs->rxs_dmamap, 1527 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1528 BUS_DMA_READ|BUS_DMA_NOWAIT); 1529 if (error) { 1530 printf("%s: can't load rx DMA map %d, error = %d\n", 1531 sc->sc_dev.dv_xname, idx, error); 1532 panic("gem_add_rxbuf"); /* XXX */ 1533 } 1534 1535 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1536 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1537 1538 GEM_INIT_RXDESC(sc, idx); 1539 1540 return (0); 1541 } 1542 1543 1544 int 1545 gem_eint(sc, status) 1546 struct gem_softc *sc; 1547 u_int status; 1548 { 1549 char bits[128]; 1550 1551 if ((status & GEM_INTR_MIF) != 0) { 1552 printf("%s: XXXlink status changed\n", sc->sc_dev.dv_xname); 1553 return (1); 1554 } 1555 1556 printf("%s: status=%s\n", sc->sc_dev.dv_xname, 1557 bitmask_snprintf(status, GEM_INTR_BITS, bits, sizeof(bits))); 1558 return (1); 1559 } 1560 1561 1562 int 1563 gem_intr(v) 1564 void *v; 1565 { 1566 struct gem_softc *sc = (struct gem_softc *)v; 1567 bus_space_tag_t t = sc->sc_bustag; 1568 bus_space_handle_t seb = sc->sc_h; 1569 u_int32_t status; 1570 int r = 0; 1571 #ifdef GEM_DEBUG 1572 char bits[128]; 1573 #endif 1574 1575 sc->sc_ev_intr.ev_count++; 1576 1577 status = bus_space_read_4(t, seb, GEM_STATUS); 1578 DPRINTF(sc, ("%s: gem_intr: cplt 0x%x status %s\n", 1579 sc->sc_dev.dv_xname, (status >> 19), 1580 bitmask_snprintf(status, GEM_INTR_BITS, bits, sizeof(bits)))); 1581 1582 if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0) 1583 r |= gem_eint(sc, status); 1584 1585 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) { 1586 GEM_COUNTER_INCR(sc, sc_ev_txint); 1587 r |= gem_tint(sc); 1588 } 1589 1590 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) { 1591 GEM_COUNTER_INCR(sc, sc_ev_rxint); 1592 r |= gem_rint(sc); 1593 } 1594 1595 /* We should eventually do more than just print out error stats. */ 1596 if (status & GEM_INTR_TX_MAC) { 1597 int txstat = bus_space_read_4(t, seb, GEM_MAC_TX_STATUS); 1598 if (txstat & ~GEM_MAC_TX_XMIT_DONE) 1599 printf("%s: MAC tx fault, status %x\n", 1600 sc->sc_dev.dv_xname, txstat); 1601 } 1602 if (status & GEM_INTR_RX_MAC) { 1603 int rxstat = bus_space_read_4(t, seb, GEM_MAC_RX_STATUS); 1604 if (rxstat & ~GEM_MAC_RX_DONE) 1605 printf("%s: MAC rx fault, status %x\n", 1606 sc->sc_dev.dv_xname, rxstat); 1607 } 1608 return (r); 1609 } 1610 1611 1612 void 1613 gem_watchdog(ifp) 1614 struct ifnet *ifp; 1615 { 1616 struct gem_softc *sc = ifp->if_softc; 1617 1618 DPRINTF(sc, ("gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x " 1619 "GEM_MAC_RX_CONFIG %x\n", 1620 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_CONFIG), 1621 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_STATUS), 1622 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_CONFIG))); 1623 1624 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1625 ++ifp->if_oerrors; 1626 1627 /* Try to get more packets going. */ 1628 gem_start(ifp); 1629 } 1630 1631 /* 1632 * Initialize the MII Management Interface 1633 */ 1634 void 1635 gem_mifinit(sc) 1636 struct gem_softc *sc; 1637 { 1638 bus_space_tag_t t = sc->sc_bustag; 1639 bus_space_handle_t mif = sc->sc_h; 1640 1641 /* Configure the MIF in frame mode */ 1642 sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1643 sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA; 1644 bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config); 1645 } 1646 1647 /* 1648 * MII interface 1649 * 1650 * The GEM MII interface supports at least three different operating modes: 1651 * 1652 * Bitbang mode is implemented using data, clock and output enable registers. 1653 * 1654 * Frame mode is implemented by loading a complete frame into the frame 1655 * register and polling the valid bit for completion. 1656 * 1657 * Polling mode uses the frame register but completion is indicated by 1658 * an interrupt. 1659 * 1660 */ 1661 static int 1662 gem_mii_readreg(self, phy, reg) 1663 struct device *self; 1664 int phy, reg; 1665 { 1666 struct gem_softc *sc = (void *)self; 1667 bus_space_tag_t t = sc->sc_bustag; 1668 bus_space_handle_t mif = sc->sc_h; 1669 int n; 1670 u_int32_t v; 1671 1672 #ifdef GEM_DEBUG1 1673 if (sc->sc_debug) 1674 printf("gem_mii_readreg: phy %d reg %d\n", phy, reg); 1675 #endif 1676 1677 #if 0 1678 /* Select the desired PHY in the MIF configuration register */ 1679 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1680 /* Clear PHY select bit */ 1681 v &= ~GEM_MIF_CONFIG_PHY_SEL; 1682 if (phy == GEM_PHYAD_EXTERNAL) 1683 /* Set PHY select bit to get at external device */ 1684 v |= GEM_MIF_CONFIG_PHY_SEL; 1685 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 1686 #endif 1687 1688 /* Construct the frame command */ 1689 v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) | 1690 GEM_MIF_FRAME_READ; 1691 1692 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1693 for (n = 0; n < 100; n++) { 1694 DELAY(1); 1695 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1696 if (v & GEM_MIF_FRAME_TA0) 1697 return (v & GEM_MIF_FRAME_DATA); 1698 } 1699 1700 printf("%s: mii_read timeout\n", sc->sc_dev.dv_xname); 1701 return (0); 1702 } 1703 1704 static void 1705 gem_mii_writereg(self, phy, reg, val) 1706 struct device *self; 1707 int phy, reg, val; 1708 { 1709 struct gem_softc *sc = (void *)self; 1710 bus_space_tag_t t = sc->sc_bustag; 1711 bus_space_handle_t mif = sc->sc_h; 1712 int n; 1713 u_int32_t v; 1714 1715 #ifdef GEM_DEBUG1 1716 if (sc->sc_debug) 1717 printf("gem_mii_writereg: phy %d reg %d val %x\n", 1718 phy, reg, val); 1719 #endif 1720 1721 #if 0 1722 /* Select the desired PHY in the MIF configuration register */ 1723 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1724 /* Clear PHY select bit */ 1725 v &= ~GEM_MIF_CONFIG_PHY_SEL; 1726 if (phy == GEM_PHYAD_EXTERNAL) 1727 /* Set PHY select bit to get at external device */ 1728 v |= GEM_MIF_CONFIG_PHY_SEL; 1729 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 1730 #endif 1731 /* Construct the frame command */ 1732 v = GEM_MIF_FRAME_WRITE | 1733 (phy << GEM_MIF_PHY_SHIFT) | 1734 (reg << GEM_MIF_REG_SHIFT) | 1735 (val & GEM_MIF_FRAME_DATA); 1736 1737 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1738 for (n = 0; n < 100; n++) { 1739 DELAY(1); 1740 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1741 if (v & GEM_MIF_FRAME_TA0) 1742 return; 1743 } 1744 1745 printf("%s: mii_write timeout\n", sc->sc_dev.dv_xname); 1746 } 1747 1748 static void 1749 gem_mii_statchg(dev) 1750 struct device *dev; 1751 { 1752 struct gem_softc *sc = (void *)dev; 1753 #ifdef GEM_DEBUG 1754 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1755 #endif 1756 bus_space_tag_t t = sc->sc_bustag; 1757 bus_space_handle_t mac = sc->sc_h; 1758 u_int32_t v; 1759 1760 #ifdef GEM_DEBUG 1761 if (sc->sc_debug) 1762 printf("gem_mii_statchg: status change: phy = %d\n", 1763 sc->sc_phys[instance]); 1764 #endif 1765 1766 1767 /* Set tx full duplex options */ 1768 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0); 1769 delay(10000); /* reg must be cleared and delay before changing. */ 1770 v = GEM_MAC_TX_ENA_IPG0|GEM_MAC_TX_NGU|GEM_MAC_TX_NGU_LIMIT| 1771 GEM_MAC_TX_ENABLE; 1772 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) { 1773 v |= GEM_MAC_TX_IGN_CARRIER|GEM_MAC_TX_IGN_COLLIS; 1774 } 1775 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, v); 1776 1777 /* XIF Configuration */ 1778 /* We should really calculate all this rather than rely on defaults */ 1779 v = bus_space_read_4(t, mac, GEM_MAC_XIF_CONFIG); 1780 v = GEM_MAC_XIF_LINK_LED; 1781 v |= GEM_MAC_XIF_TX_MII_ENA; 1782 1783 /* If an external transceiver is connected, enable its MII drivers */ 1784 sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG); 1785 if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) { 1786 /* External MII needs echo disable if half duplex. */ 1787 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1788 /* turn on full duplex LED */ 1789 v |= GEM_MAC_XIF_FDPLX_LED; 1790 else 1791 /* half duplex -- disable echo */ 1792 v |= GEM_MAC_XIF_ECHO_DISABL; 1793 1794 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 1795 v |= GEM_MAC_XIF_GMII_MODE; 1796 else 1797 v &= ~GEM_MAC_XIF_GMII_MODE; 1798 } else 1799 /* Internal MII needs buf enable */ 1800 v |= GEM_MAC_XIF_MII_BUF_ENA; 1801 bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v); 1802 } 1803 1804 int 1805 gem_mediachange(ifp) 1806 struct ifnet *ifp; 1807 { 1808 struct gem_softc *sc = ifp->if_softc; 1809 1810 if (IFM_TYPE(sc->sc_media.ifm_media) != IFM_ETHER) 1811 return (EINVAL); 1812 1813 return (mii_mediachg(&sc->sc_mii)); 1814 } 1815 1816 void 1817 gem_mediastatus(ifp, ifmr) 1818 struct ifnet *ifp; 1819 struct ifmediareq *ifmr; 1820 { 1821 struct gem_softc *sc = ifp->if_softc; 1822 1823 if ((ifp->if_flags & IFF_UP) == 0) 1824 return; 1825 1826 mii_pollstat(&sc->sc_mii); 1827 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1828 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1829 } 1830 1831 int gem_ioctldebug = 0; 1832 /* 1833 * Process an ioctl request. 1834 */ 1835 int 1836 gem_ioctl(ifp, cmd, data) 1837 struct ifnet *ifp; 1838 u_long cmd; 1839 caddr_t data; 1840 { 1841 struct gem_softc *sc = ifp->if_softc; 1842 struct ifreq *ifr = (struct ifreq *)data; 1843 int s, error = 0; 1844 1845 s = splnet(); 1846 1847 switch (cmd) { 1848 case SIOCGIFMEDIA: 1849 case SIOCSIFMEDIA: 1850 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1851 break; 1852 1853 default: 1854 error = ether_ioctl(ifp, cmd, data); 1855 if (error == ENETRESET) { 1856 /* 1857 * Multicast list has changed; set the hardware filter 1858 * accordingly. 1859 */ 1860 if (gem_ioctldebug) printf("reset1\n"); 1861 gem_init(ifp); 1862 delay(50000); 1863 error = 0; 1864 } 1865 break; 1866 } 1867 1868 /* Try to get things going again */ 1869 if (ifp->if_flags & IFF_UP) { 1870 if (gem_ioctldebug) printf("start\n"); 1871 gem_start(ifp); 1872 } 1873 splx(s); 1874 return (error); 1875 } 1876 1877 1878 void 1879 gem_shutdown(arg) 1880 void *arg; 1881 { 1882 struct gem_softc *sc = (struct gem_softc *)arg; 1883 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1884 1885 gem_stop(ifp, 1); 1886 } 1887 1888 /* 1889 * Set up the logical address filter. 1890 */ 1891 void 1892 gem_setladrf(sc) 1893 struct gem_softc *sc; 1894 { 1895 struct ethercom *ec = &sc->sc_ethercom; 1896 struct ifnet *ifp = &ec->ec_if; 1897 struct ether_multi *enm; 1898 struct ether_multistep step; 1899 bus_space_tag_t t = sc->sc_bustag; 1900 bus_space_handle_t h = sc->sc_h; 1901 u_int32_t crc; 1902 u_int32_t hash[16]; 1903 u_int32_t v; 1904 int i; 1905 1906 /* Get current RX configuration */ 1907 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 1908 1909 /* 1910 * Turn off promiscuous mode, promiscuous group mode (all multicast), 1911 * and hash filter. Depending on the case, the right bit will be 1912 * enabled. 1913 */ 1914 v &= ~(GEM_MAC_RX_PROMISCUOUS|GEM_MAC_RX_HASH_FILTER| 1915 GEM_MAC_RX_PROMISC_GRP); 1916 1917 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1918 /* Turn on promiscuous mode */ 1919 v |= GEM_MAC_RX_PROMISCUOUS; 1920 ifp->if_flags |= IFF_ALLMULTI; 1921 goto chipit; 1922 } 1923 1924 /* 1925 * Set up multicast address filter by passing all multicast addresses 1926 * through a crc generator, and then using the high order 8 bits as an 1927 * index into the 256 bit logical address filter. The high order 4 1928 * bits select the word, while the other 4 bits select the bit within 1929 * the word (where bit 0 is the MSB). 1930 */ 1931 1932 /* Clear hash table */ 1933 memset(hash, 0, sizeof(hash)); 1934 1935 ETHER_FIRST_MULTI(step, ec, enm); 1936 while (enm != NULL) { 1937 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1938 /* 1939 * We must listen to a range of multicast addresses. 1940 * For now, just accept all multicasts, rather than 1941 * trying to set only those filter bits needed to match 1942 * the range. (At this time, the only use of address 1943 * ranges is for IP multicast routing, for which the 1944 * range is big enough to require all bits set.) 1945 * XXX use the addr filter for this 1946 */ 1947 ifp->if_flags |= IFF_ALLMULTI; 1948 v |= GEM_MAC_RX_PROMISC_GRP; 1949 goto chipit; 1950 } 1951 1952 /* Get the LE CRC32 of the address */ 1953 crc = ether_crc32_le(enm->enm_addrlo, sizeof(enm->enm_addrlo)); 1954 1955 /* Just want the 8 most significant bits. */ 1956 crc >>= 24; 1957 1958 /* Set the corresponding bit in the filter. */ 1959 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 1960 1961 ETHER_NEXT_MULTI(step, enm); 1962 } 1963 1964 v |= GEM_MAC_RX_HASH_FILTER; 1965 ifp->if_flags &= ~IFF_ALLMULTI; 1966 1967 /* Now load the hash table into the chip (if we are using it) */ 1968 for (i = 0; i < 16; i++) { 1969 bus_space_write_4(t, h, 1970 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1-GEM_MAC_HASH0), 1971 hash[i]); 1972 } 1973 1974 chipit: 1975 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 1976 } 1977 1978 #if notyet 1979 1980 /* 1981 * gem_power: 1982 * 1983 * Power management (suspend/resume) hook. 1984 */ 1985 void 1986 gem_power(why, arg) 1987 int why; 1988 void *arg; 1989 { 1990 struct gem_softc *sc = arg; 1991 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1992 int s; 1993 1994 s = splnet(); 1995 switch (why) { 1996 case PWR_SUSPEND: 1997 case PWR_STANDBY: 1998 gem_stop(ifp, 1); 1999 if (sc->sc_power != NULL) 2000 (*sc->sc_power)(sc, why); 2001 break; 2002 case PWR_RESUME: 2003 if (ifp->if_flags & IFF_UP) { 2004 if (sc->sc_power != NULL) 2005 (*sc->sc_power)(sc, why); 2006 gem_init(ifp); 2007 } 2008 break; 2009 case PWR_SOFTSUSPEND: 2010 case PWR_SOFTSTANDBY: 2011 case PWR_SOFTRESUME: 2012 break; 2013 } 2014 splx(s); 2015 } 2016 #endif 2017
Indexes created Thu Sep 25 08:09:54 GMT 2025