gem.c revision 1.30
1 /* $NetBSD: gem.c,v 1.30 2003/10/26 19:11:33 christos Exp $ */ 2 3 /* 4 * 5 * Copyright (C) 2001 Eduardo Horvath. 6 * All rights reserved. 7 * 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 */ 31 32 /* 33 * Driver for Sun GEM ethernet controllers. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: gem.c,v 1.30 2003/10/26 19:11:33 christos Exp $"); 38 39 #include "bpfilter.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/callout.h> 44 #include <sys/mbuf.h> 45 #include <sys/syslog.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #include <sys/socket.h> 49 #include <sys/ioctl.h> 50 #include <sys/errno.h> 51 #include <sys/device.h> 52 53 #include <machine/endian.h> 54 55 #include <uvm/uvm_extern.h> 56 57 #include <net/if.h> 58 #include <net/if_dl.h> 59 #include <net/if_media.h> 60 #include <net/if_ether.h> 61 62 #if NBPFILTER > 0 63 #include <net/bpf.h> 64 #endif 65 66 #include <machine/bus.h> 67 #include <machine/intr.h> 68 69 #include <dev/mii/mii.h> 70 #include <dev/mii/miivar.h> 71 #include <dev/mii/mii_bitbang.h> 72 73 #include <dev/ic/gemreg.h> 74 #include <dev/ic/gemvar.h> 75 76 #define TRIES 10000 77 78 void gem_start __P((struct ifnet *)); 79 void gem_stop __P((struct ifnet *, int)); 80 int gem_ioctl __P((struct ifnet *, u_long, caddr_t)); 81 void gem_tick __P((void *)); 82 void gem_watchdog __P((struct ifnet *)); 83 void gem_shutdown __P((void *)); 84 int gem_init __P((struct ifnet *)); 85 void gem_init_regs(struct gem_softc *sc); 86 static int gem_ringsize(int sz); 87 int gem_meminit __P((struct gem_softc *)); 88 void gem_mifinit __P((struct gem_softc *)); 89 void gem_reset __P((struct gem_softc *)); 90 int gem_reset_rx(struct gem_softc *sc); 91 int gem_reset_tx(struct gem_softc *sc); 92 int gem_disable_rx(struct gem_softc *sc); 93 int gem_disable_tx(struct gem_softc *sc); 94 void gem_rxdrain(struct gem_softc *sc); 95 int gem_add_rxbuf(struct gem_softc *sc, int idx); 96 void gem_setladrf __P((struct gem_softc *)); 97 98 /* MII methods & callbacks */ 99 static int gem_mii_readreg __P((struct device *, int, int)); 100 static void gem_mii_writereg __P((struct device *, int, int, int)); 101 static void gem_mii_statchg __P((struct device *)); 102 103 int gem_mediachange __P((struct ifnet *)); 104 void gem_mediastatus __P((struct ifnet *, struct ifmediareq *)); 105 106 struct mbuf *gem_get __P((struct gem_softc *, int, int)); 107 int gem_put __P((struct gem_softc *, int, struct mbuf *)); 108 void gem_read __P((struct gem_softc *, int, int)); 109 int gem_eint __P((struct gem_softc *, u_int)); 110 int gem_rint __P((struct gem_softc *)); 111 int gem_tint __P((struct gem_softc *)); 112 void gem_power __P((int, void *)); 113 114 #ifdef GEM_DEBUG 115 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 116 printf x 117 #else 118 #define DPRINTF(sc, x) /* nothing */ 119 #endif 120 121 122 /* 123 * gem_attach: 124 * 125 * Attach a Gem interface to the system. 126 */ 127 void 128 gem_attach(sc, enaddr) 129 struct gem_softc *sc; 130 const uint8_t *enaddr; 131 { 132 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 133 struct mii_data *mii = &sc->sc_mii; 134 struct mii_softc *child; 135 struct ifmedia_entry *ifm; 136 int i, error; 137 u_int32_t v; 138 139 /* Make sure the chip is stopped. */ 140 ifp->if_softc = sc; 141 gem_reset(sc); 142 143 /* 144 * Allocate the control data structures, and create and load the 145 * DMA map for it. 146 */ 147 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 148 sizeof(struct gem_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 149 1, &sc->sc_cdnseg, 0)) != 0) { 150 aprint_error( 151 "%s: unable to allocate control data, error = %d\n", 152 sc->sc_dev.dv_xname, error); 153 goto fail_0; 154 } 155 156 /* XXX should map this in with correct endianness */ 157 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg, 158 sizeof(struct gem_control_data), (caddr_t *)&sc->sc_control_data, 159 BUS_DMA_COHERENT)) != 0) { 160 aprint_error("%s: unable to map control data, error = %d\n", 161 sc->sc_dev.dv_xname, error); 162 goto fail_1; 163 } 164 165 if ((error = bus_dmamap_create(sc->sc_dmatag, 166 sizeof(struct gem_control_data), 1, 167 sizeof(struct gem_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 168 aprint_error("%s: unable to create control data DMA map, " 169 "error = %d\n", sc->sc_dev.dv_xname, error); 170 goto fail_2; 171 } 172 173 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 174 sc->sc_control_data, sizeof(struct gem_control_data), NULL, 175 0)) != 0) { 176 aprint_error( 177 "%s: unable to load control data DMA map, error = %d\n", 178 sc->sc_dev.dv_xname, error); 179 goto fail_3; 180 } 181 182 /* 183 * Initialize the transmit job descriptors. 184 */ 185 SIMPLEQ_INIT(&sc->sc_txfreeq); 186 SIMPLEQ_INIT(&sc->sc_txdirtyq); 187 188 /* 189 * Create the transmit buffer DMA maps. 190 */ 191 for (i = 0; i < GEM_TXQUEUELEN; i++) { 192 struct gem_txsoft *txs; 193 194 txs = &sc->sc_txsoft[i]; 195 txs->txs_mbuf = NULL; 196 if ((error = bus_dmamap_create(sc->sc_dmatag, 197 ETHER_MAX_LEN_JUMBO, GEM_NTXSEGS, 198 ETHER_MAX_LEN_JUMBO, 0, 0, 199 &txs->txs_dmamap)) != 0) { 200 aprint_error("%s: unable to create tx DMA map %d, " 201 "error = %d\n", sc->sc_dev.dv_xname, i, error); 202 goto fail_4; 203 } 204 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 205 } 206 207 /* 208 * Create the receive buffer DMA maps. 209 */ 210 for (i = 0; i < GEM_NRXDESC; i++) { 211 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, 212 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 213 aprint_error("%s: unable to create rx DMA map %d, " 214 "error = %d\n", sc->sc_dev.dv_xname, i, error); 215 goto fail_5; 216 } 217 sc->sc_rxsoft[i].rxs_mbuf = NULL; 218 } 219 220 /* 221 * From this point forward, the attachment cannot fail. A failure 222 * before this point releases all resources that may have been 223 * allocated. 224 */ 225 226 /* Announce ourselves. */ 227 aprint_normal("%s: Ethernet address %s", sc->sc_dev.dv_xname, 228 ether_sprintf(enaddr)); 229 230 /* Get RX FIFO size */ 231 sc->sc_rxfifosize = 64 * 232 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_FIFO_SIZE); 233 aprint_normal(", %uKB RX fifo", sc->sc_rxfifosize / 1024); 234 235 /* Get TX FIFO size */ 236 v = bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_FIFO_SIZE); 237 aprint_normal(", %uKB TX fifo\n", v / 16); 238 239 /* Initialize ifnet structure. */ 240 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 241 ifp->if_softc = sc; 242 ifp->if_flags = 243 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 244 ifp->if_start = gem_start; 245 ifp->if_ioctl = gem_ioctl; 246 ifp->if_watchdog = gem_watchdog; 247 ifp->if_stop = gem_stop; 248 ifp->if_init = gem_init; 249 IFQ_SET_READY(&ifp->if_snd); 250 251 /* Initialize ifmedia structures and MII info */ 252 mii->mii_ifp = ifp; 253 mii->mii_readreg = gem_mii_readreg; 254 mii->mii_writereg = gem_mii_writereg; 255 mii->mii_statchg = gem_mii_statchg; 256 257 ifmedia_init(&mii->mii_media, IFM_IMASK, gem_mediachange, gem_mediastatus); 258 259 gem_mifinit(sc); 260 261 mii_attach(&sc->sc_dev, mii, 0xffffffff, 262 MII_PHY_ANY, MII_OFFSET_ANY, MIIF_FORCEANEG); 263 264 child = LIST_FIRST(&mii->mii_phys); 265 if (child == NULL) { 266 /* No PHY attached */ 267 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 268 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 269 } else { 270 /* 271 * Walk along the list of attached MII devices and 272 * establish an `MII instance' to `phy number' 273 * mapping. We'll use this mapping in media change 274 * requests to determine which phy to use to program 275 * the MIF configuration register. 276 */ 277 for (; child != NULL; child = LIST_NEXT(child, mii_list)) { 278 /* 279 * Note: we support just two PHYs: the built-in 280 * internal device and an external on the MII 281 * connector. 282 */ 283 if (child->mii_phy > 1 || child->mii_inst > 1) { 284 aprint_error( 285 "%s: cannot accomodate MII device %s" 286 " at phy %d, instance %d\n", 287 sc->sc_dev.dv_xname, 288 child->mii_dev.dv_xname, 289 child->mii_phy, child->mii_inst); 290 continue; 291 } 292 293 sc->sc_phys[child->mii_inst] = child->mii_phy; 294 295 } 296 297 /* 298 * Now select and activate the PHY we will use. 299 * 300 * The order of preference is External (MDI1), 301 * Internal (MDI0), Serial Link (no MII). 302 */ 303 if (sc->sc_phys[1]) { 304 #ifdef DEBUG 305 aprint_debug("using external phy\n"); 306 #endif 307 sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL; 308 } else { 309 #ifdef DEBUG 310 aprint_debug("using internal phy\n"); 311 #endif 312 sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL; 313 } 314 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_MIF_CONFIG, 315 sc->sc_mif_config); 316 317 /* 318 * XXX - we can really do the following ONLY if the 319 * phy indeed has the auto negotiation capability!! 320 */ 321 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO); 322 } 323 324 /* 325 * If we support GigE media, we support jumbo frames too. 326 * Unless we are Apple. 327 */ 328 TAILQ_FOREACH(ifm, &sc->sc_media.ifm_list, ifm_list) { 329 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_T || 330 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_SX || 331 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_LX || 332 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_CX) { 333 if (sc->sc_variant != GEM_APPLE_GMAC) 334 sc->sc_ethercom.ec_capabilities 335 |= ETHERCAP_JUMBO_MTU; 336 337 sc->sc_flags |= GEM_GIGABIT; 338 break; 339 } 340 } 341 342 /* claim 802.1q capability */ 343 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 344 345 /* Attach the interface. */ 346 if_attach(ifp); 347 ether_ifattach(ifp, enaddr); 348 349 sc->sc_sh = shutdownhook_establish(gem_shutdown, sc); 350 if (sc->sc_sh == NULL) 351 panic("gem_config: can't establish shutdownhook"); 352 353 #if NRND > 0 354 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 355 RND_TYPE_NET, 0); 356 #endif 357 358 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, 359 NULL, sc->sc_dev.dv_xname, "interrupts"); 360 #ifdef GEM_COUNTERS 361 evcnt_attach_dynamic(&sc->sc_ev_txint, EVCNT_TYPE_INTR, 362 &sc->sc_ev_intr, sc->sc_dev.dv_xname, "tx interrupts"); 363 evcnt_attach_dynamic(&sc->sc_ev_rxint, EVCNT_TYPE_INTR, 364 &sc->sc_ev_intr, sc->sc_dev.dv_xname, "rx interrupts"); 365 evcnt_attach_dynamic(&sc->sc_ev_rxfull, EVCNT_TYPE_INTR, 366 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx ring full"); 367 evcnt_attach_dynamic(&sc->sc_ev_rxnobuf, EVCNT_TYPE_INTR, 368 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx malloc failure"); 369 evcnt_attach_dynamic(&sc->sc_ev_rxhist[0], EVCNT_TYPE_INTR, 370 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 0desc"); 371 evcnt_attach_dynamic(&sc->sc_ev_rxhist[1], EVCNT_TYPE_INTR, 372 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 1desc"); 373 evcnt_attach_dynamic(&sc->sc_ev_rxhist[2], EVCNT_TYPE_INTR, 374 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 2desc"); 375 evcnt_attach_dynamic(&sc->sc_ev_rxhist[3], EVCNT_TYPE_INTR, 376 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 3desc"); 377 evcnt_attach_dynamic(&sc->sc_ev_rxhist[4], EVCNT_TYPE_INTR, 378 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >3desc"); 379 evcnt_attach_dynamic(&sc->sc_ev_rxhist[5], EVCNT_TYPE_INTR, 380 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >7desc"); 381 evcnt_attach_dynamic(&sc->sc_ev_rxhist[6], EVCNT_TYPE_INTR, 382 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >15desc"); 383 evcnt_attach_dynamic(&sc->sc_ev_rxhist[7], EVCNT_TYPE_INTR, 384 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >31desc"); 385 evcnt_attach_dynamic(&sc->sc_ev_rxhist[8], EVCNT_TYPE_INTR, 386 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >63desc"); 387 #endif 388 389 #if notyet 390 /* 391 * Add a suspend hook to make sure we come back up after a 392 * resume. 393 */ 394 sc->sc_powerhook = powerhook_establish(gem_power, sc); 395 if (sc->sc_powerhook == NULL) 396 aprint_error("%s: WARNING: unable to establish power hook\n", 397 sc->sc_dev.dv_xname); 398 #endif 399 400 callout_init(&sc->sc_tick_ch); 401 return; 402 403 /* 404 * Free any resources we've allocated during the failed attach 405 * attempt. Do this in reverse order and fall through. 406 */ 407 fail_5: 408 for (i = 0; i < GEM_NRXDESC; i++) { 409 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 410 bus_dmamap_destroy(sc->sc_dmatag, 411 sc->sc_rxsoft[i].rxs_dmamap); 412 } 413 fail_4: 414 for (i = 0; i < GEM_TXQUEUELEN; i++) { 415 if (sc->sc_txsoft[i].txs_dmamap != NULL) 416 bus_dmamap_destroy(sc->sc_dmatag, 417 sc->sc_txsoft[i].txs_dmamap); 418 } 419 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 420 fail_3: 421 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 422 fail_2: 423 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)sc->sc_control_data, 424 sizeof(struct gem_control_data)); 425 fail_1: 426 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 427 fail_0: 428 return; 429 } 430 431 432 void 433 gem_tick(arg) 434 void *arg; 435 { 436 struct gem_softc *sc = arg; 437 int s; 438 439 s = splnet(); 440 mii_tick(&sc->sc_mii); 441 splx(s); 442 443 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 444 445 } 446 447 void 448 gem_reset(sc) 449 struct gem_softc *sc; 450 { 451 bus_space_tag_t t = sc->sc_bustag; 452 bus_space_handle_t h = sc->sc_h; 453 int i; 454 int s; 455 456 s = splnet(); 457 DPRINTF(sc, ("%s: gem_reset\n", sc->sc_dev.dv_xname)); 458 gem_reset_rx(sc); 459 gem_reset_tx(sc); 460 461 /* Do a full reset */ 462 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX|GEM_RESET_TX); 463 for (i=TRIES; i--; delay(100)) 464 if ((bus_space_read_4(t, h, GEM_RESET) & 465 (GEM_RESET_RX|GEM_RESET_TX)) == 0) 466 break; 467 if ((bus_space_read_4(t, h, GEM_RESET) & 468 (GEM_RESET_RX|GEM_RESET_TX)) != 0) { 469 printf("%s: cannot reset device\n", 470 sc->sc_dev.dv_xname); 471 } 472 splx(s); 473 } 474 475 476 /* 477 * gem_rxdrain: 478 * 479 * Drain the receive queue. 480 */ 481 void 482 gem_rxdrain(struct gem_softc *sc) 483 { 484 struct gem_rxsoft *rxs; 485 int i; 486 487 for (i = 0; i < GEM_NRXDESC; i++) { 488 rxs = &sc->sc_rxsoft[i]; 489 if (rxs->rxs_mbuf != NULL) { 490 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 491 m_freem(rxs->rxs_mbuf); 492 rxs->rxs_mbuf = NULL; 493 } 494 } 495 } 496 497 /* 498 * Reset the whole thing. 499 */ 500 void 501 gem_stop(struct ifnet *ifp, int disable) 502 { 503 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 504 struct gem_txsoft *txs; 505 506 DPRINTF(sc, ("%s: gem_stop\n", sc->sc_dev.dv_xname)); 507 508 callout_stop(&sc->sc_tick_ch); 509 mii_down(&sc->sc_mii); 510 511 /* XXX - Should we reset these instead? */ 512 gem_disable_rx(sc); 513 gem_disable_tx(sc); 514 515 /* 516 * Release any queued transmit buffers. 517 */ 518 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 519 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 520 if (txs->txs_mbuf != NULL) { 521 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 522 m_freem(txs->txs_mbuf); 523 txs->txs_mbuf = NULL; 524 } 525 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 526 } 527 528 if (disable) { 529 gem_rxdrain(sc); 530 } 531 532 /* 533 * Mark the interface down and cancel the watchdog timer. 534 */ 535 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 536 ifp->if_timer = 0; 537 } 538 539 540 /* 541 * Reset the receiver 542 */ 543 int 544 gem_reset_rx(struct gem_softc *sc) 545 { 546 bus_space_tag_t t = sc->sc_bustag; 547 bus_space_handle_t h = sc->sc_h; 548 int i; 549 550 551 /* 552 * Resetting while DMA is in progress can cause a bus hang, so we 553 * disable DMA first. 554 */ 555 gem_disable_rx(sc); 556 bus_space_write_4(t, h, GEM_RX_CONFIG, 0); 557 /* Wait till it finishes */ 558 for (i=TRIES; i--; delay(100)) 559 if ((bus_space_read_4(t, h, GEM_RX_CONFIG) & 1) == 0) 560 break; 561 if ((bus_space_read_4(t, h, GEM_RX_CONFIG) & 1) != 0) 562 printf("%s: cannot disable read DMA\n", 563 sc->sc_dev.dv_xname); 564 565 /* Wait 5ms extra. */ 566 delay(5000); 567 568 /* Finally, reset the ERX */ 569 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX); 570 /* Wait till it finishes */ 571 for (i=TRIES; i--; delay(100)) 572 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_RX) == 0) 573 break; 574 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_RX) != 0) { 575 printf("%s: cannot reset receiver\n", 576 sc->sc_dev.dv_xname); 577 return (1); 578 } 579 return (0); 580 } 581 582 583 /* 584 * Reset the transmitter 585 */ 586 int 587 gem_reset_tx(struct gem_softc *sc) 588 { 589 bus_space_tag_t t = sc->sc_bustag; 590 bus_space_handle_t h = sc->sc_h; 591 int i; 592 593 /* 594 * Resetting while DMA is in progress can cause a bus hang, so we 595 * disable DMA first. 596 */ 597 gem_disable_tx(sc); 598 bus_space_write_4(t, h, GEM_TX_CONFIG, 0); 599 /* Wait till it finishes */ 600 for (i=TRIES; i--; delay(100)) 601 if ((bus_space_read_4(t, h, GEM_TX_CONFIG) & 1) == 0) 602 break; 603 if ((bus_space_read_4(t, h, GEM_TX_CONFIG) & 1) != 0) 604 printf("%s: cannot disable read DMA\n", 605 sc->sc_dev.dv_xname); 606 607 /* Wait 5ms extra. */ 608 delay(5000); 609 610 /* Finally, reset the ETX */ 611 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_TX); 612 /* Wait till it finishes */ 613 for (i=TRIES; i--; delay(100)) 614 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_TX) == 0) 615 break; 616 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_TX) != 0) { 617 printf("%s: cannot reset receiver\n", 618 sc->sc_dev.dv_xname); 619 return (1); 620 } 621 return (0); 622 } 623 624 /* 625 * disable receiver. 626 */ 627 int 628 gem_disable_rx(struct gem_softc *sc) 629 { 630 bus_space_tag_t t = sc->sc_bustag; 631 bus_space_handle_t h = sc->sc_h; 632 int i; 633 u_int32_t cfg; 634 635 /* Flip the enable bit */ 636 cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 637 cfg &= ~GEM_MAC_RX_ENABLE; 638 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg); 639 640 /* Wait for it to finish */ 641 for (i=TRIES; i--; delay(100)) 642 if ((bus_space_read_4(t, h, GEM_MAC_RX_CONFIG) & 643 GEM_MAC_RX_ENABLE) == 0) 644 return (0); 645 return (1); 646 } 647 648 /* 649 * disable transmitter. 650 */ 651 int 652 gem_disable_tx(struct gem_softc *sc) 653 { 654 bus_space_tag_t t = sc->sc_bustag; 655 bus_space_handle_t h = sc->sc_h; 656 int i; 657 u_int32_t cfg; 658 659 /* Flip the enable bit */ 660 cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG); 661 cfg &= ~GEM_MAC_TX_ENABLE; 662 bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg); 663 664 /* Wait for it to finish */ 665 for (i=TRIES; i--; delay(100)) 666 if ((bus_space_read_4(t, h, GEM_MAC_TX_CONFIG) & 667 GEM_MAC_TX_ENABLE) == 0) 668 return (0); 669 return (1); 670 } 671 672 /* 673 * Initialize interface. 674 */ 675 int 676 gem_meminit(struct gem_softc *sc) 677 { 678 struct gem_rxsoft *rxs; 679 int i, error; 680 681 /* 682 * Initialize the transmit descriptor ring. 683 */ 684 memset((void *)sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 685 for (i = 0; i < GEM_NTXDESC; i++) { 686 sc->sc_txdescs[i].gd_flags = 0; 687 sc->sc_txdescs[i].gd_addr = 0; 688 } 689 GEM_CDTXSYNC(sc, 0, GEM_NTXDESC, 690 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 691 sc->sc_txfree = GEM_NTXDESC-1; 692 sc->sc_txnext = 0; 693 sc->sc_txwin = 0; 694 695 /* 696 * Initialize the receive descriptor and receive job 697 * descriptor rings. 698 */ 699 for (i = 0; i < GEM_NRXDESC; i++) { 700 rxs = &sc->sc_rxsoft[i]; 701 if (rxs->rxs_mbuf == NULL) { 702 if ((error = gem_add_rxbuf(sc, i)) != 0) { 703 printf("%s: unable to allocate or map rx " 704 "buffer %d, error = %d\n", 705 sc->sc_dev.dv_xname, i, error); 706 /* 707 * XXX Should attempt to run with fewer receive 708 * XXX buffers instead of just failing. 709 */ 710 gem_rxdrain(sc); 711 return (1); 712 } 713 } else 714 GEM_INIT_RXDESC(sc, i); 715 } 716 sc->sc_rxptr = 0; 717 718 return (0); 719 } 720 721 static int 722 gem_ringsize(int sz) 723 { 724 switch (sz) { 725 case 32: 726 return GEM_RING_SZ_32; 727 case 64: 728 return GEM_RING_SZ_64; 729 case 128: 730 return GEM_RING_SZ_128; 731 case 256: 732 return GEM_RING_SZ_256; 733 case 512: 734 return GEM_RING_SZ_512; 735 case 1024: 736 return GEM_RING_SZ_1024; 737 case 2048: 738 return GEM_RING_SZ_2048; 739 case 4096: 740 return GEM_RING_SZ_4096; 741 case 8192: 742 return GEM_RING_SZ_8192; 743 default: 744 printf("gem: invalid Receive Descriptor ring size %d\n", sz); 745 return GEM_RING_SZ_32; 746 } 747 } 748 749 /* 750 * Initialization of interface; set up initialization block 751 * and transmit/receive descriptor rings. 752 */ 753 int 754 gem_init(struct ifnet *ifp) 755 { 756 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 757 bus_space_tag_t t = sc->sc_bustag; 758 bus_space_handle_t h = sc->sc_h; 759 int s; 760 u_int max_frame_size; 761 u_int32_t v; 762 763 s = splnet(); 764 765 DPRINTF(sc, ("%s: gem_init: calling stop\n", sc->sc_dev.dv_xname)); 766 /* 767 * Initialization sequence. The numbered steps below correspond 768 * to the sequence outlined in section 6.3.5.1 in the Ethernet 769 * Channel Engine manual (part of the PCIO manual). 770 * See also the STP2002-STQ document from Sun Microsystems. 771 */ 772 773 /* step 1 & 2. Reset the Ethernet Channel */ 774 gem_stop(ifp, 0); 775 gem_reset(sc); 776 DPRINTF(sc, ("%s: gem_init: restarting\n", sc->sc_dev.dv_xname)); 777 778 /* Re-initialize the MIF */ 779 gem_mifinit(sc); 780 781 /* Call MI reset function if any */ 782 if (sc->sc_hwreset) 783 (*sc->sc_hwreset)(sc); 784 785 /* step 3. Setup data structures in host memory */ 786 gem_meminit(sc); 787 788 /* step 4. TX MAC registers & counters */ 789 gem_init_regs(sc); 790 max_frame_size = max(sc->sc_ethercom.ec_if.if_mtu, ETHERMTU); 791 max_frame_size += ETHER_HDR_LEN + ETHER_CRC_LEN; 792 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 793 max_frame_size += ETHER_VLAN_ENCAP_LEN; 794 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 795 max_frame_size|/* burst size */(0x2000<<16)); 796 797 /* step 5. RX MAC registers & counters */ 798 gem_setladrf(sc); 799 800 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 801 /* NOTE: we use only 32-bit DMA addresses here. */ 802 bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 0); 803 bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 804 805 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0); 806 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 807 808 /* step 8. Global Configuration & Interrupt Mask */ 809 bus_space_write_4(t, h, GEM_INTMASK, 810 ~(GEM_INTR_TX_INTME| 811 GEM_INTR_TX_EMPTY| 812 GEM_INTR_RX_DONE|GEM_INTR_RX_NOBUF| 813 GEM_INTR_RX_TAG_ERR|GEM_INTR_PCS| 814 GEM_INTR_MAC_CONTROL|GEM_INTR_MIF| 815 GEM_INTR_BERR)); 816 bus_space_write_4(t, h, GEM_MAC_RX_MASK, 817 GEM_MAC_RX_DONE|GEM_MAC_RX_FRAME_CNT); 818 bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXXX */ 819 bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 0); /* XXXX */ 820 821 /* step 9. ETX Configuration: use mostly default values */ 822 823 /* Enable DMA */ 824 v = gem_ringsize(GEM_NTXDESC /*XXX*/); 825 bus_space_write_4(t, h, GEM_TX_CONFIG, 826 v|GEM_TX_CONFIG_TXDMA_EN| 827 ((0x400<<10)&GEM_TX_CONFIG_TXFIFO_TH)); 828 bus_space_write_4(t, h, GEM_TX_KICK, sc->sc_txnext); 829 830 /* step 10. ERX Configuration */ 831 832 /* Encode Receive Descriptor ring size: four possible values */ 833 v = gem_ringsize(GEM_NRXDESC /*XXX*/); 834 835 /* Enable DMA */ 836 bus_space_write_4(t, h, GEM_RX_CONFIG, 837 v|(GEM_THRSH_1024<<GEM_RX_CONFIG_FIFO_THRS_SHIFT)| 838 (2<<GEM_RX_CONFIG_FBOFF_SHFT)|GEM_RX_CONFIG_RXDMA_EN| 839 (0<<GEM_RX_CONFIG_CXM_START_SHFT)); 840 /* 841 * The following value is for an OFF Threshold of about 3/4 full 842 * and an ON Threshold of 1/4 full. 843 */ 844 bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH, 845 (3 * sc->sc_rxfifosize / 256) | 846 ( (sc->sc_rxfifosize / 256) << 12)); 847 bus_space_write_4(t, h, GEM_RX_BLANKING, (6<<12)|6); 848 849 /* step 11. Configure Media */ 850 mii_mediachg(&sc->sc_mii); 851 852 /* XXXX Serial link needs a whole different setup. */ 853 854 855 /* step 12. RX_MAC Configuration Register */ 856 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 857 v |= GEM_MAC_RX_ENABLE; 858 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 859 860 /* step 14. Issue Transmit Pending command */ 861 862 /* Call MI initialization function if any */ 863 if (sc->sc_hwinit) 864 (*sc->sc_hwinit)(sc); 865 866 867 /* step 15. Give the reciever a swift kick */ 868 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4); 869 870 /* Start the one second timer. */ 871 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 872 873 ifp->if_flags |= IFF_RUNNING; 874 ifp->if_flags &= ~IFF_OACTIVE; 875 ifp->if_timer = 0; 876 splx(s); 877 878 return (0); 879 } 880 881 void 882 gem_init_regs(struct gem_softc *sc) 883 { 884 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 885 bus_space_tag_t t = sc->sc_bustag; 886 bus_space_handle_t h = sc->sc_h; 887 const u_char *laddr = LLADDR(ifp->if_sadl); 888 u_int32_t v; 889 890 /* These regs are not cleared on reset */ 891 if (!sc->sc_inited) { 892 893 /* Wooo. Magic values. */ 894 bus_space_write_4(t, h, GEM_MAC_IPG0, 0); 895 bus_space_write_4(t, h, GEM_MAC_IPG1, 8); 896 bus_space_write_4(t, h, GEM_MAC_IPG2, 4); 897 898 bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 899 /* Max frame and max burst size */ 900 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 901 ETHER_MAX_LEN | (0x2000<<16)); 902 903 bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x7); 904 bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x4); 905 bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10); 906 /* Dunno.... */ 907 bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088); 908 bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED, 909 ((laddr[5]<<8)|laddr[4])&0x3ff); 910 911 /* Secondary MAC addr set to 0:0:0:0:0:0 */ 912 bus_space_write_4(t, h, GEM_MAC_ADDR3, 0); 913 bus_space_write_4(t, h, GEM_MAC_ADDR4, 0); 914 bus_space_write_4(t, h, GEM_MAC_ADDR5, 0); 915 916 /* MAC control addr set to 01:80:c2:00:00:01 */ 917 bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001); 918 bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200); 919 bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180); 920 921 /* MAC filter addr set to 0:0:0:0:0:0 */ 922 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0); 923 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0); 924 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0); 925 926 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0); 927 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0); 928 929 sc->sc_inited = 1; 930 } 931 932 /* Counters need to be zeroed */ 933 bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0); 934 bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0); 935 bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0); 936 bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0); 937 bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0); 938 bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0); 939 bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0); 940 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 941 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 942 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 943 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 944 945 /* Un-pause stuff */ 946 #if 0 947 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); 948 #else 949 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0); 950 #endif 951 952 /* 953 * Set the station address. 954 */ 955 bus_space_write_4(t, h, GEM_MAC_ADDR0, (laddr[4]<<8)|laddr[5]); 956 bus_space_write_4(t, h, GEM_MAC_ADDR1, (laddr[2]<<8)|laddr[3]); 957 bus_space_write_4(t, h, GEM_MAC_ADDR2, (laddr[0]<<8)|laddr[1]); 958 959 #if 0 960 if (sc->sc_variant != APPLE_GMAC) 961 return; 962 #endif 963 964 /* 965 * Enable MII outputs. Enable GMII if there is a gigabit PHY. 966 */ 967 sc->sc_mif_config = bus_space_read_4(t, h, GEM_MIF_CONFIG); 968 v = GEM_MAC_XIF_TX_MII_ENA; 969 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) { 970 v |= GEM_MAC_XIF_FDPLX_LED; 971 if (sc->sc_flags & GEM_GIGABIT) 972 v |= GEM_MAC_XIF_GMII_MODE; 973 } 974 bus_space_write_4(t, h, GEM_MAC_XIF_CONFIG, v); 975 } 976 977 void 978 gem_start(ifp) 979 struct ifnet *ifp; 980 { 981 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 982 struct mbuf *m0, *m; 983 struct gem_txsoft *txs, *last_txs; 984 bus_dmamap_t dmamap; 985 int error, firsttx, nexttx, lasttx = -1, ofree, seg; 986 987 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 988 return; 989 990 /* 991 * Remember the previous number of free descriptors and 992 * the first descriptor we'll use. 993 */ 994 ofree = sc->sc_txfree; 995 firsttx = sc->sc_txnext; 996 997 DPRINTF(sc, ("%s: gem_start: txfree %d, txnext %d\n", 998 sc->sc_dev.dv_xname, ofree, firsttx)); 999 1000 /* 1001 * Loop through the send queue, setting up transmit descriptors 1002 * until we drain the queue, or use up all available transmit 1003 * descriptors. 1004 */ 1005 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 1006 sc->sc_txfree != 0) { 1007 /* 1008 * Grab a packet off the queue. 1009 */ 1010 IFQ_POLL(&ifp->if_snd, m0); 1011 if (m0 == NULL) 1012 break; 1013 m = NULL; 1014 1015 dmamap = txs->txs_dmamap; 1016 1017 /* 1018 * Load the DMA map. If this fails, the packet either 1019 * didn't fit in the alloted number of segments, or we were 1020 * short on resources. In this case, we'll copy and try 1021 * again. 1022 */ 1023 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m0, 1024 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1025 if (m0->m_pkthdr.len > MCLBYTES) { 1026 printf("%s: unable to allocate jumbo Tx " 1027 "cluster\n", sc->sc_dev.dv_xname); 1028 IFQ_DEQUEUE(&ifp->if_snd, m0); 1029 m_freem(m0); 1030 continue; 1031 } 1032 MGETHDR(m, M_DONTWAIT, MT_DATA); 1033 if (m == NULL) { 1034 printf("%s: unable to allocate Tx mbuf\n", 1035 sc->sc_dev.dv_xname); 1036 break; 1037 } 1038 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1039 if (m0->m_pkthdr.len > MHLEN) { 1040 MCLGET(m, M_DONTWAIT); 1041 if ((m->m_flags & M_EXT) == 0) { 1042 printf("%s: unable to allocate Tx " 1043 "cluster\n", sc->sc_dev.dv_xname); 1044 m_freem(m); 1045 break; 1046 } 1047 } 1048 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 1049 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1050 error = bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, 1051 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1052 if (error) { 1053 printf("%s: unable to load Tx buffer, " 1054 "error = %d\n", sc->sc_dev.dv_xname, error); 1055 break; 1056 } 1057 } 1058 1059 /* 1060 * Ensure we have enough descriptors free to describe 1061 * the packet. 1062 */ 1063 if (dmamap->dm_nsegs > sc->sc_txfree) { 1064 /* 1065 * Not enough free descriptors to transmit this 1066 * packet. We haven't committed to anything yet, 1067 * so just unload the DMA map, put the packet 1068 * back on the queue, and punt. Notify the upper 1069 * layer that there are no more slots left. 1070 * 1071 * XXX We could allocate an mbuf and copy, but 1072 * XXX it is worth it? 1073 */ 1074 ifp->if_flags |= IFF_OACTIVE; 1075 bus_dmamap_unload(sc->sc_dmatag, dmamap); 1076 if (m != NULL) 1077 m_freem(m); 1078 break; 1079 } 1080 1081 IFQ_DEQUEUE(&ifp->if_snd, m0); 1082 if (m != NULL) { 1083 m_freem(m0); 1084 m0 = m; 1085 } 1086 1087 /* 1088 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1089 */ 1090 1091 /* Sync the DMA map. */ 1092 bus_dmamap_sync(sc->sc_dmatag, dmamap, 0, dmamap->dm_mapsize, 1093 BUS_DMASYNC_PREWRITE); 1094 1095 /* 1096 * Initialize the transmit descriptors. 1097 */ 1098 for (nexttx = sc->sc_txnext, seg = 0; 1099 seg < dmamap->dm_nsegs; 1100 seg++, nexttx = GEM_NEXTTX(nexttx)) { 1101 uint64_t flags; 1102 1103 /* 1104 * If this is the first descriptor we're 1105 * enqueueing, set the start of packet flag, 1106 * and the checksum stuff if we want the hardware 1107 * to do it. 1108 */ 1109 sc->sc_txdescs[nexttx].gd_addr = 1110 GEM_DMA_WRITE(sc, dmamap->dm_segs[seg].ds_addr); 1111 flags = dmamap->dm_segs[seg].ds_len & GEM_TD_BUFSIZE; 1112 if (nexttx == firsttx) { 1113 flags |= GEM_TD_START_OF_PACKET; 1114 if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) { 1115 sc->sc_txwin = 0; 1116 flags |= GEM_TD_INTERRUPT_ME; 1117 } 1118 } 1119 if (seg == dmamap->dm_nsegs - 1) { 1120 flags |= GEM_TD_END_OF_PACKET; 1121 } 1122 sc->sc_txdescs[nexttx].gd_flags = 1123 GEM_DMA_WRITE(sc, flags); 1124 lasttx = nexttx; 1125 } 1126 1127 KASSERT(lasttx != -1); 1128 1129 #ifdef GEM_DEBUG 1130 if (ifp->if_flags & IFF_DEBUG) { 1131 printf(" gem_start %p transmit chain:\n", txs); 1132 for (seg = sc->sc_txnext;; seg = GEM_NEXTTX(seg)) { 1133 printf("descriptor %d:\t", seg); 1134 printf("gd_flags: 0x%016llx\t", (long long) 1135 GEM_DMA_READ(sc, sc->sc_txdescs[seg].gd_flags)); 1136 printf("gd_addr: 0x%016llx\n", (long long) 1137 GEM_DMA_READ(sc, sc->sc_txdescs[seg].gd_addr)); 1138 if (seg == lasttx) 1139 break; 1140 } 1141 } 1142 #endif 1143 1144 /* Sync the descriptors we're using. */ 1145 GEM_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1146 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1147 1148 /* 1149 * Store a pointer to the packet so we can free it later, 1150 * and remember what txdirty will be once the packet is 1151 * done. 1152 */ 1153 txs->txs_mbuf = m0; 1154 txs->txs_firstdesc = sc->sc_txnext; 1155 txs->txs_lastdesc = lasttx; 1156 txs->txs_ndescs = dmamap->dm_nsegs; 1157 1158 /* Advance the tx pointer. */ 1159 sc->sc_txfree -= dmamap->dm_nsegs; 1160 sc->sc_txnext = nexttx; 1161 1162 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1163 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1164 1165 last_txs = txs; 1166 1167 #if NBPFILTER > 0 1168 /* 1169 * Pass the packet to any BPF listeners. 1170 */ 1171 if (ifp->if_bpf) 1172 bpf_mtap(ifp->if_bpf, m0); 1173 #endif /* NBPFILTER > 0 */ 1174 } 1175 1176 if (txs == NULL || sc->sc_txfree == 0) { 1177 /* No more slots left; notify upper layer. */ 1178 ifp->if_flags |= IFF_OACTIVE; 1179 } 1180 1181 if (sc->sc_txfree != ofree) { 1182 DPRINTF(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 1183 sc->sc_dev.dv_xname, lasttx, firsttx)); 1184 /* 1185 * The entire packet chain is set up. 1186 * Kick the transmitter. 1187 */ 1188 DPRINTF(sc, ("%s: gem_start: kicking tx %d\n", 1189 sc->sc_dev.dv_xname, nexttx)); 1190 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_TX_KICK, 1191 sc->sc_txnext); 1192 1193 /* Set a watchdog timer in case the chip flakes out. */ 1194 ifp->if_timer = 5; 1195 DPRINTF(sc, ("%s: gem_start: watchdog %d\n", 1196 sc->sc_dev.dv_xname, ifp->if_timer)); 1197 } 1198 } 1199 1200 /* 1201 * Transmit interrupt. 1202 */ 1203 int 1204 gem_tint(sc) 1205 struct gem_softc *sc; 1206 { 1207 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1208 bus_space_tag_t t = sc->sc_bustag; 1209 bus_space_handle_t mac = sc->sc_h; 1210 struct gem_txsoft *txs; 1211 int txlast; 1212 int progress = 0; 1213 1214 1215 DPRINTF(sc, ("%s: gem_tint\n", sc->sc_dev.dv_xname)); 1216 1217 /* 1218 * Unload collision counters 1219 */ 1220 ifp->if_collisions += 1221 bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) + 1222 bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT) + 1223 bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) + 1224 bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT); 1225 1226 /* 1227 * then clear the hardware counters. 1228 */ 1229 bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0); 1230 bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0); 1231 bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0); 1232 bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0); 1233 1234 /* 1235 * Go through our Tx list and free mbufs for those 1236 * frames that have been transmitted. 1237 */ 1238 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1239 GEM_CDTXSYNC(sc, txs->txs_lastdesc, 1240 txs->txs_ndescs, 1241 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1242 1243 #ifdef GEM_DEBUG 1244 if (ifp->if_flags & IFF_DEBUG) { 1245 int i; 1246 printf(" txsoft %p transmit chain:\n", txs); 1247 for (i = txs->txs_firstdesc;; i = GEM_NEXTTX(i)) { 1248 printf("descriptor %d: ", i); 1249 printf("gd_flags: 0x%016llx\t", (long long) 1250 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags)); 1251 printf("gd_addr: 0x%016llx\n", (long long) 1252 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr)); 1253 if (i == txs->txs_lastdesc) 1254 break; 1255 } 1256 } 1257 #endif 1258 1259 /* 1260 * In theory, we could harveast some descriptors before 1261 * the ring is empty, but that's a bit complicated. 1262 * 1263 * GEM_TX_COMPLETION points to the last descriptor 1264 * processed +1. 1265 */ 1266 txlast = bus_space_read_4(t, mac, GEM_TX_COMPLETION); 1267 DPRINTF(sc, 1268 ("gem_tint: txs->txs_lastdesc = %d, txlast = %d\n", 1269 txs->txs_lastdesc, txlast)); 1270 if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1271 if ((txlast >= txs->txs_firstdesc) && 1272 (txlast <= txs->txs_lastdesc)) 1273 break; 1274 } else { 1275 /* Ick -- this command wraps */ 1276 if ((txlast >= txs->txs_firstdesc) || 1277 (txlast <= txs->txs_lastdesc)) 1278 break; 1279 } 1280 1281 DPRINTF(sc, ("gem_tint: releasing a desc\n")); 1282 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1283 1284 sc->sc_txfree += txs->txs_ndescs; 1285 1286 if (txs->txs_mbuf == NULL) { 1287 #ifdef DIAGNOSTIC 1288 panic("gem_txintr: null mbuf"); 1289 #endif 1290 } 1291 1292 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 1293 0, txs->txs_dmamap->dm_mapsize, 1294 BUS_DMASYNC_POSTWRITE); 1295 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 1296 m_freem(txs->txs_mbuf); 1297 txs->txs_mbuf = NULL; 1298 1299 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1300 1301 ifp->if_opackets++; 1302 progress = 1; 1303 } 1304 1305 #if 0 1306 DPRINTF(sc, ("gem_tint: GEM_TX_STATE_MACHINE %x " 1307 "GEM_TX_DATA_PTR %llx " 1308 "GEM_TX_COMPLETION %x\n", 1309 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_STATE_MACHINE), 1310 ((long long) bus_space_read_4(sc->sc_bustag, sc->sc_h, 1311 GEM_TX_DATA_PTR_HI) << 32) | 1312 bus_space_read_4(sc->sc_bustag, sc->sc_h, 1313 GEM_TX_DATA_PTR_LO), 1314 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_COMPLETION))); 1315 #endif 1316 1317 if (progress) { 1318 if (sc->sc_txfree == GEM_NTXDESC - 1) 1319 sc->sc_txwin = 0; 1320 1321 ifp->if_flags &= ~IFF_OACTIVE; 1322 gem_start(ifp); 1323 1324 if (SIMPLEQ_EMPTY(&sc->sc_txdirtyq)) 1325 ifp->if_timer = 0; 1326 } 1327 DPRINTF(sc, ("%s: gem_tint: watchdog %d\n", 1328 sc->sc_dev.dv_xname, ifp->if_timer)); 1329 1330 return (1); 1331 } 1332 1333 /* 1334 * Receive interrupt. 1335 */ 1336 int 1337 gem_rint(sc) 1338 struct gem_softc *sc; 1339 { 1340 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1341 bus_space_tag_t t = sc->sc_bustag; 1342 bus_space_handle_t h = sc->sc_h; 1343 struct ether_header *eh; 1344 struct gem_rxsoft *rxs; 1345 struct mbuf *m; 1346 u_int64_t rxstat; 1347 u_int32_t rxcomp; 1348 int i, len, progress = 0; 1349 1350 DPRINTF(sc, ("%s: gem_rint\n", sc->sc_dev.dv_xname)); 1351 1352 /* 1353 * Read the completion register once. This limits 1354 * how long the following loop can execute. 1355 */ 1356 rxcomp = bus_space_read_4(t, h, GEM_RX_COMPLETION); 1357 1358 /* 1359 * XXXX Read the lastrx only once at the top for speed. 1360 */ 1361 DPRINTF(sc, ("gem_rint: sc->rxptr %d, complete %d\n", 1362 sc->sc_rxptr, rxcomp)); 1363 1364 /* 1365 * Go into the loop at least once. 1366 */ 1367 for (i = sc->sc_rxptr; i == sc->sc_rxptr || i != rxcomp; 1368 i = GEM_NEXTRX(i)) { 1369 rxs = &sc->sc_rxsoft[i]; 1370 1371 GEM_CDRXSYNC(sc, i, 1372 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1373 1374 rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags); 1375 1376 if (rxstat & GEM_RD_OWN) { 1377 /* 1378 * We have processed all of the receive buffers. 1379 */ 1380 break; 1381 } 1382 1383 progress++; 1384 ifp->if_ipackets++; 1385 1386 if (rxstat & GEM_RD_BAD_CRC) { 1387 ifp->if_ierrors++; 1388 printf("%s: receive error: CRC error\n", 1389 sc->sc_dev.dv_xname); 1390 GEM_INIT_RXDESC(sc, i); 1391 continue; 1392 } 1393 1394 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1395 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1396 #ifdef GEM_DEBUG 1397 if (ifp->if_flags & IFF_DEBUG) { 1398 printf(" rxsoft %p descriptor %d: ", rxs, i); 1399 printf("gd_flags: 0x%016llx\t", (long long) 1400 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags)); 1401 printf("gd_addr: 0x%016llx\n", (long long) 1402 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr)); 1403 } 1404 #endif 1405 1406 /* 1407 * No errors; receive the packet. Note the Gem 1408 * includes the CRC with every packet. 1409 */ 1410 len = GEM_RD_BUFLEN(rxstat); 1411 1412 /* 1413 * Allocate a new mbuf cluster. If that fails, we are 1414 * out of memory, and must drop the packet and recycle 1415 * the buffer that's already attached to this descriptor. 1416 */ 1417 m = rxs->rxs_mbuf; 1418 if (gem_add_rxbuf(sc, i) != 0) { 1419 GEM_COUNTER_INCR(sc, sc_ev_rxnobuf); 1420 ifp->if_ierrors++; 1421 GEM_INIT_RXDESC(sc, i); 1422 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1423 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1424 continue; 1425 } 1426 m->m_data += 2; /* We're already off by two */ 1427 1428 eh = mtod(m, struct ether_header *); 1429 m->m_flags |= M_HASFCS; 1430 m->m_pkthdr.rcvif = ifp; 1431 m->m_pkthdr.len = m->m_len = len; 1432 1433 #if NBPFILTER > 0 1434 /* 1435 * Pass this up to any BPF listeners, but only 1436 * pass it up the stack if its for us. 1437 */ 1438 if (ifp->if_bpf) 1439 bpf_mtap(ifp->if_bpf, m); 1440 #endif /* NPBFILTER > 0 */ 1441 1442 /* Pass it on. */ 1443 (*ifp->if_input)(ifp, m); 1444 } 1445 1446 if (progress) { 1447 /* Update the receive pointer. */ 1448 if (i == sc->sc_rxptr) { 1449 GEM_COUNTER_INCR(sc, sc_ev_rxfull); 1450 #ifdef GEM_DEBUG 1451 if (ifp->if_flags & IFF_DEBUG) 1452 printf("%s: rint: ring wrap\n", 1453 sc->sc_dev.dv_xname); 1454 #endif 1455 } 1456 sc->sc_rxptr = i; 1457 bus_space_write_4(t, h, GEM_RX_KICK, GEM_PREVRX(i)); 1458 } 1459 #ifdef GEM_COUNTERS 1460 if (progress <= 4) { 1461 GEM_COUNTER_INCR(sc, sc_ev_rxhist[progress]); 1462 } else if (progress < 32) { 1463 if (progress < 16) 1464 GEM_COUNTER_INCR(sc, sc_ev_rxhist[5]); 1465 else 1466 GEM_COUNTER_INCR(sc, sc_ev_rxhist[6]); 1467 1468 } else { 1469 if (progress < 64) 1470 GEM_COUNTER_INCR(sc, sc_ev_rxhist[7]); 1471 else 1472 GEM_COUNTER_INCR(sc, sc_ev_rxhist[8]); 1473 } 1474 #endif 1475 1476 DPRINTF(sc, ("gem_rint: done sc->rxptr %d, complete %d\n", 1477 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION))); 1478 1479 return (1); 1480 } 1481 1482 1483 /* 1484 * gem_add_rxbuf: 1485 * 1486 * Add a receive buffer to the indicated descriptor. 1487 */ 1488 int 1489 gem_add_rxbuf(struct gem_softc *sc, int idx) 1490 { 1491 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1492 struct mbuf *m; 1493 int error; 1494 1495 MGETHDR(m, M_DONTWAIT, MT_DATA); 1496 if (m == NULL) 1497 return (ENOBUFS); 1498 1499 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1500 MCLGET(m, M_DONTWAIT); 1501 if ((m->m_flags & M_EXT) == 0) { 1502 m_freem(m); 1503 return (ENOBUFS); 1504 } 1505 1506 #ifdef GEM_DEBUG 1507 /* bzero the packet to check DMA */ 1508 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 1509 #endif 1510 1511 if (rxs->rxs_mbuf != NULL) 1512 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 1513 1514 rxs->rxs_mbuf = m; 1515 1516 error = bus_dmamap_load(sc->sc_dmatag, rxs->rxs_dmamap, 1517 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1518 BUS_DMA_READ|BUS_DMA_NOWAIT); 1519 if (error) { 1520 printf("%s: can't load rx DMA map %d, error = %d\n", 1521 sc->sc_dev.dv_xname, idx, error); 1522 panic("gem_add_rxbuf"); /* XXX */ 1523 } 1524 1525 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1526 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1527 1528 GEM_INIT_RXDESC(sc, idx); 1529 1530 return (0); 1531 } 1532 1533 1534 int 1535 gem_eint(sc, status) 1536 struct gem_softc *sc; 1537 u_int status; 1538 { 1539 char bits[128]; 1540 1541 if ((status & GEM_INTR_MIF) != 0) { 1542 printf("%s: XXXlink status changed\n", sc->sc_dev.dv_xname); 1543 return (1); 1544 } 1545 1546 printf("%s: status=%s\n", sc->sc_dev.dv_xname, 1547 bitmask_snprintf(status, GEM_INTR_BITS, bits, sizeof(bits))); 1548 return (1); 1549 } 1550 1551 1552 int 1553 gem_intr(v) 1554 void *v; 1555 { 1556 struct gem_softc *sc = (struct gem_softc *)v; 1557 bus_space_tag_t t = sc->sc_bustag; 1558 bus_space_handle_t seb = sc->sc_h; 1559 u_int32_t status; 1560 int r = 0; 1561 #ifdef GEM_DEBUG 1562 char bits[128]; 1563 #endif 1564 1565 sc->sc_ev_intr.ev_count++; 1566 1567 status = bus_space_read_4(t, seb, GEM_STATUS); 1568 DPRINTF(sc, ("%s: gem_intr: cplt 0x%x status %s\n", 1569 sc->sc_dev.dv_xname, (status >> 19), 1570 bitmask_snprintf(status, GEM_INTR_BITS, bits, sizeof(bits)))); 1571 1572 if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0) 1573 r |= gem_eint(sc, status); 1574 1575 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) { 1576 GEM_COUNTER_INCR(sc, sc_ev_txint); 1577 r |= gem_tint(sc); 1578 } 1579 1580 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) { 1581 GEM_COUNTER_INCR(sc, sc_ev_rxint); 1582 r |= gem_rint(sc); 1583 } 1584 1585 /* We should eventually do more than just print out error stats. */ 1586 if (status & GEM_INTR_TX_MAC) { 1587 int txstat = bus_space_read_4(t, seb, GEM_MAC_TX_STATUS); 1588 if (txstat & ~GEM_MAC_TX_XMIT_DONE) 1589 printf("%s: MAC tx fault, status %x\n", 1590 sc->sc_dev.dv_xname, txstat); 1591 } 1592 if (status & GEM_INTR_RX_MAC) { 1593 int rxstat = bus_space_read_4(t, seb, GEM_MAC_RX_STATUS); 1594 if (rxstat & ~GEM_MAC_RX_DONE) 1595 printf("%s: MAC rx fault, status %x\n", 1596 sc->sc_dev.dv_xname, rxstat); 1597 } 1598 return (r); 1599 } 1600 1601 1602 void 1603 gem_watchdog(ifp) 1604 struct ifnet *ifp; 1605 { 1606 struct gem_softc *sc = ifp->if_softc; 1607 1608 DPRINTF(sc, ("gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x " 1609 "GEM_MAC_RX_CONFIG %x\n", 1610 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_CONFIG), 1611 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_STATUS), 1612 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_CONFIG))); 1613 1614 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1615 ++ifp->if_oerrors; 1616 1617 /* Try to get more packets going. */ 1618 gem_start(ifp); 1619 } 1620 1621 /* 1622 * Initialize the MII Management Interface 1623 */ 1624 void 1625 gem_mifinit(sc) 1626 struct gem_softc *sc; 1627 { 1628 bus_space_tag_t t = sc->sc_bustag; 1629 bus_space_handle_t mif = sc->sc_h; 1630 1631 /* Configure the MIF in frame mode */ 1632 sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1633 sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA; 1634 bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config); 1635 } 1636 1637 /* 1638 * MII interface 1639 * 1640 * The GEM MII interface supports at least three different operating modes: 1641 * 1642 * Bitbang mode is implemented using data, clock and output enable registers. 1643 * 1644 * Frame mode is implemented by loading a complete frame into the frame 1645 * register and polling the valid bit for completion. 1646 * 1647 * Polling mode uses the frame register but completion is indicated by 1648 * an interrupt. 1649 * 1650 */ 1651 static int 1652 gem_mii_readreg(self, phy, reg) 1653 struct device *self; 1654 int phy, reg; 1655 { 1656 struct gem_softc *sc = (void *)self; 1657 bus_space_tag_t t = sc->sc_bustag; 1658 bus_space_handle_t mif = sc->sc_h; 1659 int n; 1660 u_int32_t v; 1661 1662 #ifdef GEM_DEBUG1 1663 if (sc->sc_debug) 1664 printf("gem_mii_readreg: phy %d reg %d\n", phy, reg); 1665 #endif 1666 1667 #if 0 1668 /* Select the desired PHY in the MIF configuration register */ 1669 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1670 /* Clear PHY select bit */ 1671 v &= ~GEM_MIF_CONFIG_PHY_SEL; 1672 if (phy == GEM_PHYAD_EXTERNAL) 1673 /* Set PHY select bit to get at external device */ 1674 v |= GEM_MIF_CONFIG_PHY_SEL; 1675 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 1676 #endif 1677 1678 /* Construct the frame command */ 1679 v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) | 1680 GEM_MIF_FRAME_READ; 1681 1682 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1683 for (n = 0; n < 100; n++) { 1684 DELAY(1); 1685 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1686 if (v & GEM_MIF_FRAME_TA0) 1687 return (v & GEM_MIF_FRAME_DATA); 1688 } 1689 1690 printf("%s: mii_read timeout\n", sc->sc_dev.dv_xname); 1691 return (0); 1692 } 1693 1694 static void 1695 gem_mii_writereg(self, phy, reg, val) 1696 struct device *self; 1697 int phy, reg, val; 1698 { 1699 struct gem_softc *sc = (void *)self; 1700 bus_space_tag_t t = sc->sc_bustag; 1701 bus_space_handle_t mif = sc->sc_h; 1702 int n; 1703 u_int32_t v; 1704 1705 #ifdef GEM_DEBUG1 1706 if (sc->sc_debug) 1707 printf("gem_mii_writereg: phy %d reg %d val %x\n", 1708 phy, reg, val); 1709 #endif 1710 1711 #if 0 1712 /* Select the desired PHY in the MIF configuration register */ 1713 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1714 /* Clear PHY select bit */ 1715 v &= ~GEM_MIF_CONFIG_PHY_SEL; 1716 if (phy == GEM_PHYAD_EXTERNAL) 1717 /* Set PHY select bit to get at external device */ 1718 v |= GEM_MIF_CONFIG_PHY_SEL; 1719 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 1720 #endif 1721 /* Construct the frame command */ 1722 v = GEM_MIF_FRAME_WRITE | 1723 (phy << GEM_MIF_PHY_SHIFT) | 1724 (reg << GEM_MIF_REG_SHIFT) | 1725 (val & GEM_MIF_FRAME_DATA); 1726 1727 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1728 for (n = 0; n < 100; n++) { 1729 DELAY(1); 1730 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1731 if (v & GEM_MIF_FRAME_TA0) 1732 return; 1733 } 1734 1735 printf("%s: mii_write timeout\n", sc->sc_dev.dv_xname); 1736 } 1737 1738 static void 1739 gem_mii_statchg(dev) 1740 struct device *dev; 1741 { 1742 struct gem_softc *sc = (void *)dev; 1743 #ifdef GEM_DEBUG 1744 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1745 #endif 1746 bus_space_tag_t t = sc->sc_bustag; 1747 bus_space_handle_t mac = sc->sc_h; 1748 u_int32_t v; 1749 1750 #ifdef GEM_DEBUG 1751 if (sc->sc_debug) 1752 printf("gem_mii_statchg: status change: phy = %d\n", 1753 sc->sc_phys[instance]); 1754 #endif 1755 1756 1757 /* Set tx full duplex options */ 1758 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0); 1759 delay(10000); /* reg must be cleared and delay before changing. */ 1760 v = GEM_MAC_TX_ENA_IPG0|GEM_MAC_TX_NGU|GEM_MAC_TX_NGU_LIMIT| 1761 GEM_MAC_TX_ENABLE; 1762 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) { 1763 v |= GEM_MAC_TX_IGN_CARRIER|GEM_MAC_TX_IGN_COLLIS; 1764 } 1765 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, v); 1766 1767 /* XIF Configuration */ 1768 /* We should really calculate all this rather than rely on defaults */ 1769 v = bus_space_read_4(t, mac, GEM_MAC_XIF_CONFIG); 1770 v = GEM_MAC_XIF_LINK_LED; 1771 v |= GEM_MAC_XIF_TX_MII_ENA; 1772 1773 /* If an external transceiver is connected, enable its MII drivers */ 1774 sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG); 1775 if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) { 1776 /* External MII needs echo disable if half duplex. */ 1777 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1778 /* turn on full duplex LED */ 1779 v |= GEM_MAC_XIF_FDPLX_LED; 1780 else 1781 /* half duplex -- disable echo */ 1782 v |= GEM_MAC_XIF_ECHO_DISABL; 1783 1784 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 1785 v |= GEM_MAC_XIF_GMII_MODE; 1786 else 1787 v &= ~GEM_MAC_XIF_GMII_MODE; 1788 } else 1789 /* Internal MII needs buf enable */ 1790 v |= GEM_MAC_XIF_MII_BUF_ENA; 1791 bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v); 1792 } 1793 1794 int 1795 gem_mediachange(ifp) 1796 struct ifnet *ifp; 1797 { 1798 struct gem_softc *sc = ifp->if_softc; 1799 1800 if (IFM_TYPE(sc->sc_media.ifm_media) != IFM_ETHER) 1801 return (EINVAL); 1802 1803 return (mii_mediachg(&sc->sc_mii)); 1804 } 1805 1806 void 1807 gem_mediastatus(ifp, ifmr) 1808 struct ifnet *ifp; 1809 struct ifmediareq *ifmr; 1810 { 1811 struct gem_softc *sc = ifp->if_softc; 1812 1813 if ((ifp->if_flags & IFF_UP) == 0) 1814 return; 1815 1816 mii_pollstat(&sc->sc_mii); 1817 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1818 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1819 } 1820 1821 int gem_ioctldebug = 0; 1822 /* 1823 * Process an ioctl request. 1824 */ 1825 int 1826 gem_ioctl(ifp, cmd, data) 1827 struct ifnet *ifp; 1828 u_long cmd; 1829 caddr_t data; 1830 { 1831 struct gem_softc *sc = ifp->if_softc; 1832 struct ifreq *ifr = (struct ifreq *)data; 1833 int s, error = 0; 1834 1835 s = splnet(); 1836 1837 switch (cmd) { 1838 case SIOCGIFMEDIA: 1839 case SIOCSIFMEDIA: 1840 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1841 break; 1842 1843 default: 1844 error = ether_ioctl(ifp, cmd, data); 1845 if (error == ENETRESET) { 1846 /* 1847 * Multicast list has changed; set the hardware filter 1848 * accordingly. 1849 */ 1850 if (gem_ioctldebug) printf("reset1\n"); 1851 gem_init(ifp); 1852 delay(50000); 1853 error = 0; 1854 } 1855 break; 1856 } 1857 1858 /* Try to get things going again */ 1859 if (ifp->if_flags & IFF_UP) { 1860 if (gem_ioctldebug) printf("start\n"); 1861 gem_start(ifp); 1862 } 1863 splx(s); 1864 return (error); 1865 } 1866 1867 1868 void 1869 gem_shutdown(arg) 1870 void *arg; 1871 { 1872 struct gem_softc *sc = (struct gem_softc *)arg; 1873 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1874 1875 gem_stop(ifp, 1); 1876 } 1877 1878 /* 1879 * Set up the logical address filter. 1880 */ 1881 void 1882 gem_setladrf(sc) 1883 struct gem_softc *sc; 1884 { 1885 struct ethercom *ec = &sc->sc_ethercom; 1886 struct ifnet *ifp = &ec->ec_if; 1887 struct ether_multi *enm; 1888 struct ether_multistep step; 1889 bus_space_tag_t t = sc->sc_bustag; 1890 bus_space_handle_t h = sc->sc_h; 1891 u_int32_t crc; 1892 u_int32_t hash[16]; 1893 u_int32_t v; 1894 int i; 1895 1896 /* Get current RX configuration */ 1897 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 1898 1899 /* 1900 * Turn off promiscuous mode, promiscuous group mode (all multicast), 1901 * and hash filter. Depending on the case, the right bit will be 1902 * enabled. 1903 */ 1904 v &= ~(GEM_MAC_RX_PROMISCUOUS|GEM_MAC_RX_HASH_FILTER| 1905 GEM_MAC_RX_PROMISC_GRP); 1906 1907 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1908 /* Turn on promiscuous mode */ 1909 v |= GEM_MAC_RX_PROMISCUOUS; 1910 ifp->if_flags |= IFF_ALLMULTI; 1911 goto chipit; 1912 } 1913 1914 /* 1915 * Set up multicast address filter by passing all multicast addresses 1916 * through a crc generator, and then using the high order 8 bits as an 1917 * index into the 256 bit logical address filter. The high order 4 1918 * bits select the word, while the other 4 bits select the bit within 1919 * the word (where bit 0 is the MSB). 1920 */ 1921 1922 /* Clear hash table */ 1923 memset(hash, 0, sizeof(hash)); 1924 1925 ETHER_FIRST_MULTI(step, ec, enm); 1926 while (enm != NULL) { 1927 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1928 /* 1929 * We must listen to a range of multicast addresses. 1930 * For now, just accept all multicasts, rather than 1931 * trying to set only those filter bits needed to match 1932 * the range. (At this time, the only use of address 1933 * ranges is for IP multicast routing, for which the 1934 * range is big enough to require all bits set.) 1935 * XXX use the addr filter for this 1936 */ 1937 ifp->if_flags |= IFF_ALLMULTI; 1938 v |= GEM_MAC_RX_PROMISC_GRP; 1939 goto chipit; 1940 } 1941 1942 /* Get the LE CRC32 of the address */ 1943 crc = ether_crc32_le(enm->enm_addrlo, sizeof(enm->enm_addrlo)); 1944 1945 /* Just want the 8 most significant bits. */ 1946 crc >>= 24; 1947 1948 /* Set the corresponding bit in the filter. */ 1949 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 1950 1951 ETHER_NEXT_MULTI(step, enm); 1952 } 1953 1954 v |= GEM_MAC_RX_HASH_FILTER; 1955 ifp->if_flags &= ~IFF_ALLMULTI; 1956 1957 /* Now load the hash table into the chip (if we are using it) */ 1958 for (i = 0; i < 16; i++) { 1959 bus_space_write_4(t, h, 1960 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1-GEM_MAC_HASH0), 1961 hash[i]); 1962 } 1963 1964 chipit: 1965 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 1966 } 1967 1968 #if notyet 1969 1970 /* 1971 * gem_power: 1972 * 1973 * Power management (suspend/resume) hook. 1974 */ 1975 void 1976 gem_power(why, arg) 1977 int why; 1978 void *arg; 1979 { 1980 struct gem_softc *sc = arg; 1981 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1982 int s; 1983 1984 s = splnet(); 1985 switch (why) { 1986 case PWR_SUSPEND: 1987 case PWR_STANDBY: 1988 gem_stop(ifp, 1); 1989 if (sc->sc_power != NULL) 1990 (*sc->sc_power)(sc, why); 1991 break; 1992 case PWR_RESUME: 1993 if (ifp->if_flags & IFF_UP) { 1994 if (sc->sc_power != NULL) 1995 (*sc->sc_power)(sc, why); 1996 gem_init(ifp); 1997 } 1998 break; 1999 case PWR_SOFTSUSPEND: 2000 case PWR_SOFTSTANDBY: 2001 case PWR_SOFTRESUME: 2002 break; 2003 } 2004 splx(s); 2005 } 2006 #endif 2007
Indexes created Tue Sep 23 14:10:03 GMT 2025