gem.c revision 1.48
1 /* $NetBSD: gem.c,v 1.48 2006/09/24 03:53:08 jmcneill Exp $ */ 2 3 /* 4 * 5 * Copyright (C) 2001 Eduardo Horvath. 6 * All rights reserved. 7 * 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 */ 31 32 /* 33 * Driver for Sun GEM ethernet controllers. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: gem.c,v 1.48 2006/09/24 03:53:08 jmcneill Exp $"); 38 39 #include "opt_inet.h" 40 #include "bpfilter.h" 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/callout.h> 45 #include <sys/mbuf.h> 46 #include <sys/syslog.h> 47 #include <sys/malloc.h> 48 #include <sys/kernel.h> 49 #include <sys/socket.h> 50 #include <sys/ioctl.h> 51 #include <sys/errno.h> 52 #include <sys/device.h> 53 54 #include <machine/endian.h> 55 56 #include <uvm/uvm_extern.h> 57 58 #include <net/if.h> 59 #include <net/if_dl.h> 60 #include <net/if_media.h> 61 #include <net/if_ether.h> 62 63 #ifdef INET 64 #include <netinet/in.h> 65 #include <netinet/in_systm.h> 66 #include <netinet/in_var.h> 67 #include <netinet/ip.h> 68 #include <netinet/tcp.h> 69 #include <netinet/udp.h> 70 #endif 71 72 #if NBPFILTER > 0 73 #include <net/bpf.h> 74 #endif 75 76 #include <machine/bus.h> 77 #include <machine/intr.h> 78 79 #include <dev/mii/mii.h> 80 #include <dev/mii/miivar.h> 81 #include <dev/mii/mii_bitbang.h> 82 83 #include <dev/ic/gemreg.h> 84 #include <dev/ic/gemvar.h> 85 86 #define TRIES 10000 87 88 static void gem_start(struct ifnet *); 89 static void gem_stop(struct ifnet *, int); 90 int gem_ioctl(struct ifnet *, u_long, caddr_t); 91 void gem_tick(void *); 92 void gem_watchdog(struct ifnet *); 93 void gem_shutdown(void *); 94 int gem_init(struct ifnet *); 95 void gem_init_regs(struct gem_softc *sc); 96 static int gem_ringsize(int sz); 97 static int gem_meminit(struct gem_softc *); 98 void gem_mifinit(struct gem_softc *); 99 static int gem_bitwait(struct gem_softc *sc, int, u_int32_t, u_int32_t); 100 void gem_reset(struct gem_softc *); 101 int gem_reset_rx(struct gem_softc *sc); 102 int gem_reset_tx(struct gem_softc *sc); 103 int gem_disable_rx(struct gem_softc *sc); 104 int gem_disable_tx(struct gem_softc *sc); 105 static void gem_rxdrain(struct gem_softc *sc); 106 int gem_add_rxbuf(struct gem_softc *sc, int idx); 107 void gem_setladrf(struct gem_softc *); 108 109 /* MII methods & callbacks */ 110 static int gem_mii_readreg(struct device *, int, int); 111 static void gem_mii_writereg(struct device *, int, int, int); 112 static void gem_mii_statchg(struct device *); 113 114 int gem_mediachange(struct ifnet *); 115 void gem_mediastatus(struct ifnet *, struct ifmediareq *); 116 117 struct mbuf *gem_get(struct gem_softc *, int, int); 118 int gem_put(struct gem_softc *, int, struct mbuf *); 119 void gem_read(struct gem_softc *, int, int); 120 int gem_eint(struct gem_softc *, u_int); 121 int gem_rint(struct gem_softc *); 122 int gem_tint(struct gem_softc *); 123 void gem_power(int, void *); 124 125 #ifdef GEM_DEBUG 126 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 127 printf x 128 #else 129 #define DPRINTF(sc, x) /* nothing */ 130 #endif 131 132 #define ETHER_MIN_TX (ETHERMIN + sizeof(struct ether_header)) 133 134 135 /* 136 * gem_attach: 137 * 138 * Attach a Gem interface to the system. 139 */ 140 void 141 gem_attach(sc, enaddr) 142 struct gem_softc *sc; 143 const uint8_t *enaddr; 144 { 145 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 146 struct mii_data *mii = &sc->sc_mii; 147 struct mii_softc *child; 148 struct ifmedia_entry *ifm; 149 int i, error; 150 u_int32_t v; 151 char *nullbuf; 152 153 /* Make sure the chip is stopped. */ 154 ifp->if_softc = sc; 155 gem_reset(sc); 156 157 /* 158 * Allocate the control data structures, and create and load the 159 * DMA map for it. gem_control_data is 9216 bytes, we have space for 160 * the padding buffer in the bus_dmamem_alloc()'d memory. 161 */ 162 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 163 sizeof(struct gem_control_data) + ETHER_MIN_TX, PAGE_SIZE, 164 0, &sc->sc_cdseg, 1, &sc->sc_cdnseg, 0)) != 0) { 165 aprint_error( 166 "%s: unable to allocate control data, error = %d\n", 167 sc->sc_dev.dv_xname, error); 168 goto fail_0; 169 } 170 171 /* XXX should map this in with correct endianness */ 172 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg, 173 sizeof(struct gem_control_data), (caddr_t *)&sc->sc_control_data, 174 BUS_DMA_COHERENT)) != 0) { 175 aprint_error("%s: unable to map control data, error = %d\n", 176 sc->sc_dev.dv_xname, error); 177 goto fail_1; 178 } 179 180 nullbuf = 181 (caddr_t)sc->sc_control_data + sizeof(struct gem_control_data); 182 183 if ((error = bus_dmamap_create(sc->sc_dmatag, 184 sizeof(struct gem_control_data), 1, 185 sizeof(struct gem_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 186 aprint_error("%s: unable to create control data DMA map, " 187 "error = %d\n", sc->sc_dev.dv_xname, error); 188 goto fail_2; 189 } 190 191 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 192 sc->sc_control_data, sizeof(struct gem_control_data), NULL, 193 0)) != 0) { 194 aprint_error( 195 "%s: unable to load control data DMA map, error = %d\n", 196 sc->sc_dev.dv_xname, error); 197 goto fail_3; 198 } 199 200 memset(nullbuf, 0, ETHER_MIN_TX); 201 if ((error = bus_dmamap_create(sc->sc_dmatag, 202 ETHER_MIN_TX, 1, ETHER_MIN_TX, 0, 0, &sc->sc_nulldmamap)) != 0) { 203 aprint_error("%s: unable to create padding DMA map, " 204 "error = %d\n", sc->sc_dev.dv_xname, error); 205 goto fail_4; 206 } 207 208 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_nulldmamap, 209 nullbuf, ETHER_MIN_TX, NULL, 0)) != 0) { 210 aprint_error( 211 "%s: unable to load padding DMA map, error = %d\n", 212 sc->sc_dev.dv_xname, error); 213 goto fail_5; 214 } 215 216 bus_dmamap_sync(sc->sc_dmatag, sc->sc_nulldmamap, 0, ETHER_MIN_TX, 217 BUS_DMASYNC_PREWRITE); 218 219 /* 220 * Initialize the transmit job descriptors. 221 */ 222 SIMPLEQ_INIT(&sc->sc_txfreeq); 223 SIMPLEQ_INIT(&sc->sc_txdirtyq); 224 225 /* 226 * Create the transmit buffer DMA maps. 227 */ 228 for (i = 0; i < GEM_TXQUEUELEN; i++) { 229 struct gem_txsoft *txs; 230 231 txs = &sc->sc_txsoft[i]; 232 txs->txs_mbuf = NULL; 233 if ((error = bus_dmamap_create(sc->sc_dmatag, 234 ETHER_MAX_LEN_JUMBO, GEM_NTXSEGS, 235 ETHER_MAX_LEN_JUMBO, 0, 0, 236 &txs->txs_dmamap)) != 0) { 237 aprint_error("%s: unable to create tx DMA map %d, " 238 "error = %d\n", sc->sc_dev.dv_xname, i, error); 239 goto fail_6; 240 } 241 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 242 } 243 244 /* 245 * Create the receive buffer DMA maps. 246 */ 247 for (i = 0; i < GEM_NRXDESC; i++) { 248 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, 249 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 250 aprint_error("%s: unable to create rx DMA map %d, " 251 "error = %d\n", sc->sc_dev.dv_xname, i, error); 252 goto fail_7; 253 } 254 sc->sc_rxsoft[i].rxs_mbuf = NULL; 255 } 256 257 /* 258 * From this point forward, the attachment cannot fail. A failure 259 * before this point releases all resources that may have been 260 * allocated. 261 */ 262 263 /* Announce ourselves. */ 264 aprint_normal("%s: Ethernet address %s", sc->sc_dev.dv_xname, 265 ether_sprintf(enaddr)); 266 267 /* Get RX FIFO size */ 268 sc->sc_rxfifosize = 64 * 269 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_FIFO_SIZE); 270 aprint_normal(", %uKB RX fifo", sc->sc_rxfifosize / 1024); 271 272 /* Get TX FIFO size */ 273 v = bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_FIFO_SIZE); 274 aprint_normal(", %uKB TX fifo\n", v / 16); 275 276 /* Initialize ifnet structure. */ 277 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 278 ifp->if_softc = sc; 279 ifp->if_flags = 280 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 281 sc->sc_if_flags = ifp->if_flags; 282 ifp->if_capabilities |= 283 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 284 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 285 ifp->if_start = gem_start; 286 ifp->if_ioctl = gem_ioctl; 287 ifp->if_watchdog = gem_watchdog; 288 ifp->if_stop = gem_stop; 289 ifp->if_init = gem_init; 290 IFQ_SET_READY(&ifp->if_snd); 291 292 /* Initialize ifmedia structures and MII info */ 293 mii->mii_ifp = ifp; 294 mii->mii_readreg = gem_mii_readreg; 295 mii->mii_writereg = gem_mii_writereg; 296 mii->mii_statchg = gem_mii_statchg; 297 298 ifmedia_init(&mii->mii_media, IFM_IMASK, gem_mediachange, gem_mediastatus); 299 300 gem_mifinit(sc); 301 302 #if defined (PMAC_G5) 303 mii_attach(&sc->sc_dev, mii, 0xffffffff, 304 1, MII_OFFSET_ANY, MIIF_FORCEANEG); 305 #else 306 mii_attach(&sc->sc_dev, mii, 0xffffffff, 307 MII_PHY_ANY, MII_OFFSET_ANY, MIIF_FORCEANEG); 308 #endif 309 310 child = LIST_FIRST(&mii->mii_phys); 311 if (child == NULL) { 312 /* No PHY attached */ 313 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 314 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 315 } else { 316 /* 317 * Walk along the list of attached MII devices and 318 * establish an `MII instance' to `phy number' 319 * mapping. We'll use this mapping in media change 320 * requests to determine which phy to use to program 321 * the MIF configuration register. 322 */ 323 for (; child != NULL; child = LIST_NEXT(child, mii_list)) { 324 /* 325 * Note: we support just two PHYs: the built-in 326 * internal device and an external on the MII 327 * connector. 328 */ 329 if (child->mii_phy > 1 || child->mii_inst > 1) { 330 aprint_error( 331 "%s: cannot accomodate MII device %s" 332 " at phy %d, instance %d\n", 333 sc->sc_dev.dv_xname, 334 child->mii_dev.dv_xname, 335 child->mii_phy, child->mii_inst); 336 continue; 337 } 338 339 sc->sc_phys[child->mii_inst] = child->mii_phy; 340 } 341 342 /* 343 * Now select and activate the PHY we will use. 344 * 345 * The order of preference is External (MDI1), 346 * Internal (MDI0), Serial Link (no MII). 347 */ 348 if (sc->sc_phys[1]) { 349 #ifdef GEM_DEBUG 350 aprint_debug("using external phy\n"); 351 #endif 352 sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL; 353 } else { 354 #ifdef GEM_DEBUG 355 aprint_debug("using internal phy\n"); 356 #endif 357 sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL; 358 } 359 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_MIF_CONFIG, 360 sc->sc_mif_config); 361 362 /* 363 * XXX - we can really do the following ONLY if the 364 * phy indeed has the auto negotiation capability!! 365 */ 366 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO); 367 } 368 369 /* 370 * If we support GigE media, we support jumbo frames too. 371 * Unless we are Apple. 372 */ 373 TAILQ_FOREACH(ifm, &sc->sc_media.ifm_list, ifm_list) { 374 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_T || 375 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_SX || 376 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_LX || 377 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_CX) { 378 if (sc->sc_variant != GEM_APPLE_GMAC) 379 sc->sc_ethercom.ec_capabilities 380 |= ETHERCAP_JUMBO_MTU; 381 382 sc->sc_flags |= GEM_GIGABIT; 383 break; 384 } 385 } 386 387 /* claim 802.1q capability */ 388 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 389 390 /* Attach the interface. */ 391 if_attach(ifp); 392 ether_ifattach(ifp, enaddr); 393 394 sc->sc_sh = shutdownhook_establish(gem_shutdown, sc); 395 if (sc->sc_sh == NULL) 396 panic("gem_config: can't establish shutdownhook"); 397 398 #if NRND > 0 399 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 400 RND_TYPE_NET, 0); 401 #endif 402 403 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, 404 NULL, sc->sc_dev.dv_xname, "interrupts"); 405 #ifdef GEM_COUNTERS 406 evcnt_attach_dynamic(&sc->sc_ev_txint, EVCNT_TYPE_INTR, 407 &sc->sc_ev_intr, sc->sc_dev.dv_xname, "tx interrupts"); 408 evcnt_attach_dynamic(&sc->sc_ev_rxint, EVCNT_TYPE_INTR, 409 &sc->sc_ev_intr, sc->sc_dev.dv_xname, "rx interrupts"); 410 evcnt_attach_dynamic(&sc->sc_ev_rxfull, EVCNT_TYPE_INTR, 411 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx ring full"); 412 evcnt_attach_dynamic(&sc->sc_ev_rxnobuf, EVCNT_TYPE_INTR, 413 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx malloc failure"); 414 evcnt_attach_dynamic(&sc->sc_ev_rxhist[0], EVCNT_TYPE_INTR, 415 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 0desc"); 416 evcnt_attach_dynamic(&sc->sc_ev_rxhist[1], EVCNT_TYPE_INTR, 417 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 1desc"); 418 evcnt_attach_dynamic(&sc->sc_ev_rxhist[2], EVCNT_TYPE_INTR, 419 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 2desc"); 420 evcnt_attach_dynamic(&sc->sc_ev_rxhist[3], EVCNT_TYPE_INTR, 421 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 3desc"); 422 evcnt_attach_dynamic(&sc->sc_ev_rxhist[4], EVCNT_TYPE_INTR, 423 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >3desc"); 424 evcnt_attach_dynamic(&sc->sc_ev_rxhist[5], EVCNT_TYPE_INTR, 425 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >7desc"); 426 evcnt_attach_dynamic(&sc->sc_ev_rxhist[6], EVCNT_TYPE_INTR, 427 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >15desc"); 428 evcnt_attach_dynamic(&sc->sc_ev_rxhist[7], EVCNT_TYPE_INTR, 429 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >31desc"); 430 evcnt_attach_dynamic(&sc->sc_ev_rxhist[8], EVCNT_TYPE_INTR, 431 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >63desc"); 432 #endif 433 434 #if notyet 435 /* 436 * Add a suspend hook to make sure we come back up after a 437 * resume. 438 */ 439 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 440 gem_power, sc); 441 if (sc->sc_powerhook == NULL) 442 aprint_error("%s: WARNING: unable to establish power hook\n", 443 sc->sc_dev.dv_xname); 444 #endif 445 446 callout_init(&sc->sc_tick_ch); 447 return; 448 449 /* 450 * Free any resources we've allocated during the failed attach 451 * attempt. Do this in reverse order and fall through. 452 */ 453 fail_7: 454 for (i = 0; i < GEM_NRXDESC; i++) { 455 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 456 bus_dmamap_destroy(sc->sc_dmatag, 457 sc->sc_rxsoft[i].rxs_dmamap); 458 } 459 fail_6: 460 for (i = 0; i < GEM_TXQUEUELEN; i++) { 461 if (sc->sc_txsoft[i].txs_dmamap != NULL) 462 bus_dmamap_destroy(sc->sc_dmatag, 463 sc->sc_txsoft[i].txs_dmamap); 464 } 465 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 466 fail_5: 467 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_nulldmamap); 468 fail_4: 469 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)nullbuf, ETHER_MIN_TX); 470 fail_3: 471 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 472 fail_2: 473 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)sc->sc_control_data, 474 sizeof(struct gem_control_data)); 475 fail_1: 476 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 477 fail_0: 478 return; 479 } 480 481 482 void 483 gem_tick(arg) 484 void *arg; 485 { 486 struct gem_softc *sc = arg; 487 int s; 488 489 s = splnet(); 490 mii_tick(&sc->sc_mii); 491 splx(s); 492 493 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 494 495 } 496 497 static int 498 gem_bitwait(sc, r, clr, set) 499 struct gem_softc *sc; 500 int r; 501 u_int32_t clr; 502 u_int32_t set; 503 { 504 int i; 505 u_int32_t reg; 506 507 for (i = TRIES; i--; DELAY(100)) { 508 reg = bus_space_read_4(sc->sc_bustag, sc->sc_h, r); 509 if ((r & clr) == 0 && (r & set) == set) 510 return (1); 511 } 512 return (0); 513 } 514 515 void 516 gem_reset(sc) 517 struct gem_softc *sc; 518 { 519 bus_space_tag_t t = sc->sc_bustag; 520 bus_space_handle_t h = sc->sc_h; 521 int s; 522 523 s = splnet(); 524 DPRINTF(sc, ("%s: gem_reset\n", sc->sc_dev.dv_xname)); 525 gem_reset_rx(sc); 526 gem_reset_tx(sc); 527 528 /* Do a full reset */ 529 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX|GEM_RESET_TX); 530 if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0)) 531 printf("%s: cannot reset device\n", sc->sc_dev.dv_xname); 532 splx(s); 533 } 534 535 536 /* 537 * gem_rxdrain: 538 * 539 * Drain the receive queue. 540 */ 541 static void 542 gem_rxdrain(struct gem_softc *sc) 543 { 544 struct gem_rxsoft *rxs; 545 int i; 546 547 for (i = 0; i < GEM_NRXDESC; i++) { 548 rxs = &sc->sc_rxsoft[i]; 549 if (rxs->rxs_mbuf != NULL) { 550 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 551 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 552 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 553 m_freem(rxs->rxs_mbuf); 554 rxs->rxs_mbuf = NULL; 555 } 556 } 557 } 558 559 /* 560 * Reset the whole thing. 561 */ 562 static void 563 gem_stop(struct ifnet *ifp, int disable) 564 { 565 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 566 struct gem_txsoft *txs; 567 568 DPRINTF(sc, ("%s: gem_stop\n", sc->sc_dev.dv_xname)); 569 570 callout_stop(&sc->sc_tick_ch); 571 mii_down(&sc->sc_mii); 572 573 /* XXX - Should we reset these instead? */ 574 gem_disable_rx(sc); 575 gem_disable_tx(sc); 576 577 /* 578 * Release any queued transmit buffers. 579 */ 580 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 581 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 582 if (txs->txs_mbuf != NULL) { 583 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 0, 584 txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 585 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 586 m_freem(txs->txs_mbuf); 587 txs->txs_mbuf = NULL; 588 } 589 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 590 } 591 592 if (disable) { 593 gem_rxdrain(sc); 594 } 595 596 /* 597 * Mark the interface down and cancel the watchdog timer. 598 */ 599 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 600 sc->sc_if_flags = ifp->if_flags; 601 ifp->if_timer = 0; 602 } 603 604 605 /* 606 * Reset the receiver 607 */ 608 int 609 gem_reset_rx(struct gem_softc *sc) 610 { 611 bus_space_tag_t t = sc->sc_bustag; 612 bus_space_handle_t h = sc->sc_h; 613 614 /* 615 * Resetting while DMA is in progress can cause a bus hang, so we 616 * disable DMA first. 617 */ 618 gem_disable_rx(sc); 619 bus_space_write_4(t, h, GEM_RX_CONFIG, 0); 620 /* Wait till it finishes */ 621 if (!gem_bitwait(sc, GEM_RX_CONFIG, 1, 0)) 622 printf("%s: cannot disable read dma\n", sc->sc_dev.dv_xname); 623 /* Wait 5ms extra. */ 624 delay(5000); 625 626 /* Finally, reset the ERX */ 627 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX); 628 /* Wait till it finishes */ 629 if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_TX, 0)) { 630 printf("%s: cannot reset receiver\n", sc->sc_dev.dv_xname); 631 return (1); 632 } 633 return (0); 634 } 635 636 637 /* 638 * Reset the transmitter 639 */ 640 int 641 gem_reset_tx(struct gem_softc *sc) 642 { 643 bus_space_tag_t t = sc->sc_bustag; 644 bus_space_handle_t h = sc->sc_h; 645 646 /* 647 * Resetting while DMA is in progress can cause a bus hang, so we 648 * disable DMA first. 649 */ 650 gem_disable_tx(sc); 651 bus_space_write_4(t, h, GEM_TX_CONFIG, 0); 652 /* Wait till it finishes */ 653 if (!gem_bitwait(sc, GEM_TX_CONFIG, 1, 0)) 654 printf("%s: cannot disable read dma\n", sc->sc_dev.dv_xname); 655 /* Wait 5ms extra. */ 656 delay(5000); 657 658 /* Finally, reset the ETX */ 659 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_TX); 660 /* Wait till it finishes */ 661 if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_TX, 0)) { 662 printf("%s: cannot reset receiver\n", 663 sc->sc_dev.dv_xname); 664 return (1); 665 } 666 return (0); 667 } 668 669 /* 670 * disable receiver. 671 */ 672 int 673 gem_disable_rx(struct gem_softc *sc) 674 { 675 bus_space_tag_t t = sc->sc_bustag; 676 bus_space_handle_t h = sc->sc_h; 677 u_int32_t cfg; 678 679 /* Flip the enable bit */ 680 cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 681 cfg &= ~GEM_MAC_RX_ENABLE; 682 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg); 683 684 /* Wait for it to finish */ 685 return (gem_bitwait(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)); 686 } 687 688 /* 689 * disable transmitter. 690 */ 691 int 692 gem_disable_tx(struct gem_softc *sc) 693 { 694 bus_space_tag_t t = sc->sc_bustag; 695 bus_space_handle_t h = sc->sc_h; 696 u_int32_t cfg; 697 698 /* Flip the enable bit */ 699 cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG); 700 cfg &= ~GEM_MAC_TX_ENABLE; 701 bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg); 702 703 /* Wait for it to finish */ 704 return (gem_bitwait(sc, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)); 705 } 706 707 /* 708 * Initialize interface. 709 */ 710 int 711 gem_meminit(struct gem_softc *sc) 712 { 713 struct gem_rxsoft *rxs; 714 int i, error; 715 716 /* 717 * Initialize the transmit descriptor ring. 718 */ 719 memset((void *)sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 720 for (i = 0; i < GEM_NTXDESC; i++) { 721 sc->sc_txdescs[i].gd_flags = 0; 722 sc->sc_txdescs[i].gd_addr = 0; 723 } 724 GEM_CDTXSYNC(sc, 0, GEM_NTXDESC, 725 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 726 sc->sc_txfree = GEM_NTXDESC-1; 727 sc->sc_txnext = 0; 728 sc->sc_txwin = 0; 729 730 /* 731 * Initialize the receive descriptor and receive job 732 * descriptor rings. 733 */ 734 for (i = 0; i < GEM_NRXDESC; i++) { 735 rxs = &sc->sc_rxsoft[i]; 736 if (rxs->rxs_mbuf == NULL) { 737 if ((error = gem_add_rxbuf(sc, i)) != 0) { 738 printf("%s: unable to allocate or map rx " 739 "buffer %d, error = %d\n", 740 sc->sc_dev.dv_xname, i, error); 741 /* 742 * XXX Should attempt to run with fewer receive 743 * XXX buffers instead of just failing. 744 */ 745 gem_rxdrain(sc); 746 return (1); 747 } 748 } else 749 GEM_INIT_RXDESC(sc, i); 750 } 751 sc->sc_rxptr = 0; 752 753 return (0); 754 } 755 756 static int 757 gem_ringsize(int sz) 758 { 759 switch (sz) { 760 case 32: 761 return GEM_RING_SZ_32; 762 case 64: 763 return GEM_RING_SZ_64; 764 case 128: 765 return GEM_RING_SZ_128; 766 case 256: 767 return GEM_RING_SZ_256; 768 case 512: 769 return GEM_RING_SZ_512; 770 case 1024: 771 return GEM_RING_SZ_1024; 772 case 2048: 773 return GEM_RING_SZ_2048; 774 case 4096: 775 return GEM_RING_SZ_4096; 776 case 8192: 777 return GEM_RING_SZ_8192; 778 default: 779 printf("gem: invalid Receive Descriptor ring size %d\n", sz); 780 return GEM_RING_SZ_32; 781 } 782 } 783 784 /* 785 * Initialization of interface; set up initialization block 786 * and transmit/receive descriptor rings. 787 */ 788 int 789 gem_init(struct ifnet *ifp) 790 { 791 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 792 bus_space_tag_t t = sc->sc_bustag; 793 bus_space_handle_t h = sc->sc_h; 794 int s; 795 u_int max_frame_size; 796 u_int32_t v; 797 798 s = splnet(); 799 800 DPRINTF(sc, ("%s: gem_init: calling stop\n", sc->sc_dev.dv_xname)); 801 /* 802 * Initialization sequence. The numbered steps below correspond 803 * to the sequence outlined in section 6.3.5.1 in the Ethernet 804 * Channel Engine manual (part of the PCIO manual). 805 * See also the STP2002-STQ document from Sun Microsystems. 806 */ 807 808 /* step 1 & 2. Reset the Ethernet Channel */ 809 gem_stop(ifp, 0); 810 gem_reset(sc); 811 DPRINTF(sc, ("%s: gem_init: restarting\n", sc->sc_dev.dv_xname)); 812 813 /* Re-initialize the MIF */ 814 gem_mifinit(sc); 815 816 /* Call MI reset function if any */ 817 if (sc->sc_hwreset) 818 (*sc->sc_hwreset)(sc); 819 820 /* step 3. Setup data structures in host memory */ 821 gem_meminit(sc); 822 823 /* step 4. TX MAC registers & counters */ 824 gem_init_regs(sc); 825 max_frame_size = max(sc->sc_ethercom.ec_if.if_mtu, ETHERMTU); 826 max_frame_size += ETHER_HDR_LEN + ETHER_CRC_LEN; 827 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 828 max_frame_size += ETHER_VLAN_ENCAP_LEN; 829 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 830 max_frame_size|/* burst size */(0x2000<<16)); 831 832 /* step 5. RX MAC registers & counters */ 833 gem_setladrf(sc); 834 835 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 836 /* NOTE: we use only 32-bit DMA addresses here. */ 837 bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 0); 838 bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 839 840 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0); 841 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 842 843 /* step 8. Global Configuration & Interrupt Mask */ 844 bus_space_write_4(t, h, GEM_INTMASK, 845 ~(GEM_INTR_TX_INTME| 846 GEM_INTR_TX_EMPTY| 847 GEM_INTR_RX_DONE|GEM_INTR_RX_NOBUF| 848 GEM_INTR_RX_TAG_ERR|GEM_INTR_PCS| 849 GEM_INTR_MAC_CONTROL|GEM_INTR_MIF| 850 GEM_INTR_BERR)); 851 bus_space_write_4(t, h, GEM_MAC_RX_MASK, 852 GEM_MAC_RX_DONE|GEM_MAC_RX_FRAME_CNT); 853 bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXXX */ 854 bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 0); /* XXXX */ 855 856 /* step 9. ETX Configuration: use mostly default values */ 857 858 /* Enable DMA */ 859 v = gem_ringsize(GEM_NTXDESC /*XXX*/); 860 bus_space_write_4(t, h, GEM_TX_CONFIG, 861 v|GEM_TX_CONFIG_TXDMA_EN| 862 ((0x400<<10)&GEM_TX_CONFIG_TXFIFO_TH)); 863 bus_space_write_4(t, h, GEM_TX_KICK, sc->sc_txnext); 864 865 /* step 10. ERX Configuration */ 866 867 /* Encode Receive Descriptor ring size: four possible values */ 868 v = gem_ringsize(GEM_NRXDESC /*XXX*/); 869 870 /* Set receive h/w checksum offset */ 871 #ifdef INET 872 v |= (ETHER_HDR_LEN + sizeof(struct ip) + 873 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 874 ETHER_VLAN_ENCAP_LEN : 0)) << GEM_RX_CONFIG_CXM_START_SHFT; 875 #endif 876 877 /* Enable DMA */ 878 bus_space_write_4(t, h, GEM_RX_CONFIG, 879 v|(GEM_THRSH_1024<<GEM_RX_CONFIG_FIFO_THRS_SHIFT)| 880 (2<<GEM_RX_CONFIG_FBOFF_SHFT)|GEM_RX_CONFIG_RXDMA_EN); 881 882 /* 883 * The following value is for an OFF Threshold of about 3/4 full 884 * and an ON Threshold of 1/4 full. 885 */ 886 bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH, 887 (3 * sc->sc_rxfifosize / 256) | 888 ( (sc->sc_rxfifosize / 256) << 12)); 889 bus_space_write_4(t, h, GEM_RX_BLANKING, (6<<12)|6); 890 891 /* step 11. Configure Media */ 892 mii_mediachg(&sc->sc_mii); 893 894 /* XXXX Serial link needs a whole different setup. */ 895 896 897 /* step 12. RX_MAC Configuration Register */ 898 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 899 v |= GEM_MAC_RX_ENABLE | GEM_MAC_RX_STRIP_CRC; 900 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 901 902 /* step 14. Issue Transmit Pending command */ 903 904 /* Call MI initialization function if any */ 905 if (sc->sc_hwinit) 906 (*sc->sc_hwinit)(sc); 907 908 909 /* step 15. Give the reciever a swift kick */ 910 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4); 911 912 /* Start the one second timer. */ 913 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 914 915 ifp->if_flags |= IFF_RUNNING; 916 ifp->if_flags &= ~IFF_OACTIVE; 917 ifp->if_timer = 0; 918 sc->sc_if_flags = ifp->if_flags; 919 splx(s); 920 921 return (0); 922 } 923 924 void 925 gem_init_regs(struct gem_softc *sc) 926 { 927 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 928 bus_space_tag_t t = sc->sc_bustag; 929 bus_space_handle_t h = sc->sc_h; 930 const u_char *laddr = LLADDR(ifp->if_sadl); 931 u_int32_t v; 932 933 /* These regs are not cleared on reset */ 934 if (!sc->sc_inited) { 935 936 /* Wooo. Magic values. */ 937 bus_space_write_4(t, h, GEM_MAC_IPG0, 0); 938 bus_space_write_4(t, h, GEM_MAC_IPG1, 8); 939 bus_space_write_4(t, h, GEM_MAC_IPG2, 4); 940 941 bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 942 /* Max frame and max burst size */ 943 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 944 ETHER_MAX_LEN | (0x2000<<16)); 945 946 bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x7); 947 bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x4); 948 bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10); 949 /* Dunno.... */ 950 bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088); 951 bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED, 952 ((laddr[5]<<8)|laddr[4])&0x3ff); 953 954 /* Secondary MAC addr set to 0:0:0:0:0:0 */ 955 bus_space_write_4(t, h, GEM_MAC_ADDR3, 0); 956 bus_space_write_4(t, h, GEM_MAC_ADDR4, 0); 957 bus_space_write_4(t, h, GEM_MAC_ADDR5, 0); 958 959 /* MAC control addr set to 01:80:c2:00:00:01 */ 960 bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001); 961 bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200); 962 bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180); 963 964 /* MAC filter addr set to 0:0:0:0:0:0 */ 965 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0); 966 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0); 967 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0); 968 969 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0); 970 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0); 971 972 sc->sc_inited = 1; 973 } 974 975 /* Counters need to be zeroed */ 976 bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0); 977 bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0); 978 bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0); 979 bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0); 980 bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0); 981 bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0); 982 bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0); 983 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 984 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 985 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 986 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 987 988 /* Un-pause stuff */ 989 #if 0 990 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); 991 #else 992 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0); 993 #endif 994 995 /* 996 * Set the station address. 997 */ 998 bus_space_write_4(t, h, GEM_MAC_ADDR0, (laddr[4]<<8)|laddr[5]); 999 bus_space_write_4(t, h, GEM_MAC_ADDR1, (laddr[2]<<8)|laddr[3]); 1000 bus_space_write_4(t, h, GEM_MAC_ADDR2, (laddr[0]<<8)|laddr[1]); 1001 1002 #if 0 1003 if (sc->sc_variant != APPLE_GMAC) 1004 return; 1005 #endif 1006 1007 /* 1008 * Enable MII outputs. Enable GMII if there is a gigabit PHY. 1009 */ 1010 sc->sc_mif_config = bus_space_read_4(t, h, GEM_MIF_CONFIG); 1011 v = GEM_MAC_XIF_TX_MII_ENA; 1012 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) { 1013 v |= GEM_MAC_XIF_FDPLX_LED; 1014 if (sc->sc_flags & GEM_GIGABIT) 1015 v |= GEM_MAC_XIF_GMII_MODE; 1016 } 1017 bus_space_write_4(t, h, GEM_MAC_XIF_CONFIG, v); 1018 } 1019 1020 static void 1021 gem_start(ifp) 1022 struct ifnet *ifp; 1023 { 1024 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 1025 struct mbuf *m0, *m; 1026 struct gem_txsoft *txs, *last_txs; 1027 bus_dmamap_t dmamap; 1028 int error, firsttx, nexttx, lasttx = -1, ofree, seg; 1029 uint64_t flags = 0; 1030 1031 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1032 return; 1033 1034 /* 1035 * Remember the previous number of free descriptors and 1036 * the first descriptor we'll use. 1037 */ 1038 ofree = sc->sc_txfree; 1039 firsttx = sc->sc_txnext; 1040 1041 DPRINTF(sc, ("%s: gem_start: txfree %d, txnext %d\n", 1042 sc->sc_dev.dv_xname, ofree, firsttx)); 1043 1044 /* 1045 * Loop through the send queue, setting up transmit descriptors 1046 * until we drain the queue, or use up all available transmit 1047 * descriptors. 1048 */ 1049 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 1050 sc->sc_txfree != 0) { 1051 /* 1052 * Grab a packet off the queue. 1053 */ 1054 IFQ_POLL(&ifp->if_snd, m0); 1055 if (m0 == NULL) 1056 break; 1057 m = NULL; 1058 1059 dmamap = txs->txs_dmamap; 1060 1061 /* 1062 * Load the DMA map. If this fails, the packet either 1063 * didn't fit in the alloted number of segments, or we were 1064 * short on resources. In this case, we'll copy and try 1065 * again. 1066 */ 1067 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m0, 1068 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0 || 1069 (m0->m_pkthdr.len < ETHER_MIN_TX && 1070 dmamap->dm_nsegs == GEM_NTXSEGS)) { 1071 if (m0->m_pkthdr.len > MCLBYTES) { 1072 printf("%s: unable to allocate jumbo Tx " 1073 "cluster\n", sc->sc_dev.dv_xname); 1074 IFQ_DEQUEUE(&ifp->if_snd, m0); 1075 m_freem(m0); 1076 continue; 1077 } 1078 MGETHDR(m, M_DONTWAIT, MT_DATA); 1079 if (m == NULL) { 1080 printf("%s: unable to allocate Tx mbuf\n", 1081 sc->sc_dev.dv_xname); 1082 break; 1083 } 1084 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1085 if (m0->m_pkthdr.len > MHLEN) { 1086 MCLGET(m, M_DONTWAIT); 1087 if ((m->m_flags & M_EXT) == 0) { 1088 printf("%s: unable to allocate Tx " 1089 "cluster\n", sc->sc_dev.dv_xname); 1090 m_freem(m); 1091 break; 1092 } 1093 } 1094 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 1095 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1096 error = bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, 1097 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1098 if (error) { 1099 printf("%s: unable to load Tx buffer, " 1100 "error = %d\n", sc->sc_dev.dv_xname, error); 1101 break; 1102 } 1103 } 1104 1105 /* 1106 * Ensure we have enough descriptors free to describe 1107 * the packet. 1108 */ 1109 if (dmamap->dm_nsegs > ((m0->m_pkthdr.len < ETHER_MIN_TX) ? 1110 (sc->sc_txfree - 1) : sc->sc_txfree)) { 1111 /* 1112 * Not enough free descriptors to transmit this 1113 * packet. We haven't committed to anything yet, 1114 * so just unload the DMA map, put the packet 1115 * back on the queue, and punt. Notify the upper 1116 * layer that there are no more slots left. 1117 * 1118 * XXX We could allocate an mbuf and copy, but 1119 * XXX it is worth it? 1120 */ 1121 ifp->if_flags |= IFF_OACTIVE; 1122 sc->sc_if_flags = ifp->if_flags; 1123 bus_dmamap_unload(sc->sc_dmatag, dmamap); 1124 if (m != NULL) 1125 m_freem(m); 1126 break; 1127 } 1128 1129 IFQ_DEQUEUE(&ifp->if_snd, m0); 1130 if (m != NULL) { 1131 m_freem(m0); 1132 m0 = m; 1133 } 1134 1135 /* 1136 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1137 */ 1138 1139 /* Sync the DMA map. */ 1140 bus_dmamap_sync(sc->sc_dmatag, dmamap, 0, dmamap->dm_mapsize, 1141 BUS_DMASYNC_PREWRITE); 1142 1143 /* 1144 * Initialize the transmit descriptors. 1145 */ 1146 for (nexttx = sc->sc_txnext, seg = 0; 1147 seg < dmamap->dm_nsegs; 1148 seg++, nexttx = GEM_NEXTTX(nexttx)) { 1149 1150 /* 1151 * If this is the first descriptor we're 1152 * enqueueing, set the start of packet flag, 1153 * and the checksum stuff if we want the hardware 1154 * to do it. 1155 */ 1156 sc->sc_txdescs[nexttx].gd_addr = 1157 GEM_DMA_WRITE(sc, dmamap->dm_segs[seg].ds_addr); 1158 flags = dmamap->dm_segs[seg].ds_len & GEM_TD_BUFSIZE; 1159 if (nexttx == firsttx) { 1160 flags |= GEM_TD_START_OF_PACKET; 1161 if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) { 1162 sc->sc_txwin = 0; 1163 flags |= GEM_TD_INTERRUPT_ME; 1164 } 1165 1166 #ifdef INET 1167 /* h/w checksum */ 1168 if (ifp->if_csum_flags_tx & (M_CSUM_TCPv4 | 1169 M_CSUM_UDPv4) && m0->m_pkthdr.csum_flags & 1170 (M_CSUM_TCPv4|M_CSUM_UDPv4)) { 1171 struct ether_header *eh; 1172 uint16_t offset, start; 1173 1174 eh = mtod(m0, struct ether_header *); 1175 switch (ntohs(eh->ether_type)) { 1176 case ETHERTYPE_IP: 1177 start = ETHER_HDR_LEN; 1178 break; 1179 case ETHERTYPE_VLAN: 1180 start = ETHER_HDR_LEN + 1181 ETHER_VLAN_ENCAP_LEN; 1182 break; 1183 default: 1184 /* unsupported, drop it */ 1185 m_free(m0); 1186 continue; 1187 } 1188 start += M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 1189 offset = M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data) + start; 1190 flags |= (start << 1191 GEM_TD_CXSUM_STARTSHFT) | 1192 (offset << 1193 GEM_TD_CXSUM_STUFFSHFT) | 1194 GEM_TD_CXSUM_ENABLE; 1195 } 1196 #endif 1197 } 1198 if (seg == dmamap->dm_nsegs - 1) { 1199 flags |= GEM_TD_END_OF_PACKET; 1200 } else { 1201 /* last flag set outside of loop */ 1202 sc->sc_txdescs[nexttx].gd_flags = 1203 GEM_DMA_WRITE(sc, flags); 1204 } 1205 lasttx = nexttx; 1206 } 1207 if (m0->m_pkthdr.len < ETHER_MIN_TX) { 1208 /* add padding buffer at end of chain */ 1209 flags &= ~GEM_TD_END_OF_PACKET; 1210 sc->sc_txdescs[lasttx].gd_flags = 1211 GEM_DMA_WRITE(sc, flags); 1212 1213 sc->sc_txdescs[nexttx].gd_addr = 1214 GEM_DMA_WRITE(sc, 1215 sc->sc_nulldmamap->dm_segs[0].ds_addr); 1216 flags = ((ETHER_MIN_TX - m0->m_pkthdr.len) & 1217 GEM_TD_BUFSIZE) | GEM_TD_END_OF_PACKET; 1218 lasttx = nexttx; 1219 nexttx = GEM_NEXTTX(nexttx); 1220 seg++; 1221 } 1222 sc->sc_txdescs[lasttx].gd_flags = GEM_DMA_WRITE(sc, flags); 1223 1224 KASSERT(lasttx != -1); 1225 1226 /* 1227 * Store a pointer to the packet so we can free it later, 1228 * and remember what txdirty will be once the packet is 1229 * done. 1230 */ 1231 txs->txs_mbuf = m0; 1232 txs->txs_firstdesc = sc->sc_txnext; 1233 txs->txs_lastdesc = lasttx; 1234 txs->txs_ndescs = seg; 1235 1236 #ifdef GEM_DEBUG 1237 if (ifp->if_flags & IFF_DEBUG) { 1238 printf(" gem_start %p transmit chain:\n", txs); 1239 for (seg = sc->sc_txnext;; seg = GEM_NEXTTX(seg)) { 1240 printf("descriptor %d:\t", seg); 1241 printf("gd_flags: 0x%016llx\t", (long long) 1242 GEM_DMA_READ(sc, sc->sc_txdescs[seg].gd_flags)); 1243 printf("gd_addr: 0x%016llx\n", (long long) 1244 GEM_DMA_READ(sc, sc->sc_txdescs[seg].gd_addr)); 1245 if (seg == lasttx) 1246 break; 1247 } 1248 } 1249 #endif 1250 1251 /* Sync the descriptors we're using. */ 1252 GEM_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1253 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1254 1255 /* Advance the tx pointer. */ 1256 sc->sc_txfree -= txs->txs_ndescs; 1257 sc->sc_txnext = nexttx; 1258 1259 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1260 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1261 1262 last_txs = txs; 1263 1264 #if NBPFILTER > 0 1265 /* 1266 * Pass the packet to any BPF listeners. 1267 */ 1268 if (ifp->if_bpf) 1269 bpf_mtap(ifp->if_bpf, m0); 1270 #endif /* NBPFILTER > 0 */ 1271 } 1272 1273 if (txs == NULL || sc->sc_txfree == 0) { 1274 /* No more slots left; notify upper layer. */ 1275 ifp->if_flags |= IFF_OACTIVE; 1276 sc->sc_if_flags = ifp->if_flags; 1277 } 1278 1279 if (sc->sc_txfree != ofree) { 1280 DPRINTF(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 1281 sc->sc_dev.dv_xname, lasttx, firsttx)); 1282 /* 1283 * The entire packet chain is set up. 1284 * Kick the transmitter. 1285 */ 1286 DPRINTF(sc, ("%s: gem_start: kicking tx %d\n", 1287 sc->sc_dev.dv_xname, nexttx)); 1288 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_TX_KICK, 1289 sc->sc_txnext); 1290 1291 /* Set a watchdog timer in case the chip flakes out. */ 1292 ifp->if_timer = 5; 1293 DPRINTF(sc, ("%s: gem_start: watchdog %d\n", 1294 sc->sc_dev.dv_xname, ifp->if_timer)); 1295 } 1296 } 1297 1298 /* 1299 * Transmit interrupt. 1300 */ 1301 int 1302 gem_tint(sc) 1303 struct gem_softc *sc; 1304 { 1305 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1306 bus_space_tag_t t = sc->sc_bustag; 1307 bus_space_handle_t mac = sc->sc_h; 1308 struct gem_txsoft *txs; 1309 int txlast; 1310 int progress = 0; 1311 1312 1313 DPRINTF(sc, ("%s: gem_tint\n", sc->sc_dev.dv_xname)); 1314 1315 /* 1316 * Unload collision counters 1317 */ 1318 ifp->if_collisions += 1319 bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) + 1320 bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT) + 1321 bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) + 1322 bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT); 1323 1324 /* 1325 * then clear the hardware counters. 1326 */ 1327 bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0); 1328 bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0); 1329 bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0); 1330 bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0); 1331 1332 /* 1333 * Go through our Tx list and free mbufs for those 1334 * frames that have been transmitted. 1335 */ 1336 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1337 GEM_CDTXSYNC(sc, txs->txs_lastdesc, 1338 txs->txs_ndescs, 1339 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1340 1341 #ifdef GEM_DEBUG 1342 if (ifp->if_flags & IFF_DEBUG) { 1343 int i; 1344 printf(" txsoft %p transmit chain:\n", txs); 1345 for (i = txs->txs_firstdesc;; i = GEM_NEXTTX(i)) { 1346 printf("descriptor %d: ", i); 1347 printf("gd_flags: 0x%016llx\t", (long long) 1348 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags)); 1349 printf("gd_addr: 0x%016llx\n", (long long) 1350 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr)); 1351 if (i == txs->txs_lastdesc) 1352 break; 1353 } 1354 } 1355 #endif 1356 1357 /* 1358 * In theory, we could harveast some descriptors before 1359 * the ring is empty, but that's a bit complicated. 1360 * 1361 * GEM_TX_COMPLETION points to the last descriptor 1362 * processed +1. 1363 */ 1364 txlast = bus_space_read_4(t, mac, GEM_TX_COMPLETION); 1365 DPRINTF(sc, 1366 ("gem_tint: txs->txs_lastdesc = %d, txlast = %d\n", 1367 txs->txs_lastdesc, txlast)); 1368 if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1369 if ((txlast >= txs->txs_firstdesc) && 1370 (txlast <= txs->txs_lastdesc)) 1371 break; 1372 } else { 1373 /* Ick -- this command wraps */ 1374 if ((txlast >= txs->txs_firstdesc) || 1375 (txlast <= txs->txs_lastdesc)) 1376 break; 1377 } 1378 1379 DPRINTF(sc, ("gem_tint: releasing a desc\n")); 1380 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1381 1382 sc->sc_txfree += txs->txs_ndescs; 1383 1384 if (txs->txs_mbuf == NULL) { 1385 #ifdef DIAGNOSTIC 1386 panic("gem_txintr: null mbuf"); 1387 #endif 1388 } 1389 1390 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 1391 0, txs->txs_dmamap->dm_mapsize, 1392 BUS_DMASYNC_POSTWRITE); 1393 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 1394 m_freem(txs->txs_mbuf); 1395 txs->txs_mbuf = NULL; 1396 1397 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1398 1399 ifp->if_opackets++; 1400 progress = 1; 1401 } 1402 1403 #if 0 1404 DPRINTF(sc, ("gem_tint: GEM_TX_STATE_MACHINE %x " 1405 "GEM_TX_DATA_PTR %llx " 1406 "GEM_TX_COMPLETION %x\n", 1407 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_STATE_MACHINE), 1408 ((long long) bus_space_read_4(sc->sc_bustag, sc->sc_h, 1409 GEM_TX_DATA_PTR_HI) << 32) | 1410 bus_space_read_4(sc->sc_bustag, sc->sc_h, 1411 GEM_TX_DATA_PTR_LO), 1412 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_COMPLETION))); 1413 #endif 1414 1415 if (progress) { 1416 if (sc->sc_txfree == GEM_NTXDESC - 1) 1417 sc->sc_txwin = 0; 1418 1419 ifp->if_flags &= ~IFF_OACTIVE; 1420 sc->sc_if_flags = ifp->if_flags; 1421 gem_start(ifp); 1422 1423 if (SIMPLEQ_EMPTY(&sc->sc_txdirtyq)) 1424 ifp->if_timer = 0; 1425 } 1426 DPRINTF(sc, ("%s: gem_tint: watchdog %d\n", 1427 sc->sc_dev.dv_xname, ifp->if_timer)); 1428 1429 return (1); 1430 } 1431 1432 /* 1433 * Receive interrupt. 1434 */ 1435 int 1436 gem_rint(sc) 1437 struct gem_softc *sc; 1438 { 1439 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1440 bus_space_tag_t t = sc->sc_bustag; 1441 bus_space_handle_t h = sc->sc_h; 1442 struct gem_rxsoft *rxs; 1443 struct mbuf *m; 1444 u_int64_t rxstat; 1445 u_int32_t rxcomp; 1446 int i, len, progress = 0; 1447 1448 DPRINTF(sc, ("%s: gem_rint\n", sc->sc_dev.dv_xname)); 1449 1450 /* 1451 * Read the completion register once. This limits 1452 * how long the following loop can execute. 1453 */ 1454 rxcomp = bus_space_read_4(t, h, GEM_RX_COMPLETION); 1455 1456 /* 1457 * XXXX Read the lastrx only once at the top for speed. 1458 */ 1459 DPRINTF(sc, ("gem_rint: sc->rxptr %d, complete %d\n", 1460 sc->sc_rxptr, rxcomp)); 1461 1462 /* 1463 * Go into the loop at least once. 1464 */ 1465 for (i = sc->sc_rxptr; i == sc->sc_rxptr || i != rxcomp; 1466 i = GEM_NEXTRX(i)) { 1467 rxs = &sc->sc_rxsoft[i]; 1468 1469 GEM_CDRXSYNC(sc, i, 1470 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1471 1472 rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags); 1473 1474 if (rxstat & GEM_RD_OWN) { 1475 /* 1476 * We have processed all of the receive buffers. 1477 */ 1478 break; 1479 } 1480 1481 progress++; 1482 ifp->if_ipackets++; 1483 1484 if (rxstat & GEM_RD_BAD_CRC) { 1485 ifp->if_ierrors++; 1486 printf("%s: receive error: CRC error\n", 1487 sc->sc_dev.dv_xname); 1488 GEM_INIT_RXDESC(sc, i); 1489 continue; 1490 } 1491 1492 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1493 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1494 #ifdef GEM_DEBUG 1495 if (ifp->if_flags & IFF_DEBUG) { 1496 printf(" rxsoft %p descriptor %d: ", rxs, i); 1497 printf("gd_flags: 0x%016llx\t", (long long) 1498 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags)); 1499 printf("gd_addr: 0x%016llx\n", (long long) 1500 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr)); 1501 } 1502 #endif 1503 1504 /* No errors; receive the packet. */ 1505 len = GEM_RD_BUFLEN(rxstat); 1506 1507 /* 1508 * Allocate a new mbuf cluster. If that fails, we are 1509 * out of memory, and must drop the packet and recycle 1510 * the buffer that's already attached to this descriptor. 1511 */ 1512 m = rxs->rxs_mbuf; 1513 if (gem_add_rxbuf(sc, i) != 0) { 1514 GEM_COUNTER_INCR(sc, sc_ev_rxnobuf); 1515 ifp->if_ierrors++; 1516 GEM_INIT_RXDESC(sc, i); 1517 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1518 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1519 continue; 1520 } 1521 m->m_data += 2; /* We're already off by two */ 1522 1523 m->m_pkthdr.rcvif = ifp; 1524 m->m_pkthdr.len = m->m_len = len; 1525 1526 #if NBPFILTER > 0 1527 /* 1528 * Pass this up to any BPF listeners, but only 1529 * pass it up the stack if its for us. 1530 */ 1531 if (ifp->if_bpf) 1532 bpf_mtap(ifp->if_bpf, m); 1533 #endif /* NPBFILTER > 0 */ 1534 1535 #ifdef INET 1536 /* hardware checksum */ 1537 if (ifp->if_csum_flags_rx & (M_CSUM_UDPv4 | M_CSUM_TCPv4)) { 1538 struct ether_header *eh; 1539 struct ip *ip; 1540 struct udphdr *uh; 1541 int32_t hlen, pktlen; 1542 1543 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1544 pktlen = m->m_pkthdr.len - ETHER_HDR_LEN - 1545 ETHER_VLAN_ENCAP_LEN; 1546 eh = (struct ether_header *) mtod(m, caddr_t) + 1547 ETHER_VLAN_ENCAP_LEN; 1548 } else { 1549 pktlen = m->m_pkthdr.len - ETHER_HDR_LEN; 1550 eh = mtod(m, struct ether_header *); 1551 } 1552 if (ntohs(eh->ether_type) != ETHERTYPE_IP) 1553 goto swcsum; 1554 ip = (struct ip *) ((caddr_t)eh + ETHER_HDR_LEN); 1555 1556 /* IPv4 only */ 1557 if (ip->ip_v != IPVERSION) 1558 goto swcsum; 1559 1560 hlen = ip->ip_hl << 2; 1561 if (hlen < sizeof(struct ip)) 1562 goto swcsum; 1563 1564 /* 1565 * bail if too short, has random trailing garbage, 1566 * truncated, fragment, or has ethernet pad. 1567 */ 1568 if ((ntohs(ip->ip_len) < hlen) || 1569 (ntohs(ip->ip_len) != pktlen) || 1570 (ntohs(ip->ip_off) & (IP_MF | IP_OFFMASK))) 1571 goto swcsum; 1572 1573 switch (ip->ip_p) { 1574 case IPPROTO_TCP: 1575 if (! (ifp->if_csum_flags_rx & M_CSUM_TCPv4)) 1576 goto swcsum; 1577 if (pktlen < (hlen + sizeof(struct tcphdr))) 1578 goto swcsum; 1579 m->m_pkthdr.csum_flags = M_CSUM_TCPv4; 1580 break; 1581 case IPPROTO_UDP: 1582 if (! (ifp->if_csum_flags_rx & M_CSUM_UDPv4)) 1583 goto swcsum; 1584 if (pktlen < (hlen + sizeof(struct udphdr))) 1585 goto swcsum; 1586 uh = (struct udphdr *)((caddr_t)ip + hlen); 1587 /* no checksum */ 1588 if (uh->uh_sum == 0) 1589 goto swcsum; 1590 m->m_pkthdr.csum_flags = M_CSUM_UDPv4; 1591 break; 1592 default: 1593 goto swcsum; 1594 } 1595 1596 /* the uncomplemented sum is expected */ 1597 m->m_pkthdr.csum_data = (~rxstat) & GEM_RD_CHECKSUM; 1598 1599 /* if the pkt had ip options, we have to deduct them */ 1600 if (hlen > sizeof(struct ip)) { 1601 uint16_t *opts; 1602 uint32_t optsum, temp; 1603 1604 optsum = 0; 1605 temp = hlen - sizeof(struct ip); 1606 opts = (uint16_t *) ((caddr_t) ip + 1607 sizeof(struct ip)); 1608 1609 while (temp > 1) { 1610 optsum += ntohs(*opts++); 1611 temp -= 2; 1612 } 1613 while (optsum >> 16) 1614 optsum = (optsum >> 16) + 1615 (optsum & 0xffff); 1616 1617 /* Deduct ip opts sum from hwsum (rfc 1624). */ 1618 m->m_pkthdr.csum_data = 1619 ~((~m->m_pkthdr.csum_data) - ~optsum); 1620 1621 while (m->m_pkthdr.csum_data >> 16) 1622 m->m_pkthdr.csum_data = 1623 (m->m_pkthdr.csum_data >> 16) + 1624 (m->m_pkthdr.csum_data & 1625 0xffff); 1626 } 1627 1628 m->m_pkthdr.csum_flags |= M_CSUM_DATA | 1629 M_CSUM_NO_PSEUDOHDR; 1630 } else 1631 swcsum: 1632 m->m_pkthdr.csum_flags = 0; 1633 #endif 1634 /* Pass it on. */ 1635 (*ifp->if_input)(ifp, m); 1636 } 1637 1638 if (progress) { 1639 /* Update the receive pointer. */ 1640 if (i == sc->sc_rxptr) { 1641 GEM_COUNTER_INCR(sc, sc_ev_rxfull); 1642 #ifdef GEM_DEBUG 1643 if (ifp->if_flags & IFF_DEBUG) 1644 printf("%s: rint: ring wrap\n", 1645 sc->sc_dev.dv_xname); 1646 #endif 1647 } 1648 sc->sc_rxptr = i; 1649 bus_space_write_4(t, h, GEM_RX_KICK, GEM_PREVRX(i)); 1650 } 1651 #ifdef GEM_COUNTERS 1652 if (progress <= 4) { 1653 GEM_COUNTER_INCR(sc, sc_ev_rxhist[progress]); 1654 } else if (progress < 32) { 1655 if (progress < 16) 1656 GEM_COUNTER_INCR(sc, sc_ev_rxhist[5]); 1657 else 1658 GEM_COUNTER_INCR(sc, sc_ev_rxhist[6]); 1659 1660 } else { 1661 if (progress < 64) 1662 GEM_COUNTER_INCR(sc, sc_ev_rxhist[7]); 1663 else 1664 GEM_COUNTER_INCR(sc, sc_ev_rxhist[8]); 1665 } 1666 #endif 1667 1668 DPRINTF(sc, ("gem_rint: done sc->rxptr %d, complete %d\n", 1669 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION))); 1670 1671 return (1); 1672 } 1673 1674 1675 /* 1676 * gem_add_rxbuf: 1677 * 1678 * Add a receive buffer to the indicated descriptor. 1679 */ 1680 int 1681 gem_add_rxbuf(struct gem_softc *sc, int idx) 1682 { 1683 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1684 struct mbuf *m; 1685 int error; 1686 1687 MGETHDR(m, M_DONTWAIT, MT_DATA); 1688 if (m == NULL) 1689 return (ENOBUFS); 1690 1691 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1692 MCLGET(m, M_DONTWAIT); 1693 if ((m->m_flags & M_EXT) == 0) { 1694 m_freem(m); 1695 return (ENOBUFS); 1696 } 1697 1698 #ifdef GEM_DEBUG 1699 /* bzero the packet to check DMA */ 1700 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 1701 #endif 1702 1703 if (rxs->rxs_mbuf != NULL) 1704 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 1705 1706 rxs->rxs_mbuf = m; 1707 1708 error = bus_dmamap_load(sc->sc_dmatag, rxs->rxs_dmamap, 1709 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1710 BUS_DMA_READ|BUS_DMA_NOWAIT); 1711 if (error) { 1712 printf("%s: can't load rx DMA map %d, error = %d\n", 1713 sc->sc_dev.dv_xname, idx, error); 1714 panic("gem_add_rxbuf"); /* XXX */ 1715 } 1716 1717 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1718 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1719 1720 GEM_INIT_RXDESC(sc, idx); 1721 1722 return (0); 1723 } 1724 1725 1726 int 1727 gem_eint(sc, status) 1728 struct gem_softc *sc; 1729 u_int status; 1730 { 1731 char bits[128]; 1732 1733 if ((status & GEM_INTR_MIF) != 0) { 1734 printf("%s: XXXlink status changed\n", sc->sc_dev.dv_xname); 1735 return (1); 1736 } 1737 1738 printf("%s: status=%s\n", sc->sc_dev.dv_xname, 1739 bitmask_snprintf(status, GEM_INTR_BITS, bits, sizeof(bits))); 1740 return (1); 1741 } 1742 1743 1744 int 1745 gem_intr(v) 1746 void *v; 1747 { 1748 struct gem_softc *sc = (struct gem_softc *)v; 1749 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1750 bus_space_tag_t t = sc->sc_bustag; 1751 bus_space_handle_t seb = sc->sc_h; 1752 u_int32_t status; 1753 int r = 0; 1754 #ifdef GEM_DEBUG 1755 char bits[128]; 1756 #endif 1757 1758 sc->sc_ev_intr.ev_count++; 1759 1760 status = bus_space_read_4(t, seb, GEM_STATUS); 1761 DPRINTF(sc, ("%s: gem_intr: cplt 0x%x status %s\n", 1762 sc->sc_dev.dv_xname, (status >> 19), 1763 bitmask_snprintf(status, GEM_INTR_BITS, bits, sizeof(bits)))); 1764 1765 if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0) 1766 r |= gem_eint(sc, status); 1767 1768 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) { 1769 GEM_COUNTER_INCR(sc, sc_ev_txint); 1770 r |= gem_tint(sc); 1771 } 1772 1773 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) { 1774 GEM_COUNTER_INCR(sc, sc_ev_rxint); 1775 r |= gem_rint(sc); 1776 } 1777 1778 /* We should eventually do more than just print out error stats. */ 1779 if (status & GEM_INTR_TX_MAC) { 1780 int txstat = bus_space_read_4(t, seb, GEM_MAC_TX_STATUS); 1781 if (txstat & ~GEM_MAC_TX_XMIT_DONE) 1782 printf("%s: MAC tx fault, status %x\n", 1783 sc->sc_dev.dv_xname, txstat); 1784 if (txstat & (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG)) 1785 gem_init(ifp); 1786 } 1787 if (status & GEM_INTR_RX_MAC) { 1788 int rxstat = bus_space_read_4(t, seb, GEM_MAC_RX_STATUS); 1789 if (rxstat & ~GEM_MAC_RX_DONE) 1790 printf("%s: MAC rx fault, status %x\n", 1791 sc->sc_dev.dv_xname, rxstat); 1792 /* 1793 * On some chip revisions GEM_MAC_RX_OVERFLOW happen often 1794 * due to a silicon bug so handle them silently. 1795 */ 1796 if (rxstat & GEM_MAC_RX_OVERFLOW) 1797 gem_init(ifp); 1798 else if (rxstat & ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT)) 1799 printf("%s: MAC rx fault, status %x\n", 1800 sc->sc_dev.dv_xname, rxstat); 1801 } 1802 #if NRND > 0 1803 rnd_add_uint32(&sc->rnd_source, status); 1804 #endif 1805 return (r); 1806 } 1807 1808 1809 void 1810 gem_watchdog(ifp) 1811 struct ifnet *ifp; 1812 { 1813 struct gem_softc *sc = ifp->if_softc; 1814 1815 DPRINTF(sc, ("gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x " 1816 "GEM_MAC_RX_CONFIG %x\n", 1817 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_CONFIG), 1818 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_STATUS), 1819 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_CONFIG))); 1820 1821 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1822 ++ifp->if_oerrors; 1823 1824 /* Try to get more packets going. */ 1825 gem_start(ifp); 1826 } 1827 1828 /* 1829 * Initialize the MII Management Interface 1830 */ 1831 void 1832 gem_mifinit(sc) 1833 struct gem_softc *sc; 1834 { 1835 bus_space_tag_t t = sc->sc_bustag; 1836 bus_space_handle_t mif = sc->sc_h; 1837 1838 /* Configure the MIF in frame mode */ 1839 sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1840 sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA; 1841 bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config); 1842 } 1843 1844 /* 1845 * MII interface 1846 * 1847 * The GEM MII interface supports at least three different operating modes: 1848 * 1849 * Bitbang mode is implemented using data, clock and output enable registers. 1850 * 1851 * Frame mode is implemented by loading a complete frame into the frame 1852 * register and polling the valid bit for completion. 1853 * 1854 * Polling mode uses the frame register but completion is indicated by 1855 * an interrupt. 1856 * 1857 */ 1858 static int 1859 gem_mii_readreg(self, phy, reg) 1860 struct device *self; 1861 int phy, reg; 1862 { 1863 struct gem_softc *sc = (void *)self; 1864 bus_space_tag_t t = sc->sc_bustag; 1865 bus_space_handle_t mif = sc->sc_h; 1866 int n; 1867 u_int32_t v; 1868 1869 #ifdef GEM_DEBUG1 1870 if (sc->sc_debug) 1871 printf("gem_mii_readreg: phy %d reg %d\n", phy, reg); 1872 #endif 1873 1874 #if 0 1875 /* Select the desired PHY in the MIF configuration register */ 1876 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1877 /* Clear PHY select bit */ 1878 v &= ~GEM_MIF_CONFIG_PHY_SEL; 1879 if (phy == GEM_PHYAD_EXTERNAL) 1880 /* Set PHY select bit to get at external device */ 1881 v |= GEM_MIF_CONFIG_PHY_SEL; 1882 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 1883 #endif 1884 1885 /* Construct the frame command */ 1886 v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) | 1887 GEM_MIF_FRAME_READ; 1888 1889 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1890 for (n = 0; n < 100; n++) { 1891 DELAY(1); 1892 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1893 if (v & GEM_MIF_FRAME_TA0) 1894 return (v & GEM_MIF_FRAME_DATA); 1895 } 1896 1897 printf("%s: mii_read timeout\n", sc->sc_dev.dv_xname); 1898 return (0); 1899 } 1900 1901 static void 1902 gem_mii_writereg(self, phy, reg, val) 1903 struct device *self; 1904 int phy, reg, val; 1905 { 1906 struct gem_softc *sc = (void *)self; 1907 bus_space_tag_t t = sc->sc_bustag; 1908 bus_space_handle_t mif = sc->sc_h; 1909 int n; 1910 u_int32_t v; 1911 1912 #ifdef GEM_DEBUG1 1913 if (sc->sc_debug) 1914 printf("gem_mii_writereg: phy %d reg %d val %x\n", 1915 phy, reg, val); 1916 #endif 1917 1918 #if 0 1919 /* Select the desired PHY in the MIF configuration register */ 1920 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1921 /* Clear PHY select bit */ 1922 v &= ~GEM_MIF_CONFIG_PHY_SEL; 1923 if (phy == GEM_PHYAD_EXTERNAL) 1924 /* Set PHY select bit to get at external device */ 1925 v |= GEM_MIF_CONFIG_PHY_SEL; 1926 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 1927 #endif 1928 /* Construct the frame command */ 1929 v = GEM_MIF_FRAME_WRITE | 1930 (phy << GEM_MIF_PHY_SHIFT) | 1931 (reg << GEM_MIF_REG_SHIFT) | 1932 (val & GEM_MIF_FRAME_DATA); 1933 1934 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1935 for (n = 0; n < 100; n++) { 1936 DELAY(1); 1937 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1938 if (v & GEM_MIF_FRAME_TA0) 1939 return; 1940 } 1941 1942 printf("%s: mii_write timeout\n", sc->sc_dev.dv_xname); 1943 } 1944 1945 static void 1946 gem_mii_statchg(dev) 1947 struct device *dev; 1948 { 1949 struct gem_softc *sc = (void *)dev; 1950 #ifdef GEM_DEBUG 1951 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1952 #endif 1953 bus_space_tag_t t = sc->sc_bustag; 1954 bus_space_handle_t mac = sc->sc_h; 1955 u_int32_t v; 1956 1957 #ifdef GEM_DEBUG 1958 if (sc->sc_debug) 1959 printf("gem_mii_statchg: status change: phy = %d\n", 1960 sc->sc_phys[instance]); 1961 #endif 1962 1963 1964 /* Set tx full duplex options */ 1965 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0); 1966 delay(10000); /* reg must be cleared and delay before changing. */ 1967 v = GEM_MAC_TX_ENA_IPG0|GEM_MAC_TX_NGU|GEM_MAC_TX_NGU_LIMIT| 1968 GEM_MAC_TX_ENABLE; 1969 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) { 1970 v |= GEM_MAC_TX_IGN_CARRIER|GEM_MAC_TX_IGN_COLLIS; 1971 } 1972 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, v); 1973 1974 /* XIF Configuration */ 1975 /* We should really calculate all this rather than rely on defaults */ 1976 v = bus_space_read_4(t, mac, GEM_MAC_XIF_CONFIG); 1977 v = GEM_MAC_XIF_LINK_LED; 1978 v |= GEM_MAC_XIF_TX_MII_ENA; 1979 1980 /* If an external transceiver is connected, enable its MII drivers */ 1981 sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG); 1982 if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) { 1983 /* External MII needs echo disable if half duplex. */ 1984 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1985 /* turn on full duplex LED */ 1986 v |= GEM_MAC_XIF_FDPLX_LED; 1987 else 1988 /* half duplex -- disable echo */ 1989 v |= GEM_MAC_XIF_ECHO_DISABL; 1990 1991 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 1992 v |= GEM_MAC_XIF_GMII_MODE; 1993 else 1994 v &= ~GEM_MAC_XIF_GMII_MODE; 1995 } else 1996 /* Internal MII needs buf enable */ 1997 v |= GEM_MAC_XIF_MII_BUF_ENA; 1998 bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v); 1999 } 2000 2001 int 2002 gem_mediachange(ifp) 2003 struct ifnet *ifp; 2004 { 2005 struct gem_softc *sc = ifp->if_softc; 2006 2007 if (IFM_TYPE(sc->sc_media.ifm_media) != IFM_ETHER) 2008 return (EINVAL); 2009 2010 return (mii_mediachg(&sc->sc_mii)); 2011 } 2012 2013 void 2014 gem_mediastatus(ifp, ifmr) 2015 struct ifnet *ifp; 2016 struct ifmediareq *ifmr; 2017 { 2018 struct gem_softc *sc = ifp->if_softc; 2019 2020 if ((ifp->if_flags & IFF_UP) == 0) 2021 return; 2022 2023 mii_pollstat(&sc->sc_mii); 2024 ifmr->ifm_active = sc->sc_mii.mii_media_active; 2025 ifmr->ifm_status = sc->sc_mii.mii_media_status; 2026 } 2027 2028 /* 2029 * Process an ioctl request. 2030 */ 2031 int 2032 gem_ioctl(ifp, cmd, data) 2033 struct ifnet *ifp; 2034 u_long cmd; 2035 caddr_t data; 2036 { 2037 struct gem_softc *sc = ifp->if_softc; 2038 struct ifreq *ifr = (struct ifreq *)data; 2039 int s, error = 0; 2040 2041 s = splnet(); 2042 2043 switch (cmd) { 2044 case SIOCGIFMEDIA: 2045 case SIOCSIFMEDIA: 2046 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 2047 break; 2048 case SIOCSIFFLAGS: 2049 #define RESETIGN (IFF_CANTCHANGE|IFF_DEBUG) 2050 if (((ifp->if_flags & (IFF_UP|IFF_RUNNING)) 2051 == (IFF_UP|IFF_RUNNING)) 2052 && ((ifp->if_flags & (~RESETIGN)) 2053 == (sc->sc_if_flags & (~RESETIGN)))) { 2054 gem_setladrf(sc); 2055 break; 2056 } 2057 #undef RESETIGN 2058 /*FALLTHROUGH*/ 2059 default: 2060 error = ether_ioctl(ifp, cmd, data); 2061 if (error == ENETRESET) { 2062 /* 2063 * Multicast list has changed; set the hardware filter 2064 * accordingly. 2065 */ 2066 if (ifp->if_flags & IFF_RUNNING) 2067 gem_setladrf(sc); 2068 error = 0; 2069 } 2070 break; 2071 } 2072 2073 /* Try to get things going again */ 2074 if (ifp->if_flags & IFF_UP) 2075 gem_start(ifp); 2076 splx(s); 2077 return (error); 2078 } 2079 2080 2081 void 2082 gem_shutdown(arg) 2083 void *arg; 2084 { 2085 struct gem_softc *sc = (struct gem_softc *)arg; 2086 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2087 2088 gem_stop(ifp, 1); 2089 } 2090 2091 /* 2092 * Set up the logical address filter. 2093 */ 2094 void 2095 gem_setladrf(sc) 2096 struct gem_softc *sc; 2097 { 2098 struct ethercom *ec = &sc->sc_ethercom; 2099 struct ifnet *ifp = &ec->ec_if; 2100 struct ether_multi *enm; 2101 struct ether_multistep step; 2102 bus_space_tag_t t = sc->sc_bustag; 2103 bus_space_handle_t h = sc->sc_h; 2104 u_int32_t crc; 2105 u_int32_t hash[16]; 2106 u_int32_t v; 2107 int i; 2108 2109 /* Get current RX configuration */ 2110 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 2111 2112 /* 2113 * Turn off promiscuous mode, promiscuous group mode (all multicast), 2114 * and hash filter. Depending on the case, the right bit will be 2115 * enabled. 2116 */ 2117 v &= ~(GEM_MAC_RX_PROMISCUOUS|GEM_MAC_RX_HASH_FILTER| 2118 GEM_MAC_RX_PROMISC_GRP); 2119 2120 if ((ifp->if_flags & IFF_PROMISC) != 0) { 2121 /* Turn on promiscuous mode */ 2122 v |= GEM_MAC_RX_PROMISCUOUS; 2123 ifp->if_flags |= IFF_ALLMULTI; 2124 goto chipit; 2125 } 2126 2127 /* 2128 * Set up multicast address filter by passing all multicast addresses 2129 * through a crc generator, and then using the high order 8 bits as an 2130 * index into the 256 bit logical address filter. The high order 4 2131 * bits selects the word, while the other 4 bits select the bit within 2132 * the word (where bit 0 is the MSB). 2133 */ 2134 2135 /* Clear hash table */ 2136 memset(hash, 0, sizeof(hash)); 2137 2138 ETHER_FIRST_MULTI(step, ec, enm); 2139 while (enm != NULL) { 2140 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2141 /* 2142 * We must listen to a range of multicast addresses. 2143 * For now, just accept all multicasts, rather than 2144 * trying to set only those filter bits needed to match 2145 * the range. (At this time, the only use of address 2146 * ranges is for IP multicast routing, for which the 2147 * range is big enough to require all bits set.) 2148 * XXX use the addr filter for this 2149 */ 2150 ifp->if_flags |= IFF_ALLMULTI; 2151 v |= GEM_MAC_RX_PROMISC_GRP; 2152 goto chipit; 2153 } 2154 2155 /* Get the LE CRC32 of the address */ 2156 crc = ether_crc32_le(enm->enm_addrlo, sizeof(enm->enm_addrlo)); 2157 2158 /* Just want the 8 most significant bits. */ 2159 crc >>= 24; 2160 2161 /* Set the corresponding bit in the filter. */ 2162 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 2163 2164 ETHER_NEXT_MULTI(step, enm); 2165 } 2166 2167 v |= GEM_MAC_RX_HASH_FILTER; 2168 ifp->if_flags &= ~IFF_ALLMULTI; 2169 2170 /* Now load the hash table into the chip (if we are using it) */ 2171 for (i = 0; i < 16; i++) { 2172 bus_space_write_4(t, h, 2173 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1-GEM_MAC_HASH0), 2174 hash[i]); 2175 } 2176 2177 chipit: 2178 sc->sc_if_flags = ifp->if_flags; 2179 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 2180 } 2181 2182 #if notyet 2183 2184 /* 2185 * gem_power: 2186 * 2187 * Power management (suspend/resume) hook. 2188 */ 2189 void 2190 gem_power(why, arg) 2191 int why; 2192 void *arg; 2193 { 2194 struct gem_softc *sc = arg; 2195 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2196 int s; 2197 2198 s = splnet(); 2199 switch (why) { 2200 case PWR_SUSPEND: 2201 case PWR_STANDBY: 2202 gem_stop(ifp, 1); 2203 if (sc->sc_power != NULL) 2204 (*sc->sc_power)(sc, why); 2205 break; 2206 case PWR_RESUME: 2207 if (ifp->if_flags & IFF_UP) { 2208 if (sc->sc_power != NULL) 2209 (*sc->sc_power)(sc, why); 2210 gem_init(ifp); 2211 } 2212 break; 2213 case PWR_SOFTSUSPEND: 2214 case PWR_SOFTSTANDBY: 2215 case PWR_SOFTRESUME: 2216 break; 2217 } 2218 splx(s); 2219 } 2220 #endif 2221
Indexes created Mon Sep 22 13:09:51 GMT 2025