gem.c revision 1.5
1 /* $NetBSD: gem.c,v 1.5 2001/10/18 06:28:17 thorpej Exp $ */ 2 3 /* 4 * 5 * Copyright (C) 2001 Eduardo Horvath. 6 * All rights reserved. 7 * 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 */ 31 32 /* 33 * Driver for Sun GEM ethernet controllers. 34 */ 35 36 #include "bpfilter.h" 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/callout.h> 41 #include <sys/mbuf.h> 42 #include <sys/syslog.h> 43 #include <sys/malloc.h> 44 #include <sys/kernel.h> 45 #include <sys/socket.h> 46 #include <sys/ioctl.h> 47 #include <sys/errno.h> 48 #include <sys/device.h> 49 50 #include <machine/endian.h> 51 52 #include <uvm/uvm_extern.h> 53 54 #include <net/if.h> 55 #include <net/if_dl.h> 56 #include <net/if_media.h> 57 #include <net/if_ether.h> 58 59 #if NBPFILTER > 0 60 #include <net/bpf.h> 61 #endif 62 63 #include <machine/bus.h> 64 #include <machine/intr.h> 65 66 #include <dev/mii/mii.h> 67 #include <dev/mii/miivar.h> 68 #include <dev/mii/mii_bitbang.h> 69 70 #include <dev/ic/gemreg.h> 71 #include <dev/ic/gemvar.h> 72 73 #define TRIES 10000 74 75 void gem_start __P((struct ifnet *)); 76 void gem_stop __P((struct ifnet *, int)); 77 int gem_ioctl __P((struct ifnet *, u_long, caddr_t)); 78 void gem_tick __P((void *)); 79 void gem_watchdog __P((struct ifnet *)); 80 void gem_shutdown __P((void *)); 81 int gem_init __P((struct ifnet *)); 82 void gem_init_regs(struct gem_softc *sc); 83 static int gem_ringsize(int sz); 84 int gem_meminit __P((struct gem_softc *)); 85 void gem_mifinit __P((struct gem_softc *)); 86 void gem_reset __P((struct gem_softc *)); 87 int gem_reset_rx(struct gem_softc *sc); 88 int gem_reset_tx(struct gem_softc *sc); 89 int gem_disable_rx(struct gem_softc *sc); 90 int gem_disable_tx(struct gem_softc *sc); 91 void gem_rxdrain(struct gem_softc *sc); 92 int gem_add_rxbuf(struct gem_softc *sc, int idx); 93 void gem_setladrf __P((struct gem_softc *)); 94 95 /* MII methods & callbacks */ 96 static int gem_mii_readreg __P((struct device *, int, int)); 97 static void gem_mii_writereg __P((struct device *, int, int, int)); 98 static void gem_mii_statchg __P((struct device *)); 99 100 int gem_mediachange __P((struct ifnet *)); 101 void gem_mediastatus __P((struct ifnet *, struct ifmediareq *)); 102 103 struct mbuf *gem_get __P((struct gem_softc *, int, int)); 104 int gem_put __P((struct gem_softc *, int, struct mbuf *)); 105 void gem_read __P((struct gem_softc *, int, int)); 106 int gem_eint __P((struct gem_softc *, u_int)); 107 int gem_rint __P((struct gem_softc *)); 108 int gem_tint __P((struct gem_softc *)); 109 void gem_power __P((int, void *)); 110 111 static int ether_cmp __P((u_char *, u_char *)); 112 113 /* Default buffer copy routines */ 114 void gem_copytobuf_contig __P((struct gem_softc *, void *, int, int)); 115 void gem_copyfrombuf_contig __P((struct gem_softc *, void *, int, int)); 116 void gem_zerobuf_contig __P((struct gem_softc *, int, int)); 117 118 119 #ifdef GEM_DEBUG 120 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 121 printf x 122 #else 123 #define DPRINTF(sc, x) /* nothing */ 124 #endif 125 126 127 /* 128 * gem_config: 129 * 130 * Attach a Gem interface to the system. 131 */ 132 void 133 gem_config(sc) 134 struct gem_softc *sc; 135 { 136 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 137 struct mii_data *mii = &sc->sc_mii; 138 struct mii_softc *child; 139 int i, error; 140 141 /* Make sure the chip is stopped. */ 142 ifp->if_softc = sc; 143 gem_reset(sc); 144 145 /* 146 * Allocate the control data structures, and create and load the 147 * DMA map for it. 148 */ 149 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 150 sizeof(struct gem_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 151 1, &sc->sc_cdnseg, 0)) != 0) { 152 printf("%s: unable to allocate control data, error = %d\n", 153 sc->sc_dev.dv_xname, error); 154 goto fail_0; 155 } 156 157 /* XXX should map this in with correct endianness */ 158 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg, 159 sizeof(struct gem_control_data), (caddr_t *)&sc->sc_control_data, 160 BUS_DMA_COHERENT)) != 0) { 161 printf("%s: unable to map control data, error = %d\n", 162 sc->sc_dev.dv_xname, error); 163 goto fail_1; 164 } 165 166 if ((error = bus_dmamap_create(sc->sc_dmatag, 167 sizeof(struct gem_control_data), 1, 168 sizeof(struct gem_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 169 printf("%s: unable to create control data DMA map, " 170 "error = %d\n", sc->sc_dev.dv_xname, error); 171 goto fail_2; 172 } 173 174 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 175 sc->sc_control_data, sizeof(struct gem_control_data), NULL, 176 0)) != 0) { 177 printf("%s: unable to load control data DMA map, error = %d\n", 178 sc->sc_dev.dv_xname, error); 179 goto fail_3; 180 } 181 182 /* 183 * Initialize the transmit job descriptors. 184 */ 185 SIMPLEQ_INIT(&sc->sc_txfreeq); 186 SIMPLEQ_INIT(&sc->sc_txdirtyq); 187 188 /* 189 * Create the transmit buffer DMA maps. 190 */ 191 for (i = 0; i < GEM_TXQUEUELEN; i++) { 192 struct gem_txsoft *txs; 193 194 txs = &sc->sc_txsoft[i]; 195 txs->txs_mbuf = NULL; 196 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 197 GEM_NTXSEGS, MCLBYTES, 0, 0, 198 &txs->txs_dmamap)) != 0) { 199 printf("%s: unable to create tx DMA map %d, " 200 "error = %d\n", sc->sc_dev.dv_xname, i, error); 201 goto fail_4; 202 } 203 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 204 } 205 206 /* 207 * Create the receive buffer DMA maps. 208 */ 209 for (i = 0; i < GEM_NRXDESC; i++) { 210 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, 211 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 212 printf("%s: unable to create rx DMA map %d, " 213 "error = %d\n", sc->sc_dev.dv_xname, i, error); 214 goto fail_5; 215 } 216 sc->sc_rxsoft[i].rxs_mbuf = NULL; 217 } 218 219 /* 220 * From this point forward, the attachment cannot fail. A failure 221 * before this point releases all resources that may have been 222 * allocated. 223 */ 224 225 /* Announce ourselves. */ 226 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 227 ether_sprintf(sc->sc_enaddr)); 228 229 /* Initialize ifnet structure. */ 230 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 231 ifp->if_softc = sc; 232 ifp->if_flags = 233 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 234 ifp->if_start = gem_start; 235 ifp->if_ioctl = gem_ioctl; 236 ifp->if_watchdog = gem_watchdog; 237 ifp->if_stop = gem_stop; 238 ifp->if_init = gem_init; 239 IFQ_SET_READY(&ifp->if_snd); 240 241 /* Initialize ifmedia structures and MII info */ 242 mii->mii_ifp = ifp; 243 mii->mii_readreg = gem_mii_readreg; 244 mii->mii_writereg = gem_mii_writereg; 245 mii->mii_statchg = gem_mii_statchg; 246 247 ifmedia_init(&mii->mii_media, 0, gem_mediachange, gem_mediastatus); 248 249 gem_mifinit(sc); 250 251 mii_attach(&sc->sc_dev, mii, 0xffffffff, 252 MII_PHY_ANY, MII_OFFSET_ANY, 0); 253 254 child = LIST_FIRST(&mii->mii_phys); 255 if (child == NULL) { 256 /* No PHY attached */ 257 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 258 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 259 } else { 260 /* 261 * Walk along the list of attached MII devices and 262 * establish an `MII instance' to `phy number' 263 * mapping. We'll use this mapping in media change 264 * requests to determine which phy to use to program 265 * the MIF configuration register. 266 */ 267 for (; child != NULL; child = LIST_NEXT(child, mii_list)) { 268 /* 269 * Note: we support just two PHYs: the built-in 270 * internal device and an external on the MII 271 * connector. 272 */ 273 if (child->mii_phy > 1 || child->mii_inst > 1) { 274 printf("%s: cannot accomodate MII device %s" 275 " at phy %d, instance %d\n", 276 sc->sc_dev.dv_xname, 277 child->mii_dev.dv_xname, 278 child->mii_phy, child->mii_inst); 279 continue; 280 } 281 282 sc->sc_phys[child->mii_inst] = child->mii_phy; 283 } 284 285 /* 286 * Now select and activate the PHY we will use. 287 * 288 * The order of preference is External (MDI1), 289 * Internal (MDI0), Serial Link (no MII). 290 */ 291 if (sc->sc_phys[1]) { 292 #ifdef DEBUG 293 printf("using external phy\n"); 294 #endif 295 sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL; 296 } else { 297 #ifdef DEBUG 298 printf("using internal phy\n"); 299 #endif 300 sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL; 301 } 302 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_MIF_CONFIG, 303 sc->sc_mif_config); 304 305 /* 306 * XXX - we can really do the following ONLY if the 307 * phy indeed has the auto negotiation capability!! 308 */ 309 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO); 310 } 311 312 /* claim 802.1q capability */ 313 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 314 315 /* Attach the interface. */ 316 if_attach(ifp); 317 ether_ifattach(ifp, sc->sc_enaddr); 318 319 sc->sc_sh = shutdownhook_establish(gem_shutdown, sc); 320 if (sc->sc_sh == NULL) 321 panic("gem_config: can't establish shutdownhook"); 322 323 #if NRND > 0 324 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 325 RND_TYPE_NET, 0); 326 #endif 327 328 329 #if notyet 330 /* 331 * Add a suspend hook to make sure we come back up after a 332 * resume. 333 */ 334 sc->sc_powerhook = powerhook_establish(gem_power, sc); 335 if (sc->sc_powerhook == NULL) 336 printf("%s: WARNING: unable to establish power hook\n", 337 sc->sc_dev.dv_xname); 338 #endif 339 340 callout_init(&sc->sc_tick_ch); 341 return; 342 343 /* 344 * Free any resources we've allocated during the failed attach 345 * attempt. Do this in reverse order and fall through. 346 */ 347 fail_5: 348 for (i = 0; i < GEM_NRXDESC; i++) { 349 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 350 bus_dmamap_destroy(sc->sc_dmatag, 351 sc->sc_rxsoft[i].rxs_dmamap); 352 } 353 fail_4: 354 for (i = 0; i < GEM_TXQUEUELEN; i++) { 355 if (sc->sc_txsoft[i].txs_dmamap != NULL) 356 bus_dmamap_destroy(sc->sc_dmatag, 357 sc->sc_txsoft[i].txs_dmamap); 358 } 359 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 360 fail_3: 361 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 362 fail_2: 363 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)sc->sc_control_data, 364 sizeof(struct gem_control_data)); 365 fail_1: 366 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 367 fail_0: 368 return; 369 } 370 371 372 void 373 gem_tick(arg) 374 void *arg; 375 { 376 struct gem_softc *sc = arg; 377 int s; 378 379 s = splnet(); 380 mii_tick(&sc->sc_mii); 381 splx(s); 382 383 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 384 385 } 386 387 void 388 gem_reset(sc) 389 struct gem_softc *sc; 390 { 391 bus_space_tag_t t = sc->sc_bustag; 392 bus_space_handle_t h = sc->sc_h; 393 int i; 394 int s; 395 396 s = splnet(); 397 DPRINTF(sc, ("%s: gem_reset\n", sc->sc_dev.dv_xname)); 398 gem_reset_rx(sc); 399 gem_reset_tx(sc); 400 401 /* Do a full reset */ 402 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX|GEM_RESET_TX); 403 for (i=TRIES; i--; delay(100)) 404 if ((bus_space_read_4(t, h, GEM_RESET) & 405 (GEM_RESET_RX|GEM_RESET_TX)) == 0) 406 break; 407 if ((bus_space_read_4(t, h, GEM_RESET) & 408 (GEM_RESET_RX|GEM_RESET_TX)) != 0) { 409 printf("%s: cannot reset device\n", 410 sc->sc_dev.dv_xname); 411 } 412 splx(s); 413 } 414 415 416 /* 417 * gem_rxdrain: 418 * 419 * Drain the receive queue. 420 */ 421 void 422 gem_rxdrain(struct gem_softc *sc) 423 { 424 struct gem_rxsoft *rxs; 425 int i; 426 427 for (i = 0; i < GEM_NRXDESC; i++) { 428 rxs = &sc->sc_rxsoft[i]; 429 if (rxs->rxs_mbuf != NULL) { 430 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 431 m_freem(rxs->rxs_mbuf); 432 rxs->rxs_mbuf = NULL; 433 } 434 } 435 } 436 437 /* 438 * Reset the whole thing. 439 */ 440 void 441 gem_stop(struct ifnet *ifp, int disable) 442 { 443 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 444 struct gem_txsoft *txs; 445 446 DPRINTF(sc, ("%s: gem_stop\n", sc->sc_dev.dv_xname)); 447 448 callout_stop(&sc->sc_tick_ch); 449 mii_down(&sc->sc_mii); 450 451 /* XXX - Should we reset these instead? */ 452 gem_disable_rx(sc); 453 gem_disable_rx(sc); 454 455 /* 456 * Release any queued transmit buffers. 457 */ 458 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 459 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs, txs_q); 460 if (txs->txs_mbuf != NULL) { 461 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 462 m_freem(txs->txs_mbuf); 463 txs->txs_mbuf = NULL; 464 } 465 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 466 } 467 468 if (disable) { 469 gem_rxdrain(sc); 470 } 471 472 /* 473 * Mark the interface down and cancel the watchdog timer. 474 */ 475 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 476 ifp->if_timer = 0; 477 } 478 479 480 /* 481 * Reset the receiver 482 */ 483 int 484 gem_reset_rx(struct gem_softc *sc) 485 { 486 bus_space_tag_t t = sc->sc_bustag; 487 bus_space_handle_t h = sc->sc_h; 488 int i; 489 490 491 /* 492 * Resetting while DMA is in progress can cause a bus hang, so we 493 * disable DMA first. 494 */ 495 gem_disable_rx(sc); 496 bus_space_write_4(t, h, GEM_RX_CONFIG, 0); 497 /* Wait till it finishes */ 498 for (i=TRIES; i--; delay(100)) 499 if ((bus_space_read_4(t, h, GEM_RX_CONFIG) & 1) == 0) 500 break; 501 if ((bus_space_read_4(t, h, GEM_RX_CONFIG) & 1) != 0) 502 printf("%s: cannot disable read dma\n", 503 sc->sc_dev.dv_xname); 504 505 /* Wait 5ms extra. */ 506 delay(5000); 507 508 /* Finally, reset the ERX */ 509 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX); 510 /* Wait till it finishes */ 511 for (i=TRIES; i--; delay(100)) 512 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_RX) == 0) 513 break; 514 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_RX) != 0) { 515 printf("%s: cannot reset receiver\n", 516 sc->sc_dev.dv_xname); 517 return (1); 518 } 519 return (0); 520 } 521 522 523 /* 524 * Reset the transmitter 525 */ 526 int 527 gem_reset_tx(struct gem_softc *sc) 528 { 529 bus_space_tag_t t = sc->sc_bustag; 530 bus_space_handle_t h = sc->sc_h; 531 int i; 532 533 /* 534 * Resetting while DMA is in progress can cause a bus hang, so we 535 * disable DMA first. 536 */ 537 gem_disable_tx(sc); 538 bus_space_write_4(t, h, GEM_TX_CONFIG, 0); 539 /* Wait till it finishes */ 540 for (i=TRIES; i--; delay(100)) 541 if ((bus_space_read_4(t, h, GEM_TX_CONFIG) & 1) == 0) 542 break; 543 if ((bus_space_read_4(t, h, GEM_TX_CONFIG) & 1) != 0) 544 printf("%s: cannot disable read dma\n", 545 sc->sc_dev.dv_xname); 546 547 /* Wait 5ms extra. */ 548 delay(5000); 549 550 /* Finally, reset the ETX */ 551 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_TX); 552 /* Wait till it finishes */ 553 for (i=TRIES; i--; delay(100)) 554 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_TX) == 0) 555 break; 556 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_TX) != 0) { 557 printf("%s: cannot reset receiver\n", 558 sc->sc_dev.dv_xname); 559 return (1); 560 } 561 return (0); 562 } 563 564 /* 565 * disable receiver. 566 */ 567 int 568 gem_disable_rx(struct gem_softc *sc) 569 { 570 bus_space_tag_t t = sc->sc_bustag; 571 bus_space_handle_t h = sc->sc_h; 572 int i; 573 u_int32_t cfg; 574 575 /* Flip the enable bit */ 576 cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 577 cfg &= ~GEM_MAC_RX_ENABLE; 578 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg); 579 580 /* Wait for it to finish */ 581 for (i=TRIES; i--; delay(100)) 582 if ((bus_space_read_4(t, h, GEM_MAC_RX_CONFIG) & 583 GEM_MAC_RX_ENABLE) == 0) 584 return (0); 585 return (1); 586 } 587 588 /* 589 * disable transmitter. 590 */ 591 int 592 gem_disable_tx(struct gem_softc *sc) 593 { 594 bus_space_tag_t t = sc->sc_bustag; 595 bus_space_handle_t h = sc->sc_h; 596 int i; 597 u_int32_t cfg; 598 599 /* Flip the enable bit */ 600 cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG); 601 cfg &= ~GEM_MAC_TX_ENABLE; 602 bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg); 603 604 /* Wait for it to finish */ 605 for (i=TRIES; i--; delay(100)) 606 if ((bus_space_read_4(t, h, GEM_MAC_TX_CONFIG) & 607 GEM_MAC_TX_ENABLE) == 0) 608 return (0); 609 return (1); 610 } 611 612 /* 613 * Initialize interface. 614 */ 615 int 616 gem_meminit(struct gem_softc *sc) 617 { 618 struct gem_rxsoft *rxs; 619 int i, error; 620 621 /* 622 * Initialize the transmit descriptor ring. 623 */ 624 memset((void *)sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 625 for (i = 0; i < GEM_NTXDESC; i++) { 626 sc->sc_txdescs[i].gd_flags = 0; 627 sc->sc_txdescs[i].gd_addr = 0; 628 } 629 GEM_CDTXSYNC(sc, 0, GEM_NTXDESC, 630 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 631 sc->sc_txfree = GEM_NTXDESC; 632 sc->sc_txnext = 0; 633 634 /* 635 * Initialize the receive descriptor and receive job 636 * descriptor rings. 637 */ 638 for (i = 0; i < GEM_NRXDESC; i++) { 639 rxs = &sc->sc_rxsoft[i]; 640 if (rxs->rxs_mbuf == NULL) { 641 if ((error = gem_add_rxbuf(sc, i)) != 0) { 642 printf("%s: unable to allocate or map rx " 643 "buffer %d, error = %d\n", 644 sc->sc_dev.dv_xname, i, error); 645 /* 646 * XXX Should attempt to run with fewer receive 647 * XXX buffers instead of just failing. 648 */ 649 gem_rxdrain(sc); 650 return (1); 651 } 652 } else 653 GEM_INIT_RXDESC(sc, i); 654 } 655 sc->sc_rxptr = 0; 656 657 return (0); 658 } 659 660 static int 661 gem_ringsize(int sz) 662 { 663 int v; 664 665 switch (sz) { 666 case 32: 667 v = GEM_RING_SZ_32; 668 break; 669 case 64: 670 v = GEM_RING_SZ_64; 671 break; 672 case 128: 673 v = GEM_RING_SZ_128; 674 break; 675 case 256: 676 v = GEM_RING_SZ_256; 677 break; 678 case 512: 679 v = GEM_RING_SZ_512; 680 break; 681 case 1024: 682 v = GEM_RING_SZ_1024; 683 break; 684 case 2048: 685 v = GEM_RING_SZ_2048; 686 break; 687 case 4096: 688 v = GEM_RING_SZ_4096; 689 break; 690 case 8192: 691 v = GEM_RING_SZ_8192; 692 break; 693 default: 694 printf("gem: invalid Receive Descriptor ring size\n"); 695 break; 696 } 697 return (v); 698 } 699 700 /* 701 * Initialization of interface; set up initialization block 702 * and transmit/receive descriptor rings. 703 */ 704 int 705 gem_init(struct ifnet *ifp) 706 { 707 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 708 bus_space_tag_t t = sc->sc_bustag; 709 bus_space_handle_t h = sc->sc_h; 710 int s; 711 u_int32_t v; 712 713 s = splnet(); 714 715 DPRINTF(sc, ("%s: gem_init: calling stop\n", sc->sc_dev.dv_xname)); 716 /* 717 * Initialization sequence. The numbered steps below correspond 718 * to the sequence outlined in section 6.3.5.1 in the Ethernet 719 * Channel Engine manual (part of the PCIO manual). 720 * See also the STP2002-STQ document from Sun Microsystems. 721 */ 722 723 /* step 1 & 2. Reset the Ethernet Channel */ 724 gem_stop(ifp, 0); 725 gem_reset(sc); 726 DPRINTF(sc, ("%s: gem_init: restarting\n", sc->sc_dev.dv_xname)); 727 728 /* Re-initialize the MIF */ 729 gem_mifinit(sc); 730 731 /* Call MI reset function if any */ 732 if (sc->sc_hwreset) 733 (*sc->sc_hwreset)(sc); 734 735 /* step 3. Setup data structures in host memory */ 736 gem_meminit(sc); 737 738 /* step 4. TX MAC registers & counters */ 739 gem_init_regs(sc); 740 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 741 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 742 ETHER_VLAN_ENCAP_LEN + ETHER_MAX_LEN + sizeof(struct ether_header): 743 ETHER_MAX_LEN + sizeof(struct ether_header)) | (0x2000<<16)); 744 745 /* step 5. RX MAC registers & counters */ 746 gem_setladrf(sc); 747 748 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 749 /* NOTE: we use only 32-bit DMA addresses here. */ 750 bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 0); 751 bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 752 753 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0); 754 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 755 756 /* step 8. Global Configuration & Interrupt Mask */ 757 bus_space_write_4(t, h, GEM_INTMASK, 758 ~(GEM_INTR_TX_INTME| 759 GEM_INTR_TX_EMPTY| 760 GEM_INTR_RX_DONE|GEM_INTR_RX_NOBUF| 761 GEM_INTR_RX_TAG_ERR|GEM_INTR_PCS| 762 GEM_INTR_MAC_CONTROL|GEM_INTR_MIF| 763 GEM_INTR_BERR)); 764 bus_space_write_4(t, h, GEM_MAC_RX_MASK, 0); /* XXXX */ 765 bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXXX */ 766 bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 0); /* XXXX */ 767 768 /* step 9. ETX Configuration: use mostly default values */ 769 770 /* Enable DMA */ 771 v = gem_ringsize(GEM_NTXDESC /*XXX*/); 772 bus_space_write_4(t, h, GEM_TX_CONFIG, 773 v|GEM_TX_CONFIG_TXDMA_EN| 774 ((0x400<<10)&GEM_TX_CONFIG_TXFIFO_TH)); 775 bus_space_write_4(t, h, GEM_TX_KICK, sc->sc_txnext); 776 777 /* step 10. ERX Configuration */ 778 779 /* Encode Receive Descriptor ring size: four possible values */ 780 v = gem_ringsize(GEM_NRXDESC /*XXX*/); 781 782 /* Enable DMA */ 783 bus_space_write_4(t, h, GEM_RX_CONFIG, 784 v|(GEM_THRSH_1024<<GEM_RX_CONFIG_FIFO_THRS_SHIFT)| 785 (2<<GEM_RX_CONFIG_FBOFF_SHFT)|GEM_RX_CONFIG_RXDMA_EN| 786 (0<<GEM_RX_CONFIG_CXM_START_SHFT)); 787 /* 788 * The following value is for an OFF Threshold of about 15.5 Kbytes 789 * and an ON Threshold of 4K bytes. 790 */ 791 bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH, 0xf8 | (0x40 << 12)); 792 bus_space_write_4(t, h, GEM_RX_BLANKING, (2<<12)|6); 793 794 /* step 11. Configure Media */ 795 gem_mii_statchg(&sc->sc_dev); 796 797 /* XXXX Serial link needs a whole different setup. */ 798 799 800 /* step 12. RX_MAC Configuration Register */ 801 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 802 v |= GEM_MAC_RX_ENABLE; 803 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 804 805 /* step 14. Issue Transmit Pending command */ 806 807 /* Call MI initialization function if any */ 808 if (sc->sc_hwinit) 809 (*sc->sc_hwinit)(sc); 810 811 812 /* step 15. Give the reciever a swift kick */ 813 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4); 814 815 /* Start the one second timer. */ 816 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 817 818 ifp->if_flags |= IFF_RUNNING; 819 ifp->if_flags &= ~IFF_OACTIVE; 820 ifp->if_timer = 0; 821 splx(s); 822 823 return (0); 824 } 825 826 /* 827 * Compare two Ether/802 addresses for equality, inlined and unrolled for 828 * speed. 829 */ 830 static __inline__ int 831 ether_cmp(a, b) 832 u_char *a, *b; 833 { 834 835 if (a[5] != b[5] || a[4] != b[4] || a[3] != b[3] || 836 a[2] != b[2] || a[1] != b[1] || a[0] != b[0]) 837 return (0); 838 return (1); 839 } 840 841 842 void 843 gem_init_regs(struct gem_softc *sc) 844 { 845 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 846 bus_space_tag_t t = sc->sc_bustag; 847 bus_space_handle_t h = sc->sc_h; 848 849 /* These regs are not cleared on reset */ 850 sc->sc_inited = 0; 851 if (!sc->sc_inited) { 852 853 /* Wooo. Magic values. */ 854 bus_space_write_4(t, h, GEM_MAC_IPG0, 0); 855 bus_space_write_4(t, h, GEM_MAC_IPG1, 8); 856 bus_space_write_4(t, h, GEM_MAC_IPG2, 4); 857 858 bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 859 /* Max frame and max burst size */ 860 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 861 (ifp->if_mtu+18) | (0x2000<<16)/* Burst size */); 862 bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x7); 863 bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x4); 864 bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10); 865 /* Dunno.... */ 866 bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088); 867 bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED, 868 ((sc->sc_enaddr[5]<<8)|sc->sc_enaddr[4])&0x3ff); 869 /* Secondary MAC addr set to 0:0:0:0:0:0 */ 870 bus_space_write_4(t, h, GEM_MAC_ADDR3, 0); 871 bus_space_write_4(t, h, GEM_MAC_ADDR4, 0); 872 bus_space_write_4(t, h, GEM_MAC_ADDR5, 0); 873 /* MAC control addr set to 0:1:c2:0:1:80 */ 874 bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001); 875 bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200); 876 bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180); 877 878 /* MAC filter addr set to 0:0:0:0:0:0 */ 879 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0); 880 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0); 881 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0); 882 883 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0); 884 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0); 885 886 sc->sc_inited = 1; 887 } 888 889 /* Counters need to be zeroed */ 890 bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0); 891 bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0); 892 bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0); 893 bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0); 894 bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0); 895 bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0); 896 bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0); 897 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 898 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 899 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 900 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 901 902 /* Un-pause stuff */ 903 #if 0 904 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); 905 #else 906 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0); 907 #endif 908 909 /* 910 * Set the station address. 911 */ 912 bus_space_write_4(t, h, GEM_MAC_ADDR0, 913 (sc->sc_enaddr[4]<<8) | sc->sc_enaddr[5]); 914 bus_space_write_4(t, h, GEM_MAC_ADDR1, 915 (sc->sc_enaddr[2]<<8) | sc->sc_enaddr[3]); 916 bus_space_write_4(t, h, GEM_MAC_ADDR2, 917 (sc->sc_enaddr[0]<<8) | sc->sc_enaddr[1]); 918 919 } 920 921 922 923 void 924 gem_start(ifp) 925 struct ifnet *ifp; 926 { 927 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 928 struct mbuf *m0, *m; 929 struct gem_txsoft *txs, *last_txs; 930 bus_dmamap_t dmamap; 931 int error, firsttx, nexttx, lasttx, ofree, seg; 932 933 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 934 return; 935 936 /* 937 * Remember the previous number of free descriptors and 938 * the first descriptor we'll use. 939 */ 940 ofree = sc->sc_txfree; 941 firsttx = sc->sc_txnext; 942 943 DPRINTF(sc, ("%s: gem_start: txfree %d, txnext %d\n", 944 sc->sc_dev.dv_xname, ofree, firsttx)); 945 946 /* 947 * Loop through the send queue, setting up transmit descriptors 948 * until we drain the queue, or use up all available transmit 949 * descriptors. 950 */ 951 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 952 sc->sc_txfree != 0) { 953 /* 954 * Grab a packet off the queue. 955 */ 956 IFQ_POLL(&ifp->if_snd, m0); 957 if (m0 == NULL) 958 break; 959 m = NULL; 960 961 dmamap = txs->txs_dmamap; 962 963 /* 964 * Load the DMA map. If this fails, the packet either 965 * didn't fit in the alloted number of segments, or we were 966 * short on resources. In this case, we'll copy and try 967 * again. 968 */ 969 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m0, 970 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 971 MGETHDR(m, M_DONTWAIT, MT_DATA); 972 if (m == NULL) { 973 printf("%s: unable to allocate Tx mbuf\n", 974 sc->sc_dev.dv_xname); 975 break; 976 } 977 if (m0->m_pkthdr.len > MHLEN) { 978 MCLGET(m, M_DONTWAIT); 979 if ((m->m_flags & M_EXT) == 0) { 980 printf("%s: unable to allocate Tx " 981 "cluster\n", sc->sc_dev.dv_xname); 982 m_freem(m); 983 break; 984 } 985 } 986 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 987 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 988 error = bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, 989 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 990 if (error) { 991 printf("%s: unable to load Tx buffer, " 992 "error = %d\n", sc->sc_dev.dv_xname, error); 993 break; 994 } 995 } 996 997 /* 998 * Ensure we have enough descriptors free to describe 999 * the packet. 1000 */ 1001 if (dmamap->dm_nsegs > sc->sc_txfree) { 1002 /* 1003 * Not enough free descriptors to transmit this 1004 * packet. We haven't committed to anything yet, 1005 * so just unload the DMA map, put the packet 1006 * back on the queue, and punt. Notify the upper 1007 * layer that there are no more slots left. 1008 * 1009 * XXX We could allocate an mbuf and copy, but 1010 * XXX it is worth it? 1011 */ 1012 ifp->if_flags |= IFF_OACTIVE; 1013 bus_dmamap_unload(sc->sc_dmatag, dmamap); 1014 if (m != NULL) 1015 m_freem(m); 1016 break; 1017 } 1018 1019 IFQ_DEQUEUE(&ifp->if_snd, m0); 1020 if (m != NULL) { 1021 m_freem(m0); 1022 m0 = m; 1023 } 1024 1025 /* 1026 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1027 */ 1028 1029 /* Sync the DMA map. */ 1030 bus_dmamap_sync(sc->sc_dmatag, dmamap, 0, dmamap->dm_mapsize, 1031 BUS_DMASYNC_PREWRITE); 1032 1033 /* 1034 * Initialize the transmit descriptors. 1035 */ 1036 for (nexttx = sc->sc_txnext, seg = 0; 1037 seg < dmamap->dm_nsegs; 1038 seg++, nexttx = GEM_NEXTTX(nexttx)) { 1039 uint64_t flags; 1040 1041 /* 1042 * If this is the first descriptor we're 1043 * enqueueing, set the start of packet flag, 1044 * and the checksum stuff if we want the hardware 1045 * to do it. 1046 */ 1047 sc->sc_txdescs[nexttx].gd_addr = 1048 GEM_DMA_WRITE(sc, dmamap->dm_segs[seg].ds_addr); 1049 flags = dmamap->dm_segs[seg].ds_len & GEM_TD_BUFSIZE; 1050 if (nexttx == firsttx) { 1051 flags |= GEM_TD_START_OF_PACKET; 1052 } 1053 if (seg == dmamap->dm_nsegs - 1) { 1054 flags |= GEM_TD_END_OF_PACKET; 1055 } 1056 sc->sc_txdescs[nexttx].gd_flags = 1057 GEM_DMA_WRITE(sc, flags); 1058 lasttx = nexttx; 1059 } 1060 1061 #ifdef GEM_DEBUG 1062 if (ifp->if_flags & IFF_DEBUG) { 1063 printf(" gem_start %p transmit chain:\n", txs); 1064 for (seg = sc->sc_txnext;; seg = GEM_NEXTTX(seg)) { 1065 printf("descriptor %d:\t", seg); 1066 printf("gd_flags: 0x%016llx\t", (long long) 1067 GEM_DMA_READ(sc, sc->sc_txdescs[seg].gd_flags)); 1068 printf("gd_addr: 0x%016llx\n", (long long) 1069 GEM_DMA_READ(sc, sc->sc_txdescs[seg].gd_addr)); 1070 if (seg == lasttx) 1071 break; 1072 } 1073 } 1074 #endif 1075 1076 /* Sync the descriptors we're using. */ 1077 GEM_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1078 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1079 1080 /* 1081 * Store a pointer to the packet so we can free it later, 1082 * and remember what txdirty will be once the packet is 1083 * done. 1084 */ 1085 txs->txs_mbuf = m0; 1086 txs->txs_firstdesc = sc->sc_txnext; 1087 txs->txs_lastdesc = lasttx; 1088 txs->txs_ndescs = dmamap->dm_nsegs; 1089 1090 /* Advance the tx pointer. */ 1091 sc->sc_txfree -= dmamap->dm_nsegs; 1092 sc->sc_txnext = nexttx; 1093 1094 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs, txs_q); 1095 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1096 1097 last_txs = txs; 1098 1099 #if NBPFILTER > 0 1100 /* 1101 * Pass the packet to any BPF listeners. 1102 */ 1103 if (ifp->if_bpf) 1104 bpf_mtap(ifp->if_bpf, m0); 1105 #endif /* NBPFILTER > 0 */ 1106 } 1107 1108 if (txs == NULL || sc->sc_txfree == 0) { 1109 /* No more slots left; notify upper layer. */ 1110 ifp->if_flags |= IFF_OACTIVE; 1111 } 1112 1113 if (sc->sc_txfree != ofree) { 1114 DPRINTF(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 1115 sc->sc_dev.dv_xname, lasttx, firsttx)); 1116 /* 1117 * The entire packet chain is set up. 1118 * Kick the transmitter. 1119 */ 1120 DPRINTF(sc, ("%s: gem_start: kicking tx %d\n", 1121 sc->sc_dev.dv_xname, nexttx)); 1122 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_TX_KICK, 1123 sc->sc_txnext); 1124 1125 /* Set a watchdog timer in case the chip flakes out. */ 1126 ifp->if_timer = 5; 1127 DPRINTF(sc, ("%s: gem_start: watchdog %d\n", 1128 sc->sc_dev.dv_xname, ifp->if_timer)); 1129 } 1130 } 1131 1132 /* 1133 * Transmit interrupt. 1134 */ 1135 int 1136 gem_tint(sc) 1137 struct gem_softc *sc; 1138 { 1139 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1140 bus_space_tag_t t = sc->sc_bustag; 1141 bus_space_handle_t mac = sc->sc_h; 1142 struct gem_txsoft *txs; 1143 int txlast; 1144 1145 1146 DPRINTF(sc, ("%s: gem_tint\n", sc->sc_dev.dv_xname)); 1147 1148 /* 1149 * Unload collision counters 1150 */ 1151 ifp->if_collisions += 1152 bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) + 1153 bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT) + 1154 bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) + 1155 bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT); 1156 1157 /* 1158 * then clear the hardware counters. 1159 */ 1160 bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0); 1161 bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0); 1162 bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0); 1163 bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0); 1164 1165 /* 1166 * Go through our Tx list and free mbufs for those 1167 * frames that have been transmitted. 1168 */ 1169 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1170 GEM_CDTXSYNC(sc, txs->txs_lastdesc, 1171 txs->txs_ndescs, 1172 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1173 1174 #ifdef GEM_DEBUG 1175 if (ifp->if_flags & IFF_DEBUG) { 1176 int i; 1177 printf(" txsoft %p transmit chain:\n", txs); 1178 for (i = txs->txs_firstdesc;; i = GEM_NEXTTX(i)) { 1179 printf("descriptor %d: ", i); 1180 printf("gd_flags: 0x%016llx\t", (long long) 1181 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags)); 1182 printf("gd_addr: 0x%016llx\n", (long long) 1183 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr)); 1184 if (i == txs->txs_lastdesc) 1185 break; 1186 } 1187 } 1188 #endif 1189 1190 /* 1191 * In theory, we could harveast some descriptors before 1192 * the ring is empty, but that's a bit complicated. 1193 * 1194 * GEM_TX_COMPLETION points to the last descriptor 1195 * processed +1. 1196 */ 1197 txlast = bus_space_read_4(t, mac, GEM_TX_COMPLETION); 1198 DPRINTF(sc, 1199 ("gem_tint: txs->txs_lastdesc = %d, txlast = %d\n", 1200 txs->txs_lastdesc, txlast)); 1201 if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1202 if ((txlast >= txs->txs_firstdesc) && 1203 (txlast <= txs->txs_lastdesc)) 1204 break; 1205 } else { 1206 /* Ick -- this command wraps */ 1207 if ((txlast >= txs->txs_firstdesc) || 1208 (txlast <= txs->txs_lastdesc)) 1209 break; 1210 } 1211 1212 DPRINTF(sc, ("gem_tint: releasing a desc\n")); 1213 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs, txs_q); 1214 1215 sc->sc_txfree += txs->txs_ndescs; 1216 1217 if (txs->txs_mbuf == NULL) { 1218 #ifdef DIAGNOSTIC 1219 panic("gem_txintr: null mbuf"); 1220 #endif 1221 } 1222 1223 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 1224 0, txs->txs_dmamap->dm_mapsize, 1225 BUS_DMASYNC_POSTWRITE); 1226 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 1227 m_freem(txs->txs_mbuf); 1228 txs->txs_mbuf = NULL; 1229 1230 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1231 1232 ifp->if_opackets++; 1233 } 1234 1235 DPRINTF(sc, ("gem_tint: GEM_TX_STATE_MACHINE %x " 1236 "GEM_TX_DATA_PTR %llx " 1237 "GEM_TX_COMPLETION %x\n", 1238 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_STATE_MACHINE), 1239 ((long long) bus_space_read_4(sc->sc_bustag, sc->sc_h, 1240 GEM_TX_DATA_PTR_HI) << 32) | 1241 bus_space_read_4(sc->sc_bustag, sc->sc_h, 1242 GEM_TX_DATA_PTR_LO), 1243 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_COMPLETION))); 1244 1245 gem_start(ifp); 1246 1247 if (SIMPLEQ_FIRST(&sc->sc_txdirtyq) == NULL) 1248 ifp->if_timer = 0; 1249 DPRINTF(sc, ("%s: gem_tint: watchdog %d\n", 1250 sc->sc_dev.dv_xname, ifp->if_timer)); 1251 1252 return (1); 1253 } 1254 1255 /* 1256 * Receive interrupt. 1257 */ 1258 int 1259 gem_rint(sc) 1260 struct gem_softc *sc; 1261 { 1262 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1263 bus_space_tag_t t = sc->sc_bustag; 1264 bus_space_handle_t h = sc->sc_h; 1265 struct ether_header *eh; 1266 struct gem_rxsoft *rxs; 1267 struct mbuf *m; 1268 u_int64_t rxstat; 1269 int i, len; 1270 1271 DPRINTF(sc, ("%s: gem_rint\n", sc->sc_dev.dv_xname)); 1272 /* 1273 * XXXX Read the lastrx only once at the top for speed. 1274 */ 1275 DPRINTF(sc, ("gem_rint: sc->rxptr %d, complete %d\n", 1276 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION))); 1277 for (i = sc->sc_rxptr; i != bus_space_read_4(t, h, GEM_RX_COMPLETION); 1278 i = GEM_NEXTRX(i)) { 1279 rxs = &sc->sc_rxsoft[i]; 1280 1281 GEM_CDRXSYNC(sc, i, 1282 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1283 1284 rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags); 1285 1286 if (rxstat & GEM_RD_OWN) { 1287 printf("gem_rint: completed descriptor " 1288 "still owned %d\n", i); 1289 /* 1290 * We have processed all of the receive buffers. 1291 */ 1292 break; 1293 } 1294 1295 if (rxstat & GEM_RD_BAD_CRC) { 1296 printf("%s: receive error: CRC error\n", 1297 sc->sc_dev.dv_xname); 1298 GEM_INIT_RXDESC(sc, i); 1299 continue; 1300 } 1301 1302 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1303 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1304 #ifdef GEM_DEBUG 1305 if (ifp->if_flags & IFF_DEBUG) { 1306 printf(" rxsoft %p descriptor %d: ", rxs, i); 1307 printf("gd_flags: 0x%016llx\t", (long long) 1308 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags)); 1309 printf("gd_addr: 0x%016llx\n", (long long) 1310 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr)); 1311 } 1312 #endif 1313 1314 /* 1315 * No errors; receive the packet. Note the Gem 1316 * includes the CRC with every packet. 1317 */ 1318 len = GEM_RD_BUFLEN(rxstat); 1319 1320 /* 1321 * Allocate a new mbuf cluster. If that fails, we are 1322 * out of memory, and must drop the packet and recycle 1323 * the buffer that's already attached to this descriptor. 1324 */ 1325 m = rxs->rxs_mbuf; 1326 if (gem_add_rxbuf(sc, i) != 0) { 1327 ifp->if_ierrors++; 1328 GEM_INIT_RXDESC(sc, i); 1329 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1330 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1331 continue; 1332 } 1333 m->m_data += 2; /* We're already off by two */ 1334 1335 ifp->if_ipackets++; 1336 eh = mtod(m, struct ether_header *); 1337 m->m_flags |= M_HASFCS; 1338 m->m_pkthdr.rcvif = ifp; 1339 m->m_pkthdr.len = m->m_len = len; 1340 1341 #if NBPFILTER > 0 1342 /* 1343 * Pass this up to any BPF listeners, but only 1344 * pass it up the stack if its for us. 1345 */ 1346 if (ifp->if_bpf) 1347 bpf_mtap(ifp->if_bpf, m); 1348 #endif /* NPBFILTER > 0 */ 1349 1350 #if 0 1351 /* 1352 * We sometimes have to run the 21140 in Hash-Only 1353 * mode. If we're in that mode, and not in promiscuous 1354 * mode, and we have a unicast packet that isn't for 1355 * us, then drop it. 1356 */ 1357 if (sc->sc_filtmode == TDCTL_Tx_FT_HASHONLY && 1358 (ifp->if_flags & IFF_PROMISC) == 0 && 1359 ETHER_IS_MULTICAST(eh->ether_dhost) == 0 && 1360 memcmp(LLADDR(ifp->if_sadl), eh->ether_dhost, 1361 ETHER_ADDR_LEN) != 0) { 1362 m_freem(m); 1363 continue; 1364 } 1365 #endif 1366 1367 /* Pass it on. */ 1368 (*ifp->if_input)(ifp, m); 1369 } 1370 1371 /* Update the receive pointer. */ 1372 sc->sc_rxptr = i; 1373 bus_space_write_4(t, h, GEM_RX_KICK, i); 1374 1375 DPRINTF(sc, ("gem_rint: done sc->rxptr %d, complete %d\n", 1376 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION))); 1377 1378 return (1); 1379 } 1380 1381 1382 /* 1383 * gem_add_rxbuf: 1384 * 1385 * Add a receive buffer to the indicated descriptor. 1386 */ 1387 int 1388 gem_add_rxbuf(struct gem_softc *sc, int idx) 1389 { 1390 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1391 struct mbuf *m; 1392 int error; 1393 1394 MGETHDR(m, M_DONTWAIT, MT_DATA); 1395 if (m == NULL) 1396 return (ENOBUFS); 1397 1398 MCLGET(m, M_DONTWAIT); 1399 if ((m->m_flags & M_EXT) == 0) { 1400 m_freem(m); 1401 return (ENOBUFS); 1402 } 1403 1404 #ifdef GEM_DEBUG 1405 /* bzero the packet to check dma */ 1406 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 1407 #endif 1408 1409 if (rxs->rxs_mbuf != NULL) 1410 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 1411 1412 rxs->rxs_mbuf = m; 1413 1414 error = bus_dmamap_load(sc->sc_dmatag, rxs->rxs_dmamap, 1415 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1416 BUS_DMA_READ|BUS_DMA_NOWAIT); 1417 if (error) { 1418 printf("%s: can't load rx DMA map %d, error = %d\n", 1419 sc->sc_dev.dv_xname, idx, error); 1420 panic("gem_add_rxbuf"); /* XXX */ 1421 } 1422 1423 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1424 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1425 1426 GEM_INIT_RXDESC(sc, idx); 1427 1428 return (0); 1429 } 1430 1431 1432 int 1433 gem_eint(sc, status) 1434 struct gem_softc *sc; 1435 u_int status; 1436 { 1437 char bits[128]; 1438 1439 if ((status & GEM_INTR_MIF) != 0) { 1440 printf("%s: XXXlink status changed\n", sc->sc_dev.dv_xname); 1441 return (1); 1442 } 1443 1444 printf("%s: status=%s\n", sc->sc_dev.dv_xname, 1445 bitmask_snprintf(status, GEM_INTR_BITS, bits, sizeof(bits))); 1446 return (1); 1447 } 1448 1449 1450 int 1451 gem_intr(v) 1452 void *v; 1453 { 1454 struct gem_softc *sc = (struct gem_softc *)v; 1455 bus_space_tag_t t = sc->sc_bustag; 1456 bus_space_handle_t seb = sc->sc_h; 1457 u_int32_t status; 1458 int r = 0; 1459 #ifdef GEM_DEBUG 1460 char bits[128]; 1461 #endif 1462 1463 status = bus_space_read_4(t, seb, GEM_STATUS); 1464 DPRINTF(sc, ("%s: gem_intr: cplt %xstatus %s\n", 1465 sc->sc_dev.dv_xname, (status>>19), 1466 bitmask_snprintf(status, GEM_INTR_BITS, bits, sizeof(bits)))); 1467 1468 if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0) 1469 r |= gem_eint(sc, status); 1470 1471 if ((status & 1472 (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) 1473 != 0) 1474 r |= gem_tint(sc); 1475 1476 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) 1477 r |= gem_rint(sc); 1478 1479 /* We should eventually do more than just print out error stats. */ 1480 if (status & GEM_INTR_TX_MAC) { 1481 int txstat = bus_space_read_4(t, seb, GEM_MAC_TX_STATUS); 1482 if (txstat & ~GEM_MAC_TX_XMIT_DONE) 1483 printf("MAC tx fault, status %x\n", txstat); 1484 } 1485 if (status & GEM_INTR_RX_MAC) { 1486 int rxstat = bus_space_read_4(t, seb, GEM_MAC_RX_STATUS); 1487 if (rxstat & ~GEM_MAC_RX_DONE) 1488 printf("MAC rx fault, status %x\n", rxstat); 1489 } 1490 return (r); 1491 } 1492 1493 1494 void 1495 gem_watchdog(ifp) 1496 struct ifnet *ifp; 1497 { 1498 struct gem_softc *sc = ifp->if_softc; 1499 1500 DPRINTF(sc, ("gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x " 1501 "GEM_MAC_RX_CONFIG %x\n", 1502 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_CONFIG), 1503 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_STATUS), 1504 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_CONFIG))); 1505 1506 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1507 ++ifp->if_oerrors; 1508 1509 /* Try to get more packets going. */ 1510 gem_start(ifp); 1511 } 1512 1513 /* 1514 * Initialize the MII Management Interface 1515 */ 1516 void 1517 gem_mifinit(sc) 1518 struct gem_softc *sc; 1519 { 1520 bus_space_tag_t t = sc->sc_bustag; 1521 bus_space_handle_t mif = sc->sc_h; 1522 1523 /* Configure the MIF in frame mode */ 1524 sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1525 sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA; 1526 bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config); 1527 } 1528 1529 /* 1530 * MII interface 1531 * 1532 * The GEM MII interface supports at least three different operating modes: 1533 * 1534 * Bitbang mode is implemented using data, clock and output enable registers. 1535 * 1536 * Frame mode is implemented by loading a complete frame into the frame 1537 * register and polling the valid bit for completion. 1538 * 1539 * Polling mode uses the frame register but completion is indicated by 1540 * an interrupt. 1541 * 1542 */ 1543 static int 1544 gem_mii_readreg(self, phy, reg) 1545 struct device *self; 1546 int phy, reg; 1547 { 1548 struct gem_softc *sc = (void *)self; 1549 bus_space_tag_t t = sc->sc_bustag; 1550 bus_space_handle_t mif = sc->sc_h; 1551 int n; 1552 u_int32_t v; 1553 1554 #ifdef GEM_DEBUG1 1555 if (sc->sc_debug) 1556 printf("gem_mii_readreg: phy %d reg %d\n", phy, reg); 1557 #endif 1558 1559 #if 0 1560 /* Select the desired PHY in the MIF configuration register */ 1561 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1562 /* Clear PHY select bit */ 1563 v &= ~GEM_MIF_CONFIG_PHY_SEL; 1564 if (phy == GEM_PHYAD_EXTERNAL) 1565 /* Set PHY select bit to get at external device */ 1566 v |= GEM_MIF_CONFIG_PHY_SEL; 1567 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 1568 #endif 1569 1570 /* Construct the frame command */ 1571 v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) | 1572 GEM_MIF_FRAME_READ; 1573 1574 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1575 for (n = 0; n < 100; n++) { 1576 DELAY(1); 1577 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1578 if (v & GEM_MIF_FRAME_TA0) 1579 return (v & GEM_MIF_FRAME_DATA); 1580 } 1581 1582 printf("%s: mii_read timeout\n", sc->sc_dev.dv_xname); 1583 return (0); 1584 } 1585 1586 static void 1587 gem_mii_writereg(self, phy, reg, val) 1588 struct device *self; 1589 int phy, reg, val; 1590 { 1591 struct gem_softc *sc = (void *)self; 1592 bus_space_tag_t t = sc->sc_bustag; 1593 bus_space_handle_t mif = sc->sc_h; 1594 int n; 1595 u_int32_t v; 1596 1597 #ifdef GEM_DEBUG1 1598 if (sc->sc_debug) 1599 printf("gem_mii_writereg: phy %d reg %d val %x\n", 1600 phy, reg, val); 1601 #endif 1602 1603 #if 0 1604 /* Select the desired PHY in the MIF configuration register */ 1605 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1606 /* Clear PHY select bit */ 1607 v &= ~GEM_MIF_CONFIG_PHY_SEL; 1608 if (phy == GEM_PHYAD_EXTERNAL) 1609 /* Set PHY select bit to get at external device */ 1610 v |= GEM_MIF_CONFIG_PHY_SEL; 1611 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 1612 #endif 1613 /* Construct the frame command */ 1614 v = GEM_MIF_FRAME_WRITE | 1615 (phy << GEM_MIF_PHY_SHIFT) | 1616 (reg << GEM_MIF_REG_SHIFT) | 1617 (val & GEM_MIF_FRAME_DATA); 1618 1619 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1620 for (n = 0; n < 100; n++) { 1621 DELAY(1); 1622 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1623 if (v & GEM_MIF_FRAME_TA0) 1624 return; 1625 } 1626 1627 printf("%s: mii_write timeout\n", sc->sc_dev.dv_xname); 1628 } 1629 1630 static void 1631 gem_mii_statchg(dev) 1632 struct device *dev; 1633 { 1634 struct gem_softc *sc = (void *)dev; 1635 #ifdef GEM_DEBUG 1636 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1637 #endif 1638 bus_space_tag_t t = sc->sc_bustag; 1639 bus_space_handle_t mac = sc->sc_h; 1640 u_int32_t v; 1641 1642 #ifdef GEM_DEBUG 1643 if (sc->sc_debug) 1644 printf("gem_mii_statchg: status change: phy = %d\n", 1645 sc->sc_phys[instance];); 1646 #endif 1647 1648 1649 /* Set tx full duplex options */ 1650 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0); 1651 delay(10000); /* reg must be cleared and delay before changing. */ 1652 v = GEM_MAC_TX_ENA_IPG0|GEM_MAC_TX_NGU|GEM_MAC_TX_NGU_LIMIT| 1653 GEM_MAC_TX_ENABLE; 1654 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) { 1655 v |= GEM_MAC_TX_IGN_CARRIER|GEM_MAC_TX_IGN_COLLIS; 1656 } 1657 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, v); 1658 1659 /* XIF Configuration */ 1660 /* We should really calculate all this rather than rely on defaults */ 1661 v = bus_space_read_4(t, mac, GEM_MAC_XIF_CONFIG); 1662 v = GEM_MAC_XIF_LINK_LED; 1663 v |= GEM_MAC_XIF_TX_MII_ENA; 1664 /* If an external transceiver is connected, enable its MII drivers */ 1665 sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG); 1666 if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) { 1667 /* External MII needs echo disable if half duplex. */ 1668 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1669 /* turn on full duplex LED */ 1670 v |= GEM_MAC_XIF_FDPLX_LED; 1671 else 1672 /* half duplex -- disable echo */ 1673 v |= GEM_MAC_XIF_ECHO_DISABL; 1674 } else 1675 /* Internal MII needs buf enable */ 1676 v |= GEM_MAC_XIF_MII_BUF_ENA; 1677 bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v); 1678 } 1679 1680 int 1681 gem_mediachange(ifp) 1682 struct ifnet *ifp; 1683 { 1684 struct gem_softc *sc = ifp->if_softc; 1685 1686 if (IFM_TYPE(sc->sc_media.ifm_media) != IFM_ETHER) 1687 return (EINVAL); 1688 1689 return (mii_mediachg(&sc->sc_mii)); 1690 } 1691 1692 void 1693 gem_mediastatus(ifp, ifmr) 1694 struct ifnet *ifp; 1695 struct ifmediareq *ifmr; 1696 { 1697 struct gem_softc *sc = ifp->if_softc; 1698 1699 if ((ifp->if_flags & IFF_UP) == 0) 1700 return; 1701 1702 mii_pollstat(&sc->sc_mii); 1703 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1704 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1705 } 1706 1707 int gem_ioctldebug = 0; 1708 /* 1709 * Process an ioctl request. 1710 */ 1711 int 1712 gem_ioctl(ifp, cmd, data) 1713 struct ifnet *ifp; 1714 u_long cmd; 1715 caddr_t data; 1716 { 1717 struct gem_softc *sc = ifp->if_softc; 1718 struct ifreq *ifr = (struct ifreq *)data; 1719 int s, error = 0; 1720 1721 1722 switch (cmd) { 1723 case SIOCGIFMEDIA: 1724 case SIOCSIFMEDIA: 1725 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1726 break; 1727 1728 default: 1729 error = ether_ioctl(ifp, cmd, data); 1730 if (error == ENETRESET) { 1731 /* 1732 * Multicast list has changed; set the hardware filter 1733 * accordingly. 1734 */ 1735 if (gem_ioctldebug) printf("reset1\n"); 1736 gem_init(ifp); 1737 delay(50000); 1738 error = 0; 1739 } 1740 break; 1741 } 1742 1743 /* Try to get things going again */ 1744 if (ifp->if_flags & IFF_UP) { 1745 if (gem_ioctldebug) printf("start\n"); 1746 gem_start(ifp); 1747 } 1748 splx(s); 1749 return (error); 1750 } 1751 1752 1753 void 1754 gem_shutdown(arg) 1755 void *arg; 1756 { 1757 struct gem_softc *sc = (struct gem_softc *)arg; 1758 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1759 1760 gem_stop(ifp, 1); 1761 } 1762 1763 /* 1764 * Set up the logical address filter. 1765 */ 1766 void 1767 gem_setladrf(sc) 1768 struct gem_softc *sc; 1769 { 1770 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1771 struct ether_multi *enm; 1772 struct ether_multistep step; 1773 struct ethercom *ec = &sc->sc_ethercom; 1774 bus_space_tag_t t = sc->sc_bustag; 1775 bus_space_handle_t h = sc->sc_h; 1776 u_char *cp; 1777 u_int32_t crc; 1778 u_int32_t hash[16]; 1779 u_int32_t v; 1780 int len; 1781 1782 /* Clear hash table */ 1783 memset(hash, 0, sizeof(hash)); 1784 1785 /* Get current RX configuration */ 1786 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 1787 1788 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1789 /* Turn on promiscuous mode; turn off the hash filter */ 1790 v |= GEM_MAC_RX_PROMISCUOUS; 1791 v &= ~GEM_MAC_RX_HASH_FILTER; 1792 ifp->if_flags |= IFF_ALLMULTI; 1793 goto chipit; 1794 } 1795 1796 /* Turn off promiscuous mode; turn on the hash filter */ 1797 v &= ~GEM_MAC_RX_PROMISCUOUS; 1798 v |= GEM_MAC_RX_HASH_FILTER; 1799 1800 /* 1801 * Set up multicast address filter by passing all multicast addresses 1802 * through a crc generator, and then using the high order 6 bits as an 1803 * index into the 256 bit logical address filter. The high order bit 1804 * selects the word, while the rest of the bits select the bit within 1805 * the word. 1806 */ 1807 1808 ETHER_FIRST_MULTI(step, ec, enm); 1809 while (enm != NULL) { 1810 if (ether_cmp(enm->enm_addrlo, enm->enm_addrhi)) { 1811 /* 1812 * We must listen to a range of multicast addresses. 1813 * For now, just accept all multicasts, rather than 1814 * trying to set only those filter bits needed to match 1815 * the range. (At this time, the only use of address 1816 * ranges is for IP multicast routing, for which the 1817 * range is big enough to require all bits set.) 1818 */ 1819 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1820 ifp->if_flags |= IFF_ALLMULTI; 1821 goto chipit; 1822 } 1823 1824 cp = enm->enm_addrlo; 1825 crc = 0xffffffff; 1826 for (len = sizeof(enm->enm_addrlo); --len >= 0;) { 1827 int octet = *cp++; 1828 int i; 1829 1830 #define MC_POLY_LE 0xedb88320UL /* mcast crc, little endian */ 1831 for (i = 0; i < 8; i++) { 1832 if ((crc & 1) ^ (octet & 1)) { 1833 crc >>= 1; 1834 crc ^= MC_POLY_LE; 1835 } else { 1836 crc >>= 1; 1837 } 1838 octet >>= 1; 1839 } 1840 } 1841 /* Just want the 8 most significant bits. */ 1842 crc >>= 24; 1843 1844 /* Set the corresponding bit in the filter. */ 1845 hash[crc >> 4] |= 1 << (crc & 0xf); 1846 1847 ETHER_NEXT_MULTI(step, enm); 1848 } 1849 1850 ifp->if_flags &= ~IFF_ALLMULTI; 1851 1852 chipit: 1853 /* Now load the hash table into the chip */ 1854 bus_space_write_4(t, h, GEM_MAC_HASH0, hash[0]); 1855 bus_space_write_4(t, h, GEM_MAC_HASH1, hash[1]); 1856 bus_space_write_4(t, h, GEM_MAC_HASH2, hash[2]); 1857 bus_space_write_4(t, h, GEM_MAC_HASH3, hash[3]); 1858 bus_space_write_4(t, h, GEM_MAC_HASH4, hash[4]); 1859 bus_space_write_4(t, h, GEM_MAC_HASH5, hash[5]); 1860 bus_space_write_4(t, h, GEM_MAC_HASH6, hash[6]); 1861 bus_space_write_4(t, h, GEM_MAC_HASH7, hash[7]); 1862 bus_space_write_4(t, h, GEM_MAC_HASH8, hash[8]); 1863 bus_space_write_4(t, h, GEM_MAC_HASH9, hash[9]); 1864 bus_space_write_4(t, h, GEM_MAC_HASH10, hash[10]); 1865 bus_space_write_4(t, h, GEM_MAC_HASH11, hash[11]); 1866 bus_space_write_4(t, h, GEM_MAC_HASH12, hash[12]); 1867 bus_space_write_4(t, h, GEM_MAC_HASH13, hash[13]); 1868 bus_space_write_4(t, h, GEM_MAC_HASH14, hash[14]); 1869 bus_space_write_4(t, h, GEM_MAC_HASH15, hash[15]); 1870 1871 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 1872 } 1873 1874 #if notyet 1875 1876 /* 1877 * gem_power: 1878 * 1879 * Power management (suspend/resume) hook. 1880 */ 1881 void 1882 gem_power(why, arg) 1883 int why; 1884 void *arg; 1885 { 1886 struct gem_softc *sc = arg; 1887 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1888 int s; 1889 1890 s = splnet(); 1891 switch (why) { 1892 case PWR_SUSPEND: 1893 case PWR_STANDBY: 1894 gem_stop(ifp, 1); 1895 if (sc->sc_power != NULL) 1896 (*sc->sc_power)(sc, why); 1897 break; 1898 case PWR_RESUME: 1899 if (ifp->if_flags & IFF_UP) { 1900 if (sc->sc_power != NULL) 1901 (*sc->sc_power)(sc, why); 1902 gem_init(ifp); 1903 } 1904 break; 1905 case PWR_SOFTSUSPEND: 1906 case PWR_SOFTSTANDBY: 1907 case PWR_SOFTRESUME: 1908 break; 1909 } 1910 splx(s); 1911 } 1912 #endif 1913
Indexes created Tue Sep 23 14:10:03 GMT 2025