gem.c revision 1.6
1 /* $NetBSD: gem.c,v 1.6 2001/10/18 15:09:15 thorpej Exp $ */ 2 3 /* 4 * 5 * Copyright (C) 2001 Eduardo Horvath. 6 * All rights reserved. 7 * 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 */ 31 32 /* 33 * Driver for Sun GEM ethernet controllers. 34 */ 35 36 #include "bpfilter.h" 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/callout.h> 41 #include <sys/mbuf.h> 42 #include <sys/syslog.h> 43 #include <sys/malloc.h> 44 #include <sys/kernel.h> 45 #include <sys/socket.h> 46 #include <sys/ioctl.h> 47 #include <sys/errno.h> 48 #include <sys/device.h> 49 50 #include <machine/endian.h> 51 52 #include <uvm/uvm_extern.h> 53 54 #include <net/if.h> 55 #include <net/if_dl.h> 56 #include <net/if_media.h> 57 #include <net/if_ether.h> 58 59 #if NBPFILTER > 0 60 #include <net/bpf.h> 61 #endif 62 63 #include <machine/bus.h> 64 #include <machine/intr.h> 65 66 #include <dev/mii/mii.h> 67 #include <dev/mii/miivar.h> 68 #include <dev/mii/mii_bitbang.h> 69 70 #include <dev/ic/gemreg.h> 71 #include <dev/ic/gemvar.h> 72 73 #define TRIES 10000 74 75 void gem_start __P((struct ifnet *)); 76 void gem_stop __P((struct ifnet *, int)); 77 int gem_ioctl __P((struct ifnet *, u_long, caddr_t)); 78 void gem_tick __P((void *)); 79 void gem_watchdog __P((struct ifnet *)); 80 void gem_shutdown __P((void *)); 81 int gem_init __P((struct ifnet *)); 82 void gem_init_regs(struct gem_softc *sc); 83 static int gem_ringsize(int sz); 84 int gem_meminit __P((struct gem_softc *)); 85 void gem_mifinit __P((struct gem_softc *)); 86 void gem_reset __P((struct gem_softc *)); 87 int gem_reset_rx(struct gem_softc *sc); 88 int gem_reset_tx(struct gem_softc *sc); 89 int gem_disable_rx(struct gem_softc *sc); 90 int gem_disable_tx(struct gem_softc *sc); 91 void gem_rxdrain(struct gem_softc *sc); 92 int gem_add_rxbuf(struct gem_softc *sc, int idx); 93 void gem_setladrf __P((struct gem_softc *)); 94 95 /* MII methods & callbacks */ 96 static int gem_mii_readreg __P((struct device *, int, int)); 97 static void gem_mii_writereg __P((struct device *, int, int, int)); 98 static void gem_mii_statchg __P((struct device *)); 99 100 int gem_mediachange __P((struct ifnet *)); 101 void gem_mediastatus __P((struct ifnet *, struct ifmediareq *)); 102 103 struct mbuf *gem_get __P((struct gem_softc *, int, int)); 104 int gem_put __P((struct gem_softc *, int, struct mbuf *)); 105 void gem_read __P((struct gem_softc *, int, int)); 106 int gem_eint __P((struct gem_softc *, u_int)); 107 int gem_rint __P((struct gem_softc *)); 108 int gem_tint __P((struct gem_softc *)); 109 void gem_power __P((int, void *)); 110 111 /* Default buffer copy routines */ 112 void gem_copytobuf_contig __P((struct gem_softc *, void *, int, int)); 113 void gem_copyfrombuf_contig __P((struct gem_softc *, void *, int, int)); 114 void gem_zerobuf_contig __P((struct gem_softc *, int, int)); 115 116 117 #ifdef GEM_DEBUG 118 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 119 printf x 120 #else 121 #define DPRINTF(sc, x) /* nothing */ 122 #endif 123 124 125 /* 126 * gem_attach: 127 * 128 * Attach a Gem interface to the system. 129 */ 130 void 131 gem_attach(sc, enaddr) 132 struct gem_softc *sc; 133 const uint8_t *enaddr; 134 { 135 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 136 struct mii_data *mii = &sc->sc_mii; 137 struct mii_softc *child; 138 int i, error; 139 140 /* Make sure the chip is stopped. */ 141 ifp->if_softc = sc; 142 gem_reset(sc); 143 144 /* 145 * Allocate the control data structures, and create and load the 146 * DMA map for it. 147 */ 148 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 149 sizeof(struct gem_control_data), PAGE_SIZE, 0, &sc->sc_cdseg, 150 1, &sc->sc_cdnseg, 0)) != 0) { 151 printf("%s: unable to allocate control data, error = %d\n", 152 sc->sc_dev.dv_xname, error); 153 goto fail_0; 154 } 155 156 /* XXX should map this in with correct endianness */ 157 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg, 158 sizeof(struct gem_control_data), (caddr_t *)&sc->sc_control_data, 159 BUS_DMA_COHERENT)) != 0) { 160 printf("%s: unable to map control data, error = %d\n", 161 sc->sc_dev.dv_xname, error); 162 goto fail_1; 163 } 164 165 if ((error = bus_dmamap_create(sc->sc_dmatag, 166 sizeof(struct gem_control_data), 1, 167 sizeof(struct gem_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 168 printf("%s: unable to create control data DMA map, " 169 "error = %d\n", sc->sc_dev.dv_xname, error); 170 goto fail_2; 171 } 172 173 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 174 sc->sc_control_data, sizeof(struct gem_control_data), NULL, 175 0)) != 0) { 176 printf("%s: unable to load control data DMA map, error = %d\n", 177 sc->sc_dev.dv_xname, error); 178 goto fail_3; 179 } 180 181 /* 182 * Initialize the transmit job descriptors. 183 */ 184 SIMPLEQ_INIT(&sc->sc_txfreeq); 185 SIMPLEQ_INIT(&sc->sc_txdirtyq); 186 187 /* 188 * Create the transmit buffer DMA maps. 189 */ 190 for (i = 0; i < GEM_TXQUEUELEN; i++) { 191 struct gem_txsoft *txs; 192 193 txs = &sc->sc_txsoft[i]; 194 txs->txs_mbuf = NULL; 195 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 196 GEM_NTXSEGS, MCLBYTES, 0, 0, 197 &txs->txs_dmamap)) != 0) { 198 printf("%s: unable to create tx DMA map %d, " 199 "error = %d\n", sc->sc_dev.dv_xname, i, error); 200 goto fail_4; 201 } 202 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 203 } 204 205 /* 206 * Create the receive buffer DMA maps. 207 */ 208 for (i = 0; i < GEM_NRXDESC; i++) { 209 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, 210 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 211 printf("%s: unable to create rx DMA map %d, " 212 "error = %d\n", sc->sc_dev.dv_xname, i, error); 213 goto fail_5; 214 } 215 sc->sc_rxsoft[i].rxs_mbuf = NULL; 216 } 217 218 /* 219 * From this point forward, the attachment cannot fail. A failure 220 * before this point releases all resources that may have been 221 * allocated. 222 */ 223 224 /* Announce ourselves. */ 225 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 226 ether_sprintf(enaddr)); 227 228 /* Initialize ifnet structure. */ 229 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 230 ifp->if_softc = sc; 231 ifp->if_flags = 232 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 233 ifp->if_start = gem_start; 234 ifp->if_ioctl = gem_ioctl; 235 ifp->if_watchdog = gem_watchdog; 236 ifp->if_stop = gem_stop; 237 ifp->if_init = gem_init; 238 IFQ_SET_READY(&ifp->if_snd); 239 240 /* Initialize ifmedia structures and MII info */ 241 mii->mii_ifp = ifp; 242 mii->mii_readreg = gem_mii_readreg; 243 mii->mii_writereg = gem_mii_writereg; 244 mii->mii_statchg = gem_mii_statchg; 245 246 ifmedia_init(&mii->mii_media, 0, gem_mediachange, gem_mediastatus); 247 248 gem_mifinit(sc); 249 250 mii_attach(&sc->sc_dev, mii, 0xffffffff, 251 MII_PHY_ANY, MII_OFFSET_ANY, 0); 252 253 child = LIST_FIRST(&mii->mii_phys); 254 if (child == NULL) { 255 /* No PHY attached */ 256 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 257 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL); 258 } else { 259 /* 260 * Walk along the list of attached MII devices and 261 * establish an `MII instance' to `phy number' 262 * mapping. We'll use this mapping in media change 263 * requests to determine which phy to use to program 264 * the MIF configuration register. 265 */ 266 for (; child != NULL; child = LIST_NEXT(child, mii_list)) { 267 /* 268 * Note: we support just two PHYs: the built-in 269 * internal device and an external on the MII 270 * connector. 271 */ 272 if (child->mii_phy > 1 || child->mii_inst > 1) { 273 printf("%s: cannot accomodate MII device %s" 274 " at phy %d, instance %d\n", 275 sc->sc_dev.dv_xname, 276 child->mii_dev.dv_xname, 277 child->mii_phy, child->mii_inst); 278 continue; 279 } 280 281 sc->sc_phys[child->mii_inst] = child->mii_phy; 282 } 283 284 /* 285 * Now select and activate the PHY we will use. 286 * 287 * The order of preference is External (MDI1), 288 * Internal (MDI0), Serial Link (no MII). 289 */ 290 if (sc->sc_phys[1]) { 291 #ifdef DEBUG 292 printf("using external phy\n"); 293 #endif 294 sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL; 295 } else { 296 #ifdef DEBUG 297 printf("using internal phy\n"); 298 #endif 299 sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL; 300 } 301 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_MIF_CONFIG, 302 sc->sc_mif_config); 303 304 /* 305 * XXX - we can really do the following ONLY if the 306 * phy indeed has the auto negotiation capability!! 307 */ 308 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO); 309 } 310 311 /* claim 802.1q capability */ 312 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 313 314 /* Attach the interface. */ 315 if_attach(ifp); 316 ether_ifattach(ifp, enaddr); 317 318 sc->sc_sh = shutdownhook_establish(gem_shutdown, sc); 319 if (sc->sc_sh == NULL) 320 panic("gem_config: can't establish shutdownhook"); 321 322 #if NRND > 0 323 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 324 RND_TYPE_NET, 0); 325 #endif 326 327 328 #if notyet 329 /* 330 * Add a suspend hook to make sure we come back up after a 331 * resume. 332 */ 333 sc->sc_powerhook = powerhook_establish(gem_power, sc); 334 if (sc->sc_powerhook == NULL) 335 printf("%s: WARNING: unable to establish power hook\n", 336 sc->sc_dev.dv_xname); 337 #endif 338 339 callout_init(&sc->sc_tick_ch); 340 return; 341 342 /* 343 * Free any resources we've allocated during the failed attach 344 * attempt. Do this in reverse order and fall through. 345 */ 346 fail_5: 347 for (i = 0; i < GEM_NRXDESC; i++) { 348 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 349 bus_dmamap_destroy(sc->sc_dmatag, 350 sc->sc_rxsoft[i].rxs_dmamap); 351 } 352 fail_4: 353 for (i = 0; i < GEM_TXQUEUELEN; i++) { 354 if (sc->sc_txsoft[i].txs_dmamap != NULL) 355 bus_dmamap_destroy(sc->sc_dmatag, 356 sc->sc_txsoft[i].txs_dmamap); 357 } 358 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 359 fail_3: 360 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 361 fail_2: 362 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)sc->sc_control_data, 363 sizeof(struct gem_control_data)); 364 fail_1: 365 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 366 fail_0: 367 return; 368 } 369 370 371 void 372 gem_tick(arg) 373 void *arg; 374 { 375 struct gem_softc *sc = arg; 376 int s; 377 378 s = splnet(); 379 mii_tick(&sc->sc_mii); 380 splx(s); 381 382 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 383 384 } 385 386 void 387 gem_reset(sc) 388 struct gem_softc *sc; 389 { 390 bus_space_tag_t t = sc->sc_bustag; 391 bus_space_handle_t h = sc->sc_h; 392 int i; 393 int s; 394 395 s = splnet(); 396 DPRINTF(sc, ("%s: gem_reset\n", sc->sc_dev.dv_xname)); 397 gem_reset_rx(sc); 398 gem_reset_tx(sc); 399 400 /* Do a full reset */ 401 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX|GEM_RESET_TX); 402 for (i=TRIES; i--; delay(100)) 403 if ((bus_space_read_4(t, h, GEM_RESET) & 404 (GEM_RESET_RX|GEM_RESET_TX)) == 0) 405 break; 406 if ((bus_space_read_4(t, h, GEM_RESET) & 407 (GEM_RESET_RX|GEM_RESET_TX)) != 0) { 408 printf("%s: cannot reset device\n", 409 sc->sc_dev.dv_xname); 410 } 411 splx(s); 412 } 413 414 415 /* 416 * gem_rxdrain: 417 * 418 * Drain the receive queue. 419 */ 420 void 421 gem_rxdrain(struct gem_softc *sc) 422 { 423 struct gem_rxsoft *rxs; 424 int i; 425 426 for (i = 0; i < GEM_NRXDESC; i++) { 427 rxs = &sc->sc_rxsoft[i]; 428 if (rxs->rxs_mbuf != NULL) { 429 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 430 m_freem(rxs->rxs_mbuf); 431 rxs->rxs_mbuf = NULL; 432 } 433 } 434 } 435 436 /* 437 * Reset the whole thing. 438 */ 439 void 440 gem_stop(struct ifnet *ifp, int disable) 441 { 442 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 443 struct gem_txsoft *txs; 444 445 DPRINTF(sc, ("%s: gem_stop\n", sc->sc_dev.dv_xname)); 446 447 callout_stop(&sc->sc_tick_ch); 448 mii_down(&sc->sc_mii); 449 450 /* XXX - Should we reset these instead? */ 451 gem_disable_rx(sc); 452 gem_disable_rx(sc); 453 454 /* 455 * Release any queued transmit buffers. 456 */ 457 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 458 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs, txs_q); 459 if (txs->txs_mbuf != NULL) { 460 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 461 m_freem(txs->txs_mbuf); 462 txs->txs_mbuf = NULL; 463 } 464 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 465 } 466 467 if (disable) { 468 gem_rxdrain(sc); 469 } 470 471 /* 472 * Mark the interface down and cancel the watchdog timer. 473 */ 474 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 475 ifp->if_timer = 0; 476 } 477 478 479 /* 480 * Reset the receiver 481 */ 482 int 483 gem_reset_rx(struct gem_softc *sc) 484 { 485 bus_space_tag_t t = sc->sc_bustag; 486 bus_space_handle_t h = sc->sc_h; 487 int i; 488 489 490 /* 491 * Resetting while DMA is in progress can cause a bus hang, so we 492 * disable DMA first. 493 */ 494 gem_disable_rx(sc); 495 bus_space_write_4(t, h, GEM_RX_CONFIG, 0); 496 /* Wait till it finishes */ 497 for (i=TRIES; i--; delay(100)) 498 if ((bus_space_read_4(t, h, GEM_RX_CONFIG) & 1) == 0) 499 break; 500 if ((bus_space_read_4(t, h, GEM_RX_CONFIG) & 1) != 0) 501 printf("%s: cannot disable read dma\n", 502 sc->sc_dev.dv_xname); 503 504 /* Wait 5ms extra. */ 505 delay(5000); 506 507 /* Finally, reset the ERX */ 508 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX); 509 /* Wait till it finishes */ 510 for (i=TRIES; i--; delay(100)) 511 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_RX) == 0) 512 break; 513 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_RX) != 0) { 514 printf("%s: cannot reset receiver\n", 515 sc->sc_dev.dv_xname); 516 return (1); 517 } 518 return (0); 519 } 520 521 522 /* 523 * Reset the transmitter 524 */ 525 int 526 gem_reset_tx(struct gem_softc *sc) 527 { 528 bus_space_tag_t t = sc->sc_bustag; 529 bus_space_handle_t h = sc->sc_h; 530 int i; 531 532 /* 533 * Resetting while DMA is in progress can cause a bus hang, so we 534 * disable DMA first. 535 */ 536 gem_disable_tx(sc); 537 bus_space_write_4(t, h, GEM_TX_CONFIG, 0); 538 /* Wait till it finishes */ 539 for (i=TRIES; i--; delay(100)) 540 if ((bus_space_read_4(t, h, GEM_TX_CONFIG) & 1) == 0) 541 break; 542 if ((bus_space_read_4(t, h, GEM_TX_CONFIG) & 1) != 0) 543 printf("%s: cannot disable read dma\n", 544 sc->sc_dev.dv_xname); 545 546 /* Wait 5ms extra. */ 547 delay(5000); 548 549 /* Finally, reset the ETX */ 550 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_TX); 551 /* Wait till it finishes */ 552 for (i=TRIES; i--; delay(100)) 553 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_TX) == 0) 554 break; 555 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_TX) != 0) { 556 printf("%s: cannot reset receiver\n", 557 sc->sc_dev.dv_xname); 558 return (1); 559 } 560 return (0); 561 } 562 563 /* 564 * disable receiver. 565 */ 566 int 567 gem_disable_rx(struct gem_softc *sc) 568 { 569 bus_space_tag_t t = sc->sc_bustag; 570 bus_space_handle_t h = sc->sc_h; 571 int i; 572 u_int32_t cfg; 573 574 /* Flip the enable bit */ 575 cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 576 cfg &= ~GEM_MAC_RX_ENABLE; 577 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg); 578 579 /* Wait for it to finish */ 580 for (i=TRIES; i--; delay(100)) 581 if ((bus_space_read_4(t, h, GEM_MAC_RX_CONFIG) & 582 GEM_MAC_RX_ENABLE) == 0) 583 return (0); 584 return (1); 585 } 586 587 /* 588 * disable transmitter. 589 */ 590 int 591 gem_disable_tx(struct gem_softc *sc) 592 { 593 bus_space_tag_t t = sc->sc_bustag; 594 bus_space_handle_t h = sc->sc_h; 595 int i; 596 u_int32_t cfg; 597 598 /* Flip the enable bit */ 599 cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG); 600 cfg &= ~GEM_MAC_TX_ENABLE; 601 bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg); 602 603 /* Wait for it to finish */ 604 for (i=TRIES; i--; delay(100)) 605 if ((bus_space_read_4(t, h, GEM_MAC_TX_CONFIG) & 606 GEM_MAC_TX_ENABLE) == 0) 607 return (0); 608 return (1); 609 } 610 611 /* 612 * Initialize interface. 613 */ 614 int 615 gem_meminit(struct gem_softc *sc) 616 { 617 struct gem_rxsoft *rxs; 618 int i, error; 619 620 /* 621 * Initialize the transmit descriptor ring. 622 */ 623 memset((void *)sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 624 for (i = 0; i < GEM_NTXDESC; i++) { 625 sc->sc_txdescs[i].gd_flags = 0; 626 sc->sc_txdescs[i].gd_addr = 0; 627 } 628 GEM_CDTXSYNC(sc, 0, GEM_NTXDESC, 629 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 630 sc->sc_txfree = GEM_NTXDESC; 631 sc->sc_txnext = 0; 632 633 /* 634 * Initialize the receive descriptor and receive job 635 * descriptor rings. 636 */ 637 for (i = 0; i < GEM_NRXDESC; i++) { 638 rxs = &sc->sc_rxsoft[i]; 639 if (rxs->rxs_mbuf == NULL) { 640 if ((error = gem_add_rxbuf(sc, i)) != 0) { 641 printf("%s: unable to allocate or map rx " 642 "buffer %d, error = %d\n", 643 sc->sc_dev.dv_xname, i, error); 644 /* 645 * XXX Should attempt to run with fewer receive 646 * XXX buffers instead of just failing. 647 */ 648 gem_rxdrain(sc); 649 return (1); 650 } 651 } else 652 GEM_INIT_RXDESC(sc, i); 653 } 654 sc->sc_rxptr = 0; 655 656 return (0); 657 } 658 659 static int 660 gem_ringsize(int sz) 661 { 662 int v; 663 664 switch (sz) { 665 case 32: 666 v = GEM_RING_SZ_32; 667 break; 668 case 64: 669 v = GEM_RING_SZ_64; 670 break; 671 case 128: 672 v = GEM_RING_SZ_128; 673 break; 674 case 256: 675 v = GEM_RING_SZ_256; 676 break; 677 case 512: 678 v = GEM_RING_SZ_512; 679 break; 680 case 1024: 681 v = GEM_RING_SZ_1024; 682 break; 683 case 2048: 684 v = GEM_RING_SZ_2048; 685 break; 686 case 4096: 687 v = GEM_RING_SZ_4096; 688 break; 689 case 8192: 690 v = GEM_RING_SZ_8192; 691 break; 692 default: 693 printf("gem: invalid Receive Descriptor ring size\n"); 694 break; 695 } 696 return (v); 697 } 698 699 /* 700 * Initialization of interface; set up initialization block 701 * and transmit/receive descriptor rings. 702 */ 703 int 704 gem_init(struct ifnet *ifp) 705 { 706 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 707 bus_space_tag_t t = sc->sc_bustag; 708 bus_space_handle_t h = sc->sc_h; 709 int s; 710 u_int32_t v; 711 712 s = splnet(); 713 714 DPRINTF(sc, ("%s: gem_init: calling stop\n", sc->sc_dev.dv_xname)); 715 /* 716 * Initialization sequence. The numbered steps below correspond 717 * to the sequence outlined in section 6.3.5.1 in the Ethernet 718 * Channel Engine manual (part of the PCIO manual). 719 * See also the STP2002-STQ document from Sun Microsystems. 720 */ 721 722 /* step 1 & 2. Reset the Ethernet Channel */ 723 gem_stop(ifp, 0); 724 gem_reset(sc); 725 DPRINTF(sc, ("%s: gem_init: restarting\n", sc->sc_dev.dv_xname)); 726 727 /* Re-initialize the MIF */ 728 gem_mifinit(sc); 729 730 /* Call MI reset function if any */ 731 if (sc->sc_hwreset) 732 (*sc->sc_hwreset)(sc); 733 734 /* step 3. Setup data structures in host memory */ 735 gem_meminit(sc); 736 737 /* step 4. TX MAC registers & counters */ 738 gem_init_regs(sc); 739 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 740 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 741 ETHER_VLAN_ENCAP_LEN + ETHER_MAX_LEN + sizeof(struct ether_header): 742 ETHER_MAX_LEN + sizeof(struct ether_header)) | (0x2000<<16)); 743 744 /* step 5. RX MAC registers & counters */ 745 gem_setladrf(sc); 746 747 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 748 /* NOTE: we use only 32-bit DMA addresses here. */ 749 bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 0); 750 bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 751 752 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0); 753 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 754 755 /* step 8. Global Configuration & Interrupt Mask */ 756 bus_space_write_4(t, h, GEM_INTMASK, 757 ~(GEM_INTR_TX_INTME| 758 GEM_INTR_TX_EMPTY| 759 GEM_INTR_RX_DONE|GEM_INTR_RX_NOBUF| 760 GEM_INTR_RX_TAG_ERR|GEM_INTR_PCS| 761 GEM_INTR_MAC_CONTROL|GEM_INTR_MIF| 762 GEM_INTR_BERR)); 763 bus_space_write_4(t, h, GEM_MAC_RX_MASK, 0); /* XXXX */ 764 bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXXX */ 765 bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 0); /* XXXX */ 766 767 /* step 9. ETX Configuration: use mostly default values */ 768 769 /* Enable DMA */ 770 v = gem_ringsize(GEM_NTXDESC /*XXX*/); 771 bus_space_write_4(t, h, GEM_TX_CONFIG, 772 v|GEM_TX_CONFIG_TXDMA_EN| 773 ((0x400<<10)&GEM_TX_CONFIG_TXFIFO_TH)); 774 bus_space_write_4(t, h, GEM_TX_KICK, sc->sc_txnext); 775 776 /* step 10. ERX Configuration */ 777 778 /* Encode Receive Descriptor ring size: four possible values */ 779 v = gem_ringsize(GEM_NRXDESC /*XXX*/); 780 781 /* Enable DMA */ 782 bus_space_write_4(t, h, GEM_RX_CONFIG, 783 v|(GEM_THRSH_1024<<GEM_RX_CONFIG_FIFO_THRS_SHIFT)| 784 (2<<GEM_RX_CONFIG_FBOFF_SHFT)|GEM_RX_CONFIG_RXDMA_EN| 785 (0<<GEM_RX_CONFIG_CXM_START_SHFT)); 786 /* 787 * The following value is for an OFF Threshold of about 15.5 Kbytes 788 * and an ON Threshold of 4K bytes. 789 */ 790 bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH, 0xf8 | (0x40 << 12)); 791 bus_space_write_4(t, h, GEM_RX_BLANKING, (2<<12)|6); 792 793 /* step 11. Configure Media */ 794 gem_mii_statchg(&sc->sc_dev); 795 796 /* XXXX Serial link needs a whole different setup. */ 797 798 799 /* step 12. RX_MAC Configuration Register */ 800 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 801 v |= GEM_MAC_RX_ENABLE; 802 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 803 804 /* step 14. Issue Transmit Pending command */ 805 806 /* Call MI initialization function if any */ 807 if (sc->sc_hwinit) 808 (*sc->sc_hwinit)(sc); 809 810 811 /* step 15. Give the reciever a swift kick */ 812 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4); 813 814 /* Start the one second timer. */ 815 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 816 817 ifp->if_flags |= IFF_RUNNING; 818 ifp->if_flags &= ~IFF_OACTIVE; 819 ifp->if_timer = 0; 820 splx(s); 821 822 return (0); 823 } 824 825 void 826 gem_init_regs(struct gem_softc *sc) 827 { 828 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 829 bus_space_tag_t t = sc->sc_bustag; 830 bus_space_handle_t h = sc->sc_h; 831 832 /* These regs are not cleared on reset */ 833 sc->sc_inited = 0; 834 if (!sc->sc_inited) { 835 836 /* Wooo. Magic values. */ 837 bus_space_write_4(t, h, GEM_MAC_IPG0, 0); 838 bus_space_write_4(t, h, GEM_MAC_IPG1, 8); 839 bus_space_write_4(t, h, GEM_MAC_IPG2, 4); 840 841 bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 842 /* Max frame and max burst size */ 843 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 844 (ifp->if_mtu+18) | (0x2000<<16)/* Burst size */); 845 bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x7); 846 bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x4); 847 bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10); 848 /* Dunno.... */ 849 bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088); 850 bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED, 851 ((LLADDR(ifp->if_sadl)[5]<<8)| 852 LLADDR(ifp->if_sadl)[4])&0x3ff); 853 /* Secondary MAC addr set to 0:0:0:0:0:0 */ 854 bus_space_write_4(t, h, GEM_MAC_ADDR3, 0); 855 bus_space_write_4(t, h, GEM_MAC_ADDR4, 0); 856 bus_space_write_4(t, h, GEM_MAC_ADDR5, 0); 857 /* MAC control addr set to 0:1:c2:0:1:80 */ 858 bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001); 859 bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200); 860 bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180); 861 862 /* MAC filter addr set to 0:0:0:0:0:0 */ 863 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0); 864 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0); 865 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0); 866 867 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0); 868 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0); 869 870 sc->sc_inited = 1; 871 } 872 873 /* Counters need to be zeroed */ 874 bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0); 875 bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0); 876 bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0); 877 bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0); 878 bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0); 879 bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0); 880 bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0); 881 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 882 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 883 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 884 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 885 886 /* Un-pause stuff */ 887 #if 0 888 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); 889 #else 890 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0); 891 #endif 892 893 /* 894 * Set the station address. 895 */ 896 bus_space_write_4(t, h, GEM_MAC_ADDR0, 897 (LLADDR(ifp->if_sadl)[4]<<8) | LLADDR(ifp->if_sadl)[5]); 898 bus_space_write_4(t, h, GEM_MAC_ADDR1, 899 (LLADDR(ifp->if_sadl)[2]<<8) | LLADDR(ifp->if_sadl)[3]); 900 bus_space_write_4(t, h, GEM_MAC_ADDR2, 901 (LLADDR(ifp->if_sadl)[0]<<8) | LLADDR(ifp->if_sadl)[1]); 902 903 } 904 905 906 907 void 908 gem_start(ifp) 909 struct ifnet *ifp; 910 { 911 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 912 struct mbuf *m0, *m; 913 struct gem_txsoft *txs, *last_txs; 914 bus_dmamap_t dmamap; 915 int error, firsttx, nexttx, lasttx, ofree, seg; 916 917 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 918 return; 919 920 /* 921 * Remember the previous number of free descriptors and 922 * the first descriptor we'll use. 923 */ 924 ofree = sc->sc_txfree; 925 firsttx = sc->sc_txnext; 926 927 DPRINTF(sc, ("%s: gem_start: txfree %d, txnext %d\n", 928 sc->sc_dev.dv_xname, ofree, firsttx)); 929 930 /* 931 * Loop through the send queue, setting up transmit descriptors 932 * until we drain the queue, or use up all available transmit 933 * descriptors. 934 */ 935 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 936 sc->sc_txfree != 0) { 937 /* 938 * Grab a packet off the queue. 939 */ 940 IFQ_POLL(&ifp->if_snd, m0); 941 if (m0 == NULL) 942 break; 943 m = NULL; 944 945 dmamap = txs->txs_dmamap; 946 947 /* 948 * Load the DMA map. If this fails, the packet either 949 * didn't fit in the alloted number of segments, or we were 950 * short on resources. In this case, we'll copy and try 951 * again. 952 */ 953 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m0, 954 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 955 MGETHDR(m, M_DONTWAIT, MT_DATA); 956 if (m == NULL) { 957 printf("%s: unable to allocate Tx mbuf\n", 958 sc->sc_dev.dv_xname); 959 break; 960 } 961 if (m0->m_pkthdr.len > MHLEN) { 962 MCLGET(m, M_DONTWAIT); 963 if ((m->m_flags & M_EXT) == 0) { 964 printf("%s: unable to allocate Tx " 965 "cluster\n", sc->sc_dev.dv_xname); 966 m_freem(m); 967 break; 968 } 969 } 970 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 971 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 972 error = bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, 973 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 974 if (error) { 975 printf("%s: unable to load Tx buffer, " 976 "error = %d\n", sc->sc_dev.dv_xname, error); 977 break; 978 } 979 } 980 981 /* 982 * Ensure we have enough descriptors free to describe 983 * the packet. 984 */ 985 if (dmamap->dm_nsegs > sc->sc_txfree) { 986 /* 987 * Not enough free descriptors to transmit this 988 * packet. We haven't committed to anything yet, 989 * so just unload the DMA map, put the packet 990 * back on the queue, and punt. Notify the upper 991 * layer that there are no more slots left. 992 * 993 * XXX We could allocate an mbuf and copy, but 994 * XXX it is worth it? 995 */ 996 ifp->if_flags |= IFF_OACTIVE; 997 bus_dmamap_unload(sc->sc_dmatag, dmamap); 998 if (m != NULL) 999 m_freem(m); 1000 break; 1001 } 1002 1003 IFQ_DEQUEUE(&ifp->if_snd, m0); 1004 if (m != NULL) { 1005 m_freem(m0); 1006 m0 = m; 1007 } 1008 1009 /* 1010 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1011 */ 1012 1013 /* Sync the DMA map. */ 1014 bus_dmamap_sync(sc->sc_dmatag, dmamap, 0, dmamap->dm_mapsize, 1015 BUS_DMASYNC_PREWRITE); 1016 1017 /* 1018 * Initialize the transmit descriptors. 1019 */ 1020 for (nexttx = sc->sc_txnext, seg = 0; 1021 seg < dmamap->dm_nsegs; 1022 seg++, nexttx = GEM_NEXTTX(nexttx)) { 1023 uint64_t flags; 1024 1025 /* 1026 * If this is the first descriptor we're 1027 * enqueueing, set the start of packet flag, 1028 * and the checksum stuff if we want the hardware 1029 * to do it. 1030 */ 1031 sc->sc_txdescs[nexttx].gd_addr = 1032 GEM_DMA_WRITE(sc, dmamap->dm_segs[seg].ds_addr); 1033 flags = dmamap->dm_segs[seg].ds_len & GEM_TD_BUFSIZE; 1034 if (nexttx == firsttx) { 1035 flags |= GEM_TD_START_OF_PACKET; 1036 } 1037 if (seg == dmamap->dm_nsegs - 1) { 1038 flags |= GEM_TD_END_OF_PACKET; 1039 } 1040 sc->sc_txdescs[nexttx].gd_flags = 1041 GEM_DMA_WRITE(sc, flags); 1042 lasttx = nexttx; 1043 } 1044 1045 #ifdef GEM_DEBUG 1046 if (ifp->if_flags & IFF_DEBUG) { 1047 printf(" gem_start %p transmit chain:\n", txs); 1048 for (seg = sc->sc_txnext;; seg = GEM_NEXTTX(seg)) { 1049 printf("descriptor %d:\t", seg); 1050 printf("gd_flags: 0x%016llx\t", (long long) 1051 GEM_DMA_READ(sc, sc->sc_txdescs[seg].gd_flags)); 1052 printf("gd_addr: 0x%016llx\n", (long long) 1053 GEM_DMA_READ(sc, sc->sc_txdescs[seg].gd_addr)); 1054 if (seg == lasttx) 1055 break; 1056 } 1057 } 1058 #endif 1059 1060 /* Sync the descriptors we're using. */ 1061 GEM_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs, 1062 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1063 1064 /* 1065 * Store a pointer to the packet so we can free it later, 1066 * and remember what txdirty will be once the packet is 1067 * done. 1068 */ 1069 txs->txs_mbuf = m0; 1070 txs->txs_firstdesc = sc->sc_txnext; 1071 txs->txs_lastdesc = lasttx; 1072 txs->txs_ndescs = dmamap->dm_nsegs; 1073 1074 /* Advance the tx pointer. */ 1075 sc->sc_txfree -= dmamap->dm_nsegs; 1076 sc->sc_txnext = nexttx; 1077 1078 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs, txs_q); 1079 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1080 1081 last_txs = txs; 1082 1083 #if NBPFILTER > 0 1084 /* 1085 * Pass the packet to any BPF listeners. 1086 */ 1087 if (ifp->if_bpf) 1088 bpf_mtap(ifp->if_bpf, m0); 1089 #endif /* NBPFILTER > 0 */ 1090 } 1091 1092 if (txs == NULL || sc->sc_txfree == 0) { 1093 /* No more slots left; notify upper layer. */ 1094 ifp->if_flags |= IFF_OACTIVE; 1095 } 1096 1097 if (sc->sc_txfree != ofree) { 1098 DPRINTF(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 1099 sc->sc_dev.dv_xname, lasttx, firsttx)); 1100 /* 1101 * The entire packet chain is set up. 1102 * Kick the transmitter. 1103 */ 1104 DPRINTF(sc, ("%s: gem_start: kicking tx %d\n", 1105 sc->sc_dev.dv_xname, nexttx)); 1106 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_TX_KICK, 1107 sc->sc_txnext); 1108 1109 /* Set a watchdog timer in case the chip flakes out. */ 1110 ifp->if_timer = 5; 1111 DPRINTF(sc, ("%s: gem_start: watchdog %d\n", 1112 sc->sc_dev.dv_xname, ifp->if_timer)); 1113 } 1114 } 1115 1116 /* 1117 * Transmit interrupt. 1118 */ 1119 int 1120 gem_tint(sc) 1121 struct gem_softc *sc; 1122 { 1123 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1124 bus_space_tag_t t = sc->sc_bustag; 1125 bus_space_handle_t mac = sc->sc_h; 1126 struct gem_txsoft *txs; 1127 int txlast; 1128 1129 1130 DPRINTF(sc, ("%s: gem_tint\n", sc->sc_dev.dv_xname)); 1131 1132 /* 1133 * Unload collision counters 1134 */ 1135 ifp->if_collisions += 1136 bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) + 1137 bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT) + 1138 bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) + 1139 bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT); 1140 1141 /* 1142 * then clear the hardware counters. 1143 */ 1144 bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0); 1145 bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0); 1146 bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0); 1147 bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0); 1148 1149 /* 1150 * Go through our Tx list and free mbufs for those 1151 * frames that have been transmitted. 1152 */ 1153 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1154 GEM_CDTXSYNC(sc, txs->txs_lastdesc, 1155 txs->txs_ndescs, 1156 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1157 1158 #ifdef GEM_DEBUG 1159 if (ifp->if_flags & IFF_DEBUG) { 1160 int i; 1161 printf(" txsoft %p transmit chain:\n", txs); 1162 for (i = txs->txs_firstdesc;; i = GEM_NEXTTX(i)) { 1163 printf("descriptor %d: ", i); 1164 printf("gd_flags: 0x%016llx\t", (long long) 1165 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags)); 1166 printf("gd_addr: 0x%016llx\n", (long long) 1167 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr)); 1168 if (i == txs->txs_lastdesc) 1169 break; 1170 } 1171 } 1172 #endif 1173 1174 /* 1175 * In theory, we could harveast some descriptors before 1176 * the ring is empty, but that's a bit complicated. 1177 * 1178 * GEM_TX_COMPLETION points to the last descriptor 1179 * processed +1. 1180 */ 1181 txlast = bus_space_read_4(t, mac, GEM_TX_COMPLETION); 1182 DPRINTF(sc, 1183 ("gem_tint: txs->txs_lastdesc = %d, txlast = %d\n", 1184 txs->txs_lastdesc, txlast)); 1185 if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1186 if ((txlast >= txs->txs_firstdesc) && 1187 (txlast <= txs->txs_lastdesc)) 1188 break; 1189 } else { 1190 /* Ick -- this command wraps */ 1191 if ((txlast >= txs->txs_firstdesc) || 1192 (txlast <= txs->txs_lastdesc)) 1193 break; 1194 } 1195 1196 DPRINTF(sc, ("gem_tint: releasing a desc\n")); 1197 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs, txs_q); 1198 1199 sc->sc_txfree += txs->txs_ndescs; 1200 1201 if (txs->txs_mbuf == NULL) { 1202 #ifdef DIAGNOSTIC 1203 panic("gem_txintr: null mbuf"); 1204 #endif 1205 } 1206 1207 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 1208 0, txs->txs_dmamap->dm_mapsize, 1209 BUS_DMASYNC_POSTWRITE); 1210 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 1211 m_freem(txs->txs_mbuf); 1212 txs->txs_mbuf = NULL; 1213 1214 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1215 1216 ifp->if_opackets++; 1217 } 1218 1219 DPRINTF(sc, ("gem_tint: GEM_TX_STATE_MACHINE %x " 1220 "GEM_TX_DATA_PTR %llx " 1221 "GEM_TX_COMPLETION %x\n", 1222 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_STATE_MACHINE), 1223 ((long long) bus_space_read_4(sc->sc_bustag, sc->sc_h, 1224 GEM_TX_DATA_PTR_HI) << 32) | 1225 bus_space_read_4(sc->sc_bustag, sc->sc_h, 1226 GEM_TX_DATA_PTR_LO), 1227 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_COMPLETION))); 1228 1229 gem_start(ifp); 1230 1231 if (SIMPLEQ_FIRST(&sc->sc_txdirtyq) == NULL) 1232 ifp->if_timer = 0; 1233 DPRINTF(sc, ("%s: gem_tint: watchdog %d\n", 1234 sc->sc_dev.dv_xname, ifp->if_timer)); 1235 1236 return (1); 1237 } 1238 1239 /* 1240 * Receive interrupt. 1241 */ 1242 int 1243 gem_rint(sc) 1244 struct gem_softc *sc; 1245 { 1246 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1247 bus_space_tag_t t = sc->sc_bustag; 1248 bus_space_handle_t h = sc->sc_h; 1249 struct ether_header *eh; 1250 struct gem_rxsoft *rxs; 1251 struct mbuf *m; 1252 u_int64_t rxstat; 1253 int i, len; 1254 1255 DPRINTF(sc, ("%s: gem_rint\n", sc->sc_dev.dv_xname)); 1256 /* 1257 * XXXX Read the lastrx only once at the top for speed. 1258 */ 1259 DPRINTF(sc, ("gem_rint: sc->rxptr %d, complete %d\n", 1260 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION))); 1261 for (i = sc->sc_rxptr; i != bus_space_read_4(t, h, GEM_RX_COMPLETION); 1262 i = GEM_NEXTRX(i)) { 1263 rxs = &sc->sc_rxsoft[i]; 1264 1265 GEM_CDRXSYNC(sc, i, 1266 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1267 1268 rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags); 1269 1270 if (rxstat & GEM_RD_OWN) { 1271 printf("gem_rint: completed descriptor " 1272 "still owned %d\n", i); 1273 /* 1274 * We have processed all of the receive buffers. 1275 */ 1276 break; 1277 } 1278 1279 if (rxstat & GEM_RD_BAD_CRC) { 1280 printf("%s: receive error: CRC error\n", 1281 sc->sc_dev.dv_xname); 1282 GEM_INIT_RXDESC(sc, i); 1283 continue; 1284 } 1285 1286 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1287 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1288 #ifdef GEM_DEBUG 1289 if (ifp->if_flags & IFF_DEBUG) { 1290 printf(" rxsoft %p descriptor %d: ", rxs, i); 1291 printf("gd_flags: 0x%016llx\t", (long long) 1292 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags)); 1293 printf("gd_addr: 0x%016llx\n", (long long) 1294 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr)); 1295 } 1296 #endif 1297 1298 /* 1299 * No errors; receive the packet. Note the Gem 1300 * includes the CRC with every packet. 1301 */ 1302 len = GEM_RD_BUFLEN(rxstat); 1303 1304 /* 1305 * Allocate a new mbuf cluster. If that fails, we are 1306 * out of memory, and must drop the packet and recycle 1307 * the buffer that's already attached to this descriptor. 1308 */ 1309 m = rxs->rxs_mbuf; 1310 if (gem_add_rxbuf(sc, i) != 0) { 1311 ifp->if_ierrors++; 1312 GEM_INIT_RXDESC(sc, i); 1313 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1314 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1315 continue; 1316 } 1317 m->m_data += 2; /* We're already off by two */ 1318 1319 ifp->if_ipackets++; 1320 eh = mtod(m, struct ether_header *); 1321 m->m_flags |= M_HASFCS; 1322 m->m_pkthdr.rcvif = ifp; 1323 m->m_pkthdr.len = m->m_len = len; 1324 1325 #if NBPFILTER > 0 1326 /* 1327 * Pass this up to any BPF listeners, but only 1328 * pass it up the stack if its for us. 1329 */ 1330 if (ifp->if_bpf) 1331 bpf_mtap(ifp->if_bpf, m); 1332 #endif /* NPBFILTER > 0 */ 1333 1334 #if 0 1335 /* 1336 * We sometimes have to run the 21140 in Hash-Only 1337 * mode. If we're in that mode, and not in promiscuous 1338 * mode, and we have a unicast packet that isn't for 1339 * us, then drop it. 1340 */ 1341 if (sc->sc_filtmode == TDCTL_Tx_FT_HASHONLY && 1342 (ifp->if_flags & IFF_PROMISC) == 0 && 1343 ETHER_IS_MULTICAST(eh->ether_dhost) == 0 && 1344 memcmp(LLADDR(ifp->if_sadl), eh->ether_dhost, 1345 ETHER_ADDR_LEN) != 0) { 1346 m_freem(m); 1347 continue; 1348 } 1349 #endif 1350 1351 /* Pass it on. */ 1352 (*ifp->if_input)(ifp, m); 1353 } 1354 1355 /* Update the receive pointer. */ 1356 sc->sc_rxptr = i; 1357 bus_space_write_4(t, h, GEM_RX_KICK, i); 1358 1359 DPRINTF(sc, ("gem_rint: done sc->rxptr %d, complete %d\n", 1360 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION))); 1361 1362 return (1); 1363 } 1364 1365 1366 /* 1367 * gem_add_rxbuf: 1368 * 1369 * Add a receive buffer to the indicated descriptor. 1370 */ 1371 int 1372 gem_add_rxbuf(struct gem_softc *sc, int idx) 1373 { 1374 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1375 struct mbuf *m; 1376 int error; 1377 1378 MGETHDR(m, M_DONTWAIT, MT_DATA); 1379 if (m == NULL) 1380 return (ENOBUFS); 1381 1382 MCLGET(m, M_DONTWAIT); 1383 if ((m->m_flags & M_EXT) == 0) { 1384 m_freem(m); 1385 return (ENOBUFS); 1386 } 1387 1388 #ifdef GEM_DEBUG 1389 /* bzero the packet to check dma */ 1390 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 1391 #endif 1392 1393 if (rxs->rxs_mbuf != NULL) 1394 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 1395 1396 rxs->rxs_mbuf = m; 1397 1398 error = bus_dmamap_load(sc->sc_dmatag, rxs->rxs_dmamap, 1399 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1400 BUS_DMA_READ|BUS_DMA_NOWAIT); 1401 if (error) { 1402 printf("%s: can't load rx DMA map %d, error = %d\n", 1403 sc->sc_dev.dv_xname, idx, error); 1404 panic("gem_add_rxbuf"); /* XXX */ 1405 } 1406 1407 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1408 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1409 1410 GEM_INIT_RXDESC(sc, idx); 1411 1412 return (0); 1413 } 1414 1415 1416 int 1417 gem_eint(sc, status) 1418 struct gem_softc *sc; 1419 u_int status; 1420 { 1421 char bits[128]; 1422 1423 if ((status & GEM_INTR_MIF) != 0) { 1424 printf("%s: XXXlink status changed\n", sc->sc_dev.dv_xname); 1425 return (1); 1426 } 1427 1428 printf("%s: status=%s\n", sc->sc_dev.dv_xname, 1429 bitmask_snprintf(status, GEM_INTR_BITS, bits, sizeof(bits))); 1430 return (1); 1431 } 1432 1433 1434 int 1435 gem_intr(v) 1436 void *v; 1437 { 1438 struct gem_softc *sc = (struct gem_softc *)v; 1439 bus_space_tag_t t = sc->sc_bustag; 1440 bus_space_handle_t seb = sc->sc_h; 1441 u_int32_t status; 1442 int r = 0; 1443 #ifdef GEM_DEBUG 1444 char bits[128]; 1445 #endif 1446 1447 status = bus_space_read_4(t, seb, GEM_STATUS); 1448 DPRINTF(sc, ("%s: gem_intr: cplt %xstatus %s\n", 1449 sc->sc_dev.dv_xname, (status>>19), 1450 bitmask_snprintf(status, GEM_INTR_BITS, bits, sizeof(bits)))); 1451 1452 if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0) 1453 r |= gem_eint(sc, status); 1454 1455 if ((status & 1456 (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) 1457 != 0) 1458 r |= gem_tint(sc); 1459 1460 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) 1461 r |= gem_rint(sc); 1462 1463 /* We should eventually do more than just print out error stats. */ 1464 if (status & GEM_INTR_TX_MAC) { 1465 int txstat = bus_space_read_4(t, seb, GEM_MAC_TX_STATUS); 1466 if (txstat & ~GEM_MAC_TX_XMIT_DONE) 1467 printf("MAC tx fault, status %x\n", txstat); 1468 } 1469 if (status & GEM_INTR_RX_MAC) { 1470 int rxstat = bus_space_read_4(t, seb, GEM_MAC_RX_STATUS); 1471 if (rxstat & ~GEM_MAC_RX_DONE) 1472 printf("MAC rx fault, status %x\n", rxstat); 1473 } 1474 return (r); 1475 } 1476 1477 1478 void 1479 gem_watchdog(ifp) 1480 struct ifnet *ifp; 1481 { 1482 struct gem_softc *sc = ifp->if_softc; 1483 1484 DPRINTF(sc, ("gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x " 1485 "GEM_MAC_RX_CONFIG %x\n", 1486 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_CONFIG), 1487 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_STATUS), 1488 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_CONFIG))); 1489 1490 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1491 ++ifp->if_oerrors; 1492 1493 /* Try to get more packets going. */ 1494 gem_start(ifp); 1495 } 1496 1497 /* 1498 * Initialize the MII Management Interface 1499 */ 1500 void 1501 gem_mifinit(sc) 1502 struct gem_softc *sc; 1503 { 1504 bus_space_tag_t t = sc->sc_bustag; 1505 bus_space_handle_t mif = sc->sc_h; 1506 1507 /* Configure the MIF in frame mode */ 1508 sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1509 sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA; 1510 bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config); 1511 } 1512 1513 /* 1514 * MII interface 1515 * 1516 * The GEM MII interface supports at least three different operating modes: 1517 * 1518 * Bitbang mode is implemented using data, clock and output enable registers. 1519 * 1520 * Frame mode is implemented by loading a complete frame into the frame 1521 * register and polling the valid bit for completion. 1522 * 1523 * Polling mode uses the frame register but completion is indicated by 1524 * an interrupt. 1525 * 1526 */ 1527 static int 1528 gem_mii_readreg(self, phy, reg) 1529 struct device *self; 1530 int phy, reg; 1531 { 1532 struct gem_softc *sc = (void *)self; 1533 bus_space_tag_t t = sc->sc_bustag; 1534 bus_space_handle_t mif = sc->sc_h; 1535 int n; 1536 u_int32_t v; 1537 1538 #ifdef GEM_DEBUG1 1539 if (sc->sc_debug) 1540 printf("gem_mii_readreg: phy %d reg %d\n", phy, reg); 1541 #endif 1542 1543 #if 0 1544 /* Select the desired PHY in the MIF configuration register */ 1545 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1546 /* Clear PHY select bit */ 1547 v &= ~GEM_MIF_CONFIG_PHY_SEL; 1548 if (phy == GEM_PHYAD_EXTERNAL) 1549 /* Set PHY select bit to get at external device */ 1550 v |= GEM_MIF_CONFIG_PHY_SEL; 1551 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 1552 #endif 1553 1554 /* Construct the frame command */ 1555 v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) | 1556 GEM_MIF_FRAME_READ; 1557 1558 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1559 for (n = 0; n < 100; n++) { 1560 DELAY(1); 1561 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1562 if (v & GEM_MIF_FRAME_TA0) 1563 return (v & GEM_MIF_FRAME_DATA); 1564 } 1565 1566 printf("%s: mii_read timeout\n", sc->sc_dev.dv_xname); 1567 return (0); 1568 } 1569 1570 static void 1571 gem_mii_writereg(self, phy, reg, val) 1572 struct device *self; 1573 int phy, reg, val; 1574 { 1575 struct gem_softc *sc = (void *)self; 1576 bus_space_tag_t t = sc->sc_bustag; 1577 bus_space_handle_t mif = sc->sc_h; 1578 int n; 1579 u_int32_t v; 1580 1581 #ifdef GEM_DEBUG1 1582 if (sc->sc_debug) 1583 printf("gem_mii_writereg: phy %d reg %d val %x\n", 1584 phy, reg, val); 1585 #endif 1586 1587 #if 0 1588 /* Select the desired PHY in the MIF configuration register */ 1589 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 1590 /* Clear PHY select bit */ 1591 v &= ~GEM_MIF_CONFIG_PHY_SEL; 1592 if (phy == GEM_PHYAD_EXTERNAL) 1593 /* Set PHY select bit to get at external device */ 1594 v |= GEM_MIF_CONFIG_PHY_SEL; 1595 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v); 1596 #endif 1597 /* Construct the frame command */ 1598 v = GEM_MIF_FRAME_WRITE | 1599 (phy << GEM_MIF_PHY_SHIFT) | 1600 (reg << GEM_MIF_REG_SHIFT) | 1601 (val & GEM_MIF_FRAME_DATA); 1602 1603 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 1604 for (n = 0; n < 100; n++) { 1605 DELAY(1); 1606 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 1607 if (v & GEM_MIF_FRAME_TA0) 1608 return; 1609 } 1610 1611 printf("%s: mii_write timeout\n", sc->sc_dev.dv_xname); 1612 } 1613 1614 static void 1615 gem_mii_statchg(dev) 1616 struct device *dev; 1617 { 1618 struct gem_softc *sc = (void *)dev; 1619 #ifdef GEM_DEBUG 1620 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1621 #endif 1622 bus_space_tag_t t = sc->sc_bustag; 1623 bus_space_handle_t mac = sc->sc_h; 1624 u_int32_t v; 1625 1626 #ifdef GEM_DEBUG 1627 if (sc->sc_debug) 1628 printf("gem_mii_statchg: status change: phy = %d\n", 1629 sc->sc_phys[instance];); 1630 #endif 1631 1632 1633 /* Set tx full duplex options */ 1634 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0); 1635 delay(10000); /* reg must be cleared and delay before changing. */ 1636 v = GEM_MAC_TX_ENA_IPG0|GEM_MAC_TX_NGU|GEM_MAC_TX_NGU_LIMIT| 1637 GEM_MAC_TX_ENABLE; 1638 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) { 1639 v |= GEM_MAC_TX_IGN_CARRIER|GEM_MAC_TX_IGN_COLLIS; 1640 } 1641 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, v); 1642 1643 /* XIF Configuration */ 1644 /* We should really calculate all this rather than rely on defaults */ 1645 v = bus_space_read_4(t, mac, GEM_MAC_XIF_CONFIG); 1646 v = GEM_MAC_XIF_LINK_LED; 1647 v |= GEM_MAC_XIF_TX_MII_ENA; 1648 /* If an external transceiver is connected, enable its MII drivers */ 1649 sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG); 1650 if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) { 1651 /* External MII needs echo disable if half duplex. */ 1652 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 1653 /* turn on full duplex LED */ 1654 v |= GEM_MAC_XIF_FDPLX_LED; 1655 else 1656 /* half duplex -- disable echo */ 1657 v |= GEM_MAC_XIF_ECHO_DISABL; 1658 } else 1659 /* Internal MII needs buf enable */ 1660 v |= GEM_MAC_XIF_MII_BUF_ENA; 1661 bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v); 1662 } 1663 1664 int 1665 gem_mediachange(ifp) 1666 struct ifnet *ifp; 1667 { 1668 struct gem_softc *sc = ifp->if_softc; 1669 1670 if (IFM_TYPE(sc->sc_media.ifm_media) != IFM_ETHER) 1671 return (EINVAL); 1672 1673 return (mii_mediachg(&sc->sc_mii)); 1674 } 1675 1676 void 1677 gem_mediastatus(ifp, ifmr) 1678 struct ifnet *ifp; 1679 struct ifmediareq *ifmr; 1680 { 1681 struct gem_softc *sc = ifp->if_softc; 1682 1683 if ((ifp->if_flags & IFF_UP) == 0) 1684 return; 1685 1686 mii_pollstat(&sc->sc_mii); 1687 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1688 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1689 } 1690 1691 int gem_ioctldebug = 0; 1692 /* 1693 * Process an ioctl request. 1694 */ 1695 int 1696 gem_ioctl(ifp, cmd, data) 1697 struct ifnet *ifp; 1698 u_long cmd; 1699 caddr_t data; 1700 { 1701 struct gem_softc *sc = ifp->if_softc; 1702 struct ifreq *ifr = (struct ifreq *)data; 1703 int s, error = 0; 1704 1705 1706 switch (cmd) { 1707 case SIOCGIFMEDIA: 1708 case SIOCSIFMEDIA: 1709 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1710 break; 1711 1712 default: 1713 error = ether_ioctl(ifp, cmd, data); 1714 if (error == ENETRESET) { 1715 /* 1716 * Multicast list has changed; set the hardware filter 1717 * accordingly. 1718 */ 1719 if (gem_ioctldebug) printf("reset1\n"); 1720 gem_init(ifp); 1721 delay(50000); 1722 error = 0; 1723 } 1724 break; 1725 } 1726 1727 /* Try to get things going again */ 1728 if (ifp->if_flags & IFF_UP) { 1729 if (gem_ioctldebug) printf("start\n"); 1730 gem_start(ifp); 1731 } 1732 splx(s); 1733 return (error); 1734 } 1735 1736 1737 void 1738 gem_shutdown(arg) 1739 void *arg; 1740 { 1741 struct gem_softc *sc = (struct gem_softc *)arg; 1742 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1743 1744 gem_stop(ifp, 1); 1745 } 1746 1747 /* 1748 * Set up the logical address filter. 1749 */ 1750 void 1751 gem_setladrf(sc) 1752 struct gem_softc *sc; 1753 { 1754 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1755 struct ether_multi *enm; 1756 struct ether_multistep step; 1757 struct ethercom *ec = &sc->sc_ethercom; 1758 bus_space_tag_t t = sc->sc_bustag; 1759 bus_space_handle_t h = sc->sc_h; 1760 u_char *cp; 1761 u_int32_t crc; 1762 u_int32_t hash[16]; 1763 u_int32_t v; 1764 int len; 1765 1766 /* Clear hash table */ 1767 memset(hash, 0, sizeof(hash)); 1768 1769 /* Get current RX configuration */ 1770 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 1771 1772 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1773 /* Turn on promiscuous mode; turn off the hash filter */ 1774 v |= GEM_MAC_RX_PROMISCUOUS; 1775 v &= ~GEM_MAC_RX_HASH_FILTER; 1776 ifp->if_flags |= IFF_ALLMULTI; 1777 goto chipit; 1778 } 1779 1780 /* Turn off promiscuous mode; turn on the hash filter */ 1781 v &= ~GEM_MAC_RX_PROMISCUOUS; 1782 v |= GEM_MAC_RX_HASH_FILTER; 1783 1784 /* 1785 * Set up multicast address filter by passing all multicast addresses 1786 * through a crc generator, and then using the high order 6 bits as an 1787 * index into the 256 bit logical address filter. The high order bit 1788 * selects the word, while the rest of the bits select the bit within 1789 * the word. 1790 */ 1791 1792 ETHER_FIRST_MULTI(step, ec, enm); 1793 while (enm != NULL) { 1794 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1795 /* 1796 * We must listen to a range of multicast addresses. 1797 * For now, just accept all multicasts, rather than 1798 * trying to set only those filter bits needed to match 1799 * the range. (At this time, the only use of address 1800 * ranges is for IP multicast routing, for which the 1801 * range is big enough to require all bits set.) 1802 */ 1803 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1804 ifp->if_flags |= IFF_ALLMULTI; 1805 goto chipit; 1806 } 1807 1808 cp = enm->enm_addrlo; 1809 crc = 0xffffffff; 1810 for (len = sizeof(enm->enm_addrlo); --len >= 0;) { 1811 int octet = *cp++; 1812 int i; 1813 1814 #define MC_POLY_LE 0xedb88320UL /* mcast crc, little endian */ 1815 for (i = 0; i < 8; i++) { 1816 if ((crc & 1) ^ (octet & 1)) { 1817 crc >>= 1; 1818 crc ^= MC_POLY_LE; 1819 } else { 1820 crc >>= 1; 1821 } 1822 octet >>= 1; 1823 } 1824 } 1825 /* Just want the 8 most significant bits. */ 1826 crc >>= 24; 1827 1828 /* Set the corresponding bit in the filter. */ 1829 hash[crc >> 4] |= 1 << (crc & 0xf); 1830 1831 ETHER_NEXT_MULTI(step, enm); 1832 } 1833 1834 ifp->if_flags &= ~IFF_ALLMULTI; 1835 1836 chipit: 1837 /* Now load the hash table into the chip */ 1838 bus_space_write_4(t, h, GEM_MAC_HASH0, hash[0]); 1839 bus_space_write_4(t, h, GEM_MAC_HASH1, hash[1]); 1840 bus_space_write_4(t, h, GEM_MAC_HASH2, hash[2]); 1841 bus_space_write_4(t, h, GEM_MAC_HASH3, hash[3]); 1842 bus_space_write_4(t, h, GEM_MAC_HASH4, hash[4]); 1843 bus_space_write_4(t, h, GEM_MAC_HASH5, hash[5]); 1844 bus_space_write_4(t, h, GEM_MAC_HASH6, hash[6]); 1845 bus_space_write_4(t, h, GEM_MAC_HASH7, hash[7]); 1846 bus_space_write_4(t, h, GEM_MAC_HASH8, hash[8]); 1847 bus_space_write_4(t, h, GEM_MAC_HASH9, hash[9]); 1848 bus_space_write_4(t, h, GEM_MAC_HASH10, hash[10]); 1849 bus_space_write_4(t, h, GEM_MAC_HASH11, hash[11]); 1850 bus_space_write_4(t, h, GEM_MAC_HASH12, hash[12]); 1851 bus_space_write_4(t, h, GEM_MAC_HASH13, hash[13]); 1852 bus_space_write_4(t, h, GEM_MAC_HASH14, hash[14]); 1853 bus_space_write_4(t, h, GEM_MAC_HASH15, hash[15]); 1854 1855 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 1856 } 1857 1858 #if notyet 1859 1860 /* 1861 * gem_power: 1862 * 1863 * Power management (suspend/resume) hook. 1864 */ 1865 void 1866 gem_power(why, arg) 1867 int why; 1868 void *arg; 1869 { 1870 struct gem_softc *sc = arg; 1871 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1872 int s; 1873 1874 s = splnet(); 1875 switch (why) { 1876 case PWR_SUSPEND: 1877 case PWR_STANDBY: 1878 gem_stop(ifp, 1); 1879 if (sc->sc_power != NULL) 1880 (*sc->sc_power)(sc, why); 1881 break; 1882 case PWR_RESUME: 1883 if (ifp->if_flags & IFF_UP) { 1884 if (sc->sc_power != NULL) 1885 (*sc->sc_power)(sc, why); 1886 gem_init(ifp); 1887 } 1888 break; 1889 case PWR_SOFTSUSPEND: 1890 case PWR_SOFTSTANDBY: 1891 case PWR_SOFTRESUME: 1892 break; 1893 } 1894 splx(s); 1895 } 1896 #endif 1897
Indexes created Tue Sep 23 07:09:52 GMT 2025