gem.c revision 1.69
1 /* $NetBSD: gem.c,v 1.69 2008/01/19 22:10:16 dyoung Exp $ */ 2 3 /* 4 * 5 * Copyright (C) 2001 Eduardo Horvath. 6 * Copyright (c) 2001-2003 Thomas Moestl 7 * All rights reserved. 8 * 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 */ 32 33 /* 34 * Driver for Apple GMAC, Sun ERI and Sun GEM Ethernet controllers 35 * See `GEM Gigabit Ethernet ASIC Specification' 36 * http://www.sun.com/processors/manuals/ge.pdf 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: gem.c,v 1.69 2008/01/19 22:10:16 dyoung Exp $"); 41 42 #include "opt_inet.h" 43 #include "bpfilter.h" 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/callout.h> 48 #include <sys/mbuf.h> 49 #include <sys/syslog.h> 50 #include <sys/malloc.h> 51 #include <sys/kernel.h> 52 #include <sys/socket.h> 53 #include <sys/ioctl.h> 54 #include <sys/errno.h> 55 #include <sys/device.h> 56 57 #include <machine/endian.h> 58 59 #include <uvm/uvm_extern.h> 60 61 #include <net/if.h> 62 #include <net/if_dl.h> 63 #include <net/if_media.h> 64 #include <net/if_ether.h> 65 66 #ifdef INET 67 #include <netinet/in.h> 68 #include <netinet/in_systm.h> 69 #include <netinet/in_var.h> 70 #include <netinet/ip.h> 71 #include <netinet/tcp.h> 72 #include <netinet/udp.h> 73 #endif 74 75 #if NBPFILTER > 0 76 #include <net/bpf.h> 77 #endif 78 79 #include <sys/bus.h> 80 #include <sys/intr.h> 81 82 #include <dev/mii/mii.h> 83 #include <dev/mii/miivar.h> 84 #include <dev/mii/mii_bitbang.h> 85 86 #include <dev/ic/gemreg.h> 87 #include <dev/ic/gemvar.h> 88 89 #define TRIES 10000 90 91 static void gem_start(struct ifnet *); 92 static void gem_stop(struct ifnet *, int); 93 int gem_ioctl(struct ifnet *, u_long, void *); 94 void gem_tick(void *); 95 void gem_watchdog(struct ifnet *); 96 void gem_shutdown(void *); 97 void gem_pcs_start(struct gem_softc *sc); 98 void gem_pcs_stop(struct gem_softc *sc, int); 99 int gem_init(struct ifnet *); 100 void gem_init_regs(struct gem_softc *sc); 101 static int gem_ringsize(int sz); 102 static int gem_meminit(struct gem_softc *); 103 void gem_mifinit(struct gem_softc *); 104 static int gem_bitwait(struct gem_softc *sc, bus_space_handle_t, int, 105 u_int32_t, u_int32_t); 106 void gem_reset(struct gem_softc *); 107 int gem_reset_rx(struct gem_softc *sc); 108 static void gem_reset_rxdma(struct gem_softc *sc); 109 static void gem_rx_common(struct gem_softc *sc); 110 int gem_reset_tx(struct gem_softc *sc); 111 int gem_disable_rx(struct gem_softc *sc); 112 int gem_disable_tx(struct gem_softc *sc); 113 static void gem_rxdrain(struct gem_softc *sc); 114 int gem_add_rxbuf(struct gem_softc *sc, int idx); 115 void gem_setladrf(struct gem_softc *); 116 117 /* MII methods & callbacks */ 118 static int gem_mii_readreg(struct device *, int, int); 119 static void gem_mii_writereg(struct device *, int, int, int); 120 static void gem_mii_statchg(struct device *); 121 122 void gem_statuschange(struct gem_softc *); 123 124 int gem_ser_mediachange(struct ifnet *); 125 void gem_ser_mediastatus(struct ifnet *, struct ifmediareq *); 126 127 struct mbuf *gem_get(struct gem_softc *, int, int); 128 int gem_put(struct gem_softc *, int, struct mbuf *); 129 void gem_read(struct gem_softc *, int, int); 130 int gem_pint(struct gem_softc *); 131 int gem_eint(struct gem_softc *, u_int); 132 int gem_rint(struct gem_softc *); 133 int gem_tint(struct gem_softc *); 134 void gem_power(int, void *); 135 136 #ifdef GEM_DEBUG 137 static void gem_txsoft_print(const struct gem_softc *, int, int); 138 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 139 printf x 140 #else 141 #define DPRINTF(sc, x) /* nothing */ 142 #endif 143 144 #define ETHER_MIN_TX (ETHERMIN + sizeof(struct ether_header)) 145 146 147 /* 148 * gem_attach: 149 * 150 * Attach a Gem interface to the system. 151 */ 152 void 153 gem_attach(sc, enaddr) 154 struct gem_softc *sc; 155 const uint8_t *enaddr; 156 { 157 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 158 struct mii_data *mii = &sc->sc_mii; 159 bus_space_tag_t t = sc->sc_bustag; 160 bus_space_handle_t h = sc->sc_h1; 161 struct ifmedia_entry *ifm; 162 int i, error; 163 u_int32_t v; 164 char *nullbuf; 165 166 /* Make sure the chip is stopped. */ 167 ifp->if_softc = sc; 168 gem_reset(sc); 169 170 /* 171 * Allocate the control data structures, and create and load the 172 * DMA map for it. gem_control_data is 9216 bytes, we have space for 173 * the padding buffer in the bus_dmamem_alloc()'d memory. 174 */ 175 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 176 sizeof(struct gem_control_data) + ETHER_MIN_TX, PAGE_SIZE, 177 0, &sc->sc_cdseg, 1, &sc->sc_cdnseg, 0)) != 0) { 178 aprint_error( 179 "%s: unable to allocate control data, error = %d\n", 180 sc->sc_dev.dv_xname, error); 181 goto fail_0; 182 } 183 184 /* XXX should map this in with correct endianness */ 185 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg, 186 sizeof(struct gem_control_data), (void **)&sc->sc_control_data, 187 BUS_DMA_COHERENT)) != 0) { 188 aprint_error("%s: unable to map control data, error = %d\n", 189 sc->sc_dev.dv_xname, error); 190 goto fail_1; 191 } 192 193 nullbuf = 194 (char *)sc->sc_control_data + sizeof(struct gem_control_data); 195 196 if ((error = bus_dmamap_create(sc->sc_dmatag, 197 sizeof(struct gem_control_data), 1, 198 sizeof(struct gem_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 199 aprint_error("%s: unable to create control data DMA map, " 200 "error = %d\n", sc->sc_dev.dv_xname, error); 201 goto fail_2; 202 } 203 204 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 205 sc->sc_control_data, sizeof(struct gem_control_data), NULL, 206 0)) != 0) { 207 aprint_error( 208 "%s: unable to load control data DMA map, error = %d\n", 209 sc->sc_dev.dv_xname, error); 210 goto fail_3; 211 } 212 213 memset(nullbuf, 0, ETHER_MIN_TX); 214 if ((error = bus_dmamap_create(sc->sc_dmatag, 215 ETHER_MIN_TX, 1, ETHER_MIN_TX, 0, 0, &sc->sc_nulldmamap)) != 0) { 216 aprint_error("%s: unable to create padding DMA map, " 217 "error = %d\n", sc->sc_dev.dv_xname, error); 218 goto fail_4; 219 } 220 221 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_nulldmamap, 222 nullbuf, ETHER_MIN_TX, NULL, 0)) != 0) { 223 aprint_error( 224 "%s: unable to load padding DMA map, error = %d\n", 225 sc->sc_dev.dv_xname, error); 226 goto fail_5; 227 } 228 229 bus_dmamap_sync(sc->sc_dmatag, sc->sc_nulldmamap, 0, ETHER_MIN_TX, 230 BUS_DMASYNC_PREWRITE); 231 232 /* 233 * Initialize the transmit job descriptors. 234 */ 235 SIMPLEQ_INIT(&sc->sc_txfreeq); 236 SIMPLEQ_INIT(&sc->sc_txdirtyq); 237 238 /* 239 * Create the transmit buffer DMA maps. 240 */ 241 for (i = 0; i < GEM_TXQUEUELEN; i++) { 242 struct gem_txsoft *txs; 243 244 txs = &sc->sc_txsoft[i]; 245 txs->txs_mbuf = NULL; 246 if ((error = bus_dmamap_create(sc->sc_dmatag, 247 ETHER_MAX_LEN_JUMBO, GEM_NTXSEGS, 248 ETHER_MAX_LEN_JUMBO, 0, 0, 249 &txs->txs_dmamap)) != 0) { 250 aprint_error("%s: unable to create tx DMA map %d, " 251 "error = %d\n", sc->sc_dev.dv_xname, i, error); 252 goto fail_6; 253 } 254 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 255 } 256 257 /* 258 * Create the receive buffer DMA maps. 259 */ 260 for (i = 0; i < GEM_NRXDESC; i++) { 261 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, 262 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 263 aprint_error("%s: unable to create rx DMA map %d, " 264 "error = %d\n", sc->sc_dev.dv_xname, i, error); 265 goto fail_7; 266 } 267 sc->sc_rxsoft[i].rxs_mbuf = NULL; 268 } 269 270 /* Initialize ifmedia structures and MII info */ 271 mii->mii_ifp = ifp; 272 mii->mii_readreg = gem_mii_readreg; 273 mii->mii_writereg = gem_mii_writereg; 274 mii->mii_statchg = gem_mii_statchg; 275 276 sc->sc_ethercom.ec_mii = mii; 277 278 /* 279 * Initialization based on `GEM Gigabit Ethernet ASIC Specification' 280 * Section 3.2.1 `Initialization Sequence'. 281 * However, we can't assume SERDES or Serialink if neither 282 * GEM_MIF_CONFIG_MDI0 nor GEM_MIF_CONFIG_MDI1 are set 283 * being set, as both are set on Sun X1141A (with SERDES). So, 284 * we rely on our bus attachment setting GEM_SERDES or GEM_SERIAL. 285 */ 286 gem_mifinit(sc); 287 288 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) { 289 ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange, 290 ether_mediastatus); 291 mii_attach(&sc->sc_dev, mii, 0xffffffff, 292 MII_PHY_ANY, MII_OFFSET_ANY, MIIF_FORCEANEG); 293 if (LIST_EMPTY(&mii->mii_phys)) { 294 /* No PHY attached */ 295 aprint_error("%s: PHY probe failed\n", 296 sc->sc_dev.dv_xname); 297 goto fail_7; 298 } else { 299 struct mii_softc *child; 300 301 /* 302 * Walk along the list of attached MII devices and 303 * establish an `MII instance' to `PHY number' 304 * mapping. 305 */ 306 LIST_FOREACH(child, &mii->mii_phys, mii_list) { 307 /* 308 * Note: we support just one PHY: the internal 309 * or external MII is already selected for us 310 * by the GEM_MIF_CONFIG register. 311 */ 312 if (child->mii_phy > 1 || child->mii_inst > 0) { 313 aprint_error( 314 "%s: cannot accommodate MII device" 315 " %s at PHY %d, instance %d\n", 316 sc->sc_dev.dv_xname, 317 child->mii_dev.dv_xname, 318 child->mii_phy, child->mii_inst); 319 continue; 320 } 321 sc->sc_phys[child->mii_inst] = child->mii_phy; 322 } 323 324 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI0) { 325 #ifdef GEM_DEBUG 326 aprint_debug("%s: using PHY at MDIO_0\n", 327 sc->sc_dev.dv_xname); 328 #endif 329 } else { 330 #ifdef GEM_DEBUG 331 aprint_debug("%s: using PHY at MDIO_1\n", 332 sc->sc_dev.dv_xname); 333 #endif 334 } 335 if (sc->sc_variant != GEM_SUN_ERI) 336 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 337 GEM_MII_DATAPATH_MII); 338 339 /* 340 * XXX - we can really do the following ONLY if the 341 * PHY indeed has the auto negotiation capability!! 342 */ 343 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 344 } 345 } else { 346 ifmedia_init(&mii->mii_media, IFM_IMASK, gem_ser_mediachange, 347 gem_ser_mediastatus); 348 /* SERDES or Serialink */ 349 if (sc->sc_flags & GEM_SERDES) { 350 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 351 GEM_MII_DATAPATH_SERDES); 352 } else { 353 sc->sc_flags |= GEM_SERIAL; 354 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 355 GEM_MII_DATAPATH_SERIAL); 356 } 357 358 aprint_normal("%s: using external PCS %s: ", 359 sc->sc_dev.dv_xname, 360 sc->sc_flags & GEM_SERDES ? "SERDES" : "Serialink"); 361 362 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO, 0, NULL); 363 /* Check for FDX and HDX capabilities */ 364 sc->sc_mii_anar = bus_space_read_4(t, h, GEM_MII_ANAR); 365 if (sc->sc_mii_anar & GEM_MII_ANEG_FUL_DUPLX) { 366 ifmedia_add(&sc->sc_mii.mii_media, 367 IFM_ETHER|IFM_1000_SX|IFM_MANUAL|IFM_FDX, 0, NULL); 368 aprint_normal("1000baseSX-FDX, "); 369 } 370 if (sc->sc_mii_anar & GEM_MII_ANEG_HLF_DUPLX) { 371 ifmedia_add(&sc->sc_mii.mii_media, 372 IFM_ETHER|IFM_1000_SX|IFM_MANUAL|IFM_HDX, 0, NULL); 373 aprint_normal("1000baseSX-HDX, "); 374 } 375 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 376 sc->sc_mii_media = IFM_AUTO; 377 aprint_normal("auto\n"); 378 379 gem_pcs_stop(sc, 1); 380 } 381 382 /* 383 * From this point forward, the attachment cannot fail. A failure 384 * before this point releases all resources that may have been 385 * allocated. 386 */ 387 388 /* Announce ourselves. */ 389 aprint_normal("%s: Ethernet address %s", sc->sc_dev.dv_xname, 390 ether_sprintf(enaddr)); 391 392 /* Get RX FIFO size */ 393 sc->sc_rxfifosize = 64 * 394 bus_space_read_4(t, h, GEM_RX_FIFO_SIZE); 395 aprint_normal(", %uKB RX fifo", sc->sc_rxfifosize / 1024); 396 397 /* Get TX FIFO size */ 398 v = bus_space_read_4(t, h, GEM_TX_FIFO_SIZE); 399 aprint_normal(", %uKB TX fifo\n", v / 16); 400 401 /* Initialize ifnet structure. */ 402 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 403 ifp->if_softc = sc; 404 ifp->if_flags = 405 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 406 sc->sc_if_flags = ifp->if_flags; 407 /* The GEM hardware supports basic TCP checksum offloading only. */ 408 ifp->if_capabilities |= 409 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx; 410 ifp->if_start = gem_start; 411 ifp->if_ioctl = gem_ioctl; 412 ifp->if_watchdog = gem_watchdog; 413 ifp->if_stop = gem_stop; 414 ifp->if_init = gem_init; 415 IFQ_SET_READY(&ifp->if_snd); 416 417 /* 418 * If we support GigE media, we support jumbo frames too. 419 * Unless we are Apple. 420 */ 421 TAILQ_FOREACH(ifm, &sc->sc_mii.mii_media.ifm_list, ifm_list) { 422 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_T || 423 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_SX || 424 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_LX || 425 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_CX) { 426 if (sc->sc_variant != GEM_APPLE_GMAC) 427 sc->sc_ethercom.ec_capabilities 428 |= ETHERCAP_JUMBO_MTU; 429 430 sc->sc_flags |= GEM_GIGABIT; 431 break; 432 } 433 } 434 435 /* claim 802.1q capability */ 436 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 437 438 /* Attach the interface. */ 439 if_attach(ifp); 440 ether_ifattach(ifp, enaddr); 441 442 sc->sc_sh = shutdownhook_establish(gem_shutdown, sc); 443 if (sc->sc_sh == NULL) 444 panic("gem_config: can't establish shutdownhook"); 445 446 #if NRND > 0 447 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 448 RND_TYPE_NET, 0); 449 #endif 450 451 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, 452 NULL, sc->sc_dev.dv_xname, "interrupts"); 453 #ifdef GEM_COUNTERS 454 evcnt_attach_dynamic(&sc->sc_ev_txint, EVCNT_TYPE_INTR, 455 &sc->sc_ev_intr, sc->sc_dev.dv_xname, "tx interrupts"); 456 evcnt_attach_dynamic(&sc->sc_ev_rxint, EVCNT_TYPE_INTR, 457 &sc->sc_ev_intr, sc->sc_dev.dv_xname, "rx interrupts"); 458 evcnt_attach_dynamic(&sc->sc_ev_rxfull, EVCNT_TYPE_INTR, 459 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx ring full"); 460 evcnt_attach_dynamic(&sc->sc_ev_rxnobuf, EVCNT_TYPE_INTR, 461 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx malloc failure"); 462 evcnt_attach_dynamic(&sc->sc_ev_rxhist[0], EVCNT_TYPE_INTR, 463 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 0desc"); 464 evcnt_attach_dynamic(&sc->sc_ev_rxhist[1], EVCNT_TYPE_INTR, 465 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 1desc"); 466 evcnt_attach_dynamic(&sc->sc_ev_rxhist[2], EVCNT_TYPE_INTR, 467 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 2desc"); 468 evcnt_attach_dynamic(&sc->sc_ev_rxhist[3], EVCNT_TYPE_INTR, 469 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 3desc"); 470 evcnt_attach_dynamic(&sc->sc_ev_rxhist[4], EVCNT_TYPE_INTR, 471 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >3desc"); 472 evcnt_attach_dynamic(&sc->sc_ev_rxhist[5], EVCNT_TYPE_INTR, 473 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >7desc"); 474 evcnt_attach_dynamic(&sc->sc_ev_rxhist[6], EVCNT_TYPE_INTR, 475 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >15desc"); 476 evcnt_attach_dynamic(&sc->sc_ev_rxhist[7], EVCNT_TYPE_INTR, 477 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >31desc"); 478 evcnt_attach_dynamic(&sc->sc_ev_rxhist[8], EVCNT_TYPE_INTR, 479 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >63desc"); 480 #endif 481 482 #if notyet 483 /* 484 * Add a suspend hook to make sure we come back up after a 485 * resume. 486 */ 487 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 488 gem_power, sc); 489 if (sc->sc_powerhook == NULL) 490 aprint_error("%s: WARNING: unable to establish power hook\n", 491 sc->sc_dev.dv_xname); 492 #endif 493 494 callout_init(&sc->sc_tick_ch, 0); 495 return; 496 497 /* 498 * Free any resources we've allocated during the failed attach 499 * attempt. Do this in reverse order and fall through. 500 */ 501 fail_7: 502 for (i = 0; i < GEM_NRXDESC; i++) { 503 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 504 bus_dmamap_destroy(sc->sc_dmatag, 505 sc->sc_rxsoft[i].rxs_dmamap); 506 } 507 fail_6: 508 for (i = 0; i < GEM_TXQUEUELEN; i++) { 509 if (sc->sc_txsoft[i].txs_dmamap != NULL) 510 bus_dmamap_destroy(sc->sc_dmatag, 511 sc->sc_txsoft[i].txs_dmamap); 512 } 513 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 514 fail_5: 515 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_nulldmamap); 516 fail_4: 517 bus_dmamem_unmap(sc->sc_dmatag, (void *)nullbuf, ETHER_MIN_TX); 518 fail_3: 519 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 520 fail_2: 521 bus_dmamem_unmap(sc->sc_dmatag, (void *)sc->sc_control_data, 522 sizeof(struct gem_control_data)); 523 fail_1: 524 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 525 fail_0: 526 return; 527 } 528 529 530 void 531 gem_tick(arg) 532 void *arg; 533 { 534 struct gem_softc *sc = arg; 535 int s; 536 537 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) { 538 /* 539 * We have to reset everything if we failed to get a 540 * PCS interrupt. Restarting the callout is handled 541 * in gem_pcs_start(). 542 */ 543 gem_init(&sc->sc_ethercom.ec_if); 544 } else { 545 s = splnet(); 546 mii_tick(&sc->sc_mii); 547 splx(s); 548 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 549 } 550 } 551 552 static int 553 gem_bitwait(sc, h, r, clr, set) 554 struct gem_softc *sc; 555 bus_space_handle_t h; 556 int r; 557 u_int32_t clr; 558 u_int32_t set; 559 { 560 int i; 561 u_int32_t reg; 562 563 for (i = TRIES; i--; DELAY(100)) { 564 reg = bus_space_read_4(sc->sc_bustag, h, r); 565 if ((reg & clr) == 0 && (reg & set) == set) 566 return (1); 567 } 568 return (0); 569 } 570 571 void 572 gem_reset(sc) 573 struct gem_softc *sc; 574 { 575 bus_space_tag_t t = sc->sc_bustag; 576 bus_space_handle_t h = sc->sc_h2; 577 int s; 578 579 s = splnet(); 580 DPRINTF(sc, ("%s: gem_reset\n", sc->sc_dev.dv_xname)); 581 gem_reset_rx(sc); 582 gem_reset_tx(sc); 583 584 /* Do a full reset */ 585 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX|GEM_RESET_TX); 586 if (!gem_bitwait(sc, h, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0)) 587 printf("%s: cannot reset device\n", sc->sc_dev.dv_xname); 588 splx(s); 589 } 590 591 592 /* 593 * gem_rxdrain: 594 * 595 * Drain the receive queue. 596 */ 597 static void 598 gem_rxdrain(struct gem_softc *sc) 599 { 600 struct gem_rxsoft *rxs; 601 int i; 602 603 for (i = 0; i < GEM_NRXDESC; i++) { 604 rxs = &sc->sc_rxsoft[i]; 605 if (rxs->rxs_mbuf != NULL) { 606 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 607 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 608 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 609 m_freem(rxs->rxs_mbuf); 610 rxs->rxs_mbuf = NULL; 611 } 612 } 613 } 614 615 /* 616 * Reset the whole thing. 617 */ 618 static void 619 gem_stop(struct ifnet *ifp, int disable) 620 { 621 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 622 struct gem_txsoft *txs; 623 624 DPRINTF(sc, ("%s: gem_stop\n", sc->sc_dev.dv_xname)); 625 626 callout_stop(&sc->sc_tick_ch); 627 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 628 gem_pcs_stop(sc, disable); 629 else 630 mii_down(&sc->sc_mii); 631 632 /* XXX - Should we reset these instead? */ 633 gem_disable_tx(sc); 634 gem_disable_rx(sc); 635 636 /* 637 * Release any queued transmit buffers. 638 */ 639 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 640 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 641 if (txs->txs_mbuf != NULL) { 642 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 0, 643 txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 644 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 645 m_freem(txs->txs_mbuf); 646 txs->txs_mbuf = NULL; 647 } 648 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 649 } 650 651 if (disable) { 652 gem_rxdrain(sc); 653 } 654 655 /* 656 * Mark the interface down and cancel the watchdog timer. 657 */ 658 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 659 sc->sc_if_flags = ifp->if_flags; 660 ifp->if_timer = 0; 661 } 662 663 664 /* 665 * Reset the receiver 666 */ 667 int 668 gem_reset_rx(struct gem_softc *sc) 669 { 670 bus_space_tag_t t = sc->sc_bustag; 671 bus_space_handle_t h = sc->sc_h1, h2 = sc->sc_h2; 672 673 /* 674 * Resetting while DMA is in progress can cause a bus hang, so we 675 * disable DMA first. 676 */ 677 gem_disable_rx(sc); 678 bus_space_write_4(t, h, GEM_RX_CONFIG, 0); 679 bus_space_barrier(t, h, GEM_RX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 680 /* Wait till it finishes */ 681 if (!gem_bitwait(sc, h, GEM_RX_CONFIG, 1, 0)) 682 printf("%s: cannot disable read dma\n", sc->sc_dev.dv_xname); 683 684 /* Finally, reset the ERX */ 685 bus_space_write_4(t, h2, GEM_RESET, GEM_RESET_RX); 686 bus_space_barrier(t, h, GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE); 687 /* Wait till it finishes */ 688 if (!gem_bitwait(sc, h2, GEM_RESET, GEM_RESET_RX, 0)) { 689 printf("%s: cannot reset receiver\n", sc->sc_dev.dv_xname); 690 return (1); 691 } 692 return (0); 693 } 694 695 696 /* 697 * Reset the receiver DMA engine. 698 * 699 * Intended to be used in case of GEM_INTR_RX_TAG_ERR, GEM_MAC_RX_OVERFLOW 700 * etc in order to reset the receiver DMA engine only and not do a full 701 * reset which amongst others also downs the link and clears the FIFOs. 702 */ 703 static void 704 gem_reset_rxdma(struct gem_softc *sc) 705 { 706 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 707 bus_space_tag_t t = sc->sc_bustag; 708 bus_space_handle_t h = sc->sc_h1; 709 int i; 710 711 if (gem_reset_rx(sc) != 0) { 712 gem_init(ifp); 713 return; 714 } 715 for (i = 0; i < GEM_NRXDESC; i++) 716 if (sc->sc_rxsoft[i].rxs_mbuf != NULL) 717 GEM_UPDATE_RXDESC(sc, i); 718 sc->sc_rxptr = 0; 719 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE); 720 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD); 721 722 /* Reprogram Descriptor Ring Base Addresses */ 723 /* NOTE: we use only 32-bit DMA addresses here. */ 724 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0); 725 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 726 727 /* Redo ERX Configuration */ 728 gem_rx_common(sc); 729 730 /* Give the reciever a swift kick */ 731 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC - 4); 732 } 733 734 /* 735 * Common RX configuration for gem_init() and gem_reset_rxdma(). 736 */ 737 static void 738 gem_rx_common(struct gem_softc *sc) 739 { 740 bus_space_tag_t t = sc->sc_bustag; 741 bus_space_handle_t h = sc->sc_h1; 742 u_int32_t v; 743 744 /* Encode Receive Descriptor ring size: four possible values */ 745 v = gem_ringsize(GEM_NRXDESC /*XXX*/); 746 747 /* Set receive h/w checksum offset */ 748 #ifdef INET 749 v |= (ETHER_HDR_LEN + sizeof(struct ip) + 750 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 751 ETHER_VLAN_ENCAP_LEN : 0)) << GEM_RX_CONFIG_CXM_START_SHFT; 752 #endif 753 754 /* Enable RX DMA */ 755 bus_space_write_4(t, h, GEM_RX_CONFIG, 756 v | (GEM_THRSH_1024 << GEM_RX_CONFIG_FIFO_THRS_SHIFT) | 757 (2 << GEM_RX_CONFIG_FBOFF_SHFT) | GEM_RX_CONFIG_RXDMA_EN); 758 759 /* 760 * The following value is for an OFF Threshold of about 3/4 full 761 * and an ON Threshold of 1/4 full. 762 */ 763 bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH, 764 (3 * sc->sc_rxfifosize / 256) | 765 ((sc->sc_rxfifosize / 256) << 12)); 766 bus_space_write_4(t, h, GEM_RX_BLANKING, 767 (6 << GEM_RX_BLANKING_TIME_SHIFT) | 6); 768 } 769 770 /* 771 * Reset the transmitter 772 */ 773 int 774 gem_reset_tx(struct gem_softc *sc) 775 { 776 bus_space_tag_t t = sc->sc_bustag; 777 bus_space_handle_t h = sc->sc_h1, h2 = sc->sc_h2; 778 779 /* 780 * Resetting while DMA is in progress can cause a bus hang, so we 781 * disable DMA first. 782 */ 783 gem_disable_tx(sc); 784 bus_space_write_4(t, h, GEM_TX_CONFIG, 0); 785 bus_space_barrier(t, h, GEM_TX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 786 /* Wait till it finishes */ 787 if (!gem_bitwait(sc, h, GEM_TX_CONFIG, 1, 0)) 788 printf("%s: cannot disable read dma\n", sc->sc_dev.dv_xname); 789 /* Wait 5ms extra. */ 790 delay(5000); 791 792 /* Finally, reset the ETX */ 793 bus_space_write_4(t, h2, GEM_RESET, GEM_RESET_TX); 794 bus_space_barrier(t, h, GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE); 795 /* Wait till it finishes */ 796 if (!gem_bitwait(sc, h2, GEM_RESET, GEM_RESET_TX, 0)) { 797 printf("%s: cannot reset receiver\n", 798 sc->sc_dev.dv_xname); 799 return (1); 800 } 801 return (0); 802 } 803 804 /* 805 * disable receiver. 806 */ 807 int 808 gem_disable_rx(struct gem_softc *sc) 809 { 810 bus_space_tag_t t = sc->sc_bustag; 811 bus_space_handle_t h = sc->sc_h1; 812 u_int32_t cfg; 813 814 /* Flip the enable bit */ 815 cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 816 cfg &= ~GEM_MAC_RX_ENABLE; 817 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg); 818 bus_space_barrier(t, h, GEM_MAC_RX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 819 /* Wait for it to finish */ 820 return (gem_bitwait(sc, h, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)); 821 } 822 823 /* 824 * disable transmitter. 825 */ 826 int 827 gem_disable_tx(struct gem_softc *sc) 828 { 829 bus_space_tag_t t = sc->sc_bustag; 830 bus_space_handle_t h = sc->sc_h1; 831 u_int32_t cfg; 832 833 /* Flip the enable bit */ 834 cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG); 835 cfg &= ~GEM_MAC_TX_ENABLE; 836 bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg); 837 bus_space_barrier(t, h, GEM_MAC_TX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 838 /* Wait for it to finish */ 839 return (gem_bitwait(sc, h, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)); 840 } 841 842 /* 843 * Initialize interface. 844 */ 845 int 846 gem_meminit(struct gem_softc *sc) 847 { 848 struct gem_rxsoft *rxs; 849 int i, error; 850 851 /* 852 * Initialize the transmit descriptor ring. 853 */ 854 memset((void *)sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 855 for (i = 0; i < GEM_NTXDESC; i++) { 856 sc->sc_txdescs[i].gd_flags = 0; 857 sc->sc_txdescs[i].gd_addr = 0; 858 } 859 GEM_CDTXSYNC(sc, 0, GEM_NTXDESC, 860 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 861 sc->sc_txfree = GEM_NTXDESC-1; 862 sc->sc_txnext = 0; 863 sc->sc_txwin = 0; 864 865 /* 866 * Initialize the receive descriptor and receive job 867 * descriptor rings. 868 */ 869 for (i = 0; i < GEM_NRXDESC; i++) { 870 rxs = &sc->sc_rxsoft[i]; 871 if (rxs->rxs_mbuf == NULL) { 872 if ((error = gem_add_rxbuf(sc, i)) != 0) { 873 printf("%s: unable to allocate or map rx " 874 "buffer %d, error = %d\n", 875 sc->sc_dev.dv_xname, i, error); 876 /* 877 * XXX Should attempt to run with fewer receive 878 * XXX buffers instead of just failing. 879 */ 880 gem_rxdrain(sc); 881 return (1); 882 } 883 } else 884 GEM_INIT_RXDESC(sc, i); 885 } 886 sc->sc_rxptr = 0; 887 sc->sc_meminited = 1; 888 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE); 889 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD); 890 891 return (0); 892 } 893 894 static int 895 gem_ringsize(int sz) 896 { 897 switch (sz) { 898 case 32: 899 return GEM_RING_SZ_32; 900 case 64: 901 return GEM_RING_SZ_64; 902 case 128: 903 return GEM_RING_SZ_128; 904 case 256: 905 return GEM_RING_SZ_256; 906 case 512: 907 return GEM_RING_SZ_512; 908 case 1024: 909 return GEM_RING_SZ_1024; 910 case 2048: 911 return GEM_RING_SZ_2048; 912 case 4096: 913 return GEM_RING_SZ_4096; 914 case 8192: 915 return GEM_RING_SZ_8192; 916 default: 917 printf("gem: invalid Receive Descriptor ring size %d\n", sz); 918 return GEM_RING_SZ_32; 919 } 920 } 921 922 923 /* 924 * Start PCS 925 */ 926 void 927 gem_pcs_start(struct gem_softc *sc) 928 { 929 bus_space_tag_t t = sc->sc_bustag; 930 bus_space_handle_t h = sc->sc_h1; 931 uint32_t v; 932 933 #ifdef GEM_DEBUG 934 aprint_debug("%s: gem_pcs_start()\n", sc->sc_dev.dv_xname); 935 #endif 936 937 /* 938 * Set up. We must disable the MII before modifying the 939 * GEM_MII_ANAR register 940 */ 941 if (sc->sc_flags & GEM_SERDES) { 942 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 943 GEM_MII_DATAPATH_SERDES); 944 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 945 GEM_MII_SLINK_LOOPBACK); 946 } else { 947 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 948 GEM_MII_DATAPATH_SERIAL); 949 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 0); 950 } 951 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 952 v = bus_space_read_4(t, h, GEM_MII_ANAR); 953 v |= (GEM_MII_ANEG_SYM_PAUSE | GEM_MII_ANEG_ASYM_PAUSE); 954 if (sc->sc_mii_media == IFM_AUTO) 955 v |= (GEM_MII_ANEG_FUL_DUPLX | GEM_MII_ANEG_HLF_DUPLX); 956 else if (sc->sc_mii_media == IFM_FDX) { 957 v |= GEM_MII_ANEG_FUL_DUPLX; 958 v &= ~GEM_MII_ANEG_HLF_DUPLX; 959 } else if (sc->sc_mii_media == IFM_HDX) { 960 v &= ~GEM_MII_ANEG_FUL_DUPLX; 961 v |= GEM_MII_ANEG_HLF_DUPLX; 962 } 963 964 /* Configure link. */ 965 bus_space_write_4(t, h, GEM_MII_ANAR, v); 966 bus_space_write_4(t, h, GEM_MII_CONTROL, 967 GEM_MII_CONTROL_AUTONEG | GEM_MII_CONTROL_RAN); 968 bus_space_write_4(t, h, GEM_MII_CONFIG, GEM_MII_CONFIG_ENABLE); 969 gem_bitwait(sc, h, GEM_MII_STATUS, 0, GEM_MII_STATUS_ANEG_CPT); 970 971 /* Start the 10 second timer */ 972 callout_reset(&sc->sc_tick_ch, hz * 10, gem_tick, sc); 973 } 974 975 /* 976 * Stop PCS 977 */ 978 void 979 gem_pcs_stop(struct gem_softc *sc, int disable) 980 { 981 bus_space_tag_t t = sc->sc_bustag; 982 bus_space_handle_t h = sc->sc_h1; 983 984 #ifdef GEM_DEBUG 985 aprint_debug("%s: gem_pcs_stop()\n", sc->sc_dev.dv_xname); 986 #endif 987 988 /* Tell link partner that we're going away */ 989 bus_space_write_4(t, h, GEM_MII_ANAR, GEM_MII_ANEG_RF); 990 991 /* 992 * Disable PCS MII. The documentation suggests that setting 993 * GEM_MII_CONFIG_ENABLE to zero and then restarting auto- 994 * negotiation will shut down the link. However, it appears 995 * that we also need to unset the datapath mode. 996 */ 997 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 998 bus_space_write_4(t, h, GEM_MII_CONTROL, 999 GEM_MII_CONTROL_AUTONEG | GEM_MII_CONTROL_RAN); 1000 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, GEM_MII_DATAPATH_MII); 1001 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 1002 1003 if (disable) { 1004 if (sc->sc_flags & GEM_SERDES) 1005 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 1006 GEM_MII_SLINK_POWER_OFF); 1007 else 1008 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 1009 GEM_MII_SLINK_LOOPBACK | GEM_MII_SLINK_POWER_OFF); 1010 } 1011 1012 sc->sc_flags &= ~GEM_LINK; 1013 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_NONE; 1014 sc->sc_mii.mii_media_status = IFM_AVALID; 1015 } 1016 1017 1018 /* 1019 * Initialization of interface; set up initialization block 1020 * and transmit/receive descriptor rings. 1021 */ 1022 int 1023 gem_init(struct ifnet *ifp) 1024 { 1025 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 1026 bus_space_tag_t t = sc->sc_bustag; 1027 bus_space_handle_t h = sc->sc_h1; 1028 int rc = 0, s; 1029 u_int max_frame_size; 1030 u_int32_t v; 1031 1032 s = splnet(); 1033 1034 DPRINTF(sc, ("%s: gem_init: calling stop\n", sc->sc_dev.dv_xname)); 1035 /* 1036 * Initialization sequence. The numbered steps below correspond 1037 * to the sequence outlined in section 6.3.5.1 in the Ethernet 1038 * Channel Engine manual (part of the PCIO manual). 1039 * See also the STP2002-STQ document from Sun Microsystems. 1040 */ 1041 1042 /* step 1 & 2. Reset the Ethernet Channel */ 1043 gem_stop(ifp, 0); 1044 gem_reset(sc); 1045 DPRINTF(sc, ("%s: gem_init: restarting\n", sc->sc_dev.dv_xname)); 1046 1047 /* Re-initialize the MIF */ 1048 gem_mifinit(sc); 1049 1050 /* Set up correct datapath for non-SERDES/Serialink */ 1051 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0 && 1052 sc->sc_variant != GEM_SUN_ERI) 1053 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 1054 GEM_MII_DATAPATH_MII); 1055 1056 /* Call MI reset function if any */ 1057 if (sc->sc_hwreset) 1058 (*sc->sc_hwreset)(sc); 1059 1060 /* step 3. Setup data structures in host memory */ 1061 if (gem_meminit(sc) != 0) 1062 return 1; 1063 1064 /* step 4. TX MAC registers & counters */ 1065 gem_init_regs(sc); 1066 max_frame_size = max(sc->sc_ethercom.ec_if.if_mtu, ETHERMTU); 1067 max_frame_size += ETHER_HDR_LEN + ETHER_CRC_LEN; 1068 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1069 max_frame_size += ETHER_VLAN_ENCAP_LEN; 1070 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 1071 max_frame_size|/* burst size */(0x2000<<16)); 1072 1073 /* step 5. RX MAC registers & counters */ 1074 gem_setladrf(sc); 1075 1076 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 1077 /* NOTE: we use only 32-bit DMA addresses here. */ 1078 bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 0); 1079 bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 1080 1081 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0); 1082 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 1083 1084 /* step 8. Global Configuration & Interrupt Mask */ 1085 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 1086 v = GEM_INTR_PCS; 1087 else 1088 v = GEM_INTR_MIF; 1089 bus_space_write_4(t, h, GEM_INTMASK, 1090 ~(GEM_INTR_TX_INTME | 1091 GEM_INTR_TX_EMPTY | 1092 GEM_INTR_TX_MAC | 1093 GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF| 1094 GEM_INTR_RX_TAG_ERR | GEM_INTR_MAC_CONTROL| 1095 GEM_INTR_BERR | v)); 1096 bus_space_write_4(t, h, GEM_MAC_RX_MASK, 1097 GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT); 1098 bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXX */ 1099 bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 1100 GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME); 1101 1102 /* step 9. ETX Configuration: use mostly default values */ 1103 1104 /* Enable TX DMA */ 1105 v = gem_ringsize(GEM_NTXDESC /*XXX*/); 1106 bus_space_write_4(t, h, GEM_TX_CONFIG, 1107 v|GEM_TX_CONFIG_TXDMA_EN| 1108 ((0x4FF<<10)&GEM_TX_CONFIG_TXFIFO_TH)); 1109 bus_space_write_4(t, h, GEM_TX_KICK, sc->sc_txnext); 1110 1111 /* step 10. ERX Configuration */ 1112 gem_rx_common(sc); 1113 1114 /* step 11. Configure Media */ 1115 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0 && 1116 (rc = mii_ifmedia_change(&sc->sc_mii)) != 0) 1117 goto out; 1118 1119 /* step 12. RX_MAC Configuration Register */ 1120 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 1121 v |= GEM_MAC_RX_ENABLE | GEM_MAC_RX_STRIP_CRC; 1122 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 1123 1124 /* step 14. Issue Transmit Pending command */ 1125 1126 /* Call MI initialization function if any */ 1127 if (sc->sc_hwinit) 1128 (*sc->sc_hwinit)(sc); 1129 1130 1131 /* step 15. Give the reciever a swift kick */ 1132 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4); 1133 1134 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 1135 /* Configure PCS */ 1136 gem_pcs_start(sc); 1137 else 1138 /* Start the one second timer. */ 1139 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 1140 1141 sc->sc_flags &= ~GEM_LINK; 1142 ifp->if_flags |= IFF_RUNNING; 1143 ifp->if_flags &= ~IFF_OACTIVE; 1144 ifp->if_timer = 0; 1145 sc->sc_if_flags = ifp->if_flags; 1146 out: 1147 splx(s); 1148 1149 return (0); 1150 } 1151 1152 void 1153 gem_init_regs(struct gem_softc *sc) 1154 { 1155 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1156 bus_space_tag_t t = sc->sc_bustag; 1157 bus_space_handle_t h = sc->sc_h1; 1158 const u_char *laddr = CLLADDR(ifp->if_sadl); 1159 u_int32_t v; 1160 1161 /* These regs are not cleared on reset */ 1162 if (!sc->sc_inited) { 1163 1164 /* Load recommended values */ 1165 bus_space_write_4(t, h, GEM_MAC_IPG0, 0x00); 1166 bus_space_write_4(t, h, GEM_MAC_IPG1, 0x08); 1167 bus_space_write_4(t, h, GEM_MAC_IPG2, 0x04); 1168 1169 bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 1170 /* Max frame and max burst size */ 1171 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 1172 ETHER_MAX_LEN | (0x2000<<16)); 1173 1174 bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x07); 1175 bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x04); 1176 bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10); 1177 bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088); 1178 bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED, 1179 ((laddr[5]<<8)|laddr[4])&0x3ff); 1180 1181 /* Secondary MAC addr set to 0:0:0:0:0:0 */ 1182 bus_space_write_4(t, h, GEM_MAC_ADDR3, 0); 1183 bus_space_write_4(t, h, GEM_MAC_ADDR4, 0); 1184 bus_space_write_4(t, h, GEM_MAC_ADDR5, 0); 1185 1186 /* MAC control addr set to 01:80:c2:00:00:01 */ 1187 bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001); 1188 bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200); 1189 bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180); 1190 1191 /* MAC filter addr set to 0:0:0:0:0:0 */ 1192 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0); 1193 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0); 1194 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0); 1195 1196 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0); 1197 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0); 1198 1199 sc->sc_inited = 1; 1200 } 1201 1202 /* Counters need to be zeroed */ 1203 bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0); 1204 bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0); 1205 bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0); 1206 bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0); 1207 bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0); 1208 bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0); 1209 bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0); 1210 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 1211 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 1212 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 1213 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 1214 1215 /* Set XOFF PAUSE time. */ 1216 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); 1217 1218 /* 1219 * Set the internal arbitration to "infinite" bursts of the 1220 * maximum length of 31 * 64 bytes so DMA transfers aren't 1221 * split up in cache line size chunks. This greatly improves 1222 * especially RX performance. 1223 * Enable silicon bug workarounds for the Apple variants. 1224 */ 1225 bus_space_write_4(t, h, GEM_CONFIG, 1226 GEM_CONFIG_TXDMA_LIMIT | GEM_CONFIG_RXDMA_LIMIT | 1227 GEM_CONFIG_BURST_INF | (GEM_IS_APPLE(sc) ? 1228 GEM_CONFIG_RONPAULBIT | GEM_CONFIG_BUG2FIX : 0)); 1229 1230 /* 1231 * Set the station address. 1232 */ 1233 bus_space_write_4(t, h, GEM_MAC_ADDR0, (laddr[4]<<8)|laddr[5]); 1234 bus_space_write_4(t, h, GEM_MAC_ADDR1, (laddr[2]<<8)|laddr[3]); 1235 bus_space_write_4(t, h, GEM_MAC_ADDR2, (laddr[0]<<8)|laddr[1]); 1236 1237 /* 1238 * Enable MII outputs. Enable GMII if there is a gigabit PHY. 1239 */ 1240 v = GEM_MAC_XIF_TX_MII_ENA; 1241 if (sc->sc_flags & GEM_GIGABIT) 1242 v |= GEM_MAC_XIF_GMII_MODE; 1243 bus_space_write_4(t, h, GEM_MAC_XIF_CONFIG, v); 1244 } 1245 1246 #ifdef GEM_DEBUG 1247 static void 1248 gem_txsoft_print(const struct gem_softc *sc, int firstdesc, int lastdesc) 1249 { 1250 int i; 1251 1252 for (i = firstdesc;; i = GEM_NEXTTX(i)) { 1253 printf("descriptor %d:\t", i); 1254 printf("gd_flags: 0x%016" PRIx64 "\t", 1255 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags)); 1256 printf("gd_addr: 0x%016" PRIx64 "\n", 1257 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr)); 1258 if (i == lastdesc) 1259 break; 1260 } 1261 } 1262 #endif 1263 1264 static void 1265 gem_start(ifp) 1266 struct ifnet *ifp; 1267 { 1268 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 1269 struct mbuf *m0, *m; 1270 struct gem_txsoft *txs; 1271 bus_dmamap_t dmamap; 1272 int error, firsttx, nexttx = -1, lasttx = -1, ofree, seg; 1273 uint64_t flags = 0; 1274 1275 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1276 return; 1277 1278 /* 1279 * Remember the previous number of free descriptors and 1280 * the first descriptor we'll use. 1281 */ 1282 ofree = sc->sc_txfree; 1283 firsttx = sc->sc_txnext; 1284 1285 DPRINTF(sc, ("%s: gem_start: txfree %d, txnext %d\n", 1286 sc->sc_dev.dv_xname, ofree, firsttx)); 1287 1288 /* 1289 * Loop through the send queue, setting up transmit descriptors 1290 * until we drain the queue, or use up all available transmit 1291 * descriptors. 1292 */ 1293 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 1294 sc->sc_txfree != 0) { 1295 /* 1296 * Grab a packet off the queue. 1297 */ 1298 IFQ_POLL(&ifp->if_snd, m0); 1299 if (m0 == NULL) 1300 break; 1301 m = NULL; 1302 1303 dmamap = txs->txs_dmamap; 1304 1305 /* 1306 * Load the DMA map. If this fails, the packet either 1307 * didn't fit in the alloted number of segments, or we were 1308 * short on resources. In this case, we'll copy and try 1309 * again. 1310 */ 1311 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m0, 1312 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0 || 1313 (m0->m_pkthdr.len < ETHER_MIN_TX && 1314 dmamap->dm_nsegs == GEM_NTXSEGS)) { 1315 if (m0->m_pkthdr.len > MCLBYTES) { 1316 printf("%s: unable to allocate jumbo Tx " 1317 "cluster\n", sc->sc_dev.dv_xname); 1318 IFQ_DEQUEUE(&ifp->if_snd, m0); 1319 m_freem(m0); 1320 continue; 1321 } 1322 MGETHDR(m, M_DONTWAIT, MT_DATA); 1323 if (m == NULL) { 1324 printf("%s: unable to allocate Tx mbuf\n", 1325 sc->sc_dev.dv_xname); 1326 break; 1327 } 1328 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1329 if (m0->m_pkthdr.len > MHLEN) { 1330 MCLGET(m, M_DONTWAIT); 1331 if ((m->m_flags & M_EXT) == 0) { 1332 printf("%s: unable to allocate Tx " 1333 "cluster\n", sc->sc_dev.dv_xname); 1334 m_freem(m); 1335 break; 1336 } 1337 } 1338 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1339 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1340 error = bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, 1341 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1342 if (error) { 1343 printf("%s: unable to load Tx buffer, " 1344 "error = %d\n", sc->sc_dev.dv_xname, error); 1345 break; 1346 } 1347 } 1348 1349 /* 1350 * Ensure we have enough descriptors free to describe 1351 * the packet. 1352 */ 1353 if (dmamap->dm_nsegs > ((m0->m_pkthdr.len < ETHER_MIN_TX) ? 1354 (sc->sc_txfree - 1) : sc->sc_txfree)) { 1355 /* 1356 * Not enough free descriptors to transmit this 1357 * packet. We haven't committed to anything yet, 1358 * so just unload the DMA map, put the packet 1359 * back on the queue, and punt. Notify the upper 1360 * layer that there are no more slots left. 1361 * 1362 * XXX We could allocate an mbuf and copy, but 1363 * XXX it is worth it? 1364 */ 1365 ifp->if_flags |= IFF_OACTIVE; 1366 sc->sc_if_flags = ifp->if_flags; 1367 bus_dmamap_unload(sc->sc_dmatag, dmamap); 1368 if (m != NULL) 1369 m_freem(m); 1370 break; 1371 } 1372 1373 IFQ_DEQUEUE(&ifp->if_snd, m0); 1374 if (m != NULL) { 1375 m_freem(m0); 1376 m0 = m; 1377 } 1378 1379 /* 1380 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1381 */ 1382 1383 /* Sync the DMA map. */ 1384 bus_dmamap_sync(sc->sc_dmatag, dmamap, 0, dmamap->dm_mapsize, 1385 BUS_DMASYNC_PREWRITE); 1386 1387 /* 1388 * Initialize the transmit descriptors. 1389 */ 1390 for (nexttx = sc->sc_txnext, seg = 0; 1391 seg < dmamap->dm_nsegs; 1392 seg++, nexttx = GEM_NEXTTX(nexttx)) { 1393 1394 /* 1395 * If this is the first descriptor we're 1396 * enqueueing, set the start of packet flag, 1397 * and the checksum stuff if we want the hardware 1398 * to do it. 1399 */ 1400 sc->sc_txdescs[nexttx].gd_addr = 1401 GEM_DMA_WRITE(sc, dmamap->dm_segs[seg].ds_addr); 1402 flags = dmamap->dm_segs[seg].ds_len & GEM_TD_BUFSIZE; 1403 if (nexttx == firsttx) { 1404 flags |= GEM_TD_START_OF_PACKET; 1405 if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) { 1406 sc->sc_txwin = 0; 1407 flags |= GEM_TD_INTERRUPT_ME; 1408 } 1409 1410 #ifdef INET 1411 /* h/w checksum */ 1412 if (ifp->if_csum_flags_tx & M_CSUM_TCPv4 && 1413 m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1414 struct ether_header *eh; 1415 uint16_t offset, start; 1416 1417 eh = mtod(m0, struct ether_header *); 1418 switch (ntohs(eh->ether_type)) { 1419 case ETHERTYPE_IP: 1420 start = ETHER_HDR_LEN; 1421 break; 1422 case ETHERTYPE_VLAN: 1423 start = ETHER_HDR_LEN + 1424 ETHER_VLAN_ENCAP_LEN; 1425 break; 1426 default: 1427 /* unsupported, drop it */ 1428 m_free(m0); 1429 continue; 1430 } 1431 start += M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 1432 offset = M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data) + start; 1433 flags |= (start << 1434 GEM_TD_CXSUM_STARTSHFT) | 1435 (offset << 1436 GEM_TD_CXSUM_STUFFSHFT) | 1437 GEM_TD_CXSUM_ENABLE; 1438 } 1439 #endif 1440 } 1441 if (seg == dmamap->dm_nsegs - 1) { 1442 flags |= GEM_TD_END_OF_PACKET; 1443 } else { 1444 /* last flag set outside of loop */ 1445 sc->sc_txdescs[nexttx].gd_flags = 1446 GEM_DMA_WRITE(sc, flags); 1447 } 1448 lasttx = nexttx; 1449 } 1450 if (m0->m_pkthdr.len < ETHER_MIN_TX) { 1451 /* add padding buffer at end of chain */ 1452 flags &= ~GEM_TD_END_OF_PACKET; 1453 sc->sc_txdescs[lasttx].gd_flags = 1454 GEM_DMA_WRITE(sc, flags); 1455 1456 sc->sc_txdescs[nexttx].gd_addr = 1457 GEM_DMA_WRITE(sc, 1458 sc->sc_nulldmamap->dm_segs[0].ds_addr); 1459 flags = ((ETHER_MIN_TX - m0->m_pkthdr.len) & 1460 GEM_TD_BUFSIZE) | GEM_TD_END_OF_PACKET; 1461 lasttx = nexttx; 1462 nexttx = GEM_NEXTTX(nexttx); 1463 seg++; 1464 } 1465 sc->sc_txdescs[lasttx].gd_flags = GEM_DMA_WRITE(sc, flags); 1466 1467 KASSERT(lasttx != -1); 1468 1469 /* 1470 * Store a pointer to the packet so we can free it later, 1471 * and remember what txdirty will be once the packet is 1472 * done. 1473 */ 1474 txs->txs_mbuf = m0; 1475 txs->txs_firstdesc = sc->sc_txnext; 1476 txs->txs_lastdesc = lasttx; 1477 txs->txs_ndescs = seg; 1478 1479 #ifdef GEM_DEBUG 1480 if (ifp->if_flags & IFF_DEBUG) { 1481 printf(" gem_start %p transmit chain:\n", txs); 1482 gem_txsoft_print(sc, txs->txs_firstdesc, 1483 txs->txs_lastdesc); 1484 } 1485 #endif 1486 1487 /* Sync the descriptors we're using. */ 1488 GEM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndescs, 1489 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1490 1491 /* Advance the tx pointer. */ 1492 sc->sc_txfree -= txs->txs_ndescs; 1493 sc->sc_txnext = nexttx; 1494 1495 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1496 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1497 1498 #if NBPFILTER > 0 1499 /* 1500 * Pass the packet to any BPF listeners. 1501 */ 1502 if (ifp->if_bpf) 1503 bpf_mtap(ifp->if_bpf, m0); 1504 #endif /* NBPFILTER > 0 */ 1505 } 1506 1507 if (txs == NULL || sc->sc_txfree == 0) { 1508 /* No more slots left; notify upper layer. */ 1509 ifp->if_flags |= IFF_OACTIVE; 1510 sc->sc_if_flags = ifp->if_flags; 1511 } 1512 1513 if (sc->sc_txfree != ofree) { 1514 DPRINTF(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 1515 sc->sc_dev.dv_xname, lasttx, firsttx)); 1516 /* 1517 * The entire packet chain is set up. 1518 * Kick the transmitter. 1519 */ 1520 DPRINTF(sc, ("%s: gem_start: kicking tx %d\n", 1521 sc->sc_dev.dv_xname, nexttx)); 1522 bus_space_write_4(sc->sc_bustag, sc->sc_h1, GEM_TX_KICK, 1523 sc->sc_txnext); 1524 1525 /* Set a watchdog timer in case the chip flakes out. */ 1526 ifp->if_timer = 5; 1527 DPRINTF(sc, ("%s: gem_start: watchdog %d\n", 1528 sc->sc_dev.dv_xname, ifp->if_timer)); 1529 } 1530 } 1531 1532 /* 1533 * Transmit interrupt. 1534 */ 1535 int 1536 gem_tint(sc) 1537 struct gem_softc *sc; 1538 { 1539 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1540 bus_space_tag_t t = sc->sc_bustag; 1541 bus_space_handle_t mac = sc->sc_h1; 1542 struct gem_txsoft *txs; 1543 int txlast; 1544 int progress = 0; 1545 1546 DPRINTF(sc, ("%s: gem_tint\n", sc->sc_dev.dv_xname)); 1547 1548 /* 1549 * Unload collision counters 1550 */ 1551 ifp->if_collisions += 1552 bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) + 1553 bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT) + 1554 bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) + 1555 bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT); 1556 1557 /* 1558 * then clear the hardware counters. 1559 */ 1560 bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0); 1561 bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0); 1562 bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0); 1563 bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0); 1564 1565 /* 1566 * Go through our Tx list and free mbufs for those 1567 * frames that have been transmitted. 1568 */ 1569 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1570 /* 1571 * In theory, we could harvest some descriptors before 1572 * the ring is empty, but that's a bit complicated. 1573 * 1574 * GEM_TX_COMPLETION points to the last descriptor 1575 * processed +1. 1576 * 1577 * Let's assume that the NIC writes back to the Tx 1578 * descriptors before it updates the completion 1579 * register. If the NIC has posted writes to the 1580 * Tx descriptors, PCI ordering requires that the 1581 * posted writes flush to RAM before the register-read 1582 * finishes. So let's read the completion register, 1583 * before syncing the descriptors, so that we 1584 * examine Tx descriptors that are at least as 1585 * current as the completion register. 1586 */ 1587 txlast = bus_space_read_4(t, mac, GEM_TX_COMPLETION); 1588 DPRINTF(sc, 1589 ("gem_tint: txs->txs_lastdesc = %d, txlast = %d\n", 1590 txs->txs_lastdesc, txlast)); 1591 if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1592 if (txlast >= txs->txs_firstdesc && 1593 txlast <= txs->txs_lastdesc) 1594 break; 1595 } else if (txlast >= txs->txs_firstdesc || 1596 txlast <= txs->txs_lastdesc) 1597 break; 1598 1599 GEM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndescs, 1600 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1601 1602 #ifdef GEM_DEBUG /* XXX DMA synchronization? */ 1603 if (ifp->if_flags & IFF_DEBUG) { 1604 printf(" txsoft %p transmit chain:\n", txs); 1605 gem_txsoft_print(sc, txs->txs_firstdesc, 1606 txs->txs_lastdesc); 1607 } 1608 #endif 1609 1610 1611 DPRINTF(sc, ("gem_tint: releasing a desc\n")); 1612 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1613 1614 sc->sc_txfree += txs->txs_ndescs; 1615 1616 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 1617 0, txs->txs_dmamap->dm_mapsize, 1618 BUS_DMASYNC_POSTWRITE); 1619 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 1620 if (txs->txs_mbuf != NULL) { 1621 m_freem(txs->txs_mbuf); 1622 txs->txs_mbuf = NULL; 1623 } 1624 1625 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1626 1627 ifp->if_opackets++; 1628 progress = 1; 1629 } 1630 1631 #if 0 1632 DPRINTF(sc, ("gem_tint: GEM_TX_STATE_MACHINE %x " 1633 "GEM_TX_DATA_PTR %" PRIx64 "GEM_TX_COMPLETION %" PRIx32 "\n", 1634 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_TX_STATE_MACHINE), 1635 ((uint64_t)bus_space_read_4(sc->sc_bustag, sc->sc_h1, 1636 GEM_TX_DATA_PTR_HI) << 32) | 1637 bus_space_read_4(sc->sc_bustag, sc->sc_h1, 1638 GEM_TX_DATA_PTR_LO), 1639 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_TX_COMPLETION))); 1640 #endif 1641 1642 if (progress) { 1643 if (sc->sc_txfree == GEM_NTXDESC - 1) 1644 sc->sc_txwin = 0; 1645 1646 /* Freed some descriptors, so reset IFF_OACTIVE and restart. */ 1647 ifp->if_flags &= ~IFF_OACTIVE; 1648 sc->sc_if_flags = ifp->if_flags; 1649 ifp->if_timer = SIMPLEQ_EMPTY(&sc->sc_txdirtyq) ? 0 : 5; 1650 gem_start(ifp); 1651 } 1652 DPRINTF(sc, ("%s: gem_tint: watchdog %d\n", 1653 sc->sc_dev.dv_xname, ifp->if_timer)); 1654 1655 return (1); 1656 } 1657 1658 /* 1659 * Receive interrupt. 1660 */ 1661 int 1662 gem_rint(sc) 1663 struct gem_softc *sc; 1664 { 1665 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1666 bus_space_tag_t t = sc->sc_bustag; 1667 bus_space_handle_t h = sc->sc_h1; 1668 struct gem_rxsoft *rxs; 1669 struct mbuf *m; 1670 u_int64_t rxstat; 1671 u_int32_t rxcomp; 1672 int i, len, progress = 0; 1673 1674 DPRINTF(sc, ("%s: gem_rint\n", sc->sc_dev.dv_xname)); 1675 1676 /* 1677 * Ignore spurious interrupt that sometimes occurs before 1678 * we are set up when we network boot. 1679 */ 1680 if (!sc->sc_meminited) 1681 return 1; 1682 1683 /* 1684 * Read the completion register once. This limits 1685 * how long the following loop can execute. 1686 */ 1687 rxcomp = bus_space_read_4(t, h, GEM_RX_COMPLETION); 1688 1689 /* 1690 * XXX Read the lastrx only once at the top for speed. 1691 */ 1692 DPRINTF(sc, ("gem_rint: sc->rxptr %d, complete %d\n", 1693 sc->sc_rxptr, rxcomp)); 1694 1695 /* 1696 * Go into the loop at least once. 1697 */ 1698 for (i = sc->sc_rxptr; i == sc->sc_rxptr || i != rxcomp; 1699 i = GEM_NEXTRX(i)) { 1700 rxs = &sc->sc_rxsoft[i]; 1701 1702 GEM_CDRXSYNC(sc, i, 1703 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1704 1705 rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags); 1706 1707 if (rxstat & GEM_RD_OWN) { 1708 GEM_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); 1709 /* 1710 * We have processed all of the receive buffers. 1711 */ 1712 break; 1713 } 1714 1715 progress++; 1716 ifp->if_ipackets++; 1717 1718 if (rxstat & GEM_RD_BAD_CRC) { 1719 ifp->if_ierrors++; 1720 printf("%s: receive error: CRC error\n", 1721 sc->sc_dev.dv_xname); 1722 GEM_INIT_RXDESC(sc, i); 1723 continue; 1724 } 1725 1726 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1727 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1728 #ifdef GEM_DEBUG 1729 if (ifp->if_flags & IFF_DEBUG) { 1730 printf(" rxsoft %p descriptor %d: ", rxs, i); 1731 printf("gd_flags: 0x%016llx\t", (long long) 1732 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags)); 1733 printf("gd_addr: 0x%016llx\n", (long long) 1734 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr)); 1735 } 1736 #endif 1737 1738 /* No errors; receive the packet. */ 1739 len = GEM_RD_BUFLEN(rxstat); 1740 1741 /* 1742 * Allocate a new mbuf cluster. If that fails, we are 1743 * out of memory, and must drop the packet and recycle 1744 * the buffer that's already attached to this descriptor. 1745 */ 1746 m = rxs->rxs_mbuf; 1747 if (gem_add_rxbuf(sc, i) != 0) { 1748 GEM_COUNTER_INCR(sc, sc_ev_rxnobuf); 1749 ifp->if_ierrors++; 1750 GEM_INIT_RXDESC(sc, i); 1751 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1752 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1753 continue; 1754 } 1755 m->m_data += 2; /* We're already off by two */ 1756 1757 m->m_pkthdr.rcvif = ifp; 1758 m->m_pkthdr.len = m->m_len = len; 1759 1760 #if NBPFILTER > 0 1761 /* 1762 * Pass this up to any BPF listeners, but only 1763 * pass it up the stack if it's for us. 1764 */ 1765 if (ifp->if_bpf) 1766 bpf_mtap(ifp->if_bpf, m); 1767 #endif /* NBPFILTER > 0 */ 1768 1769 #ifdef INET 1770 /* hardware checksum */ 1771 if (ifp->if_csum_flags_rx & M_CSUM_TCPv4) { 1772 struct ether_header *eh; 1773 struct ip *ip; 1774 int32_t hlen, pktlen; 1775 1776 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1777 pktlen = m->m_pkthdr.len - ETHER_HDR_LEN - 1778 ETHER_VLAN_ENCAP_LEN; 1779 eh = (struct ether_header *) mtod(m, void *) + 1780 ETHER_VLAN_ENCAP_LEN; 1781 } else { 1782 pktlen = m->m_pkthdr.len - ETHER_HDR_LEN; 1783 eh = mtod(m, struct ether_header *); 1784 } 1785 if (ntohs(eh->ether_type) != ETHERTYPE_IP) 1786 goto swcsum; 1787 ip = (struct ip *) ((char *)eh + ETHER_HDR_LEN); 1788 1789 /* IPv4 only */ 1790 if (ip->ip_v != IPVERSION) 1791 goto swcsum; 1792 1793 hlen = ip->ip_hl << 2; 1794 if (hlen < sizeof(struct ip)) 1795 goto swcsum; 1796 1797 /* 1798 * bail if too short, has random trailing garbage, 1799 * truncated, fragment, or has ethernet pad. 1800 */ 1801 if ((ntohs(ip->ip_len) < hlen) || 1802 (ntohs(ip->ip_len) != pktlen) || 1803 (ntohs(ip->ip_off) & (IP_MF | IP_OFFMASK))) 1804 goto swcsum; 1805 1806 switch (ip->ip_p) { 1807 case IPPROTO_TCP: 1808 if (! (ifp->if_csum_flags_rx & M_CSUM_TCPv4)) 1809 goto swcsum; 1810 if (pktlen < (hlen + sizeof(struct tcphdr))) 1811 goto swcsum; 1812 m->m_pkthdr.csum_flags = M_CSUM_TCPv4; 1813 break; 1814 case IPPROTO_UDP: 1815 /* FALLTHROUGH */ 1816 default: 1817 goto swcsum; 1818 } 1819 1820 /* the uncomplemented sum is expected */ 1821 m->m_pkthdr.csum_data = (~rxstat) & GEM_RD_CHECKSUM; 1822 1823 /* if the pkt had ip options, we have to deduct them */ 1824 if (hlen > sizeof(struct ip)) { 1825 uint16_t *opts; 1826 uint32_t optsum, temp; 1827 1828 optsum = 0; 1829 temp = hlen - sizeof(struct ip); 1830 opts = (uint16_t *) ((char *) ip + 1831 sizeof(struct ip)); 1832 1833 while (temp > 1) { 1834 optsum += ntohs(*opts++); 1835 temp -= 2; 1836 } 1837 while (optsum >> 16) 1838 optsum = (optsum >> 16) + 1839 (optsum & 0xffff); 1840 1841 /* Deduct ip opts sum from hwsum (rfc 1624). */ 1842 m->m_pkthdr.csum_data = 1843 ~((~m->m_pkthdr.csum_data) - ~optsum); 1844 1845 while (m->m_pkthdr.csum_data >> 16) 1846 m->m_pkthdr.csum_data = 1847 (m->m_pkthdr.csum_data >> 16) + 1848 (m->m_pkthdr.csum_data & 1849 0xffff); 1850 } 1851 1852 m->m_pkthdr.csum_flags |= M_CSUM_DATA | 1853 M_CSUM_NO_PSEUDOHDR; 1854 } else 1855 swcsum: 1856 m->m_pkthdr.csum_flags = 0; 1857 #endif 1858 /* Pass it on. */ 1859 (*ifp->if_input)(ifp, m); 1860 } 1861 1862 if (progress) { 1863 /* Update the receive pointer. */ 1864 if (i == sc->sc_rxptr) { 1865 GEM_COUNTER_INCR(sc, sc_ev_rxfull); 1866 #ifdef GEM_DEBUG 1867 if (ifp->if_flags & IFF_DEBUG) 1868 printf("%s: rint: ring wrap\n", 1869 sc->sc_dev.dv_xname); 1870 #endif 1871 } 1872 sc->sc_rxptr = i; 1873 bus_space_write_4(t, h, GEM_RX_KICK, GEM_PREVRX(i)); 1874 } 1875 #ifdef GEM_COUNTERS 1876 if (progress <= 4) { 1877 GEM_COUNTER_INCR(sc, sc_ev_rxhist[progress]); 1878 } else if (progress < 32) { 1879 if (progress < 16) 1880 GEM_COUNTER_INCR(sc, sc_ev_rxhist[5]); 1881 else 1882 GEM_COUNTER_INCR(sc, sc_ev_rxhist[6]); 1883 1884 } else { 1885 if (progress < 64) 1886 GEM_COUNTER_INCR(sc, sc_ev_rxhist[7]); 1887 else 1888 GEM_COUNTER_INCR(sc, sc_ev_rxhist[8]); 1889 } 1890 #endif 1891 1892 DPRINTF(sc, ("gem_rint: done sc->rxptr %d, complete %d\n", 1893 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION))); 1894 1895 return (1); 1896 } 1897 1898 1899 /* 1900 * gem_add_rxbuf: 1901 * 1902 * Add a receive buffer to the indicated descriptor. 1903 */ 1904 int 1905 gem_add_rxbuf(struct gem_softc *sc, int idx) 1906 { 1907 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1908 struct mbuf *m; 1909 int error; 1910 1911 MGETHDR(m, M_DONTWAIT, MT_DATA); 1912 if (m == NULL) 1913 return (ENOBUFS); 1914 1915 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1916 MCLGET(m, M_DONTWAIT); 1917 if ((m->m_flags & M_EXT) == 0) { 1918 m_freem(m); 1919 return (ENOBUFS); 1920 } 1921 1922 #ifdef GEM_DEBUG 1923 /* bzero the packet to check DMA */ 1924 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 1925 #endif 1926 1927 if (rxs->rxs_mbuf != NULL) 1928 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 1929 1930 rxs->rxs_mbuf = m; 1931 1932 error = bus_dmamap_load(sc->sc_dmatag, rxs->rxs_dmamap, 1933 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1934 BUS_DMA_READ|BUS_DMA_NOWAIT); 1935 if (error) { 1936 printf("%s: can't load rx DMA map %d, error = %d\n", 1937 sc->sc_dev.dv_xname, idx, error); 1938 panic("gem_add_rxbuf"); /* XXX */ 1939 } 1940 1941 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1942 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1943 1944 GEM_INIT_RXDESC(sc, idx); 1945 1946 return (0); 1947 } 1948 1949 1950 int 1951 gem_eint(struct gem_softc *sc, u_int status) 1952 { 1953 char bits[128]; 1954 u_int32_t v; 1955 1956 if ((status & GEM_INTR_MIF) != 0) { 1957 printf("%s: XXXlink status changed\n", sc->sc_dev.dv_xname); 1958 return (1); 1959 } 1960 1961 if ((status & GEM_INTR_RX_TAG_ERR) != 0) { 1962 gem_reset_rxdma(sc); 1963 return (1); 1964 } 1965 1966 if (status & GEM_INTR_BERR) { 1967 bus_space_read_4(sc->sc_bustag, sc->sc_h2, GEM_ERROR_STATUS); 1968 v = bus_space_read_4(sc->sc_bustag, sc->sc_h2, 1969 GEM_ERROR_STATUS); 1970 printf("%s: bus error interrupt: 0x%02x\n", 1971 sc->sc_dev.dv_xname, v); 1972 return (1); 1973 } 1974 1975 printf("%s: status=%s\n", sc->sc_dev.dv_xname, 1976 bitmask_snprintf(status, GEM_INTR_BITS, bits, sizeof(bits))); 1977 return (1); 1978 } 1979 1980 1981 /* 1982 * PCS interrupts. 1983 * We should receive these when the link status changes, but sometimes 1984 * we don't receive them for link up. We compensate for this in the 1985 * gem_tick() callout. 1986 */ 1987 int 1988 gem_pint(struct gem_softc *sc) 1989 { 1990 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1991 bus_space_tag_t t = sc->sc_bustag; 1992 bus_space_handle_t h = sc->sc_h1; 1993 u_int32_t v, v2; 1994 1995 /* 1996 * Clear the PCS interrupt from GEM_STATUS. The PCS register is 1997 * latched, so we have to read it twice. There is only one bit in 1998 * use, so the value is meaningless. 1999 */ 2000 bus_space_read_4(t, h, GEM_MII_INTERRUP_STATUS); 2001 bus_space_read_4(t, h, GEM_MII_INTERRUP_STATUS); 2002 2003 if ((ifp->if_flags & IFF_UP) == 0) 2004 return 1; 2005 2006 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) 2007 return 1; 2008 2009 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2010 /* If we see remote fault, our link partner is probably going away */ 2011 if ((v & GEM_MII_STATUS_REM_FLT) != 0) { 2012 gem_bitwait(sc, h, GEM_MII_STATUS, GEM_MII_STATUS_REM_FLT, 0); 2013 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2014 /* Otherwise, we may need to wait after auto-negotiation completes */ 2015 } else if ((v & (GEM_MII_STATUS_LINK_STS | GEM_MII_STATUS_ANEG_CPT)) == 2016 GEM_MII_STATUS_ANEG_CPT) { 2017 gem_bitwait(sc, h, GEM_MII_STATUS, 0, GEM_MII_STATUS_LINK_STS); 2018 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2019 } 2020 if ((v & GEM_MII_STATUS_LINK_STS) != 0) { 2021 if (sc->sc_flags & GEM_LINK) { 2022 return 1; 2023 } 2024 callout_stop(&sc->sc_tick_ch); 2025 v = bus_space_read_4(t, h, GEM_MII_ANAR); 2026 v2 = bus_space_read_4(t, h, GEM_MII_ANLPAR); 2027 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_1000_SX; 2028 sc->sc_mii.mii_media_status = IFM_AVALID | IFM_ACTIVE; 2029 v &= v2; 2030 if (v & GEM_MII_ANEG_FUL_DUPLX) { 2031 sc->sc_mii.mii_media_active |= IFM_FDX; 2032 #ifdef GEM_DEBUG 2033 aprint_debug("%s: link up: full duplex\n", 2034 sc->sc_dev.dv_xname); 2035 #endif 2036 } else if (v & GEM_MII_ANEG_HLF_DUPLX) { 2037 sc->sc_mii.mii_media_active |= IFM_HDX; 2038 #ifdef GEM_DEBUG 2039 aprint_debug("%s: link up: half duplex\n", 2040 sc->sc_dev.dv_xname); 2041 #endif 2042 } else { 2043 #ifdef GEM_DEBUG 2044 aprint_debug("%s: duplex mismatch\n", 2045 sc->sc_dev.dv_xname); 2046 #endif 2047 } 2048 gem_statuschange(sc); 2049 } else { 2050 if ((sc->sc_flags & GEM_LINK) == 0) { 2051 return 1; 2052 } 2053 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_NONE; 2054 sc->sc_mii.mii_media_status = IFM_AVALID; 2055 #ifdef GEM_DEBUG 2056 aprint_debug("%s: link down\n", 2057 sc->sc_dev.dv_xname); 2058 #endif 2059 gem_statuschange(sc); 2060 2061 /* Start the 10 second timer */ 2062 callout_reset(&sc->sc_tick_ch, hz * 10, gem_tick, sc); 2063 } 2064 return 1; 2065 } 2066 2067 2068 2069 int 2070 gem_intr(v) 2071 void *v; 2072 { 2073 struct gem_softc *sc = (struct gem_softc *)v; 2074 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2075 bus_space_tag_t t = sc->sc_bustag; 2076 bus_space_handle_t h = sc->sc_h1; 2077 u_int32_t status; 2078 int r = 0; 2079 #ifdef GEM_DEBUG 2080 char bits[128]; 2081 #endif 2082 2083 /* XXX We should probably mask out interrupts until we're done */ 2084 2085 sc->sc_ev_intr.ev_count++; 2086 2087 status = bus_space_read_4(t, h, GEM_STATUS); 2088 DPRINTF(sc, ("%s: gem_intr: cplt 0x%x status %s\n", 2089 sc->sc_dev.dv_xname, (status >> 19), 2090 bitmask_snprintf(status, GEM_INTR_BITS, bits, sizeof(bits)))); 2091 2092 if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0) 2093 r |= gem_eint(sc, status); 2094 2095 /* We don't bother with GEM_INTR_TX_DONE */ 2096 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) { 2097 GEM_COUNTER_INCR(sc, sc_ev_txint); 2098 r |= gem_tint(sc); 2099 } 2100 2101 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) { 2102 GEM_COUNTER_INCR(sc, sc_ev_rxint); 2103 r |= gem_rint(sc); 2104 } 2105 2106 /* We should eventually do more than just print out error stats. */ 2107 if (status & GEM_INTR_TX_MAC) { 2108 int txstat = bus_space_read_4(t, h, GEM_MAC_TX_STATUS); 2109 if (txstat & ~GEM_MAC_TX_XMIT_DONE) 2110 printf("%s: MAC tx fault, status %x\n", 2111 sc->sc_dev.dv_xname, txstat); 2112 if (txstat & (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG)) 2113 gem_init(ifp); 2114 } 2115 if (status & GEM_INTR_RX_MAC) { 2116 int rxstat = bus_space_read_4(t, h, GEM_MAC_RX_STATUS); 2117 if (rxstat & ~GEM_MAC_RX_DONE) 2118 printf("%s: MAC rx fault, status %x\n", 2119 sc->sc_dev.dv_xname, rxstat); 2120 /* 2121 * At least with GEM_SUN_GEM and some GEM_SUN_ERI 2122 * revisions GEM_MAC_RX_OVERFLOW happen often due to a 2123 * silicon bug so handle them silently. Moreover, it's 2124 * likely that the receiver has hung so we reset it. 2125 */ 2126 if (rxstat & GEM_MAC_RX_OVERFLOW) { 2127 ifp->if_ierrors++; 2128 gem_reset_rxdma(sc); 2129 } else if (rxstat & ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT)) 2130 printf("%s: MAC rx fault, status %x\n", 2131 sc->sc_dev.dv_xname, rxstat); 2132 } 2133 if (status & GEM_INTR_PCS) { 2134 r |= gem_pint(sc); 2135 } 2136 2137 /* Do we need to do anything with these? 2138 if ((status & GEM_MAC_CONTROL_STATUS) != 0) { 2139 status2 = bus_read_4(sc->sc_res[0], GEM_MAC_CONTROL_STATUS); 2140 if ((status2 & GEM_MAC_PAUSED) != 0) 2141 aprintf_debug("%s: PAUSE received (%d slots)\n", 2142 GEM_MAC_PAUSE_TIME(status2), sc->sc_dev.dv_xname); 2143 if ((status2 & GEM_MAC_PAUSE) != 0) 2144 aprintf_debug("%s: transited to PAUSE state\n", 2145 sc->sc_dev.dv_xname); 2146 if ((status2 & GEM_MAC_RESUME) != 0) 2147 aprintf_debug("%s: transited to non-PAUSE state\n", 2148 sc->sc_dev.dv_xname); 2149 } 2150 if ((status & GEM_INTR_MIF) != 0) 2151 aprintf_debug("%s: MIF interrupt\n", sc->sc_dev.dv_xname); 2152 */ 2153 #if NRND > 0 2154 rnd_add_uint32(&sc->rnd_source, status); 2155 #endif 2156 return (r); 2157 } 2158 2159 2160 void 2161 gem_watchdog(ifp) 2162 struct ifnet *ifp; 2163 { 2164 struct gem_softc *sc = ifp->if_softc; 2165 2166 DPRINTF(sc, ("gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x " 2167 "GEM_MAC_RX_CONFIG %x\n", 2168 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_RX_CONFIG), 2169 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_MAC_RX_STATUS), 2170 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_MAC_RX_CONFIG))); 2171 2172 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 2173 ++ifp->if_oerrors; 2174 2175 /* Try to get more packets going. */ 2176 gem_start(ifp); 2177 } 2178 2179 /* 2180 * Initialize the MII Management Interface 2181 */ 2182 void 2183 gem_mifinit(sc) 2184 struct gem_softc *sc; 2185 { 2186 bus_space_tag_t t = sc->sc_bustag; 2187 bus_space_handle_t mif = sc->sc_h1; 2188 2189 /* Configure the MIF in frame mode */ 2190 sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 2191 sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA; 2192 bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config); 2193 } 2194 2195 /* 2196 * MII interface 2197 * 2198 * The GEM MII interface supports at least three different operating modes: 2199 * 2200 * Bitbang mode is implemented using data, clock and output enable registers. 2201 * 2202 * Frame mode is implemented by loading a complete frame into the frame 2203 * register and polling the valid bit for completion. 2204 * 2205 * Polling mode uses the frame register but completion is indicated by 2206 * an interrupt. 2207 * 2208 */ 2209 static int 2210 gem_mii_readreg(self, phy, reg) 2211 struct device *self; 2212 int phy, reg; 2213 { 2214 struct gem_softc *sc = (void *)self; 2215 bus_space_tag_t t = sc->sc_bustag; 2216 bus_space_handle_t mif = sc->sc_h1; 2217 int n; 2218 u_int32_t v; 2219 2220 #ifdef GEM_DEBUG1 2221 if (sc->sc_debug) 2222 printf("gem_mii_readreg: PHY %d reg %d\n", phy, reg); 2223 #endif 2224 2225 /* Construct the frame command */ 2226 v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) | 2227 GEM_MIF_FRAME_READ; 2228 2229 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 2230 for (n = 0; n < 100; n++) { 2231 DELAY(1); 2232 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 2233 if (v & GEM_MIF_FRAME_TA0) 2234 return (v & GEM_MIF_FRAME_DATA); 2235 } 2236 2237 printf("%s: mii_read timeout\n", sc->sc_dev.dv_xname); 2238 return (0); 2239 } 2240 2241 static void 2242 gem_mii_writereg(self, phy, reg, val) 2243 struct device *self; 2244 int phy, reg, val; 2245 { 2246 struct gem_softc *sc = (void *)self; 2247 bus_space_tag_t t = sc->sc_bustag; 2248 bus_space_handle_t mif = sc->sc_h1; 2249 int n; 2250 u_int32_t v; 2251 2252 #ifdef GEM_DEBUG1 2253 if (sc->sc_debug) 2254 printf("gem_mii_writereg: PHY %d reg %d val %x\n", 2255 phy, reg, val); 2256 #endif 2257 2258 /* Construct the frame command */ 2259 v = GEM_MIF_FRAME_WRITE | 2260 (phy << GEM_MIF_PHY_SHIFT) | 2261 (reg << GEM_MIF_REG_SHIFT) | 2262 (val & GEM_MIF_FRAME_DATA); 2263 2264 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 2265 for (n = 0; n < 100; n++) { 2266 DELAY(1); 2267 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 2268 if (v & GEM_MIF_FRAME_TA0) 2269 return; 2270 } 2271 2272 printf("%s: mii_write timeout\n", sc->sc_dev.dv_xname); 2273 } 2274 2275 static void 2276 gem_mii_statchg(dev) 2277 struct device *dev; 2278 { 2279 struct gem_softc *sc = (void *)dev; 2280 #ifdef GEM_DEBUG 2281 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 2282 #endif 2283 2284 #ifdef GEM_DEBUG 2285 if (sc->sc_debug) 2286 printf("gem_mii_statchg: status change: phy = %d\n", 2287 sc->sc_phys[instance]); 2288 #endif 2289 gem_statuschange(sc); 2290 } 2291 2292 /* 2293 * Common status change for gem_mii_statchg() and gem_pint() 2294 */ 2295 void 2296 gem_statuschange(struct gem_softc* sc) 2297 { 2298 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2299 bus_space_tag_t t = sc->sc_bustag; 2300 bus_space_handle_t mac = sc->sc_h1; 2301 int gigabit; 2302 u_int32_t rxcfg, txcfg, v; 2303 2304 if ((sc->sc_mii.mii_media_status & IFM_ACTIVE) != 0 && 2305 IFM_SUBTYPE(sc->sc_mii.mii_media_active) != IFM_NONE) 2306 sc->sc_flags |= GEM_LINK; 2307 else 2308 sc->sc_flags &= ~GEM_LINK; 2309 2310 switch (IFM_SUBTYPE(sc->sc_mii.mii_media_active)) { 2311 case IFM_1000_SX: 2312 case IFM_1000_LX: 2313 case IFM_1000_CX: 2314 case IFM_1000_T: 2315 gigabit = 1; 2316 break; 2317 default: 2318 gigabit = 0; 2319 } 2320 2321 /* 2322 * The configuration done here corresponds to the steps F) and 2323 * G) and as far as enabling of RX and TX MAC goes also step H) 2324 * of the initialization sequence outlined in section 3.2.1 of 2325 * the GEM Gigabit Ethernet ASIC Specification. 2326 */ 2327 2328 rxcfg = bus_space_read_4(t, mac, GEM_MAC_RX_CONFIG); 2329 rxcfg &= ~(GEM_MAC_RX_CARR_EXTEND | GEM_MAC_RX_ENABLE); 2330 txcfg = GEM_MAC_TX_ENA_IPG0 | GEM_MAC_TX_NGU | GEM_MAC_TX_NGU_LIMIT; 2331 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 2332 txcfg |= GEM_MAC_TX_IGN_CARRIER | GEM_MAC_TX_IGN_COLLIS; 2333 else if (gigabit) { 2334 rxcfg |= GEM_MAC_RX_CARR_EXTEND; 2335 txcfg |= GEM_MAC_RX_CARR_EXTEND; 2336 } 2337 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0); 2338 bus_space_barrier(t, mac, GEM_MAC_TX_CONFIG, 4, 2339 BUS_SPACE_BARRIER_WRITE); 2340 if (!gem_bitwait(sc, mac, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)) 2341 aprint_normal("%s: cannot disable TX MAC\n", 2342 sc->sc_dev.dv_xname); 2343 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, txcfg); 2344 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, 0); 2345 bus_space_barrier(t, mac, GEM_MAC_RX_CONFIG, 4, 2346 BUS_SPACE_BARRIER_WRITE); 2347 if (!gem_bitwait(sc, mac, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)) 2348 aprint_normal("%s: cannot disable RX MAC\n", 2349 sc->sc_dev.dv_xname); 2350 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, rxcfg); 2351 2352 v = bus_space_read_4(t, mac, GEM_MAC_CONTROL_CONFIG) & 2353 ~(GEM_MAC_CC_RX_PAUSE | GEM_MAC_CC_TX_PAUSE); 2354 bus_space_write_4(t, mac, GEM_MAC_CONTROL_CONFIG, v); 2355 2356 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) == 0 && 2357 gigabit != 0) 2358 bus_space_write_4(t, mac, GEM_MAC_SLOT_TIME, 2359 GEM_MAC_SLOT_TIME_CARR_EXTEND); 2360 else 2361 bus_space_write_4(t, mac, GEM_MAC_SLOT_TIME, 2362 GEM_MAC_SLOT_TIME_NORMAL); 2363 2364 /* XIF Configuration */ 2365 if (sc->sc_flags & GEM_LINK) 2366 v = GEM_MAC_XIF_LINK_LED; 2367 else 2368 v = 0; 2369 v |= GEM_MAC_XIF_TX_MII_ENA; 2370 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) == 0) { 2371 /* MII/GMII needs echo disable if half duplex. */ 2372 if ((sc->sc_flags &(GEM_SERDES | GEM_SERIAL)) == 0) 2373 v |= GEM_MAC_XIF_ECHO_DISABL; 2374 v &= ~GEM_MAC_XIF_FDPLX_LED; 2375 } else { 2376 v |= GEM_MAC_XIF_MII_BUF_ENA; 2377 v |= GEM_MAC_XIF_FDPLX_LED; 2378 } 2379 if (gigabit != 0) 2380 v |= GEM_MAC_XIF_GMII_MODE; 2381 if ((ifp->if_flags & IFF_RUNNING) != 0 && 2382 (sc->sc_flags & GEM_LINK) != 0) { 2383 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 2384 txcfg | GEM_MAC_TX_ENABLE); 2385 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, 2386 rxcfg | GEM_MAC_RX_ENABLE); 2387 } 2388 } 2389 2390 int 2391 gem_ser_mediachange(struct ifnet *ifp) 2392 { 2393 struct gem_softc *sc = ifp->if_softc; 2394 u_int s, t; 2395 2396 if (IFM_TYPE(sc->sc_mii.mii_media.ifm_media) != IFM_ETHER) 2397 return EINVAL; 2398 2399 s = IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media); 2400 if (s == IFM_AUTO) { 2401 if (sc->sc_mii_media != s) { 2402 #ifdef GEM_DEBUG 2403 aprint_debug("%s: setting media to auto\n", 2404 sc->sc_dev.dv_xname); 2405 #endif 2406 sc->sc_mii_media = s; 2407 if (ifp->if_flags & IFF_UP) { 2408 gem_pcs_stop(sc, 0); 2409 gem_pcs_start(sc); 2410 } 2411 } 2412 return 0; 2413 } 2414 if (s == IFM_1000_SX) { 2415 t = IFM_OPTIONS(sc->sc_mii.mii_media.ifm_media); 2416 if (t == IFM_FDX || t == IFM_HDX) { 2417 if (sc->sc_mii_media != t) { 2418 sc->sc_mii_media = t; 2419 #ifdef GEM_DEBUG 2420 aprint_debug("%s:" 2421 " setting media to 1000baseSX-%s\n", 2422 sc->sc_dev.dv_xname, 2423 t == IFM_FDX ? "FDX" : "HDX"); 2424 #endif 2425 if (ifp->if_flags & IFF_UP) { 2426 gem_pcs_stop(sc, 0); 2427 gem_pcs_start(sc); 2428 } 2429 } 2430 return 0; 2431 } 2432 } 2433 return EINVAL; 2434 } 2435 2436 void 2437 gem_ser_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2438 { 2439 struct gem_softc *sc = ifp->if_softc; 2440 2441 if ((ifp->if_flags & IFF_UP) == 0) 2442 return; 2443 ifmr->ifm_active = sc->sc_mii.mii_media_active; 2444 ifmr->ifm_status = sc->sc_mii.mii_media_status; 2445 } 2446 2447 /* 2448 * Process an ioctl request. 2449 */ 2450 int 2451 gem_ioctl(ifp, cmd, data) 2452 struct ifnet *ifp; 2453 u_long cmd; 2454 void *data; 2455 { 2456 struct gem_softc *sc = ifp->if_softc; 2457 int s, error = 0; 2458 2459 s = splnet(); 2460 2461 switch (cmd) { 2462 case SIOCSIFFLAGS: 2463 #define RESETIGN (IFF_CANTCHANGE|IFF_DEBUG) 2464 if (((ifp->if_flags & (IFF_UP|IFF_RUNNING)) 2465 == (IFF_UP|IFF_RUNNING)) 2466 && ((ifp->if_flags & (~RESETIGN)) 2467 == (sc->sc_if_flags & (~RESETIGN)))) { 2468 gem_setladrf(sc); 2469 break; 2470 } 2471 #undef RESETIGN 2472 /*FALLTHROUGH*/ 2473 default: 2474 error = ether_ioctl(ifp, cmd, data); 2475 if (error == ENETRESET) { 2476 /* 2477 * Multicast list has changed; set the hardware filter 2478 * accordingly. 2479 */ 2480 if (ifp->if_flags & IFF_RUNNING) 2481 gem_setladrf(sc); 2482 error = 0; 2483 } 2484 break; 2485 } 2486 2487 /* Try to get things going again */ 2488 if (ifp->if_flags & IFF_UP) 2489 gem_start(ifp); 2490 splx(s); 2491 return (error); 2492 } 2493 2494 2495 void 2496 gem_shutdown(arg) 2497 void *arg; 2498 { 2499 struct gem_softc *sc = (struct gem_softc *)arg; 2500 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2501 2502 gem_stop(ifp, 1); 2503 } 2504 2505 /* 2506 * Set up the logical address filter. 2507 */ 2508 void 2509 gem_setladrf(sc) 2510 struct gem_softc *sc; 2511 { 2512 struct ethercom *ec = &sc->sc_ethercom; 2513 struct ifnet *ifp = &ec->ec_if; 2514 struct ether_multi *enm; 2515 struct ether_multistep step; 2516 bus_space_tag_t t = sc->sc_bustag; 2517 bus_space_handle_t h = sc->sc_h1; 2518 u_int32_t crc; 2519 u_int32_t hash[16]; 2520 u_int32_t v; 2521 int i; 2522 2523 /* Get current RX configuration */ 2524 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 2525 2526 /* 2527 * Turn off promiscuous mode, promiscuous group mode (all multicast), 2528 * and hash filter. Depending on the case, the right bit will be 2529 * enabled. 2530 */ 2531 v &= ~(GEM_MAC_RX_PROMISCUOUS|GEM_MAC_RX_HASH_FILTER| 2532 GEM_MAC_RX_PROMISC_GRP); 2533 2534 if ((ifp->if_flags & IFF_PROMISC) != 0) { 2535 /* Turn on promiscuous mode */ 2536 v |= GEM_MAC_RX_PROMISCUOUS; 2537 ifp->if_flags |= IFF_ALLMULTI; 2538 goto chipit; 2539 } 2540 2541 /* 2542 * Set up multicast address filter by passing all multicast addresses 2543 * through a crc generator, and then using the high order 8 bits as an 2544 * index into the 256 bit logical address filter. The high order 4 2545 * bits selects the word, while the other 4 bits select the bit within 2546 * the word (where bit 0 is the MSB). 2547 */ 2548 2549 /* Clear hash table */ 2550 memset(hash, 0, sizeof(hash)); 2551 2552 ETHER_FIRST_MULTI(step, ec, enm); 2553 while (enm != NULL) { 2554 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2555 /* 2556 * We must listen to a range of multicast addresses. 2557 * For now, just accept all multicasts, rather than 2558 * trying to set only those filter bits needed to match 2559 * the range. (At this time, the only use of address 2560 * ranges is for IP multicast routing, for which the 2561 * range is big enough to require all bits set.) 2562 * XXX should use the address filters for this 2563 */ 2564 ifp->if_flags |= IFF_ALLMULTI; 2565 v |= GEM_MAC_RX_PROMISC_GRP; 2566 goto chipit; 2567 } 2568 2569 /* Get the LE CRC32 of the address */ 2570 crc = ether_crc32_le(enm->enm_addrlo, sizeof(enm->enm_addrlo)); 2571 2572 /* Just want the 8 most significant bits. */ 2573 crc >>= 24; 2574 2575 /* Set the corresponding bit in the filter. */ 2576 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 2577 2578 ETHER_NEXT_MULTI(step, enm); 2579 } 2580 2581 v |= GEM_MAC_RX_HASH_FILTER; 2582 ifp->if_flags &= ~IFF_ALLMULTI; 2583 2584 /* Now load the hash table into the chip (if we are using it) */ 2585 for (i = 0; i < 16; i++) { 2586 bus_space_write_4(t, h, 2587 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1-GEM_MAC_HASH0), 2588 hash[i]); 2589 } 2590 2591 chipit: 2592 sc->sc_if_flags = ifp->if_flags; 2593 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 2594 } 2595 2596 #if notyet 2597 2598 /* 2599 * gem_power: 2600 * 2601 * Power management (suspend/resume) hook. 2602 */ 2603 void 2604 gem_power(why, arg) 2605 int why; 2606 void *arg; 2607 { 2608 struct gem_softc *sc = arg; 2609 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2610 int s; 2611 2612 s = splnet(); 2613 switch (why) { 2614 case PWR_SUSPEND: 2615 case PWR_STANDBY: 2616 gem_stop(ifp, 1); 2617 if (sc->sc_power != NULL) 2618 (*sc->sc_power)(sc, why); 2619 break; 2620 case PWR_RESUME: 2621 if (ifp->if_flags & IFF_UP) { 2622 if (sc->sc_power != NULL) 2623 (*sc->sc_power)(sc, why); 2624 gem_init(ifp); 2625 } 2626 break; 2627 case PWR_SOFTSUSPEND: 2628 case PWR_SOFTSTANDBY: 2629 case PWR_SOFTRESUME: 2630 break; 2631 } 2632 splx(s); 2633 } 2634 #endif 2635
Indexes created Mon Sep 22 13:09:51 GMT 2025