gem.c revision 1.70
1 /* $NetBSD: gem.c,v 1.70 2008/01/20 15:12:33 jdc Exp $ */ 2 3 /* 4 * 5 * Copyright (C) 2001 Eduardo Horvath. 6 * Copyright (c) 2001-2003 Thomas Moestl 7 * All rights reserved. 8 * 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 */ 32 33 /* 34 * Driver for Apple GMAC, Sun ERI and Sun GEM Ethernet controllers 35 * See `GEM Gigabit Ethernet ASIC Specification' 36 * http://www.sun.com/processors/manuals/ge.pdf 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: gem.c,v 1.70 2008/01/20 15:12:33 jdc Exp $"); 41 42 #include "opt_inet.h" 43 #include "bpfilter.h" 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/callout.h> 48 #include <sys/mbuf.h> 49 #include <sys/syslog.h> 50 #include <sys/malloc.h> 51 #include <sys/kernel.h> 52 #include <sys/socket.h> 53 #include <sys/ioctl.h> 54 #include <sys/errno.h> 55 #include <sys/device.h> 56 57 #include <machine/endian.h> 58 59 #include <uvm/uvm_extern.h> 60 61 #include <net/if.h> 62 #include <net/if_dl.h> 63 #include <net/if_media.h> 64 #include <net/if_ether.h> 65 66 #ifdef INET 67 #include <netinet/in.h> 68 #include <netinet/in_systm.h> 69 #include <netinet/in_var.h> 70 #include <netinet/ip.h> 71 #include <netinet/tcp.h> 72 #include <netinet/udp.h> 73 #endif 74 75 #if NBPFILTER > 0 76 #include <net/bpf.h> 77 #endif 78 79 #include <sys/bus.h> 80 #include <sys/intr.h> 81 82 #include <dev/mii/mii.h> 83 #include <dev/mii/miivar.h> 84 #include <dev/mii/mii_bitbang.h> 85 86 #include <dev/ic/gemreg.h> 87 #include <dev/ic/gemvar.h> 88 89 #define TRIES 10000 90 91 static void gem_start(struct ifnet *); 92 static void gem_stop(struct ifnet *, int); 93 int gem_ioctl(struct ifnet *, u_long, void *); 94 void gem_tick(void *); 95 void gem_watchdog(struct ifnet *); 96 void gem_shutdown(void *); 97 void gem_pcs_start(struct gem_softc *sc); 98 void gem_pcs_stop(struct gem_softc *sc, int); 99 int gem_init(struct ifnet *); 100 void gem_init_regs(struct gem_softc *sc); 101 static int gem_ringsize(int sz); 102 static int gem_meminit(struct gem_softc *); 103 void gem_mifinit(struct gem_softc *); 104 static int gem_bitwait(struct gem_softc *sc, bus_space_handle_t, int, 105 u_int32_t, u_int32_t); 106 void gem_reset(struct gem_softc *); 107 int gem_reset_rx(struct gem_softc *sc); 108 static void gem_reset_rxdma(struct gem_softc *sc); 109 static void gem_rx_common(struct gem_softc *sc); 110 int gem_reset_tx(struct gem_softc *sc); 111 int gem_disable_rx(struct gem_softc *sc); 112 int gem_disable_tx(struct gem_softc *sc); 113 static void gem_rxdrain(struct gem_softc *sc); 114 int gem_add_rxbuf(struct gem_softc *sc, int idx); 115 void gem_setladrf(struct gem_softc *); 116 117 /* MII methods & callbacks */ 118 static int gem_mii_readreg(struct device *, int, int); 119 static void gem_mii_writereg(struct device *, int, int, int); 120 static void gem_mii_statchg(struct device *); 121 122 void gem_statuschange(struct gem_softc *); 123 124 int gem_ser_mediachange(struct ifnet *); 125 void gem_ser_mediastatus(struct ifnet *, struct ifmediareq *); 126 127 struct mbuf *gem_get(struct gem_softc *, int, int); 128 int gem_put(struct gem_softc *, int, struct mbuf *); 129 void gem_read(struct gem_softc *, int, int); 130 int gem_pint(struct gem_softc *); 131 int gem_eint(struct gem_softc *, u_int); 132 int gem_rint(struct gem_softc *); 133 int gem_tint(struct gem_softc *); 134 void gem_power(int, void *); 135 136 #ifdef GEM_DEBUG 137 static void gem_txsoft_print(const struct gem_softc *, int, int); 138 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 139 printf x 140 #else 141 #define DPRINTF(sc, x) /* nothing */ 142 #endif 143 144 #define ETHER_MIN_TX (ETHERMIN + sizeof(struct ether_header)) 145 146 147 /* 148 * gem_attach: 149 * 150 * Attach a Gem interface to the system. 151 */ 152 void 153 gem_attach(sc, enaddr) 154 struct gem_softc *sc; 155 const uint8_t *enaddr; 156 { 157 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 158 struct mii_data *mii = &sc->sc_mii; 159 bus_space_tag_t t = sc->sc_bustag; 160 bus_space_handle_t h = sc->sc_h1; 161 struct ifmedia_entry *ifm; 162 int i, error; 163 u_int32_t v; 164 char *nullbuf; 165 166 /* Make sure the chip is stopped. */ 167 ifp->if_softc = sc; 168 gem_reset(sc); 169 170 /* 171 * Allocate the control data structures, and create and load the 172 * DMA map for it. gem_control_data is 9216 bytes, we have space for 173 * the padding buffer in the bus_dmamem_alloc()'d memory. 174 */ 175 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 176 sizeof(struct gem_control_data) + ETHER_MIN_TX, PAGE_SIZE, 177 0, &sc->sc_cdseg, 1, &sc->sc_cdnseg, 0)) != 0) { 178 aprint_error( 179 "%s: unable to allocate control data, error = %d\n", 180 sc->sc_dev.dv_xname, error); 181 goto fail_0; 182 } 183 184 /* XXX should map this in with correct endianness */ 185 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg, 186 sizeof(struct gem_control_data), (void **)&sc->sc_control_data, 187 BUS_DMA_COHERENT)) != 0) { 188 aprint_error("%s: unable to map control data, error = %d\n", 189 sc->sc_dev.dv_xname, error); 190 goto fail_1; 191 } 192 193 nullbuf = 194 (char *)sc->sc_control_data + sizeof(struct gem_control_data); 195 196 if ((error = bus_dmamap_create(sc->sc_dmatag, 197 sizeof(struct gem_control_data), 1, 198 sizeof(struct gem_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 199 aprint_error("%s: unable to create control data DMA map, " 200 "error = %d\n", sc->sc_dev.dv_xname, error); 201 goto fail_2; 202 } 203 204 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 205 sc->sc_control_data, sizeof(struct gem_control_data), NULL, 206 0)) != 0) { 207 aprint_error( 208 "%s: unable to load control data DMA map, error = %d\n", 209 sc->sc_dev.dv_xname, error); 210 goto fail_3; 211 } 212 213 memset(nullbuf, 0, ETHER_MIN_TX); 214 if ((error = bus_dmamap_create(sc->sc_dmatag, 215 ETHER_MIN_TX, 1, ETHER_MIN_TX, 0, 0, &sc->sc_nulldmamap)) != 0) { 216 aprint_error("%s: unable to create padding DMA map, " 217 "error = %d\n", sc->sc_dev.dv_xname, error); 218 goto fail_4; 219 } 220 221 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_nulldmamap, 222 nullbuf, ETHER_MIN_TX, NULL, 0)) != 0) { 223 aprint_error( 224 "%s: unable to load padding DMA map, error = %d\n", 225 sc->sc_dev.dv_xname, error); 226 goto fail_5; 227 } 228 229 bus_dmamap_sync(sc->sc_dmatag, sc->sc_nulldmamap, 0, ETHER_MIN_TX, 230 BUS_DMASYNC_PREWRITE); 231 232 /* 233 * Initialize the transmit job descriptors. 234 */ 235 SIMPLEQ_INIT(&sc->sc_txfreeq); 236 SIMPLEQ_INIT(&sc->sc_txdirtyq); 237 238 /* 239 * Create the transmit buffer DMA maps. 240 */ 241 for (i = 0; i < GEM_TXQUEUELEN; i++) { 242 struct gem_txsoft *txs; 243 244 txs = &sc->sc_txsoft[i]; 245 txs->txs_mbuf = NULL; 246 if ((error = bus_dmamap_create(sc->sc_dmatag, 247 ETHER_MAX_LEN_JUMBO, GEM_NTXSEGS, 248 ETHER_MAX_LEN_JUMBO, 0, 0, 249 &txs->txs_dmamap)) != 0) { 250 aprint_error("%s: unable to create tx DMA map %d, " 251 "error = %d\n", sc->sc_dev.dv_xname, i, error); 252 goto fail_6; 253 } 254 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 255 } 256 257 /* 258 * Create the receive buffer DMA maps. 259 */ 260 for (i = 0; i < GEM_NRXDESC; i++) { 261 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, 262 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 263 aprint_error("%s: unable to create rx DMA map %d, " 264 "error = %d\n", sc->sc_dev.dv_xname, i, error); 265 goto fail_7; 266 } 267 sc->sc_rxsoft[i].rxs_mbuf = NULL; 268 } 269 270 /* Initialize ifmedia structures and MII info */ 271 mii->mii_ifp = ifp; 272 mii->mii_readreg = gem_mii_readreg; 273 mii->mii_writereg = gem_mii_writereg; 274 mii->mii_statchg = gem_mii_statchg; 275 276 sc->sc_ethercom.ec_mii = mii; 277 278 /* 279 * Initialization based on `GEM Gigabit Ethernet ASIC Specification' 280 * Section 3.2.1 `Initialization Sequence'. 281 * However, we can't assume SERDES or Serialink if neither 282 * GEM_MIF_CONFIG_MDI0 nor GEM_MIF_CONFIG_MDI1 are set 283 * being set, as both are set on Sun X1141A (with SERDES). So, 284 * we rely on our bus attachment setting GEM_SERDES or GEM_SERIAL. 285 * Also, for Apple variants with 2 PHY's, we prefer the external 286 * PHY over the internal PHY. 287 */ 288 gem_mifinit(sc); 289 290 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) { 291 ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange, 292 ether_mediastatus); 293 mii_attach(&sc->sc_dev, mii, 0xffffffff, 294 MII_PHY_ANY, MII_OFFSET_ANY, MIIF_FORCEANEG); 295 if (LIST_EMPTY(&mii->mii_phys)) { 296 /* No PHY attached */ 297 aprint_error("%s: PHY probe failed\n", 298 sc->sc_dev.dv_xname); 299 goto fail_7; 300 } else { 301 struct mii_softc *child; 302 303 /* 304 * Walk along the list of attached MII devices and 305 * establish an `MII instance' to `PHY number' 306 * mapping. 307 */ 308 LIST_FOREACH(child, &mii->mii_phys, mii_list) { 309 /* 310 * Note: we support just one PHY: the internal 311 * or external MII is already selected for us 312 * by the GEM_MIF_CONFIG register. 313 */ 314 if (child->mii_phy > 1 || child->mii_inst > 0) { 315 aprint_error( 316 "%s: cannot accommodate MII device" 317 " %s at PHY %d, instance %d\n", 318 sc->sc_dev.dv_xname, 319 child->mii_dev.dv_xname, 320 child->mii_phy, child->mii_inst); 321 continue; 322 } 323 sc->sc_phys[child->mii_inst] = child->mii_phy; 324 } 325 326 /* 327 * Now select and activate the PHY we will use. 328 * 329 * The order of preference is External (MDI1), 330 * then Internal (MDI0), 331 */ 332 if (sc->sc_phys[1]) { 333 #ifdef GEM_DEBUG 334 aprint_debug("%s: using external PHY\n", 335 sc->sc_dev.dv_xname); 336 #endif 337 sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL; 338 } else { 339 #ifdef GEM_DEBUG 340 aprint_debug("%s: using internal PHY\n", 341 sc->sc_dev.dv_xname); 342 sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL; 343 #endif 344 } 345 bus_space_write_4(t, h, GEM_MIF_CONFIG, 346 sc->sc_mif_config); 347 if (sc->sc_variant != GEM_SUN_ERI) 348 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 349 GEM_MII_DATAPATH_MII); 350 351 /* 352 * XXX - we can really do the following ONLY if the 353 * PHY indeed has the auto negotiation capability!! 354 */ 355 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 356 } 357 } else { 358 ifmedia_init(&mii->mii_media, IFM_IMASK, gem_ser_mediachange, 359 gem_ser_mediastatus); 360 /* SERDES or Serialink */ 361 if (sc->sc_flags & GEM_SERDES) { 362 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 363 GEM_MII_DATAPATH_SERDES); 364 } else { 365 sc->sc_flags |= GEM_SERIAL; 366 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 367 GEM_MII_DATAPATH_SERIAL); 368 } 369 370 aprint_normal("%s: using external PCS %s: ", 371 sc->sc_dev.dv_xname, 372 sc->sc_flags & GEM_SERDES ? "SERDES" : "Serialink"); 373 374 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO, 0, NULL); 375 /* Check for FDX and HDX capabilities */ 376 sc->sc_mii_anar = bus_space_read_4(t, h, GEM_MII_ANAR); 377 if (sc->sc_mii_anar & GEM_MII_ANEG_FUL_DUPLX) { 378 ifmedia_add(&sc->sc_mii.mii_media, 379 IFM_ETHER|IFM_1000_SX|IFM_MANUAL|IFM_FDX, 0, NULL); 380 aprint_normal("1000baseSX-FDX, "); 381 } 382 if (sc->sc_mii_anar & GEM_MII_ANEG_HLF_DUPLX) { 383 ifmedia_add(&sc->sc_mii.mii_media, 384 IFM_ETHER|IFM_1000_SX|IFM_MANUAL|IFM_HDX, 0, NULL); 385 aprint_normal("1000baseSX-HDX, "); 386 } 387 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 388 sc->sc_mii_media = IFM_AUTO; 389 aprint_normal("auto\n"); 390 391 gem_pcs_stop(sc, 1); 392 } 393 394 /* 395 * From this point forward, the attachment cannot fail. A failure 396 * before this point releases all resources that may have been 397 * allocated. 398 */ 399 400 /* Announce ourselves. */ 401 aprint_normal("%s: Ethernet address %s", sc->sc_dev.dv_xname, 402 ether_sprintf(enaddr)); 403 404 /* Get RX FIFO size */ 405 sc->sc_rxfifosize = 64 * 406 bus_space_read_4(t, h, GEM_RX_FIFO_SIZE); 407 aprint_normal(", %uKB RX fifo", sc->sc_rxfifosize / 1024); 408 409 /* Get TX FIFO size */ 410 v = bus_space_read_4(t, h, GEM_TX_FIFO_SIZE); 411 aprint_normal(", %uKB TX fifo\n", v / 16); 412 413 /* Initialize ifnet structure. */ 414 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 415 ifp->if_softc = sc; 416 ifp->if_flags = 417 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 418 sc->sc_if_flags = ifp->if_flags; 419 /* The GEM hardware supports basic TCP checksum offloading only. */ 420 ifp->if_capabilities |= 421 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx; 422 ifp->if_start = gem_start; 423 ifp->if_ioctl = gem_ioctl; 424 ifp->if_watchdog = gem_watchdog; 425 ifp->if_stop = gem_stop; 426 ifp->if_init = gem_init; 427 IFQ_SET_READY(&ifp->if_snd); 428 429 /* 430 * If we support GigE media, we support jumbo frames too. 431 * Unless we are Apple. 432 */ 433 TAILQ_FOREACH(ifm, &sc->sc_mii.mii_media.ifm_list, ifm_list) { 434 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_T || 435 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_SX || 436 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_LX || 437 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_CX) { 438 if (!GEM_IS_APPLE(sc)) 439 sc->sc_ethercom.ec_capabilities 440 |= ETHERCAP_JUMBO_MTU; 441 sc->sc_flags |= GEM_GIGABIT; 442 break; 443 } 444 } 445 446 /* claim 802.1q capability */ 447 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 448 449 /* Attach the interface. */ 450 if_attach(ifp); 451 ether_ifattach(ifp, enaddr); 452 453 sc->sc_sh = shutdownhook_establish(gem_shutdown, sc); 454 if (sc->sc_sh == NULL) 455 panic("gem_config: can't establish shutdownhook"); 456 457 #if NRND > 0 458 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 459 RND_TYPE_NET, 0); 460 #endif 461 462 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, 463 NULL, sc->sc_dev.dv_xname, "interrupts"); 464 #ifdef GEM_COUNTERS 465 evcnt_attach_dynamic(&sc->sc_ev_txint, EVCNT_TYPE_INTR, 466 &sc->sc_ev_intr, sc->sc_dev.dv_xname, "tx interrupts"); 467 evcnt_attach_dynamic(&sc->sc_ev_rxint, EVCNT_TYPE_INTR, 468 &sc->sc_ev_intr, sc->sc_dev.dv_xname, "rx interrupts"); 469 evcnt_attach_dynamic(&sc->sc_ev_rxfull, EVCNT_TYPE_INTR, 470 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx ring full"); 471 evcnt_attach_dynamic(&sc->sc_ev_rxnobuf, EVCNT_TYPE_INTR, 472 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx malloc failure"); 473 evcnt_attach_dynamic(&sc->sc_ev_rxhist[0], EVCNT_TYPE_INTR, 474 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 0desc"); 475 evcnt_attach_dynamic(&sc->sc_ev_rxhist[1], EVCNT_TYPE_INTR, 476 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 1desc"); 477 evcnt_attach_dynamic(&sc->sc_ev_rxhist[2], EVCNT_TYPE_INTR, 478 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 2desc"); 479 evcnt_attach_dynamic(&sc->sc_ev_rxhist[3], EVCNT_TYPE_INTR, 480 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 3desc"); 481 evcnt_attach_dynamic(&sc->sc_ev_rxhist[4], EVCNT_TYPE_INTR, 482 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >3desc"); 483 evcnt_attach_dynamic(&sc->sc_ev_rxhist[5], EVCNT_TYPE_INTR, 484 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >7desc"); 485 evcnt_attach_dynamic(&sc->sc_ev_rxhist[6], EVCNT_TYPE_INTR, 486 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >15desc"); 487 evcnt_attach_dynamic(&sc->sc_ev_rxhist[7], EVCNT_TYPE_INTR, 488 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >31desc"); 489 evcnt_attach_dynamic(&sc->sc_ev_rxhist[8], EVCNT_TYPE_INTR, 490 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >63desc"); 491 #endif 492 493 #if notyet 494 /* 495 * Add a suspend hook to make sure we come back up after a 496 * resume. 497 */ 498 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 499 gem_power, sc); 500 if (sc->sc_powerhook == NULL) 501 aprint_error("%s: WARNING: unable to establish power hook\n", 502 sc->sc_dev.dv_xname); 503 #endif 504 505 callout_init(&sc->sc_tick_ch, 0); 506 return; 507 508 /* 509 * Free any resources we've allocated during the failed attach 510 * attempt. Do this in reverse order and fall through. 511 */ 512 fail_7: 513 for (i = 0; i < GEM_NRXDESC; i++) { 514 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 515 bus_dmamap_destroy(sc->sc_dmatag, 516 sc->sc_rxsoft[i].rxs_dmamap); 517 } 518 fail_6: 519 for (i = 0; i < GEM_TXQUEUELEN; i++) { 520 if (sc->sc_txsoft[i].txs_dmamap != NULL) 521 bus_dmamap_destroy(sc->sc_dmatag, 522 sc->sc_txsoft[i].txs_dmamap); 523 } 524 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 525 fail_5: 526 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_nulldmamap); 527 fail_4: 528 bus_dmamem_unmap(sc->sc_dmatag, (void *)nullbuf, ETHER_MIN_TX); 529 fail_3: 530 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 531 fail_2: 532 bus_dmamem_unmap(sc->sc_dmatag, (void *)sc->sc_control_data, 533 sizeof(struct gem_control_data)); 534 fail_1: 535 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 536 fail_0: 537 return; 538 } 539 540 541 void 542 gem_tick(arg) 543 void *arg; 544 { 545 struct gem_softc *sc = arg; 546 int s; 547 548 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) { 549 /* 550 * We have to reset everything if we failed to get a 551 * PCS interrupt. Restarting the callout is handled 552 * in gem_pcs_start(). 553 */ 554 gem_init(&sc->sc_ethercom.ec_if); 555 } else { 556 s = splnet(); 557 mii_tick(&sc->sc_mii); 558 splx(s); 559 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 560 } 561 } 562 563 static int 564 gem_bitwait(sc, h, r, clr, set) 565 struct gem_softc *sc; 566 bus_space_handle_t h; 567 int r; 568 u_int32_t clr; 569 u_int32_t set; 570 { 571 int i; 572 u_int32_t reg; 573 574 for (i = TRIES; i--; DELAY(100)) { 575 reg = bus_space_read_4(sc->sc_bustag, h, r); 576 if ((reg & clr) == 0 && (reg & set) == set) 577 return (1); 578 } 579 return (0); 580 } 581 582 void 583 gem_reset(sc) 584 struct gem_softc *sc; 585 { 586 bus_space_tag_t t = sc->sc_bustag; 587 bus_space_handle_t h = sc->sc_h2; 588 int s; 589 590 s = splnet(); 591 DPRINTF(sc, ("%s: gem_reset\n", sc->sc_dev.dv_xname)); 592 gem_reset_rx(sc); 593 gem_reset_tx(sc); 594 595 /* Do a full reset */ 596 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX|GEM_RESET_TX); 597 if (!gem_bitwait(sc, h, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0)) 598 printf("%s: cannot reset device\n", sc->sc_dev.dv_xname); 599 splx(s); 600 } 601 602 603 /* 604 * gem_rxdrain: 605 * 606 * Drain the receive queue. 607 */ 608 static void 609 gem_rxdrain(struct gem_softc *sc) 610 { 611 struct gem_rxsoft *rxs; 612 int i; 613 614 for (i = 0; i < GEM_NRXDESC; i++) { 615 rxs = &sc->sc_rxsoft[i]; 616 if (rxs->rxs_mbuf != NULL) { 617 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 618 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 619 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 620 m_freem(rxs->rxs_mbuf); 621 rxs->rxs_mbuf = NULL; 622 } 623 } 624 } 625 626 /* 627 * Reset the whole thing. 628 */ 629 static void 630 gem_stop(struct ifnet *ifp, int disable) 631 { 632 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 633 struct gem_txsoft *txs; 634 635 DPRINTF(sc, ("%s: gem_stop\n", sc->sc_dev.dv_xname)); 636 637 callout_stop(&sc->sc_tick_ch); 638 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 639 gem_pcs_stop(sc, disable); 640 else 641 mii_down(&sc->sc_mii); 642 643 /* XXX - Should we reset these instead? */ 644 gem_disable_tx(sc); 645 gem_disable_rx(sc); 646 647 /* 648 * Release any queued transmit buffers. 649 */ 650 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 651 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 652 if (txs->txs_mbuf != NULL) { 653 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 0, 654 txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 655 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 656 m_freem(txs->txs_mbuf); 657 txs->txs_mbuf = NULL; 658 } 659 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 660 } 661 662 if (disable) { 663 gem_rxdrain(sc); 664 } 665 666 /* 667 * Mark the interface down and cancel the watchdog timer. 668 */ 669 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 670 sc->sc_if_flags = ifp->if_flags; 671 ifp->if_timer = 0; 672 } 673 674 675 /* 676 * Reset the receiver 677 */ 678 int 679 gem_reset_rx(struct gem_softc *sc) 680 { 681 bus_space_tag_t t = sc->sc_bustag; 682 bus_space_handle_t h = sc->sc_h1, h2 = sc->sc_h2; 683 684 /* 685 * Resetting while DMA is in progress can cause a bus hang, so we 686 * disable DMA first. 687 */ 688 gem_disable_rx(sc); 689 bus_space_write_4(t, h, GEM_RX_CONFIG, 0); 690 bus_space_barrier(t, h, GEM_RX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 691 /* Wait till it finishes */ 692 if (!gem_bitwait(sc, h, GEM_RX_CONFIG, 1, 0)) 693 printf("%s: cannot disable read dma\n", sc->sc_dev.dv_xname); 694 695 /* Finally, reset the ERX */ 696 bus_space_write_4(t, h2, GEM_RESET, GEM_RESET_RX); 697 bus_space_barrier(t, h, GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE); 698 /* Wait till it finishes */ 699 if (!gem_bitwait(sc, h2, GEM_RESET, GEM_RESET_RX, 0)) { 700 printf("%s: cannot reset receiver\n", sc->sc_dev.dv_xname); 701 return (1); 702 } 703 return (0); 704 } 705 706 707 /* 708 * Reset the receiver DMA engine. 709 * 710 * Intended to be used in case of GEM_INTR_RX_TAG_ERR, GEM_MAC_RX_OVERFLOW 711 * etc in order to reset the receiver DMA engine only and not do a full 712 * reset which amongst others also downs the link and clears the FIFOs. 713 */ 714 static void 715 gem_reset_rxdma(struct gem_softc *sc) 716 { 717 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 718 bus_space_tag_t t = sc->sc_bustag; 719 bus_space_handle_t h = sc->sc_h1; 720 int i; 721 722 if (gem_reset_rx(sc) != 0) { 723 gem_init(ifp); 724 return; 725 } 726 for (i = 0; i < GEM_NRXDESC; i++) 727 if (sc->sc_rxsoft[i].rxs_mbuf != NULL) 728 GEM_UPDATE_RXDESC(sc, i); 729 sc->sc_rxptr = 0; 730 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE); 731 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD); 732 733 /* Reprogram Descriptor Ring Base Addresses */ 734 /* NOTE: we use only 32-bit DMA addresses here. */ 735 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0); 736 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 737 738 /* Redo ERX Configuration */ 739 gem_rx_common(sc); 740 741 /* Give the reciever a swift kick */ 742 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC - 4); 743 } 744 745 /* 746 * Common RX configuration for gem_init() and gem_reset_rxdma(). 747 */ 748 static void 749 gem_rx_common(struct gem_softc *sc) 750 { 751 bus_space_tag_t t = sc->sc_bustag; 752 bus_space_handle_t h = sc->sc_h1; 753 u_int32_t v; 754 755 /* Encode Receive Descriptor ring size: four possible values */ 756 v = gem_ringsize(GEM_NRXDESC /*XXX*/); 757 758 /* Set receive h/w checksum offset */ 759 #ifdef INET 760 v |= (ETHER_HDR_LEN + sizeof(struct ip) + 761 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 762 ETHER_VLAN_ENCAP_LEN : 0)) << GEM_RX_CONFIG_CXM_START_SHFT; 763 #endif 764 765 /* Enable RX DMA */ 766 bus_space_write_4(t, h, GEM_RX_CONFIG, 767 v | (GEM_THRSH_1024 << GEM_RX_CONFIG_FIFO_THRS_SHIFT) | 768 (2 << GEM_RX_CONFIG_FBOFF_SHFT) | GEM_RX_CONFIG_RXDMA_EN); 769 770 /* 771 * The following value is for an OFF Threshold of about 3/4 full 772 * and an ON Threshold of 1/4 full. 773 */ 774 bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH, 775 (3 * sc->sc_rxfifosize / 256) | 776 ((sc->sc_rxfifosize / 256) << 12)); 777 bus_space_write_4(t, h, GEM_RX_BLANKING, 778 (6 << GEM_RX_BLANKING_TIME_SHIFT) | 6); 779 } 780 781 /* 782 * Reset the transmitter 783 */ 784 int 785 gem_reset_tx(struct gem_softc *sc) 786 { 787 bus_space_tag_t t = sc->sc_bustag; 788 bus_space_handle_t h = sc->sc_h1, h2 = sc->sc_h2; 789 790 /* 791 * Resetting while DMA is in progress can cause a bus hang, so we 792 * disable DMA first. 793 */ 794 gem_disable_tx(sc); 795 bus_space_write_4(t, h, GEM_TX_CONFIG, 0); 796 bus_space_barrier(t, h, GEM_TX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 797 /* Wait till it finishes */ 798 if (!gem_bitwait(sc, h, GEM_TX_CONFIG, 1, 0)) 799 printf("%s: cannot disable read dma\n", sc->sc_dev.dv_xname); 800 /* Wait 5ms extra. */ 801 delay(5000); 802 803 /* Finally, reset the ETX */ 804 bus_space_write_4(t, h2, GEM_RESET, GEM_RESET_TX); 805 bus_space_barrier(t, h, GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE); 806 /* Wait till it finishes */ 807 if (!gem_bitwait(sc, h2, GEM_RESET, GEM_RESET_TX, 0)) { 808 printf("%s: cannot reset receiver\n", 809 sc->sc_dev.dv_xname); 810 return (1); 811 } 812 return (0); 813 } 814 815 /* 816 * disable receiver. 817 */ 818 int 819 gem_disable_rx(struct gem_softc *sc) 820 { 821 bus_space_tag_t t = sc->sc_bustag; 822 bus_space_handle_t h = sc->sc_h1; 823 u_int32_t cfg; 824 825 /* Flip the enable bit */ 826 cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 827 cfg &= ~GEM_MAC_RX_ENABLE; 828 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg); 829 bus_space_barrier(t, h, GEM_MAC_RX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 830 /* Wait for it to finish */ 831 return (gem_bitwait(sc, h, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)); 832 } 833 834 /* 835 * disable transmitter. 836 */ 837 int 838 gem_disable_tx(struct gem_softc *sc) 839 { 840 bus_space_tag_t t = sc->sc_bustag; 841 bus_space_handle_t h = sc->sc_h1; 842 u_int32_t cfg; 843 844 /* Flip the enable bit */ 845 cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG); 846 cfg &= ~GEM_MAC_TX_ENABLE; 847 bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg); 848 bus_space_barrier(t, h, GEM_MAC_TX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 849 /* Wait for it to finish */ 850 return (gem_bitwait(sc, h, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)); 851 } 852 853 /* 854 * Initialize interface. 855 */ 856 int 857 gem_meminit(struct gem_softc *sc) 858 { 859 struct gem_rxsoft *rxs; 860 int i, error; 861 862 /* 863 * Initialize the transmit descriptor ring. 864 */ 865 memset((void *)sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 866 for (i = 0; i < GEM_NTXDESC; i++) { 867 sc->sc_txdescs[i].gd_flags = 0; 868 sc->sc_txdescs[i].gd_addr = 0; 869 } 870 GEM_CDTXSYNC(sc, 0, GEM_NTXDESC, 871 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 872 sc->sc_txfree = GEM_NTXDESC-1; 873 sc->sc_txnext = 0; 874 sc->sc_txwin = 0; 875 876 /* 877 * Initialize the receive descriptor and receive job 878 * descriptor rings. 879 */ 880 for (i = 0; i < GEM_NRXDESC; i++) { 881 rxs = &sc->sc_rxsoft[i]; 882 if (rxs->rxs_mbuf == NULL) { 883 if ((error = gem_add_rxbuf(sc, i)) != 0) { 884 printf("%s: unable to allocate or map rx " 885 "buffer %d, error = %d\n", 886 sc->sc_dev.dv_xname, i, error); 887 /* 888 * XXX Should attempt to run with fewer receive 889 * XXX buffers instead of just failing. 890 */ 891 gem_rxdrain(sc); 892 return (1); 893 } 894 } else 895 GEM_INIT_RXDESC(sc, i); 896 } 897 sc->sc_rxptr = 0; 898 sc->sc_meminited = 1; 899 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE); 900 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD); 901 902 return (0); 903 } 904 905 static int 906 gem_ringsize(int sz) 907 { 908 switch (sz) { 909 case 32: 910 return GEM_RING_SZ_32; 911 case 64: 912 return GEM_RING_SZ_64; 913 case 128: 914 return GEM_RING_SZ_128; 915 case 256: 916 return GEM_RING_SZ_256; 917 case 512: 918 return GEM_RING_SZ_512; 919 case 1024: 920 return GEM_RING_SZ_1024; 921 case 2048: 922 return GEM_RING_SZ_2048; 923 case 4096: 924 return GEM_RING_SZ_4096; 925 case 8192: 926 return GEM_RING_SZ_8192; 927 default: 928 printf("gem: invalid Receive Descriptor ring size %d\n", sz); 929 return GEM_RING_SZ_32; 930 } 931 } 932 933 934 /* 935 * Start PCS 936 */ 937 void 938 gem_pcs_start(struct gem_softc *sc) 939 { 940 bus_space_tag_t t = sc->sc_bustag; 941 bus_space_handle_t h = sc->sc_h1; 942 uint32_t v; 943 944 #ifdef GEM_DEBUG 945 aprint_debug("%s: gem_pcs_start()\n", sc->sc_dev.dv_xname); 946 #endif 947 948 /* 949 * Set up. We must disable the MII before modifying the 950 * GEM_MII_ANAR register 951 */ 952 if (sc->sc_flags & GEM_SERDES) { 953 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 954 GEM_MII_DATAPATH_SERDES); 955 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 956 GEM_MII_SLINK_LOOPBACK); 957 } else { 958 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 959 GEM_MII_DATAPATH_SERIAL); 960 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 0); 961 } 962 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 963 v = bus_space_read_4(t, h, GEM_MII_ANAR); 964 v |= (GEM_MII_ANEG_SYM_PAUSE | GEM_MII_ANEG_ASYM_PAUSE); 965 if (sc->sc_mii_media == IFM_AUTO) 966 v |= (GEM_MII_ANEG_FUL_DUPLX | GEM_MII_ANEG_HLF_DUPLX); 967 else if (sc->sc_mii_media == IFM_FDX) { 968 v |= GEM_MII_ANEG_FUL_DUPLX; 969 v &= ~GEM_MII_ANEG_HLF_DUPLX; 970 } else if (sc->sc_mii_media == IFM_HDX) { 971 v &= ~GEM_MII_ANEG_FUL_DUPLX; 972 v |= GEM_MII_ANEG_HLF_DUPLX; 973 } 974 975 /* Configure link. */ 976 bus_space_write_4(t, h, GEM_MII_ANAR, v); 977 bus_space_write_4(t, h, GEM_MII_CONTROL, 978 GEM_MII_CONTROL_AUTONEG | GEM_MII_CONTROL_RAN); 979 bus_space_write_4(t, h, GEM_MII_CONFIG, GEM_MII_CONFIG_ENABLE); 980 gem_bitwait(sc, h, GEM_MII_STATUS, 0, GEM_MII_STATUS_ANEG_CPT); 981 982 /* Start the 10 second timer */ 983 callout_reset(&sc->sc_tick_ch, hz * 10, gem_tick, sc); 984 } 985 986 /* 987 * Stop PCS 988 */ 989 void 990 gem_pcs_stop(struct gem_softc *sc, int disable) 991 { 992 bus_space_tag_t t = sc->sc_bustag; 993 bus_space_handle_t h = sc->sc_h1; 994 995 #ifdef GEM_DEBUG 996 aprint_debug("%s: gem_pcs_stop()\n", sc->sc_dev.dv_xname); 997 #endif 998 999 /* Tell link partner that we're going away */ 1000 bus_space_write_4(t, h, GEM_MII_ANAR, GEM_MII_ANEG_RF); 1001 1002 /* 1003 * Disable PCS MII. The documentation suggests that setting 1004 * GEM_MII_CONFIG_ENABLE to zero and then restarting auto- 1005 * negotiation will shut down the link. However, it appears 1006 * that we also need to unset the datapath mode. 1007 */ 1008 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 1009 bus_space_write_4(t, h, GEM_MII_CONTROL, 1010 GEM_MII_CONTROL_AUTONEG | GEM_MII_CONTROL_RAN); 1011 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, GEM_MII_DATAPATH_MII); 1012 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 1013 1014 if (disable) { 1015 if (sc->sc_flags & GEM_SERDES) 1016 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 1017 GEM_MII_SLINK_POWER_OFF); 1018 else 1019 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 1020 GEM_MII_SLINK_LOOPBACK | GEM_MII_SLINK_POWER_OFF); 1021 } 1022 1023 sc->sc_flags &= ~GEM_LINK; 1024 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_NONE; 1025 sc->sc_mii.mii_media_status = IFM_AVALID; 1026 } 1027 1028 1029 /* 1030 * Initialization of interface; set up initialization block 1031 * and transmit/receive descriptor rings. 1032 */ 1033 int 1034 gem_init(struct ifnet *ifp) 1035 { 1036 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 1037 bus_space_tag_t t = sc->sc_bustag; 1038 bus_space_handle_t h = sc->sc_h1; 1039 int rc = 0, s; 1040 u_int max_frame_size; 1041 u_int32_t v; 1042 1043 s = splnet(); 1044 1045 DPRINTF(sc, ("%s: gem_init: calling stop\n", sc->sc_dev.dv_xname)); 1046 /* 1047 * Initialization sequence. The numbered steps below correspond 1048 * to the sequence outlined in section 6.3.5.1 in the Ethernet 1049 * Channel Engine manual (part of the PCIO manual). 1050 * See also the STP2002-STQ document from Sun Microsystems. 1051 */ 1052 1053 /* step 1 & 2. Reset the Ethernet Channel */ 1054 gem_stop(ifp, 0); 1055 gem_reset(sc); 1056 DPRINTF(sc, ("%s: gem_init: restarting\n", sc->sc_dev.dv_xname)); 1057 1058 /* Re-initialize the MIF */ 1059 gem_mifinit(sc); 1060 1061 /* Set up correct datapath for non-SERDES/Serialink */ 1062 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0 && 1063 sc->sc_variant != GEM_SUN_ERI) 1064 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 1065 GEM_MII_DATAPATH_MII); 1066 1067 /* Call MI reset function if any */ 1068 if (sc->sc_hwreset) 1069 (*sc->sc_hwreset)(sc); 1070 1071 /* step 3. Setup data structures in host memory */ 1072 if (gem_meminit(sc) != 0) 1073 return 1; 1074 1075 /* step 4. TX MAC registers & counters */ 1076 gem_init_regs(sc); 1077 max_frame_size = max(sc->sc_ethercom.ec_if.if_mtu, ETHERMTU); 1078 max_frame_size += ETHER_HDR_LEN + ETHER_CRC_LEN; 1079 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1080 max_frame_size += ETHER_VLAN_ENCAP_LEN; 1081 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 1082 max_frame_size|/* burst size */(0x2000<<16)); 1083 1084 /* step 5. RX MAC registers & counters */ 1085 gem_setladrf(sc); 1086 1087 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 1088 /* NOTE: we use only 32-bit DMA addresses here. */ 1089 bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 0); 1090 bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 1091 1092 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0); 1093 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 1094 1095 /* step 8. Global Configuration & Interrupt Mask */ 1096 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 1097 v = GEM_INTR_PCS; 1098 else 1099 v = GEM_INTR_MIF; 1100 bus_space_write_4(t, h, GEM_INTMASK, 1101 ~(GEM_INTR_TX_INTME | 1102 GEM_INTR_TX_EMPTY | 1103 GEM_INTR_TX_MAC | 1104 GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF| 1105 GEM_INTR_RX_TAG_ERR | GEM_INTR_MAC_CONTROL| 1106 GEM_INTR_BERR | v)); 1107 bus_space_write_4(t, h, GEM_MAC_RX_MASK, 1108 GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT); 1109 bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXX */ 1110 bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 1111 GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME); 1112 1113 /* step 9. ETX Configuration: use mostly default values */ 1114 1115 /* Enable TX DMA */ 1116 v = gem_ringsize(GEM_NTXDESC /*XXX*/); 1117 bus_space_write_4(t, h, GEM_TX_CONFIG, 1118 v|GEM_TX_CONFIG_TXDMA_EN| 1119 ((0x4FF<<10)&GEM_TX_CONFIG_TXFIFO_TH)); 1120 bus_space_write_4(t, h, GEM_TX_KICK, sc->sc_txnext); 1121 1122 /* step 10. ERX Configuration */ 1123 gem_rx_common(sc); 1124 1125 /* step 11. Configure Media */ 1126 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0 && 1127 (rc = mii_ifmedia_change(&sc->sc_mii)) != 0) 1128 goto out; 1129 1130 /* step 12. RX_MAC Configuration Register */ 1131 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 1132 v |= GEM_MAC_RX_ENABLE | GEM_MAC_RX_STRIP_CRC; 1133 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 1134 1135 /* step 14. Issue Transmit Pending command */ 1136 1137 /* Call MI initialization function if any */ 1138 if (sc->sc_hwinit) 1139 (*sc->sc_hwinit)(sc); 1140 1141 1142 /* step 15. Give the reciever a swift kick */ 1143 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4); 1144 1145 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 1146 /* Configure PCS */ 1147 gem_pcs_start(sc); 1148 else 1149 /* Start the one second timer. */ 1150 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 1151 1152 sc->sc_flags &= ~GEM_LINK; 1153 ifp->if_flags |= IFF_RUNNING; 1154 ifp->if_flags &= ~IFF_OACTIVE; 1155 ifp->if_timer = 0; 1156 sc->sc_if_flags = ifp->if_flags; 1157 out: 1158 splx(s); 1159 1160 return (0); 1161 } 1162 1163 void 1164 gem_init_regs(struct gem_softc *sc) 1165 { 1166 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1167 bus_space_tag_t t = sc->sc_bustag; 1168 bus_space_handle_t h = sc->sc_h1; 1169 const u_char *laddr = CLLADDR(ifp->if_sadl); 1170 u_int32_t v; 1171 1172 /* These regs are not cleared on reset */ 1173 if (!sc->sc_inited) { 1174 1175 /* Load recommended values */ 1176 bus_space_write_4(t, h, GEM_MAC_IPG0, 0x00); 1177 bus_space_write_4(t, h, GEM_MAC_IPG1, 0x08); 1178 bus_space_write_4(t, h, GEM_MAC_IPG2, 0x04); 1179 1180 bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 1181 /* Max frame and max burst size */ 1182 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 1183 ETHER_MAX_LEN | (0x2000<<16)); 1184 1185 bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x07); 1186 bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x04); 1187 bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10); 1188 bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088); 1189 bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED, 1190 ((laddr[5]<<8)|laddr[4])&0x3ff); 1191 1192 /* Secondary MAC addr set to 0:0:0:0:0:0 */ 1193 bus_space_write_4(t, h, GEM_MAC_ADDR3, 0); 1194 bus_space_write_4(t, h, GEM_MAC_ADDR4, 0); 1195 bus_space_write_4(t, h, GEM_MAC_ADDR5, 0); 1196 1197 /* MAC control addr set to 01:80:c2:00:00:01 */ 1198 bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001); 1199 bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200); 1200 bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180); 1201 1202 /* MAC filter addr set to 0:0:0:0:0:0 */ 1203 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0); 1204 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0); 1205 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0); 1206 1207 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0); 1208 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0); 1209 1210 sc->sc_inited = 1; 1211 } 1212 1213 /* Counters need to be zeroed */ 1214 bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0); 1215 bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0); 1216 bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0); 1217 bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0); 1218 bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0); 1219 bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0); 1220 bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0); 1221 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 1222 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 1223 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 1224 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 1225 1226 /* Set XOFF PAUSE time. */ 1227 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); 1228 1229 /* 1230 * Set the internal arbitration to "infinite" bursts of the 1231 * maximum length of 31 * 64 bytes so DMA transfers aren't 1232 * split up in cache line size chunks. This greatly improves 1233 * especially RX performance. 1234 * Enable silicon bug workarounds for the Apple variants. 1235 */ 1236 bus_space_write_4(t, h, GEM_CONFIG, 1237 GEM_CONFIG_TXDMA_LIMIT | GEM_CONFIG_RXDMA_LIMIT | 1238 GEM_CONFIG_BURST_INF | (GEM_IS_APPLE(sc) ? 1239 GEM_CONFIG_RONPAULBIT | GEM_CONFIG_BUG2FIX : 0)); 1240 1241 /* 1242 * Set the station address. 1243 */ 1244 bus_space_write_4(t, h, GEM_MAC_ADDR0, (laddr[4]<<8)|laddr[5]); 1245 bus_space_write_4(t, h, GEM_MAC_ADDR1, (laddr[2]<<8)|laddr[3]); 1246 bus_space_write_4(t, h, GEM_MAC_ADDR2, (laddr[0]<<8)|laddr[1]); 1247 1248 /* 1249 * Enable MII outputs. Enable GMII if there is a gigabit PHY. 1250 */ 1251 sc->sc_mif_config = bus_space_read_4(t, h, GEM_MIF_CONFIG); 1252 v = GEM_MAC_XIF_TX_MII_ENA; 1253 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) { 1254 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) { 1255 v |= GEM_MAC_XIF_FDPLX_LED; 1256 if (sc->sc_flags & GEM_GIGABIT) 1257 v |= GEM_MAC_XIF_GMII_MODE; 1258 } 1259 } else { 1260 v |= GEM_MAC_XIF_GMII_MODE; 1261 } 1262 bus_space_write_4(t, h, GEM_MAC_XIF_CONFIG, v); 1263 } 1264 1265 #ifdef GEM_DEBUG 1266 static void 1267 gem_txsoft_print(const struct gem_softc *sc, int firstdesc, int lastdesc) 1268 { 1269 int i; 1270 1271 for (i = firstdesc;; i = GEM_NEXTTX(i)) { 1272 printf("descriptor %d:\t", i); 1273 printf("gd_flags: 0x%016" PRIx64 "\t", 1274 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags)); 1275 printf("gd_addr: 0x%016" PRIx64 "\n", 1276 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr)); 1277 if (i == lastdesc) 1278 break; 1279 } 1280 } 1281 #endif 1282 1283 static void 1284 gem_start(ifp) 1285 struct ifnet *ifp; 1286 { 1287 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 1288 struct mbuf *m0, *m; 1289 struct gem_txsoft *txs; 1290 bus_dmamap_t dmamap; 1291 int error, firsttx, nexttx = -1, lasttx = -1, ofree, seg; 1292 uint64_t flags = 0; 1293 1294 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1295 return; 1296 1297 /* 1298 * Remember the previous number of free descriptors and 1299 * the first descriptor we'll use. 1300 */ 1301 ofree = sc->sc_txfree; 1302 firsttx = sc->sc_txnext; 1303 1304 DPRINTF(sc, ("%s: gem_start: txfree %d, txnext %d\n", 1305 sc->sc_dev.dv_xname, ofree, firsttx)); 1306 1307 /* 1308 * Loop through the send queue, setting up transmit descriptors 1309 * until we drain the queue, or use up all available transmit 1310 * descriptors. 1311 */ 1312 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 1313 sc->sc_txfree != 0) { 1314 /* 1315 * Grab a packet off the queue. 1316 */ 1317 IFQ_POLL(&ifp->if_snd, m0); 1318 if (m0 == NULL) 1319 break; 1320 m = NULL; 1321 1322 dmamap = txs->txs_dmamap; 1323 1324 /* 1325 * Load the DMA map. If this fails, the packet either 1326 * didn't fit in the alloted number of segments, or we were 1327 * short on resources. In this case, we'll copy and try 1328 * again. 1329 */ 1330 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m0, 1331 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0 || 1332 (m0->m_pkthdr.len < ETHER_MIN_TX && 1333 dmamap->dm_nsegs == GEM_NTXSEGS)) { 1334 if (m0->m_pkthdr.len > MCLBYTES) { 1335 printf("%s: unable to allocate jumbo Tx " 1336 "cluster\n", sc->sc_dev.dv_xname); 1337 IFQ_DEQUEUE(&ifp->if_snd, m0); 1338 m_freem(m0); 1339 continue; 1340 } 1341 MGETHDR(m, M_DONTWAIT, MT_DATA); 1342 if (m == NULL) { 1343 printf("%s: unable to allocate Tx mbuf\n", 1344 sc->sc_dev.dv_xname); 1345 break; 1346 } 1347 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1348 if (m0->m_pkthdr.len > MHLEN) { 1349 MCLGET(m, M_DONTWAIT); 1350 if ((m->m_flags & M_EXT) == 0) { 1351 printf("%s: unable to allocate Tx " 1352 "cluster\n", sc->sc_dev.dv_xname); 1353 m_freem(m); 1354 break; 1355 } 1356 } 1357 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1358 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1359 error = bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, 1360 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1361 if (error) { 1362 printf("%s: unable to load Tx buffer, " 1363 "error = %d\n", sc->sc_dev.dv_xname, error); 1364 break; 1365 } 1366 } 1367 1368 /* 1369 * Ensure we have enough descriptors free to describe 1370 * the packet. 1371 */ 1372 if (dmamap->dm_nsegs > ((m0->m_pkthdr.len < ETHER_MIN_TX) ? 1373 (sc->sc_txfree - 1) : sc->sc_txfree)) { 1374 /* 1375 * Not enough free descriptors to transmit this 1376 * packet. We haven't committed to anything yet, 1377 * so just unload the DMA map, put the packet 1378 * back on the queue, and punt. Notify the upper 1379 * layer that there are no more slots left. 1380 * 1381 * XXX We could allocate an mbuf and copy, but 1382 * XXX it is worth it? 1383 */ 1384 ifp->if_flags |= IFF_OACTIVE; 1385 sc->sc_if_flags = ifp->if_flags; 1386 bus_dmamap_unload(sc->sc_dmatag, dmamap); 1387 if (m != NULL) 1388 m_freem(m); 1389 break; 1390 } 1391 1392 IFQ_DEQUEUE(&ifp->if_snd, m0); 1393 if (m != NULL) { 1394 m_freem(m0); 1395 m0 = m; 1396 } 1397 1398 /* 1399 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1400 */ 1401 1402 /* Sync the DMA map. */ 1403 bus_dmamap_sync(sc->sc_dmatag, dmamap, 0, dmamap->dm_mapsize, 1404 BUS_DMASYNC_PREWRITE); 1405 1406 /* 1407 * Initialize the transmit descriptors. 1408 */ 1409 for (nexttx = sc->sc_txnext, seg = 0; 1410 seg < dmamap->dm_nsegs; 1411 seg++, nexttx = GEM_NEXTTX(nexttx)) { 1412 1413 /* 1414 * If this is the first descriptor we're 1415 * enqueueing, set the start of packet flag, 1416 * and the checksum stuff if we want the hardware 1417 * to do it. 1418 */ 1419 sc->sc_txdescs[nexttx].gd_addr = 1420 GEM_DMA_WRITE(sc, dmamap->dm_segs[seg].ds_addr); 1421 flags = dmamap->dm_segs[seg].ds_len & GEM_TD_BUFSIZE; 1422 if (nexttx == firsttx) { 1423 flags |= GEM_TD_START_OF_PACKET; 1424 if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) { 1425 sc->sc_txwin = 0; 1426 flags |= GEM_TD_INTERRUPT_ME; 1427 } 1428 1429 #ifdef INET 1430 /* h/w checksum */ 1431 if (ifp->if_csum_flags_tx & M_CSUM_TCPv4 && 1432 m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1433 struct ether_header *eh; 1434 uint16_t offset, start; 1435 1436 eh = mtod(m0, struct ether_header *); 1437 switch (ntohs(eh->ether_type)) { 1438 case ETHERTYPE_IP: 1439 start = ETHER_HDR_LEN; 1440 break; 1441 case ETHERTYPE_VLAN: 1442 start = ETHER_HDR_LEN + 1443 ETHER_VLAN_ENCAP_LEN; 1444 break; 1445 default: 1446 /* unsupported, drop it */ 1447 m_free(m0); 1448 continue; 1449 } 1450 start += M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 1451 offset = M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data) + start; 1452 flags |= (start << 1453 GEM_TD_CXSUM_STARTSHFT) | 1454 (offset << 1455 GEM_TD_CXSUM_STUFFSHFT) | 1456 GEM_TD_CXSUM_ENABLE; 1457 } 1458 #endif 1459 } 1460 if (seg == dmamap->dm_nsegs - 1) { 1461 flags |= GEM_TD_END_OF_PACKET; 1462 } else { 1463 /* last flag set outside of loop */ 1464 sc->sc_txdescs[nexttx].gd_flags = 1465 GEM_DMA_WRITE(sc, flags); 1466 } 1467 lasttx = nexttx; 1468 } 1469 if (m0->m_pkthdr.len < ETHER_MIN_TX) { 1470 /* add padding buffer at end of chain */ 1471 flags &= ~GEM_TD_END_OF_PACKET; 1472 sc->sc_txdescs[lasttx].gd_flags = 1473 GEM_DMA_WRITE(sc, flags); 1474 1475 sc->sc_txdescs[nexttx].gd_addr = 1476 GEM_DMA_WRITE(sc, 1477 sc->sc_nulldmamap->dm_segs[0].ds_addr); 1478 flags = ((ETHER_MIN_TX - m0->m_pkthdr.len) & 1479 GEM_TD_BUFSIZE) | GEM_TD_END_OF_PACKET; 1480 lasttx = nexttx; 1481 nexttx = GEM_NEXTTX(nexttx); 1482 seg++; 1483 } 1484 sc->sc_txdescs[lasttx].gd_flags = GEM_DMA_WRITE(sc, flags); 1485 1486 KASSERT(lasttx != -1); 1487 1488 /* 1489 * Store a pointer to the packet so we can free it later, 1490 * and remember what txdirty will be once the packet is 1491 * done. 1492 */ 1493 txs->txs_mbuf = m0; 1494 txs->txs_firstdesc = sc->sc_txnext; 1495 txs->txs_lastdesc = lasttx; 1496 txs->txs_ndescs = seg; 1497 1498 #ifdef GEM_DEBUG 1499 if (ifp->if_flags & IFF_DEBUG) { 1500 printf(" gem_start %p transmit chain:\n", txs); 1501 gem_txsoft_print(sc, txs->txs_firstdesc, 1502 txs->txs_lastdesc); 1503 } 1504 #endif 1505 1506 /* Sync the descriptors we're using. */ 1507 GEM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndescs, 1508 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1509 1510 /* Advance the tx pointer. */ 1511 sc->sc_txfree -= txs->txs_ndescs; 1512 sc->sc_txnext = nexttx; 1513 1514 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1515 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1516 1517 #if NBPFILTER > 0 1518 /* 1519 * Pass the packet to any BPF listeners. 1520 */ 1521 if (ifp->if_bpf) 1522 bpf_mtap(ifp->if_bpf, m0); 1523 #endif /* NBPFILTER > 0 */ 1524 } 1525 1526 if (txs == NULL || sc->sc_txfree == 0) { 1527 /* No more slots left; notify upper layer. */ 1528 ifp->if_flags |= IFF_OACTIVE; 1529 sc->sc_if_flags = ifp->if_flags; 1530 } 1531 1532 if (sc->sc_txfree != ofree) { 1533 DPRINTF(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 1534 sc->sc_dev.dv_xname, lasttx, firsttx)); 1535 /* 1536 * The entire packet chain is set up. 1537 * Kick the transmitter. 1538 */ 1539 DPRINTF(sc, ("%s: gem_start: kicking tx %d\n", 1540 sc->sc_dev.dv_xname, nexttx)); 1541 bus_space_write_4(sc->sc_bustag, sc->sc_h1, GEM_TX_KICK, 1542 sc->sc_txnext); 1543 1544 /* Set a watchdog timer in case the chip flakes out. */ 1545 ifp->if_timer = 5; 1546 DPRINTF(sc, ("%s: gem_start: watchdog %d\n", 1547 sc->sc_dev.dv_xname, ifp->if_timer)); 1548 } 1549 } 1550 1551 /* 1552 * Transmit interrupt. 1553 */ 1554 int 1555 gem_tint(sc) 1556 struct gem_softc *sc; 1557 { 1558 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1559 bus_space_tag_t t = sc->sc_bustag; 1560 bus_space_handle_t mac = sc->sc_h1; 1561 struct gem_txsoft *txs; 1562 int txlast; 1563 int progress = 0; 1564 1565 DPRINTF(sc, ("%s: gem_tint\n", sc->sc_dev.dv_xname)); 1566 1567 /* 1568 * Unload collision counters 1569 */ 1570 ifp->if_collisions += 1571 bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) + 1572 bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT) + 1573 bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) + 1574 bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT); 1575 1576 /* 1577 * then clear the hardware counters. 1578 */ 1579 bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0); 1580 bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0); 1581 bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0); 1582 bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0); 1583 1584 /* 1585 * Go through our Tx list and free mbufs for those 1586 * frames that have been transmitted. 1587 */ 1588 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1589 /* 1590 * In theory, we could harvest some descriptors before 1591 * the ring is empty, but that's a bit complicated. 1592 * 1593 * GEM_TX_COMPLETION points to the last descriptor 1594 * processed +1. 1595 * 1596 * Let's assume that the NIC writes back to the Tx 1597 * descriptors before it updates the completion 1598 * register. If the NIC has posted writes to the 1599 * Tx descriptors, PCI ordering requires that the 1600 * posted writes flush to RAM before the register-read 1601 * finishes. So let's read the completion register, 1602 * before syncing the descriptors, so that we 1603 * examine Tx descriptors that are at least as 1604 * current as the completion register. 1605 */ 1606 txlast = bus_space_read_4(t, mac, GEM_TX_COMPLETION); 1607 DPRINTF(sc, 1608 ("gem_tint: txs->txs_lastdesc = %d, txlast = %d\n", 1609 txs->txs_lastdesc, txlast)); 1610 if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1611 if (txlast >= txs->txs_firstdesc && 1612 txlast <= txs->txs_lastdesc) 1613 break; 1614 } else if (txlast >= txs->txs_firstdesc || 1615 txlast <= txs->txs_lastdesc) 1616 break; 1617 1618 GEM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndescs, 1619 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1620 1621 #ifdef GEM_DEBUG /* XXX DMA synchronization? */ 1622 if (ifp->if_flags & IFF_DEBUG) { 1623 printf(" txsoft %p transmit chain:\n", txs); 1624 gem_txsoft_print(sc, txs->txs_firstdesc, 1625 txs->txs_lastdesc); 1626 } 1627 #endif 1628 1629 1630 DPRINTF(sc, ("gem_tint: releasing a desc\n")); 1631 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1632 1633 sc->sc_txfree += txs->txs_ndescs; 1634 1635 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 1636 0, txs->txs_dmamap->dm_mapsize, 1637 BUS_DMASYNC_POSTWRITE); 1638 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 1639 if (txs->txs_mbuf != NULL) { 1640 m_freem(txs->txs_mbuf); 1641 txs->txs_mbuf = NULL; 1642 } 1643 1644 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1645 1646 ifp->if_opackets++; 1647 progress = 1; 1648 } 1649 1650 #if 0 1651 DPRINTF(sc, ("gem_tint: GEM_TX_STATE_MACHINE %x " 1652 "GEM_TX_DATA_PTR %" PRIx64 "GEM_TX_COMPLETION %" PRIx32 "\n", 1653 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_TX_STATE_MACHINE), 1654 ((uint64_t)bus_space_read_4(sc->sc_bustag, sc->sc_h1, 1655 GEM_TX_DATA_PTR_HI) << 32) | 1656 bus_space_read_4(sc->sc_bustag, sc->sc_h1, 1657 GEM_TX_DATA_PTR_LO), 1658 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_TX_COMPLETION))); 1659 #endif 1660 1661 if (progress) { 1662 if (sc->sc_txfree == GEM_NTXDESC - 1) 1663 sc->sc_txwin = 0; 1664 1665 /* Freed some descriptors, so reset IFF_OACTIVE and restart. */ 1666 ifp->if_flags &= ~IFF_OACTIVE; 1667 sc->sc_if_flags = ifp->if_flags; 1668 ifp->if_timer = SIMPLEQ_EMPTY(&sc->sc_txdirtyq) ? 0 : 5; 1669 gem_start(ifp); 1670 } 1671 DPRINTF(sc, ("%s: gem_tint: watchdog %d\n", 1672 sc->sc_dev.dv_xname, ifp->if_timer)); 1673 1674 return (1); 1675 } 1676 1677 /* 1678 * Receive interrupt. 1679 */ 1680 int 1681 gem_rint(sc) 1682 struct gem_softc *sc; 1683 { 1684 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1685 bus_space_tag_t t = sc->sc_bustag; 1686 bus_space_handle_t h = sc->sc_h1; 1687 struct gem_rxsoft *rxs; 1688 struct mbuf *m; 1689 u_int64_t rxstat; 1690 u_int32_t rxcomp; 1691 int i, len, progress = 0; 1692 1693 DPRINTF(sc, ("%s: gem_rint\n", sc->sc_dev.dv_xname)); 1694 1695 /* 1696 * Ignore spurious interrupt that sometimes occurs before 1697 * we are set up when we network boot. 1698 */ 1699 if (!sc->sc_meminited) 1700 return 1; 1701 1702 /* 1703 * Read the completion register once. This limits 1704 * how long the following loop can execute. 1705 */ 1706 rxcomp = bus_space_read_4(t, h, GEM_RX_COMPLETION); 1707 1708 /* 1709 * XXX Read the lastrx only once at the top for speed. 1710 */ 1711 DPRINTF(sc, ("gem_rint: sc->rxptr %d, complete %d\n", 1712 sc->sc_rxptr, rxcomp)); 1713 1714 /* 1715 * Go into the loop at least once. 1716 */ 1717 for (i = sc->sc_rxptr; i == sc->sc_rxptr || i != rxcomp; 1718 i = GEM_NEXTRX(i)) { 1719 rxs = &sc->sc_rxsoft[i]; 1720 1721 GEM_CDRXSYNC(sc, i, 1722 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1723 1724 rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags); 1725 1726 if (rxstat & GEM_RD_OWN) { 1727 GEM_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); 1728 /* 1729 * We have processed all of the receive buffers. 1730 */ 1731 break; 1732 } 1733 1734 progress++; 1735 ifp->if_ipackets++; 1736 1737 if (rxstat & GEM_RD_BAD_CRC) { 1738 ifp->if_ierrors++; 1739 printf("%s: receive error: CRC error\n", 1740 sc->sc_dev.dv_xname); 1741 GEM_INIT_RXDESC(sc, i); 1742 continue; 1743 } 1744 1745 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1746 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1747 #ifdef GEM_DEBUG 1748 if (ifp->if_flags & IFF_DEBUG) { 1749 printf(" rxsoft %p descriptor %d: ", rxs, i); 1750 printf("gd_flags: 0x%016llx\t", (long long) 1751 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags)); 1752 printf("gd_addr: 0x%016llx\n", (long long) 1753 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr)); 1754 } 1755 #endif 1756 1757 /* No errors; receive the packet. */ 1758 len = GEM_RD_BUFLEN(rxstat); 1759 1760 /* 1761 * Allocate a new mbuf cluster. If that fails, we are 1762 * out of memory, and must drop the packet and recycle 1763 * the buffer that's already attached to this descriptor. 1764 */ 1765 m = rxs->rxs_mbuf; 1766 if (gem_add_rxbuf(sc, i) != 0) { 1767 GEM_COUNTER_INCR(sc, sc_ev_rxnobuf); 1768 ifp->if_ierrors++; 1769 GEM_INIT_RXDESC(sc, i); 1770 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1771 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1772 continue; 1773 } 1774 m->m_data += 2; /* We're already off by two */ 1775 1776 m->m_pkthdr.rcvif = ifp; 1777 m->m_pkthdr.len = m->m_len = len; 1778 1779 #if NBPFILTER > 0 1780 /* 1781 * Pass this up to any BPF listeners, but only 1782 * pass it up the stack if it's for us. 1783 */ 1784 if (ifp->if_bpf) 1785 bpf_mtap(ifp->if_bpf, m); 1786 #endif /* NBPFILTER > 0 */ 1787 1788 #ifdef INET 1789 /* hardware checksum */ 1790 if (ifp->if_csum_flags_rx & M_CSUM_TCPv4) { 1791 struct ether_header *eh; 1792 struct ip *ip; 1793 int32_t hlen, pktlen; 1794 1795 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1796 pktlen = m->m_pkthdr.len - ETHER_HDR_LEN - 1797 ETHER_VLAN_ENCAP_LEN; 1798 eh = (struct ether_header *) mtod(m, void *) + 1799 ETHER_VLAN_ENCAP_LEN; 1800 } else { 1801 pktlen = m->m_pkthdr.len - ETHER_HDR_LEN; 1802 eh = mtod(m, struct ether_header *); 1803 } 1804 if (ntohs(eh->ether_type) != ETHERTYPE_IP) 1805 goto swcsum; 1806 ip = (struct ip *) ((char *)eh + ETHER_HDR_LEN); 1807 1808 /* IPv4 only */ 1809 if (ip->ip_v != IPVERSION) 1810 goto swcsum; 1811 1812 hlen = ip->ip_hl << 2; 1813 if (hlen < sizeof(struct ip)) 1814 goto swcsum; 1815 1816 /* 1817 * bail if too short, has random trailing garbage, 1818 * truncated, fragment, or has ethernet pad. 1819 */ 1820 if ((ntohs(ip->ip_len) < hlen) || 1821 (ntohs(ip->ip_len) != pktlen) || 1822 (ntohs(ip->ip_off) & (IP_MF | IP_OFFMASK))) 1823 goto swcsum; 1824 1825 switch (ip->ip_p) { 1826 case IPPROTO_TCP: 1827 if (! (ifp->if_csum_flags_rx & M_CSUM_TCPv4)) 1828 goto swcsum; 1829 if (pktlen < (hlen + sizeof(struct tcphdr))) 1830 goto swcsum; 1831 m->m_pkthdr.csum_flags = M_CSUM_TCPv4; 1832 break; 1833 case IPPROTO_UDP: 1834 /* FALLTHROUGH */ 1835 default: 1836 goto swcsum; 1837 } 1838 1839 /* the uncomplemented sum is expected */ 1840 m->m_pkthdr.csum_data = (~rxstat) & GEM_RD_CHECKSUM; 1841 1842 /* if the pkt had ip options, we have to deduct them */ 1843 if (hlen > sizeof(struct ip)) { 1844 uint16_t *opts; 1845 uint32_t optsum, temp; 1846 1847 optsum = 0; 1848 temp = hlen - sizeof(struct ip); 1849 opts = (uint16_t *) ((char *) ip + 1850 sizeof(struct ip)); 1851 1852 while (temp > 1) { 1853 optsum += ntohs(*opts++); 1854 temp -= 2; 1855 } 1856 while (optsum >> 16) 1857 optsum = (optsum >> 16) + 1858 (optsum & 0xffff); 1859 1860 /* Deduct ip opts sum from hwsum (rfc 1624). */ 1861 m->m_pkthdr.csum_data = 1862 ~((~m->m_pkthdr.csum_data) - ~optsum); 1863 1864 while (m->m_pkthdr.csum_data >> 16) 1865 m->m_pkthdr.csum_data = 1866 (m->m_pkthdr.csum_data >> 16) + 1867 (m->m_pkthdr.csum_data & 1868 0xffff); 1869 } 1870 1871 m->m_pkthdr.csum_flags |= M_CSUM_DATA | 1872 M_CSUM_NO_PSEUDOHDR; 1873 } else 1874 swcsum: 1875 m->m_pkthdr.csum_flags = 0; 1876 #endif 1877 /* Pass it on. */ 1878 (*ifp->if_input)(ifp, m); 1879 } 1880 1881 if (progress) { 1882 /* Update the receive pointer. */ 1883 if (i == sc->sc_rxptr) { 1884 GEM_COUNTER_INCR(sc, sc_ev_rxfull); 1885 #ifdef GEM_DEBUG 1886 if (ifp->if_flags & IFF_DEBUG) 1887 printf("%s: rint: ring wrap\n", 1888 sc->sc_dev.dv_xname); 1889 #endif 1890 } 1891 sc->sc_rxptr = i; 1892 bus_space_write_4(t, h, GEM_RX_KICK, GEM_PREVRX(i)); 1893 } 1894 #ifdef GEM_COUNTERS 1895 if (progress <= 4) { 1896 GEM_COUNTER_INCR(sc, sc_ev_rxhist[progress]); 1897 } else if (progress < 32) { 1898 if (progress < 16) 1899 GEM_COUNTER_INCR(sc, sc_ev_rxhist[5]); 1900 else 1901 GEM_COUNTER_INCR(sc, sc_ev_rxhist[6]); 1902 1903 } else { 1904 if (progress < 64) 1905 GEM_COUNTER_INCR(sc, sc_ev_rxhist[7]); 1906 else 1907 GEM_COUNTER_INCR(sc, sc_ev_rxhist[8]); 1908 } 1909 #endif 1910 1911 DPRINTF(sc, ("gem_rint: done sc->rxptr %d, complete %d\n", 1912 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION))); 1913 1914 return (1); 1915 } 1916 1917 1918 /* 1919 * gem_add_rxbuf: 1920 * 1921 * Add a receive buffer to the indicated descriptor. 1922 */ 1923 int 1924 gem_add_rxbuf(struct gem_softc *sc, int idx) 1925 { 1926 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1927 struct mbuf *m; 1928 int error; 1929 1930 MGETHDR(m, M_DONTWAIT, MT_DATA); 1931 if (m == NULL) 1932 return (ENOBUFS); 1933 1934 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1935 MCLGET(m, M_DONTWAIT); 1936 if ((m->m_flags & M_EXT) == 0) { 1937 m_freem(m); 1938 return (ENOBUFS); 1939 } 1940 1941 #ifdef GEM_DEBUG 1942 /* bzero the packet to check DMA */ 1943 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 1944 #endif 1945 1946 if (rxs->rxs_mbuf != NULL) 1947 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 1948 1949 rxs->rxs_mbuf = m; 1950 1951 error = bus_dmamap_load(sc->sc_dmatag, rxs->rxs_dmamap, 1952 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1953 BUS_DMA_READ|BUS_DMA_NOWAIT); 1954 if (error) { 1955 printf("%s: can't load rx DMA map %d, error = %d\n", 1956 sc->sc_dev.dv_xname, idx, error); 1957 panic("gem_add_rxbuf"); /* XXX */ 1958 } 1959 1960 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1961 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1962 1963 GEM_INIT_RXDESC(sc, idx); 1964 1965 return (0); 1966 } 1967 1968 1969 int 1970 gem_eint(struct gem_softc *sc, u_int status) 1971 { 1972 char bits[128]; 1973 u_int32_t v; 1974 1975 if ((status & GEM_INTR_MIF) != 0) { 1976 printf("%s: XXXlink status changed\n", sc->sc_dev.dv_xname); 1977 return (1); 1978 } 1979 1980 if ((status & GEM_INTR_RX_TAG_ERR) != 0) { 1981 gem_reset_rxdma(sc); 1982 return (1); 1983 } 1984 1985 if (status & GEM_INTR_BERR) { 1986 bus_space_read_4(sc->sc_bustag, sc->sc_h2, GEM_ERROR_STATUS); 1987 v = bus_space_read_4(sc->sc_bustag, sc->sc_h2, 1988 GEM_ERROR_STATUS); 1989 printf("%s: bus error interrupt: 0x%02x\n", 1990 sc->sc_dev.dv_xname, v); 1991 return (1); 1992 } 1993 1994 printf("%s: status=%s\n", sc->sc_dev.dv_xname, 1995 bitmask_snprintf(status, GEM_INTR_BITS, bits, sizeof(bits))); 1996 return (1); 1997 } 1998 1999 2000 /* 2001 * PCS interrupts. 2002 * We should receive these when the link status changes, but sometimes 2003 * we don't receive them for link up. We compensate for this in the 2004 * gem_tick() callout. 2005 */ 2006 int 2007 gem_pint(struct gem_softc *sc) 2008 { 2009 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2010 bus_space_tag_t t = sc->sc_bustag; 2011 bus_space_handle_t h = sc->sc_h1; 2012 u_int32_t v, v2; 2013 2014 /* 2015 * Clear the PCS interrupt from GEM_STATUS. The PCS register is 2016 * latched, so we have to read it twice. There is only one bit in 2017 * use, so the value is meaningless. 2018 */ 2019 bus_space_read_4(t, h, GEM_MII_INTERRUP_STATUS); 2020 bus_space_read_4(t, h, GEM_MII_INTERRUP_STATUS); 2021 2022 if ((ifp->if_flags & IFF_UP) == 0) 2023 return 1; 2024 2025 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) 2026 return 1; 2027 2028 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2029 /* If we see remote fault, our link partner is probably going away */ 2030 if ((v & GEM_MII_STATUS_REM_FLT) != 0) { 2031 gem_bitwait(sc, h, GEM_MII_STATUS, GEM_MII_STATUS_REM_FLT, 0); 2032 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2033 /* Otherwise, we may need to wait after auto-negotiation completes */ 2034 } else if ((v & (GEM_MII_STATUS_LINK_STS | GEM_MII_STATUS_ANEG_CPT)) == 2035 GEM_MII_STATUS_ANEG_CPT) { 2036 gem_bitwait(sc, h, GEM_MII_STATUS, 0, GEM_MII_STATUS_LINK_STS); 2037 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2038 } 2039 if ((v & GEM_MII_STATUS_LINK_STS) != 0) { 2040 if (sc->sc_flags & GEM_LINK) { 2041 return 1; 2042 } 2043 callout_stop(&sc->sc_tick_ch); 2044 v = bus_space_read_4(t, h, GEM_MII_ANAR); 2045 v2 = bus_space_read_4(t, h, GEM_MII_ANLPAR); 2046 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_1000_SX; 2047 sc->sc_mii.mii_media_status = IFM_AVALID | IFM_ACTIVE; 2048 v &= v2; 2049 if (v & GEM_MII_ANEG_FUL_DUPLX) { 2050 sc->sc_mii.mii_media_active |= IFM_FDX; 2051 #ifdef GEM_DEBUG 2052 aprint_debug("%s: link up: full duplex\n", 2053 sc->sc_dev.dv_xname); 2054 #endif 2055 } else if (v & GEM_MII_ANEG_HLF_DUPLX) { 2056 sc->sc_mii.mii_media_active |= IFM_HDX; 2057 #ifdef GEM_DEBUG 2058 aprint_debug("%s: link up: half duplex\n", 2059 sc->sc_dev.dv_xname); 2060 #endif 2061 } else { 2062 #ifdef GEM_DEBUG 2063 aprint_debug("%s: duplex mismatch\n", 2064 sc->sc_dev.dv_xname); 2065 #endif 2066 } 2067 gem_statuschange(sc); 2068 } else { 2069 if ((sc->sc_flags & GEM_LINK) == 0) { 2070 return 1; 2071 } 2072 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_NONE; 2073 sc->sc_mii.mii_media_status = IFM_AVALID; 2074 #ifdef GEM_DEBUG 2075 aprint_debug("%s: link down\n", 2076 sc->sc_dev.dv_xname); 2077 #endif 2078 gem_statuschange(sc); 2079 2080 /* Start the 10 second timer */ 2081 callout_reset(&sc->sc_tick_ch, hz * 10, gem_tick, sc); 2082 } 2083 return 1; 2084 } 2085 2086 2087 2088 int 2089 gem_intr(v) 2090 void *v; 2091 { 2092 struct gem_softc *sc = (struct gem_softc *)v; 2093 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2094 bus_space_tag_t t = sc->sc_bustag; 2095 bus_space_handle_t h = sc->sc_h1; 2096 u_int32_t status; 2097 int r = 0; 2098 #ifdef GEM_DEBUG 2099 char bits[128]; 2100 #endif 2101 2102 /* XXX We should probably mask out interrupts until we're done */ 2103 2104 sc->sc_ev_intr.ev_count++; 2105 2106 status = bus_space_read_4(t, h, GEM_STATUS); 2107 DPRINTF(sc, ("%s: gem_intr: cplt 0x%x status %s\n", 2108 sc->sc_dev.dv_xname, (status >> 19), 2109 bitmask_snprintf(status, GEM_INTR_BITS, bits, sizeof(bits)))); 2110 2111 if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0) 2112 r |= gem_eint(sc, status); 2113 2114 /* We don't bother with GEM_INTR_TX_DONE */ 2115 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) { 2116 GEM_COUNTER_INCR(sc, sc_ev_txint); 2117 r |= gem_tint(sc); 2118 } 2119 2120 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) { 2121 GEM_COUNTER_INCR(sc, sc_ev_rxint); 2122 r |= gem_rint(sc); 2123 } 2124 2125 /* We should eventually do more than just print out error stats. */ 2126 if (status & GEM_INTR_TX_MAC) { 2127 int txstat = bus_space_read_4(t, h, GEM_MAC_TX_STATUS); 2128 if (txstat & ~GEM_MAC_TX_XMIT_DONE) 2129 printf("%s: MAC tx fault, status %x\n", 2130 sc->sc_dev.dv_xname, txstat); 2131 if (txstat & (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG)) 2132 gem_init(ifp); 2133 } 2134 if (status & GEM_INTR_RX_MAC) { 2135 int rxstat = bus_space_read_4(t, h, GEM_MAC_RX_STATUS); 2136 if (rxstat & ~GEM_MAC_RX_DONE) 2137 printf("%s: MAC rx fault, status %x\n", 2138 sc->sc_dev.dv_xname, rxstat); 2139 /* 2140 * At least with GEM_SUN_GEM and some GEM_SUN_ERI 2141 * revisions GEM_MAC_RX_OVERFLOW happen often due to a 2142 * silicon bug so handle them silently. Moreover, it's 2143 * likely that the receiver has hung so we reset it. 2144 */ 2145 if (rxstat & GEM_MAC_RX_OVERFLOW) { 2146 ifp->if_ierrors++; 2147 gem_reset_rxdma(sc); 2148 } else if (rxstat & ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT)) 2149 printf("%s: MAC rx fault, status %x\n", 2150 sc->sc_dev.dv_xname, rxstat); 2151 } 2152 if (status & GEM_INTR_PCS) { 2153 r |= gem_pint(sc); 2154 } 2155 2156 /* Do we need to do anything with these? 2157 if ((status & GEM_MAC_CONTROL_STATUS) != 0) { 2158 status2 = bus_read_4(sc->sc_res[0], GEM_MAC_CONTROL_STATUS); 2159 if ((status2 & GEM_MAC_PAUSED) != 0) 2160 aprintf_debug("%s: PAUSE received (%d slots)\n", 2161 GEM_MAC_PAUSE_TIME(status2), sc->sc_dev.dv_xname); 2162 if ((status2 & GEM_MAC_PAUSE) != 0) 2163 aprintf_debug("%s: transited to PAUSE state\n", 2164 sc->sc_dev.dv_xname); 2165 if ((status2 & GEM_MAC_RESUME) != 0) 2166 aprintf_debug("%s: transited to non-PAUSE state\n", 2167 sc->sc_dev.dv_xname); 2168 } 2169 if ((status & GEM_INTR_MIF) != 0) 2170 aprintf_debug("%s: MIF interrupt\n", sc->sc_dev.dv_xname); 2171 */ 2172 #if NRND > 0 2173 rnd_add_uint32(&sc->rnd_source, status); 2174 #endif 2175 return (r); 2176 } 2177 2178 2179 void 2180 gem_watchdog(ifp) 2181 struct ifnet *ifp; 2182 { 2183 struct gem_softc *sc = ifp->if_softc; 2184 2185 DPRINTF(sc, ("gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x " 2186 "GEM_MAC_RX_CONFIG %x\n", 2187 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_RX_CONFIG), 2188 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_MAC_RX_STATUS), 2189 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_MAC_RX_CONFIG))); 2190 2191 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 2192 ++ifp->if_oerrors; 2193 2194 /* Try to get more packets going. */ 2195 gem_start(ifp); 2196 } 2197 2198 /* 2199 * Initialize the MII Management Interface 2200 */ 2201 void 2202 gem_mifinit(sc) 2203 struct gem_softc *sc; 2204 { 2205 bus_space_tag_t t = sc->sc_bustag; 2206 bus_space_handle_t mif = sc->sc_h1; 2207 2208 /* Configure the MIF in frame mode */ 2209 sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 2210 sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA; 2211 bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config); 2212 } 2213 2214 /* 2215 * MII interface 2216 * 2217 * The GEM MII interface supports at least three different operating modes: 2218 * 2219 * Bitbang mode is implemented using data, clock and output enable registers. 2220 * 2221 * Frame mode is implemented by loading a complete frame into the frame 2222 * register and polling the valid bit for completion. 2223 * 2224 * Polling mode uses the frame register but completion is indicated by 2225 * an interrupt. 2226 * 2227 */ 2228 static int 2229 gem_mii_readreg(self, phy, reg) 2230 struct device *self; 2231 int phy, reg; 2232 { 2233 struct gem_softc *sc = (void *)self; 2234 bus_space_tag_t t = sc->sc_bustag; 2235 bus_space_handle_t mif = sc->sc_h1; 2236 int n; 2237 u_int32_t v; 2238 2239 #ifdef GEM_DEBUG1 2240 if (sc->sc_debug) 2241 printf("gem_mii_readreg: PHY %d reg %d\n", phy, reg); 2242 #endif 2243 2244 /* Construct the frame command */ 2245 v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) | 2246 GEM_MIF_FRAME_READ; 2247 2248 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 2249 for (n = 0; n < 100; n++) { 2250 DELAY(1); 2251 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 2252 if (v & GEM_MIF_FRAME_TA0) 2253 return (v & GEM_MIF_FRAME_DATA); 2254 } 2255 2256 printf("%s: mii_read timeout\n", sc->sc_dev.dv_xname); 2257 return (0); 2258 } 2259 2260 static void 2261 gem_mii_writereg(self, phy, reg, val) 2262 struct device *self; 2263 int phy, reg, val; 2264 { 2265 struct gem_softc *sc = (void *)self; 2266 bus_space_tag_t t = sc->sc_bustag; 2267 bus_space_handle_t mif = sc->sc_h1; 2268 int n; 2269 u_int32_t v; 2270 2271 #ifdef GEM_DEBUG1 2272 if (sc->sc_debug) 2273 printf("gem_mii_writereg: PHY %d reg %d val %x\n", 2274 phy, reg, val); 2275 #endif 2276 2277 /* Construct the frame command */ 2278 v = GEM_MIF_FRAME_WRITE | 2279 (phy << GEM_MIF_PHY_SHIFT) | 2280 (reg << GEM_MIF_REG_SHIFT) | 2281 (val & GEM_MIF_FRAME_DATA); 2282 2283 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 2284 for (n = 0; n < 100; n++) { 2285 DELAY(1); 2286 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 2287 if (v & GEM_MIF_FRAME_TA0) 2288 return; 2289 } 2290 2291 printf("%s: mii_write timeout\n", sc->sc_dev.dv_xname); 2292 } 2293 2294 static void 2295 gem_mii_statchg(dev) 2296 struct device *dev; 2297 { 2298 struct gem_softc *sc = (void *)dev; 2299 #ifdef GEM_DEBUG 2300 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 2301 #endif 2302 2303 #ifdef GEM_DEBUG 2304 if (sc->sc_debug) 2305 printf("gem_mii_statchg: status change: phy = %d\n", 2306 sc->sc_phys[instance]); 2307 #endif 2308 gem_statuschange(sc); 2309 } 2310 2311 /* 2312 * Common status change for gem_mii_statchg() and gem_pint() 2313 */ 2314 void 2315 gem_statuschange(struct gem_softc* sc) 2316 { 2317 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2318 bus_space_tag_t t = sc->sc_bustag; 2319 bus_space_handle_t mac = sc->sc_h1; 2320 int gigabit; 2321 u_int32_t rxcfg, txcfg, v; 2322 2323 if ((sc->sc_mii.mii_media_status & IFM_ACTIVE) != 0 && 2324 IFM_SUBTYPE(sc->sc_mii.mii_media_active) != IFM_NONE) 2325 sc->sc_flags |= GEM_LINK; 2326 else 2327 sc->sc_flags &= ~GEM_LINK; 2328 2329 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 2330 gigabit = 1; 2331 else 2332 gigabit = 0; 2333 2334 /* 2335 * The configuration done here corresponds to the steps F) and 2336 * G) and as far as enabling of RX and TX MAC goes also step H) 2337 * of the initialization sequence outlined in section 3.2.1 of 2338 * the GEM Gigabit Ethernet ASIC Specification. 2339 */ 2340 2341 rxcfg = bus_space_read_4(t, mac, GEM_MAC_RX_CONFIG); 2342 rxcfg &= ~(GEM_MAC_RX_CARR_EXTEND | GEM_MAC_RX_ENABLE); 2343 txcfg = GEM_MAC_TX_ENA_IPG0 | GEM_MAC_TX_NGU | GEM_MAC_TX_NGU_LIMIT; 2344 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 2345 txcfg |= GEM_MAC_TX_IGN_CARRIER | GEM_MAC_TX_IGN_COLLIS; 2346 else if (gigabit) { 2347 rxcfg |= GEM_MAC_RX_CARR_EXTEND; 2348 txcfg |= GEM_MAC_RX_CARR_EXTEND; 2349 } 2350 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0); 2351 bus_space_barrier(t, mac, GEM_MAC_TX_CONFIG, 4, 2352 BUS_SPACE_BARRIER_WRITE); 2353 if (!gem_bitwait(sc, mac, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)) 2354 aprint_normal("%s: cannot disable TX MAC\n", 2355 sc->sc_dev.dv_xname); 2356 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, txcfg); 2357 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, 0); 2358 bus_space_barrier(t, mac, GEM_MAC_RX_CONFIG, 4, 2359 BUS_SPACE_BARRIER_WRITE); 2360 if (!gem_bitwait(sc, mac, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)) 2361 aprint_normal("%s: cannot disable RX MAC\n", 2362 sc->sc_dev.dv_xname); 2363 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, rxcfg); 2364 2365 v = bus_space_read_4(t, mac, GEM_MAC_CONTROL_CONFIG) & 2366 ~(GEM_MAC_CC_RX_PAUSE | GEM_MAC_CC_TX_PAUSE); 2367 bus_space_write_4(t, mac, GEM_MAC_CONTROL_CONFIG, v); 2368 2369 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) == 0 && 2370 gigabit != 0) 2371 bus_space_write_4(t, mac, GEM_MAC_SLOT_TIME, 2372 GEM_MAC_SLOT_TIME_CARR_EXTEND); 2373 else 2374 bus_space_write_4(t, mac, GEM_MAC_SLOT_TIME, 2375 GEM_MAC_SLOT_TIME_NORMAL); 2376 2377 /* XIF Configuration */ 2378 if (sc->sc_flags & GEM_LINK) 2379 v = GEM_MAC_XIF_LINK_LED; 2380 else 2381 v = 0; 2382 v |= GEM_MAC_XIF_TX_MII_ENA; 2383 2384 /* If an external transceiver is connected, enable its MII drivers */ 2385 sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG); 2386 if ((sc->sc_flags &(GEM_SERDES | GEM_SERIAL)) == 0) { 2387 if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) { 2388 /* External MII needs echo disable if half duplex. */ 2389 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & 2390 IFM_FDX) != 0) 2391 /* turn on full duplex LED */ 2392 v |= GEM_MAC_XIF_FDPLX_LED; 2393 else 2394 /* half duplex -- disable echo */ 2395 v |= GEM_MAC_XIF_ECHO_DISABL; 2396 if (gigabit) 2397 v |= GEM_MAC_XIF_GMII_MODE; 2398 else 2399 v &= ~GEM_MAC_XIF_GMII_MODE; 2400 } else 2401 /* Internal MII needs buf enable */ 2402 v |= GEM_MAC_XIF_MII_BUF_ENA; 2403 } else { 2404 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 2405 v |= GEM_MAC_XIF_FDPLX_LED; 2406 v |= GEM_MAC_XIF_GMII_MODE; 2407 } 2408 bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v); 2409 2410 if ((ifp->if_flags & IFF_RUNNING) != 0 && 2411 (sc->sc_flags & GEM_LINK) != 0) { 2412 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 2413 txcfg | GEM_MAC_TX_ENABLE); 2414 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, 2415 rxcfg | GEM_MAC_RX_ENABLE); 2416 } 2417 } 2418 2419 int 2420 gem_ser_mediachange(struct ifnet *ifp) 2421 { 2422 struct gem_softc *sc = ifp->if_softc; 2423 u_int s, t; 2424 2425 if (IFM_TYPE(sc->sc_mii.mii_media.ifm_media) != IFM_ETHER) 2426 return EINVAL; 2427 2428 s = IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media); 2429 if (s == IFM_AUTO) { 2430 if (sc->sc_mii_media != s) { 2431 #ifdef GEM_DEBUG 2432 aprint_debug("%s: setting media to auto\n", 2433 sc->sc_dev.dv_xname); 2434 #endif 2435 sc->sc_mii_media = s; 2436 if (ifp->if_flags & IFF_UP) { 2437 gem_pcs_stop(sc, 0); 2438 gem_pcs_start(sc); 2439 } 2440 } 2441 return 0; 2442 } 2443 if (s == IFM_1000_SX) { 2444 t = IFM_OPTIONS(sc->sc_mii.mii_media.ifm_media); 2445 if (t == IFM_FDX || t == IFM_HDX) { 2446 if (sc->sc_mii_media != t) { 2447 sc->sc_mii_media = t; 2448 #ifdef GEM_DEBUG 2449 aprint_debug("%s:" 2450 " setting media to 1000baseSX-%s\n", 2451 sc->sc_dev.dv_xname, 2452 t == IFM_FDX ? "FDX" : "HDX"); 2453 #endif 2454 if (ifp->if_flags & IFF_UP) { 2455 gem_pcs_stop(sc, 0); 2456 gem_pcs_start(sc); 2457 } 2458 } 2459 return 0; 2460 } 2461 } 2462 return EINVAL; 2463 } 2464 2465 void 2466 gem_ser_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2467 { 2468 struct gem_softc *sc = ifp->if_softc; 2469 2470 if ((ifp->if_flags & IFF_UP) == 0) 2471 return; 2472 ifmr->ifm_active = sc->sc_mii.mii_media_active; 2473 ifmr->ifm_status = sc->sc_mii.mii_media_status; 2474 } 2475 2476 /* 2477 * Process an ioctl request. 2478 */ 2479 int 2480 gem_ioctl(ifp, cmd, data) 2481 struct ifnet *ifp; 2482 u_long cmd; 2483 void *data; 2484 { 2485 struct gem_softc *sc = ifp->if_softc; 2486 int s, error = 0; 2487 2488 s = splnet(); 2489 2490 switch (cmd) { 2491 case SIOCSIFFLAGS: 2492 #define RESETIGN (IFF_CANTCHANGE|IFF_DEBUG) 2493 if (((ifp->if_flags & (IFF_UP|IFF_RUNNING)) 2494 == (IFF_UP|IFF_RUNNING)) 2495 && ((ifp->if_flags & (~RESETIGN)) 2496 == (sc->sc_if_flags & (~RESETIGN)))) { 2497 gem_setladrf(sc); 2498 break; 2499 } 2500 #undef RESETIGN 2501 /*FALLTHROUGH*/ 2502 default: 2503 error = ether_ioctl(ifp, cmd, data); 2504 if (error == ENETRESET) { 2505 /* 2506 * Multicast list has changed; set the hardware filter 2507 * accordingly. 2508 */ 2509 if (ifp->if_flags & IFF_RUNNING) 2510 gem_setladrf(sc); 2511 error = 0; 2512 } 2513 break; 2514 } 2515 2516 /* Try to get things going again */ 2517 if (ifp->if_flags & IFF_UP) 2518 gem_start(ifp); 2519 splx(s); 2520 return (error); 2521 } 2522 2523 2524 void 2525 gem_shutdown(arg) 2526 void *arg; 2527 { 2528 struct gem_softc *sc = (struct gem_softc *)arg; 2529 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2530 2531 gem_stop(ifp, 1); 2532 } 2533 2534 /* 2535 * Set up the logical address filter. 2536 */ 2537 void 2538 gem_setladrf(sc) 2539 struct gem_softc *sc; 2540 { 2541 struct ethercom *ec = &sc->sc_ethercom; 2542 struct ifnet *ifp = &ec->ec_if; 2543 struct ether_multi *enm; 2544 struct ether_multistep step; 2545 bus_space_tag_t t = sc->sc_bustag; 2546 bus_space_handle_t h = sc->sc_h1; 2547 u_int32_t crc; 2548 u_int32_t hash[16]; 2549 u_int32_t v; 2550 int i; 2551 2552 /* Get current RX configuration */ 2553 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 2554 2555 /* 2556 * Turn off promiscuous mode, promiscuous group mode (all multicast), 2557 * and hash filter. Depending on the case, the right bit will be 2558 * enabled. 2559 */ 2560 v &= ~(GEM_MAC_RX_PROMISCUOUS|GEM_MAC_RX_HASH_FILTER| 2561 GEM_MAC_RX_PROMISC_GRP); 2562 2563 if ((ifp->if_flags & IFF_PROMISC) != 0) { 2564 /* Turn on promiscuous mode */ 2565 v |= GEM_MAC_RX_PROMISCUOUS; 2566 ifp->if_flags |= IFF_ALLMULTI; 2567 goto chipit; 2568 } 2569 2570 /* 2571 * Set up multicast address filter by passing all multicast addresses 2572 * through a crc generator, and then using the high order 8 bits as an 2573 * index into the 256 bit logical address filter. The high order 4 2574 * bits selects the word, while the other 4 bits select the bit within 2575 * the word (where bit 0 is the MSB). 2576 */ 2577 2578 /* Clear hash table */ 2579 memset(hash, 0, sizeof(hash)); 2580 2581 ETHER_FIRST_MULTI(step, ec, enm); 2582 while (enm != NULL) { 2583 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2584 /* 2585 * We must listen to a range of multicast addresses. 2586 * For now, just accept all multicasts, rather than 2587 * trying to set only those filter bits needed to match 2588 * the range. (At this time, the only use of address 2589 * ranges is for IP multicast routing, for which the 2590 * range is big enough to require all bits set.) 2591 * XXX should use the address filters for this 2592 */ 2593 ifp->if_flags |= IFF_ALLMULTI; 2594 v |= GEM_MAC_RX_PROMISC_GRP; 2595 goto chipit; 2596 } 2597 2598 /* Get the LE CRC32 of the address */ 2599 crc = ether_crc32_le(enm->enm_addrlo, sizeof(enm->enm_addrlo)); 2600 2601 /* Just want the 8 most significant bits. */ 2602 crc >>= 24; 2603 2604 /* Set the corresponding bit in the filter. */ 2605 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 2606 2607 ETHER_NEXT_MULTI(step, enm); 2608 } 2609 2610 v |= GEM_MAC_RX_HASH_FILTER; 2611 ifp->if_flags &= ~IFF_ALLMULTI; 2612 2613 /* Now load the hash table into the chip (if we are using it) */ 2614 for (i = 0; i < 16; i++) { 2615 bus_space_write_4(t, h, 2616 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1-GEM_MAC_HASH0), 2617 hash[i]); 2618 } 2619 2620 chipit: 2621 sc->sc_if_flags = ifp->if_flags; 2622 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 2623 } 2624 2625 #if notyet 2626 2627 /* 2628 * gem_power: 2629 * 2630 * Power management (suspend/resume) hook. 2631 */ 2632 void 2633 gem_power(why, arg) 2634 int why; 2635 void *arg; 2636 { 2637 struct gem_softc *sc = arg; 2638 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2639 int s; 2640 2641 s = splnet(); 2642 switch (why) { 2643 case PWR_SUSPEND: 2644 case PWR_STANDBY: 2645 gem_stop(ifp, 1); 2646 if (sc->sc_power != NULL) 2647 (*sc->sc_power)(sc, why); 2648 break; 2649 case PWR_RESUME: 2650 if (ifp->if_flags & IFF_UP) { 2651 if (sc->sc_power != NULL) 2652 (*sc->sc_power)(sc, why); 2653 gem_init(ifp); 2654 } 2655 break; 2656 case PWR_SOFTSUSPEND: 2657 case PWR_SOFTSTANDBY: 2658 case PWR_SOFTRESUME: 2659 break; 2660 } 2661 splx(s); 2662 } 2663 #endif 2664
Indexes created Tue Sep 23 07:09:52 GMT 2025