gem.c revision 1.74
1 /* $NetBSD: gem.c,v 1.74 2008/02/07 01:21:53 dyoung Exp $ */ 2 3 /* 4 * 5 * Copyright (C) 2001 Eduardo Horvath. 6 * Copyright (c) 2001-2003 Thomas Moestl 7 * All rights reserved. 8 * 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 */ 32 33 /* 34 * Driver for Apple GMAC, Sun ERI and Sun GEM Ethernet controllers 35 * See `GEM Gigabit Ethernet ASIC Specification' 36 * http://www.sun.com/processors/manuals/ge.pdf 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: gem.c,v 1.74 2008/02/07 01:21:53 dyoung Exp $"); 41 42 #include "opt_inet.h" 43 #include "bpfilter.h" 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/callout.h> 48 #include <sys/mbuf.h> 49 #include <sys/syslog.h> 50 #include <sys/malloc.h> 51 #include <sys/kernel.h> 52 #include <sys/socket.h> 53 #include <sys/ioctl.h> 54 #include <sys/errno.h> 55 #include <sys/device.h> 56 57 #include <machine/endian.h> 58 59 #include <uvm/uvm_extern.h> 60 61 #include <net/if.h> 62 #include <net/if_dl.h> 63 #include <net/if_media.h> 64 #include <net/if_ether.h> 65 66 #ifdef INET 67 #include <netinet/in.h> 68 #include <netinet/in_systm.h> 69 #include <netinet/in_var.h> 70 #include <netinet/ip.h> 71 #include <netinet/tcp.h> 72 #include <netinet/udp.h> 73 #endif 74 75 #if NBPFILTER > 0 76 #include <net/bpf.h> 77 #endif 78 79 #include <sys/bus.h> 80 #include <sys/intr.h> 81 82 #include <dev/mii/mii.h> 83 #include <dev/mii/miivar.h> 84 #include <dev/mii/mii_bitbang.h> 85 86 #include <dev/ic/gemreg.h> 87 #include <dev/ic/gemvar.h> 88 89 #define TRIES 10000 90 91 static void gem_start(struct ifnet *); 92 static void gem_stop(struct ifnet *, int); 93 int gem_ioctl(struct ifnet *, u_long, void *); 94 void gem_tick(void *); 95 void gem_watchdog(struct ifnet *); 96 void gem_shutdown(void *); 97 void gem_pcs_start(struct gem_softc *sc); 98 void gem_pcs_stop(struct gem_softc *sc, int); 99 int gem_init(struct ifnet *); 100 void gem_init_regs(struct gem_softc *sc); 101 static int gem_ringsize(int sz); 102 static int gem_meminit(struct gem_softc *); 103 void gem_mifinit(struct gem_softc *); 104 static int gem_bitwait(struct gem_softc *sc, bus_space_handle_t, int, 105 u_int32_t, u_int32_t); 106 void gem_reset(struct gem_softc *); 107 int gem_reset_rx(struct gem_softc *sc); 108 static void gem_reset_rxdma(struct gem_softc *sc); 109 static void gem_rx_common(struct gem_softc *sc); 110 int gem_reset_tx(struct gem_softc *sc); 111 int gem_disable_rx(struct gem_softc *sc); 112 int gem_disable_tx(struct gem_softc *sc); 113 static void gem_rxdrain(struct gem_softc *sc); 114 int gem_add_rxbuf(struct gem_softc *sc, int idx); 115 void gem_setladrf(struct gem_softc *); 116 117 /* MII methods & callbacks */ 118 static int gem_mii_readreg(struct device *, int, int); 119 static void gem_mii_writereg(struct device *, int, int, int); 120 static void gem_mii_statchg(struct device *); 121 122 void gem_statuschange(struct gem_softc *); 123 124 int gem_ser_mediachange(struct ifnet *); 125 void gem_ser_mediastatus(struct ifnet *, struct ifmediareq *); 126 127 struct mbuf *gem_get(struct gem_softc *, int, int); 128 int gem_put(struct gem_softc *, int, struct mbuf *); 129 void gem_read(struct gem_softc *, int, int); 130 int gem_pint(struct gem_softc *); 131 int gem_eint(struct gem_softc *, u_int); 132 int gem_rint(struct gem_softc *); 133 int gem_tint(struct gem_softc *); 134 void gem_power(int, void *); 135 136 #ifdef GEM_DEBUG 137 static void gem_txsoft_print(const struct gem_softc *, int, int); 138 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 139 printf x 140 #else 141 #define DPRINTF(sc, x) /* nothing */ 142 #endif 143 144 #define ETHER_MIN_TX (ETHERMIN + sizeof(struct ether_header)) 145 146 147 /* 148 * gem_attach: 149 * 150 * Attach a Gem interface to the system. 151 */ 152 void 153 gem_attach(sc, enaddr) 154 struct gem_softc *sc; 155 const uint8_t *enaddr; 156 { 157 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 158 struct mii_data *mii = &sc->sc_mii; 159 bus_space_tag_t t = sc->sc_bustag; 160 bus_space_handle_t h = sc->sc_h1; 161 struct ifmedia_entry *ifm; 162 int i, error; 163 u_int32_t v; 164 char *nullbuf; 165 166 /* Make sure the chip is stopped. */ 167 ifp->if_softc = sc; 168 gem_reset(sc); 169 170 /* 171 * Allocate the control data structures, and create and load the 172 * DMA map for it. gem_control_data is 9216 bytes, we have space for 173 * the padding buffer in the bus_dmamem_alloc()'d memory. 174 */ 175 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 176 sizeof(struct gem_control_data) + ETHER_MIN_TX, PAGE_SIZE, 177 0, &sc->sc_cdseg, 1, &sc->sc_cdnseg, 0)) != 0) { 178 aprint_error( 179 "%s: unable to allocate control data, error = %d\n", 180 sc->sc_dev.dv_xname, error); 181 goto fail_0; 182 } 183 184 /* XXX should map this in with correct endianness */ 185 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg, 186 sizeof(struct gem_control_data), (void **)&sc->sc_control_data, 187 BUS_DMA_COHERENT)) != 0) { 188 aprint_error("%s: unable to map control data, error = %d\n", 189 sc->sc_dev.dv_xname, error); 190 goto fail_1; 191 } 192 193 nullbuf = 194 (char *)sc->sc_control_data + sizeof(struct gem_control_data); 195 196 if ((error = bus_dmamap_create(sc->sc_dmatag, 197 sizeof(struct gem_control_data), 1, 198 sizeof(struct gem_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 199 aprint_error("%s: unable to create control data DMA map, " 200 "error = %d\n", sc->sc_dev.dv_xname, error); 201 goto fail_2; 202 } 203 204 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 205 sc->sc_control_data, sizeof(struct gem_control_data), NULL, 206 0)) != 0) { 207 aprint_error( 208 "%s: unable to load control data DMA map, error = %d\n", 209 sc->sc_dev.dv_xname, error); 210 goto fail_3; 211 } 212 213 memset(nullbuf, 0, ETHER_MIN_TX); 214 if ((error = bus_dmamap_create(sc->sc_dmatag, 215 ETHER_MIN_TX, 1, ETHER_MIN_TX, 0, 0, &sc->sc_nulldmamap)) != 0) { 216 aprint_error("%s: unable to create padding DMA map, " 217 "error = %d\n", sc->sc_dev.dv_xname, error); 218 goto fail_4; 219 } 220 221 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_nulldmamap, 222 nullbuf, ETHER_MIN_TX, NULL, 0)) != 0) { 223 aprint_error( 224 "%s: unable to load padding DMA map, error = %d\n", 225 sc->sc_dev.dv_xname, error); 226 goto fail_5; 227 } 228 229 bus_dmamap_sync(sc->sc_dmatag, sc->sc_nulldmamap, 0, ETHER_MIN_TX, 230 BUS_DMASYNC_PREWRITE); 231 232 /* 233 * Initialize the transmit job descriptors. 234 */ 235 SIMPLEQ_INIT(&sc->sc_txfreeq); 236 SIMPLEQ_INIT(&sc->sc_txdirtyq); 237 238 /* 239 * Create the transmit buffer DMA maps. 240 */ 241 for (i = 0; i < GEM_TXQUEUELEN; i++) { 242 struct gem_txsoft *txs; 243 244 txs = &sc->sc_txsoft[i]; 245 txs->txs_mbuf = NULL; 246 if ((error = bus_dmamap_create(sc->sc_dmatag, 247 ETHER_MAX_LEN_JUMBO, GEM_NTXSEGS, 248 ETHER_MAX_LEN_JUMBO, 0, 0, 249 &txs->txs_dmamap)) != 0) { 250 aprint_error("%s: unable to create tx DMA map %d, " 251 "error = %d\n", sc->sc_dev.dv_xname, i, error); 252 goto fail_6; 253 } 254 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 255 } 256 257 /* 258 * Create the receive buffer DMA maps. 259 */ 260 for (i = 0; i < GEM_NRXDESC; i++) { 261 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, 262 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 263 aprint_error("%s: unable to create rx DMA map %d, " 264 "error = %d\n", sc->sc_dev.dv_xname, i, error); 265 goto fail_7; 266 } 267 sc->sc_rxsoft[i].rxs_mbuf = NULL; 268 } 269 270 /* Initialize ifmedia structures and MII info */ 271 mii->mii_ifp = ifp; 272 mii->mii_readreg = gem_mii_readreg; 273 mii->mii_writereg = gem_mii_writereg; 274 mii->mii_statchg = gem_mii_statchg; 275 276 sc->sc_ethercom.ec_mii = mii; 277 278 /* 279 * Initialization based on `GEM Gigabit Ethernet ASIC Specification' 280 * Section 3.2.1 `Initialization Sequence'. 281 * However, we can't assume SERDES or Serialink if neither 282 * GEM_MIF_CONFIG_MDI0 nor GEM_MIF_CONFIG_MDI1 are set 283 * being set, as both are set on Sun X1141A (with SERDES). So, 284 * we rely on our bus attachment setting GEM_SERDES or GEM_SERIAL. 285 * Also, for Apple variants with 2 PHY's, we prefer the external 286 * PHY over the internal PHY. 287 */ 288 gem_mifinit(sc); 289 290 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) { 291 ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange, 292 ether_mediastatus); 293 mii_attach(&sc->sc_dev, mii, 0xffffffff, 294 MII_PHY_ANY, MII_OFFSET_ANY, MIIF_FORCEANEG); 295 if (LIST_EMPTY(&mii->mii_phys)) { 296 /* No PHY attached */ 297 aprint_error("%s: PHY probe failed\n", 298 sc->sc_dev.dv_xname); 299 goto fail_7; 300 } else { 301 struct mii_softc *child; 302 303 /* 304 * Walk along the list of attached MII devices and 305 * establish an `MII instance' to `PHY number' 306 * mapping. 307 */ 308 LIST_FOREACH(child, &mii->mii_phys, mii_list) { 309 /* 310 * Note: we support just one PHY: the internal 311 * or external MII is already selected for us 312 * by the GEM_MIF_CONFIG register. 313 */ 314 if (child->mii_phy > 1 || child->mii_inst > 0) { 315 aprint_error( 316 "%s: cannot accommodate MII device" 317 " %s at PHY %d, instance %d\n", 318 sc->sc_dev.dv_xname, 319 child->mii_dev.dv_xname, 320 child->mii_phy, child->mii_inst); 321 continue; 322 } 323 sc->sc_phys[child->mii_inst] = child->mii_phy; 324 } 325 326 /* 327 * Now select and activate the PHY we will use. 328 * 329 * The order of preference is External (MDI1), 330 * then Internal (MDI0), 331 */ 332 if (sc->sc_phys[1]) { 333 #ifdef GEM_DEBUG 334 aprint_debug("%s: using external PHY\n", 335 sc->sc_dev.dv_xname); 336 #endif 337 sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL; 338 } else { 339 #ifdef GEM_DEBUG 340 aprint_debug("%s: using internal PHY\n", 341 sc->sc_dev.dv_xname); 342 sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL; 343 #endif 344 } 345 bus_space_write_4(t, h, GEM_MIF_CONFIG, 346 sc->sc_mif_config); 347 if (sc->sc_variant != GEM_SUN_ERI) 348 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 349 GEM_MII_DATAPATH_MII); 350 351 /* 352 * XXX - we can really do the following ONLY if the 353 * PHY indeed has the auto negotiation capability!! 354 */ 355 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 356 } 357 } else { 358 ifmedia_init(&mii->mii_media, IFM_IMASK, gem_ser_mediachange, 359 gem_ser_mediastatus); 360 /* SERDES or Serialink */ 361 if (sc->sc_flags & GEM_SERDES) { 362 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 363 GEM_MII_DATAPATH_SERDES); 364 } else { 365 sc->sc_flags |= GEM_SERIAL; 366 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 367 GEM_MII_DATAPATH_SERIAL); 368 } 369 370 aprint_normal("%s: using external PCS %s: ", 371 sc->sc_dev.dv_xname, 372 sc->sc_flags & GEM_SERDES ? "SERDES" : "Serialink"); 373 374 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO, 0, NULL); 375 /* Check for FDX and HDX capabilities */ 376 sc->sc_mii_anar = bus_space_read_4(t, h, GEM_MII_ANAR); 377 if (sc->sc_mii_anar & GEM_MII_ANEG_FUL_DUPLX) { 378 ifmedia_add(&sc->sc_mii.mii_media, 379 IFM_ETHER|IFM_1000_SX|IFM_MANUAL|IFM_FDX, 0, NULL); 380 aprint_normal("1000baseSX-FDX, "); 381 } 382 if (sc->sc_mii_anar & GEM_MII_ANEG_HLF_DUPLX) { 383 ifmedia_add(&sc->sc_mii.mii_media, 384 IFM_ETHER|IFM_1000_SX|IFM_MANUAL|IFM_HDX, 0, NULL); 385 aprint_normal("1000baseSX-HDX, "); 386 } 387 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 388 sc->sc_mii_media = IFM_AUTO; 389 aprint_normal("auto\n"); 390 391 gem_pcs_stop(sc, 1); 392 } 393 394 /* 395 * From this point forward, the attachment cannot fail. A failure 396 * before this point releases all resources that may have been 397 * allocated. 398 */ 399 400 /* Announce ourselves. */ 401 aprint_normal("%s: Ethernet address %s", sc->sc_dev.dv_xname, 402 ether_sprintf(enaddr)); 403 404 /* Get RX FIFO size */ 405 sc->sc_rxfifosize = 64 * 406 bus_space_read_4(t, h, GEM_RX_FIFO_SIZE); 407 aprint_normal(", %uKB RX fifo", sc->sc_rxfifosize / 1024); 408 409 /* Get TX FIFO size */ 410 v = bus_space_read_4(t, h, GEM_TX_FIFO_SIZE); 411 aprint_normal(", %uKB TX fifo\n", v / 16); 412 413 /* Initialize ifnet structure. */ 414 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 415 ifp->if_softc = sc; 416 ifp->if_flags = 417 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 418 sc->sc_if_flags = ifp->if_flags; 419 /* 420 * The GEM hardware supports basic TCP checksum offloading only. 421 * Several (all?) revisions (Sun rev. 01 and Apple rev. 00 and 80) 422 * have bugs in the receive checksum, so don't enable it for now. 423 if ((GEM_IS_SUN(sc) && sc->sc_chiprev != 1) || 424 (GEM_IS_APPLE(sc) && 425 (sc->sc_chiprev != 0 && sc->sc_chiprev != 0x80))) 426 ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Rx; 427 */ 428 ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Tx; 429 ifp->if_start = gem_start; 430 ifp->if_ioctl = gem_ioctl; 431 ifp->if_watchdog = gem_watchdog; 432 ifp->if_stop = gem_stop; 433 ifp->if_init = gem_init; 434 IFQ_SET_READY(&ifp->if_snd); 435 436 /* 437 * If we support GigE media, we support jumbo frames too. 438 * Unless we are Apple. 439 */ 440 TAILQ_FOREACH(ifm, &sc->sc_mii.mii_media.ifm_list, ifm_list) { 441 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_T || 442 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_SX || 443 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_LX || 444 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_CX) { 445 if (!GEM_IS_APPLE(sc)) 446 sc->sc_ethercom.ec_capabilities 447 |= ETHERCAP_JUMBO_MTU; 448 sc->sc_flags |= GEM_GIGABIT; 449 break; 450 } 451 } 452 453 /* claim 802.1q capability */ 454 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 455 456 /* Attach the interface. */ 457 if_attach(ifp); 458 ether_ifattach(ifp, enaddr); 459 460 sc->sc_sh = shutdownhook_establish(gem_shutdown, sc); 461 if (sc->sc_sh == NULL) 462 panic("gem_config: can't establish shutdownhook"); 463 464 #if NRND > 0 465 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 466 RND_TYPE_NET, 0); 467 #endif 468 469 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, 470 NULL, sc->sc_dev.dv_xname, "interrupts"); 471 #ifdef GEM_COUNTERS 472 evcnt_attach_dynamic(&sc->sc_ev_txint, EVCNT_TYPE_INTR, 473 &sc->sc_ev_intr, sc->sc_dev.dv_xname, "tx interrupts"); 474 evcnt_attach_dynamic(&sc->sc_ev_rxint, EVCNT_TYPE_INTR, 475 &sc->sc_ev_intr, sc->sc_dev.dv_xname, "rx interrupts"); 476 evcnt_attach_dynamic(&sc->sc_ev_rxfull, EVCNT_TYPE_INTR, 477 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx ring full"); 478 evcnt_attach_dynamic(&sc->sc_ev_rxnobuf, EVCNT_TYPE_INTR, 479 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx malloc failure"); 480 evcnt_attach_dynamic(&sc->sc_ev_rxhist[0], EVCNT_TYPE_INTR, 481 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 0desc"); 482 evcnt_attach_dynamic(&sc->sc_ev_rxhist[1], EVCNT_TYPE_INTR, 483 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 1desc"); 484 evcnt_attach_dynamic(&sc->sc_ev_rxhist[2], EVCNT_TYPE_INTR, 485 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 2desc"); 486 evcnt_attach_dynamic(&sc->sc_ev_rxhist[3], EVCNT_TYPE_INTR, 487 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 3desc"); 488 evcnt_attach_dynamic(&sc->sc_ev_rxhist[4], EVCNT_TYPE_INTR, 489 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >3desc"); 490 evcnt_attach_dynamic(&sc->sc_ev_rxhist[5], EVCNT_TYPE_INTR, 491 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >7desc"); 492 evcnt_attach_dynamic(&sc->sc_ev_rxhist[6], EVCNT_TYPE_INTR, 493 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >15desc"); 494 evcnt_attach_dynamic(&sc->sc_ev_rxhist[7], EVCNT_TYPE_INTR, 495 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >31desc"); 496 evcnt_attach_dynamic(&sc->sc_ev_rxhist[8], EVCNT_TYPE_INTR, 497 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >63desc"); 498 #endif 499 500 #if notyet 501 /* 502 * Add a suspend hook to make sure we come back up after a 503 * resume. 504 */ 505 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 506 gem_power, sc); 507 if (sc->sc_powerhook == NULL) 508 aprint_error("%s: WARNING: unable to establish power hook\n", 509 sc->sc_dev.dv_xname); 510 #endif 511 512 callout_init(&sc->sc_tick_ch, 0); 513 return; 514 515 /* 516 * Free any resources we've allocated during the failed attach 517 * attempt. Do this in reverse order and fall through. 518 */ 519 fail_7: 520 for (i = 0; i < GEM_NRXDESC; i++) { 521 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 522 bus_dmamap_destroy(sc->sc_dmatag, 523 sc->sc_rxsoft[i].rxs_dmamap); 524 } 525 fail_6: 526 for (i = 0; i < GEM_TXQUEUELEN; i++) { 527 if (sc->sc_txsoft[i].txs_dmamap != NULL) 528 bus_dmamap_destroy(sc->sc_dmatag, 529 sc->sc_txsoft[i].txs_dmamap); 530 } 531 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 532 fail_5: 533 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_nulldmamap); 534 fail_4: 535 bus_dmamem_unmap(sc->sc_dmatag, (void *)nullbuf, ETHER_MIN_TX); 536 fail_3: 537 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 538 fail_2: 539 bus_dmamem_unmap(sc->sc_dmatag, (void *)sc->sc_control_data, 540 sizeof(struct gem_control_data)); 541 fail_1: 542 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 543 fail_0: 544 return; 545 } 546 547 548 void 549 gem_tick(arg) 550 void *arg; 551 { 552 struct gem_softc *sc = arg; 553 int s; 554 555 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) { 556 /* 557 * We have to reset everything if we failed to get a 558 * PCS interrupt. Restarting the callout is handled 559 * in gem_pcs_start(). 560 */ 561 gem_init(&sc->sc_ethercom.ec_if); 562 } else { 563 s = splnet(); 564 mii_tick(&sc->sc_mii); 565 splx(s); 566 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 567 } 568 } 569 570 static int 571 gem_bitwait(sc, h, r, clr, set) 572 struct gem_softc *sc; 573 bus_space_handle_t h; 574 int r; 575 u_int32_t clr; 576 u_int32_t set; 577 { 578 int i; 579 u_int32_t reg; 580 581 for (i = TRIES; i--; DELAY(100)) { 582 reg = bus_space_read_4(sc->sc_bustag, h, r); 583 if ((reg & clr) == 0 && (reg & set) == set) 584 return (1); 585 } 586 return (0); 587 } 588 589 void 590 gem_reset(sc) 591 struct gem_softc *sc; 592 { 593 bus_space_tag_t t = sc->sc_bustag; 594 bus_space_handle_t h = sc->sc_h2; 595 int s; 596 597 s = splnet(); 598 DPRINTF(sc, ("%s: gem_reset\n", sc->sc_dev.dv_xname)); 599 gem_reset_rx(sc); 600 gem_reset_tx(sc); 601 602 /* Do a full reset */ 603 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX|GEM_RESET_TX); 604 if (!gem_bitwait(sc, h, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0)) 605 printf("%s: cannot reset device\n", sc->sc_dev.dv_xname); 606 splx(s); 607 } 608 609 610 /* 611 * gem_rxdrain: 612 * 613 * Drain the receive queue. 614 */ 615 static void 616 gem_rxdrain(struct gem_softc *sc) 617 { 618 struct gem_rxsoft *rxs; 619 int i; 620 621 for (i = 0; i < GEM_NRXDESC; i++) { 622 rxs = &sc->sc_rxsoft[i]; 623 if (rxs->rxs_mbuf != NULL) { 624 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 625 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 626 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 627 m_freem(rxs->rxs_mbuf); 628 rxs->rxs_mbuf = NULL; 629 } 630 } 631 } 632 633 /* 634 * Reset the whole thing. 635 */ 636 static void 637 gem_stop(struct ifnet *ifp, int disable) 638 { 639 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 640 struct gem_txsoft *txs; 641 642 DPRINTF(sc, ("%s: gem_stop\n", sc->sc_dev.dv_xname)); 643 644 callout_stop(&sc->sc_tick_ch); 645 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 646 gem_pcs_stop(sc, disable); 647 else 648 mii_down(&sc->sc_mii); 649 650 /* XXX - Should we reset these instead? */ 651 gem_disable_tx(sc); 652 gem_disable_rx(sc); 653 654 /* 655 * Release any queued transmit buffers. 656 */ 657 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 658 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 659 if (txs->txs_mbuf != NULL) { 660 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 0, 661 txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 662 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 663 m_freem(txs->txs_mbuf); 664 txs->txs_mbuf = NULL; 665 } 666 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 667 } 668 669 if (disable) { 670 gem_rxdrain(sc); 671 } 672 673 /* 674 * Mark the interface down and cancel the watchdog timer. 675 */ 676 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 677 sc->sc_if_flags = ifp->if_flags; 678 ifp->if_timer = 0; 679 } 680 681 682 /* 683 * Reset the receiver 684 */ 685 int 686 gem_reset_rx(struct gem_softc *sc) 687 { 688 bus_space_tag_t t = sc->sc_bustag; 689 bus_space_handle_t h = sc->sc_h1, h2 = sc->sc_h2; 690 691 /* 692 * Resetting while DMA is in progress can cause a bus hang, so we 693 * disable DMA first. 694 */ 695 gem_disable_rx(sc); 696 bus_space_write_4(t, h, GEM_RX_CONFIG, 0); 697 bus_space_barrier(t, h, GEM_RX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 698 /* Wait till it finishes */ 699 if (!gem_bitwait(sc, h, GEM_RX_CONFIG, 1, 0)) 700 printf("%s: cannot disable read dma\n", sc->sc_dev.dv_xname); 701 702 /* Finally, reset the ERX */ 703 bus_space_write_4(t, h2, GEM_RESET, GEM_RESET_RX); 704 bus_space_barrier(t, h, GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE); 705 /* Wait till it finishes */ 706 if (!gem_bitwait(sc, h2, GEM_RESET, GEM_RESET_RX, 0)) { 707 printf("%s: cannot reset receiver\n", sc->sc_dev.dv_xname); 708 return (1); 709 } 710 return (0); 711 } 712 713 714 /* 715 * Reset the receiver DMA engine. 716 * 717 * Intended to be used in case of GEM_INTR_RX_TAG_ERR, GEM_MAC_RX_OVERFLOW 718 * etc in order to reset the receiver DMA engine only and not do a full 719 * reset which amongst others also downs the link and clears the FIFOs. 720 */ 721 static void 722 gem_reset_rxdma(struct gem_softc *sc) 723 { 724 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 725 bus_space_tag_t t = sc->sc_bustag; 726 bus_space_handle_t h = sc->sc_h1; 727 int i; 728 729 if (gem_reset_rx(sc) != 0) { 730 gem_init(ifp); 731 return; 732 } 733 for (i = 0; i < GEM_NRXDESC; i++) 734 if (sc->sc_rxsoft[i].rxs_mbuf != NULL) 735 GEM_UPDATE_RXDESC(sc, i); 736 sc->sc_rxptr = 0; 737 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE); 738 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD); 739 740 /* Reprogram Descriptor Ring Base Addresses */ 741 /* NOTE: we use only 32-bit DMA addresses here. */ 742 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0); 743 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 744 745 /* Redo ERX Configuration */ 746 gem_rx_common(sc); 747 748 /* Give the reciever a swift kick */ 749 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC - 4); 750 } 751 752 /* 753 * Common RX configuration for gem_init() and gem_reset_rxdma(). 754 */ 755 static void 756 gem_rx_common(struct gem_softc *sc) 757 { 758 bus_space_tag_t t = sc->sc_bustag; 759 bus_space_handle_t h = sc->sc_h1; 760 u_int32_t v; 761 762 /* Encode Receive Descriptor ring size: four possible values */ 763 v = gem_ringsize(GEM_NRXDESC /*XXX*/); 764 765 /* Set receive h/w checksum offset */ 766 #ifdef INET 767 v |= (ETHER_HDR_LEN + sizeof(struct ip) + 768 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 769 ETHER_VLAN_ENCAP_LEN : 0)) << GEM_RX_CONFIG_CXM_START_SHFT; 770 #endif 771 772 /* Enable RX DMA */ 773 bus_space_write_4(t, h, GEM_RX_CONFIG, 774 v | (GEM_THRSH_1024 << GEM_RX_CONFIG_FIFO_THRS_SHIFT) | 775 (2 << GEM_RX_CONFIG_FBOFF_SHFT) | GEM_RX_CONFIG_RXDMA_EN); 776 777 /* 778 * The following value is for an OFF Threshold of about 3/4 full 779 * and an ON Threshold of 1/4 full. 780 */ 781 bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH, 782 (3 * sc->sc_rxfifosize / 256) | 783 ((sc->sc_rxfifosize / 256) << 12)); 784 bus_space_write_4(t, h, GEM_RX_BLANKING, 785 (6 << GEM_RX_BLANKING_TIME_SHIFT) | 6); 786 } 787 788 /* 789 * Reset the transmitter 790 */ 791 int 792 gem_reset_tx(struct gem_softc *sc) 793 { 794 bus_space_tag_t t = sc->sc_bustag; 795 bus_space_handle_t h = sc->sc_h1, h2 = sc->sc_h2; 796 797 /* 798 * Resetting while DMA is in progress can cause a bus hang, so we 799 * disable DMA first. 800 */ 801 gem_disable_tx(sc); 802 bus_space_write_4(t, h, GEM_TX_CONFIG, 0); 803 bus_space_barrier(t, h, GEM_TX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 804 /* Wait till it finishes */ 805 if (!gem_bitwait(sc, h, GEM_TX_CONFIG, 1, 0)) 806 printf("%s: cannot disable read dma\n", sc->sc_dev.dv_xname); 807 /* Wait 5ms extra. */ 808 delay(5000); 809 810 /* Finally, reset the ETX */ 811 bus_space_write_4(t, h2, GEM_RESET, GEM_RESET_TX); 812 bus_space_barrier(t, h, GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE); 813 /* Wait till it finishes */ 814 if (!gem_bitwait(sc, h2, GEM_RESET, GEM_RESET_TX, 0)) { 815 printf("%s: cannot reset receiver\n", 816 sc->sc_dev.dv_xname); 817 return (1); 818 } 819 return (0); 820 } 821 822 /* 823 * disable receiver. 824 */ 825 int 826 gem_disable_rx(struct gem_softc *sc) 827 { 828 bus_space_tag_t t = sc->sc_bustag; 829 bus_space_handle_t h = sc->sc_h1; 830 u_int32_t cfg; 831 832 /* Flip the enable bit */ 833 cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 834 cfg &= ~GEM_MAC_RX_ENABLE; 835 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg); 836 bus_space_barrier(t, h, GEM_MAC_RX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 837 /* Wait for it to finish */ 838 return (gem_bitwait(sc, h, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)); 839 } 840 841 /* 842 * disable transmitter. 843 */ 844 int 845 gem_disable_tx(struct gem_softc *sc) 846 { 847 bus_space_tag_t t = sc->sc_bustag; 848 bus_space_handle_t h = sc->sc_h1; 849 u_int32_t cfg; 850 851 /* Flip the enable bit */ 852 cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG); 853 cfg &= ~GEM_MAC_TX_ENABLE; 854 bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg); 855 bus_space_barrier(t, h, GEM_MAC_TX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 856 /* Wait for it to finish */ 857 return (gem_bitwait(sc, h, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)); 858 } 859 860 /* 861 * Initialize interface. 862 */ 863 int 864 gem_meminit(struct gem_softc *sc) 865 { 866 struct gem_rxsoft *rxs; 867 int i, error; 868 869 /* 870 * Initialize the transmit descriptor ring. 871 */ 872 memset((void *)sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 873 for (i = 0; i < GEM_NTXDESC; i++) { 874 sc->sc_txdescs[i].gd_flags = 0; 875 sc->sc_txdescs[i].gd_addr = 0; 876 } 877 GEM_CDTXSYNC(sc, 0, GEM_NTXDESC, 878 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 879 sc->sc_txfree = GEM_NTXDESC-1; 880 sc->sc_txnext = 0; 881 sc->sc_txwin = 0; 882 883 /* 884 * Initialize the receive descriptor and receive job 885 * descriptor rings. 886 */ 887 for (i = 0; i < GEM_NRXDESC; i++) { 888 rxs = &sc->sc_rxsoft[i]; 889 if (rxs->rxs_mbuf == NULL) { 890 if ((error = gem_add_rxbuf(sc, i)) != 0) { 891 printf("%s: unable to allocate or map rx " 892 "buffer %d, error = %d\n", 893 sc->sc_dev.dv_xname, i, error); 894 /* 895 * XXX Should attempt to run with fewer receive 896 * XXX buffers instead of just failing. 897 */ 898 gem_rxdrain(sc); 899 return (1); 900 } 901 } else 902 GEM_INIT_RXDESC(sc, i); 903 } 904 sc->sc_rxptr = 0; 905 sc->sc_meminited = 1; 906 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE); 907 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD); 908 909 return (0); 910 } 911 912 static int 913 gem_ringsize(int sz) 914 { 915 switch (sz) { 916 case 32: 917 return GEM_RING_SZ_32; 918 case 64: 919 return GEM_RING_SZ_64; 920 case 128: 921 return GEM_RING_SZ_128; 922 case 256: 923 return GEM_RING_SZ_256; 924 case 512: 925 return GEM_RING_SZ_512; 926 case 1024: 927 return GEM_RING_SZ_1024; 928 case 2048: 929 return GEM_RING_SZ_2048; 930 case 4096: 931 return GEM_RING_SZ_4096; 932 case 8192: 933 return GEM_RING_SZ_8192; 934 default: 935 printf("gem: invalid Receive Descriptor ring size %d\n", sz); 936 return GEM_RING_SZ_32; 937 } 938 } 939 940 941 /* 942 * Start PCS 943 */ 944 void 945 gem_pcs_start(struct gem_softc *sc) 946 { 947 bus_space_tag_t t = sc->sc_bustag; 948 bus_space_handle_t h = sc->sc_h1; 949 uint32_t v; 950 951 #ifdef GEM_DEBUG 952 aprint_debug("%s: gem_pcs_start()\n", sc->sc_dev.dv_xname); 953 #endif 954 955 /* 956 * Set up. We must disable the MII before modifying the 957 * GEM_MII_ANAR register 958 */ 959 if (sc->sc_flags & GEM_SERDES) { 960 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 961 GEM_MII_DATAPATH_SERDES); 962 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 963 GEM_MII_SLINK_LOOPBACK); 964 } else { 965 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 966 GEM_MII_DATAPATH_SERIAL); 967 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 0); 968 } 969 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 970 v = bus_space_read_4(t, h, GEM_MII_ANAR); 971 v |= (GEM_MII_ANEG_SYM_PAUSE | GEM_MII_ANEG_ASYM_PAUSE); 972 if (sc->sc_mii_media == IFM_AUTO) 973 v |= (GEM_MII_ANEG_FUL_DUPLX | GEM_MII_ANEG_HLF_DUPLX); 974 else if (sc->sc_mii_media == IFM_FDX) { 975 v |= GEM_MII_ANEG_FUL_DUPLX; 976 v &= ~GEM_MII_ANEG_HLF_DUPLX; 977 } else if (sc->sc_mii_media == IFM_HDX) { 978 v &= ~GEM_MII_ANEG_FUL_DUPLX; 979 v |= GEM_MII_ANEG_HLF_DUPLX; 980 } 981 982 /* Configure link. */ 983 bus_space_write_4(t, h, GEM_MII_ANAR, v); 984 bus_space_write_4(t, h, GEM_MII_CONTROL, 985 GEM_MII_CONTROL_AUTONEG | GEM_MII_CONTROL_RAN); 986 bus_space_write_4(t, h, GEM_MII_CONFIG, GEM_MII_CONFIG_ENABLE); 987 gem_bitwait(sc, h, GEM_MII_STATUS, 0, GEM_MII_STATUS_ANEG_CPT); 988 989 /* Start the 10 second timer */ 990 callout_reset(&sc->sc_tick_ch, hz * 10, gem_tick, sc); 991 } 992 993 /* 994 * Stop PCS 995 */ 996 void 997 gem_pcs_stop(struct gem_softc *sc, int disable) 998 { 999 bus_space_tag_t t = sc->sc_bustag; 1000 bus_space_handle_t h = sc->sc_h1; 1001 1002 #ifdef GEM_DEBUG 1003 aprint_debug("%s: gem_pcs_stop()\n", sc->sc_dev.dv_xname); 1004 #endif 1005 1006 /* Tell link partner that we're going away */ 1007 bus_space_write_4(t, h, GEM_MII_ANAR, GEM_MII_ANEG_RF); 1008 1009 /* 1010 * Disable PCS MII. The documentation suggests that setting 1011 * GEM_MII_CONFIG_ENABLE to zero and then restarting auto- 1012 * negotiation will shut down the link. However, it appears 1013 * that we also need to unset the datapath mode. 1014 */ 1015 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 1016 bus_space_write_4(t, h, GEM_MII_CONTROL, 1017 GEM_MII_CONTROL_AUTONEG | GEM_MII_CONTROL_RAN); 1018 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, GEM_MII_DATAPATH_MII); 1019 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 1020 1021 if (disable) { 1022 if (sc->sc_flags & GEM_SERDES) 1023 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 1024 GEM_MII_SLINK_POWER_OFF); 1025 else 1026 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 1027 GEM_MII_SLINK_LOOPBACK | GEM_MII_SLINK_POWER_OFF); 1028 } 1029 1030 sc->sc_flags &= ~GEM_LINK; 1031 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_NONE; 1032 sc->sc_mii.mii_media_status = IFM_AVALID; 1033 } 1034 1035 1036 /* 1037 * Initialization of interface; set up initialization block 1038 * and transmit/receive descriptor rings. 1039 */ 1040 int 1041 gem_init(struct ifnet *ifp) 1042 { 1043 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 1044 bus_space_tag_t t = sc->sc_bustag; 1045 bus_space_handle_t h = sc->sc_h1; 1046 int rc = 0, s; 1047 u_int max_frame_size; 1048 u_int32_t v; 1049 1050 s = splnet(); 1051 1052 DPRINTF(sc, ("%s: gem_init: calling stop\n", sc->sc_dev.dv_xname)); 1053 /* 1054 * Initialization sequence. The numbered steps below correspond 1055 * to the sequence outlined in section 6.3.5.1 in the Ethernet 1056 * Channel Engine manual (part of the PCIO manual). 1057 * See also the STP2002-STQ document from Sun Microsystems. 1058 */ 1059 1060 /* step 1 & 2. Reset the Ethernet Channel */ 1061 gem_stop(ifp, 0); 1062 gem_reset(sc); 1063 DPRINTF(sc, ("%s: gem_init: restarting\n", sc->sc_dev.dv_xname)); 1064 1065 /* Re-initialize the MIF */ 1066 gem_mifinit(sc); 1067 1068 /* Set up correct datapath for non-SERDES/Serialink */ 1069 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0 && 1070 sc->sc_variant != GEM_SUN_ERI) 1071 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 1072 GEM_MII_DATAPATH_MII); 1073 1074 /* Call MI reset function if any */ 1075 if (sc->sc_hwreset) 1076 (*sc->sc_hwreset)(sc); 1077 1078 /* step 3. Setup data structures in host memory */ 1079 if (gem_meminit(sc) != 0) 1080 return 1; 1081 1082 /* step 4. TX MAC registers & counters */ 1083 gem_init_regs(sc); 1084 max_frame_size = max(sc->sc_ethercom.ec_if.if_mtu, ETHERMTU); 1085 max_frame_size += ETHER_HDR_LEN + ETHER_CRC_LEN; 1086 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1087 max_frame_size += ETHER_VLAN_ENCAP_LEN; 1088 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 1089 max_frame_size|/* burst size */(0x2000<<16)); 1090 1091 /* step 5. RX MAC registers & counters */ 1092 gem_setladrf(sc); 1093 1094 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 1095 /* NOTE: we use only 32-bit DMA addresses here. */ 1096 bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 0); 1097 bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 1098 1099 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0); 1100 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 1101 1102 /* step 8. Global Configuration & Interrupt Mask */ 1103 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 1104 v = GEM_INTR_PCS; 1105 else 1106 v = GEM_INTR_MIF; 1107 bus_space_write_4(t, h, GEM_INTMASK, 1108 ~(GEM_INTR_TX_INTME | 1109 GEM_INTR_TX_EMPTY | 1110 GEM_INTR_TX_MAC | 1111 GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF| 1112 GEM_INTR_RX_TAG_ERR | GEM_INTR_MAC_CONTROL| 1113 GEM_INTR_BERR | v)); 1114 bus_space_write_4(t, h, GEM_MAC_RX_MASK, 1115 GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT); 1116 bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXX */ 1117 bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 1118 GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME); 1119 1120 /* step 9. ETX Configuration: use mostly default values */ 1121 1122 /* Enable TX DMA */ 1123 v = gem_ringsize(GEM_NTXDESC /*XXX*/); 1124 bus_space_write_4(t, h, GEM_TX_CONFIG, 1125 v|GEM_TX_CONFIG_TXDMA_EN| 1126 ((0x4FF<<10)&GEM_TX_CONFIG_TXFIFO_TH)); 1127 bus_space_write_4(t, h, GEM_TX_KICK, sc->sc_txnext); 1128 1129 /* step 10. ERX Configuration */ 1130 gem_rx_common(sc); 1131 1132 /* step 11. Configure Media */ 1133 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0 && 1134 (rc = mii_ifmedia_change(&sc->sc_mii)) != 0) 1135 goto out; 1136 1137 /* step 12. RX_MAC Configuration Register */ 1138 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 1139 v |= GEM_MAC_RX_ENABLE | GEM_MAC_RX_STRIP_CRC; 1140 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 1141 1142 /* step 14. Issue Transmit Pending command */ 1143 1144 /* Call MI initialization function if any */ 1145 if (sc->sc_hwinit) 1146 (*sc->sc_hwinit)(sc); 1147 1148 1149 /* step 15. Give the reciever a swift kick */ 1150 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4); 1151 1152 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 1153 /* Configure PCS */ 1154 gem_pcs_start(sc); 1155 else 1156 /* Start the one second timer. */ 1157 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 1158 1159 sc->sc_flags &= ~GEM_LINK; 1160 ifp->if_flags |= IFF_RUNNING; 1161 ifp->if_flags &= ~IFF_OACTIVE; 1162 ifp->if_timer = 0; 1163 sc->sc_if_flags = ifp->if_flags; 1164 out: 1165 splx(s); 1166 1167 return (0); 1168 } 1169 1170 void 1171 gem_init_regs(struct gem_softc *sc) 1172 { 1173 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1174 bus_space_tag_t t = sc->sc_bustag; 1175 bus_space_handle_t h = sc->sc_h1; 1176 const u_char *laddr = CLLADDR(ifp->if_sadl); 1177 u_int32_t v; 1178 1179 /* These regs are not cleared on reset */ 1180 if (!sc->sc_inited) { 1181 1182 /* Load recommended values */ 1183 bus_space_write_4(t, h, GEM_MAC_IPG0, 0x00); 1184 bus_space_write_4(t, h, GEM_MAC_IPG1, 0x08); 1185 bus_space_write_4(t, h, GEM_MAC_IPG2, 0x04); 1186 1187 bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 1188 /* Max frame and max burst size */ 1189 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 1190 ETHER_MAX_LEN | (0x2000<<16)); 1191 1192 bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x07); 1193 bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x04); 1194 bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10); 1195 bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088); 1196 bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED, 1197 ((laddr[5]<<8)|laddr[4])&0x3ff); 1198 1199 /* Secondary MAC addr set to 0:0:0:0:0:0 */ 1200 bus_space_write_4(t, h, GEM_MAC_ADDR3, 0); 1201 bus_space_write_4(t, h, GEM_MAC_ADDR4, 0); 1202 bus_space_write_4(t, h, GEM_MAC_ADDR5, 0); 1203 1204 /* MAC control addr set to 01:80:c2:00:00:01 */ 1205 bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001); 1206 bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200); 1207 bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180); 1208 1209 /* MAC filter addr set to 0:0:0:0:0:0 */ 1210 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0); 1211 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0); 1212 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0); 1213 1214 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0); 1215 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0); 1216 1217 sc->sc_inited = 1; 1218 } 1219 1220 /* Counters need to be zeroed */ 1221 bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0); 1222 bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0); 1223 bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0); 1224 bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0); 1225 bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0); 1226 bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0); 1227 bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0); 1228 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 1229 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 1230 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 1231 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 1232 1233 /* Set XOFF PAUSE time. */ 1234 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); 1235 1236 /* 1237 * Set the internal arbitration to "infinite" bursts of the 1238 * maximum length of 31 * 64 bytes so DMA transfers aren't 1239 * split up in cache line size chunks. This greatly improves 1240 * especially RX performance. 1241 * Enable silicon bug workarounds for the Apple variants. 1242 */ 1243 bus_space_write_4(t, h, GEM_CONFIG, 1244 GEM_CONFIG_TXDMA_LIMIT | GEM_CONFIG_RXDMA_LIMIT | 1245 GEM_CONFIG_BURST_INF | (GEM_IS_APPLE(sc) ? 1246 GEM_CONFIG_RONPAULBIT | GEM_CONFIG_BUG2FIX : 0)); 1247 1248 /* 1249 * Set the station address. 1250 */ 1251 bus_space_write_4(t, h, GEM_MAC_ADDR0, (laddr[4]<<8)|laddr[5]); 1252 bus_space_write_4(t, h, GEM_MAC_ADDR1, (laddr[2]<<8)|laddr[3]); 1253 bus_space_write_4(t, h, GEM_MAC_ADDR2, (laddr[0]<<8)|laddr[1]); 1254 1255 /* 1256 * Enable MII outputs. Enable GMII if there is a gigabit PHY. 1257 */ 1258 sc->sc_mif_config = bus_space_read_4(t, h, GEM_MIF_CONFIG); 1259 v = GEM_MAC_XIF_TX_MII_ENA; 1260 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) { 1261 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) { 1262 v |= GEM_MAC_XIF_FDPLX_LED; 1263 if (sc->sc_flags & GEM_GIGABIT) 1264 v |= GEM_MAC_XIF_GMII_MODE; 1265 } 1266 } else { 1267 v |= GEM_MAC_XIF_GMII_MODE; 1268 } 1269 bus_space_write_4(t, h, GEM_MAC_XIF_CONFIG, v); 1270 } 1271 1272 #ifdef GEM_DEBUG 1273 static void 1274 gem_txsoft_print(const struct gem_softc *sc, int firstdesc, int lastdesc) 1275 { 1276 int i; 1277 1278 for (i = firstdesc;; i = GEM_NEXTTX(i)) { 1279 printf("descriptor %d:\t", i); 1280 printf("gd_flags: 0x%016" PRIx64 "\t", 1281 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags)); 1282 printf("gd_addr: 0x%016" PRIx64 "\n", 1283 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr)); 1284 if (i == lastdesc) 1285 break; 1286 } 1287 } 1288 #endif 1289 1290 static void 1291 gem_start(ifp) 1292 struct ifnet *ifp; 1293 { 1294 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 1295 struct mbuf *m0, *m; 1296 struct gem_txsoft *txs; 1297 bus_dmamap_t dmamap; 1298 int error, firsttx, nexttx = -1, lasttx = -1, ofree, seg; 1299 uint64_t flags = 0; 1300 1301 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1302 return; 1303 1304 /* 1305 * Remember the previous number of free descriptors and 1306 * the first descriptor we'll use. 1307 */ 1308 ofree = sc->sc_txfree; 1309 firsttx = sc->sc_txnext; 1310 1311 DPRINTF(sc, ("%s: gem_start: txfree %d, txnext %d\n", 1312 sc->sc_dev.dv_xname, ofree, firsttx)); 1313 1314 /* 1315 * Loop through the send queue, setting up transmit descriptors 1316 * until we drain the queue, or use up all available transmit 1317 * descriptors. 1318 */ 1319 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 1320 sc->sc_txfree != 0) { 1321 /* 1322 * Grab a packet off the queue. 1323 */ 1324 IFQ_POLL(&ifp->if_snd, m0); 1325 if (m0 == NULL) 1326 break; 1327 m = NULL; 1328 1329 dmamap = txs->txs_dmamap; 1330 1331 /* 1332 * Load the DMA map. If this fails, the packet either 1333 * didn't fit in the alloted number of segments, or we were 1334 * short on resources. In this case, we'll copy and try 1335 * again. 1336 */ 1337 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m0, 1338 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0 || 1339 (m0->m_pkthdr.len < ETHER_MIN_TX && 1340 dmamap->dm_nsegs == GEM_NTXSEGS)) { 1341 if (m0->m_pkthdr.len > MCLBYTES) { 1342 printf("%s: unable to allocate jumbo Tx " 1343 "cluster\n", sc->sc_dev.dv_xname); 1344 IFQ_DEQUEUE(&ifp->if_snd, m0); 1345 m_freem(m0); 1346 continue; 1347 } 1348 MGETHDR(m, M_DONTWAIT, MT_DATA); 1349 if (m == NULL) { 1350 printf("%s: unable to allocate Tx mbuf\n", 1351 sc->sc_dev.dv_xname); 1352 break; 1353 } 1354 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1355 if (m0->m_pkthdr.len > MHLEN) { 1356 MCLGET(m, M_DONTWAIT); 1357 if ((m->m_flags & M_EXT) == 0) { 1358 printf("%s: unable to allocate Tx " 1359 "cluster\n", sc->sc_dev.dv_xname); 1360 m_freem(m); 1361 break; 1362 } 1363 } 1364 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1365 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1366 error = bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, 1367 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1368 if (error) { 1369 printf("%s: unable to load Tx buffer, " 1370 "error = %d\n", sc->sc_dev.dv_xname, error); 1371 break; 1372 } 1373 } 1374 1375 /* 1376 * Ensure we have enough descriptors free to describe 1377 * the packet. 1378 */ 1379 if (dmamap->dm_nsegs > ((m0->m_pkthdr.len < ETHER_MIN_TX) ? 1380 (sc->sc_txfree - 1) : sc->sc_txfree)) { 1381 /* 1382 * Not enough free descriptors to transmit this 1383 * packet. We haven't committed to anything yet, 1384 * so just unload the DMA map, put the packet 1385 * back on the queue, and punt. Notify the upper 1386 * layer that there are no more slots left. 1387 * 1388 * XXX We could allocate an mbuf and copy, but 1389 * XXX it is worth it? 1390 */ 1391 ifp->if_flags |= IFF_OACTIVE; 1392 sc->sc_if_flags = ifp->if_flags; 1393 bus_dmamap_unload(sc->sc_dmatag, dmamap); 1394 if (m != NULL) 1395 m_freem(m); 1396 break; 1397 } 1398 1399 IFQ_DEQUEUE(&ifp->if_snd, m0); 1400 if (m != NULL) { 1401 m_freem(m0); 1402 m0 = m; 1403 } 1404 1405 /* 1406 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1407 */ 1408 1409 /* Sync the DMA map. */ 1410 bus_dmamap_sync(sc->sc_dmatag, dmamap, 0, dmamap->dm_mapsize, 1411 BUS_DMASYNC_PREWRITE); 1412 1413 /* 1414 * Initialize the transmit descriptors. 1415 */ 1416 for (nexttx = sc->sc_txnext, seg = 0; 1417 seg < dmamap->dm_nsegs; 1418 seg++, nexttx = GEM_NEXTTX(nexttx)) { 1419 1420 /* 1421 * If this is the first descriptor we're 1422 * enqueueing, set the start of packet flag, 1423 * and the checksum stuff if we want the hardware 1424 * to do it. 1425 */ 1426 sc->sc_txdescs[nexttx].gd_addr = 1427 GEM_DMA_WRITE(sc, dmamap->dm_segs[seg].ds_addr); 1428 flags = dmamap->dm_segs[seg].ds_len & GEM_TD_BUFSIZE; 1429 if (nexttx == firsttx) { 1430 flags |= GEM_TD_START_OF_PACKET; 1431 if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) { 1432 sc->sc_txwin = 0; 1433 flags |= GEM_TD_INTERRUPT_ME; 1434 } 1435 1436 #ifdef INET 1437 /* h/w checksum */ 1438 if (ifp->if_csum_flags_tx & M_CSUM_TCPv4 && 1439 m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1440 struct ether_header *eh; 1441 uint16_t offset, start; 1442 1443 eh = mtod(m0, struct ether_header *); 1444 switch (ntohs(eh->ether_type)) { 1445 case ETHERTYPE_IP: 1446 start = ETHER_HDR_LEN; 1447 break; 1448 case ETHERTYPE_VLAN: 1449 start = ETHER_HDR_LEN + 1450 ETHER_VLAN_ENCAP_LEN; 1451 break; 1452 default: 1453 /* unsupported, drop it */ 1454 m_free(m0); 1455 continue; 1456 } 1457 start += M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 1458 offset = M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data) + start; 1459 flags |= (start << 1460 GEM_TD_CXSUM_STARTSHFT) | 1461 (offset << 1462 GEM_TD_CXSUM_STUFFSHFT) | 1463 GEM_TD_CXSUM_ENABLE; 1464 } 1465 #endif 1466 } 1467 if (seg == dmamap->dm_nsegs - 1) { 1468 flags |= GEM_TD_END_OF_PACKET; 1469 } else { 1470 /* last flag set outside of loop */ 1471 sc->sc_txdescs[nexttx].gd_flags = 1472 GEM_DMA_WRITE(sc, flags); 1473 } 1474 lasttx = nexttx; 1475 } 1476 if (m0->m_pkthdr.len < ETHER_MIN_TX) { 1477 /* add padding buffer at end of chain */ 1478 flags &= ~GEM_TD_END_OF_PACKET; 1479 sc->sc_txdescs[lasttx].gd_flags = 1480 GEM_DMA_WRITE(sc, flags); 1481 1482 sc->sc_txdescs[nexttx].gd_addr = 1483 GEM_DMA_WRITE(sc, 1484 sc->sc_nulldmamap->dm_segs[0].ds_addr); 1485 flags = ((ETHER_MIN_TX - m0->m_pkthdr.len) & 1486 GEM_TD_BUFSIZE) | GEM_TD_END_OF_PACKET; 1487 lasttx = nexttx; 1488 nexttx = GEM_NEXTTX(nexttx); 1489 seg++; 1490 } 1491 sc->sc_txdescs[lasttx].gd_flags = GEM_DMA_WRITE(sc, flags); 1492 1493 KASSERT(lasttx != -1); 1494 1495 /* 1496 * Store a pointer to the packet so we can free it later, 1497 * and remember what txdirty will be once the packet is 1498 * done. 1499 */ 1500 txs->txs_mbuf = m0; 1501 txs->txs_firstdesc = sc->sc_txnext; 1502 txs->txs_lastdesc = lasttx; 1503 txs->txs_ndescs = seg; 1504 1505 #ifdef GEM_DEBUG 1506 if (ifp->if_flags & IFF_DEBUG) { 1507 printf(" gem_start %p transmit chain:\n", txs); 1508 gem_txsoft_print(sc, txs->txs_firstdesc, 1509 txs->txs_lastdesc); 1510 } 1511 #endif 1512 1513 /* Sync the descriptors we're using. */ 1514 GEM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndescs, 1515 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1516 1517 /* Advance the tx pointer. */ 1518 sc->sc_txfree -= txs->txs_ndescs; 1519 sc->sc_txnext = nexttx; 1520 1521 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1522 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1523 1524 #if NBPFILTER > 0 1525 /* 1526 * Pass the packet to any BPF listeners. 1527 */ 1528 if (ifp->if_bpf) 1529 bpf_mtap(ifp->if_bpf, m0); 1530 #endif /* NBPFILTER > 0 */ 1531 } 1532 1533 if (txs == NULL || sc->sc_txfree == 0) { 1534 /* No more slots left; notify upper layer. */ 1535 ifp->if_flags |= IFF_OACTIVE; 1536 sc->sc_if_flags = ifp->if_flags; 1537 } 1538 1539 if (sc->sc_txfree != ofree) { 1540 DPRINTF(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 1541 sc->sc_dev.dv_xname, lasttx, firsttx)); 1542 /* 1543 * The entire packet chain is set up. 1544 * Kick the transmitter. 1545 */ 1546 DPRINTF(sc, ("%s: gem_start: kicking tx %d\n", 1547 sc->sc_dev.dv_xname, nexttx)); 1548 bus_space_write_4(sc->sc_bustag, sc->sc_h1, GEM_TX_KICK, 1549 sc->sc_txnext); 1550 1551 /* Set a watchdog timer in case the chip flakes out. */ 1552 ifp->if_timer = 5; 1553 DPRINTF(sc, ("%s: gem_start: watchdog %d\n", 1554 sc->sc_dev.dv_xname, ifp->if_timer)); 1555 } 1556 } 1557 1558 /* 1559 * Transmit interrupt. 1560 */ 1561 int 1562 gem_tint(sc) 1563 struct gem_softc *sc; 1564 { 1565 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1566 bus_space_tag_t t = sc->sc_bustag; 1567 bus_space_handle_t mac = sc->sc_h1; 1568 struct gem_txsoft *txs; 1569 int txlast; 1570 int progress = 0; 1571 u_int32_t v; 1572 1573 DPRINTF(sc, ("%s: gem_tint\n", sc->sc_dev.dv_xname)); 1574 1575 /* Unload collision counters ... */ 1576 v = bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) + 1577 bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT); 1578 ifp->if_collisions += v + 1579 bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) + 1580 bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT); 1581 ifp->if_oerrors += v; 1582 1583 /* ... then clear the hardware counters. */ 1584 bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0); 1585 bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0); 1586 bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0); 1587 bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0); 1588 1589 /* 1590 * Go through our Tx list and free mbufs for those 1591 * frames that have been transmitted. 1592 */ 1593 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1594 /* 1595 * In theory, we could harvest some descriptors before 1596 * the ring is empty, but that's a bit complicated. 1597 * 1598 * GEM_TX_COMPLETION points to the last descriptor 1599 * processed +1. 1600 * 1601 * Let's assume that the NIC writes back to the Tx 1602 * descriptors before it updates the completion 1603 * register. If the NIC has posted writes to the 1604 * Tx descriptors, PCI ordering requires that the 1605 * posted writes flush to RAM before the register-read 1606 * finishes. So let's read the completion register, 1607 * before syncing the descriptors, so that we 1608 * examine Tx descriptors that are at least as 1609 * current as the completion register. 1610 */ 1611 txlast = bus_space_read_4(t, mac, GEM_TX_COMPLETION); 1612 DPRINTF(sc, 1613 ("gem_tint: txs->txs_lastdesc = %d, txlast = %d\n", 1614 txs->txs_lastdesc, txlast)); 1615 if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1616 if (txlast >= txs->txs_firstdesc && 1617 txlast <= txs->txs_lastdesc) 1618 break; 1619 } else if (txlast >= txs->txs_firstdesc || 1620 txlast <= txs->txs_lastdesc) 1621 break; 1622 1623 GEM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndescs, 1624 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1625 1626 #ifdef GEM_DEBUG /* XXX DMA synchronization? */ 1627 if (ifp->if_flags & IFF_DEBUG) { 1628 printf(" txsoft %p transmit chain:\n", txs); 1629 gem_txsoft_print(sc, txs->txs_firstdesc, 1630 txs->txs_lastdesc); 1631 } 1632 #endif 1633 1634 1635 DPRINTF(sc, ("gem_tint: releasing a desc\n")); 1636 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1637 1638 sc->sc_txfree += txs->txs_ndescs; 1639 1640 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 1641 0, txs->txs_dmamap->dm_mapsize, 1642 BUS_DMASYNC_POSTWRITE); 1643 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 1644 if (txs->txs_mbuf != NULL) { 1645 m_freem(txs->txs_mbuf); 1646 txs->txs_mbuf = NULL; 1647 } 1648 1649 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1650 1651 ifp->if_opackets++; 1652 progress = 1; 1653 } 1654 1655 #if 0 1656 DPRINTF(sc, ("gem_tint: GEM_TX_STATE_MACHINE %x " 1657 "GEM_TX_DATA_PTR %" PRIx64 "GEM_TX_COMPLETION %" PRIx32 "\n", 1658 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_TX_STATE_MACHINE), 1659 ((uint64_t)bus_space_read_4(sc->sc_bustag, sc->sc_h1, 1660 GEM_TX_DATA_PTR_HI) << 32) | 1661 bus_space_read_4(sc->sc_bustag, sc->sc_h1, 1662 GEM_TX_DATA_PTR_LO), 1663 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_TX_COMPLETION))); 1664 #endif 1665 1666 if (progress) { 1667 if (sc->sc_txfree == GEM_NTXDESC - 1) 1668 sc->sc_txwin = 0; 1669 1670 /* Freed some descriptors, so reset IFF_OACTIVE and restart. */ 1671 ifp->if_flags &= ~IFF_OACTIVE; 1672 sc->sc_if_flags = ifp->if_flags; 1673 ifp->if_timer = SIMPLEQ_EMPTY(&sc->sc_txdirtyq) ? 0 : 5; 1674 gem_start(ifp); 1675 } 1676 DPRINTF(sc, ("%s: gem_tint: watchdog %d\n", 1677 sc->sc_dev.dv_xname, ifp->if_timer)); 1678 1679 return (1); 1680 } 1681 1682 /* 1683 * Receive interrupt. 1684 */ 1685 int 1686 gem_rint(sc) 1687 struct gem_softc *sc; 1688 { 1689 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1690 bus_space_tag_t t = sc->sc_bustag; 1691 bus_space_handle_t h = sc->sc_h1; 1692 struct gem_rxsoft *rxs; 1693 struct mbuf *m; 1694 u_int64_t rxstat; 1695 u_int32_t rxcomp; 1696 int i, len, progress = 0; 1697 1698 DPRINTF(sc, ("%s: gem_rint\n", sc->sc_dev.dv_xname)); 1699 1700 /* 1701 * Ignore spurious interrupt that sometimes occurs before 1702 * we are set up when we network boot. 1703 */ 1704 if (!sc->sc_meminited) 1705 return 1; 1706 1707 /* 1708 * Read the completion register once. This limits 1709 * how long the following loop can execute. 1710 */ 1711 rxcomp = bus_space_read_4(t, h, GEM_RX_COMPLETION); 1712 1713 /* 1714 * XXX Read the lastrx only once at the top for speed. 1715 */ 1716 DPRINTF(sc, ("gem_rint: sc->rxptr %d, complete %d\n", 1717 sc->sc_rxptr, rxcomp)); 1718 1719 /* 1720 * Go into the loop at least once. 1721 */ 1722 for (i = sc->sc_rxptr; i == sc->sc_rxptr || i != rxcomp; 1723 i = GEM_NEXTRX(i)) { 1724 rxs = &sc->sc_rxsoft[i]; 1725 1726 GEM_CDRXSYNC(sc, i, 1727 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1728 1729 rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags); 1730 1731 if (rxstat & GEM_RD_OWN) { 1732 GEM_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); 1733 /* 1734 * We have processed all of the receive buffers. 1735 */ 1736 break; 1737 } 1738 1739 progress++; 1740 ifp->if_ipackets++; 1741 1742 if (rxstat & GEM_RD_BAD_CRC) { 1743 ifp->if_ierrors++; 1744 printf("%s: receive error: CRC error\n", 1745 sc->sc_dev.dv_xname); 1746 GEM_INIT_RXDESC(sc, i); 1747 continue; 1748 } 1749 1750 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1751 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1752 #ifdef GEM_DEBUG 1753 if (ifp->if_flags & IFF_DEBUG) { 1754 printf(" rxsoft %p descriptor %d: ", rxs, i); 1755 printf("gd_flags: 0x%016llx\t", (long long) 1756 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags)); 1757 printf("gd_addr: 0x%016llx\n", (long long) 1758 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr)); 1759 } 1760 #endif 1761 1762 /* No errors; receive the packet. */ 1763 len = GEM_RD_BUFLEN(rxstat); 1764 1765 /* 1766 * Allocate a new mbuf cluster. If that fails, we are 1767 * out of memory, and must drop the packet and recycle 1768 * the buffer that's already attached to this descriptor. 1769 */ 1770 m = rxs->rxs_mbuf; 1771 if (gem_add_rxbuf(sc, i) != 0) { 1772 GEM_COUNTER_INCR(sc, sc_ev_rxnobuf); 1773 ifp->if_ierrors++; 1774 GEM_INIT_RXDESC(sc, i); 1775 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1776 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1777 continue; 1778 } 1779 m->m_data += 2; /* We're already off by two */ 1780 1781 m->m_pkthdr.rcvif = ifp; 1782 m->m_pkthdr.len = m->m_len = len; 1783 1784 #if NBPFILTER > 0 1785 /* 1786 * Pass this up to any BPF listeners, but only 1787 * pass it up the stack if it's for us. 1788 */ 1789 if (ifp->if_bpf) 1790 bpf_mtap(ifp->if_bpf, m); 1791 #endif /* NBPFILTER > 0 */ 1792 1793 #ifdef INET 1794 /* hardware checksum */ 1795 if (ifp->if_csum_flags_rx & M_CSUM_TCPv4) { 1796 struct ether_header *eh; 1797 struct ip *ip; 1798 int32_t hlen, pktlen; 1799 1800 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1801 pktlen = m->m_pkthdr.len - ETHER_HDR_LEN - 1802 ETHER_VLAN_ENCAP_LEN; 1803 eh = (struct ether_header *) (mtod(m, char *) + 1804 ETHER_VLAN_ENCAP_LEN); 1805 } else { 1806 pktlen = m->m_pkthdr.len - ETHER_HDR_LEN; 1807 eh = mtod(m, struct ether_header *); 1808 } 1809 if (ntohs(eh->ether_type) != ETHERTYPE_IP) 1810 goto swcsum; 1811 ip = (struct ip *) ((char *)eh + ETHER_HDR_LEN); 1812 1813 /* IPv4 only */ 1814 if (ip->ip_v != IPVERSION) 1815 goto swcsum; 1816 1817 hlen = ip->ip_hl << 2; 1818 if (hlen < sizeof(struct ip)) 1819 goto swcsum; 1820 1821 /* 1822 * bail if too short, has random trailing garbage, 1823 * truncated, fragment, or has ethernet pad. 1824 */ 1825 if ((ntohs(ip->ip_len) < hlen) || 1826 (ntohs(ip->ip_len) != pktlen) || 1827 (ntohs(ip->ip_off) & (IP_MF | IP_OFFMASK))) 1828 goto swcsum; 1829 1830 switch (ip->ip_p) { 1831 case IPPROTO_TCP: 1832 if (! (ifp->if_csum_flags_rx & M_CSUM_TCPv4)) 1833 goto swcsum; 1834 if (pktlen < (hlen + sizeof(struct tcphdr))) 1835 goto swcsum; 1836 m->m_pkthdr.csum_flags = M_CSUM_TCPv4; 1837 break; 1838 case IPPROTO_UDP: 1839 /* FALLTHROUGH */ 1840 default: 1841 goto swcsum; 1842 } 1843 1844 /* the uncomplemented sum is expected */ 1845 m->m_pkthdr.csum_data = (~rxstat) & GEM_RD_CHECKSUM; 1846 1847 /* if the pkt had ip options, we have to deduct them */ 1848 if (hlen > sizeof(struct ip)) { 1849 uint16_t *opts; 1850 uint32_t optsum, temp; 1851 1852 optsum = 0; 1853 temp = hlen - sizeof(struct ip); 1854 opts = (uint16_t *) ((char *) ip + 1855 sizeof(struct ip)); 1856 1857 while (temp > 1) { 1858 optsum += ntohs(*opts++); 1859 temp -= 2; 1860 } 1861 while (optsum >> 16) 1862 optsum = (optsum >> 16) + 1863 (optsum & 0xffff); 1864 1865 /* Deduct ip opts sum from hwsum (rfc 1624). */ 1866 m->m_pkthdr.csum_data = 1867 ~((~m->m_pkthdr.csum_data) - ~optsum); 1868 1869 while (m->m_pkthdr.csum_data >> 16) 1870 m->m_pkthdr.csum_data = 1871 (m->m_pkthdr.csum_data >> 16) + 1872 (m->m_pkthdr.csum_data & 1873 0xffff); 1874 } 1875 1876 m->m_pkthdr.csum_flags |= M_CSUM_DATA | 1877 M_CSUM_NO_PSEUDOHDR; 1878 } else 1879 swcsum: 1880 m->m_pkthdr.csum_flags = 0; 1881 #endif 1882 /* Pass it on. */ 1883 (*ifp->if_input)(ifp, m); 1884 } 1885 1886 if (progress) { 1887 /* Update the receive pointer. */ 1888 if (i == sc->sc_rxptr) { 1889 GEM_COUNTER_INCR(sc, sc_ev_rxfull); 1890 #ifdef GEM_DEBUG 1891 if (ifp->if_flags & IFF_DEBUG) 1892 printf("%s: rint: ring wrap\n", 1893 sc->sc_dev.dv_xname); 1894 #endif 1895 } 1896 sc->sc_rxptr = i; 1897 bus_space_write_4(t, h, GEM_RX_KICK, GEM_PREVRX(i)); 1898 } 1899 #ifdef GEM_COUNTERS 1900 if (progress <= 4) { 1901 GEM_COUNTER_INCR(sc, sc_ev_rxhist[progress]); 1902 } else if (progress < 32) { 1903 if (progress < 16) 1904 GEM_COUNTER_INCR(sc, sc_ev_rxhist[5]); 1905 else 1906 GEM_COUNTER_INCR(sc, sc_ev_rxhist[6]); 1907 1908 } else { 1909 if (progress < 64) 1910 GEM_COUNTER_INCR(sc, sc_ev_rxhist[7]); 1911 else 1912 GEM_COUNTER_INCR(sc, sc_ev_rxhist[8]); 1913 } 1914 #endif 1915 1916 DPRINTF(sc, ("gem_rint: done sc->rxptr %d, complete %d\n", 1917 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION))); 1918 1919 /* Read error counters ... */ 1920 ifp->if_ierrors += 1921 bus_space_read_4(t, h, GEM_MAC_RX_LEN_ERR_CNT) + 1922 bus_space_read_4(t, h, GEM_MAC_RX_ALIGN_ERR) + 1923 bus_space_read_4(t, h, GEM_MAC_RX_CRC_ERR_CNT) + 1924 bus_space_read_4(t, h, GEM_MAC_RX_CODE_VIOL); 1925 1926 /* ... then clear the hardware counters. */ 1927 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 1928 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 1929 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 1930 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 1931 1932 return (1); 1933 } 1934 1935 1936 /* 1937 * gem_add_rxbuf: 1938 * 1939 * Add a receive buffer to the indicated descriptor. 1940 */ 1941 int 1942 gem_add_rxbuf(struct gem_softc *sc, int idx) 1943 { 1944 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1945 struct mbuf *m; 1946 int error; 1947 1948 MGETHDR(m, M_DONTWAIT, MT_DATA); 1949 if (m == NULL) 1950 return (ENOBUFS); 1951 1952 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1953 MCLGET(m, M_DONTWAIT); 1954 if ((m->m_flags & M_EXT) == 0) { 1955 m_freem(m); 1956 return (ENOBUFS); 1957 } 1958 1959 #ifdef GEM_DEBUG 1960 /* bzero the packet to check DMA */ 1961 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 1962 #endif 1963 1964 if (rxs->rxs_mbuf != NULL) 1965 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 1966 1967 rxs->rxs_mbuf = m; 1968 1969 error = bus_dmamap_load(sc->sc_dmatag, rxs->rxs_dmamap, 1970 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1971 BUS_DMA_READ|BUS_DMA_NOWAIT); 1972 if (error) { 1973 printf("%s: can't load rx DMA map %d, error = %d\n", 1974 sc->sc_dev.dv_xname, idx, error); 1975 panic("gem_add_rxbuf"); /* XXX */ 1976 } 1977 1978 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1979 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1980 1981 GEM_INIT_RXDESC(sc, idx); 1982 1983 return (0); 1984 } 1985 1986 1987 int 1988 gem_eint(struct gem_softc *sc, u_int status) 1989 { 1990 char bits[128]; 1991 u_int32_t v; 1992 1993 if ((status & GEM_INTR_MIF) != 0) { 1994 printf("%s: XXXlink status changed\n", sc->sc_dev.dv_xname); 1995 return (1); 1996 } 1997 1998 if ((status & GEM_INTR_RX_TAG_ERR) != 0) { 1999 gem_reset_rxdma(sc); 2000 return (1); 2001 } 2002 2003 if (status & GEM_INTR_BERR) { 2004 bus_space_read_4(sc->sc_bustag, sc->sc_h2, GEM_ERROR_STATUS); 2005 v = bus_space_read_4(sc->sc_bustag, sc->sc_h2, 2006 GEM_ERROR_STATUS); 2007 printf("%s: bus error interrupt: 0x%02x\n", 2008 sc->sc_dev.dv_xname, v); 2009 return (1); 2010 } 2011 2012 printf("%s: status=%s\n", sc->sc_dev.dv_xname, 2013 bitmask_snprintf(status, GEM_INTR_BITS, bits, sizeof(bits))); 2014 return (1); 2015 } 2016 2017 2018 /* 2019 * PCS interrupts. 2020 * We should receive these when the link status changes, but sometimes 2021 * we don't receive them for link up. We compensate for this in the 2022 * gem_tick() callout. 2023 */ 2024 int 2025 gem_pint(struct gem_softc *sc) 2026 { 2027 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2028 bus_space_tag_t t = sc->sc_bustag; 2029 bus_space_handle_t h = sc->sc_h1; 2030 u_int32_t v, v2; 2031 2032 /* 2033 * Clear the PCS interrupt from GEM_STATUS. The PCS register is 2034 * latched, so we have to read it twice. There is only one bit in 2035 * use, so the value is meaningless. 2036 */ 2037 bus_space_read_4(t, h, GEM_MII_INTERRUP_STATUS); 2038 bus_space_read_4(t, h, GEM_MII_INTERRUP_STATUS); 2039 2040 if ((ifp->if_flags & IFF_UP) == 0) 2041 return 1; 2042 2043 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) 2044 return 1; 2045 2046 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2047 /* If we see remote fault, our link partner is probably going away */ 2048 if ((v & GEM_MII_STATUS_REM_FLT) != 0) { 2049 gem_bitwait(sc, h, GEM_MII_STATUS, GEM_MII_STATUS_REM_FLT, 0); 2050 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2051 /* Otherwise, we may need to wait after auto-negotiation completes */ 2052 } else if ((v & (GEM_MII_STATUS_LINK_STS | GEM_MII_STATUS_ANEG_CPT)) == 2053 GEM_MII_STATUS_ANEG_CPT) { 2054 gem_bitwait(sc, h, GEM_MII_STATUS, 0, GEM_MII_STATUS_LINK_STS); 2055 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2056 } 2057 if ((v & GEM_MII_STATUS_LINK_STS) != 0) { 2058 if (sc->sc_flags & GEM_LINK) { 2059 return 1; 2060 } 2061 callout_stop(&sc->sc_tick_ch); 2062 v = bus_space_read_4(t, h, GEM_MII_ANAR); 2063 v2 = bus_space_read_4(t, h, GEM_MII_ANLPAR); 2064 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_1000_SX; 2065 sc->sc_mii.mii_media_status = IFM_AVALID | IFM_ACTIVE; 2066 v &= v2; 2067 if (v & GEM_MII_ANEG_FUL_DUPLX) { 2068 sc->sc_mii.mii_media_active |= IFM_FDX; 2069 #ifdef GEM_DEBUG 2070 aprint_debug("%s: link up: full duplex\n", 2071 sc->sc_dev.dv_xname); 2072 #endif 2073 } else if (v & GEM_MII_ANEG_HLF_DUPLX) { 2074 sc->sc_mii.mii_media_active |= IFM_HDX; 2075 #ifdef GEM_DEBUG 2076 aprint_debug("%s: link up: half duplex\n", 2077 sc->sc_dev.dv_xname); 2078 #endif 2079 } else { 2080 #ifdef GEM_DEBUG 2081 aprint_debug("%s: duplex mismatch\n", 2082 sc->sc_dev.dv_xname); 2083 #endif 2084 } 2085 gem_statuschange(sc); 2086 } else { 2087 if ((sc->sc_flags & GEM_LINK) == 0) { 2088 return 1; 2089 } 2090 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_NONE; 2091 sc->sc_mii.mii_media_status = IFM_AVALID; 2092 #ifdef GEM_DEBUG 2093 aprint_debug("%s: link down\n", 2094 sc->sc_dev.dv_xname); 2095 #endif 2096 gem_statuschange(sc); 2097 2098 /* Start the 10 second timer */ 2099 callout_reset(&sc->sc_tick_ch, hz * 10, gem_tick, sc); 2100 } 2101 return 1; 2102 } 2103 2104 2105 2106 int 2107 gem_intr(v) 2108 void *v; 2109 { 2110 struct gem_softc *sc = (struct gem_softc *)v; 2111 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2112 bus_space_tag_t t = sc->sc_bustag; 2113 bus_space_handle_t h = sc->sc_h1; 2114 u_int32_t status; 2115 int r = 0; 2116 #ifdef GEM_DEBUG 2117 char bits[128]; 2118 #endif 2119 2120 /* XXX We should probably mask out interrupts until we're done */ 2121 2122 sc->sc_ev_intr.ev_count++; 2123 2124 status = bus_space_read_4(t, h, GEM_STATUS); 2125 DPRINTF(sc, ("%s: gem_intr: cplt 0x%x status %s\n", 2126 sc->sc_dev.dv_xname, (status >> 19), 2127 bitmask_snprintf(status, GEM_INTR_BITS, bits, sizeof(bits)))); 2128 2129 if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0) 2130 r |= gem_eint(sc, status); 2131 2132 /* We don't bother with GEM_INTR_TX_DONE */ 2133 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) { 2134 GEM_COUNTER_INCR(sc, sc_ev_txint); 2135 r |= gem_tint(sc); 2136 } 2137 2138 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) { 2139 GEM_COUNTER_INCR(sc, sc_ev_rxint); 2140 r |= gem_rint(sc); 2141 } 2142 2143 /* We should eventually do more than just print out error stats. */ 2144 if (status & GEM_INTR_TX_MAC) { 2145 int txstat = bus_space_read_4(t, h, GEM_MAC_TX_STATUS); 2146 if (txstat & ~GEM_MAC_TX_XMIT_DONE) 2147 printf("%s: MAC tx fault, status %x\n", 2148 sc->sc_dev.dv_xname, txstat); 2149 if (txstat & (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG)) 2150 gem_init(ifp); 2151 } 2152 if (status & GEM_INTR_RX_MAC) { 2153 int rxstat = bus_space_read_4(t, h, GEM_MAC_RX_STATUS); 2154 /* 2155 * At least with GEM_SUN_GEM and some GEM_SUN_ERI 2156 * revisions GEM_MAC_RX_OVERFLOW happen often due to a 2157 * silicon bug so handle them silently. Moreover, it's 2158 * likely that the receiver has hung so we reset it. 2159 */ 2160 if (rxstat & GEM_MAC_RX_OVERFLOW) { 2161 ifp->if_ierrors++; 2162 gem_reset_rxdma(sc); 2163 } else if (rxstat & ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT)) 2164 printf("%s: MAC rx fault, status 0x%02x\n", 2165 sc->sc_dev.dv_xname, rxstat); 2166 } 2167 if (status & GEM_INTR_PCS) { 2168 r |= gem_pint(sc); 2169 } 2170 2171 /* Do we need to do anything with these? 2172 if ((status & GEM_MAC_CONTROL_STATUS) != 0) { 2173 status2 = bus_read_4(sc->sc_res[0], GEM_MAC_CONTROL_STATUS); 2174 if ((status2 & GEM_MAC_PAUSED) != 0) 2175 aprintf_debug("%s: PAUSE received (%d slots)\n", 2176 GEM_MAC_PAUSE_TIME(status2), sc->sc_dev.dv_xname); 2177 if ((status2 & GEM_MAC_PAUSE) != 0) 2178 aprintf_debug("%s: transited to PAUSE state\n", 2179 sc->sc_dev.dv_xname); 2180 if ((status2 & GEM_MAC_RESUME) != 0) 2181 aprintf_debug("%s: transited to non-PAUSE state\n", 2182 sc->sc_dev.dv_xname); 2183 } 2184 if ((status & GEM_INTR_MIF) != 0) 2185 aprintf_debug("%s: MIF interrupt\n", sc->sc_dev.dv_xname); 2186 */ 2187 #if NRND > 0 2188 rnd_add_uint32(&sc->rnd_source, status); 2189 #endif 2190 return (r); 2191 } 2192 2193 2194 void 2195 gem_watchdog(ifp) 2196 struct ifnet *ifp; 2197 { 2198 struct gem_softc *sc = ifp->if_softc; 2199 2200 DPRINTF(sc, ("gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x " 2201 "GEM_MAC_RX_CONFIG %x\n", 2202 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_RX_CONFIG), 2203 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_MAC_RX_STATUS), 2204 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_MAC_RX_CONFIG))); 2205 2206 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 2207 ++ifp->if_oerrors; 2208 2209 /* Try to get more packets going. */ 2210 gem_start(ifp); 2211 } 2212 2213 /* 2214 * Initialize the MII Management Interface 2215 */ 2216 void 2217 gem_mifinit(sc) 2218 struct gem_softc *sc; 2219 { 2220 bus_space_tag_t t = sc->sc_bustag; 2221 bus_space_handle_t mif = sc->sc_h1; 2222 2223 /* Configure the MIF in frame mode */ 2224 sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 2225 sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA; 2226 bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config); 2227 } 2228 2229 /* 2230 * MII interface 2231 * 2232 * The GEM MII interface supports at least three different operating modes: 2233 * 2234 * Bitbang mode is implemented using data, clock and output enable registers. 2235 * 2236 * Frame mode is implemented by loading a complete frame into the frame 2237 * register and polling the valid bit for completion. 2238 * 2239 * Polling mode uses the frame register but completion is indicated by 2240 * an interrupt. 2241 * 2242 */ 2243 static int 2244 gem_mii_readreg(self, phy, reg) 2245 struct device *self; 2246 int phy, reg; 2247 { 2248 struct gem_softc *sc = (void *)self; 2249 bus_space_tag_t t = sc->sc_bustag; 2250 bus_space_handle_t mif = sc->sc_h1; 2251 int n; 2252 u_int32_t v; 2253 2254 #ifdef GEM_DEBUG1 2255 if (sc->sc_debug) 2256 printf("gem_mii_readreg: PHY %d reg %d\n", phy, reg); 2257 #endif 2258 2259 /* Construct the frame command */ 2260 v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) | 2261 GEM_MIF_FRAME_READ; 2262 2263 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 2264 for (n = 0; n < 100; n++) { 2265 DELAY(1); 2266 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 2267 if (v & GEM_MIF_FRAME_TA0) 2268 return (v & GEM_MIF_FRAME_DATA); 2269 } 2270 2271 printf("%s: mii_read timeout\n", sc->sc_dev.dv_xname); 2272 return (0); 2273 } 2274 2275 static void 2276 gem_mii_writereg(self, phy, reg, val) 2277 struct device *self; 2278 int phy, reg, val; 2279 { 2280 struct gem_softc *sc = (void *)self; 2281 bus_space_tag_t t = sc->sc_bustag; 2282 bus_space_handle_t mif = sc->sc_h1; 2283 int n; 2284 u_int32_t v; 2285 2286 #ifdef GEM_DEBUG1 2287 if (sc->sc_debug) 2288 printf("gem_mii_writereg: PHY %d reg %d val %x\n", 2289 phy, reg, val); 2290 #endif 2291 2292 /* Construct the frame command */ 2293 v = GEM_MIF_FRAME_WRITE | 2294 (phy << GEM_MIF_PHY_SHIFT) | 2295 (reg << GEM_MIF_REG_SHIFT) | 2296 (val & GEM_MIF_FRAME_DATA); 2297 2298 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 2299 for (n = 0; n < 100; n++) { 2300 DELAY(1); 2301 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 2302 if (v & GEM_MIF_FRAME_TA0) 2303 return; 2304 } 2305 2306 printf("%s: mii_write timeout\n", sc->sc_dev.dv_xname); 2307 } 2308 2309 static void 2310 gem_mii_statchg(dev) 2311 struct device *dev; 2312 { 2313 struct gem_softc *sc = (void *)dev; 2314 #ifdef GEM_DEBUG 2315 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 2316 #endif 2317 2318 #ifdef GEM_DEBUG 2319 if (sc->sc_debug) 2320 printf("gem_mii_statchg: status change: phy = %d\n", 2321 sc->sc_phys[instance]); 2322 #endif 2323 gem_statuschange(sc); 2324 } 2325 2326 /* 2327 * Common status change for gem_mii_statchg() and gem_pint() 2328 */ 2329 void 2330 gem_statuschange(struct gem_softc* sc) 2331 { 2332 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2333 bus_space_tag_t t = sc->sc_bustag; 2334 bus_space_handle_t mac = sc->sc_h1; 2335 int gigabit; 2336 u_int32_t rxcfg, txcfg, v; 2337 2338 if ((sc->sc_mii.mii_media_status & IFM_ACTIVE) != 0 && 2339 IFM_SUBTYPE(sc->sc_mii.mii_media_active) != IFM_NONE) 2340 sc->sc_flags |= GEM_LINK; 2341 else 2342 sc->sc_flags &= ~GEM_LINK; 2343 2344 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 2345 gigabit = 1; 2346 else 2347 gigabit = 0; 2348 2349 /* 2350 * The configuration done here corresponds to the steps F) and 2351 * G) and as far as enabling of RX and TX MAC goes also step H) 2352 * of the initialization sequence outlined in section 3.2.1 of 2353 * the GEM Gigabit Ethernet ASIC Specification. 2354 */ 2355 2356 rxcfg = bus_space_read_4(t, mac, GEM_MAC_RX_CONFIG); 2357 rxcfg &= ~(GEM_MAC_RX_CARR_EXTEND | GEM_MAC_RX_ENABLE); 2358 txcfg = GEM_MAC_TX_ENA_IPG0 | GEM_MAC_TX_NGU | GEM_MAC_TX_NGU_LIMIT; 2359 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 2360 txcfg |= GEM_MAC_TX_IGN_CARRIER | GEM_MAC_TX_IGN_COLLIS; 2361 else if (gigabit) { 2362 rxcfg |= GEM_MAC_RX_CARR_EXTEND; 2363 txcfg |= GEM_MAC_RX_CARR_EXTEND; 2364 } 2365 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0); 2366 bus_space_barrier(t, mac, GEM_MAC_TX_CONFIG, 4, 2367 BUS_SPACE_BARRIER_WRITE); 2368 if (!gem_bitwait(sc, mac, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)) 2369 aprint_normal("%s: cannot disable TX MAC\n", 2370 sc->sc_dev.dv_xname); 2371 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, txcfg); 2372 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, 0); 2373 bus_space_barrier(t, mac, GEM_MAC_RX_CONFIG, 4, 2374 BUS_SPACE_BARRIER_WRITE); 2375 if (!gem_bitwait(sc, mac, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)) 2376 aprint_normal("%s: cannot disable RX MAC\n", 2377 sc->sc_dev.dv_xname); 2378 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, rxcfg); 2379 2380 v = bus_space_read_4(t, mac, GEM_MAC_CONTROL_CONFIG) & 2381 ~(GEM_MAC_CC_RX_PAUSE | GEM_MAC_CC_TX_PAUSE); 2382 bus_space_write_4(t, mac, GEM_MAC_CONTROL_CONFIG, v); 2383 2384 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) == 0 && 2385 gigabit != 0) 2386 bus_space_write_4(t, mac, GEM_MAC_SLOT_TIME, 2387 GEM_MAC_SLOT_TIME_CARR_EXTEND); 2388 else 2389 bus_space_write_4(t, mac, GEM_MAC_SLOT_TIME, 2390 GEM_MAC_SLOT_TIME_NORMAL); 2391 2392 /* XIF Configuration */ 2393 if (sc->sc_flags & GEM_LINK) 2394 v = GEM_MAC_XIF_LINK_LED; 2395 else 2396 v = 0; 2397 v |= GEM_MAC_XIF_TX_MII_ENA; 2398 2399 /* If an external transceiver is connected, enable its MII drivers */ 2400 sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG); 2401 if ((sc->sc_flags &(GEM_SERDES | GEM_SERIAL)) == 0) { 2402 if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) { 2403 /* External MII needs echo disable if half duplex. */ 2404 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & 2405 IFM_FDX) != 0) 2406 /* turn on full duplex LED */ 2407 v |= GEM_MAC_XIF_FDPLX_LED; 2408 else 2409 /* half duplex -- disable echo */ 2410 v |= GEM_MAC_XIF_ECHO_DISABL; 2411 if (gigabit) 2412 v |= GEM_MAC_XIF_GMII_MODE; 2413 else 2414 v &= ~GEM_MAC_XIF_GMII_MODE; 2415 } else 2416 /* Internal MII needs buf enable */ 2417 v |= GEM_MAC_XIF_MII_BUF_ENA; 2418 } else { 2419 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 2420 v |= GEM_MAC_XIF_FDPLX_LED; 2421 v |= GEM_MAC_XIF_GMII_MODE; 2422 } 2423 bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v); 2424 2425 if ((ifp->if_flags & IFF_RUNNING) != 0 && 2426 (sc->sc_flags & GEM_LINK) != 0) { 2427 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 2428 txcfg | GEM_MAC_TX_ENABLE); 2429 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, 2430 rxcfg | GEM_MAC_RX_ENABLE); 2431 } 2432 } 2433 2434 int 2435 gem_ser_mediachange(struct ifnet *ifp) 2436 { 2437 struct gem_softc *sc = ifp->if_softc; 2438 u_int s, t; 2439 2440 if (IFM_TYPE(sc->sc_mii.mii_media.ifm_media) != IFM_ETHER) 2441 return EINVAL; 2442 2443 s = IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media); 2444 if (s == IFM_AUTO) { 2445 if (sc->sc_mii_media != s) { 2446 #ifdef GEM_DEBUG 2447 aprint_debug("%s: setting media to auto\n", 2448 sc->sc_dev.dv_xname); 2449 #endif 2450 sc->sc_mii_media = s; 2451 if (ifp->if_flags & IFF_UP) { 2452 gem_pcs_stop(sc, 0); 2453 gem_pcs_start(sc); 2454 } 2455 } 2456 return 0; 2457 } 2458 if (s == IFM_1000_SX) { 2459 t = IFM_OPTIONS(sc->sc_mii.mii_media.ifm_media); 2460 if (t == IFM_FDX || t == IFM_HDX) { 2461 if (sc->sc_mii_media != t) { 2462 sc->sc_mii_media = t; 2463 #ifdef GEM_DEBUG 2464 aprint_debug("%s:" 2465 " setting media to 1000baseSX-%s\n", 2466 sc->sc_dev.dv_xname, 2467 t == IFM_FDX ? "FDX" : "HDX"); 2468 #endif 2469 if (ifp->if_flags & IFF_UP) { 2470 gem_pcs_stop(sc, 0); 2471 gem_pcs_start(sc); 2472 } 2473 } 2474 return 0; 2475 } 2476 } 2477 return EINVAL; 2478 } 2479 2480 void 2481 gem_ser_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2482 { 2483 struct gem_softc *sc = ifp->if_softc; 2484 2485 if ((ifp->if_flags & IFF_UP) == 0) 2486 return; 2487 ifmr->ifm_active = sc->sc_mii.mii_media_active; 2488 ifmr->ifm_status = sc->sc_mii.mii_media_status; 2489 } 2490 2491 /* 2492 * Process an ioctl request. 2493 */ 2494 int 2495 gem_ioctl(ifp, cmd, data) 2496 struct ifnet *ifp; 2497 u_long cmd; 2498 void *data; 2499 { 2500 struct gem_softc *sc = ifp->if_softc; 2501 int s, error = 0; 2502 2503 s = splnet(); 2504 2505 switch (cmd) { 2506 case SIOCSIFFLAGS: 2507 #define RESETIGN (IFF_CANTCHANGE|IFF_DEBUG) 2508 if (((ifp->if_flags & (IFF_UP|IFF_RUNNING)) 2509 == (IFF_UP|IFF_RUNNING)) 2510 && ((ifp->if_flags & (~RESETIGN)) 2511 == (sc->sc_if_flags & (~RESETIGN)))) { 2512 gem_setladrf(sc); 2513 break; 2514 } 2515 #undef RESETIGN 2516 /*FALLTHROUGH*/ 2517 default: 2518 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 2519 break; 2520 2521 error = 0; 2522 2523 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 2524 ; 2525 else if (ifp->if_flags & IFF_RUNNING) { 2526 /* 2527 * Multicast list has changed; set the hardware filter 2528 * accordingly. 2529 */ 2530 gem_setladrf(sc); 2531 } 2532 break; 2533 } 2534 2535 /* Try to get things going again */ 2536 if (ifp->if_flags & IFF_UP) 2537 gem_start(ifp); 2538 splx(s); 2539 return (error); 2540 } 2541 2542 2543 void 2544 gem_shutdown(arg) 2545 void *arg; 2546 { 2547 struct gem_softc *sc = (struct gem_softc *)arg; 2548 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2549 2550 gem_stop(ifp, 1); 2551 } 2552 2553 /* 2554 * Set up the logical address filter. 2555 */ 2556 void 2557 gem_setladrf(sc) 2558 struct gem_softc *sc; 2559 { 2560 struct ethercom *ec = &sc->sc_ethercom; 2561 struct ifnet *ifp = &ec->ec_if; 2562 struct ether_multi *enm; 2563 struct ether_multistep step; 2564 bus_space_tag_t t = sc->sc_bustag; 2565 bus_space_handle_t h = sc->sc_h1; 2566 u_int32_t crc; 2567 u_int32_t hash[16]; 2568 u_int32_t v; 2569 int i; 2570 2571 /* Get current RX configuration */ 2572 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 2573 2574 /* 2575 * Turn off promiscuous mode, promiscuous group mode (all multicast), 2576 * and hash filter. Depending on the case, the right bit will be 2577 * enabled. 2578 */ 2579 v &= ~(GEM_MAC_RX_PROMISCUOUS|GEM_MAC_RX_HASH_FILTER| 2580 GEM_MAC_RX_PROMISC_GRP); 2581 2582 if ((ifp->if_flags & IFF_PROMISC) != 0) { 2583 /* Turn on promiscuous mode */ 2584 v |= GEM_MAC_RX_PROMISCUOUS; 2585 ifp->if_flags |= IFF_ALLMULTI; 2586 goto chipit; 2587 } 2588 2589 /* 2590 * Set up multicast address filter by passing all multicast addresses 2591 * through a crc generator, and then using the high order 8 bits as an 2592 * index into the 256 bit logical address filter. The high order 4 2593 * bits selects the word, while the other 4 bits select the bit within 2594 * the word (where bit 0 is the MSB). 2595 */ 2596 2597 /* Clear hash table */ 2598 memset(hash, 0, sizeof(hash)); 2599 2600 ETHER_FIRST_MULTI(step, ec, enm); 2601 while (enm != NULL) { 2602 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2603 /* 2604 * We must listen to a range of multicast addresses. 2605 * For now, just accept all multicasts, rather than 2606 * trying to set only those filter bits needed to match 2607 * the range. (At this time, the only use of address 2608 * ranges is for IP multicast routing, for which the 2609 * range is big enough to require all bits set.) 2610 * XXX should use the address filters for this 2611 */ 2612 ifp->if_flags |= IFF_ALLMULTI; 2613 v |= GEM_MAC_RX_PROMISC_GRP; 2614 goto chipit; 2615 } 2616 2617 /* Get the LE CRC32 of the address */ 2618 crc = ether_crc32_le(enm->enm_addrlo, sizeof(enm->enm_addrlo)); 2619 2620 /* Just want the 8 most significant bits. */ 2621 crc >>= 24; 2622 2623 /* Set the corresponding bit in the filter. */ 2624 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 2625 2626 ETHER_NEXT_MULTI(step, enm); 2627 } 2628 2629 v |= GEM_MAC_RX_HASH_FILTER; 2630 ifp->if_flags &= ~IFF_ALLMULTI; 2631 2632 /* Now load the hash table into the chip (if we are using it) */ 2633 for (i = 0; i < 16; i++) { 2634 bus_space_write_4(t, h, 2635 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1-GEM_MAC_HASH0), 2636 hash[i]); 2637 } 2638 2639 chipit: 2640 sc->sc_if_flags = ifp->if_flags; 2641 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 2642 } 2643 2644 #if notyet 2645 2646 /* 2647 * gem_power: 2648 * 2649 * Power management (suspend/resume) hook. 2650 */ 2651 void 2652 gem_power(why, arg) 2653 int why; 2654 void *arg; 2655 { 2656 struct gem_softc *sc = arg; 2657 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2658 int s; 2659 2660 s = splnet(); 2661 switch (why) { 2662 case PWR_SUSPEND: 2663 case PWR_STANDBY: 2664 gem_stop(ifp, 1); 2665 if (sc->sc_power != NULL) 2666 (*sc->sc_power)(sc, why); 2667 break; 2668 case PWR_RESUME: 2669 if (ifp->if_flags & IFF_UP) { 2670 if (sc->sc_power != NULL) 2671 (*sc->sc_power)(sc, why); 2672 gem_init(ifp); 2673 } 2674 break; 2675 case PWR_SOFTSUSPEND: 2676 case PWR_SOFTSTANDBY: 2677 case PWR_SOFTRESUME: 2678 break; 2679 } 2680 splx(s); 2681 } 2682 #endif 2683
Indexes created Tue Sep 23 23:09:58 GMT 2025