gem.c revision 1.75
1 /* $NetBSD: gem.c,v 1.75 2008/03/11 23:58:06 dyoung Exp $ */ 2 3 /* 4 * 5 * Copyright (C) 2001 Eduardo Horvath. 6 * Copyright (c) 2001-2003 Thomas Moestl 7 * All rights reserved. 8 * 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 */ 32 33 /* 34 * Driver for Apple GMAC, Sun ERI and Sun GEM Ethernet controllers 35 * See `GEM Gigabit Ethernet ASIC Specification' 36 * http://www.sun.com/processors/manuals/ge.pdf 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: gem.c,v 1.75 2008/03/11 23:58:06 dyoung Exp $"); 41 42 #include "opt_inet.h" 43 #include "bpfilter.h" 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/callout.h> 48 #include <sys/mbuf.h> 49 #include <sys/syslog.h> 50 #include <sys/malloc.h> 51 #include <sys/kernel.h> 52 #include <sys/socket.h> 53 #include <sys/ioctl.h> 54 #include <sys/errno.h> 55 #include <sys/device.h> 56 57 #include <machine/endian.h> 58 59 #include <uvm/uvm_extern.h> 60 61 #include <net/if.h> 62 #include <net/if_dl.h> 63 #include <net/if_media.h> 64 #include <net/if_ether.h> 65 66 #ifdef INET 67 #include <netinet/in.h> 68 #include <netinet/in_systm.h> 69 #include <netinet/in_var.h> 70 #include <netinet/ip.h> 71 #include <netinet/tcp.h> 72 #include <netinet/udp.h> 73 #endif 74 75 #if NBPFILTER > 0 76 #include <net/bpf.h> 77 #endif 78 79 #include <sys/bus.h> 80 #include <sys/intr.h> 81 82 #include <dev/mii/mii.h> 83 #include <dev/mii/miivar.h> 84 #include <dev/mii/mii_bitbang.h> 85 86 #include <dev/ic/gemreg.h> 87 #include <dev/ic/gemvar.h> 88 89 #define TRIES 10000 90 91 static void gem_start(struct ifnet *); 92 static void gem_stop(struct ifnet *, int); 93 int gem_ioctl(struct ifnet *, u_long, void *); 94 void gem_tick(void *); 95 void gem_watchdog(struct ifnet *); 96 void gem_shutdown(void *); 97 void gem_pcs_start(struct gem_softc *sc); 98 void gem_pcs_stop(struct gem_softc *sc, int); 99 int gem_init(struct ifnet *); 100 void gem_init_regs(struct gem_softc *sc); 101 static int gem_ringsize(int sz); 102 static int gem_meminit(struct gem_softc *); 103 void gem_mifinit(struct gem_softc *); 104 static int gem_bitwait(struct gem_softc *sc, bus_space_handle_t, int, 105 u_int32_t, u_int32_t); 106 void gem_reset(struct gem_softc *); 107 int gem_reset_rx(struct gem_softc *sc); 108 static void gem_reset_rxdma(struct gem_softc *sc); 109 static void gem_rx_common(struct gem_softc *sc); 110 int gem_reset_tx(struct gem_softc *sc); 111 int gem_disable_rx(struct gem_softc *sc); 112 int gem_disable_tx(struct gem_softc *sc); 113 static void gem_rxdrain(struct gem_softc *sc); 114 int gem_add_rxbuf(struct gem_softc *sc, int idx); 115 void gem_setladrf(struct gem_softc *); 116 117 /* MII methods & callbacks */ 118 static int gem_mii_readreg(struct device *, int, int); 119 static void gem_mii_writereg(struct device *, int, int, int); 120 static void gem_mii_statchg(struct device *); 121 122 void gem_statuschange(struct gem_softc *); 123 124 int gem_ser_mediachange(struct ifnet *); 125 void gem_ser_mediastatus(struct ifnet *, struct ifmediareq *); 126 127 struct mbuf *gem_get(struct gem_softc *, int, int); 128 int gem_put(struct gem_softc *, int, struct mbuf *); 129 void gem_read(struct gem_softc *, int, int); 130 int gem_pint(struct gem_softc *); 131 int gem_eint(struct gem_softc *, u_int); 132 int gem_rint(struct gem_softc *); 133 int gem_tint(struct gem_softc *); 134 void gem_power(int, void *); 135 136 #ifdef GEM_DEBUG 137 static void gem_txsoft_print(const struct gem_softc *, int, int); 138 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 139 printf x 140 #else 141 #define DPRINTF(sc, x) /* nothing */ 142 #endif 143 144 #define ETHER_MIN_TX (ETHERMIN + sizeof(struct ether_header)) 145 146 147 /* 148 * gem_attach: 149 * 150 * Attach a Gem interface to the system. 151 */ 152 void 153 gem_attach(sc, enaddr) 154 struct gem_softc *sc; 155 const uint8_t *enaddr; 156 { 157 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 158 struct mii_data *mii = &sc->sc_mii; 159 bus_space_tag_t t = sc->sc_bustag; 160 bus_space_handle_t h = sc->sc_h1; 161 struct ifmedia_entry *ifm; 162 int i, error; 163 u_int32_t v; 164 char *nullbuf; 165 166 /* Make sure the chip is stopped. */ 167 ifp->if_softc = sc; 168 gem_reset(sc); 169 170 /* 171 * Allocate the control data structures, and create and load the 172 * DMA map for it. gem_control_data is 9216 bytes, we have space for 173 * the padding buffer in the bus_dmamem_alloc()'d memory. 174 */ 175 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 176 sizeof(struct gem_control_data) + ETHER_MIN_TX, PAGE_SIZE, 177 0, &sc->sc_cdseg, 1, &sc->sc_cdnseg, 0)) != 0) { 178 aprint_error( 179 "%s: unable to allocate control data, error = %d\n", 180 sc->sc_dev.dv_xname, error); 181 goto fail_0; 182 } 183 184 /* XXX should map this in with correct endianness */ 185 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg, 186 sizeof(struct gem_control_data), (void **)&sc->sc_control_data, 187 BUS_DMA_COHERENT)) != 0) { 188 aprint_error("%s: unable to map control data, error = %d\n", 189 sc->sc_dev.dv_xname, error); 190 goto fail_1; 191 } 192 193 nullbuf = 194 (char *)sc->sc_control_data + sizeof(struct gem_control_data); 195 196 if ((error = bus_dmamap_create(sc->sc_dmatag, 197 sizeof(struct gem_control_data), 1, 198 sizeof(struct gem_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 199 aprint_error("%s: unable to create control data DMA map, " 200 "error = %d\n", sc->sc_dev.dv_xname, error); 201 goto fail_2; 202 } 203 204 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 205 sc->sc_control_data, sizeof(struct gem_control_data), NULL, 206 0)) != 0) { 207 aprint_error( 208 "%s: unable to load control data DMA map, error = %d\n", 209 sc->sc_dev.dv_xname, error); 210 goto fail_3; 211 } 212 213 memset(nullbuf, 0, ETHER_MIN_TX); 214 if ((error = bus_dmamap_create(sc->sc_dmatag, 215 ETHER_MIN_TX, 1, ETHER_MIN_TX, 0, 0, &sc->sc_nulldmamap)) != 0) { 216 aprint_error("%s: unable to create padding DMA map, " 217 "error = %d\n", sc->sc_dev.dv_xname, error); 218 goto fail_4; 219 } 220 221 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_nulldmamap, 222 nullbuf, ETHER_MIN_TX, NULL, 0)) != 0) { 223 aprint_error( 224 "%s: unable to load padding DMA map, error = %d\n", 225 sc->sc_dev.dv_xname, error); 226 goto fail_5; 227 } 228 229 bus_dmamap_sync(sc->sc_dmatag, sc->sc_nulldmamap, 0, ETHER_MIN_TX, 230 BUS_DMASYNC_PREWRITE); 231 232 /* 233 * Initialize the transmit job descriptors. 234 */ 235 SIMPLEQ_INIT(&sc->sc_txfreeq); 236 SIMPLEQ_INIT(&sc->sc_txdirtyq); 237 238 /* 239 * Create the transmit buffer DMA maps. 240 */ 241 for (i = 0; i < GEM_TXQUEUELEN; i++) { 242 struct gem_txsoft *txs; 243 244 txs = &sc->sc_txsoft[i]; 245 txs->txs_mbuf = NULL; 246 if ((error = bus_dmamap_create(sc->sc_dmatag, 247 ETHER_MAX_LEN_JUMBO, GEM_NTXSEGS, 248 ETHER_MAX_LEN_JUMBO, 0, 0, 249 &txs->txs_dmamap)) != 0) { 250 aprint_error("%s: unable to create tx DMA map %d, " 251 "error = %d\n", sc->sc_dev.dv_xname, i, error); 252 goto fail_6; 253 } 254 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 255 } 256 257 /* 258 * Create the receive buffer DMA maps. 259 */ 260 for (i = 0; i < GEM_NRXDESC; i++) { 261 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, 262 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 263 aprint_error("%s: unable to create rx DMA map %d, " 264 "error = %d\n", sc->sc_dev.dv_xname, i, error); 265 goto fail_7; 266 } 267 sc->sc_rxsoft[i].rxs_mbuf = NULL; 268 } 269 270 /* Initialize ifmedia structures and MII info */ 271 mii->mii_ifp = ifp; 272 mii->mii_readreg = gem_mii_readreg; 273 mii->mii_writereg = gem_mii_writereg; 274 mii->mii_statchg = gem_mii_statchg; 275 276 sc->sc_ethercom.ec_mii = mii; 277 278 /* 279 * Initialization based on `GEM Gigabit Ethernet ASIC Specification' 280 * Section 3.2.1 `Initialization Sequence'. 281 * However, we can't assume SERDES or Serialink if neither 282 * GEM_MIF_CONFIG_MDI0 nor GEM_MIF_CONFIG_MDI1 are set 283 * being set, as both are set on Sun X1141A (with SERDES). So, 284 * we rely on our bus attachment setting GEM_SERDES or GEM_SERIAL. 285 * Also, for Apple variants with 2 PHY's, we prefer the external 286 * PHY over the internal PHY. 287 */ 288 gem_mifinit(sc); 289 290 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) { 291 ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange, 292 ether_mediastatus); 293 mii_attach(&sc->sc_dev, mii, 0xffffffff, 294 MII_PHY_ANY, MII_OFFSET_ANY, MIIF_FORCEANEG); 295 if (LIST_EMPTY(&mii->mii_phys)) { 296 /* No PHY attached */ 297 aprint_error("%s: PHY probe failed\n", 298 sc->sc_dev.dv_xname); 299 goto fail_7; 300 } else { 301 struct mii_softc *child; 302 303 /* 304 * Walk along the list of attached MII devices and 305 * establish an `MII instance' to `PHY number' 306 * mapping. 307 */ 308 LIST_FOREACH(child, &mii->mii_phys, mii_list) { 309 /* 310 * Note: we support just one PHY: the internal 311 * or external MII is already selected for us 312 * by the GEM_MIF_CONFIG register. 313 */ 314 if (child->mii_phy > 1 || child->mii_inst > 0) { 315 aprint_error( 316 "%s: cannot accommodate MII device" 317 " %s at PHY %d, instance %d\n", 318 sc->sc_dev.dv_xname, 319 child->mii_dev.dv_xname, 320 child->mii_phy, child->mii_inst); 321 continue; 322 } 323 sc->sc_phys[child->mii_inst] = child->mii_phy; 324 } 325 326 /* 327 * Now select and activate the PHY we will use. 328 * 329 * The order of preference is External (MDI1), 330 * then Internal (MDI0), 331 */ 332 if (sc->sc_phys[1]) { 333 #ifdef GEM_DEBUG 334 aprint_debug("%s: using external PHY\n", 335 sc->sc_dev.dv_xname); 336 #endif 337 sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL; 338 } else { 339 #ifdef GEM_DEBUG 340 aprint_debug("%s: using internal PHY\n", 341 sc->sc_dev.dv_xname); 342 sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL; 343 #endif 344 } 345 bus_space_write_4(t, h, GEM_MIF_CONFIG, 346 sc->sc_mif_config); 347 if (sc->sc_variant != GEM_SUN_ERI) 348 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 349 GEM_MII_DATAPATH_MII); 350 351 /* 352 * XXX - we can really do the following ONLY if the 353 * PHY indeed has the auto negotiation capability!! 354 */ 355 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 356 } 357 } else { 358 ifmedia_init(&mii->mii_media, IFM_IMASK, gem_ser_mediachange, 359 gem_ser_mediastatus); 360 /* SERDES or Serialink */ 361 if (sc->sc_flags & GEM_SERDES) { 362 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 363 GEM_MII_DATAPATH_SERDES); 364 } else { 365 sc->sc_flags |= GEM_SERIAL; 366 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 367 GEM_MII_DATAPATH_SERIAL); 368 } 369 370 aprint_normal("%s: using external PCS %s: ", 371 sc->sc_dev.dv_xname, 372 sc->sc_flags & GEM_SERDES ? "SERDES" : "Serialink"); 373 374 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO, 0, NULL); 375 /* Check for FDX and HDX capabilities */ 376 sc->sc_mii_anar = bus_space_read_4(t, h, GEM_MII_ANAR); 377 if (sc->sc_mii_anar & GEM_MII_ANEG_FUL_DUPLX) { 378 ifmedia_add(&sc->sc_mii.mii_media, 379 IFM_ETHER|IFM_1000_SX|IFM_MANUAL|IFM_FDX, 0, NULL); 380 aprint_normal("1000baseSX-FDX, "); 381 } 382 if (sc->sc_mii_anar & GEM_MII_ANEG_HLF_DUPLX) { 383 ifmedia_add(&sc->sc_mii.mii_media, 384 IFM_ETHER|IFM_1000_SX|IFM_MANUAL|IFM_HDX, 0, NULL); 385 aprint_normal("1000baseSX-HDX, "); 386 } 387 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 388 sc->sc_mii_media = IFM_AUTO; 389 aprint_normal("auto\n"); 390 391 gem_pcs_stop(sc, 1); 392 } 393 394 /* 395 * From this point forward, the attachment cannot fail. A failure 396 * before this point releases all resources that may have been 397 * allocated. 398 */ 399 400 /* Announce ourselves. */ 401 aprint_normal("%s: Ethernet address %s", sc->sc_dev.dv_xname, 402 ether_sprintf(enaddr)); 403 404 /* Get RX FIFO size */ 405 sc->sc_rxfifosize = 64 * 406 bus_space_read_4(t, h, GEM_RX_FIFO_SIZE); 407 aprint_normal(", %uKB RX fifo", sc->sc_rxfifosize / 1024); 408 409 /* Get TX FIFO size */ 410 v = bus_space_read_4(t, h, GEM_TX_FIFO_SIZE); 411 aprint_normal(", %uKB TX fifo\n", v / 16); 412 413 /* Initialize ifnet structure. */ 414 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 415 ifp->if_softc = sc; 416 ifp->if_flags = 417 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 418 sc->sc_if_flags = ifp->if_flags; 419 /* 420 * The GEM hardware supports basic TCP checksum offloading only. 421 * Several (all?) revisions (Sun rev. 01 and Apple rev. 00 and 80) 422 * have bugs in the receive checksum, so don't enable it for now. 423 if ((GEM_IS_SUN(sc) && sc->sc_chiprev != 1) || 424 (GEM_IS_APPLE(sc) && 425 (sc->sc_chiprev != 0 && sc->sc_chiprev != 0x80))) 426 ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Rx; 427 */ 428 ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Tx; 429 ifp->if_start = gem_start; 430 ifp->if_ioctl = gem_ioctl; 431 ifp->if_watchdog = gem_watchdog; 432 ifp->if_stop = gem_stop; 433 ifp->if_init = gem_init; 434 IFQ_SET_READY(&ifp->if_snd); 435 436 /* 437 * If we support GigE media, we support jumbo frames too. 438 * Unless we are Apple. 439 */ 440 TAILQ_FOREACH(ifm, &sc->sc_mii.mii_media.ifm_list, ifm_list) { 441 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_T || 442 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_SX || 443 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_LX || 444 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_CX) { 445 if (!GEM_IS_APPLE(sc)) 446 sc->sc_ethercom.ec_capabilities 447 |= ETHERCAP_JUMBO_MTU; 448 sc->sc_flags |= GEM_GIGABIT; 449 break; 450 } 451 } 452 453 /* claim 802.1q capability */ 454 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 455 456 /* Attach the interface. */ 457 if_attach(ifp); 458 ether_ifattach(ifp, enaddr); 459 460 sc->sc_sh = shutdownhook_establish(gem_shutdown, sc); 461 if (sc->sc_sh == NULL) 462 panic("gem_config: can't establish shutdownhook"); 463 464 #if NRND > 0 465 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 466 RND_TYPE_NET, 0); 467 #endif 468 469 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, 470 NULL, sc->sc_dev.dv_xname, "interrupts"); 471 #ifdef GEM_COUNTERS 472 evcnt_attach_dynamic(&sc->sc_ev_txint, EVCNT_TYPE_INTR, 473 &sc->sc_ev_intr, sc->sc_dev.dv_xname, "tx interrupts"); 474 evcnt_attach_dynamic(&sc->sc_ev_rxint, EVCNT_TYPE_INTR, 475 &sc->sc_ev_intr, sc->sc_dev.dv_xname, "rx interrupts"); 476 evcnt_attach_dynamic(&sc->sc_ev_rxfull, EVCNT_TYPE_INTR, 477 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx ring full"); 478 evcnt_attach_dynamic(&sc->sc_ev_rxnobuf, EVCNT_TYPE_INTR, 479 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx malloc failure"); 480 evcnt_attach_dynamic(&sc->sc_ev_rxhist[0], EVCNT_TYPE_INTR, 481 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 0desc"); 482 evcnt_attach_dynamic(&sc->sc_ev_rxhist[1], EVCNT_TYPE_INTR, 483 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 1desc"); 484 evcnt_attach_dynamic(&sc->sc_ev_rxhist[2], EVCNT_TYPE_INTR, 485 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 2desc"); 486 evcnt_attach_dynamic(&sc->sc_ev_rxhist[3], EVCNT_TYPE_INTR, 487 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx 3desc"); 488 evcnt_attach_dynamic(&sc->sc_ev_rxhist[4], EVCNT_TYPE_INTR, 489 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >3desc"); 490 evcnt_attach_dynamic(&sc->sc_ev_rxhist[5], EVCNT_TYPE_INTR, 491 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >7desc"); 492 evcnt_attach_dynamic(&sc->sc_ev_rxhist[6], EVCNT_TYPE_INTR, 493 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >15desc"); 494 evcnt_attach_dynamic(&sc->sc_ev_rxhist[7], EVCNT_TYPE_INTR, 495 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >31desc"); 496 evcnt_attach_dynamic(&sc->sc_ev_rxhist[8], EVCNT_TYPE_INTR, 497 &sc->sc_ev_rxint, sc->sc_dev.dv_xname, "rx >63desc"); 498 #endif 499 500 #if notyet 501 /* 502 * Add a suspend hook to make sure we come back up after a 503 * resume. 504 */ 505 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 506 gem_power, sc); 507 if (sc->sc_powerhook == NULL) 508 aprint_error("%s: WARNING: unable to establish power hook\n", 509 sc->sc_dev.dv_xname); 510 #endif 511 512 callout_init(&sc->sc_tick_ch, 0); 513 return; 514 515 /* 516 * Free any resources we've allocated during the failed attach 517 * attempt. Do this in reverse order and fall through. 518 */ 519 fail_7: 520 for (i = 0; i < GEM_NRXDESC; i++) { 521 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 522 bus_dmamap_destroy(sc->sc_dmatag, 523 sc->sc_rxsoft[i].rxs_dmamap); 524 } 525 fail_6: 526 for (i = 0; i < GEM_TXQUEUELEN; i++) { 527 if (sc->sc_txsoft[i].txs_dmamap != NULL) 528 bus_dmamap_destroy(sc->sc_dmatag, 529 sc->sc_txsoft[i].txs_dmamap); 530 } 531 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 532 fail_5: 533 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_nulldmamap); 534 fail_4: 535 bus_dmamem_unmap(sc->sc_dmatag, (void *)nullbuf, ETHER_MIN_TX); 536 fail_3: 537 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 538 fail_2: 539 bus_dmamem_unmap(sc->sc_dmatag, (void *)sc->sc_control_data, 540 sizeof(struct gem_control_data)); 541 fail_1: 542 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 543 fail_0: 544 return; 545 } 546 547 548 void 549 gem_tick(arg) 550 void *arg; 551 { 552 struct gem_softc *sc = arg; 553 int s; 554 555 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) { 556 /* 557 * We have to reset everything if we failed to get a 558 * PCS interrupt. Restarting the callout is handled 559 * in gem_pcs_start(). 560 */ 561 gem_init(&sc->sc_ethercom.ec_if); 562 } else { 563 s = splnet(); 564 mii_tick(&sc->sc_mii); 565 splx(s); 566 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 567 } 568 } 569 570 static int 571 gem_bitwait(sc, h, r, clr, set) 572 struct gem_softc *sc; 573 bus_space_handle_t h; 574 int r; 575 u_int32_t clr; 576 u_int32_t set; 577 { 578 int i; 579 u_int32_t reg; 580 581 for (i = TRIES; i--; DELAY(100)) { 582 reg = bus_space_read_4(sc->sc_bustag, h, r); 583 if ((reg & clr) == 0 && (reg & set) == set) 584 return (1); 585 } 586 return (0); 587 } 588 589 void 590 gem_reset(sc) 591 struct gem_softc *sc; 592 { 593 bus_space_tag_t t = sc->sc_bustag; 594 bus_space_handle_t h = sc->sc_h2; 595 int s; 596 597 s = splnet(); 598 DPRINTF(sc, ("%s: gem_reset\n", sc->sc_dev.dv_xname)); 599 gem_reset_rx(sc); 600 gem_reset_tx(sc); 601 602 /* Do a full reset */ 603 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX|GEM_RESET_TX); 604 if (!gem_bitwait(sc, h, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0)) 605 printf("%s: cannot reset device\n", sc->sc_dev.dv_xname); 606 splx(s); 607 } 608 609 610 /* 611 * gem_rxdrain: 612 * 613 * Drain the receive queue. 614 */ 615 static void 616 gem_rxdrain(struct gem_softc *sc) 617 { 618 struct gem_rxsoft *rxs; 619 int i; 620 621 for (i = 0; i < GEM_NRXDESC; i++) { 622 rxs = &sc->sc_rxsoft[i]; 623 if (rxs->rxs_mbuf != NULL) { 624 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 625 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 626 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 627 m_freem(rxs->rxs_mbuf); 628 rxs->rxs_mbuf = NULL; 629 } 630 } 631 } 632 633 /* 634 * Reset the whole thing. 635 */ 636 static void 637 gem_stop(struct ifnet *ifp, int disable) 638 { 639 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 640 struct gem_txsoft *txs; 641 642 DPRINTF(sc, ("%s: gem_stop\n", sc->sc_dev.dv_xname)); 643 644 callout_stop(&sc->sc_tick_ch); 645 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 646 gem_pcs_stop(sc, disable); 647 else 648 mii_down(&sc->sc_mii); 649 650 /* XXX - Should we reset these instead? */ 651 gem_disable_tx(sc); 652 gem_disable_rx(sc); 653 654 /* 655 * Release any queued transmit buffers. 656 */ 657 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 658 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 659 if (txs->txs_mbuf != NULL) { 660 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 0, 661 txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 662 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 663 m_freem(txs->txs_mbuf); 664 txs->txs_mbuf = NULL; 665 } 666 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 667 } 668 669 /* 670 * Mark the interface down and cancel the watchdog timer. 671 */ 672 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 673 sc->sc_if_flags = ifp->if_flags; 674 ifp->if_timer = 0; 675 676 if (disable) 677 gem_rxdrain(sc); 678 } 679 680 681 /* 682 * Reset the receiver 683 */ 684 int 685 gem_reset_rx(struct gem_softc *sc) 686 { 687 bus_space_tag_t t = sc->sc_bustag; 688 bus_space_handle_t h = sc->sc_h1, h2 = sc->sc_h2; 689 690 /* 691 * Resetting while DMA is in progress can cause a bus hang, so we 692 * disable DMA first. 693 */ 694 gem_disable_rx(sc); 695 bus_space_write_4(t, h, GEM_RX_CONFIG, 0); 696 bus_space_barrier(t, h, GEM_RX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 697 /* Wait till it finishes */ 698 if (!gem_bitwait(sc, h, GEM_RX_CONFIG, 1, 0)) 699 printf("%s: cannot disable read dma\n", sc->sc_dev.dv_xname); 700 701 /* Finally, reset the ERX */ 702 bus_space_write_4(t, h2, GEM_RESET, GEM_RESET_RX); 703 bus_space_barrier(t, h, GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE); 704 /* Wait till it finishes */ 705 if (!gem_bitwait(sc, h2, GEM_RESET, GEM_RESET_RX, 0)) { 706 printf("%s: cannot reset receiver\n", sc->sc_dev.dv_xname); 707 return (1); 708 } 709 return (0); 710 } 711 712 713 /* 714 * Reset the receiver DMA engine. 715 * 716 * Intended to be used in case of GEM_INTR_RX_TAG_ERR, GEM_MAC_RX_OVERFLOW 717 * etc in order to reset the receiver DMA engine only and not do a full 718 * reset which amongst others also downs the link and clears the FIFOs. 719 */ 720 static void 721 gem_reset_rxdma(struct gem_softc *sc) 722 { 723 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 724 bus_space_tag_t t = sc->sc_bustag; 725 bus_space_handle_t h = sc->sc_h1; 726 int i; 727 728 if (gem_reset_rx(sc) != 0) { 729 gem_init(ifp); 730 return; 731 } 732 for (i = 0; i < GEM_NRXDESC; i++) 733 if (sc->sc_rxsoft[i].rxs_mbuf != NULL) 734 GEM_UPDATE_RXDESC(sc, i); 735 sc->sc_rxptr = 0; 736 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE); 737 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD); 738 739 /* Reprogram Descriptor Ring Base Addresses */ 740 /* NOTE: we use only 32-bit DMA addresses here. */ 741 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0); 742 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 743 744 /* Redo ERX Configuration */ 745 gem_rx_common(sc); 746 747 /* Give the reciever a swift kick */ 748 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC - 4); 749 } 750 751 /* 752 * Common RX configuration for gem_init() and gem_reset_rxdma(). 753 */ 754 static void 755 gem_rx_common(struct gem_softc *sc) 756 { 757 bus_space_tag_t t = sc->sc_bustag; 758 bus_space_handle_t h = sc->sc_h1; 759 u_int32_t v; 760 761 /* Encode Receive Descriptor ring size: four possible values */ 762 v = gem_ringsize(GEM_NRXDESC /*XXX*/); 763 764 /* Set receive h/w checksum offset */ 765 #ifdef INET 766 v |= (ETHER_HDR_LEN + sizeof(struct ip) + 767 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 768 ETHER_VLAN_ENCAP_LEN : 0)) << GEM_RX_CONFIG_CXM_START_SHFT; 769 #endif 770 771 /* Enable RX DMA */ 772 bus_space_write_4(t, h, GEM_RX_CONFIG, 773 v | (GEM_THRSH_1024 << GEM_RX_CONFIG_FIFO_THRS_SHIFT) | 774 (2 << GEM_RX_CONFIG_FBOFF_SHFT) | GEM_RX_CONFIG_RXDMA_EN); 775 776 /* 777 * The following value is for an OFF Threshold of about 3/4 full 778 * and an ON Threshold of 1/4 full. 779 */ 780 bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH, 781 (3 * sc->sc_rxfifosize / 256) | 782 ((sc->sc_rxfifosize / 256) << 12)); 783 bus_space_write_4(t, h, GEM_RX_BLANKING, 784 (6 << GEM_RX_BLANKING_TIME_SHIFT) | 6); 785 } 786 787 /* 788 * Reset the transmitter 789 */ 790 int 791 gem_reset_tx(struct gem_softc *sc) 792 { 793 bus_space_tag_t t = sc->sc_bustag; 794 bus_space_handle_t h = sc->sc_h1, h2 = sc->sc_h2; 795 796 /* 797 * Resetting while DMA is in progress can cause a bus hang, so we 798 * disable DMA first. 799 */ 800 gem_disable_tx(sc); 801 bus_space_write_4(t, h, GEM_TX_CONFIG, 0); 802 bus_space_barrier(t, h, GEM_TX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 803 /* Wait till it finishes */ 804 if (!gem_bitwait(sc, h, GEM_TX_CONFIG, 1, 0)) 805 printf("%s: cannot disable read dma\n", sc->sc_dev.dv_xname); 806 /* Wait 5ms extra. */ 807 delay(5000); 808 809 /* Finally, reset the ETX */ 810 bus_space_write_4(t, h2, GEM_RESET, GEM_RESET_TX); 811 bus_space_barrier(t, h, GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE); 812 /* Wait till it finishes */ 813 if (!gem_bitwait(sc, h2, GEM_RESET, GEM_RESET_TX, 0)) { 814 printf("%s: cannot reset receiver\n", 815 sc->sc_dev.dv_xname); 816 return (1); 817 } 818 return (0); 819 } 820 821 /* 822 * disable receiver. 823 */ 824 int 825 gem_disable_rx(struct gem_softc *sc) 826 { 827 bus_space_tag_t t = sc->sc_bustag; 828 bus_space_handle_t h = sc->sc_h1; 829 u_int32_t cfg; 830 831 /* Flip the enable bit */ 832 cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 833 cfg &= ~GEM_MAC_RX_ENABLE; 834 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg); 835 bus_space_barrier(t, h, GEM_MAC_RX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 836 /* Wait for it to finish */ 837 return (gem_bitwait(sc, h, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)); 838 } 839 840 /* 841 * disable transmitter. 842 */ 843 int 844 gem_disable_tx(struct gem_softc *sc) 845 { 846 bus_space_tag_t t = sc->sc_bustag; 847 bus_space_handle_t h = sc->sc_h1; 848 u_int32_t cfg; 849 850 /* Flip the enable bit */ 851 cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG); 852 cfg &= ~GEM_MAC_TX_ENABLE; 853 bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg); 854 bus_space_barrier(t, h, GEM_MAC_TX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 855 /* Wait for it to finish */ 856 return (gem_bitwait(sc, h, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)); 857 } 858 859 /* 860 * Initialize interface. 861 */ 862 int 863 gem_meminit(struct gem_softc *sc) 864 { 865 struct gem_rxsoft *rxs; 866 int i, error; 867 868 /* 869 * Initialize the transmit descriptor ring. 870 */ 871 memset((void *)sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 872 for (i = 0; i < GEM_NTXDESC; i++) { 873 sc->sc_txdescs[i].gd_flags = 0; 874 sc->sc_txdescs[i].gd_addr = 0; 875 } 876 GEM_CDTXSYNC(sc, 0, GEM_NTXDESC, 877 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 878 sc->sc_txfree = GEM_NTXDESC-1; 879 sc->sc_txnext = 0; 880 sc->sc_txwin = 0; 881 882 /* 883 * Initialize the receive descriptor and receive job 884 * descriptor rings. 885 */ 886 for (i = 0; i < GEM_NRXDESC; i++) { 887 rxs = &sc->sc_rxsoft[i]; 888 if (rxs->rxs_mbuf == NULL) { 889 if ((error = gem_add_rxbuf(sc, i)) != 0) { 890 printf("%s: unable to allocate or map rx " 891 "buffer %d, error = %d\n", 892 sc->sc_dev.dv_xname, i, error); 893 /* 894 * XXX Should attempt to run with fewer receive 895 * XXX buffers instead of just failing. 896 */ 897 gem_rxdrain(sc); 898 return (1); 899 } 900 } else 901 GEM_INIT_RXDESC(sc, i); 902 } 903 sc->sc_rxptr = 0; 904 sc->sc_meminited = 1; 905 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE); 906 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD); 907 908 return (0); 909 } 910 911 static int 912 gem_ringsize(int sz) 913 { 914 switch (sz) { 915 case 32: 916 return GEM_RING_SZ_32; 917 case 64: 918 return GEM_RING_SZ_64; 919 case 128: 920 return GEM_RING_SZ_128; 921 case 256: 922 return GEM_RING_SZ_256; 923 case 512: 924 return GEM_RING_SZ_512; 925 case 1024: 926 return GEM_RING_SZ_1024; 927 case 2048: 928 return GEM_RING_SZ_2048; 929 case 4096: 930 return GEM_RING_SZ_4096; 931 case 8192: 932 return GEM_RING_SZ_8192; 933 default: 934 printf("gem: invalid Receive Descriptor ring size %d\n", sz); 935 return GEM_RING_SZ_32; 936 } 937 } 938 939 940 /* 941 * Start PCS 942 */ 943 void 944 gem_pcs_start(struct gem_softc *sc) 945 { 946 bus_space_tag_t t = sc->sc_bustag; 947 bus_space_handle_t h = sc->sc_h1; 948 uint32_t v; 949 950 #ifdef GEM_DEBUG 951 aprint_debug("%s: gem_pcs_start()\n", sc->sc_dev.dv_xname); 952 #endif 953 954 /* 955 * Set up. We must disable the MII before modifying the 956 * GEM_MII_ANAR register 957 */ 958 if (sc->sc_flags & GEM_SERDES) { 959 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 960 GEM_MII_DATAPATH_SERDES); 961 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 962 GEM_MII_SLINK_LOOPBACK); 963 } else { 964 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 965 GEM_MII_DATAPATH_SERIAL); 966 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 0); 967 } 968 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 969 v = bus_space_read_4(t, h, GEM_MII_ANAR); 970 v |= (GEM_MII_ANEG_SYM_PAUSE | GEM_MII_ANEG_ASYM_PAUSE); 971 if (sc->sc_mii_media == IFM_AUTO) 972 v |= (GEM_MII_ANEG_FUL_DUPLX | GEM_MII_ANEG_HLF_DUPLX); 973 else if (sc->sc_mii_media == IFM_FDX) { 974 v |= GEM_MII_ANEG_FUL_DUPLX; 975 v &= ~GEM_MII_ANEG_HLF_DUPLX; 976 } else if (sc->sc_mii_media == IFM_HDX) { 977 v &= ~GEM_MII_ANEG_FUL_DUPLX; 978 v |= GEM_MII_ANEG_HLF_DUPLX; 979 } 980 981 /* Configure link. */ 982 bus_space_write_4(t, h, GEM_MII_ANAR, v); 983 bus_space_write_4(t, h, GEM_MII_CONTROL, 984 GEM_MII_CONTROL_AUTONEG | GEM_MII_CONTROL_RAN); 985 bus_space_write_4(t, h, GEM_MII_CONFIG, GEM_MII_CONFIG_ENABLE); 986 gem_bitwait(sc, h, GEM_MII_STATUS, 0, GEM_MII_STATUS_ANEG_CPT); 987 988 /* Start the 10 second timer */ 989 callout_reset(&sc->sc_tick_ch, hz * 10, gem_tick, sc); 990 } 991 992 /* 993 * Stop PCS 994 */ 995 void 996 gem_pcs_stop(struct gem_softc *sc, int disable) 997 { 998 bus_space_tag_t t = sc->sc_bustag; 999 bus_space_handle_t h = sc->sc_h1; 1000 1001 #ifdef GEM_DEBUG 1002 aprint_debug("%s: gem_pcs_stop()\n", sc->sc_dev.dv_xname); 1003 #endif 1004 1005 /* Tell link partner that we're going away */ 1006 bus_space_write_4(t, h, GEM_MII_ANAR, GEM_MII_ANEG_RF); 1007 1008 /* 1009 * Disable PCS MII. The documentation suggests that setting 1010 * GEM_MII_CONFIG_ENABLE to zero and then restarting auto- 1011 * negotiation will shut down the link. However, it appears 1012 * that we also need to unset the datapath mode. 1013 */ 1014 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 1015 bus_space_write_4(t, h, GEM_MII_CONTROL, 1016 GEM_MII_CONTROL_AUTONEG | GEM_MII_CONTROL_RAN); 1017 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, GEM_MII_DATAPATH_MII); 1018 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 1019 1020 if (disable) { 1021 if (sc->sc_flags & GEM_SERDES) 1022 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 1023 GEM_MII_SLINK_POWER_OFF); 1024 else 1025 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 1026 GEM_MII_SLINK_LOOPBACK | GEM_MII_SLINK_POWER_OFF); 1027 } 1028 1029 sc->sc_flags &= ~GEM_LINK; 1030 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_NONE; 1031 sc->sc_mii.mii_media_status = IFM_AVALID; 1032 } 1033 1034 1035 /* 1036 * Initialization of interface; set up initialization block 1037 * and transmit/receive descriptor rings. 1038 */ 1039 int 1040 gem_init(struct ifnet *ifp) 1041 { 1042 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 1043 bus_space_tag_t t = sc->sc_bustag; 1044 bus_space_handle_t h = sc->sc_h1; 1045 int rc = 0, s; 1046 u_int max_frame_size; 1047 u_int32_t v; 1048 1049 s = splnet(); 1050 1051 DPRINTF(sc, ("%s: gem_init: calling stop\n", sc->sc_dev.dv_xname)); 1052 /* 1053 * Initialization sequence. The numbered steps below correspond 1054 * to the sequence outlined in section 6.3.5.1 in the Ethernet 1055 * Channel Engine manual (part of the PCIO manual). 1056 * See also the STP2002-STQ document from Sun Microsystems. 1057 */ 1058 1059 /* step 1 & 2. Reset the Ethernet Channel */ 1060 gem_stop(ifp, 0); 1061 gem_reset(sc); 1062 DPRINTF(sc, ("%s: gem_init: restarting\n", sc->sc_dev.dv_xname)); 1063 1064 /* Re-initialize the MIF */ 1065 gem_mifinit(sc); 1066 1067 /* Set up correct datapath for non-SERDES/Serialink */ 1068 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0 && 1069 sc->sc_variant != GEM_SUN_ERI) 1070 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 1071 GEM_MII_DATAPATH_MII); 1072 1073 /* Call MI reset function if any */ 1074 if (sc->sc_hwreset) 1075 (*sc->sc_hwreset)(sc); 1076 1077 /* step 3. Setup data structures in host memory */ 1078 if (gem_meminit(sc) != 0) 1079 return 1; 1080 1081 /* step 4. TX MAC registers & counters */ 1082 gem_init_regs(sc); 1083 max_frame_size = max(sc->sc_ethercom.ec_if.if_mtu, ETHERMTU); 1084 max_frame_size += ETHER_HDR_LEN + ETHER_CRC_LEN; 1085 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1086 max_frame_size += ETHER_VLAN_ENCAP_LEN; 1087 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 1088 max_frame_size|/* burst size */(0x2000<<16)); 1089 1090 /* step 5. RX MAC registers & counters */ 1091 gem_setladrf(sc); 1092 1093 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 1094 /* NOTE: we use only 32-bit DMA addresses here. */ 1095 bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 0); 1096 bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 1097 1098 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0); 1099 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 1100 1101 /* step 8. Global Configuration & Interrupt Mask */ 1102 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 1103 v = GEM_INTR_PCS; 1104 else 1105 v = GEM_INTR_MIF; 1106 bus_space_write_4(t, h, GEM_INTMASK, 1107 ~(GEM_INTR_TX_INTME | 1108 GEM_INTR_TX_EMPTY | 1109 GEM_INTR_TX_MAC | 1110 GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF| 1111 GEM_INTR_RX_TAG_ERR | GEM_INTR_MAC_CONTROL| 1112 GEM_INTR_BERR | v)); 1113 bus_space_write_4(t, h, GEM_MAC_RX_MASK, 1114 GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT); 1115 bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXX */ 1116 bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 1117 GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME); 1118 1119 /* step 9. ETX Configuration: use mostly default values */ 1120 1121 /* Enable TX DMA */ 1122 v = gem_ringsize(GEM_NTXDESC /*XXX*/); 1123 bus_space_write_4(t, h, GEM_TX_CONFIG, 1124 v|GEM_TX_CONFIG_TXDMA_EN| 1125 ((0x4FF<<10)&GEM_TX_CONFIG_TXFIFO_TH)); 1126 bus_space_write_4(t, h, GEM_TX_KICK, sc->sc_txnext); 1127 1128 /* step 10. ERX Configuration */ 1129 gem_rx_common(sc); 1130 1131 /* step 11. Configure Media */ 1132 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0 && 1133 (rc = mii_ifmedia_change(&sc->sc_mii)) != 0) 1134 goto out; 1135 1136 /* step 12. RX_MAC Configuration Register */ 1137 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 1138 v |= GEM_MAC_RX_ENABLE | GEM_MAC_RX_STRIP_CRC; 1139 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 1140 1141 /* step 14. Issue Transmit Pending command */ 1142 1143 /* Call MI initialization function if any */ 1144 if (sc->sc_hwinit) 1145 (*sc->sc_hwinit)(sc); 1146 1147 1148 /* step 15. Give the reciever a swift kick */ 1149 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4); 1150 1151 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 1152 /* Configure PCS */ 1153 gem_pcs_start(sc); 1154 else 1155 /* Start the one second timer. */ 1156 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 1157 1158 sc->sc_flags &= ~GEM_LINK; 1159 ifp->if_flags |= IFF_RUNNING; 1160 ifp->if_flags &= ~IFF_OACTIVE; 1161 ifp->if_timer = 0; 1162 sc->sc_if_flags = ifp->if_flags; 1163 out: 1164 splx(s); 1165 1166 return (0); 1167 } 1168 1169 void 1170 gem_init_regs(struct gem_softc *sc) 1171 { 1172 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1173 bus_space_tag_t t = sc->sc_bustag; 1174 bus_space_handle_t h = sc->sc_h1; 1175 const u_char *laddr = CLLADDR(ifp->if_sadl); 1176 u_int32_t v; 1177 1178 /* These regs are not cleared on reset */ 1179 if (!sc->sc_inited) { 1180 1181 /* Load recommended values */ 1182 bus_space_write_4(t, h, GEM_MAC_IPG0, 0x00); 1183 bus_space_write_4(t, h, GEM_MAC_IPG1, 0x08); 1184 bus_space_write_4(t, h, GEM_MAC_IPG2, 0x04); 1185 1186 bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 1187 /* Max frame and max burst size */ 1188 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 1189 ETHER_MAX_LEN | (0x2000<<16)); 1190 1191 bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x07); 1192 bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x04); 1193 bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10); 1194 bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088); 1195 bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED, 1196 ((laddr[5]<<8)|laddr[4])&0x3ff); 1197 1198 /* Secondary MAC addr set to 0:0:0:0:0:0 */ 1199 bus_space_write_4(t, h, GEM_MAC_ADDR3, 0); 1200 bus_space_write_4(t, h, GEM_MAC_ADDR4, 0); 1201 bus_space_write_4(t, h, GEM_MAC_ADDR5, 0); 1202 1203 /* MAC control addr set to 01:80:c2:00:00:01 */ 1204 bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001); 1205 bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200); 1206 bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180); 1207 1208 /* MAC filter addr set to 0:0:0:0:0:0 */ 1209 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0); 1210 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0); 1211 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0); 1212 1213 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0); 1214 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0); 1215 1216 sc->sc_inited = 1; 1217 } 1218 1219 /* Counters need to be zeroed */ 1220 bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0); 1221 bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0); 1222 bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0); 1223 bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0); 1224 bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0); 1225 bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0); 1226 bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0); 1227 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 1228 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 1229 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 1230 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 1231 1232 /* Set XOFF PAUSE time. */ 1233 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); 1234 1235 /* 1236 * Set the internal arbitration to "infinite" bursts of the 1237 * maximum length of 31 * 64 bytes so DMA transfers aren't 1238 * split up in cache line size chunks. This greatly improves 1239 * especially RX performance. 1240 * Enable silicon bug workarounds for the Apple variants. 1241 */ 1242 bus_space_write_4(t, h, GEM_CONFIG, 1243 GEM_CONFIG_TXDMA_LIMIT | GEM_CONFIG_RXDMA_LIMIT | 1244 GEM_CONFIG_BURST_INF | (GEM_IS_APPLE(sc) ? 1245 GEM_CONFIG_RONPAULBIT | GEM_CONFIG_BUG2FIX : 0)); 1246 1247 /* 1248 * Set the station address. 1249 */ 1250 bus_space_write_4(t, h, GEM_MAC_ADDR0, (laddr[4]<<8)|laddr[5]); 1251 bus_space_write_4(t, h, GEM_MAC_ADDR1, (laddr[2]<<8)|laddr[3]); 1252 bus_space_write_4(t, h, GEM_MAC_ADDR2, (laddr[0]<<8)|laddr[1]); 1253 1254 /* 1255 * Enable MII outputs. Enable GMII if there is a gigabit PHY. 1256 */ 1257 sc->sc_mif_config = bus_space_read_4(t, h, GEM_MIF_CONFIG); 1258 v = GEM_MAC_XIF_TX_MII_ENA; 1259 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) { 1260 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) { 1261 v |= GEM_MAC_XIF_FDPLX_LED; 1262 if (sc->sc_flags & GEM_GIGABIT) 1263 v |= GEM_MAC_XIF_GMII_MODE; 1264 } 1265 } else { 1266 v |= GEM_MAC_XIF_GMII_MODE; 1267 } 1268 bus_space_write_4(t, h, GEM_MAC_XIF_CONFIG, v); 1269 } 1270 1271 #ifdef GEM_DEBUG 1272 static void 1273 gem_txsoft_print(const struct gem_softc *sc, int firstdesc, int lastdesc) 1274 { 1275 int i; 1276 1277 for (i = firstdesc;; i = GEM_NEXTTX(i)) { 1278 printf("descriptor %d:\t", i); 1279 printf("gd_flags: 0x%016" PRIx64 "\t", 1280 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags)); 1281 printf("gd_addr: 0x%016" PRIx64 "\n", 1282 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr)); 1283 if (i == lastdesc) 1284 break; 1285 } 1286 } 1287 #endif 1288 1289 static void 1290 gem_start(ifp) 1291 struct ifnet *ifp; 1292 { 1293 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 1294 struct mbuf *m0, *m; 1295 struct gem_txsoft *txs; 1296 bus_dmamap_t dmamap; 1297 int error, firsttx, nexttx = -1, lasttx = -1, ofree, seg; 1298 uint64_t flags = 0; 1299 1300 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1301 return; 1302 1303 /* 1304 * Remember the previous number of free descriptors and 1305 * the first descriptor we'll use. 1306 */ 1307 ofree = sc->sc_txfree; 1308 firsttx = sc->sc_txnext; 1309 1310 DPRINTF(sc, ("%s: gem_start: txfree %d, txnext %d\n", 1311 sc->sc_dev.dv_xname, ofree, firsttx)); 1312 1313 /* 1314 * Loop through the send queue, setting up transmit descriptors 1315 * until we drain the queue, or use up all available transmit 1316 * descriptors. 1317 */ 1318 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 1319 sc->sc_txfree != 0) { 1320 /* 1321 * Grab a packet off the queue. 1322 */ 1323 IFQ_POLL(&ifp->if_snd, m0); 1324 if (m0 == NULL) 1325 break; 1326 m = NULL; 1327 1328 dmamap = txs->txs_dmamap; 1329 1330 /* 1331 * Load the DMA map. If this fails, the packet either 1332 * didn't fit in the alloted number of segments, or we were 1333 * short on resources. In this case, we'll copy and try 1334 * again. 1335 */ 1336 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m0, 1337 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0 || 1338 (m0->m_pkthdr.len < ETHER_MIN_TX && 1339 dmamap->dm_nsegs == GEM_NTXSEGS)) { 1340 if (m0->m_pkthdr.len > MCLBYTES) { 1341 printf("%s: unable to allocate jumbo Tx " 1342 "cluster\n", sc->sc_dev.dv_xname); 1343 IFQ_DEQUEUE(&ifp->if_snd, m0); 1344 m_freem(m0); 1345 continue; 1346 } 1347 MGETHDR(m, M_DONTWAIT, MT_DATA); 1348 if (m == NULL) { 1349 printf("%s: unable to allocate Tx mbuf\n", 1350 sc->sc_dev.dv_xname); 1351 break; 1352 } 1353 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1354 if (m0->m_pkthdr.len > MHLEN) { 1355 MCLGET(m, M_DONTWAIT); 1356 if ((m->m_flags & M_EXT) == 0) { 1357 printf("%s: unable to allocate Tx " 1358 "cluster\n", sc->sc_dev.dv_xname); 1359 m_freem(m); 1360 break; 1361 } 1362 } 1363 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1364 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1365 error = bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, 1366 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1367 if (error) { 1368 printf("%s: unable to load Tx buffer, " 1369 "error = %d\n", sc->sc_dev.dv_xname, error); 1370 break; 1371 } 1372 } 1373 1374 /* 1375 * Ensure we have enough descriptors free to describe 1376 * the packet. 1377 */ 1378 if (dmamap->dm_nsegs > ((m0->m_pkthdr.len < ETHER_MIN_TX) ? 1379 (sc->sc_txfree - 1) : sc->sc_txfree)) { 1380 /* 1381 * Not enough free descriptors to transmit this 1382 * packet. We haven't committed to anything yet, 1383 * so just unload the DMA map, put the packet 1384 * back on the queue, and punt. Notify the upper 1385 * layer that there are no more slots left. 1386 * 1387 * XXX We could allocate an mbuf and copy, but 1388 * XXX it is worth it? 1389 */ 1390 ifp->if_flags |= IFF_OACTIVE; 1391 sc->sc_if_flags = ifp->if_flags; 1392 bus_dmamap_unload(sc->sc_dmatag, dmamap); 1393 if (m != NULL) 1394 m_freem(m); 1395 break; 1396 } 1397 1398 IFQ_DEQUEUE(&ifp->if_snd, m0); 1399 if (m != NULL) { 1400 m_freem(m0); 1401 m0 = m; 1402 } 1403 1404 /* 1405 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1406 */ 1407 1408 /* Sync the DMA map. */ 1409 bus_dmamap_sync(sc->sc_dmatag, dmamap, 0, dmamap->dm_mapsize, 1410 BUS_DMASYNC_PREWRITE); 1411 1412 /* 1413 * Initialize the transmit descriptors. 1414 */ 1415 for (nexttx = sc->sc_txnext, seg = 0; 1416 seg < dmamap->dm_nsegs; 1417 seg++, nexttx = GEM_NEXTTX(nexttx)) { 1418 1419 /* 1420 * If this is the first descriptor we're 1421 * enqueueing, set the start of packet flag, 1422 * and the checksum stuff if we want the hardware 1423 * to do it. 1424 */ 1425 sc->sc_txdescs[nexttx].gd_addr = 1426 GEM_DMA_WRITE(sc, dmamap->dm_segs[seg].ds_addr); 1427 flags = dmamap->dm_segs[seg].ds_len & GEM_TD_BUFSIZE; 1428 if (nexttx == firsttx) { 1429 flags |= GEM_TD_START_OF_PACKET; 1430 if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) { 1431 sc->sc_txwin = 0; 1432 flags |= GEM_TD_INTERRUPT_ME; 1433 } 1434 1435 #ifdef INET 1436 /* h/w checksum */ 1437 if (ifp->if_csum_flags_tx & M_CSUM_TCPv4 && 1438 m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1439 struct ether_header *eh; 1440 uint16_t offset, start; 1441 1442 eh = mtod(m0, struct ether_header *); 1443 switch (ntohs(eh->ether_type)) { 1444 case ETHERTYPE_IP: 1445 start = ETHER_HDR_LEN; 1446 break; 1447 case ETHERTYPE_VLAN: 1448 start = ETHER_HDR_LEN + 1449 ETHER_VLAN_ENCAP_LEN; 1450 break; 1451 default: 1452 /* unsupported, drop it */ 1453 m_free(m0); 1454 continue; 1455 } 1456 start += M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 1457 offset = M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data) + start; 1458 flags |= (start << 1459 GEM_TD_CXSUM_STARTSHFT) | 1460 (offset << 1461 GEM_TD_CXSUM_STUFFSHFT) | 1462 GEM_TD_CXSUM_ENABLE; 1463 } 1464 #endif 1465 } 1466 if (seg == dmamap->dm_nsegs - 1) { 1467 flags |= GEM_TD_END_OF_PACKET; 1468 } else { 1469 /* last flag set outside of loop */ 1470 sc->sc_txdescs[nexttx].gd_flags = 1471 GEM_DMA_WRITE(sc, flags); 1472 } 1473 lasttx = nexttx; 1474 } 1475 if (m0->m_pkthdr.len < ETHER_MIN_TX) { 1476 /* add padding buffer at end of chain */ 1477 flags &= ~GEM_TD_END_OF_PACKET; 1478 sc->sc_txdescs[lasttx].gd_flags = 1479 GEM_DMA_WRITE(sc, flags); 1480 1481 sc->sc_txdescs[nexttx].gd_addr = 1482 GEM_DMA_WRITE(sc, 1483 sc->sc_nulldmamap->dm_segs[0].ds_addr); 1484 flags = ((ETHER_MIN_TX - m0->m_pkthdr.len) & 1485 GEM_TD_BUFSIZE) | GEM_TD_END_OF_PACKET; 1486 lasttx = nexttx; 1487 nexttx = GEM_NEXTTX(nexttx); 1488 seg++; 1489 } 1490 sc->sc_txdescs[lasttx].gd_flags = GEM_DMA_WRITE(sc, flags); 1491 1492 KASSERT(lasttx != -1); 1493 1494 /* 1495 * Store a pointer to the packet so we can free it later, 1496 * and remember what txdirty will be once the packet is 1497 * done. 1498 */ 1499 txs->txs_mbuf = m0; 1500 txs->txs_firstdesc = sc->sc_txnext; 1501 txs->txs_lastdesc = lasttx; 1502 txs->txs_ndescs = seg; 1503 1504 #ifdef GEM_DEBUG 1505 if (ifp->if_flags & IFF_DEBUG) { 1506 printf(" gem_start %p transmit chain:\n", txs); 1507 gem_txsoft_print(sc, txs->txs_firstdesc, 1508 txs->txs_lastdesc); 1509 } 1510 #endif 1511 1512 /* Sync the descriptors we're using. */ 1513 GEM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndescs, 1514 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1515 1516 /* Advance the tx pointer. */ 1517 sc->sc_txfree -= txs->txs_ndescs; 1518 sc->sc_txnext = nexttx; 1519 1520 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1521 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1522 1523 #if NBPFILTER > 0 1524 /* 1525 * Pass the packet to any BPF listeners. 1526 */ 1527 if (ifp->if_bpf) 1528 bpf_mtap(ifp->if_bpf, m0); 1529 #endif /* NBPFILTER > 0 */ 1530 } 1531 1532 if (txs == NULL || sc->sc_txfree == 0) { 1533 /* No more slots left; notify upper layer. */ 1534 ifp->if_flags |= IFF_OACTIVE; 1535 sc->sc_if_flags = ifp->if_flags; 1536 } 1537 1538 if (sc->sc_txfree != ofree) { 1539 DPRINTF(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 1540 sc->sc_dev.dv_xname, lasttx, firsttx)); 1541 /* 1542 * The entire packet chain is set up. 1543 * Kick the transmitter. 1544 */ 1545 DPRINTF(sc, ("%s: gem_start: kicking tx %d\n", 1546 sc->sc_dev.dv_xname, nexttx)); 1547 bus_space_write_4(sc->sc_bustag, sc->sc_h1, GEM_TX_KICK, 1548 sc->sc_txnext); 1549 1550 /* Set a watchdog timer in case the chip flakes out. */ 1551 ifp->if_timer = 5; 1552 DPRINTF(sc, ("%s: gem_start: watchdog %d\n", 1553 sc->sc_dev.dv_xname, ifp->if_timer)); 1554 } 1555 } 1556 1557 /* 1558 * Transmit interrupt. 1559 */ 1560 int 1561 gem_tint(sc) 1562 struct gem_softc *sc; 1563 { 1564 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1565 bus_space_tag_t t = sc->sc_bustag; 1566 bus_space_handle_t mac = sc->sc_h1; 1567 struct gem_txsoft *txs; 1568 int txlast; 1569 int progress = 0; 1570 u_int32_t v; 1571 1572 DPRINTF(sc, ("%s: gem_tint\n", sc->sc_dev.dv_xname)); 1573 1574 /* Unload collision counters ... */ 1575 v = bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) + 1576 bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT); 1577 ifp->if_collisions += v + 1578 bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) + 1579 bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT); 1580 ifp->if_oerrors += v; 1581 1582 /* ... then clear the hardware counters. */ 1583 bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0); 1584 bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0); 1585 bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0); 1586 bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0); 1587 1588 /* 1589 * Go through our Tx list and free mbufs for those 1590 * frames that have been transmitted. 1591 */ 1592 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1593 /* 1594 * In theory, we could harvest some descriptors before 1595 * the ring is empty, but that's a bit complicated. 1596 * 1597 * GEM_TX_COMPLETION points to the last descriptor 1598 * processed +1. 1599 * 1600 * Let's assume that the NIC writes back to the Tx 1601 * descriptors before it updates the completion 1602 * register. If the NIC has posted writes to the 1603 * Tx descriptors, PCI ordering requires that the 1604 * posted writes flush to RAM before the register-read 1605 * finishes. So let's read the completion register, 1606 * before syncing the descriptors, so that we 1607 * examine Tx descriptors that are at least as 1608 * current as the completion register. 1609 */ 1610 txlast = bus_space_read_4(t, mac, GEM_TX_COMPLETION); 1611 DPRINTF(sc, 1612 ("gem_tint: txs->txs_lastdesc = %d, txlast = %d\n", 1613 txs->txs_lastdesc, txlast)); 1614 if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1615 if (txlast >= txs->txs_firstdesc && 1616 txlast <= txs->txs_lastdesc) 1617 break; 1618 } else if (txlast >= txs->txs_firstdesc || 1619 txlast <= txs->txs_lastdesc) 1620 break; 1621 1622 GEM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndescs, 1623 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1624 1625 #ifdef GEM_DEBUG /* XXX DMA synchronization? */ 1626 if (ifp->if_flags & IFF_DEBUG) { 1627 printf(" txsoft %p transmit chain:\n", txs); 1628 gem_txsoft_print(sc, txs->txs_firstdesc, 1629 txs->txs_lastdesc); 1630 } 1631 #endif 1632 1633 1634 DPRINTF(sc, ("gem_tint: releasing a desc\n")); 1635 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1636 1637 sc->sc_txfree += txs->txs_ndescs; 1638 1639 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 1640 0, txs->txs_dmamap->dm_mapsize, 1641 BUS_DMASYNC_POSTWRITE); 1642 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 1643 if (txs->txs_mbuf != NULL) { 1644 m_freem(txs->txs_mbuf); 1645 txs->txs_mbuf = NULL; 1646 } 1647 1648 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1649 1650 ifp->if_opackets++; 1651 progress = 1; 1652 } 1653 1654 #if 0 1655 DPRINTF(sc, ("gem_tint: GEM_TX_STATE_MACHINE %x " 1656 "GEM_TX_DATA_PTR %" PRIx64 "GEM_TX_COMPLETION %" PRIx32 "\n", 1657 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_TX_STATE_MACHINE), 1658 ((uint64_t)bus_space_read_4(sc->sc_bustag, sc->sc_h1, 1659 GEM_TX_DATA_PTR_HI) << 32) | 1660 bus_space_read_4(sc->sc_bustag, sc->sc_h1, 1661 GEM_TX_DATA_PTR_LO), 1662 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_TX_COMPLETION))); 1663 #endif 1664 1665 if (progress) { 1666 if (sc->sc_txfree == GEM_NTXDESC - 1) 1667 sc->sc_txwin = 0; 1668 1669 /* Freed some descriptors, so reset IFF_OACTIVE and restart. */ 1670 ifp->if_flags &= ~IFF_OACTIVE; 1671 sc->sc_if_flags = ifp->if_flags; 1672 ifp->if_timer = SIMPLEQ_EMPTY(&sc->sc_txdirtyq) ? 0 : 5; 1673 gem_start(ifp); 1674 } 1675 DPRINTF(sc, ("%s: gem_tint: watchdog %d\n", 1676 sc->sc_dev.dv_xname, ifp->if_timer)); 1677 1678 return (1); 1679 } 1680 1681 /* 1682 * Receive interrupt. 1683 */ 1684 int 1685 gem_rint(sc) 1686 struct gem_softc *sc; 1687 { 1688 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1689 bus_space_tag_t t = sc->sc_bustag; 1690 bus_space_handle_t h = sc->sc_h1; 1691 struct gem_rxsoft *rxs; 1692 struct mbuf *m; 1693 u_int64_t rxstat; 1694 u_int32_t rxcomp; 1695 int i, len, progress = 0; 1696 1697 DPRINTF(sc, ("%s: gem_rint\n", sc->sc_dev.dv_xname)); 1698 1699 /* 1700 * Ignore spurious interrupt that sometimes occurs before 1701 * we are set up when we network boot. 1702 */ 1703 if (!sc->sc_meminited) 1704 return 1; 1705 1706 /* 1707 * Read the completion register once. This limits 1708 * how long the following loop can execute. 1709 */ 1710 rxcomp = bus_space_read_4(t, h, GEM_RX_COMPLETION); 1711 1712 /* 1713 * XXX Read the lastrx only once at the top for speed. 1714 */ 1715 DPRINTF(sc, ("gem_rint: sc->rxptr %d, complete %d\n", 1716 sc->sc_rxptr, rxcomp)); 1717 1718 /* 1719 * Go into the loop at least once. 1720 */ 1721 for (i = sc->sc_rxptr; i == sc->sc_rxptr || i != rxcomp; 1722 i = GEM_NEXTRX(i)) { 1723 rxs = &sc->sc_rxsoft[i]; 1724 1725 GEM_CDRXSYNC(sc, i, 1726 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1727 1728 rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags); 1729 1730 if (rxstat & GEM_RD_OWN) { 1731 GEM_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); 1732 /* 1733 * We have processed all of the receive buffers. 1734 */ 1735 break; 1736 } 1737 1738 progress++; 1739 ifp->if_ipackets++; 1740 1741 if (rxstat & GEM_RD_BAD_CRC) { 1742 ifp->if_ierrors++; 1743 printf("%s: receive error: CRC error\n", 1744 sc->sc_dev.dv_xname); 1745 GEM_INIT_RXDESC(sc, i); 1746 continue; 1747 } 1748 1749 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1750 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1751 #ifdef GEM_DEBUG 1752 if (ifp->if_flags & IFF_DEBUG) { 1753 printf(" rxsoft %p descriptor %d: ", rxs, i); 1754 printf("gd_flags: 0x%016llx\t", (long long) 1755 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags)); 1756 printf("gd_addr: 0x%016llx\n", (long long) 1757 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr)); 1758 } 1759 #endif 1760 1761 /* No errors; receive the packet. */ 1762 len = GEM_RD_BUFLEN(rxstat); 1763 1764 /* 1765 * Allocate a new mbuf cluster. If that fails, we are 1766 * out of memory, and must drop the packet and recycle 1767 * the buffer that's already attached to this descriptor. 1768 */ 1769 m = rxs->rxs_mbuf; 1770 if (gem_add_rxbuf(sc, i) != 0) { 1771 GEM_COUNTER_INCR(sc, sc_ev_rxnobuf); 1772 ifp->if_ierrors++; 1773 GEM_INIT_RXDESC(sc, i); 1774 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1775 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1776 continue; 1777 } 1778 m->m_data += 2; /* We're already off by two */ 1779 1780 m->m_pkthdr.rcvif = ifp; 1781 m->m_pkthdr.len = m->m_len = len; 1782 1783 #if NBPFILTER > 0 1784 /* 1785 * Pass this up to any BPF listeners, but only 1786 * pass it up the stack if it's for us. 1787 */ 1788 if (ifp->if_bpf) 1789 bpf_mtap(ifp->if_bpf, m); 1790 #endif /* NBPFILTER > 0 */ 1791 1792 #ifdef INET 1793 /* hardware checksum */ 1794 if (ifp->if_csum_flags_rx & M_CSUM_TCPv4) { 1795 struct ether_header *eh; 1796 struct ip *ip; 1797 int32_t hlen, pktlen; 1798 1799 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1800 pktlen = m->m_pkthdr.len - ETHER_HDR_LEN - 1801 ETHER_VLAN_ENCAP_LEN; 1802 eh = (struct ether_header *) (mtod(m, char *) + 1803 ETHER_VLAN_ENCAP_LEN); 1804 } else { 1805 pktlen = m->m_pkthdr.len - ETHER_HDR_LEN; 1806 eh = mtod(m, struct ether_header *); 1807 } 1808 if (ntohs(eh->ether_type) != ETHERTYPE_IP) 1809 goto swcsum; 1810 ip = (struct ip *) ((char *)eh + ETHER_HDR_LEN); 1811 1812 /* IPv4 only */ 1813 if (ip->ip_v != IPVERSION) 1814 goto swcsum; 1815 1816 hlen = ip->ip_hl << 2; 1817 if (hlen < sizeof(struct ip)) 1818 goto swcsum; 1819 1820 /* 1821 * bail if too short, has random trailing garbage, 1822 * truncated, fragment, or has ethernet pad. 1823 */ 1824 if ((ntohs(ip->ip_len) < hlen) || 1825 (ntohs(ip->ip_len) != pktlen) || 1826 (ntohs(ip->ip_off) & (IP_MF | IP_OFFMASK))) 1827 goto swcsum; 1828 1829 switch (ip->ip_p) { 1830 case IPPROTO_TCP: 1831 if (! (ifp->if_csum_flags_rx & M_CSUM_TCPv4)) 1832 goto swcsum; 1833 if (pktlen < (hlen + sizeof(struct tcphdr))) 1834 goto swcsum; 1835 m->m_pkthdr.csum_flags = M_CSUM_TCPv4; 1836 break; 1837 case IPPROTO_UDP: 1838 /* FALLTHROUGH */ 1839 default: 1840 goto swcsum; 1841 } 1842 1843 /* the uncomplemented sum is expected */ 1844 m->m_pkthdr.csum_data = (~rxstat) & GEM_RD_CHECKSUM; 1845 1846 /* if the pkt had ip options, we have to deduct them */ 1847 if (hlen > sizeof(struct ip)) { 1848 uint16_t *opts; 1849 uint32_t optsum, temp; 1850 1851 optsum = 0; 1852 temp = hlen - sizeof(struct ip); 1853 opts = (uint16_t *) ((char *) ip + 1854 sizeof(struct ip)); 1855 1856 while (temp > 1) { 1857 optsum += ntohs(*opts++); 1858 temp -= 2; 1859 } 1860 while (optsum >> 16) 1861 optsum = (optsum >> 16) + 1862 (optsum & 0xffff); 1863 1864 /* Deduct ip opts sum from hwsum (rfc 1624). */ 1865 m->m_pkthdr.csum_data = 1866 ~((~m->m_pkthdr.csum_data) - ~optsum); 1867 1868 while (m->m_pkthdr.csum_data >> 16) 1869 m->m_pkthdr.csum_data = 1870 (m->m_pkthdr.csum_data >> 16) + 1871 (m->m_pkthdr.csum_data & 1872 0xffff); 1873 } 1874 1875 m->m_pkthdr.csum_flags |= M_CSUM_DATA | 1876 M_CSUM_NO_PSEUDOHDR; 1877 } else 1878 swcsum: 1879 m->m_pkthdr.csum_flags = 0; 1880 #endif 1881 /* Pass it on. */ 1882 (*ifp->if_input)(ifp, m); 1883 } 1884 1885 if (progress) { 1886 /* Update the receive pointer. */ 1887 if (i == sc->sc_rxptr) { 1888 GEM_COUNTER_INCR(sc, sc_ev_rxfull); 1889 #ifdef GEM_DEBUG 1890 if (ifp->if_flags & IFF_DEBUG) 1891 printf("%s: rint: ring wrap\n", 1892 sc->sc_dev.dv_xname); 1893 #endif 1894 } 1895 sc->sc_rxptr = i; 1896 bus_space_write_4(t, h, GEM_RX_KICK, GEM_PREVRX(i)); 1897 } 1898 #ifdef GEM_COUNTERS 1899 if (progress <= 4) { 1900 GEM_COUNTER_INCR(sc, sc_ev_rxhist[progress]); 1901 } else if (progress < 32) { 1902 if (progress < 16) 1903 GEM_COUNTER_INCR(sc, sc_ev_rxhist[5]); 1904 else 1905 GEM_COUNTER_INCR(sc, sc_ev_rxhist[6]); 1906 1907 } else { 1908 if (progress < 64) 1909 GEM_COUNTER_INCR(sc, sc_ev_rxhist[7]); 1910 else 1911 GEM_COUNTER_INCR(sc, sc_ev_rxhist[8]); 1912 } 1913 #endif 1914 1915 DPRINTF(sc, ("gem_rint: done sc->rxptr %d, complete %d\n", 1916 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION))); 1917 1918 /* Read error counters ... */ 1919 ifp->if_ierrors += 1920 bus_space_read_4(t, h, GEM_MAC_RX_LEN_ERR_CNT) + 1921 bus_space_read_4(t, h, GEM_MAC_RX_ALIGN_ERR) + 1922 bus_space_read_4(t, h, GEM_MAC_RX_CRC_ERR_CNT) + 1923 bus_space_read_4(t, h, GEM_MAC_RX_CODE_VIOL); 1924 1925 /* ... then clear the hardware counters. */ 1926 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 1927 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 1928 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 1929 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 1930 1931 return (1); 1932 } 1933 1934 1935 /* 1936 * gem_add_rxbuf: 1937 * 1938 * Add a receive buffer to the indicated descriptor. 1939 */ 1940 int 1941 gem_add_rxbuf(struct gem_softc *sc, int idx) 1942 { 1943 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1944 struct mbuf *m; 1945 int error; 1946 1947 MGETHDR(m, M_DONTWAIT, MT_DATA); 1948 if (m == NULL) 1949 return (ENOBUFS); 1950 1951 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1952 MCLGET(m, M_DONTWAIT); 1953 if ((m->m_flags & M_EXT) == 0) { 1954 m_freem(m); 1955 return (ENOBUFS); 1956 } 1957 1958 #ifdef GEM_DEBUG 1959 /* bzero the packet to check DMA */ 1960 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 1961 #endif 1962 1963 if (rxs->rxs_mbuf != NULL) 1964 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 1965 1966 rxs->rxs_mbuf = m; 1967 1968 error = bus_dmamap_load(sc->sc_dmatag, rxs->rxs_dmamap, 1969 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1970 BUS_DMA_READ|BUS_DMA_NOWAIT); 1971 if (error) { 1972 printf("%s: can't load rx DMA map %d, error = %d\n", 1973 sc->sc_dev.dv_xname, idx, error); 1974 panic("gem_add_rxbuf"); /* XXX */ 1975 } 1976 1977 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1978 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1979 1980 GEM_INIT_RXDESC(sc, idx); 1981 1982 return (0); 1983 } 1984 1985 1986 int 1987 gem_eint(struct gem_softc *sc, u_int status) 1988 { 1989 char bits[128]; 1990 u_int32_t v; 1991 1992 if ((status & GEM_INTR_MIF) != 0) { 1993 printf("%s: XXXlink status changed\n", sc->sc_dev.dv_xname); 1994 return (1); 1995 } 1996 1997 if ((status & GEM_INTR_RX_TAG_ERR) != 0) { 1998 gem_reset_rxdma(sc); 1999 return (1); 2000 } 2001 2002 if (status & GEM_INTR_BERR) { 2003 bus_space_read_4(sc->sc_bustag, sc->sc_h2, GEM_ERROR_STATUS); 2004 v = bus_space_read_4(sc->sc_bustag, sc->sc_h2, 2005 GEM_ERROR_STATUS); 2006 printf("%s: bus error interrupt: 0x%02x\n", 2007 sc->sc_dev.dv_xname, v); 2008 return (1); 2009 } 2010 2011 printf("%s: status=%s\n", sc->sc_dev.dv_xname, 2012 bitmask_snprintf(status, GEM_INTR_BITS, bits, sizeof(bits))); 2013 return (1); 2014 } 2015 2016 2017 /* 2018 * PCS interrupts. 2019 * We should receive these when the link status changes, but sometimes 2020 * we don't receive them for link up. We compensate for this in the 2021 * gem_tick() callout. 2022 */ 2023 int 2024 gem_pint(struct gem_softc *sc) 2025 { 2026 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2027 bus_space_tag_t t = sc->sc_bustag; 2028 bus_space_handle_t h = sc->sc_h1; 2029 u_int32_t v, v2; 2030 2031 /* 2032 * Clear the PCS interrupt from GEM_STATUS. The PCS register is 2033 * latched, so we have to read it twice. There is only one bit in 2034 * use, so the value is meaningless. 2035 */ 2036 bus_space_read_4(t, h, GEM_MII_INTERRUP_STATUS); 2037 bus_space_read_4(t, h, GEM_MII_INTERRUP_STATUS); 2038 2039 if ((ifp->if_flags & IFF_UP) == 0) 2040 return 1; 2041 2042 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) 2043 return 1; 2044 2045 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2046 /* If we see remote fault, our link partner is probably going away */ 2047 if ((v & GEM_MII_STATUS_REM_FLT) != 0) { 2048 gem_bitwait(sc, h, GEM_MII_STATUS, GEM_MII_STATUS_REM_FLT, 0); 2049 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2050 /* Otherwise, we may need to wait after auto-negotiation completes */ 2051 } else if ((v & (GEM_MII_STATUS_LINK_STS | GEM_MII_STATUS_ANEG_CPT)) == 2052 GEM_MII_STATUS_ANEG_CPT) { 2053 gem_bitwait(sc, h, GEM_MII_STATUS, 0, GEM_MII_STATUS_LINK_STS); 2054 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2055 } 2056 if ((v & GEM_MII_STATUS_LINK_STS) != 0) { 2057 if (sc->sc_flags & GEM_LINK) { 2058 return 1; 2059 } 2060 callout_stop(&sc->sc_tick_ch); 2061 v = bus_space_read_4(t, h, GEM_MII_ANAR); 2062 v2 = bus_space_read_4(t, h, GEM_MII_ANLPAR); 2063 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_1000_SX; 2064 sc->sc_mii.mii_media_status = IFM_AVALID | IFM_ACTIVE; 2065 v &= v2; 2066 if (v & GEM_MII_ANEG_FUL_DUPLX) { 2067 sc->sc_mii.mii_media_active |= IFM_FDX; 2068 #ifdef GEM_DEBUG 2069 aprint_debug("%s: link up: full duplex\n", 2070 sc->sc_dev.dv_xname); 2071 #endif 2072 } else if (v & GEM_MII_ANEG_HLF_DUPLX) { 2073 sc->sc_mii.mii_media_active |= IFM_HDX; 2074 #ifdef GEM_DEBUG 2075 aprint_debug("%s: link up: half duplex\n", 2076 sc->sc_dev.dv_xname); 2077 #endif 2078 } else { 2079 #ifdef GEM_DEBUG 2080 aprint_debug("%s: duplex mismatch\n", 2081 sc->sc_dev.dv_xname); 2082 #endif 2083 } 2084 gem_statuschange(sc); 2085 } else { 2086 if ((sc->sc_flags & GEM_LINK) == 0) { 2087 return 1; 2088 } 2089 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_NONE; 2090 sc->sc_mii.mii_media_status = IFM_AVALID; 2091 #ifdef GEM_DEBUG 2092 aprint_debug("%s: link down\n", 2093 sc->sc_dev.dv_xname); 2094 #endif 2095 gem_statuschange(sc); 2096 2097 /* Start the 10 second timer */ 2098 callout_reset(&sc->sc_tick_ch, hz * 10, gem_tick, sc); 2099 } 2100 return 1; 2101 } 2102 2103 2104 2105 int 2106 gem_intr(v) 2107 void *v; 2108 { 2109 struct gem_softc *sc = (struct gem_softc *)v; 2110 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2111 bus_space_tag_t t = sc->sc_bustag; 2112 bus_space_handle_t h = sc->sc_h1; 2113 u_int32_t status; 2114 int r = 0; 2115 #ifdef GEM_DEBUG 2116 char bits[128]; 2117 #endif 2118 2119 /* XXX We should probably mask out interrupts until we're done */ 2120 2121 sc->sc_ev_intr.ev_count++; 2122 2123 status = bus_space_read_4(t, h, GEM_STATUS); 2124 DPRINTF(sc, ("%s: gem_intr: cplt 0x%x status %s\n", 2125 sc->sc_dev.dv_xname, (status >> 19), 2126 bitmask_snprintf(status, GEM_INTR_BITS, bits, sizeof(bits)))); 2127 2128 if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0) 2129 r |= gem_eint(sc, status); 2130 2131 /* We don't bother with GEM_INTR_TX_DONE */ 2132 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) { 2133 GEM_COUNTER_INCR(sc, sc_ev_txint); 2134 r |= gem_tint(sc); 2135 } 2136 2137 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) { 2138 GEM_COUNTER_INCR(sc, sc_ev_rxint); 2139 r |= gem_rint(sc); 2140 } 2141 2142 /* We should eventually do more than just print out error stats. */ 2143 if (status & GEM_INTR_TX_MAC) { 2144 int txstat = bus_space_read_4(t, h, GEM_MAC_TX_STATUS); 2145 if (txstat & ~GEM_MAC_TX_XMIT_DONE) 2146 printf("%s: MAC tx fault, status %x\n", 2147 sc->sc_dev.dv_xname, txstat); 2148 if (txstat & (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG)) 2149 gem_init(ifp); 2150 } 2151 if (status & GEM_INTR_RX_MAC) { 2152 int rxstat = bus_space_read_4(t, h, GEM_MAC_RX_STATUS); 2153 /* 2154 * At least with GEM_SUN_GEM and some GEM_SUN_ERI 2155 * revisions GEM_MAC_RX_OVERFLOW happen often due to a 2156 * silicon bug so handle them silently. Moreover, it's 2157 * likely that the receiver has hung so we reset it. 2158 */ 2159 if (rxstat & GEM_MAC_RX_OVERFLOW) { 2160 ifp->if_ierrors++; 2161 gem_reset_rxdma(sc); 2162 } else if (rxstat & ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT)) 2163 printf("%s: MAC rx fault, status 0x%02x\n", 2164 sc->sc_dev.dv_xname, rxstat); 2165 } 2166 if (status & GEM_INTR_PCS) { 2167 r |= gem_pint(sc); 2168 } 2169 2170 /* Do we need to do anything with these? 2171 if ((status & GEM_MAC_CONTROL_STATUS) != 0) { 2172 status2 = bus_read_4(sc->sc_res[0], GEM_MAC_CONTROL_STATUS); 2173 if ((status2 & GEM_MAC_PAUSED) != 0) 2174 aprintf_debug("%s: PAUSE received (%d slots)\n", 2175 GEM_MAC_PAUSE_TIME(status2), sc->sc_dev.dv_xname); 2176 if ((status2 & GEM_MAC_PAUSE) != 0) 2177 aprintf_debug("%s: transited to PAUSE state\n", 2178 sc->sc_dev.dv_xname); 2179 if ((status2 & GEM_MAC_RESUME) != 0) 2180 aprintf_debug("%s: transited to non-PAUSE state\n", 2181 sc->sc_dev.dv_xname); 2182 } 2183 if ((status & GEM_INTR_MIF) != 0) 2184 aprintf_debug("%s: MIF interrupt\n", sc->sc_dev.dv_xname); 2185 */ 2186 #if NRND > 0 2187 rnd_add_uint32(&sc->rnd_source, status); 2188 #endif 2189 return (r); 2190 } 2191 2192 2193 void 2194 gem_watchdog(ifp) 2195 struct ifnet *ifp; 2196 { 2197 struct gem_softc *sc = ifp->if_softc; 2198 2199 DPRINTF(sc, ("gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x " 2200 "GEM_MAC_RX_CONFIG %x\n", 2201 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_RX_CONFIG), 2202 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_MAC_RX_STATUS), 2203 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_MAC_RX_CONFIG))); 2204 2205 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 2206 ++ifp->if_oerrors; 2207 2208 /* Try to get more packets going. */ 2209 gem_start(ifp); 2210 } 2211 2212 /* 2213 * Initialize the MII Management Interface 2214 */ 2215 void 2216 gem_mifinit(sc) 2217 struct gem_softc *sc; 2218 { 2219 bus_space_tag_t t = sc->sc_bustag; 2220 bus_space_handle_t mif = sc->sc_h1; 2221 2222 /* Configure the MIF in frame mode */ 2223 sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 2224 sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA; 2225 bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config); 2226 } 2227 2228 /* 2229 * MII interface 2230 * 2231 * The GEM MII interface supports at least three different operating modes: 2232 * 2233 * Bitbang mode is implemented using data, clock and output enable registers. 2234 * 2235 * Frame mode is implemented by loading a complete frame into the frame 2236 * register and polling the valid bit for completion. 2237 * 2238 * Polling mode uses the frame register but completion is indicated by 2239 * an interrupt. 2240 * 2241 */ 2242 static int 2243 gem_mii_readreg(self, phy, reg) 2244 struct device *self; 2245 int phy, reg; 2246 { 2247 struct gem_softc *sc = (void *)self; 2248 bus_space_tag_t t = sc->sc_bustag; 2249 bus_space_handle_t mif = sc->sc_h1; 2250 int n; 2251 u_int32_t v; 2252 2253 #ifdef GEM_DEBUG1 2254 if (sc->sc_debug) 2255 printf("gem_mii_readreg: PHY %d reg %d\n", phy, reg); 2256 #endif 2257 2258 /* Construct the frame command */ 2259 v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) | 2260 GEM_MIF_FRAME_READ; 2261 2262 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 2263 for (n = 0; n < 100; n++) { 2264 DELAY(1); 2265 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 2266 if (v & GEM_MIF_FRAME_TA0) 2267 return (v & GEM_MIF_FRAME_DATA); 2268 } 2269 2270 printf("%s: mii_read timeout\n", sc->sc_dev.dv_xname); 2271 return (0); 2272 } 2273 2274 static void 2275 gem_mii_writereg(self, phy, reg, val) 2276 struct device *self; 2277 int phy, reg, val; 2278 { 2279 struct gem_softc *sc = (void *)self; 2280 bus_space_tag_t t = sc->sc_bustag; 2281 bus_space_handle_t mif = sc->sc_h1; 2282 int n; 2283 u_int32_t v; 2284 2285 #ifdef GEM_DEBUG1 2286 if (sc->sc_debug) 2287 printf("gem_mii_writereg: PHY %d reg %d val %x\n", 2288 phy, reg, val); 2289 #endif 2290 2291 /* Construct the frame command */ 2292 v = GEM_MIF_FRAME_WRITE | 2293 (phy << GEM_MIF_PHY_SHIFT) | 2294 (reg << GEM_MIF_REG_SHIFT) | 2295 (val & GEM_MIF_FRAME_DATA); 2296 2297 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 2298 for (n = 0; n < 100; n++) { 2299 DELAY(1); 2300 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 2301 if (v & GEM_MIF_FRAME_TA0) 2302 return; 2303 } 2304 2305 printf("%s: mii_write timeout\n", sc->sc_dev.dv_xname); 2306 } 2307 2308 static void 2309 gem_mii_statchg(dev) 2310 struct device *dev; 2311 { 2312 struct gem_softc *sc = (void *)dev; 2313 #ifdef GEM_DEBUG 2314 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 2315 #endif 2316 2317 #ifdef GEM_DEBUG 2318 if (sc->sc_debug) 2319 printf("gem_mii_statchg: status change: phy = %d\n", 2320 sc->sc_phys[instance]); 2321 #endif 2322 gem_statuschange(sc); 2323 } 2324 2325 /* 2326 * Common status change for gem_mii_statchg() and gem_pint() 2327 */ 2328 void 2329 gem_statuschange(struct gem_softc* sc) 2330 { 2331 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2332 bus_space_tag_t t = sc->sc_bustag; 2333 bus_space_handle_t mac = sc->sc_h1; 2334 int gigabit; 2335 u_int32_t rxcfg, txcfg, v; 2336 2337 if ((sc->sc_mii.mii_media_status & IFM_ACTIVE) != 0 && 2338 IFM_SUBTYPE(sc->sc_mii.mii_media_active) != IFM_NONE) 2339 sc->sc_flags |= GEM_LINK; 2340 else 2341 sc->sc_flags &= ~GEM_LINK; 2342 2343 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 2344 gigabit = 1; 2345 else 2346 gigabit = 0; 2347 2348 /* 2349 * The configuration done here corresponds to the steps F) and 2350 * G) and as far as enabling of RX and TX MAC goes also step H) 2351 * of the initialization sequence outlined in section 3.2.1 of 2352 * the GEM Gigabit Ethernet ASIC Specification. 2353 */ 2354 2355 rxcfg = bus_space_read_4(t, mac, GEM_MAC_RX_CONFIG); 2356 rxcfg &= ~(GEM_MAC_RX_CARR_EXTEND | GEM_MAC_RX_ENABLE); 2357 txcfg = GEM_MAC_TX_ENA_IPG0 | GEM_MAC_TX_NGU | GEM_MAC_TX_NGU_LIMIT; 2358 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 2359 txcfg |= GEM_MAC_TX_IGN_CARRIER | GEM_MAC_TX_IGN_COLLIS; 2360 else if (gigabit) { 2361 rxcfg |= GEM_MAC_RX_CARR_EXTEND; 2362 txcfg |= GEM_MAC_RX_CARR_EXTEND; 2363 } 2364 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0); 2365 bus_space_barrier(t, mac, GEM_MAC_TX_CONFIG, 4, 2366 BUS_SPACE_BARRIER_WRITE); 2367 if (!gem_bitwait(sc, mac, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)) 2368 aprint_normal("%s: cannot disable TX MAC\n", 2369 sc->sc_dev.dv_xname); 2370 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, txcfg); 2371 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, 0); 2372 bus_space_barrier(t, mac, GEM_MAC_RX_CONFIG, 4, 2373 BUS_SPACE_BARRIER_WRITE); 2374 if (!gem_bitwait(sc, mac, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)) 2375 aprint_normal("%s: cannot disable RX MAC\n", 2376 sc->sc_dev.dv_xname); 2377 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, rxcfg); 2378 2379 v = bus_space_read_4(t, mac, GEM_MAC_CONTROL_CONFIG) & 2380 ~(GEM_MAC_CC_RX_PAUSE | GEM_MAC_CC_TX_PAUSE); 2381 bus_space_write_4(t, mac, GEM_MAC_CONTROL_CONFIG, v); 2382 2383 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) == 0 && 2384 gigabit != 0) 2385 bus_space_write_4(t, mac, GEM_MAC_SLOT_TIME, 2386 GEM_MAC_SLOT_TIME_CARR_EXTEND); 2387 else 2388 bus_space_write_4(t, mac, GEM_MAC_SLOT_TIME, 2389 GEM_MAC_SLOT_TIME_NORMAL); 2390 2391 /* XIF Configuration */ 2392 if (sc->sc_flags & GEM_LINK) 2393 v = GEM_MAC_XIF_LINK_LED; 2394 else 2395 v = 0; 2396 v |= GEM_MAC_XIF_TX_MII_ENA; 2397 2398 /* If an external transceiver is connected, enable its MII drivers */ 2399 sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG); 2400 if ((sc->sc_flags &(GEM_SERDES | GEM_SERIAL)) == 0) { 2401 if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) { 2402 /* External MII needs echo disable if half duplex. */ 2403 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & 2404 IFM_FDX) != 0) 2405 /* turn on full duplex LED */ 2406 v |= GEM_MAC_XIF_FDPLX_LED; 2407 else 2408 /* half duplex -- disable echo */ 2409 v |= GEM_MAC_XIF_ECHO_DISABL; 2410 if (gigabit) 2411 v |= GEM_MAC_XIF_GMII_MODE; 2412 else 2413 v &= ~GEM_MAC_XIF_GMII_MODE; 2414 } else 2415 /* Internal MII needs buf enable */ 2416 v |= GEM_MAC_XIF_MII_BUF_ENA; 2417 } else { 2418 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 2419 v |= GEM_MAC_XIF_FDPLX_LED; 2420 v |= GEM_MAC_XIF_GMII_MODE; 2421 } 2422 bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v); 2423 2424 if ((ifp->if_flags & IFF_RUNNING) != 0 && 2425 (sc->sc_flags & GEM_LINK) != 0) { 2426 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 2427 txcfg | GEM_MAC_TX_ENABLE); 2428 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, 2429 rxcfg | GEM_MAC_RX_ENABLE); 2430 } 2431 } 2432 2433 int 2434 gem_ser_mediachange(struct ifnet *ifp) 2435 { 2436 struct gem_softc *sc = ifp->if_softc; 2437 u_int s, t; 2438 2439 if (IFM_TYPE(sc->sc_mii.mii_media.ifm_media) != IFM_ETHER) 2440 return EINVAL; 2441 2442 s = IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media); 2443 if (s == IFM_AUTO) { 2444 if (sc->sc_mii_media != s) { 2445 #ifdef GEM_DEBUG 2446 aprint_debug("%s: setting media to auto\n", 2447 sc->sc_dev.dv_xname); 2448 #endif 2449 sc->sc_mii_media = s; 2450 if (ifp->if_flags & IFF_UP) { 2451 gem_pcs_stop(sc, 0); 2452 gem_pcs_start(sc); 2453 } 2454 } 2455 return 0; 2456 } 2457 if (s == IFM_1000_SX) { 2458 t = IFM_OPTIONS(sc->sc_mii.mii_media.ifm_media); 2459 if (t == IFM_FDX || t == IFM_HDX) { 2460 if (sc->sc_mii_media != t) { 2461 sc->sc_mii_media = t; 2462 #ifdef GEM_DEBUG 2463 aprint_debug("%s:" 2464 " setting media to 1000baseSX-%s\n", 2465 sc->sc_dev.dv_xname, 2466 t == IFM_FDX ? "FDX" : "HDX"); 2467 #endif 2468 if (ifp->if_flags & IFF_UP) { 2469 gem_pcs_stop(sc, 0); 2470 gem_pcs_start(sc); 2471 } 2472 } 2473 return 0; 2474 } 2475 } 2476 return EINVAL; 2477 } 2478 2479 void 2480 gem_ser_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2481 { 2482 struct gem_softc *sc = ifp->if_softc; 2483 2484 if ((ifp->if_flags & IFF_UP) == 0) 2485 return; 2486 ifmr->ifm_active = sc->sc_mii.mii_media_active; 2487 ifmr->ifm_status = sc->sc_mii.mii_media_status; 2488 } 2489 2490 /* 2491 * Process an ioctl request. 2492 */ 2493 int 2494 gem_ioctl(ifp, cmd, data) 2495 struct ifnet *ifp; 2496 u_long cmd; 2497 void *data; 2498 { 2499 struct gem_softc *sc = ifp->if_softc; 2500 int s, error = 0; 2501 2502 s = splnet(); 2503 2504 switch (cmd) { 2505 case SIOCSIFFLAGS: 2506 #define RESETIGN (IFF_CANTCHANGE|IFF_DEBUG) 2507 if (((ifp->if_flags & (IFF_UP|IFF_RUNNING)) 2508 == (IFF_UP|IFF_RUNNING)) 2509 && ((ifp->if_flags & (~RESETIGN)) 2510 == (sc->sc_if_flags & (~RESETIGN)))) { 2511 gem_setladrf(sc); 2512 break; 2513 } 2514 #undef RESETIGN 2515 /*FALLTHROUGH*/ 2516 default: 2517 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 2518 break; 2519 2520 error = 0; 2521 2522 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 2523 ; 2524 else if (ifp->if_flags & IFF_RUNNING) { 2525 /* 2526 * Multicast list has changed; set the hardware filter 2527 * accordingly. 2528 */ 2529 gem_setladrf(sc); 2530 } 2531 break; 2532 } 2533 2534 /* Try to get things going again */ 2535 if (ifp->if_flags & IFF_UP) 2536 gem_start(ifp); 2537 splx(s); 2538 return (error); 2539 } 2540 2541 2542 void 2543 gem_shutdown(arg) 2544 void *arg; 2545 { 2546 struct gem_softc *sc = (struct gem_softc *)arg; 2547 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2548 2549 gem_stop(ifp, 1); 2550 } 2551 2552 /* 2553 * Set up the logical address filter. 2554 */ 2555 void 2556 gem_setladrf(sc) 2557 struct gem_softc *sc; 2558 { 2559 struct ethercom *ec = &sc->sc_ethercom; 2560 struct ifnet *ifp = &ec->ec_if; 2561 struct ether_multi *enm; 2562 struct ether_multistep step; 2563 bus_space_tag_t t = sc->sc_bustag; 2564 bus_space_handle_t h = sc->sc_h1; 2565 u_int32_t crc; 2566 u_int32_t hash[16]; 2567 u_int32_t v; 2568 int i; 2569 2570 /* Get current RX configuration */ 2571 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 2572 2573 /* 2574 * Turn off promiscuous mode, promiscuous group mode (all multicast), 2575 * and hash filter. Depending on the case, the right bit will be 2576 * enabled. 2577 */ 2578 v &= ~(GEM_MAC_RX_PROMISCUOUS|GEM_MAC_RX_HASH_FILTER| 2579 GEM_MAC_RX_PROMISC_GRP); 2580 2581 if ((ifp->if_flags & IFF_PROMISC) != 0) { 2582 /* Turn on promiscuous mode */ 2583 v |= GEM_MAC_RX_PROMISCUOUS; 2584 ifp->if_flags |= IFF_ALLMULTI; 2585 goto chipit; 2586 } 2587 2588 /* 2589 * Set up multicast address filter by passing all multicast addresses 2590 * through a crc generator, and then using the high order 8 bits as an 2591 * index into the 256 bit logical address filter. The high order 4 2592 * bits selects the word, while the other 4 bits select the bit within 2593 * the word (where bit 0 is the MSB). 2594 */ 2595 2596 /* Clear hash table */ 2597 memset(hash, 0, sizeof(hash)); 2598 2599 ETHER_FIRST_MULTI(step, ec, enm); 2600 while (enm != NULL) { 2601 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2602 /* 2603 * We must listen to a range of multicast addresses. 2604 * For now, just accept all multicasts, rather than 2605 * trying to set only those filter bits needed to match 2606 * the range. (At this time, the only use of address 2607 * ranges is for IP multicast routing, for which the 2608 * range is big enough to require all bits set.) 2609 * XXX should use the address filters for this 2610 */ 2611 ifp->if_flags |= IFF_ALLMULTI; 2612 v |= GEM_MAC_RX_PROMISC_GRP; 2613 goto chipit; 2614 } 2615 2616 /* Get the LE CRC32 of the address */ 2617 crc = ether_crc32_le(enm->enm_addrlo, sizeof(enm->enm_addrlo)); 2618 2619 /* Just want the 8 most significant bits. */ 2620 crc >>= 24; 2621 2622 /* Set the corresponding bit in the filter. */ 2623 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 2624 2625 ETHER_NEXT_MULTI(step, enm); 2626 } 2627 2628 v |= GEM_MAC_RX_HASH_FILTER; 2629 ifp->if_flags &= ~IFF_ALLMULTI; 2630 2631 /* Now load the hash table into the chip (if we are using it) */ 2632 for (i = 0; i < 16; i++) { 2633 bus_space_write_4(t, h, 2634 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1-GEM_MAC_HASH0), 2635 hash[i]); 2636 } 2637 2638 chipit: 2639 sc->sc_if_flags = ifp->if_flags; 2640 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 2641 } 2642 2643 #if notyet 2644 2645 /* 2646 * gem_power: 2647 * 2648 * Power management (suspend/resume) hook. 2649 */ 2650 void 2651 gem_power(why, arg) 2652 int why; 2653 void *arg; 2654 { 2655 struct gem_softc *sc = arg; 2656 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2657 int s; 2658 2659 s = splnet(); 2660 switch (why) { 2661 case PWR_SUSPEND: 2662 case PWR_STANDBY: 2663 gem_stop(ifp, 1); 2664 if (sc->sc_power != NULL) 2665 (*sc->sc_power)(sc, why); 2666 break; 2667 case PWR_RESUME: 2668 if (ifp->if_flags & IFF_UP) { 2669 if (sc->sc_power != NULL) 2670 (*sc->sc_power)(sc, why); 2671 gem_init(ifp); 2672 } 2673 break; 2674 case PWR_SOFTSUSPEND: 2675 case PWR_SOFTSTANDBY: 2676 case PWR_SOFTRESUME: 2677 break; 2678 } 2679 splx(s); 2680 } 2681 #endif 2682
Indexes created Mon Sep 22 13:09:51 GMT 2025