gem.c revision 1.84
1 /* $NetBSD: gem.c,v 1.84 2009/05/12 14:25:17 cegger Exp $ */ 2 3 /* 4 * 5 * Copyright (C) 2001 Eduardo Horvath. 6 * Copyright (c) 2001-2003 Thomas Moestl 7 * All rights reserved. 8 * 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 */ 32 33 /* 34 * Driver for Apple GMAC, Sun ERI and Sun GEM Ethernet controllers 35 * See `GEM Gigabit Ethernet ASIC Specification' 36 * http://www.sun.com/processors/manuals/ge.pdf 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: gem.c,v 1.84 2009/05/12 14:25:17 cegger Exp $"); 41 42 #include "opt_inet.h" 43 #include "bpfilter.h" 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/callout.h> 48 #include <sys/mbuf.h> 49 #include <sys/syslog.h> 50 #include <sys/malloc.h> 51 #include <sys/kernel.h> 52 #include <sys/socket.h> 53 #include <sys/ioctl.h> 54 #include <sys/errno.h> 55 #include <sys/device.h> 56 57 #include <machine/endian.h> 58 59 #include <uvm/uvm_extern.h> 60 61 #include <net/if.h> 62 #include <net/if_dl.h> 63 #include <net/if_media.h> 64 #include <net/if_ether.h> 65 66 #ifdef INET 67 #include <netinet/in.h> 68 #include <netinet/in_systm.h> 69 #include <netinet/in_var.h> 70 #include <netinet/ip.h> 71 #include <netinet/tcp.h> 72 #include <netinet/udp.h> 73 #endif 74 75 #if NBPFILTER > 0 76 #include <net/bpf.h> 77 #endif 78 79 #include <sys/bus.h> 80 #include <sys/intr.h> 81 82 #include <dev/mii/mii.h> 83 #include <dev/mii/miivar.h> 84 #include <dev/mii/mii_bitbang.h> 85 86 #include <dev/ic/gemreg.h> 87 #include <dev/ic/gemvar.h> 88 89 #define TRIES 10000 90 91 static void gem_start(struct ifnet *); 92 static void gem_stop(struct ifnet *, int); 93 int gem_ioctl(struct ifnet *, u_long, void *); 94 void gem_tick(void *); 95 void gem_watchdog(struct ifnet *); 96 void gem_shutdown(void *); 97 void gem_pcs_start(struct gem_softc *sc); 98 void gem_pcs_stop(struct gem_softc *sc, int); 99 int gem_init(struct ifnet *); 100 void gem_init_regs(struct gem_softc *sc); 101 static int gem_ringsize(int sz); 102 static int gem_meminit(struct gem_softc *); 103 void gem_mifinit(struct gem_softc *); 104 static int gem_bitwait(struct gem_softc *sc, bus_space_handle_t, int, 105 u_int32_t, u_int32_t); 106 void gem_reset(struct gem_softc *); 107 int gem_reset_rx(struct gem_softc *sc); 108 static void gem_reset_rxdma(struct gem_softc *sc); 109 static void gem_rx_common(struct gem_softc *sc); 110 int gem_reset_tx(struct gem_softc *sc); 111 int gem_disable_rx(struct gem_softc *sc); 112 int gem_disable_tx(struct gem_softc *sc); 113 static void gem_rxdrain(struct gem_softc *sc); 114 int gem_add_rxbuf(struct gem_softc *sc, int idx); 115 void gem_setladrf(struct gem_softc *); 116 117 /* MII methods & callbacks */ 118 static int gem_mii_readreg(device_t, int, int); 119 static void gem_mii_writereg(device_t, int, int, int); 120 static void gem_mii_statchg(device_t); 121 122 static int gem_ifflags_cb(struct ethercom *); 123 124 void gem_statuschange(struct gem_softc *); 125 126 int gem_ser_mediachange(struct ifnet *); 127 void gem_ser_mediastatus(struct ifnet *, struct ifmediareq *); 128 129 struct mbuf *gem_get(struct gem_softc *, int, int); 130 int gem_put(struct gem_softc *, int, struct mbuf *); 131 void gem_read(struct gem_softc *, int, int); 132 int gem_pint(struct gem_softc *); 133 int gem_eint(struct gem_softc *, u_int); 134 int gem_rint(struct gem_softc *); 135 int gem_tint(struct gem_softc *); 136 void gem_power(int, void *); 137 138 #ifdef GEM_DEBUG 139 static void gem_txsoft_print(const struct gem_softc *, int, int); 140 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 141 printf x 142 #else 143 #define DPRINTF(sc, x) /* nothing */ 144 #endif 145 146 #define ETHER_MIN_TX (ETHERMIN + sizeof(struct ether_header)) 147 148 149 /* 150 * gem_attach: 151 * 152 * Attach a Gem interface to the system. 153 */ 154 void 155 gem_attach(struct gem_softc *sc, const uint8_t *enaddr) 156 { 157 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 158 struct mii_data *mii = &sc->sc_mii; 159 bus_space_tag_t t = sc->sc_bustag; 160 bus_space_handle_t h = sc->sc_h1; 161 struct ifmedia_entry *ifm; 162 int i, error; 163 u_int32_t v; 164 char *nullbuf; 165 166 /* Make sure the chip is stopped. */ 167 ifp->if_softc = sc; 168 gem_reset(sc); 169 170 /* 171 * Allocate the control data structures, and create and load the 172 * DMA map for it. gem_control_data is 9216 bytes, we have space for 173 * the padding buffer in the bus_dmamem_alloc()'d memory. 174 */ 175 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 176 sizeof(struct gem_control_data) + ETHER_MIN_TX, PAGE_SIZE, 177 0, &sc->sc_cdseg, 1, &sc->sc_cdnseg, 0)) != 0) { 178 aprint_error_dev(&sc->sc_dev, 179 "unable to allocate control data, error = %d\n", 180 error); 181 goto fail_0; 182 } 183 184 /* XXX should map this in with correct endianness */ 185 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg, 186 sizeof(struct gem_control_data), (void **)&sc->sc_control_data, 187 BUS_DMA_COHERENT)) != 0) { 188 aprint_error_dev(&sc->sc_dev, "unable to map control data, error = %d\n", 189 error); 190 goto fail_1; 191 } 192 193 nullbuf = 194 (char *)sc->sc_control_data + sizeof(struct gem_control_data); 195 196 if ((error = bus_dmamap_create(sc->sc_dmatag, 197 sizeof(struct gem_control_data), 1, 198 sizeof(struct gem_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 199 aprint_error_dev(&sc->sc_dev, "unable to create control data DMA map, " 200 "error = %d\n", error); 201 goto fail_2; 202 } 203 204 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 205 sc->sc_control_data, sizeof(struct gem_control_data), NULL, 206 0)) != 0) { 207 aprint_error_dev(&sc->sc_dev, 208 "unable to load control data DMA map, error = %d\n", 209 error); 210 goto fail_3; 211 } 212 213 memset(nullbuf, 0, ETHER_MIN_TX); 214 if ((error = bus_dmamap_create(sc->sc_dmatag, 215 ETHER_MIN_TX, 1, ETHER_MIN_TX, 0, 0, &sc->sc_nulldmamap)) != 0) { 216 aprint_error_dev(&sc->sc_dev, "unable to create padding DMA map, " 217 "error = %d\n", error); 218 goto fail_4; 219 } 220 221 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_nulldmamap, 222 nullbuf, ETHER_MIN_TX, NULL, 0)) != 0) { 223 aprint_error_dev(&sc->sc_dev, 224 "unable to load padding DMA map, error = %d\n", 225 error); 226 goto fail_5; 227 } 228 229 bus_dmamap_sync(sc->sc_dmatag, sc->sc_nulldmamap, 0, ETHER_MIN_TX, 230 BUS_DMASYNC_PREWRITE); 231 232 /* 233 * Initialize the transmit job descriptors. 234 */ 235 SIMPLEQ_INIT(&sc->sc_txfreeq); 236 SIMPLEQ_INIT(&sc->sc_txdirtyq); 237 238 /* 239 * Create the transmit buffer DMA maps. 240 */ 241 for (i = 0; i < GEM_TXQUEUELEN; i++) { 242 struct gem_txsoft *txs; 243 244 txs = &sc->sc_txsoft[i]; 245 txs->txs_mbuf = NULL; 246 if ((error = bus_dmamap_create(sc->sc_dmatag, 247 ETHER_MAX_LEN_JUMBO, GEM_NTXSEGS, 248 ETHER_MAX_LEN_JUMBO, 0, 0, 249 &txs->txs_dmamap)) != 0) { 250 aprint_error_dev(&sc->sc_dev, "unable to create tx DMA map %d, " 251 "error = %d\n", i, error); 252 goto fail_6; 253 } 254 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 255 } 256 257 /* 258 * Create the receive buffer DMA maps. 259 */ 260 for (i = 0; i < GEM_NRXDESC; i++) { 261 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, 262 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 263 aprint_error_dev(&sc->sc_dev, "unable to create rx DMA map %d, " 264 "error = %d\n", i, error); 265 goto fail_7; 266 } 267 sc->sc_rxsoft[i].rxs_mbuf = NULL; 268 } 269 270 /* Initialize ifmedia structures and MII info */ 271 mii->mii_ifp = ifp; 272 mii->mii_readreg = gem_mii_readreg; 273 mii->mii_writereg = gem_mii_writereg; 274 mii->mii_statchg = gem_mii_statchg; 275 276 sc->sc_ethercom.ec_mii = mii; 277 278 /* 279 * Initialization based on `GEM Gigabit Ethernet ASIC Specification' 280 * Section 3.2.1 `Initialization Sequence'. 281 * However, we can't assume SERDES or Serialink if neither 282 * GEM_MIF_CONFIG_MDI0 nor GEM_MIF_CONFIG_MDI1 are set 283 * being set, as both are set on Sun X1141A (with SERDES). So, 284 * we rely on our bus attachment setting GEM_SERDES or GEM_SERIAL. 285 * Also, for Apple variants with 2 PHY's, we prefer the external 286 * PHY over the internal PHY. 287 */ 288 gem_mifinit(sc); 289 290 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) { 291 ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange, 292 ether_mediastatus); 293 mii_attach(&sc->sc_dev, mii, 0xffffffff, 294 MII_PHY_ANY, MII_OFFSET_ANY, MIIF_FORCEANEG); 295 if (LIST_EMPTY(&mii->mii_phys)) { 296 /* No PHY attached */ 297 aprint_error_dev(&sc->sc_dev, "PHY probe failed\n"); 298 goto fail_7; 299 } else { 300 struct mii_softc *child; 301 302 /* 303 * Walk along the list of attached MII devices and 304 * establish an `MII instance' to `PHY number' 305 * mapping. 306 */ 307 LIST_FOREACH(child, &mii->mii_phys, mii_list) { 308 /* 309 * Note: we support just one PHY: the internal 310 * or external MII is already selected for us 311 * by the GEM_MIF_CONFIG register. 312 */ 313 if (child->mii_phy > 1 || child->mii_inst > 0) { 314 aprint_error_dev(&sc->sc_dev, 315 "cannot accommodate MII device" 316 " %s at PHY %d, instance %d\n", 317 device_xname(child->mii_dev), 318 child->mii_phy, child->mii_inst); 319 continue; 320 } 321 sc->sc_phys[child->mii_inst] = child->mii_phy; 322 } 323 324 /* 325 * Now select and activate the PHY we will use. 326 * 327 * The order of preference is External (MDI1), 328 * then Internal (MDI0), 329 */ 330 if (sc->sc_phys[1]) { 331 #ifdef GEM_DEBUG 332 aprint_debug_dev(&sc->sc_dev, "using external PHY\n"); 333 #endif 334 sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL; 335 } else { 336 #ifdef GEM_DEBUG 337 aprint_debug_dev(&sc->sc_dev, "using internal PHY\n"); 338 sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL; 339 #endif 340 } 341 bus_space_write_4(t, h, GEM_MIF_CONFIG, 342 sc->sc_mif_config); 343 if (sc->sc_variant != GEM_SUN_ERI) 344 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 345 GEM_MII_DATAPATH_MII); 346 347 /* 348 * XXX - we can really do the following ONLY if the 349 * PHY indeed has the auto negotiation capability!! 350 */ 351 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 352 } 353 } else { 354 ifmedia_init(&mii->mii_media, IFM_IMASK, gem_ser_mediachange, 355 gem_ser_mediastatus); 356 /* SERDES or Serialink */ 357 if (sc->sc_flags & GEM_SERDES) { 358 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 359 GEM_MII_DATAPATH_SERDES); 360 } else { 361 sc->sc_flags |= GEM_SERIAL; 362 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 363 GEM_MII_DATAPATH_SERIAL); 364 } 365 366 aprint_normal_dev(&sc->sc_dev, "using external PCS %s: ", 367 sc->sc_flags & GEM_SERDES ? "SERDES" : "Serialink"); 368 369 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO, 0, NULL); 370 /* Check for FDX and HDX capabilities */ 371 sc->sc_mii_anar = bus_space_read_4(t, h, GEM_MII_ANAR); 372 if (sc->sc_mii_anar & GEM_MII_ANEG_FUL_DUPLX) { 373 ifmedia_add(&sc->sc_mii.mii_media, 374 IFM_ETHER|IFM_1000_SX|IFM_MANUAL|IFM_FDX, 0, NULL); 375 aprint_normal("1000baseSX-FDX, "); 376 } 377 if (sc->sc_mii_anar & GEM_MII_ANEG_HLF_DUPLX) { 378 ifmedia_add(&sc->sc_mii.mii_media, 379 IFM_ETHER|IFM_1000_SX|IFM_MANUAL|IFM_HDX, 0, NULL); 380 aprint_normal("1000baseSX-HDX, "); 381 } 382 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 383 sc->sc_mii_media = IFM_AUTO; 384 aprint_normal("auto\n"); 385 386 gem_pcs_stop(sc, 1); 387 } 388 389 /* 390 * From this point forward, the attachment cannot fail. A failure 391 * before this point releases all resources that may have been 392 * allocated. 393 */ 394 395 /* Announce ourselves. */ 396 aprint_normal_dev(&sc->sc_dev, "Ethernet address %s", 397 ether_sprintf(enaddr)); 398 399 /* Get RX FIFO size */ 400 sc->sc_rxfifosize = 64 * 401 bus_space_read_4(t, h, GEM_RX_FIFO_SIZE); 402 aprint_normal(", %uKB RX fifo", sc->sc_rxfifosize / 1024); 403 404 /* Get TX FIFO size */ 405 v = bus_space_read_4(t, h, GEM_TX_FIFO_SIZE); 406 aprint_normal(", %uKB TX fifo\n", v / 16); 407 408 /* Initialize ifnet structure. */ 409 strlcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ); 410 ifp->if_softc = sc; 411 ifp->if_flags = 412 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 413 sc->sc_if_flags = ifp->if_flags; 414 /* 415 * The GEM hardware supports basic TCP checksum offloading only. 416 * Several (all?) revisions (Sun rev. 01 and Apple rev. 00 and 80) 417 * have bugs in the receive checksum, so don't enable it for now. 418 if ((GEM_IS_SUN(sc) && sc->sc_chiprev != 1) || 419 (GEM_IS_APPLE(sc) && 420 (sc->sc_chiprev != 0 && sc->sc_chiprev != 0x80))) 421 ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Rx; 422 */ 423 ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Tx; 424 ifp->if_start = gem_start; 425 ifp->if_ioctl = gem_ioctl; 426 ifp->if_watchdog = gem_watchdog; 427 ifp->if_stop = gem_stop; 428 ifp->if_init = gem_init; 429 IFQ_SET_READY(&ifp->if_snd); 430 431 /* 432 * If we support GigE media, we support jumbo frames too. 433 * Unless we are Apple. 434 */ 435 TAILQ_FOREACH(ifm, &sc->sc_mii.mii_media.ifm_list, ifm_list) { 436 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_T || 437 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_SX || 438 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_LX || 439 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_CX) { 440 if (!GEM_IS_APPLE(sc)) 441 sc->sc_ethercom.ec_capabilities 442 |= ETHERCAP_JUMBO_MTU; 443 sc->sc_flags |= GEM_GIGABIT; 444 break; 445 } 446 } 447 448 /* claim 802.1q capability */ 449 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 450 451 /* Attach the interface. */ 452 if_attach(ifp); 453 ether_ifattach(ifp, enaddr); 454 ether_set_ifflags_cb(&sc->sc_ethercom, gem_ifflags_cb); 455 456 sc->sc_sh = shutdownhook_establish(gem_shutdown, sc); 457 if (sc->sc_sh == NULL) 458 panic("gem_config: can't establish shutdownhook"); 459 460 #if NRND > 0 461 rnd_attach_source(&sc->rnd_source, device_xname(&sc->sc_dev), 462 RND_TYPE_NET, 0); 463 #endif 464 465 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, 466 NULL, device_xname(&sc->sc_dev), "interrupts"); 467 #ifdef GEM_COUNTERS 468 evcnt_attach_dynamic(&sc->sc_ev_txint, EVCNT_TYPE_INTR, 469 &sc->sc_ev_intr, device_xname(&sc->sc_dev), "tx interrupts"); 470 evcnt_attach_dynamic(&sc->sc_ev_rxint, EVCNT_TYPE_INTR, 471 &sc->sc_ev_intr, device_xname(&sc->sc_dev), "rx interrupts"); 472 evcnt_attach_dynamic(&sc->sc_ev_rxfull, EVCNT_TYPE_INTR, 473 &sc->sc_ev_rxint, device_xname(&sc->sc_dev), "rx ring full"); 474 evcnt_attach_dynamic(&sc->sc_ev_rxnobuf, EVCNT_TYPE_INTR, 475 &sc->sc_ev_rxint, device_xname(&sc->sc_dev), "rx malloc failure"); 476 evcnt_attach_dynamic(&sc->sc_ev_rxhist[0], EVCNT_TYPE_INTR, 477 &sc->sc_ev_rxint, device_xname(&sc->sc_dev), "rx 0desc"); 478 evcnt_attach_dynamic(&sc->sc_ev_rxhist[1], EVCNT_TYPE_INTR, 479 &sc->sc_ev_rxint, device_xname(&sc->sc_dev), "rx 1desc"); 480 evcnt_attach_dynamic(&sc->sc_ev_rxhist[2], EVCNT_TYPE_INTR, 481 &sc->sc_ev_rxint, device_xname(&sc->sc_dev), "rx 2desc"); 482 evcnt_attach_dynamic(&sc->sc_ev_rxhist[3], EVCNT_TYPE_INTR, 483 &sc->sc_ev_rxint, device_xname(&sc->sc_dev), "rx 3desc"); 484 evcnt_attach_dynamic(&sc->sc_ev_rxhist[4], EVCNT_TYPE_INTR, 485 &sc->sc_ev_rxint, device_xname(&sc->sc_dev), "rx >3desc"); 486 evcnt_attach_dynamic(&sc->sc_ev_rxhist[5], EVCNT_TYPE_INTR, 487 &sc->sc_ev_rxint, device_xname(&sc->sc_dev), "rx >7desc"); 488 evcnt_attach_dynamic(&sc->sc_ev_rxhist[6], EVCNT_TYPE_INTR, 489 &sc->sc_ev_rxint, device_xname(&sc->sc_dev), "rx >15desc"); 490 evcnt_attach_dynamic(&sc->sc_ev_rxhist[7], EVCNT_TYPE_INTR, 491 &sc->sc_ev_rxint, device_xname(&sc->sc_dev), "rx >31desc"); 492 evcnt_attach_dynamic(&sc->sc_ev_rxhist[8], EVCNT_TYPE_INTR, 493 &sc->sc_ev_rxint, device_xname(&sc->sc_dev), "rx >63desc"); 494 #endif 495 496 #if notyet 497 /* 498 * Add a suspend hook to make sure we come back up after a 499 * resume. 500 */ 501 sc->sc_powerhook = powerhook_establish(device_xname(&sc->sc_dev), 502 gem_power, sc); 503 if (sc->sc_powerhook == NULL) 504 aprint_error_dev(&sc->sc_dev, "WARNING: unable to establish power hook\n"); 505 #endif 506 507 callout_init(&sc->sc_tick_ch, 0); 508 return; 509 510 /* 511 * Free any resources we've allocated during the failed attach 512 * attempt. Do this in reverse order and fall through. 513 */ 514 fail_7: 515 for (i = 0; i < GEM_NRXDESC; i++) { 516 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 517 bus_dmamap_destroy(sc->sc_dmatag, 518 sc->sc_rxsoft[i].rxs_dmamap); 519 } 520 fail_6: 521 for (i = 0; i < GEM_TXQUEUELEN; i++) { 522 if (sc->sc_txsoft[i].txs_dmamap != NULL) 523 bus_dmamap_destroy(sc->sc_dmatag, 524 sc->sc_txsoft[i].txs_dmamap); 525 } 526 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 527 fail_5: 528 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_nulldmamap); 529 fail_4: 530 bus_dmamem_unmap(sc->sc_dmatag, (void *)nullbuf, ETHER_MIN_TX); 531 fail_3: 532 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 533 fail_2: 534 bus_dmamem_unmap(sc->sc_dmatag, (void *)sc->sc_control_data, 535 sizeof(struct gem_control_data)); 536 fail_1: 537 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 538 fail_0: 539 return; 540 } 541 542 543 void 544 gem_tick(void *arg) 545 { 546 struct gem_softc *sc = arg; 547 int s; 548 549 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) { 550 /* 551 * We have to reset everything if we failed to get a 552 * PCS interrupt. Restarting the callout is handled 553 * in gem_pcs_start(). 554 */ 555 gem_init(&sc->sc_ethercom.ec_if); 556 } else { 557 s = splnet(); 558 mii_tick(&sc->sc_mii); 559 splx(s); 560 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 561 } 562 } 563 564 static int 565 gem_bitwait(struct gem_softc *sc, bus_space_handle_t h, int r, u_int32_t clr, u_int32_t set) 566 { 567 int i; 568 u_int32_t reg; 569 570 for (i = TRIES; i--; DELAY(100)) { 571 reg = bus_space_read_4(sc->sc_bustag, h, r); 572 if ((reg & clr) == 0 && (reg & set) == set) 573 return (1); 574 } 575 return (0); 576 } 577 578 void 579 gem_reset(struct gem_softc *sc) 580 { 581 bus_space_tag_t t = sc->sc_bustag; 582 bus_space_handle_t h = sc->sc_h2; 583 int s; 584 585 s = splnet(); 586 DPRINTF(sc, ("%s: gem_reset\n", device_xname(&sc->sc_dev))); 587 gem_reset_rx(sc); 588 gem_reset_tx(sc); 589 590 /* Do a full reset */ 591 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX|GEM_RESET_TX); 592 if (!gem_bitwait(sc, h, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0)) 593 aprint_error_dev(&sc->sc_dev, "cannot reset device\n"); 594 splx(s); 595 } 596 597 598 /* 599 * gem_rxdrain: 600 * 601 * Drain the receive queue. 602 */ 603 static void 604 gem_rxdrain(struct gem_softc *sc) 605 { 606 struct gem_rxsoft *rxs; 607 int i; 608 609 for (i = 0; i < GEM_NRXDESC; i++) { 610 rxs = &sc->sc_rxsoft[i]; 611 if (rxs->rxs_mbuf != NULL) { 612 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 613 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 614 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 615 m_freem(rxs->rxs_mbuf); 616 rxs->rxs_mbuf = NULL; 617 } 618 } 619 } 620 621 /* 622 * Reset the whole thing. 623 */ 624 static void 625 gem_stop(struct ifnet *ifp, int disable) 626 { 627 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 628 struct gem_txsoft *txs; 629 630 DPRINTF(sc, ("%s: gem_stop\n", device_xname(&sc->sc_dev))); 631 632 callout_stop(&sc->sc_tick_ch); 633 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 634 gem_pcs_stop(sc, disable); 635 else 636 mii_down(&sc->sc_mii); 637 638 /* XXX - Should we reset these instead? */ 639 gem_disable_tx(sc); 640 gem_disable_rx(sc); 641 642 /* 643 * Release any queued transmit buffers. 644 */ 645 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 646 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 647 if (txs->txs_mbuf != NULL) { 648 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 0, 649 txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 650 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 651 m_freem(txs->txs_mbuf); 652 txs->txs_mbuf = NULL; 653 } 654 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 655 } 656 657 /* 658 * Mark the interface down and cancel the watchdog timer. 659 */ 660 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 661 sc->sc_if_flags = ifp->if_flags; 662 ifp->if_timer = 0; 663 664 if (disable) 665 gem_rxdrain(sc); 666 } 667 668 669 /* 670 * Reset the receiver 671 */ 672 int 673 gem_reset_rx(struct gem_softc *sc) 674 { 675 bus_space_tag_t t = sc->sc_bustag; 676 bus_space_handle_t h = sc->sc_h1, h2 = sc->sc_h2; 677 678 /* 679 * Resetting while DMA is in progress can cause a bus hang, so we 680 * disable DMA first. 681 */ 682 gem_disable_rx(sc); 683 bus_space_write_4(t, h, GEM_RX_CONFIG, 0); 684 bus_space_barrier(t, h, GEM_RX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 685 /* Wait till it finishes */ 686 if (!gem_bitwait(sc, h, GEM_RX_CONFIG, 1, 0)) 687 aprint_error_dev(&sc->sc_dev, "cannot disable read dma\n"); 688 689 /* Finally, reset the ERX */ 690 bus_space_write_4(t, h2, GEM_RESET, GEM_RESET_RX); 691 bus_space_barrier(t, h, GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE); 692 /* Wait till it finishes */ 693 if (!gem_bitwait(sc, h2, GEM_RESET, GEM_RESET_RX, 0)) { 694 aprint_error_dev(&sc->sc_dev, "cannot reset receiver\n"); 695 return (1); 696 } 697 return (0); 698 } 699 700 701 /* 702 * Reset the receiver DMA engine. 703 * 704 * Intended to be used in case of GEM_INTR_RX_TAG_ERR, GEM_MAC_RX_OVERFLOW 705 * etc in order to reset the receiver DMA engine only and not do a full 706 * reset which amongst others also downs the link and clears the FIFOs. 707 */ 708 static void 709 gem_reset_rxdma(struct gem_softc *sc) 710 { 711 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 712 bus_space_tag_t t = sc->sc_bustag; 713 bus_space_handle_t h = sc->sc_h1; 714 int i; 715 716 if (gem_reset_rx(sc) != 0) { 717 gem_init(ifp); 718 return; 719 } 720 for (i = 0; i < GEM_NRXDESC; i++) 721 if (sc->sc_rxsoft[i].rxs_mbuf != NULL) 722 GEM_UPDATE_RXDESC(sc, i); 723 sc->sc_rxptr = 0; 724 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE); 725 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD); 726 727 /* Reprogram Descriptor Ring Base Addresses */ 728 /* NOTE: we use only 32-bit DMA addresses here. */ 729 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0); 730 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 731 732 /* Redo ERX Configuration */ 733 gem_rx_common(sc); 734 735 /* Give the reciever a swift kick */ 736 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC - 4); 737 } 738 739 /* 740 * Common RX configuration for gem_init() and gem_reset_rxdma(). 741 */ 742 static void 743 gem_rx_common(struct gem_softc *sc) 744 { 745 bus_space_tag_t t = sc->sc_bustag; 746 bus_space_handle_t h = sc->sc_h1; 747 u_int32_t v; 748 749 /* Encode Receive Descriptor ring size: four possible values */ 750 v = gem_ringsize(GEM_NRXDESC /*XXX*/); 751 752 /* Set receive h/w checksum offset */ 753 #ifdef INET 754 v |= (ETHER_HDR_LEN + sizeof(struct ip) + 755 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 756 ETHER_VLAN_ENCAP_LEN : 0)) << GEM_RX_CONFIG_CXM_START_SHFT; 757 #endif 758 759 /* Enable RX DMA */ 760 bus_space_write_4(t, h, GEM_RX_CONFIG, 761 v | (GEM_THRSH_1024 << GEM_RX_CONFIG_FIFO_THRS_SHIFT) | 762 (2 << GEM_RX_CONFIG_FBOFF_SHFT) | GEM_RX_CONFIG_RXDMA_EN); 763 764 /* 765 * The following value is for an OFF Threshold of about 3/4 full 766 * and an ON Threshold of 1/4 full. 767 */ 768 bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH, 769 (3 * sc->sc_rxfifosize / 256) | 770 ((sc->sc_rxfifosize / 256) << 12)); 771 bus_space_write_4(t, h, GEM_RX_BLANKING, 772 (6 << GEM_RX_BLANKING_TIME_SHIFT) | 6); 773 } 774 775 /* 776 * Reset the transmitter 777 */ 778 int 779 gem_reset_tx(struct gem_softc *sc) 780 { 781 bus_space_tag_t t = sc->sc_bustag; 782 bus_space_handle_t h = sc->sc_h1, h2 = sc->sc_h2; 783 784 /* 785 * Resetting while DMA is in progress can cause a bus hang, so we 786 * disable DMA first. 787 */ 788 gem_disable_tx(sc); 789 bus_space_write_4(t, h, GEM_TX_CONFIG, 0); 790 bus_space_barrier(t, h, GEM_TX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 791 /* Wait till it finishes */ 792 if (!gem_bitwait(sc, h, GEM_TX_CONFIG, 1, 0)) 793 aprint_error_dev(&sc->sc_dev, "cannot disable read dma\n"); 794 /* Wait 5ms extra. */ 795 delay(5000); 796 797 /* Finally, reset the ETX */ 798 bus_space_write_4(t, h2, GEM_RESET, GEM_RESET_TX); 799 bus_space_barrier(t, h, GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE); 800 /* Wait till it finishes */ 801 if (!gem_bitwait(sc, h2, GEM_RESET, GEM_RESET_TX, 0)) { 802 aprint_error_dev(&sc->sc_dev, "cannot reset receiver\n"); 803 return (1); 804 } 805 return (0); 806 } 807 808 /* 809 * disable receiver. 810 */ 811 int 812 gem_disable_rx(struct gem_softc *sc) 813 { 814 bus_space_tag_t t = sc->sc_bustag; 815 bus_space_handle_t h = sc->sc_h1; 816 u_int32_t cfg; 817 818 /* Flip the enable bit */ 819 cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 820 cfg &= ~GEM_MAC_RX_ENABLE; 821 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg); 822 bus_space_barrier(t, h, GEM_MAC_RX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 823 /* Wait for it to finish */ 824 return (gem_bitwait(sc, h, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)); 825 } 826 827 /* 828 * disable transmitter. 829 */ 830 int 831 gem_disable_tx(struct gem_softc *sc) 832 { 833 bus_space_tag_t t = sc->sc_bustag; 834 bus_space_handle_t h = sc->sc_h1; 835 u_int32_t cfg; 836 837 /* Flip the enable bit */ 838 cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG); 839 cfg &= ~GEM_MAC_TX_ENABLE; 840 bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg); 841 bus_space_barrier(t, h, GEM_MAC_TX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 842 /* Wait for it to finish */ 843 return (gem_bitwait(sc, h, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)); 844 } 845 846 /* 847 * Initialize interface. 848 */ 849 int 850 gem_meminit(struct gem_softc *sc) 851 { 852 struct gem_rxsoft *rxs; 853 int i, error; 854 855 /* 856 * Initialize the transmit descriptor ring. 857 */ 858 memset((void *)sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 859 for (i = 0; i < GEM_NTXDESC; i++) { 860 sc->sc_txdescs[i].gd_flags = 0; 861 sc->sc_txdescs[i].gd_addr = 0; 862 } 863 GEM_CDTXSYNC(sc, 0, GEM_NTXDESC, 864 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 865 sc->sc_txfree = GEM_NTXDESC-1; 866 sc->sc_txnext = 0; 867 sc->sc_txwin = 0; 868 869 /* 870 * Initialize the receive descriptor and receive job 871 * descriptor rings. 872 */ 873 for (i = 0; i < GEM_NRXDESC; i++) { 874 rxs = &sc->sc_rxsoft[i]; 875 if (rxs->rxs_mbuf == NULL) { 876 if ((error = gem_add_rxbuf(sc, i)) != 0) { 877 aprint_error_dev(&sc->sc_dev, "unable to allocate or map rx " 878 "buffer %d, error = %d\n", 879 i, error); 880 /* 881 * XXX Should attempt to run with fewer receive 882 * XXX buffers instead of just failing. 883 */ 884 gem_rxdrain(sc); 885 return (1); 886 } 887 } else 888 GEM_INIT_RXDESC(sc, i); 889 } 890 sc->sc_rxptr = 0; 891 sc->sc_meminited = 1; 892 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE); 893 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD); 894 895 return (0); 896 } 897 898 static int 899 gem_ringsize(int sz) 900 { 901 switch (sz) { 902 case 32: 903 return GEM_RING_SZ_32; 904 case 64: 905 return GEM_RING_SZ_64; 906 case 128: 907 return GEM_RING_SZ_128; 908 case 256: 909 return GEM_RING_SZ_256; 910 case 512: 911 return GEM_RING_SZ_512; 912 case 1024: 913 return GEM_RING_SZ_1024; 914 case 2048: 915 return GEM_RING_SZ_2048; 916 case 4096: 917 return GEM_RING_SZ_4096; 918 case 8192: 919 return GEM_RING_SZ_8192; 920 default: 921 printf("gem: invalid Receive Descriptor ring size %d\n", sz); 922 return GEM_RING_SZ_32; 923 } 924 } 925 926 927 /* 928 * Start PCS 929 */ 930 void 931 gem_pcs_start(struct gem_softc *sc) 932 { 933 bus_space_tag_t t = sc->sc_bustag; 934 bus_space_handle_t h = sc->sc_h1; 935 uint32_t v; 936 937 #ifdef GEM_DEBUG 938 aprint_debug_dev(&sc->sc_dev, "gem_pcs_start()\n"); 939 #endif 940 941 /* 942 * Set up. We must disable the MII before modifying the 943 * GEM_MII_ANAR register 944 */ 945 if (sc->sc_flags & GEM_SERDES) { 946 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 947 GEM_MII_DATAPATH_SERDES); 948 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 949 GEM_MII_SLINK_LOOPBACK); 950 } else { 951 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 952 GEM_MII_DATAPATH_SERIAL); 953 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 0); 954 } 955 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 956 v = bus_space_read_4(t, h, GEM_MII_ANAR); 957 v |= (GEM_MII_ANEG_SYM_PAUSE | GEM_MII_ANEG_ASYM_PAUSE); 958 if (sc->sc_mii_media == IFM_AUTO) 959 v |= (GEM_MII_ANEG_FUL_DUPLX | GEM_MII_ANEG_HLF_DUPLX); 960 else if (sc->sc_mii_media == IFM_FDX) { 961 v |= GEM_MII_ANEG_FUL_DUPLX; 962 v &= ~GEM_MII_ANEG_HLF_DUPLX; 963 } else if (sc->sc_mii_media == IFM_HDX) { 964 v &= ~GEM_MII_ANEG_FUL_DUPLX; 965 v |= GEM_MII_ANEG_HLF_DUPLX; 966 } 967 968 /* Configure link. */ 969 bus_space_write_4(t, h, GEM_MII_ANAR, v); 970 bus_space_write_4(t, h, GEM_MII_CONTROL, 971 GEM_MII_CONTROL_AUTONEG | GEM_MII_CONTROL_RAN); 972 bus_space_write_4(t, h, GEM_MII_CONFIG, GEM_MII_CONFIG_ENABLE); 973 gem_bitwait(sc, h, GEM_MII_STATUS, 0, GEM_MII_STATUS_ANEG_CPT); 974 975 /* Start the 10 second timer */ 976 callout_reset(&sc->sc_tick_ch, hz * 10, gem_tick, sc); 977 } 978 979 /* 980 * Stop PCS 981 */ 982 void 983 gem_pcs_stop(struct gem_softc *sc, int disable) 984 { 985 bus_space_tag_t t = sc->sc_bustag; 986 bus_space_handle_t h = sc->sc_h1; 987 988 #ifdef GEM_DEBUG 989 aprint_debug_dev(&sc->sc_dev, "gem_pcs_stop()\n"); 990 #endif 991 992 /* Tell link partner that we're going away */ 993 bus_space_write_4(t, h, GEM_MII_ANAR, GEM_MII_ANEG_RF); 994 995 /* 996 * Disable PCS MII. The documentation suggests that setting 997 * GEM_MII_CONFIG_ENABLE to zero and then restarting auto- 998 * negotiation will shut down the link. However, it appears 999 * that we also need to unset the datapath mode. 1000 */ 1001 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 1002 bus_space_write_4(t, h, GEM_MII_CONTROL, 1003 GEM_MII_CONTROL_AUTONEG | GEM_MII_CONTROL_RAN); 1004 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, GEM_MII_DATAPATH_MII); 1005 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 1006 1007 if (disable) { 1008 if (sc->sc_flags & GEM_SERDES) 1009 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 1010 GEM_MII_SLINK_POWER_OFF); 1011 else 1012 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 1013 GEM_MII_SLINK_LOOPBACK | GEM_MII_SLINK_POWER_OFF); 1014 } 1015 1016 sc->sc_flags &= ~GEM_LINK; 1017 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_NONE; 1018 sc->sc_mii.mii_media_status = IFM_AVALID; 1019 } 1020 1021 1022 /* 1023 * Initialization of interface; set up initialization block 1024 * and transmit/receive descriptor rings. 1025 */ 1026 int 1027 gem_init(struct ifnet *ifp) 1028 { 1029 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 1030 bus_space_tag_t t = sc->sc_bustag; 1031 bus_space_handle_t h = sc->sc_h1; 1032 int rc = 0, s; 1033 u_int max_frame_size; 1034 u_int32_t v; 1035 1036 s = splnet(); 1037 1038 DPRINTF(sc, ("%s: gem_init: calling stop\n", device_xname(&sc->sc_dev))); 1039 /* 1040 * Initialization sequence. The numbered steps below correspond 1041 * to the sequence outlined in section 6.3.5.1 in the Ethernet 1042 * Channel Engine manual (part of the PCIO manual). 1043 * See also the STP2002-STQ document from Sun Microsystems. 1044 */ 1045 1046 /* step 1 & 2. Reset the Ethernet Channel */ 1047 gem_stop(ifp, 0); 1048 gem_reset(sc); 1049 DPRINTF(sc, ("%s: gem_init: restarting\n", device_xname(&sc->sc_dev))); 1050 1051 /* Re-initialize the MIF */ 1052 gem_mifinit(sc); 1053 1054 /* Set up correct datapath for non-SERDES/Serialink */ 1055 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0 && 1056 sc->sc_variant != GEM_SUN_ERI) 1057 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 1058 GEM_MII_DATAPATH_MII); 1059 1060 /* Call MI reset function if any */ 1061 if (sc->sc_hwreset) 1062 (*sc->sc_hwreset)(sc); 1063 1064 /* step 3. Setup data structures in host memory */ 1065 if (gem_meminit(sc) != 0) 1066 return 1; 1067 1068 /* step 4. TX MAC registers & counters */ 1069 gem_init_regs(sc); 1070 max_frame_size = max(sc->sc_ethercom.ec_if.if_mtu, ETHERMTU); 1071 max_frame_size += ETHER_HDR_LEN + ETHER_CRC_LEN; 1072 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1073 max_frame_size += ETHER_VLAN_ENCAP_LEN; 1074 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 1075 max_frame_size|/* burst size */(0x2000<<16)); 1076 1077 /* step 5. RX MAC registers & counters */ 1078 gem_setladrf(sc); 1079 1080 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 1081 /* NOTE: we use only 32-bit DMA addresses here. */ 1082 bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 0); 1083 bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 1084 1085 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0); 1086 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 1087 1088 /* step 8. Global Configuration & Interrupt Mask */ 1089 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 1090 v = GEM_INTR_PCS; 1091 else 1092 v = GEM_INTR_MIF; 1093 bus_space_write_4(t, h, GEM_INTMASK, 1094 ~(GEM_INTR_TX_INTME | 1095 GEM_INTR_TX_EMPTY | 1096 GEM_INTR_TX_MAC | 1097 GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF| 1098 GEM_INTR_RX_TAG_ERR | GEM_INTR_MAC_CONTROL| 1099 GEM_INTR_BERR | v)); 1100 bus_space_write_4(t, h, GEM_MAC_RX_MASK, 1101 GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT); 1102 bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXX */ 1103 bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 1104 GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME); 1105 1106 /* step 9. ETX Configuration: use mostly default values */ 1107 1108 /* Enable TX DMA */ 1109 v = gem_ringsize(GEM_NTXDESC /*XXX*/); 1110 bus_space_write_4(t, h, GEM_TX_CONFIG, 1111 v|GEM_TX_CONFIG_TXDMA_EN| 1112 ((0x4FF<<10)&GEM_TX_CONFIG_TXFIFO_TH)); 1113 bus_space_write_4(t, h, GEM_TX_KICK, sc->sc_txnext); 1114 1115 /* step 10. ERX Configuration */ 1116 gem_rx_common(sc); 1117 1118 /* step 11. Configure Media */ 1119 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0 && 1120 (rc = mii_ifmedia_change(&sc->sc_mii)) != 0) 1121 goto out; 1122 1123 /* step 12. RX_MAC Configuration Register */ 1124 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 1125 v |= GEM_MAC_RX_ENABLE | GEM_MAC_RX_STRIP_CRC; 1126 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 1127 1128 /* step 14. Issue Transmit Pending command */ 1129 1130 /* Call MI initialization function if any */ 1131 if (sc->sc_hwinit) 1132 (*sc->sc_hwinit)(sc); 1133 1134 1135 /* step 15. Give the reciever a swift kick */ 1136 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4); 1137 1138 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 1139 /* Configure PCS */ 1140 gem_pcs_start(sc); 1141 else 1142 /* Start the one second timer. */ 1143 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 1144 1145 sc->sc_flags &= ~GEM_LINK; 1146 ifp->if_flags |= IFF_RUNNING; 1147 ifp->if_flags &= ~IFF_OACTIVE; 1148 ifp->if_timer = 0; 1149 sc->sc_if_flags = ifp->if_flags; 1150 out: 1151 splx(s); 1152 1153 return (0); 1154 } 1155 1156 void 1157 gem_init_regs(struct gem_softc *sc) 1158 { 1159 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1160 bus_space_tag_t t = sc->sc_bustag; 1161 bus_space_handle_t h = sc->sc_h1; 1162 const u_char *laddr = CLLADDR(ifp->if_sadl); 1163 u_int32_t v; 1164 1165 /* These regs are not cleared on reset */ 1166 if (!sc->sc_inited) { 1167 1168 /* Load recommended values */ 1169 bus_space_write_4(t, h, GEM_MAC_IPG0, 0x00); 1170 bus_space_write_4(t, h, GEM_MAC_IPG1, 0x08); 1171 bus_space_write_4(t, h, GEM_MAC_IPG2, 0x04); 1172 1173 bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 1174 /* Max frame and max burst size */ 1175 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 1176 ETHER_MAX_LEN | (0x2000<<16)); 1177 1178 bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x07); 1179 bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x04); 1180 bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10); 1181 bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088); 1182 bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED, 1183 ((laddr[5]<<8)|laddr[4])&0x3ff); 1184 1185 /* Secondary MAC addr set to 0:0:0:0:0:0 */ 1186 bus_space_write_4(t, h, GEM_MAC_ADDR3, 0); 1187 bus_space_write_4(t, h, GEM_MAC_ADDR4, 0); 1188 bus_space_write_4(t, h, GEM_MAC_ADDR5, 0); 1189 1190 /* MAC control addr set to 01:80:c2:00:00:01 */ 1191 bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001); 1192 bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200); 1193 bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180); 1194 1195 /* MAC filter addr set to 0:0:0:0:0:0 */ 1196 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0); 1197 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0); 1198 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0); 1199 1200 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0); 1201 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0); 1202 1203 sc->sc_inited = 1; 1204 } 1205 1206 /* Counters need to be zeroed */ 1207 bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0); 1208 bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0); 1209 bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0); 1210 bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0); 1211 bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0); 1212 bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0); 1213 bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0); 1214 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 1215 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 1216 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 1217 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 1218 1219 /* Set XOFF PAUSE time. */ 1220 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); 1221 1222 /* 1223 * Set the internal arbitration to "infinite" bursts of the 1224 * maximum length of 31 * 64 bytes so DMA transfers aren't 1225 * split up in cache line size chunks. This greatly improves 1226 * especially RX performance. 1227 * Enable silicon bug workarounds for the Apple variants. 1228 */ 1229 bus_space_write_4(t, h, GEM_CONFIG, 1230 GEM_CONFIG_TXDMA_LIMIT | GEM_CONFIG_RXDMA_LIMIT | 1231 ((sc->sc_flags & GEM_PCI) ? 1232 GEM_CONFIG_BURST_INF : GEM_CONFIG_BURST_64) | (GEM_IS_APPLE(sc) ? 1233 GEM_CONFIG_RONPAULBIT | GEM_CONFIG_BUG2FIX : 0)); 1234 1235 /* 1236 * Set the station address. 1237 */ 1238 bus_space_write_4(t, h, GEM_MAC_ADDR0, (laddr[4]<<8)|laddr[5]); 1239 bus_space_write_4(t, h, GEM_MAC_ADDR1, (laddr[2]<<8)|laddr[3]); 1240 bus_space_write_4(t, h, GEM_MAC_ADDR2, (laddr[0]<<8)|laddr[1]); 1241 1242 /* 1243 * Enable MII outputs. Enable GMII if there is a gigabit PHY. 1244 */ 1245 sc->sc_mif_config = bus_space_read_4(t, h, GEM_MIF_CONFIG); 1246 v = GEM_MAC_XIF_TX_MII_ENA; 1247 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) { 1248 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) { 1249 v |= GEM_MAC_XIF_FDPLX_LED; 1250 if (sc->sc_flags & GEM_GIGABIT) 1251 v |= GEM_MAC_XIF_GMII_MODE; 1252 } 1253 } else { 1254 v |= GEM_MAC_XIF_GMII_MODE; 1255 } 1256 bus_space_write_4(t, h, GEM_MAC_XIF_CONFIG, v); 1257 } 1258 1259 #ifdef GEM_DEBUG 1260 static void 1261 gem_txsoft_print(const struct gem_softc *sc, int firstdesc, int lastdesc) 1262 { 1263 int i; 1264 1265 for (i = firstdesc;; i = GEM_NEXTTX(i)) { 1266 printf("descriptor %d:\t", i); 1267 printf("gd_flags: 0x%016" PRIx64 "\t", 1268 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags)); 1269 printf("gd_addr: 0x%016" PRIx64 "\n", 1270 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr)); 1271 if (i == lastdesc) 1272 break; 1273 } 1274 } 1275 #endif 1276 1277 static void 1278 gem_start(struct ifnet *ifp) 1279 { 1280 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 1281 struct mbuf *m0, *m; 1282 struct gem_txsoft *txs; 1283 bus_dmamap_t dmamap; 1284 int error, firsttx, nexttx = -1, lasttx = -1, ofree, seg; 1285 uint64_t flags = 0; 1286 1287 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1288 return; 1289 1290 /* 1291 * Remember the previous number of free descriptors and 1292 * the first descriptor we'll use. 1293 */ 1294 ofree = sc->sc_txfree; 1295 firsttx = sc->sc_txnext; 1296 1297 DPRINTF(sc, ("%s: gem_start: txfree %d, txnext %d\n", 1298 device_xname(&sc->sc_dev), ofree, firsttx)); 1299 1300 /* 1301 * Loop through the send queue, setting up transmit descriptors 1302 * until we drain the queue, or use up all available transmit 1303 * descriptors. 1304 */ 1305 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 1306 sc->sc_txfree != 0) { 1307 /* 1308 * Grab a packet off the queue. 1309 */ 1310 IFQ_POLL(&ifp->if_snd, m0); 1311 if (m0 == NULL) 1312 break; 1313 m = NULL; 1314 1315 dmamap = txs->txs_dmamap; 1316 1317 /* 1318 * Load the DMA map. If this fails, the packet either 1319 * didn't fit in the alloted number of segments, or we were 1320 * short on resources. In this case, we'll copy and try 1321 * again. 1322 */ 1323 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m0, 1324 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0 || 1325 (m0->m_pkthdr.len < ETHER_MIN_TX && 1326 dmamap->dm_nsegs == GEM_NTXSEGS)) { 1327 if (m0->m_pkthdr.len > MCLBYTES) { 1328 aprint_error_dev(&sc->sc_dev, "unable to allocate jumbo Tx " 1329 "cluster\n"); 1330 IFQ_DEQUEUE(&ifp->if_snd, m0); 1331 m_freem(m0); 1332 continue; 1333 } 1334 MGETHDR(m, M_DONTWAIT, MT_DATA); 1335 if (m == NULL) { 1336 aprint_error_dev(&sc->sc_dev, "unable to allocate Tx mbuf\n"); 1337 break; 1338 } 1339 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1340 if (m0->m_pkthdr.len > MHLEN) { 1341 MCLGET(m, M_DONTWAIT); 1342 if ((m->m_flags & M_EXT) == 0) { 1343 aprint_error_dev(&sc->sc_dev, "unable to allocate Tx " 1344 "cluster\n"); 1345 m_freem(m); 1346 break; 1347 } 1348 } 1349 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1350 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1351 error = bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, 1352 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1353 if (error) { 1354 aprint_error_dev(&sc->sc_dev, "unable to load Tx buffer, " 1355 "error = %d\n", error); 1356 break; 1357 } 1358 } 1359 1360 /* 1361 * Ensure we have enough descriptors free to describe 1362 * the packet. 1363 */ 1364 if (dmamap->dm_nsegs > ((m0->m_pkthdr.len < ETHER_MIN_TX) ? 1365 (sc->sc_txfree - 1) : sc->sc_txfree)) { 1366 /* 1367 * Not enough free descriptors to transmit this 1368 * packet. We haven't committed to anything yet, 1369 * so just unload the DMA map, put the packet 1370 * back on the queue, and punt. Notify the upper 1371 * layer that there are no more slots left. 1372 * 1373 * XXX We could allocate an mbuf and copy, but 1374 * XXX it is worth it? 1375 */ 1376 ifp->if_flags |= IFF_OACTIVE; 1377 sc->sc_if_flags = ifp->if_flags; 1378 bus_dmamap_unload(sc->sc_dmatag, dmamap); 1379 if (m != NULL) 1380 m_freem(m); 1381 break; 1382 } 1383 1384 IFQ_DEQUEUE(&ifp->if_snd, m0); 1385 if (m != NULL) { 1386 m_freem(m0); 1387 m0 = m; 1388 } 1389 1390 /* 1391 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1392 */ 1393 1394 /* Sync the DMA map. */ 1395 bus_dmamap_sync(sc->sc_dmatag, dmamap, 0, dmamap->dm_mapsize, 1396 BUS_DMASYNC_PREWRITE); 1397 1398 /* 1399 * Initialize the transmit descriptors. 1400 */ 1401 for (nexttx = sc->sc_txnext, seg = 0; 1402 seg < dmamap->dm_nsegs; 1403 seg++, nexttx = GEM_NEXTTX(nexttx)) { 1404 1405 /* 1406 * If this is the first descriptor we're 1407 * enqueueing, set the start of packet flag, 1408 * and the checksum stuff if we want the hardware 1409 * to do it. 1410 */ 1411 sc->sc_txdescs[nexttx].gd_addr = 1412 GEM_DMA_WRITE(sc, dmamap->dm_segs[seg].ds_addr); 1413 flags = dmamap->dm_segs[seg].ds_len & GEM_TD_BUFSIZE; 1414 if (nexttx == firsttx) { 1415 flags |= GEM_TD_START_OF_PACKET; 1416 if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) { 1417 sc->sc_txwin = 0; 1418 flags |= GEM_TD_INTERRUPT_ME; 1419 } 1420 1421 #ifdef INET 1422 /* h/w checksum */ 1423 if (ifp->if_csum_flags_tx & M_CSUM_TCPv4 && 1424 m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1425 struct ether_header *eh; 1426 uint16_t offset, start; 1427 1428 eh = mtod(m0, struct ether_header *); 1429 switch (ntohs(eh->ether_type)) { 1430 case ETHERTYPE_IP: 1431 start = ETHER_HDR_LEN; 1432 break; 1433 case ETHERTYPE_VLAN: 1434 start = ETHER_HDR_LEN + 1435 ETHER_VLAN_ENCAP_LEN; 1436 break; 1437 default: 1438 /* unsupported, drop it */ 1439 m_free(m0); 1440 continue; 1441 } 1442 start += M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 1443 offset = M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data) + start; 1444 flags |= (start << 1445 GEM_TD_CXSUM_STARTSHFT) | 1446 (offset << 1447 GEM_TD_CXSUM_STUFFSHFT) | 1448 GEM_TD_CXSUM_ENABLE; 1449 } 1450 #endif 1451 } 1452 if (seg == dmamap->dm_nsegs - 1) { 1453 flags |= GEM_TD_END_OF_PACKET; 1454 } else { 1455 /* last flag set outside of loop */ 1456 sc->sc_txdescs[nexttx].gd_flags = 1457 GEM_DMA_WRITE(sc, flags); 1458 } 1459 lasttx = nexttx; 1460 } 1461 if (m0->m_pkthdr.len < ETHER_MIN_TX) { 1462 /* add padding buffer at end of chain */ 1463 flags &= ~GEM_TD_END_OF_PACKET; 1464 sc->sc_txdescs[lasttx].gd_flags = 1465 GEM_DMA_WRITE(sc, flags); 1466 1467 sc->sc_txdescs[nexttx].gd_addr = 1468 GEM_DMA_WRITE(sc, 1469 sc->sc_nulldmamap->dm_segs[0].ds_addr); 1470 flags = ((ETHER_MIN_TX - m0->m_pkthdr.len) & 1471 GEM_TD_BUFSIZE) | GEM_TD_END_OF_PACKET; 1472 lasttx = nexttx; 1473 nexttx = GEM_NEXTTX(nexttx); 1474 seg++; 1475 } 1476 sc->sc_txdescs[lasttx].gd_flags = GEM_DMA_WRITE(sc, flags); 1477 1478 KASSERT(lasttx != -1); 1479 1480 /* 1481 * Store a pointer to the packet so we can free it later, 1482 * and remember what txdirty will be once the packet is 1483 * done. 1484 */ 1485 txs->txs_mbuf = m0; 1486 txs->txs_firstdesc = sc->sc_txnext; 1487 txs->txs_lastdesc = lasttx; 1488 txs->txs_ndescs = seg; 1489 1490 #ifdef GEM_DEBUG 1491 if (ifp->if_flags & IFF_DEBUG) { 1492 printf(" gem_start %p transmit chain:\n", txs); 1493 gem_txsoft_print(sc, txs->txs_firstdesc, 1494 txs->txs_lastdesc); 1495 } 1496 #endif 1497 1498 /* Sync the descriptors we're using. */ 1499 GEM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndescs, 1500 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1501 1502 /* Advance the tx pointer. */ 1503 sc->sc_txfree -= txs->txs_ndescs; 1504 sc->sc_txnext = nexttx; 1505 1506 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1507 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1508 1509 #if NBPFILTER > 0 1510 /* 1511 * Pass the packet to any BPF listeners. 1512 */ 1513 if (ifp->if_bpf) 1514 bpf_mtap(ifp->if_bpf, m0); 1515 #endif /* NBPFILTER > 0 */ 1516 } 1517 1518 if (txs == NULL || sc->sc_txfree == 0) { 1519 /* No more slots left; notify upper layer. */ 1520 ifp->if_flags |= IFF_OACTIVE; 1521 sc->sc_if_flags = ifp->if_flags; 1522 } 1523 1524 if (sc->sc_txfree != ofree) { 1525 DPRINTF(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 1526 device_xname(&sc->sc_dev), lasttx, firsttx)); 1527 /* 1528 * The entire packet chain is set up. 1529 * Kick the transmitter. 1530 */ 1531 DPRINTF(sc, ("%s: gem_start: kicking tx %d\n", 1532 device_xname(&sc->sc_dev), nexttx)); 1533 bus_space_write_4(sc->sc_bustag, sc->sc_h1, GEM_TX_KICK, 1534 sc->sc_txnext); 1535 1536 /* Set a watchdog timer in case the chip flakes out. */ 1537 ifp->if_timer = 5; 1538 DPRINTF(sc, ("%s: gem_start: watchdog %d\n", 1539 device_xname(&sc->sc_dev), ifp->if_timer)); 1540 } 1541 } 1542 1543 /* 1544 * Transmit interrupt. 1545 */ 1546 int 1547 gem_tint(struct gem_softc *sc) 1548 { 1549 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1550 bus_space_tag_t t = sc->sc_bustag; 1551 bus_space_handle_t mac = sc->sc_h1; 1552 struct gem_txsoft *txs; 1553 int txlast; 1554 int progress = 0; 1555 u_int32_t v; 1556 1557 DPRINTF(sc, ("%s: gem_tint\n", device_xname(&sc->sc_dev))); 1558 1559 /* Unload collision counters ... */ 1560 v = bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) + 1561 bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT); 1562 ifp->if_collisions += v + 1563 bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) + 1564 bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT); 1565 ifp->if_oerrors += v; 1566 1567 /* ... then clear the hardware counters. */ 1568 bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0); 1569 bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0); 1570 bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0); 1571 bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0); 1572 1573 /* 1574 * Go through our Tx list and free mbufs for those 1575 * frames that have been transmitted. 1576 */ 1577 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1578 /* 1579 * In theory, we could harvest some descriptors before 1580 * the ring is empty, but that's a bit complicated. 1581 * 1582 * GEM_TX_COMPLETION points to the last descriptor 1583 * processed +1. 1584 * 1585 * Let's assume that the NIC writes back to the Tx 1586 * descriptors before it updates the completion 1587 * register. If the NIC has posted writes to the 1588 * Tx descriptors, PCI ordering requires that the 1589 * posted writes flush to RAM before the register-read 1590 * finishes. So let's read the completion register, 1591 * before syncing the descriptors, so that we 1592 * examine Tx descriptors that are at least as 1593 * current as the completion register. 1594 */ 1595 txlast = bus_space_read_4(t, mac, GEM_TX_COMPLETION); 1596 DPRINTF(sc, 1597 ("gem_tint: txs->txs_lastdesc = %d, txlast = %d\n", 1598 txs->txs_lastdesc, txlast)); 1599 if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1600 if (txlast >= txs->txs_firstdesc && 1601 txlast <= txs->txs_lastdesc) 1602 break; 1603 } else if (txlast >= txs->txs_firstdesc || 1604 txlast <= txs->txs_lastdesc) 1605 break; 1606 1607 GEM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndescs, 1608 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1609 1610 #ifdef GEM_DEBUG /* XXX DMA synchronization? */ 1611 if (ifp->if_flags & IFF_DEBUG) { 1612 printf(" txsoft %p transmit chain:\n", txs); 1613 gem_txsoft_print(sc, txs->txs_firstdesc, 1614 txs->txs_lastdesc); 1615 } 1616 #endif 1617 1618 1619 DPRINTF(sc, ("gem_tint: releasing a desc\n")); 1620 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1621 1622 sc->sc_txfree += txs->txs_ndescs; 1623 1624 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 1625 0, txs->txs_dmamap->dm_mapsize, 1626 BUS_DMASYNC_POSTWRITE); 1627 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 1628 if (txs->txs_mbuf != NULL) { 1629 m_freem(txs->txs_mbuf); 1630 txs->txs_mbuf = NULL; 1631 } 1632 1633 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1634 1635 ifp->if_opackets++; 1636 progress = 1; 1637 } 1638 1639 #if 0 1640 DPRINTF(sc, ("gem_tint: GEM_TX_STATE_MACHINE %x " 1641 "GEM_TX_DATA_PTR %" PRIx64 "GEM_TX_COMPLETION %" PRIx32 "\n", 1642 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_TX_STATE_MACHINE), 1643 ((uint64_t)bus_space_read_4(sc->sc_bustag, sc->sc_h1, 1644 GEM_TX_DATA_PTR_HI) << 32) | 1645 bus_space_read_4(sc->sc_bustag, sc->sc_h1, 1646 GEM_TX_DATA_PTR_LO), 1647 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_TX_COMPLETION))); 1648 #endif 1649 1650 if (progress) { 1651 if (sc->sc_txfree == GEM_NTXDESC - 1) 1652 sc->sc_txwin = 0; 1653 1654 /* Freed some descriptors, so reset IFF_OACTIVE and restart. */ 1655 ifp->if_flags &= ~IFF_OACTIVE; 1656 sc->sc_if_flags = ifp->if_flags; 1657 ifp->if_timer = SIMPLEQ_EMPTY(&sc->sc_txdirtyq) ? 0 : 5; 1658 gem_start(ifp); 1659 } 1660 DPRINTF(sc, ("%s: gem_tint: watchdog %d\n", 1661 device_xname(&sc->sc_dev), ifp->if_timer)); 1662 1663 return (1); 1664 } 1665 1666 /* 1667 * Receive interrupt. 1668 */ 1669 int 1670 gem_rint(struct gem_softc *sc) 1671 { 1672 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1673 bus_space_tag_t t = sc->sc_bustag; 1674 bus_space_handle_t h = sc->sc_h1; 1675 struct gem_rxsoft *rxs; 1676 struct mbuf *m; 1677 u_int64_t rxstat; 1678 u_int32_t rxcomp; 1679 int i, len, progress = 0; 1680 1681 DPRINTF(sc, ("%s: gem_rint\n", device_xname(&sc->sc_dev))); 1682 1683 /* 1684 * Ignore spurious interrupt that sometimes occurs before 1685 * we are set up when we network boot. 1686 */ 1687 if (!sc->sc_meminited) 1688 return 1; 1689 1690 /* 1691 * Read the completion register once. This limits 1692 * how long the following loop can execute. 1693 */ 1694 rxcomp = bus_space_read_4(t, h, GEM_RX_COMPLETION); 1695 1696 /* 1697 * XXX Read the lastrx only once at the top for speed. 1698 */ 1699 DPRINTF(sc, ("gem_rint: sc->rxptr %d, complete %d\n", 1700 sc->sc_rxptr, rxcomp)); 1701 1702 /* 1703 * Go into the loop at least once. 1704 */ 1705 for (i = sc->sc_rxptr; i == sc->sc_rxptr || i != rxcomp; 1706 i = GEM_NEXTRX(i)) { 1707 rxs = &sc->sc_rxsoft[i]; 1708 1709 GEM_CDRXSYNC(sc, i, 1710 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1711 1712 rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags); 1713 1714 if (rxstat & GEM_RD_OWN) { 1715 GEM_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); 1716 /* 1717 * We have processed all of the receive buffers. 1718 */ 1719 break; 1720 } 1721 1722 progress++; 1723 ifp->if_ipackets++; 1724 1725 if (rxstat & GEM_RD_BAD_CRC) { 1726 ifp->if_ierrors++; 1727 aprint_error_dev(&sc->sc_dev, "receive error: CRC error\n"); 1728 GEM_INIT_RXDESC(sc, i); 1729 continue; 1730 } 1731 1732 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1733 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1734 #ifdef GEM_DEBUG 1735 if (ifp->if_flags & IFF_DEBUG) { 1736 printf(" rxsoft %p descriptor %d: ", rxs, i); 1737 printf("gd_flags: 0x%016llx\t", (long long) 1738 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags)); 1739 printf("gd_addr: 0x%016llx\n", (long long) 1740 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr)); 1741 } 1742 #endif 1743 1744 /* No errors; receive the packet. */ 1745 len = GEM_RD_BUFLEN(rxstat); 1746 1747 /* 1748 * Allocate a new mbuf cluster. If that fails, we are 1749 * out of memory, and must drop the packet and recycle 1750 * the buffer that's already attached to this descriptor. 1751 */ 1752 m = rxs->rxs_mbuf; 1753 if (gem_add_rxbuf(sc, i) != 0) { 1754 GEM_COUNTER_INCR(sc, sc_ev_rxnobuf); 1755 ifp->if_ierrors++; 1756 GEM_INIT_RXDESC(sc, i); 1757 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1758 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1759 continue; 1760 } 1761 m->m_data += 2; /* We're already off by two */ 1762 1763 m->m_pkthdr.rcvif = ifp; 1764 m->m_pkthdr.len = m->m_len = len; 1765 1766 #if NBPFILTER > 0 1767 /* 1768 * Pass this up to any BPF listeners, but only 1769 * pass it up the stack if it's for us. 1770 */ 1771 if (ifp->if_bpf) 1772 bpf_mtap(ifp->if_bpf, m); 1773 #endif /* NBPFILTER > 0 */ 1774 1775 #ifdef INET 1776 /* hardware checksum */ 1777 if (ifp->if_csum_flags_rx & M_CSUM_TCPv4) { 1778 struct ether_header *eh; 1779 struct ip *ip; 1780 int32_t hlen, pktlen; 1781 1782 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1783 pktlen = m->m_pkthdr.len - ETHER_HDR_LEN - 1784 ETHER_VLAN_ENCAP_LEN; 1785 eh = (struct ether_header *) (mtod(m, char *) + 1786 ETHER_VLAN_ENCAP_LEN); 1787 } else { 1788 pktlen = m->m_pkthdr.len - ETHER_HDR_LEN; 1789 eh = mtod(m, struct ether_header *); 1790 } 1791 if (ntohs(eh->ether_type) != ETHERTYPE_IP) 1792 goto swcsum; 1793 ip = (struct ip *) ((char *)eh + ETHER_HDR_LEN); 1794 1795 /* IPv4 only */ 1796 if (ip->ip_v != IPVERSION) 1797 goto swcsum; 1798 1799 hlen = ip->ip_hl << 2; 1800 if (hlen < sizeof(struct ip)) 1801 goto swcsum; 1802 1803 /* 1804 * bail if too short, has random trailing garbage, 1805 * truncated, fragment, or has ethernet pad. 1806 */ 1807 if ((ntohs(ip->ip_len) < hlen) || 1808 (ntohs(ip->ip_len) != pktlen) || 1809 (ntohs(ip->ip_off) & (IP_MF | IP_OFFMASK))) 1810 goto swcsum; 1811 1812 switch (ip->ip_p) { 1813 case IPPROTO_TCP: 1814 if (! (ifp->if_csum_flags_rx & M_CSUM_TCPv4)) 1815 goto swcsum; 1816 if (pktlen < (hlen + sizeof(struct tcphdr))) 1817 goto swcsum; 1818 m->m_pkthdr.csum_flags = M_CSUM_TCPv4; 1819 break; 1820 case IPPROTO_UDP: 1821 /* FALLTHROUGH */ 1822 default: 1823 goto swcsum; 1824 } 1825 1826 /* the uncomplemented sum is expected */ 1827 m->m_pkthdr.csum_data = (~rxstat) & GEM_RD_CHECKSUM; 1828 1829 /* if the pkt had ip options, we have to deduct them */ 1830 if (hlen > sizeof(struct ip)) { 1831 uint16_t *opts; 1832 uint32_t optsum, temp; 1833 1834 optsum = 0; 1835 temp = hlen - sizeof(struct ip); 1836 opts = (uint16_t *) ((char *) ip + 1837 sizeof(struct ip)); 1838 1839 while (temp > 1) { 1840 optsum += ntohs(*opts++); 1841 temp -= 2; 1842 } 1843 while (optsum >> 16) 1844 optsum = (optsum >> 16) + 1845 (optsum & 0xffff); 1846 1847 /* Deduct ip opts sum from hwsum. */ 1848 m->m_pkthdr.csum_data += (uint16_t)~optsum; 1849 1850 while (m->m_pkthdr.csum_data >> 16) 1851 m->m_pkthdr.csum_data = 1852 (m->m_pkthdr.csum_data >> 16) + 1853 (m->m_pkthdr.csum_data & 1854 0xffff); 1855 } 1856 1857 m->m_pkthdr.csum_flags |= M_CSUM_DATA | 1858 M_CSUM_NO_PSEUDOHDR; 1859 } else 1860 swcsum: 1861 m->m_pkthdr.csum_flags = 0; 1862 #endif 1863 /* Pass it on. */ 1864 (*ifp->if_input)(ifp, m); 1865 } 1866 1867 if (progress) { 1868 /* Update the receive pointer. */ 1869 if (i == sc->sc_rxptr) { 1870 GEM_COUNTER_INCR(sc, sc_ev_rxfull); 1871 #ifdef GEM_DEBUG 1872 if (ifp->if_flags & IFF_DEBUG) 1873 printf("%s: rint: ring wrap\n", 1874 device_xname(&sc->sc_dev)); 1875 #endif 1876 } 1877 sc->sc_rxptr = i; 1878 bus_space_write_4(t, h, GEM_RX_KICK, GEM_PREVRX(i)); 1879 } 1880 #ifdef GEM_COUNTERS 1881 if (progress <= 4) { 1882 GEM_COUNTER_INCR(sc, sc_ev_rxhist[progress]); 1883 } else if (progress < 32) { 1884 if (progress < 16) 1885 GEM_COUNTER_INCR(sc, sc_ev_rxhist[5]); 1886 else 1887 GEM_COUNTER_INCR(sc, sc_ev_rxhist[6]); 1888 1889 } else { 1890 if (progress < 64) 1891 GEM_COUNTER_INCR(sc, sc_ev_rxhist[7]); 1892 else 1893 GEM_COUNTER_INCR(sc, sc_ev_rxhist[8]); 1894 } 1895 #endif 1896 1897 DPRINTF(sc, ("gem_rint: done sc->rxptr %d, complete %d\n", 1898 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION))); 1899 1900 /* Read error counters ... */ 1901 ifp->if_ierrors += 1902 bus_space_read_4(t, h, GEM_MAC_RX_LEN_ERR_CNT) + 1903 bus_space_read_4(t, h, GEM_MAC_RX_ALIGN_ERR) + 1904 bus_space_read_4(t, h, GEM_MAC_RX_CRC_ERR_CNT) + 1905 bus_space_read_4(t, h, GEM_MAC_RX_CODE_VIOL); 1906 1907 /* ... then clear the hardware counters. */ 1908 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 1909 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 1910 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 1911 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 1912 1913 return (1); 1914 } 1915 1916 1917 /* 1918 * gem_add_rxbuf: 1919 * 1920 * Add a receive buffer to the indicated descriptor. 1921 */ 1922 int 1923 gem_add_rxbuf(struct gem_softc *sc, int idx) 1924 { 1925 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1926 struct mbuf *m; 1927 int error; 1928 1929 MGETHDR(m, M_DONTWAIT, MT_DATA); 1930 if (m == NULL) 1931 return (ENOBUFS); 1932 1933 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1934 MCLGET(m, M_DONTWAIT); 1935 if ((m->m_flags & M_EXT) == 0) { 1936 m_freem(m); 1937 return (ENOBUFS); 1938 } 1939 1940 #ifdef GEM_DEBUG 1941 /* bzero the packet to check DMA */ 1942 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 1943 #endif 1944 1945 if (rxs->rxs_mbuf != NULL) 1946 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 1947 1948 rxs->rxs_mbuf = m; 1949 1950 error = bus_dmamap_load(sc->sc_dmatag, rxs->rxs_dmamap, 1951 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1952 BUS_DMA_READ|BUS_DMA_NOWAIT); 1953 if (error) { 1954 aprint_error_dev(&sc->sc_dev, "can't load rx DMA map %d, error = %d\n", 1955 idx, error); 1956 panic("gem_add_rxbuf"); /* XXX */ 1957 } 1958 1959 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1960 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1961 1962 GEM_INIT_RXDESC(sc, idx); 1963 1964 return (0); 1965 } 1966 1967 1968 int 1969 gem_eint(struct gem_softc *sc, u_int status) 1970 { 1971 char bits[128]; 1972 u_int32_t r, v; 1973 1974 if ((status & GEM_INTR_MIF) != 0) { 1975 printf("%s: XXXlink status changed\n", device_xname(&sc->sc_dev)); 1976 return (1); 1977 } 1978 1979 if ((status & GEM_INTR_RX_TAG_ERR) != 0) { 1980 gem_reset_rxdma(sc); 1981 return (1); 1982 } 1983 1984 if (status & GEM_INTR_BERR) { 1985 if (sc->sc_flags & GEM_PCI) 1986 r = GEM_ERROR_STATUS; 1987 else 1988 r = GEM_SBUS_ERROR_STATUS; 1989 bus_space_read_4(sc->sc_bustag, sc->sc_h2, r); 1990 v = bus_space_read_4(sc->sc_bustag, sc->sc_h2, r); 1991 aprint_error_dev(&sc->sc_dev, "bus error interrupt: 0x%02x\n", 1992 v); 1993 return (1); 1994 } 1995 snprintb(bits, sizeof(bits), GEM_INTR_BITS, status); 1996 printf("%s: status=%s\n", device_xname(&sc->sc_dev), bits); 1997 1998 return (1); 1999 } 2000 2001 2002 /* 2003 * PCS interrupts. 2004 * We should receive these when the link status changes, but sometimes 2005 * we don't receive them for link up. We compensate for this in the 2006 * gem_tick() callout. 2007 */ 2008 int 2009 gem_pint(struct gem_softc *sc) 2010 { 2011 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2012 bus_space_tag_t t = sc->sc_bustag; 2013 bus_space_handle_t h = sc->sc_h1; 2014 u_int32_t v, v2; 2015 2016 /* 2017 * Clear the PCS interrupt from GEM_STATUS. The PCS register is 2018 * latched, so we have to read it twice. There is only one bit in 2019 * use, so the value is meaningless. 2020 */ 2021 bus_space_read_4(t, h, GEM_MII_INTERRUP_STATUS); 2022 bus_space_read_4(t, h, GEM_MII_INTERRUP_STATUS); 2023 2024 if ((ifp->if_flags & IFF_UP) == 0) 2025 return 1; 2026 2027 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) 2028 return 1; 2029 2030 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2031 /* If we see remote fault, our link partner is probably going away */ 2032 if ((v & GEM_MII_STATUS_REM_FLT) != 0) { 2033 gem_bitwait(sc, h, GEM_MII_STATUS, GEM_MII_STATUS_REM_FLT, 0); 2034 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2035 /* Otherwise, we may need to wait after auto-negotiation completes */ 2036 } else if ((v & (GEM_MII_STATUS_LINK_STS | GEM_MII_STATUS_ANEG_CPT)) == 2037 GEM_MII_STATUS_ANEG_CPT) { 2038 gem_bitwait(sc, h, GEM_MII_STATUS, 0, GEM_MII_STATUS_LINK_STS); 2039 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2040 } 2041 if ((v & GEM_MII_STATUS_LINK_STS) != 0) { 2042 if (sc->sc_flags & GEM_LINK) { 2043 return 1; 2044 } 2045 callout_stop(&sc->sc_tick_ch); 2046 v = bus_space_read_4(t, h, GEM_MII_ANAR); 2047 v2 = bus_space_read_4(t, h, GEM_MII_ANLPAR); 2048 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_1000_SX; 2049 sc->sc_mii.mii_media_status = IFM_AVALID | IFM_ACTIVE; 2050 v &= v2; 2051 if (v & GEM_MII_ANEG_FUL_DUPLX) { 2052 sc->sc_mii.mii_media_active |= IFM_FDX; 2053 #ifdef GEM_DEBUG 2054 aprint_debug_dev(&sc->sc_dev, "link up: full duplex\n"); 2055 #endif 2056 } else if (v & GEM_MII_ANEG_HLF_DUPLX) { 2057 sc->sc_mii.mii_media_active |= IFM_HDX; 2058 #ifdef GEM_DEBUG 2059 aprint_debug_dev(&sc->sc_dev, "link up: half duplex\n"); 2060 #endif 2061 } else { 2062 #ifdef GEM_DEBUG 2063 aprint_debug_dev(&sc->sc_dev, "duplex mismatch\n"); 2064 #endif 2065 } 2066 gem_statuschange(sc); 2067 } else { 2068 if ((sc->sc_flags & GEM_LINK) == 0) { 2069 return 1; 2070 } 2071 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_NONE; 2072 sc->sc_mii.mii_media_status = IFM_AVALID; 2073 #ifdef GEM_DEBUG 2074 aprint_debug_dev(&sc->sc_dev, "link down\n"); 2075 #endif 2076 gem_statuschange(sc); 2077 2078 /* Start the 10 second timer */ 2079 callout_reset(&sc->sc_tick_ch, hz * 10, gem_tick, sc); 2080 } 2081 return 1; 2082 } 2083 2084 2085 2086 int 2087 gem_intr(void *v) 2088 { 2089 struct gem_softc *sc = (struct gem_softc *)v; 2090 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2091 bus_space_tag_t t = sc->sc_bustag; 2092 bus_space_handle_t h = sc->sc_h1; 2093 u_int32_t status; 2094 int r = 0; 2095 #ifdef GEM_DEBUG 2096 char bits[128]; 2097 #endif 2098 2099 /* XXX We should probably mask out interrupts until we're done */ 2100 2101 sc->sc_ev_intr.ev_count++; 2102 2103 status = bus_space_read_4(t, h, GEM_STATUS); 2104 #ifdef GEM_DEBUG 2105 snprintb(bits, sizeof(bits), GEM_INTR_BITS, status); 2106 #endif 2107 DPRINTF(sc, ("%s: gem_intr: cplt 0x%x status %s\n", 2108 device_xname(&sc->sc_dev), (status >> 19), bits)); 2109 2110 2111 if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0) 2112 r |= gem_eint(sc, status); 2113 2114 /* We don't bother with GEM_INTR_TX_DONE */ 2115 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) { 2116 GEM_COUNTER_INCR(sc, sc_ev_txint); 2117 r |= gem_tint(sc); 2118 } 2119 2120 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) { 2121 GEM_COUNTER_INCR(sc, sc_ev_rxint); 2122 r |= gem_rint(sc); 2123 } 2124 2125 /* We should eventually do more than just print out error stats. */ 2126 if (status & GEM_INTR_TX_MAC) { 2127 int txstat = bus_space_read_4(t, h, GEM_MAC_TX_STATUS); 2128 if (txstat & ~GEM_MAC_TX_XMIT_DONE) 2129 printf("%s: MAC tx fault, status %x\n", 2130 device_xname(&sc->sc_dev), txstat); 2131 if (txstat & (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG)) 2132 gem_init(ifp); 2133 } 2134 if (status & GEM_INTR_RX_MAC) { 2135 int rxstat = bus_space_read_4(t, h, GEM_MAC_RX_STATUS); 2136 /* 2137 * At least with GEM_SUN_GEM and some GEM_SUN_ERI 2138 * revisions GEM_MAC_RX_OVERFLOW happen often due to a 2139 * silicon bug so handle them silently. Moreover, it's 2140 * likely that the receiver has hung so we reset it. 2141 */ 2142 if (rxstat & GEM_MAC_RX_OVERFLOW) { 2143 ifp->if_ierrors++; 2144 gem_reset_rxdma(sc); 2145 } else if (rxstat & ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT)) 2146 printf("%s: MAC rx fault, status 0x%02x\n", 2147 device_xname(&sc->sc_dev), rxstat); 2148 } 2149 if (status & GEM_INTR_PCS) { 2150 r |= gem_pint(sc); 2151 } 2152 2153 /* Do we need to do anything with these? 2154 if ((status & GEM_MAC_CONTROL_STATUS) != 0) { 2155 status2 = bus_read_4(sc->sc_res[0], GEM_MAC_CONTROL_STATUS); 2156 if ((status2 & GEM_MAC_PAUSED) != 0) 2157 aprintf_debug_dev(&sc->sc_dev, "PAUSE received (%d slots)\n", 2158 GEM_MAC_PAUSE_TIME(status2)); 2159 if ((status2 & GEM_MAC_PAUSE) != 0) 2160 aprintf_debug_dev(&sc->sc_dev, "transited to PAUSE state\n"); 2161 if ((status2 & GEM_MAC_RESUME) != 0) 2162 aprintf_debug_dev(&sc->sc_dev, "transited to non-PAUSE state\n"); 2163 } 2164 if ((status & GEM_INTR_MIF) != 0) 2165 aprintf_debug_dev(&sc->sc_dev, "MIF interrupt\n"); 2166 */ 2167 #if NRND > 0 2168 rnd_add_uint32(&sc->rnd_source, status); 2169 #endif 2170 return (r); 2171 } 2172 2173 2174 void 2175 gem_watchdog(struct ifnet *ifp) 2176 { 2177 struct gem_softc *sc = ifp->if_softc; 2178 2179 DPRINTF(sc, ("gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x " 2180 "GEM_MAC_RX_CONFIG %x\n", 2181 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_RX_CONFIG), 2182 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_MAC_RX_STATUS), 2183 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_MAC_RX_CONFIG))); 2184 2185 log(LOG_ERR, "%s: device timeout\n", device_xname(&sc->sc_dev)); 2186 ++ifp->if_oerrors; 2187 2188 /* Try to get more packets going. */ 2189 gem_start(ifp); 2190 } 2191 2192 /* 2193 * Initialize the MII Management Interface 2194 */ 2195 void 2196 gem_mifinit(struct gem_softc *sc) 2197 { 2198 bus_space_tag_t t = sc->sc_bustag; 2199 bus_space_handle_t mif = sc->sc_h1; 2200 2201 /* Configure the MIF in frame mode */ 2202 sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 2203 sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA; 2204 bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config); 2205 } 2206 2207 /* 2208 * MII interface 2209 * 2210 * The GEM MII interface supports at least three different operating modes: 2211 * 2212 * Bitbang mode is implemented using data, clock and output enable registers. 2213 * 2214 * Frame mode is implemented by loading a complete frame into the frame 2215 * register and polling the valid bit for completion. 2216 * 2217 * Polling mode uses the frame register but completion is indicated by 2218 * an interrupt. 2219 * 2220 */ 2221 static int 2222 gem_mii_readreg(device_t self, int phy, int reg) 2223 { 2224 struct gem_softc *sc = (void *)self; 2225 bus_space_tag_t t = sc->sc_bustag; 2226 bus_space_handle_t mif = sc->sc_h1; 2227 int n; 2228 u_int32_t v; 2229 2230 #ifdef GEM_DEBUG1 2231 if (sc->sc_debug) 2232 printf("gem_mii_readreg: PHY %d reg %d\n", phy, reg); 2233 #endif 2234 2235 /* Construct the frame command */ 2236 v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) | 2237 GEM_MIF_FRAME_READ; 2238 2239 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 2240 for (n = 0; n < 100; n++) { 2241 DELAY(1); 2242 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 2243 if (v & GEM_MIF_FRAME_TA0) 2244 return (v & GEM_MIF_FRAME_DATA); 2245 } 2246 2247 printf("%s: mii_read timeout\n", device_xname(&sc->sc_dev)); 2248 return (0); 2249 } 2250 2251 static void 2252 gem_mii_writereg(device_t self, int phy, int reg, int val) 2253 { 2254 struct gem_softc *sc = (void *)self; 2255 bus_space_tag_t t = sc->sc_bustag; 2256 bus_space_handle_t mif = sc->sc_h1; 2257 int n; 2258 u_int32_t v; 2259 2260 #ifdef GEM_DEBUG1 2261 if (sc->sc_debug) 2262 printf("gem_mii_writereg: PHY %d reg %d val %x\n", 2263 phy, reg, val); 2264 #endif 2265 2266 /* Construct the frame command */ 2267 v = GEM_MIF_FRAME_WRITE | 2268 (phy << GEM_MIF_PHY_SHIFT) | 2269 (reg << GEM_MIF_REG_SHIFT) | 2270 (val & GEM_MIF_FRAME_DATA); 2271 2272 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 2273 for (n = 0; n < 100; n++) { 2274 DELAY(1); 2275 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 2276 if (v & GEM_MIF_FRAME_TA0) 2277 return; 2278 } 2279 2280 printf("%s: mii_write timeout\n", device_xname(&sc->sc_dev)); 2281 } 2282 2283 static void 2284 gem_mii_statchg(device_t dev) 2285 { 2286 struct gem_softc *sc = (void *)dev; 2287 #ifdef GEM_DEBUG 2288 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 2289 #endif 2290 2291 #ifdef GEM_DEBUG 2292 if (sc->sc_debug) 2293 printf("gem_mii_statchg: status change: phy = %d\n", 2294 sc->sc_phys[instance]); 2295 #endif 2296 gem_statuschange(sc); 2297 } 2298 2299 /* 2300 * Common status change for gem_mii_statchg() and gem_pint() 2301 */ 2302 void 2303 gem_statuschange(struct gem_softc* sc) 2304 { 2305 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2306 bus_space_tag_t t = sc->sc_bustag; 2307 bus_space_handle_t mac = sc->sc_h1; 2308 int gigabit; 2309 u_int32_t rxcfg, txcfg, v; 2310 2311 if ((sc->sc_mii.mii_media_status & IFM_ACTIVE) != 0 && 2312 IFM_SUBTYPE(sc->sc_mii.mii_media_active) != IFM_NONE) 2313 sc->sc_flags |= GEM_LINK; 2314 else 2315 sc->sc_flags &= ~GEM_LINK; 2316 2317 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 2318 gigabit = 1; 2319 else 2320 gigabit = 0; 2321 2322 /* 2323 * The configuration done here corresponds to the steps F) and 2324 * G) and as far as enabling of RX and TX MAC goes also step H) 2325 * of the initialization sequence outlined in section 3.2.1 of 2326 * the GEM Gigabit Ethernet ASIC Specification. 2327 */ 2328 2329 rxcfg = bus_space_read_4(t, mac, GEM_MAC_RX_CONFIG); 2330 rxcfg &= ~(GEM_MAC_RX_CARR_EXTEND | GEM_MAC_RX_ENABLE); 2331 txcfg = GEM_MAC_TX_ENA_IPG0 | GEM_MAC_TX_NGU | GEM_MAC_TX_NGU_LIMIT; 2332 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 2333 txcfg |= GEM_MAC_TX_IGN_CARRIER | GEM_MAC_TX_IGN_COLLIS; 2334 else if (gigabit) { 2335 rxcfg |= GEM_MAC_RX_CARR_EXTEND; 2336 txcfg |= GEM_MAC_RX_CARR_EXTEND; 2337 } 2338 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0); 2339 bus_space_barrier(t, mac, GEM_MAC_TX_CONFIG, 4, 2340 BUS_SPACE_BARRIER_WRITE); 2341 if (!gem_bitwait(sc, mac, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)) 2342 aprint_normal_dev(&sc->sc_dev, "cannot disable TX MAC\n"); 2343 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, txcfg); 2344 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, 0); 2345 bus_space_barrier(t, mac, GEM_MAC_RX_CONFIG, 4, 2346 BUS_SPACE_BARRIER_WRITE); 2347 if (!gem_bitwait(sc, mac, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)) 2348 aprint_normal_dev(&sc->sc_dev, "cannot disable RX MAC\n"); 2349 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, rxcfg); 2350 2351 v = bus_space_read_4(t, mac, GEM_MAC_CONTROL_CONFIG) & 2352 ~(GEM_MAC_CC_RX_PAUSE | GEM_MAC_CC_TX_PAUSE); 2353 bus_space_write_4(t, mac, GEM_MAC_CONTROL_CONFIG, v); 2354 2355 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) == 0 && 2356 gigabit != 0) 2357 bus_space_write_4(t, mac, GEM_MAC_SLOT_TIME, 2358 GEM_MAC_SLOT_TIME_CARR_EXTEND); 2359 else 2360 bus_space_write_4(t, mac, GEM_MAC_SLOT_TIME, 2361 GEM_MAC_SLOT_TIME_NORMAL); 2362 2363 /* XIF Configuration */ 2364 if (sc->sc_flags & GEM_LINK) 2365 v = GEM_MAC_XIF_LINK_LED; 2366 else 2367 v = 0; 2368 v |= GEM_MAC_XIF_TX_MII_ENA; 2369 2370 /* If an external transceiver is connected, enable its MII drivers */ 2371 sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG); 2372 if ((sc->sc_flags &(GEM_SERDES | GEM_SERIAL)) == 0) { 2373 if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) { 2374 /* External MII needs echo disable if half duplex. */ 2375 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & 2376 IFM_FDX) != 0) 2377 /* turn on full duplex LED */ 2378 v |= GEM_MAC_XIF_FDPLX_LED; 2379 else 2380 /* half duplex -- disable echo */ 2381 v |= GEM_MAC_XIF_ECHO_DISABL; 2382 if (gigabit) 2383 v |= GEM_MAC_XIF_GMII_MODE; 2384 else 2385 v &= ~GEM_MAC_XIF_GMII_MODE; 2386 } else 2387 /* Internal MII needs buf enable */ 2388 v |= GEM_MAC_XIF_MII_BUF_ENA; 2389 } else { 2390 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 2391 v |= GEM_MAC_XIF_FDPLX_LED; 2392 v |= GEM_MAC_XIF_GMII_MODE; 2393 } 2394 bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v); 2395 2396 if ((ifp->if_flags & IFF_RUNNING) != 0 && 2397 (sc->sc_flags & GEM_LINK) != 0) { 2398 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 2399 txcfg | GEM_MAC_TX_ENABLE); 2400 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, 2401 rxcfg | GEM_MAC_RX_ENABLE); 2402 } 2403 } 2404 2405 int 2406 gem_ser_mediachange(struct ifnet *ifp) 2407 { 2408 struct gem_softc *sc = ifp->if_softc; 2409 u_int s, t; 2410 2411 if (IFM_TYPE(sc->sc_mii.mii_media.ifm_media) != IFM_ETHER) 2412 return EINVAL; 2413 2414 s = IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media); 2415 if (s == IFM_AUTO) { 2416 if (sc->sc_mii_media != s) { 2417 #ifdef GEM_DEBUG 2418 aprint_debug_dev(&sc->sc_dev, "setting media to auto\n"); 2419 #endif 2420 sc->sc_mii_media = s; 2421 if (ifp->if_flags & IFF_UP) { 2422 gem_pcs_stop(sc, 0); 2423 gem_pcs_start(sc); 2424 } 2425 } 2426 return 0; 2427 } 2428 if (s == IFM_1000_SX) { 2429 t = IFM_OPTIONS(sc->sc_mii.mii_media.ifm_media); 2430 if (t == IFM_FDX || t == IFM_HDX) { 2431 if (sc->sc_mii_media != t) { 2432 sc->sc_mii_media = t; 2433 #ifdef GEM_DEBUG 2434 aprint_debug_dev(&sc->sc_dev, 2435 "setting media to 1000baseSX-%s\n", 2436 t == IFM_FDX ? "FDX" : "HDX"); 2437 #endif 2438 if (ifp->if_flags & IFF_UP) { 2439 gem_pcs_stop(sc, 0); 2440 gem_pcs_start(sc); 2441 } 2442 } 2443 return 0; 2444 } 2445 } 2446 return EINVAL; 2447 } 2448 2449 void 2450 gem_ser_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2451 { 2452 struct gem_softc *sc = ifp->if_softc; 2453 2454 if ((ifp->if_flags & IFF_UP) == 0) 2455 return; 2456 ifmr->ifm_active = sc->sc_mii.mii_media_active; 2457 ifmr->ifm_status = sc->sc_mii.mii_media_status; 2458 } 2459 2460 static int 2461 gem_ifflags_cb(struct ethercom *ec) 2462 { 2463 struct ifnet *ifp = &ec->ec_if; 2464 struct gem_softc *sc = ifp->if_softc; 2465 int change = ifp->if_flags ^ sc->sc_if_flags; 2466 2467 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 2468 return ENETRESET; 2469 else if ((change & IFF_PROMISC) != 0) 2470 gem_setladrf(sc); 2471 return 0; 2472 } 2473 2474 /* 2475 * Process an ioctl request. 2476 */ 2477 int 2478 gem_ioctl(struct ifnet *ifp, unsigned long cmd, void *data) 2479 { 2480 struct gem_softc *sc = ifp->if_softc; 2481 int s, error = 0; 2482 2483 s = splnet(); 2484 2485 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2486 error = 0; 2487 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 2488 ; 2489 else if (ifp->if_flags & IFF_RUNNING) { 2490 /* 2491 * Multicast list has changed; set the hardware filter 2492 * accordingly. 2493 */ 2494 gem_setladrf(sc); 2495 } 2496 } 2497 2498 /* Try to get things going again */ 2499 if (ifp->if_flags & IFF_UP) 2500 gem_start(ifp); 2501 splx(s); 2502 return (error); 2503 } 2504 2505 2506 void 2507 gem_shutdown(void *arg) 2508 { 2509 struct gem_softc *sc = (struct gem_softc *)arg; 2510 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2511 2512 gem_stop(ifp, 1); 2513 } 2514 2515 /* 2516 * Set up the logical address filter. 2517 */ 2518 void 2519 gem_setladrf(struct gem_softc *sc) 2520 { 2521 struct ethercom *ec = &sc->sc_ethercom; 2522 struct ifnet *ifp = &ec->ec_if; 2523 struct ether_multi *enm; 2524 struct ether_multistep step; 2525 bus_space_tag_t t = sc->sc_bustag; 2526 bus_space_handle_t h = sc->sc_h1; 2527 u_int32_t crc; 2528 u_int32_t hash[16]; 2529 u_int32_t v; 2530 int i; 2531 2532 /* Get current RX configuration */ 2533 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 2534 2535 /* 2536 * Turn off promiscuous mode, promiscuous group mode (all multicast), 2537 * and hash filter. Depending on the case, the right bit will be 2538 * enabled. 2539 */ 2540 v &= ~(GEM_MAC_RX_PROMISCUOUS|GEM_MAC_RX_HASH_FILTER| 2541 GEM_MAC_RX_PROMISC_GRP); 2542 2543 if ((ifp->if_flags & IFF_PROMISC) != 0) { 2544 /* Turn on promiscuous mode */ 2545 v |= GEM_MAC_RX_PROMISCUOUS; 2546 ifp->if_flags |= IFF_ALLMULTI; 2547 goto chipit; 2548 } 2549 2550 /* 2551 * Set up multicast address filter by passing all multicast addresses 2552 * through a crc generator, and then using the high order 8 bits as an 2553 * index into the 256 bit logical address filter. The high order 4 2554 * bits selects the word, while the other 4 bits select the bit within 2555 * the word (where bit 0 is the MSB). 2556 */ 2557 2558 /* Clear hash table */ 2559 memset(hash, 0, sizeof(hash)); 2560 2561 ETHER_FIRST_MULTI(step, ec, enm); 2562 while (enm != NULL) { 2563 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2564 /* 2565 * We must listen to a range of multicast addresses. 2566 * For now, just accept all multicasts, rather than 2567 * trying to set only those filter bits needed to match 2568 * the range. (At this time, the only use of address 2569 * ranges is for IP multicast routing, for which the 2570 * range is big enough to require all bits set.) 2571 * XXX should use the address filters for this 2572 */ 2573 ifp->if_flags |= IFF_ALLMULTI; 2574 v |= GEM_MAC_RX_PROMISC_GRP; 2575 goto chipit; 2576 } 2577 2578 /* Get the LE CRC32 of the address */ 2579 crc = ether_crc32_le(enm->enm_addrlo, sizeof(enm->enm_addrlo)); 2580 2581 /* Just want the 8 most significant bits. */ 2582 crc >>= 24; 2583 2584 /* Set the corresponding bit in the filter. */ 2585 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 2586 2587 ETHER_NEXT_MULTI(step, enm); 2588 } 2589 2590 v |= GEM_MAC_RX_HASH_FILTER; 2591 ifp->if_flags &= ~IFF_ALLMULTI; 2592 2593 /* Now load the hash table into the chip (if we are using it) */ 2594 for (i = 0; i < 16; i++) { 2595 bus_space_write_4(t, h, 2596 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1-GEM_MAC_HASH0), 2597 hash[i]); 2598 } 2599 2600 chipit: 2601 sc->sc_if_flags = ifp->if_flags; 2602 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 2603 } 2604 2605 #if notyet 2606 2607 /* 2608 * gem_power: 2609 * 2610 * Power management (suspend/resume) hook. 2611 */ 2612 void 2613 gem_power(int why, void *arg) 2614 { 2615 struct gem_softc *sc = arg; 2616 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2617 int s; 2618 2619 s = splnet(); 2620 switch (why) { 2621 case PWR_SUSPEND: 2622 case PWR_STANDBY: 2623 gem_stop(ifp, 1); 2624 if (sc->sc_power != NULL) 2625 (*sc->sc_power)(sc, why); 2626 break; 2627 case PWR_RESUME: 2628 if (ifp->if_flags & IFF_UP) { 2629 if (sc->sc_power != NULL) 2630 (*sc->sc_power)(sc, why); 2631 gem_init(ifp); 2632 } 2633 break; 2634 case PWR_SOFTSUSPEND: 2635 case PWR_SOFTSTANDBY: 2636 case PWR_SOFTRESUME: 2637 break; 2638 } 2639 splx(s); 2640 } 2641 #endif 2642
Indexes created Tue Sep 23 07:09:52 GMT 2025