gem.c revision 1.85
1 /* $NetBSD: gem.c,v 1.85 2009/07/27 18:10:53 dyoung Exp $ */ 2 3 /* 4 * 5 * Copyright (C) 2001 Eduardo Horvath. 6 * Copyright (c) 2001-2003 Thomas Moestl 7 * All rights reserved. 8 * 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 */ 32 33 /* 34 * Driver for Apple GMAC, Sun ERI and Sun GEM Ethernet controllers 35 * See `GEM Gigabit Ethernet ASIC Specification' 36 * http://www.sun.com/processors/manuals/ge.pdf 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: gem.c,v 1.85 2009/07/27 18:10:53 dyoung Exp $"); 41 42 #include "opt_inet.h" 43 #include "bpfilter.h" 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/callout.h> 48 #include <sys/mbuf.h> 49 #include <sys/syslog.h> 50 #include <sys/malloc.h> 51 #include <sys/kernel.h> 52 #include <sys/socket.h> 53 #include <sys/ioctl.h> 54 #include <sys/errno.h> 55 #include <sys/device.h> 56 57 #include <machine/endian.h> 58 59 #include <uvm/uvm_extern.h> 60 61 #include <net/if.h> 62 #include <net/if_dl.h> 63 #include <net/if_media.h> 64 #include <net/if_ether.h> 65 66 #ifdef INET 67 #include <netinet/in.h> 68 #include <netinet/in_systm.h> 69 #include <netinet/in_var.h> 70 #include <netinet/ip.h> 71 #include <netinet/tcp.h> 72 #include <netinet/udp.h> 73 #endif 74 75 #if NBPFILTER > 0 76 #include <net/bpf.h> 77 #endif 78 79 #include <sys/bus.h> 80 #include <sys/intr.h> 81 82 #include <dev/mii/mii.h> 83 #include <dev/mii/miivar.h> 84 #include <dev/mii/mii_bitbang.h> 85 86 #include <dev/ic/gemreg.h> 87 #include <dev/ic/gemvar.h> 88 89 #define TRIES 10000 90 91 static void gem_inten(struct gem_softc *); 92 static void gem_start(struct ifnet *); 93 static void gem_stop(struct ifnet *, int); 94 int gem_ioctl(struct ifnet *, u_long, void *); 95 void gem_tick(void *); 96 void gem_watchdog(struct ifnet *); 97 void gem_pcs_start(struct gem_softc *sc); 98 void gem_pcs_stop(struct gem_softc *sc, int); 99 int gem_init(struct ifnet *); 100 void gem_init_regs(struct gem_softc *sc); 101 static int gem_ringsize(int sz); 102 static int gem_meminit(struct gem_softc *); 103 void gem_mifinit(struct gem_softc *); 104 static int gem_bitwait(struct gem_softc *sc, bus_space_handle_t, int, 105 u_int32_t, u_int32_t); 106 void gem_reset(struct gem_softc *); 107 int gem_reset_rx(struct gem_softc *sc); 108 static void gem_reset_rxdma(struct gem_softc *sc); 109 static void gem_rx_common(struct gem_softc *sc); 110 int gem_reset_tx(struct gem_softc *sc); 111 int gem_disable_rx(struct gem_softc *sc); 112 int gem_disable_tx(struct gem_softc *sc); 113 static void gem_rxdrain(struct gem_softc *sc); 114 int gem_add_rxbuf(struct gem_softc *sc, int idx); 115 void gem_setladrf(struct gem_softc *); 116 117 /* MII methods & callbacks */ 118 static int gem_mii_readreg(device_t, int, int); 119 static void gem_mii_writereg(device_t, int, int, int); 120 static void gem_mii_statchg(device_t); 121 122 static int gem_ifflags_cb(struct ethercom *); 123 124 void gem_statuschange(struct gem_softc *); 125 126 int gem_ser_mediachange(struct ifnet *); 127 void gem_ser_mediastatus(struct ifnet *, struct ifmediareq *); 128 129 static void gem_partial_detach(struct gem_softc *, enum gem_attach_stage); 130 131 struct mbuf *gem_get(struct gem_softc *, int, int); 132 int gem_put(struct gem_softc *, int, struct mbuf *); 133 void gem_read(struct gem_softc *, int, int); 134 int gem_pint(struct gem_softc *); 135 int gem_eint(struct gem_softc *, u_int); 136 int gem_rint(struct gem_softc *); 137 int gem_tint(struct gem_softc *); 138 void gem_power(int, void *); 139 140 #ifdef GEM_DEBUG 141 static void gem_txsoft_print(const struct gem_softc *, int, int); 142 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 143 printf x 144 #else 145 #define DPRINTF(sc, x) /* nothing */ 146 #endif 147 148 #define ETHER_MIN_TX (ETHERMIN + sizeof(struct ether_header)) 149 150 int 151 gem_detach(struct gem_softc *sc, int flags) 152 { 153 char *nullbuf; 154 int i, rc; 155 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 156 157 nullbuf = 158 (char *)sc->sc_control_data + sizeof(struct gem_control_data); 159 160 /* 161 * Free any resources we've allocated during the attach. 162 * Do this in reverse order and fall through. 163 */ 164 switch (sc->sc_att_stage) { 165 case GEM_ATT_BACKEND_2: 166 case GEM_ATT_BACKEND_1: 167 case GEM_ATT_FINISHED: 168 gem_stop(&sc->sc_ethercom.ec_if, 1); 169 170 #ifdef GEM_COUNTERS 171 for (i = __arraycount(sc->sc_ev_rxhist); --i >= 0; ) 172 evcnt_detach(&sc->sc_ev_rxhist[i]); 173 evcnt_detach(&sc->sc_ev_rxnobuf); 174 evcnt_detach(&sc->sc_ev_rxfull); 175 evcnt_detach(&sc->sc_ev_rxint); 176 evcnt_detach(&sc->sc_ev_txint); 177 #endif 178 evcnt_detach(&sc->sc_ev_intr); 179 180 callout_destroy(&sc->sc_tick_ch); 181 #if NRND > 0 182 rnd_detach_source(&sc->rnd_source); 183 #endif 184 ether_ifdetach(ifp); 185 if_detach(ifp); 186 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 187 /*FALLTHROUGH*/ 188 case GEM_ATT_MII: 189 sc->sc_att_stage = GEM_ATT_MII; 190 if ((rc = config_detach_children(sc->sc_dev, flags)) != 0) 191 return rc; 192 /*FALLTHROUGH*/ 193 case GEM_ATT_7: 194 for (i = 0; i < GEM_NRXDESC; i++) { 195 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 196 bus_dmamap_destroy(sc->sc_dmatag, 197 sc->sc_rxsoft[i].rxs_dmamap); 198 } 199 /*FALLTHROUGH*/ 200 case GEM_ATT_6: 201 for (i = 0; i < GEM_TXQUEUELEN; i++) { 202 if (sc->sc_txsoft[i].txs_dmamap != NULL) 203 bus_dmamap_destroy(sc->sc_dmatag, 204 sc->sc_txsoft[i].txs_dmamap); 205 } 206 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 207 /*FALLTHROUGH*/ 208 case GEM_ATT_5: 209 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_nulldmamap); 210 /*FALLTHROUGH*/ 211 case GEM_ATT_4: 212 bus_dmamem_unmap(sc->sc_dmatag, nullbuf, ETHER_MIN_TX); 213 /*FALLTHROUGH*/ 214 case GEM_ATT_3: 215 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 216 /*FALLTHROUGH*/ 217 case GEM_ATT_2: 218 bus_dmamem_unmap(sc->sc_dmatag, sc->sc_control_data, 219 sizeof(struct gem_control_data)); 220 /*FALLTHROUGH*/ 221 case GEM_ATT_1: 222 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 223 /*FALLTHROUGH*/ 224 case GEM_ATT_0: 225 sc->sc_att_stage = GEM_ATT_0; 226 /*FALLTHROUGH*/ 227 case GEM_ATT_BACKEND_0: 228 break; 229 } 230 return 0; 231 } 232 233 static void 234 gem_partial_detach(struct gem_softc *sc, enum gem_attach_stage stage) 235 { 236 cfattach_t ca = device_cfattach(sc->sc_dev); 237 238 sc->sc_att_stage = stage; 239 (*ca->ca_detach)(sc->sc_dev, 0); 240 } 241 242 /* 243 * gem_attach: 244 * 245 * Attach a Gem interface to the system. 246 */ 247 void 248 gem_attach(struct gem_softc *sc, const uint8_t *enaddr) 249 { 250 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 251 struct mii_data *mii = &sc->sc_mii; 252 bus_space_tag_t t = sc->sc_bustag; 253 bus_space_handle_t h = sc->sc_h1; 254 struct ifmedia_entry *ifm; 255 int i, error; 256 u_int32_t v; 257 char *nullbuf; 258 259 /* Make sure the chip is stopped. */ 260 ifp->if_softc = sc; 261 gem_reset(sc); 262 263 /* 264 * Allocate the control data structures, and create and load the 265 * DMA map for it. gem_control_data is 9216 bytes, we have space for 266 * the padding buffer in the bus_dmamem_alloc()'d memory. 267 */ 268 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 269 sizeof(struct gem_control_data) + ETHER_MIN_TX, PAGE_SIZE, 270 0, &sc->sc_cdseg, 1, &sc->sc_cdnseg, 0)) != 0) { 271 aprint_error_dev(sc->sc_dev, 272 "unable to allocate control data, error = %d\n", 273 error); 274 gem_partial_detach(sc, GEM_ATT_0); 275 return; 276 } 277 278 /* XXX should map this in with correct endianness */ 279 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg, 280 sizeof(struct gem_control_data), (void **)&sc->sc_control_data, 281 BUS_DMA_COHERENT)) != 0) { 282 aprint_error_dev(sc->sc_dev, 283 "unable to map control data, error = %d\n", error); 284 gem_partial_detach(sc, GEM_ATT_1); 285 return; 286 } 287 288 nullbuf = 289 (char *)sc->sc_control_data + sizeof(struct gem_control_data); 290 291 if ((error = bus_dmamap_create(sc->sc_dmatag, 292 sizeof(struct gem_control_data), 1, 293 sizeof(struct gem_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 294 aprint_error_dev(sc->sc_dev, 295 "unable to create control data DMA map, error = %d\n", 296 error); 297 gem_partial_detach(sc, GEM_ATT_2); 298 return; 299 } 300 301 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 302 sc->sc_control_data, sizeof(struct gem_control_data), NULL, 303 0)) != 0) { 304 aprint_error_dev(sc->sc_dev, 305 "unable to load control data DMA map, error = %d\n", 306 error); 307 gem_partial_detach(sc, GEM_ATT_3); 308 return; 309 } 310 311 memset(nullbuf, 0, ETHER_MIN_TX); 312 if ((error = bus_dmamap_create(sc->sc_dmatag, 313 ETHER_MIN_TX, 1, ETHER_MIN_TX, 0, 0, &sc->sc_nulldmamap)) != 0) { 314 aprint_error_dev(sc->sc_dev, 315 "unable to create padding DMA map, error = %d\n", error); 316 gem_partial_detach(sc, GEM_ATT_4); 317 return; 318 } 319 320 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_nulldmamap, 321 nullbuf, ETHER_MIN_TX, NULL, 0)) != 0) { 322 aprint_error_dev(sc->sc_dev, 323 "unable to load padding DMA map, error = %d\n", error); 324 gem_partial_detach(sc, GEM_ATT_5); 325 return; 326 } 327 328 bus_dmamap_sync(sc->sc_dmatag, sc->sc_nulldmamap, 0, ETHER_MIN_TX, 329 BUS_DMASYNC_PREWRITE); 330 331 /* 332 * Initialize the transmit job descriptors. 333 */ 334 SIMPLEQ_INIT(&sc->sc_txfreeq); 335 SIMPLEQ_INIT(&sc->sc_txdirtyq); 336 337 /* 338 * Create the transmit buffer DMA maps. 339 */ 340 for (i = 0; i < GEM_TXQUEUELEN; i++) { 341 struct gem_txsoft *txs; 342 343 txs = &sc->sc_txsoft[i]; 344 txs->txs_mbuf = NULL; 345 if ((error = bus_dmamap_create(sc->sc_dmatag, 346 ETHER_MAX_LEN_JUMBO, GEM_NTXSEGS, 347 ETHER_MAX_LEN_JUMBO, 0, 0, 348 &txs->txs_dmamap)) != 0) { 349 aprint_error_dev(sc->sc_dev, 350 "unable to create tx DMA map %d, error = %d\n", 351 i, error); 352 gem_partial_detach(sc, GEM_ATT_6); 353 return; 354 } 355 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 356 } 357 358 /* 359 * Create the receive buffer DMA maps. 360 */ 361 for (i = 0; i < GEM_NRXDESC; i++) { 362 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, 363 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 364 aprint_error_dev(sc->sc_dev, 365 "unable to create rx DMA map %d, error = %d\n", 366 i, error); 367 gem_partial_detach(sc, GEM_ATT_7); 368 return; 369 } 370 sc->sc_rxsoft[i].rxs_mbuf = NULL; 371 } 372 373 /* Initialize ifmedia structures and MII info */ 374 mii->mii_ifp = ifp; 375 mii->mii_readreg = gem_mii_readreg; 376 mii->mii_writereg = gem_mii_writereg; 377 mii->mii_statchg = gem_mii_statchg; 378 379 sc->sc_ethercom.ec_mii = mii; 380 381 /* 382 * Initialization based on `GEM Gigabit Ethernet ASIC Specification' 383 * Section 3.2.1 `Initialization Sequence'. 384 * However, we can't assume SERDES or Serialink if neither 385 * GEM_MIF_CONFIG_MDI0 nor GEM_MIF_CONFIG_MDI1 are set 386 * being set, as both are set on Sun X1141A (with SERDES). So, 387 * we rely on our bus attachment setting GEM_SERDES or GEM_SERIAL. 388 * Also, for Apple variants with 2 PHY's, we prefer the external 389 * PHY over the internal PHY. 390 */ 391 gem_mifinit(sc); 392 393 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) { 394 ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange, 395 ether_mediastatus); 396 mii_attach(sc->sc_dev, mii, 0xffffffff, 397 MII_PHY_ANY, MII_OFFSET_ANY, MIIF_FORCEANEG); 398 if (LIST_EMPTY(&mii->mii_phys)) { 399 /* No PHY attached */ 400 aprint_error_dev(sc->sc_dev, 401 "PHY probe failed\n"); 402 gem_partial_detach(sc, GEM_ATT_MII); 403 return; 404 } else { 405 struct mii_softc *child; 406 407 /* 408 * Walk along the list of attached MII devices and 409 * establish an `MII instance' to `PHY number' 410 * mapping. 411 */ 412 LIST_FOREACH(child, &mii->mii_phys, mii_list) { 413 /* 414 * Note: we support just one PHY: the internal 415 * or external MII is already selected for us 416 * by the GEM_MIF_CONFIG register. 417 */ 418 if (child->mii_phy > 1 || child->mii_inst > 0) { 419 aprint_error_dev(sc->sc_dev, 420 "cannot accommodate MII device" 421 " %s at PHY %d, instance %d\n", 422 device_xname(child->mii_dev), 423 child->mii_phy, child->mii_inst); 424 continue; 425 } 426 sc->sc_phys[child->mii_inst] = child->mii_phy; 427 } 428 429 /* 430 * Now select and activate the PHY we will use. 431 * 432 * The order of preference is External (MDI1), 433 * then Internal (MDI0), 434 */ 435 if (sc->sc_phys[1]) { 436 #ifdef GEM_DEBUG 437 aprint_debug_dev(sc->sc_dev, 438 "using external PHY\n"); 439 #endif 440 sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL; 441 } else { 442 #ifdef GEM_DEBUG 443 aprint_debug_dev(sc->sc_dev, 444 "using internal PHY\n"); 445 sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL; 446 #endif 447 } 448 bus_space_write_4(t, h, GEM_MIF_CONFIG, 449 sc->sc_mif_config); 450 if (sc->sc_variant != GEM_SUN_ERI) 451 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 452 GEM_MII_DATAPATH_MII); 453 454 /* 455 * XXX - we can really do the following ONLY if the 456 * PHY indeed has the auto negotiation capability!! 457 */ 458 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 459 } 460 } else { 461 ifmedia_init(&mii->mii_media, IFM_IMASK, gem_ser_mediachange, 462 gem_ser_mediastatus); 463 /* SERDES or Serialink */ 464 if (sc->sc_flags & GEM_SERDES) { 465 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 466 GEM_MII_DATAPATH_SERDES); 467 } else { 468 sc->sc_flags |= GEM_SERIAL; 469 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 470 GEM_MII_DATAPATH_SERIAL); 471 } 472 473 aprint_normal_dev(sc->sc_dev, "using external PCS %s: ", 474 sc->sc_flags & GEM_SERDES ? "SERDES" : "Serialink"); 475 476 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO, 0, NULL); 477 /* Check for FDX and HDX capabilities */ 478 sc->sc_mii_anar = bus_space_read_4(t, h, GEM_MII_ANAR); 479 if (sc->sc_mii_anar & GEM_MII_ANEG_FUL_DUPLX) { 480 ifmedia_add(&sc->sc_mii.mii_media, 481 IFM_ETHER|IFM_1000_SX|IFM_MANUAL|IFM_FDX, 0, NULL); 482 aprint_normal("1000baseSX-FDX, "); 483 } 484 if (sc->sc_mii_anar & GEM_MII_ANEG_HLF_DUPLX) { 485 ifmedia_add(&sc->sc_mii.mii_media, 486 IFM_ETHER|IFM_1000_SX|IFM_MANUAL|IFM_HDX, 0, NULL); 487 aprint_normal("1000baseSX-HDX, "); 488 } 489 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 490 sc->sc_mii_media = IFM_AUTO; 491 aprint_normal("auto\n"); 492 493 gem_pcs_stop(sc, 1); 494 } 495 496 /* 497 * From this point forward, the attachment cannot fail. A failure 498 * before this point releases all resources that may have been 499 * allocated. 500 */ 501 502 /* Announce ourselves. */ 503 aprint_normal_dev(sc->sc_dev, "Ethernet address %s", 504 ether_sprintf(enaddr)); 505 506 /* Get RX FIFO size */ 507 sc->sc_rxfifosize = 64 * 508 bus_space_read_4(t, h, GEM_RX_FIFO_SIZE); 509 aprint_normal(", %uKB RX fifo", sc->sc_rxfifosize / 1024); 510 511 /* Get TX FIFO size */ 512 v = bus_space_read_4(t, h, GEM_TX_FIFO_SIZE); 513 aprint_normal(", %uKB TX fifo\n", v / 16); 514 515 /* Initialize ifnet structure. */ 516 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 517 ifp->if_softc = sc; 518 ifp->if_flags = 519 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 520 sc->sc_if_flags = ifp->if_flags; 521 #if 0 522 /* 523 * The GEM hardware supports basic TCP checksum offloading only. 524 * Several (all?) revisions (Sun rev. 01 and Apple rev. 00 and 80) 525 * have bugs in the receive checksum, so don't enable it for now. 526 */ 527 if ((GEM_IS_SUN(sc) && sc->sc_chiprev != 1) || 528 (GEM_IS_APPLE(sc) && 529 (sc->sc_chiprev != 0 && sc->sc_chiprev != 0x80))) 530 ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Rx; 531 #endif 532 ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Tx; 533 ifp->if_start = gem_start; 534 ifp->if_ioctl = gem_ioctl; 535 ifp->if_watchdog = gem_watchdog; 536 ifp->if_stop = gem_stop; 537 ifp->if_init = gem_init; 538 IFQ_SET_READY(&ifp->if_snd); 539 540 /* 541 * If we support GigE media, we support jumbo frames too. 542 * Unless we are Apple. 543 */ 544 TAILQ_FOREACH(ifm, &sc->sc_mii.mii_media.ifm_list, ifm_list) { 545 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_T || 546 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_SX || 547 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_LX || 548 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_CX) { 549 if (!GEM_IS_APPLE(sc)) 550 sc->sc_ethercom.ec_capabilities 551 |= ETHERCAP_JUMBO_MTU; 552 sc->sc_flags |= GEM_GIGABIT; 553 break; 554 } 555 } 556 557 /* claim 802.1q capability */ 558 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 559 560 /* Attach the interface. */ 561 if_attach(ifp); 562 ether_ifattach(ifp, enaddr); 563 ether_set_ifflags_cb(&sc->sc_ethercom, gem_ifflags_cb); 564 565 #if NRND > 0 566 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 567 RND_TYPE_NET, 0); 568 #endif 569 570 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, 571 NULL, device_xname(sc->sc_dev), "interrupts"); 572 #ifdef GEM_COUNTERS 573 evcnt_attach_dynamic(&sc->sc_ev_txint, EVCNT_TYPE_INTR, 574 &sc->sc_ev_intr, device_xname(sc->sc_dev), "tx interrupts"); 575 evcnt_attach_dynamic(&sc->sc_ev_rxint, EVCNT_TYPE_INTR, 576 &sc->sc_ev_intr, device_xname(sc->sc_dev), "rx interrupts"); 577 evcnt_attach_dynamic(&sc->sc_ev_rxfull, EVCNT_TYPE_INTR, 578 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx ring full"); 579 evcnt_attach_dynamic(&sc->sc_ev_rxnobuf, EVCNT_TYPE_INTR, 580 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx malloc failure"); 581 evcnt_attach_dynamic(&sc->sc_ev_rxhist[0], EVCNT_TYPE_INTR, 582 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 0desc"); 583 evcnt_attach_dynamic(&sc->sc_ev_rxhist[1], EVCNT_TYPE_INTR, 584 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 1desc"); 585 evcnt_attach_dynamic(&sc->sc_ev_rxhist[2], EVCNT_TYPE_INTR, 586 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 2desc"); 587 evcnt_attach_dynamic(&sc->sc_ev_rxhist[3], EVCNT_TYPE_INTR, 588 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 3desc"); 589 evcnt_attach_dynamic(&sc->sc_ev_rxhist[4], EVCNT_TYPE_INTR, 590 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >3desc"); 591 evcnt_attach_dynamic(&sc->sc_ev_rxhist[5], EVCNT_TYPE_INTR, 592 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >7desc"); 593 evcnt_attach_dynamic(&sc->sc_ev_rxhist[6], EVCNT_TYPE_INTR, 594 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >15desc"); 595 evcnt_attach_dynamic(&sc->sc_ev_rxhist[7], EVCNT_TYPE_INTR, 596 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >31desc"); 597 evcnt_attach_dynamic(&sc->sc_ev_rxhist[8], EVCNT_TYPE_INTR, 598 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >63desc"); 599 #endif 600 601 callout_init(&sc->sc_tick_ch, 0); 602 603 sc->sc_att_stage = GEM_ATT_FINISHED; 604 605 return; 606 } 607 608 void 609 gem_tick(void *arg) 610 { 611 struct gem_softc *sc = arg; 612 int s; 613 614 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) { 615 /* 616 * We have to reset everything if we failed to get a 617 * PCS interrupt. Restarting the callout is handled 618 * in gem_pcs_start(). 619 */ 620 gem_init(&sc->sc_ethercom.ec_if); 621 } else { 622 s = splnet(); 623 mii_tick(&sc->sc_mii); 624 splx(s); 625 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 626 } 627 } 628 629 static int 630 gem_bitwait(struct gem_softc *sc, bus_space_handle_t h, int r, u_int32_t clr, u_int32_t set) 631 { 632 int i; 633 u_int32_t reg; 634 635 for (i = TRIES; i--; DELAY(100)) { 636 reg = bus_space_read_4(sc->sc_bustag, h, r); 637 if ((reg & clr) == 0 && (reg & set) == set) 638 return (1); 639 } 640 return (0); 641 } 642 643 void 644 gem_reset(struct gem_softc *sc) 645 { 646 bus_space_tag_t t = sc->sc_bustag; 647 bus_space_handle_t h = sc->sc_h2; 648 int s; 649 650 s = splnet(); 651 DPRINTF(sc, ("%s: gem_reset\n", device_xname(sc->sc_dev))); 652 gem_reset_rx(sc); 653 gem_reset_tx(sc); 654 655 /* Do a full reset */ 656 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX|GEM_RESET_TX); 657 if (!gem_bitwait(sc, h, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0)) 658 aprint_error_dev(sc->sc_dev, "cannot reset device\n"); 659 splx(s); 660 } 661 662 663 /* 664 * gem_rxdrain: 665 * 666 * Drain the receive queue. 667 */ 668 static void 669 gem_rxdrain(struct gem_softc *sc) 670 { 671 struct gem_rxsoft *rxs; 672 int i; 673 674 for (i = 0; i < GEM_NRXDESC; i++) { 675 rxs = &sc->sc_rxsoft[i]; 676 if (rxs->rxs_mbuf != NULL) { 677 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 678 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 679 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 680 m_freem(rxs->rxs_mbuf); 681 rxs->rxs_mbuf = NULL; 682 } 683 } 684 } 685 686 /* 687 * Reset the whole thing. 688 */ 689 static void 690 gem_stop(struct ifnet *ifp, int disable) 691 { 692 struct gem_softc *sc = ifp->if_softc; 693 struct gem_txsoft *txs; 694 695 DPRINTF(sc, ("%s: gem_stop\n", device_xname(sc->sc_dev))); 696 697 callout_stop(&sc->sc_tick_ch); 698 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 699 gem_pcs_stop(sc, disable); 700 else 701 mii_down(&sc->sc_mii); 702 703 /* XXX - Should we reset these instead? */ 704 gem_disable_tx(sc); 705 gem_disable_rx(sc); 706 707 /* 708 * Release any queued transmit buffers. 709 */ 710 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 711 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 712 if (txs->txs_mbuf != NULL) { 713 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 0, 714 txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 715 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 716 m_freem(txs->txs_mbuf); 717 txs->txs_mbuf = NULL; 718 } 719 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 720 } 721 722 /* 723 * Mark the interface down and cancel the watchdog timer. 724 */ 725 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 726 sc->sc_if_flags = ifp->if_flags; 727 ifp->if_timer = 0; 728 729 if (disable) 730 gem_rxdrain(sc); 731 } 732 733 734 /* 735 * Reset the receiver 736 */ 737 int 738 gem_reset_rx(struct gem_softc *sc) 739 { 740 bus_space_tag_t t = sc->sc_bustag; 741 bus_space_handle_t h = sc->sc_h1, h2 = sc->sc_h2; 742 743 /* 744 * Resetting while DMA is in progress can cause a bus hang, so we 745 * disable DMA first. 746 */ 747 gem_disable_rx(sc); 748 bus_space_write_4(t, h, GEM_RX_CONFIG, 0); 749 bus_space_barrier(t, h, GEM_RX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 750 /* Wait till it finishes */ 751 if (!gem_bitwait(sc, h, GEM_RX_CONFIG, 1, 0)) 752 aprint_error_dev(sc->sc_dev, "cannot disable read dma\n"); 753 754 /* Finally, reset the ERX */ 755 bus_space_write_4(t, h2, GEM_RESET, GEM_RESET_RX); 756 bus_space_barrier(t, h, GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE); 757 /* Wait till it finishes */ 758 if (!gem_bitwait(sc, h2, GEM_RESET, GEM_RESET_RX, 0)) { 759 aprint_error_dev(sc->sc_dev, "cannot reset receiver\n"); 760 return (1); 761 } 762 return (0); 763 } 764 765 766 /* 767 * Reset the receiver DMA engine. 768 * 769 * Intended to be used in case of GEM_INTR_RX_TAG_ERR, GEM_MAC_RX_OVERFLOW 770 * etc in order to reset the receiver DMA engine only and not do a full 771 * reset which amongst others also downs the link and clears the FIFOs. 772 */ 773 static void 774 gem_reset_rxdma(struct gem_softc *sc) 775 { 776 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 777 bus_space_tag_t t = sc->sc_bustag; 778 bus_space_handle_t h = sc->sc_h1; 779 int i; 780 781 if (gem_reset_rx(sc) != 0) { 782 gem_init(ifp); 783 return; 784 } 785 for (i = 0; i < GEM_NRXDESC; i++) 786 if (sc->sc_rxsoft[i].rxs_mbuf != NULL) 787 GEM_UPDATE_RXDESC(sc, i); 788 sc->sc_rxptr = 0; 789 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE); 790 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD); 791 792 /* Reprogram Descriptor Ring Base Addresses */ 793 /* NOTE: we use only 32-bit DMA addresses here. */ 794 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0); 795 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 796 797 /* Redo ERX Configuration */ 798 gem_rx_common(sc); 799 800 /* Give the reciever a swift kick */ 801 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC - 4); 802 } 803 804 /* 805 * Common RX configuration for gem_init() and gem_reset_rxdma(). 806 */ 807 static void 808 gem_rx_common(struct gem_softc *sc) 809 { 810 bus_space_tag_t t = sc->sc_bustag; 811 bus_space_handle_t h = sc->sc_h1; 812 u_int32_t v; 813 814 /* Encode Receive Descriptor ring size: four possible values */ 815 v = gem_ringsize(GEM_NRXDESC /*XXX*/); 816 817 /* Set receive h/w checksum offset */ 818 #ifdef INET 819 v |= (ETHER_HDR_LEN + sizeof(struct ip) + 820 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 821 ETHER_VLAN_ENCAP_LEN : 0)) << GEM_RX_CONFIG_CXM_START_SHFT; 822 #endif 823 824 /* Enable RX DMA */ 825 bus_space_write_4(t, h, GEM_RX_CONFIG, 826 v | (GEM_THRSH_1024 << GEM_RX_CONFIG_FIFO_THRS_SHIFT) | 827 (2 << GEM_RX_CONFIG_FBOFF_SHFT) | GEM_RX_CONFIG_RXDMA_EN); 828 829 /* 830 * The following value is for an OFF Threshold of about 3/4 full 831 * and an ON Threshold of 1/4 full. 832 */ 833 bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH, 834 (3 * sc->sc_rxfifosize / 256) | 835 ((sc->sc_rxfifosize / 256) << 12)); 836 bus_space_write_4(t, h, GEM_RX_BLANKING, 837 (6 << GEM_RX_BLANKING_TIME_SHIFT) | 6); 838 } 839 840 /* 841 * Reset the transmitter 842 */ 843 int 844 gem_reset_tx(struct gem_softc *sc) 845 { 846 bus_space_tag_t t = sc->sc_bustag; 847 bus_space_handle_t h = sc->sc_h1, h2 = sc->sc_h2; 848 849 /* 850 * Resetting while DMA is in progress can cause a bus hang, so we 851 * disable DMA first. 852 */ 853 gem_disable_tx(sc); 854 bus_space_write_4(t, h, GEM_TX_CONFIG, 0); 855 bus_space_barrier(t, h, GEM_TX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 856 /* Wait till it finishes */ 857 if (!gem_bitwait(sc, h, GEM_TX_CONFIG, 1, 0)) 858 aprint_error_dev(sc->sc_dev, "cannot disable read dma\n"); 859 /* Wait 5ms extra. */ 860 delay(5000); 861 862 /* Finally, reset the ETX */ 863 bus_space_write_4(t, h2, GEM_RESET, GEM_RESET_TX); 864 bus_space_barrier(t, h, GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE); 865 /* Wait till it finishes */ 866 if (!gem_bitwait(sc, h2, GEM_RESET, GEM_RESET_TX, 0)) { 867 aprint_error_dev(sc->sc_dev, "cannot reset receiver\n"); 868 return (1); 869 } 870 return (0); 871 } 872 873 /* 874 * disable receiver. 875 */ 876 int 877 gem_disable_rx(struct gem_softc *sc) 878 { 879 bus_space_tag_t t = sc->sc_bustag; 880 bus_space_handle_t h = sc->sc_h1; 881 u_int32_t cfg; 882 883 /* Flip the enable bit */ 884 cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 885 cfg &= ~GEM_MAC_RX_ENABLE; 886 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg); 887 bus_space_barrier(t, h, GEM_MAC_RX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 888 /* Wait for it to finish */ 889 return (gem_bitwait(sc, h, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)); 890 } 891 892 /* 893 * disable transmitter. 894 */ 895 int 896 gem_disable_tx(struct gem_softc *sc) 897 { 898 bus_space_tag_t t = sc->sc_bustag; 899 bus_space_handle_t h = sc->sc_h1; 900 u_int32_t cfg; 901 902 /* Flip the enable bit */ 903 cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG); 904 cfg &= ~GEM_MAC_TX_ENABLE; 905 bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg); 906 bus_space_barrier(t, h, GEM_MAC_TX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 907 /* Wait for it to finish */ 908 return (gem_bitwait(sc, h, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)); 909 } 910 911 /* 912 * Initialize interface. 913 */ 914 int 915 gem_meminit(struct gem_softc *sc) 916 { 917 struct gem_rxsoft *rxs; 918 int i, error; 919 920 /* 921 * Initialize the transmit descriptor ring. 922 */ 923 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 924 for (i = 0; i < GEM_NTXDESC; i++) { 925 sc->sc_txdescs[i].gd_flags = 0; 926 sc->sc_txdescs[i].gd_addr = 0; 927 } 928 GEM_CDTXSYNC(sc, 0, GEM_NTXDESC, 929 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 930 sc->sc_txfree = GEM_NTXDESC-1; 931 sc->sc_txnext = 0; 932 sc->sc_txwin = 0; 933 934 /* 935 * Initialize the receive descriptor and receive job 936 * descriptor rings. 937 */ 938 for (i = 0; i < GEM_NRXDESC; i++) { 939 rxs = &sc->sc_rxsoft[i]; 940 if (rxs->rxs_mbuf == NULL) { 941 if ((error = gem_add_rxbuf(sc, i)) != 0) { 942 aprint_error_dev(sc->sc_dev, 943 "unable to allocate or map rx " 944 "buffer %d, error = %d\n", 945 i, error); 946 /* 947 * XXX Should attempt to run with fewer receive 948 * XXX buffers instead of just failing. 949 */ 950 gem_rxdrain(sc); 951 return (1); 952 } 953 } else 954 GEM_INIT_RXDESC(sc, i); 955 } 956 sc->sc_rxptr = 0; 957 sc->sc_meminited = 1; 958 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE); 959 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD); 960 961 return (0); 962 } 963 964 static int 965 gem_ringsize(int sz) 966 { 967 switch (sz) { 968 case 32: 969 return GEM_RING_SZ_32; 970 case 64: 971 return GEM_RING_SZ_64; 972 case 128: 973 return GEM_RING_SZ_128; 974 case 256: 975 return GEM_RING_SZ_256; 976 case 512: 977 return GEM_RING_SZ_512; 978 case 1024: 979 return GEM_RING_SZ_1024; 980 case 2048: 981 return GEM_RING_SZ_2048; 982 case 4096: 983 return GEM_RING_SZ_4096; 984 case 8192: 985 return GEM_RING_SZ_8192; 986 default: 987 printf("gem: invalid Receive Descriptor ring size %d\n", sz); 988 return GEM_RING_SZ_32; 989 } 990 } 991 992 993 /* 994 * Start PCS 995 */ 996 void 997 gem_pcs_start(struct gem_softc *sc) 998 { 999 bus_space_tag_t t = sc->sc_bustag; 1000 bus_space_handle_t h = sc->sc_h1; 1001 uint32_t v; 1002 1003 #ifdef GEM_DEBUG 1004 aprint_debug_dev(sc->sc_dev, "gem_pcs_start()\n"); 1005 #endif 1006 1007 /* 1008 * Set up. We must disable the MII before modifying the 1009 * GEM_MII_ANAR register 1010 */ 1011 if (sc->sc_flags & GEM_SERDES) { 1012 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 1013 GEM_MII_DATAPATH_SERDES); 1014 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 1015 GEM_MII_SLINK_LOOPBACK); 1016 } else { 1017 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 1018 GEM_MII_DATAPATH_SERIAL); 1019 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 0); 1020 } 1021 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 1022 v = bus_space_read_4(t, h, GEM_MII_ANAR); 1023 v |= (GEM_MII_ANEG_SYM_PAUSE | GEM_MII_ANEG_ASYM_PAUSE); 1024 if (sc->sc_mii_media == IFM_AUTO) 1025 v |= (GEM_MII_ANEG_FUL_DUPLX | GEM_MII_ANEG_HLF_DUPLX); 1026 else if (sc->sc_mii_media == IFM_FDX) { 1027 v |= GEM_MII_ANEG_FUL_DUPLX; 1028 v &= ~GEM_MII_ANEG_HLF_DUPLX; 1029 } else if (sc->sc_mii_media == IFM_HDX) { 1030 v &= ~GEM_MII_ANEG_FUL_DUPLX; 1031 v |= GEM_MII_ANEG_HLF_DUPLX; 1032 } 1033 1034 /* Configure link. */ 1035 bus_space_write_4(t, h, GEM_MII_ANAR, v); 1036 bus_space_write_4(t, h, GEM_MII_CONTROL, 1037 GEM_MII_CONTROL_AUTONEG | GEM_MII_CONTROL_RAN); 1038 bus_space_write_4(t, h, GEM_MII_CONFIG, GEM_MII_CONFIG_ENABLE); 1039 gem_bitwait(sc, h, GEM_MII_STATUS, 0, GEM_MII_STATUS_ANEG_CPT); 1040 1041 /* Start the 10 second timer */ 1042 callout_reset(&sc->sc_tick_ch, hz * 10, gem_tick, sc); 1043 } 1044 1045 /* 1046 * Stop PCS 1047 */ 1048 void 1049 gem_pcs_stop(struct gem_softc *sc, int disable) 1050 { 1051 bus_space_tag_t t = sc->sc_bustag; 1052 bus_space_handle_t h = sc->sc_h1; 1053 1054 #ifdef GEM_DEBUG 1055 aprint_debug_dev(sc->sc_dev, "gem_pcs_stop()\n"); 1056 #endif 1057 1058 /* Tell link partner that we're going away */ 1059 bus_space_write_4(t, h, GEM_MII_ANAR, GEM_MII_ANEG_RF); 1060 1061 /* 1062 * Disable PCS MII. The documentation suggests that setting 1063 * GEM_MII_CONFIG_ENABLE to zero and then restarting auto- 1064 * negotiation will shut down the link. However, it appears 1065 * that we also need to unset the datapath mode. 1066 */ 1067 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 1068 bus_space_write_4(t, h, GEM_MII_CONTROL, 1069 GEM_MII_CONTROL_AUTONEG | GEM_MII_CONTROL_RAN); 1070 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, GEM_MII_DATAPATH_MII); 1071 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 1072 1073 if (disable) { 1074 if (sc->sc_flags & GEM_SERDES) 1075 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 1076 GEM_MII_SLINK_POWER_OFF); 1077 else 1078 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 1079 GEM_MII_SLINK_LOOPBACK | GEM_MII_SLINK_POWER_OFF); 1080 } 1081 1082 sc->sc_flags &= ~GEM_LINK; 1083 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_NONE; 1084 sc->sc_mii.mii_media_status = IFM_AVALID; 1085 } 1086 1087 1088 /* 1089 * Initialization of interface; set up initialization block 1090 * and transmit/receive descriptor rings. 1091 */ 1092 int 1093 gem_init(struct ifnet *ifp) 1094 { 1095 struct gem_softc *sc = ifp->if_softc; 1096 bus_space_tag_t t = sc->sc_bustag; 1097 bus_space_handle_t h = sc->sc_h1; 1098 int rc = 0, s; 1099 u_int max_frame_size; 1100 u_int32_t v; 1101 1102 s = splnet(); 1103 1104 DPRINTF(sc, ("%s: gem_init: calling stop\n", device_xname(sc->sc_dev))); 1105 /* 1106 * Initialization sequence. The numbered steps below correspond 1107 * to the sequence outlined in section 6.3.5.1 in the Ethernet 1108 * Channel Engine manual (part of the PCIO manual). 1109 * See also the STP2002-STQ document from Sun Microsystems. 1110 */ 1111 1112 /* step 1 & 2. Reset the Ethernet Channel */ 1113 gem_stop(ifp, 0); 1114 gem_reset(sc); 1115 DPRINTF(sc, ("%s: gem_init: restarting\n", device_xname(sc->sc_dev))); 1116 1117 /* Re-initialize the MIF */ 1118 gem_mifinit(sc); 1119 1120 /* Set up correct datapath for non-SERDES/Serialink */ 1121 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0 && 1122 sc->sc_variant != GEM_SUN_ERI) 1123 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 1124 GEM_MII_DATAPATH_MII); 1125 1126 /* Call MI reset function if any */ 1127 if (sc->sc_hwreset) 1128 (*sc->sc_hwreset)(sc); 1129 1130 /* step 3. Setup data structures in host memory */ 1131 if (gem_meminit(sc) != 0) 1132 return 1; 1133 1134 /* step 4. TX MAC registers & counters */ 1135 gem_init_regs(sc); 1136 max_frame_size = max(sc->sc_ethercom.ec_if.if_mtu, ETHERMTU); 1137 max_frame_size += ETHER_HDR_LEN + ETHER_CRC_LEN; 1138 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1139 max_frame_size += ETHER_VLAN_ENCAP_LEN; 1140 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 1141 max_frame_size|/* burst size */(0x2000<<16)); 1142 1143 /* step 5. RX MAC registers & counters */ 1144 gem_setladrf(sc); 1145 1146 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 1147 /* NOTE: we use only 32-bit DMA addresses here. */ 1148 bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 0); 1149 bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 1150 1151 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0); 1152 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 1153 1154 /* step 8. Global Configuration & Interrupt Mask */ 1155 gem_inten(sc); 1156 bus_space_write_4(t, h, GEM_MAC_RX_MASK, 1157 GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT); 1158 bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXX */ 1159 bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 1160 GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME); 1161 1162 /* step 9. ETX Configuration: use mostly default values */ 1163 1164 /* Enable TX DMA */ 1165 v = gem_ringsize(GEM_NTXDESC /*XXX*/); 1166 bus_space_write_4(t, h, GEM_TX_CONFIG, 1167 v|GEM_TX_CONFIG_TXDMA_EN| 1168 ((0x4FF<<10)&GEM_TX_CONFIG_TXFIFO_TH)); 1169 bus_space_write_4(t, h, GEM_TX_KICK, sc->sc_txnext); 1170 1171 /* step 10. ERX Configuration */ 1172 gem_rx_common(sc); 1173 1174 /* step 11. Configure Media */ 1175 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0 && 1176 (rc = mii_ifmedia_change(&sc->sc_mii)) != 0) 1177 goto out; 1178 1179 /* step 12. RX_MAC Configuration Register */ 1180 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 1181 v |= GEM_MAC_RX_ENABLE | GEM_MAC_RX_STRIP_CRC; 1182 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 1183 1184 /* step 14. Issue Transmit Pending command */ 1185 1186 /* Call MI initialization function if any */ 1187 if (sc->sc_hwinit) 1188 (*sc->sc_hwinit)(sc); 1189 1190 1191 /* step 15. Give the reciever a swift kick */ 1192 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4); 1193 1194 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 1195 /* Configure PCS */ 1196 gem_pcs_start(sc); 1197 else 1198 /* Start the one second timer. */ 1199 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 1200 1201 sc->sc_flags &= ~GEM_LINK; 1202 ifp->if_flags |= IFF_RUNNING; 1203 ifp->if_flags &= ~IFF_OACTIVE; 1204 ifp->if_timer = 0; 1205 sc->sc_if_flags = ifp->if_flags; 1206 out: 1207 splx(s); 1208 1209 return (0); 1210 } 1211 1212 void 1213 gem_init_regs(struct gem_softc *sc) 1214 { 1215 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1216 bus_space_tag_t t = sc->sc_bustag; 1217 bus_space_handle_t h = sc->sc_h1; 1218 const u_char *laddr = CLLADDR(ifp->if_sadl); 1219 u_int32_t v; 1220 1221 /* These regs are not cleared on reset */ 1222 if (!sc->sc_inited) { 1223 1224 /* Load recommended values */ 1225 bus_space_write_4(t, h, GEM_MAC_IPG0, 0x00); 1226 bus_space_write_4(t, h, GEM_MAC_IPG1, 0x08); 1227 bus_space_write_4(t, h, GEM_MAC_IPG2, 0x04); 1228 1229 bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 1230 /* Max frame and max burst size */ 1231 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 1232 ETHER_MAX_LEN | (0x2000<<16)); 1233 1234 bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x07); 1235 bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x04); 1236 bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10); 1237 bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088); 1238 bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED, 1239 ((laddr[5]<<8)|laddr[4])&0x3ff); 1240 1241 /* Secondary MAC addr set to 0:0:0:0:0:0 */ 1242 bus_space_write_4(t, h, GEM_MAC_ADDR3, 0); 1243 bus_space_write_4(t, h, GEM_MAC_ADDR4, 0); 1244 bus_space_write_4(t, h, GEM_MAC_ADDR5, 0); 1245 1246 /* MAC control addr set to 01:80:c2:00:00:01 */ 1247 bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001); 1248 bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200); 1249 bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180); 1250 1251 /* MAC filter addr set to 0:0:0:0:0:0 */ 1252 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0); 1253 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0); 1254 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0); 1255 1256 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0); 1257 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0); 1258 1259 sc->sc_inited = 1; 1260 } 1261 1262 /* Counters need to be zeroed */ 1263 bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0); 1264 bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0); 1265 bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0); 1266 bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0); 1267 bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0); 1268 bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0); 1269 bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0); 1270 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 1271 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 1272 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 1273 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 1274 1275 /* Set XOFF PAUSE time. */ 1276 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); 1277 1278 /* 1279 * Set the internal arbitration to "infinite" bursts of the 1280 * maximum length of 31 * 64 bytes so DMA transfers aren't 1281 * split up in cache line size chunks. This greatly improves 1282 * especially RX performance. 1283 * Enable silicon bug workarounds for the Apple variants. 1284 */ 1285 bus_space_write_4(t, h, GEM_CONFIG, 1286 GEM_CONFIG_TXDMA_LIMIT | GEM_CONFIG_RXDMA_LIMIT | 1287 ((sc->sc_flags & GEM_PCI) ? 1288 GEM_CONFIG_BURST_INF : GEM_CONFIG_BURST_64) | (GEM_IS_APPLE(sc) ? 1289 GEM_CONFIG_RONPAULBIT | GEM_CONFIG_BUG2FIX : 0)); 1290 1291 /* 1292 * Set the station address. 1293 */ 1294 bus_space_write_4(t, h, GEM_MAC_ADDR0, (laddr[4]<<8)|laddr[5]); 1295 bus_space_write_4(t, h, GEM_MAC_ADDR1, (laddr[2]<<8)|laddr[3]); 1296 bus_space_write_4(t, h, GEM_MAC_ADDR2, (laddr[0]<<8)|laddr[1]); 1297 1298 /* 1299 * Enable MII outputs. Enable GMII if there is a gigabit PHY. 1300 */ 1301 sc->sc_mif_config = bus_space_read_4(t, h, GEM_MIF_CONFIG); 1302 v = GEM_MAC_XIF_TX_MII_ENA; 1303 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) { 1304 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) { 1305 v |= GEM_MAC_XIF_FDPLX_LED; 1306 if (sc->sc_flags & GEM_GIGABIT) 1307 v |= GEM_MAC_XIF_GMII_MODE; 1308 } 1309 } else { 1310 v |= GEM_MAC_XIF_GMII_MODE; 1311 } 1312 bus_space_write_4(t, h, GEM_MAC_XIF_CONFIG, v); 1313 } 1314 1315 #ifdef GEM_DEBUG 1316 static void 1317 gem_txsoft_print(const struct gem_softc *sc, int firstdesc, int lastdesc) 1318 { 1319 int i; 1320 1321 for (i = firstdesc;; i = GEM_NEXTTX(i)) { 1322 printf("descriptor %d:\t", i); 1323 printf("gd_flags: 0x%016" PRIx64 "\t", 1324 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags)); 1325 printf("gd_addr: 0x%016" PRIx64 "\n", 1326 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr)); 1327 if (i == lastdesc) 1328 break; 1329 } 1330 } 1331 #endif 1332 1333 static void 1334 gem_start(struct ifnet *ifp) 1335 { 1336 struct gem_softc *sc = ifp->if_softc; 1337 struct mbuf *m0, *m; 1338 struct gem_txsoft *txs; 1339 bus_dmamap_t dmamap; 1340 int error, firsttx, nexttx = -1, lasttx = -1, ofree, seg; 1341 uint64_t flags = 0; 1342 1343 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1344 return; 1345 1346 /* 1347 * Remember the previous number of free descriptors and 1348 * the first descriptor we'll use. 1349 */ 1350 ofree = sc->sc_txfree; 1351 firsttx = sc->sc_txnext; 1352 1353 DPRINTF(sc, ("%s: gem_start: txfree %d, txnext %d\n", 1354 device_xname(sc->sc_dev), ofree, firsttx)); 1355 1356 /* 1357 * Loop through the send queue, setting up transmit descriptors 1358 * until we drain the queue, or use up all available transmit 1359 * descriptors. 1360 */ 1361 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 1362 sc->sc_txfree != 0) { 1363 /* 1364 * Grab a packet off the queue. 1365 */ 1366 IFQ_POLL(&ifp->if_snd, m0); 1367 if (m0 == NULL) 1368 break; 1369 m = NULL; 1370 1371 dmamap = txs->txs_dmamap; 1372 1373 /* 1374 * Load the DMA map. If this fails, the packet either 1375 * didn't fit in the alloted number of segments, or we were 1376 * short on resources. In this case, we'll copy and try 1377 * again. 1378 */ 1379 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m0, 1380 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0 || 1381 (m0->m_pkthdr.len < ETHER_MIN_TX && 1382 dmamap->dm_nsegs == GEM_NTXSEGS)) { 1383 if (m0->m_pkthdr.len > MCLBYTES) { 1384 aprint_error_dev(sc->sc_dev, 1385 "unable to allocate jumbo Tx cluster\n"); 1386 IFQ_DEQUEUE(&ifp->if_snd, m0); 1387 m_freem(m0); 1388 continue; 1389 } 1390 MGETHDR(m, M_DONTWAIT, MT_DATA); 1391 if (m == NULL) { 1392 aprint_error_dev(sc->sc_dev, 1393 "unable to allocate Tx mbuf\n"); 1394 break; 1395 } 1396 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1397 if (m0->m_pkthdr.len > MHLEN) { 1398 MCLGET(m, M_DONTWAIT); 1399 if ((m->m_flags & M_EXT) == 0) { 1400 aprint_error_dev(sc->sc_dev, 1401 "unable to allocate Tx cluster\n"); 1402 m_freem(m); 1403 break; 1404 } 1405 } 1406 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1407 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1408 error = bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, 1409 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1410 if (error) { 1411 aprint_error_dev(sc->sc_dev, 1412 "unable to load Tx buffer, error = %d\n", 1413 error); 1414 break; 1415 } 1416 } 1417 1418 /* 1419 * Ensure we have enough descriptors free to describe 1420 * the packet. 1421 */ 1422 if (dmamap->dm_nsegs > ((m0->m_pkthdr.len < ETHER_MIN_TX) ? 1423 (sc->sc_txfree - 1) : sc->sc_txfree)) { 1424 /* 1425 * Not enough free descriptors to transmit this 1426 * packet. We haven't committed to anything yet, 1427 * so just unload the DMA map, put the packet 1428 * back on the queue, and punt. Notify the upper 1429 * layer that there are no more slots left. 1430 * 1431 * XXX We could allocate an mbuf and copy, but 1432 * XXX it is worth it? 1433 */ 1434 ifp->if_flags |= IFF_OACTIVE; 1435 sc->sc_if_flags = ifp->if_flags; 1436 bus_dmamap_unload(sc->sc_dmatag, dmamap); 1437 if (m != NULL) 1438 m_freem(m); 1439 break; 1440 } 1441 1442 IFQ_DEQUEUE(&ifp->if_snd, m0); 1443 if (m != NULL) { 1444 m_freem(m0); 1445 m0 = m; 1446 } 1447 1448 /* 1449 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1450 */ 1451 1452 /* Sync the DMA map. */ 1453 bus_dmamap_sync(sc->sc_dmatag, dmamap, 0, dmamap->dm_mapsize, 1454 BUS_DMASYNC_PREWRITE); 1455 1456 /* 1457 * Initialize the transmit descriptors. 1458 */ 1459 for (nexttx = sc->sc_txnext, seg = 0; 1460 seg < dmamap->dm_nsegs; 1461 seg++, nexttx = GEM_NEXTTX(nexttx)) { 1462 1463 /* 1464 * If this is the first descriptor we're 1465 * enqueueing, set the start of packet flag, 1466 * and the checksum stuff if we want the hardware 1467 * to do it. 1468 */ 1469 sc->sc_txdescs[nexttx].gd_addr = 1470 GEM_DMA_WRITE(sc, dmamap->dm_segs[seg].ds_addr); 1471 flags = dmamap->dm_segs[seg].ds_len & GEM_TD_BUFSIZE; 1472 if (nexttx == firsttx) { 1473 flags |= GEM_TD_START_OF_PACKET; 1474 if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) { 1475 sc->sc_txwin = 0; 1476 flags |= GEM_TD_INTERRUPT_ME; 1477 } 1478 1479 #ifdef INET 1480 /* h/w checksum */ 1481 if (ifp->if_csum_flags_tx & M_CSUM_TCPv4 && 1482 m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1483 struct ether_header *eh; 1484 uint16_t offset, start; 1485 1486 eh = mtod(m0, struct ether_header *); 1487 switch (ntohs(eh->ether_type)) { 1488 case ETHERTYPE_IP: 1489 start = ETHER_HDR_LEN; 1490 break; 1491 case ETHERTYPE_VLAN: 1492 start = ETHER_HDR_LEN + 1493 ETHER_VLAN_ENCAP_LEN; 1494 break; 1495 default: 1496 /* unsupported, drop it */ 1497 m_free(m0); 1498 continue; 1499 } 1500 start += M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 1501 offset = M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data) + start; 1502 flags |= (start << 1503 GEM_TD_CXSUM_STARTSHFT) | 1504 (offset << 1505 GEM_TD_CXSUM_STUFFSHFT) | 1506 GEM_TD_CXSUM_ENABLE; 1507 } 1508 #endif 1509 } 1510 if (seg == dmamap->dm_nsegs - 1) { 1511 flags |= GEM_TD_END_OF_PACKET; 1512 } else { 1513 /* last flag set outside of loop */ 1514 sc->sc_txdescs[nexttx].gd_flags = 1515 GEM_DMA_WRITE(sc, flags); 1516 } 1517 lasttx = nexttx; 1518 } 1519 if (m0->m_pkthdr.len < ETHER_MIN_TX) { 1520 /* add padding buffer at end of chain */ 1521 flags &= ~GEM_TD_END_OF_PACKET; 1522 sc->sc_txdescs[lasttx].gd_flags = 1523 GEM_DMA_WRITE(sc, flags); 1524 1525 sc->sc_txdescs[nexttx].gd_addr = 1526 GEM_DMA_WRITE(sc, 1527 sc->sc_nulldmamap->dm_segs[0].ds_addr); 1528 flags = ((ETHER_MIN_TX - m0->m_pkthdr.len) & 1529 GEM_TD_BUFSIZE) | GEM_TD_END_OF_PACKET; 1530 lasttx = nexttx; 1531 nexttx = GEM_NEXTTX(nexttx); 1532 seg++; 1533 } 1534 sc->sc_txdescs[lasttx].gd_flags = GEM_DMA_WRITE(sc, flags); 1535 1536 KASSERT(lasttx != -1); 1537 1538 /* 1539 * Store a pointer to the packet so we can free it later, 1540 * and remember what txdirty will be once the packet is 1541 * done. 1542 */ 1543 txs->txs_mbuf = m0; 1544 txs->txs_firstdesc = sc->sc_txnext; 1545 txs->txs_lastdesc = lasttx; 1546 txs->txs_ndescs = seg; 1547 1548 #ifdef GEM_DEBUG 1549 if (ifp->if_flags & IFF_DEBUG) { 1550 printf(" gem_start %p transmit chain:\n", txs); 1551 gem_txsoft_print(sc, txs->txs_firstdesc, 1552 txs->txs_lastdesc); 1553 } 1554 #endif 1555 1556 /* Sync the descriptors we're using. */ 1557 GEM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndescs, 1558 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1559 1560 /* Advance the tx pointer. */ 1561 sc->sc_txfree -= txs->txs_ndescs; 1562 sc->sc_txnext = nexttx; 1563 1564 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1565 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1566 1567 #if NBPFILTER > 0 1568 /* 1569 * Pass the packet to any BPF listeners. 1570 */ 1571 if (ifp->if_bpf) 1572 bpf_mtap(ifp->if_bpf, m0); 1573 #endif /* NBPFILTER > 0 */ 1574 } 1575 1576 if (txs == NULL || sc->sc_txfree == 0) { 1577 /* No more slots left; notify upper layer. */ 1578 ifp->if_flags |= IFF_OACTIVE; 1579 sc->sc_if_flags = ifp->if_flags; 1580 } 1581 1582 if (sc->sc_txfree != ofree) { 1583 DPRINTF(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 1584 device_xname(sc->sc_dev), lasttx, firsttx)); 1585 /* 1586 * The entire packet chain is set up. 1587 * Kick the transmitter. 1588 */ 1589 DPRINTF(sc, ("%s: gem_start: kicking tx %d\n", 1590 device_xname(sc->sc_dev), nexttx)); 1591 bus_space_write_4(sc->sc_bustag, sc->sc_h1, GEM_TX_KICK, 1592 sc->sc_txnext); 1593 1594 /* Set a watchdog timer in case the chip flakes out. */ 1595 ifp->if_timer = 5; 1596 DPRINTF(sc, ("%s: gem_start: watchdog %d\n", 1597 device_xname(sc->sc_dev), ifp->if_timer)); 1598 } 1599 } 1600 1601 /* 1602 * Transmit interrupt. 1603 */ 1604 int 1605 gem_tint(struct gem_softc *sc) 1606 { 1607 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1608 bus_space_tag_t t = sc->sc_bustag; 1609 bus_space_handle_t mac = sc->sc_h1; 1610 struct gem_txsoft *txs; 1611 int txlast; 1612 int progress = 0; 1613 u_int32_t v; 1614 1615 DPRINTF(sc, ("%s: gem_tint\n", device_xname(sc->sc_dev))); 1616 1617 /* Unload collision counters ... */ 1618 v = bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) + 1619 bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT); 1620 ifp->if_collisions += v + 1621 bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) + 1622 bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT); 1623 ifp->if_oerrors += v; 1624 1625 /* ... then clear the hardware counters. */ 1626 bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0); 1627 bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0); 1628 bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0); 1629 bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0); 1630 1631 /* 1632 * Go through our Tx list and free mbufs for those 1633 * frames that have been transmitted. 1634 */ 1635 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1636 /* 1637 * In theory, we could harvest some descriptors before 1638 * the ring is empty, but that's a bit complicated. 1639 * 1640 * GEM_TX_COMPLETION points to the last descriptor 1641 * processed +1. 1642 * 1643 * Let's assume that the NIC writes back to the Tx 1644 * descriptors before it updates the completion 1645 * register. If the NIC has posted writes to the 1646 * Tx descriptors, PCI ordering requires that the 1647 * posted writes flush to RAM before the register-read 1648 * finishes. So let's read the completion register, 1649 * before syncing the descriptors, so that we 1650 * examine Tx descriptors that are at least as 1651 * current as the completion register. 1652 */ 1653 txlast = bus_space_read_4(t, mac, GEM_TX_COMPLETION); 1654 DPRINTF(sc, 1655 ("gem_tint: txs->txs_lastdesc = %d, txlast = %d\n", 1656 txs->txs_lastdesc, txlast)); 1657 if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1658 if (txlast >= txs->txs_firstdesc && 1659 txlast <= txs->txs_lastdesc) 1660 break; 1661 } else if (txlast >= txs->txs_firstdesc || 1662 txlast <= txs->txs_lastdesc) 1663 break; 1664 1665 GEM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndescs, 1666 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1667 1668 #ifdef GEM_DEBUG /* XXX DMA synchronization? */ 1669 if (ifp->if_flags & IFF_DEBUG) { 1670 printf(" txsoft %p transmit chain:\n", txs); 1671 gem_txsoft_print(sc, txs->txs_firstdesc, 1672 txs->txs_lastdesc); 1673 } 1674 #endif 1675 1676 1677 DPRINTF(sc, ("gem_tint: releasing a desc\n")); 1678 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1679 1680 sc->sc_txfree += txs->txs_ndescs; 1681 1682 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 1683 0, txs->txs_dmamap->dm_mapsize, 1684 BUS_DMASYNC_POSTWRITE); 1685 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 1686 if (txs->txs_mbuf != NULL) { 1687 m_freem(txs->txs_mbuf); 1688 txs->txs_mbuf = NULL; 1689 } 1690 1691 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1692 1693 ifp->if_opackets++; 1694 progress = 1; 1695 } 1696 1697 #if 0 1698 DPRINTF(sc, ("gem_tint: GEM_TX_STATE_MACHINE %x " 1699 "GEM_TX_DATA_PTR %" PRIx64 "GEM_TX_COMPLETION %" PRIx32 "\n", 1700 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_TX_STATE_MACHINE), 1701 ((uint64_t)bus_space_read_4(sc->sc_bustag, sc->sc_h1, 1702 GEM_TX_DATA_PTR_HI) << 32) | 1703 bus_space_read_4(sc->sc_bustag, sc->sc_h1, 1704 GEM_TX_DATA_PTR_LO), 1705 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_TX_COMPLETION))); 1706 #endif 1707 1708 if (progress) { 1709 if (sc->sc_txfree == GEM_NTXDESC - 1) 1710 sc->sc_txwin = 0; 1711 1712 /* Freed some descriptors, so reset IFF_OACTIVE and restart. */ 1713 ifp->if_flags &= ~IFF_OACTIVE; 1714 sc->sc_if_flags = ifp->if_flags; 1715 ifp->if_timer = SIMPLEQ_EMPTY(&sc->sc_txdirtyq) ? 0 : 5; 1716 gem_start(ifp); 1717 } 1718 DPRINTF(sc, ("%s: gem_tint: watchdog %d\n", 1719 device_xname(sc->sc_dev), ifp->if_timer)); 1720 1721 return (1); 1722 } 1723 1724 /* 1725 * Receive interrupt. 1726 */ 1727 int 1728 gem_rint(struct gem_softc *sc) 1729 { 1730 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1731 bus_space_tag_t t = sc->sc_bustag; 1732 bus_space_handle_t h = sc->sc_h1; 1733 struct gem_rxsoft *rxs; 1734 struct mbuf *m; 1735 u_int64_t rxstat; 1736 u_int32_t rxcomp; 1737 int i, len, progress = 0; 1738 1739 DPRINTF(sc, ("%s: gem_rint\n", device_xname(sc->sc_dev))); 1740 1741 /* 1742 * Ignore spurious interrupt that sometimes occurs before 1743 * we are set up when we network boot. 1744 */ 1745 if (!sc->sc_meminited) 1746 return 1; 1747 1748 /* 1749 * Read the completion register once. This limits 1750 * how long the following loop can execute. 1751 */ 1752 rxcomp = bus_space_read_4(t, h, GEM_RX_COMPLETION); 1753 1754 /* 1755 * XXX Read the lastrx only once at the top for speed. 1756 */ 1757 DPRINTF(sc, ("gem_rint: sc->rxptr %d, complete %d\n", 1758 sc->sc_rxptr, rxcomp)); 1759 1760 /* 1761 * Go into the loop at least once. 1762 */ 1763 for (i = sc->sc_rxptr; i == sc->sc_rxptr || i != rxcomp; 1764 i = GEM_NEXTRX(i)) { 1765 rxs = &sc->sc_rxsoft[i]; 1766 1767 GEM_CDRXSYNC(sc, i, 1768 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1769 1770 rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags); 1771 1772 if (rxstat & GEM_RD_OWN) { 1773 GEM_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); 1774 /* 1775 * We have processed all of the receive buffers. 1776 */ 1777 break; 1778 } 1779 1780 progress++; 1781 ifp->if_ipackets++; 1782 1783 if (rxstat & GEM_RD_BAD_CRC) { 1784 ifp->if_ierrors++; 1785 aprint_error_dev(sc->sc_dev, 1786 "receive error: CRC error\n"); 1787 GEM_INIT_RXDESC(sc, i); 1788 continue; 1789 } 1790 1791 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1792 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1793 #ifdef GEM_DEBUG 1794 if (ifp->if_flags & IFF_DEBUG) { 1795 printf(" rxsoft %p descriptor %d: ", rxs, i); 1796 printf("gd_flags: 0x%016llx\t", (long long) 1797 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags)); 1798 printf("gd_addr: 0x%016llx\n", (long long) 1799 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr)); 1800 } 1801 #endif 1802 1803 /* No errors; receive the packet. */ 1804 len = GEM_RD_BUFLEN(rxstat); 1805 1806 /* 1807 * Allocate a new mbuf cluster. If that fails, we are 1808 * out of memory, and must drop the packet and recycle 1809 * the buffer that's already attached to this descriptor. 1810 */ 1811 m = rxs->rxs_mbuf; 1812 if (gem_add_rxbuf(sc, i) != 0) { 1813 GEM_COUNTER_INCR(sc, sc_ev_rxnobuf); 1814 ifp->if_ierrors++; 1815 GEM_INIT_RXDESC(sc, i); 1816 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1817 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1818 continue; 1819 } 1820 m->m_data += 2; /* We're already off by two */ 1821 1822 m->m_pkthdr.rcvif = ifp; 1823 m->m_pkthdr.len = m->m_len = len; 1824 1825 #if NBPFILTER > 0 1826 /* 1827 * Pass this up to any BPF listeners, but only 1828 * pass it up the stack if it's for us. 1829 */ 1830 if (ifp->if_bpf) 1831 bpf_mtap(ifp->if_bpf, m); 1832 #endif /* NBPFILTER > 0 */ 1833 1834 #ifdef INET 1835 /* hardware checksum */ 1836 if (ifp->if_csum_flags_rx & M_CSUM_TCPv4) { 1837 struct ether_header *eh; 1838 struct ip *ip; 1839 int32_t hlen, pktlen; 1840 1841 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1842 pktlen = m->m_pkthdr.len - ETHER_HDR_LEN - 1843 ETHER_VLAN_ENCAP_LEN; 1844 eh = (struct ether_header *) (mtod(m, char *) + 1845 ETHER_VLAN_ENCAP_LEN); 1846 } else { 1847 pktlen = m->m_pkthdr.len - ETHER_HDR_LEN; 1848 eh = mtod(m, struct ether_header *); 1849 } 1850 if (ntohs(eh->ether_type) != ETHERTYPE_IP) 1851 goto swcsum; 1852 ip = (struct ip *) ((char *)eh + ETHER_HDR_LEN); 1853 1854 /* IPv4 only */ 1855 if (ip->ip_v != IPVERSION) 1856 goto swcsum; 1857 1858 hlen = ip->ip_hl << 2; 1859 if (hlen < sizeof(struct ip)) 1860 goto swcsum; 1861 1862 /* 1863 * bail if too short, has random trailing garbage, 1864 * truncated, fragment, or has ethernet pad. 1865 */ 1866 if ((ntohs(ip->ip_len) < hlen) || 1867 (ntohs(ip->ip_len) != pktlen) || 1868 (ntohs(ip->ip_off) & (IP_MF | IP_OFFMASK))) 1869 goto swcsum; 1870 1871 switch (ip->ip_p) { 1872 case IPPROTO_TCP: 1873 if (! (ifp->if_csum_flags_rx & M_CSUM_TCPv4)) 1874 goto swcsum; 1875 if (pktlen < (hlen + sizeof(struct tcphdr))) 1876 goto swcsum; 1877 m->m_pkthdr.csum_flags = M_CSUM_TCPv4; 1878 break; 1879 case IPPROTO_UDP: 1880 /* FALLTHROUGH */ 1881 default: 1882 goto swcsum; 1883 } 1884 1885 /* the uncomplemented sum is expected */ 1886 m->m_pkthdr.csum_data = (~rxstat) & GEM_RD_CHECKSUM; 1887 1888 /* if the pkt had ip options, we have to deduct them */ 1889 if (hlen > sizeof(struct ip)) { 1890 uint16_t *opts; 1891 uint32_t optsum, temp; 1892 1893 optsum = 0; 1894 temp = hlen - sizeof(struct ip); 1895 opts = (uint16_t *) ((char *) ip + 1896 sizeof(struct ip)); 1897 1898 while (temp > 1) { 1899 optsum += ntohs(*opts++); 1900 temp -= 2; 1901 } 1902 while (optsum >> 16) 1903 optsum = (optsum >> 16) + 1904 (optsum & 0xffff); 1905 1906 /* Deduct ip opts sum from hwsum. */ 1907 m->m_pkthdr.csum_data += (uint16_t)~optsum; 1908 1909 while (m->m_pkthdr.csum_data >> 16) 1910 m->m_pkthdr.csum_data = 1911 (m->m_pkthdr.csum_data >> 16) + 1912 (m->m_pkthdr.csum_data & 1913 0xffff); 1914 } 1915 1916 m->m_pkthdr.csum_flags |= M_CSUM_DATA | 1917 M_CSUM_NO_PSEUDOHDR; 1918 } else 1919 swcsum: 1920 m->m_pkthdr.csum_flags = 0; 1921 #endif 1922 /* Pass it on. */ 1923 (*ifp->if_input)(ifp, m); 1924 } 1925 1926 if (progress) { 1927 /* Update the receive pointer. */ 1928 if (i == sc->sc_rxptr) { 1929 GEM_COUNTER_INCR(sc, sc_ev_rxfull); 1930 #ifdef GEM_DEBUG 1931 if (ifp->if_flags & IFF_DEBUG) 1932 printf("%s: rint: ring wrap\n", 1933 device_xname(sc->sc_dev)); 1934 #endif 1935 } 1936 sc->sc_rxptr = i; 1937 bus_space_write_4(t, h, GEM_RX_KICK, GEM_PREVRX(i)); 1938 } 1939 #ifdef GEM_COUNTERS 1940 if (progress <= 4) { 1941 GEM_COUNTER_INCR(sc, sc_ev_rxhist[progress]); 1942 } else if (progress < 32) { 1943 if (progress < 16) 1944 GEM_COUNTER_INCR(sc, sc_ev_rxhist[5]); 1945 else 1946 GEM_COUNTER_INCR(sc, sc_ev_rxhist[6]); 1947 1948 } else { 1949 if (progress < 64) 1950 GEM_COUNTER_INCR(sc, sc_ev_rxhist[7]); 1951 else 1952 GEM_COUNTER_INCR(sc, sc_ev_rxhist[8]); 1953 } 1954 #endif 1955 1956 DPRINTF(sc, ("gem_rint: done sc->rxptr %d, complete %d\n", 1957 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION))); 1958 1959 /* Read error counters ... */ 1960 ifp->if_ierrors += 1961 bus_space_read_4(t, h, GEM_MAC_RX_LEN_ERR_CNT) + 1962 bus_space_read_4(t, h, GEM_MAC_RX_ALIGN_ERR) + 1963 bus_space_read_4(t, h, GEM_MAC_RX_CRC_ERR_CNT) + 1964 bus_space_read_4(t, h, GEM_MAC_RX_CODE_VIOL); 1965 1966 /* ... then clear the hardware counters. */ 1967 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 1968 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 1969 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 1970 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 1971 1972 return (1); 1973 } 1974 1975 1976 /* 1977 * gem_add_rxbuf: 1978 * 1979 * Add a receive buffer to the indicated descriptor. 1980 */ 1981 int 1982 gem_add_rxbuf(struct gem_softc *sc, int idx) 1983 { 1984 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1985 struct mbuf *m; 1986 int error; 1987 1988 MGETHDR(m, M_DONTWAIT, MT_DATA); 1989 if (m == NULL) 1990 return (ENOBUFS); 1991 1992 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1993 MCLGET(m, M_DONTWAIT); 1994 if ((m->m_flags & M_EXT) == 0) { 1995 m_freem(m); 1996 return (ENOBUFS); 1997 } 1998 1999 #ifdef GEM_DEBUG 2000 /* bzero the packet to check DMA */ 2001 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 2002 #endif 2003 2004 if (rxs->rxs_mbuf != NULL) 2005 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 2006 2007 rxs->rxs_mbuf = m; 2008 2009 error = bus_dmamap_load(sc->sc_dmatag, rxs->rxs_dmamap, 2010 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2011 BUS_DMA_READ|BUS_DMA_NOWAIT); 2012 if (error) { 2013 aprint_error_dev(sc->sc_dev, 2014 "can't load rx DMA map %d, error = %d\n", idx, error); 2015 panic("gem_add_rxbuf"); /* XXX */ 2016 } 2017 2018 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 2019 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2020 2021 GEM_INIT_RXDESC(sc, idx); 2022 2023 return (0); 2024 } 2025 2026 2027 int 2028 gem_eint(struct gem_softc *sc, u_int status) 2029 { 2030 char bits[128]; 2031 u_int32_t r, v; 2032 2033 if ((status & GEM_INTR_MIF) != 0) { 2034 printf("%s: XXXlink status changed\n", device_xname(sc->sc_dev)); 2035 return (1); 2036 } 2037 2038 if ((status & GEM_INTR_RX_TAG_ERR) != 0) { 2039 gem_reset_rxdma(sc); 2040 return (1); 2041 } 2042 2043 if (status & GEM_INTR_BERR) { 2044 if (sc->sc_flags & GEM_PCI) 2045 r = GEM_ERROR_STATUS; 2046 else 2047 r = GEM_SBUS_ERROR_STATUS; 2048 bus_space_read_4(sc->sc_bustag, sc->sc_h2, r); 2049 v = bus_space_read_4(sc->sc_bustag, sc->sc_h2, r); 2050 aprint_error_dev(sc->sc_dev, "bus error interrupt: 0x%02x\n", 2051 v); 2052 return (1); 2053 } 2054 snprintb(bits, sizeof(bits), GEM_INTR_BITS, status); 2055 printf("%s: status=%s\n", device_xname(sc->sc_dev), bits); 2056 2057 return (1); 2058 } 2059 2060 2061 /* 2062 * PCS interrupts. 2063 * We should receive these when the link status changes, but sometimes 2064 * we don't receive them for link up. We compensate for this in the 2065 * gem_tick() callout. 2066 */ 2067 int 2068 gem_pint(struct gem_softc *sc) 2069 { 2070 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2071 bus_space_tag_t t = sc->sc_bustag; 2072 bus_space_handle_t h = sc->sc_h1; 2073 u_int32_t v, v2; 2074 2075 /* 2076 * Clear the PCS interrupt from GEM_STATUS. The PCS register is 2077 * latched, so we have to read it twice. There is only one bit in 2078 * use, so the value is meaningless. 2079 */ 2080 bus_space_read_4(t, h, GEM_MII_INTERRUP_STATUS); 2081 bus_space_read_4(t, h, GEM_MII_INTERRUP_STATUS); 2082 2083 if ((ifp->if_flags & IFF_UP) == 0) 2084 return 1; 2085 2086 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) 2087 return 1; 2088 2089 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2090 /* If we see remote fault, our link partner is probably going away */ 2091 if ((v & GEM_MII_STATUS_REM_FLT) != 0) { 2092 gem_bitwait(sc, h, GEM_MII_STATUS, GEM_MII_STATUS_REM_FLT, 0); 2093 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2094 /* Otherwise, we may need to wait after auto-negotiation completes */ 2095 } else if ((v & (GEM_MII_STATUS_LINK_STS | GEM_MII_STATUS_ANEG_CPT)) == 2096 GEM_MII_STATUS_ANEG_CPT) { 2097 gem_bitwait(sc, h, GEM_MII_STATUS, 0, GEM_MII_STATUS_LINK_STS); 2098 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2099 } 2100 if ((v & GEM_MII_STATUS_LINK_STS) != 0) { 2101 if (sc->sc_flags & GEM_LINK) { 2102 return 1; 2103 } 2104 callout_stop(&sc->sc_tick_ch); 2105 v = bus_space_read_4(t, h, GEM_MII_ANAR); 2106 v2 = bus_space_read_4(t, h, GEM_MII_ANLPAR); 2107 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_1000_SX; 2108 sc->sc_mii.mii_media_status = IFM_AVALID | IFM_ACTIVE; 2109 v &= v2; 2110 if (v & GEM_MII_ANEG_FUL_DUPLX) { 2111 sc->sc_mii.mii_media_active |= IFM_FDX; 2112 #ifdef GEM_DEBUG 2113 aprint_debug_dev(sc->sc_dev, "link up: full duplex\n"); 2114 #endif 2115 } else if (v & GEM_MII_ANEG_HLF_DUPLX) { 2116 sc->sc_mii.mii_media_active |= IFM_HDX; 2117 #ifdef GEM_DEBUG 2118 aprint_debug_dev(sc->sc_dev, "link up: half duplex\n"); 2119 #endif 2120 } else { 2121 #ifdef GEM_DEBUG 2122 aprint_debug_dev(sc->sc_dev, "duplex mismatch\n"); 2123 #endif 2124 } 2125 gem_statuschange(sc); 2126 } else { 2127 if ((sc->sc_flags & GEM_LINK) == 0) { 2128 return 1; 2129 } 2130 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_NONE; 2131 sc->sc_mii.mii_media_status = IFM_AVALID; 2132 #ifdef GEM_DEBUG 2133 aprint_debug_dev(sc->sc_dev, "link down\n"); 2134 #endif 2135 gem_statuschange(sc); 2136 2137 /* Start the 10 second timer */ 2138 callout_reset(&sc->sc_tick_ch, hz * 10, gem_tick, sc); 2139 } 2140 return 1; 2141 } 2142 2143 2144 2145 int 2146 gem_intr(void *v) 2147 { 2148 struct gem_softc *sc = v; 2149 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2150 bus_space_tag_t t = sc->sc_bustag; 2151 bus_space_handle_t h = sc->sc_h1; 2152 u_int32_t status; 2153 int r = 0; 2154 #ifdef GEM_DEBUG 2155 char bits[128]; 2156 #endif 2157 2158 /* XXX We should probably mask out interrupts until we're done */ 2159 2160 sc->sc_ev_intr.ev_count++; 2161 2162 status = bus_space_read_4(t, h, GEM_STATUS); 2163 #ifdef GEM_DEBUG 2164 snprintb(bits, sizeof(bits), GEM_INTR_BITS, status); 2165 #endif 2166 DPRINTF(sc, ("%s: gem_intr: cplt 0x%x status %s\n", 2167 device_xname(sc->sc_dev), (status >> 19), bits)); 2168 2169 2170 if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0) 2171 r |= gem_eint(sc, status); 2172 2173 /* We don't bother with GEM_INTR_TX_DONE */ 2174 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) { 2175 GEM_COUNTER_INCR(sc, sc_ev_txint); 2176 r |= gem_tint(sc); 2177 } 2178 2179 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) { 2180 GEM_COUNTER_INCR(sc, sc_ev_rxint); 2181 r |= gem_rint(sc); 2182 } 2183 2184 /* We should eventually do more than just print out error stats. */ 2185 if (status & GEM_INTR_TX_MAC) { 2186 int txstat = bus_space_read_4(t, h, GEM_MAC_TX_STATUS); 2187 if (txstat & ~GEM_MAC_TX_XMIT_DONE) 2188 printf("%s: MAC tx fault, status %x\n", 2189 device_xname(sc->sc_dev), txstat); 2190 if (txstat & (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG)) 2191 gem_init(ifp); 2192 } 2193 if (status & GEM_INTR_RX_MAC) { 2194 int rxstat = bus_space_read_4(t, h, GEM_MAC_RX_STATUS); 2195 /* 2196 * At least with GEM_SUN_GEM and some GEM_SUN_ERI 2197 * revisions GEM_MAC_RX_OVERFLOW happen often due to a 2198 * silicon bug so handle them silently. Moreover, it's 2199 * likely that the receiver has hung so we reset it. 2200 */ 2201 if (rxstat & GEM_MAC_RX_OVERFLOW) { 2202 ifp->if_ierrors++; 2203 gem_reset_rxdma(sc); 2204 } else if (rxstat & ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT)) 2205 printf("%s: MAC rx fault, status 0x%02x\n", 2206 device_xname(sc->sc_dev), rxstat); 2207 } 2208 if (status & GEM_INTR_PCS) { 2209 r |= gem_pint(sc); 2210 } 2211 2212 /* Do we need to do anything with these? 2213 if ((status & GEM_MAC_CONTROL_STATUS) != 0) { 2214 status2 = bus_read_4(sc->sc_res[0], GEM_MAC_CONTROL_STATUS); 2215 if ((status2 & GEM_MAC_PAUSED) != 0) 2216 aprintf_debug_dev(sc->sc_dev, "PAUSE received (%d slots)\n", 2217 GEM_MAC_PAUSE_TIME(status2)); 2218 if ((status2 & GEM_MAC_PAUSE) != 0) 2219 aprintf_debug_dev(sc->sc_dev, "transited to PAUSE state\n"); 2220 if ((status2 & GEM_MAC_RESUME) != 0) 2221 aprintf_debug_dev(sc->sc_dev, "transited to non-PAUSE state\n"); 2222 } 2223 if ((status & GEM_INTR_MIF) != 0) 2224 aprintf_debug_dev(sc->sc_dev, "MIF interrupt\n"); 2225 */ 2226 #if NRND > 0 2227 rnd_add_uint32(&sc->rnd_source, status); 2228 #endif 2229 return (r); 2230 } 2231 2232 2233 void 2234 gem_watchdog(struct ifnet *ifp) 2235 { 2236 struct gem_softc *sc = ifp->if_softc; 2237 2238 DPRINTF(sc, ("gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x " 2239 "GEM_MAC_RX_CONFIG %x\n", 2240 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_RX_CONFIG), 2241 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_MAC_RX_STATUS), 2242 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_MAC_RX_CONFIG))); 2243 2244 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 2245 ++ifp->if_oerrors; 2246 2247 /* Try to get more packets going. */ 2248 gem_start(ifp); 2249 } 2250 2251 /* 2252 * Initialize the MII Management Interface 2253 */ 2254 void 2255 gem_mifinit(struct gem_softc *sc) 2256 { 2257 bus_space_tag_t t = sc->sc_bustag; 2258 bus_space_handle_t mif = sc->sc_h1; 2259 2260 /* Configure the MIF in frame mode */ 2261 sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 2262 sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA; 2263 bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config); 2264 } 2265 2266 /* 2267 * MII interface 2268 * 2269 * The GEM MII interface supports at least three different operating modes: 2270 * 2271 * Bitbang mode is implemented using data, clock and output enable registers. 2272 * 2273 * Frame mode is implemented by loading a complete frame into the frame 2274 * register and polling the valid bit for completion. 2275 * 2276 * Polling mode uses the frame register but completion is indicated by 2277 * an interrupt. 2278 * 2279 */ 2280 static int 2281 gem_mii_readreg(device_t self, int phy, int reg) 2282 { 2283 struct gem_softc *sc = device_private(self); 2284 bus_space_tag_t t = sc->sc_bustag; 2285 bus_space_handle_t mif = sc->sc_h1; 2286 int n; 2287 u_int32_t v; 2288 2289 #ifdef GEM_DEBUG1 2290 if (sc->sc_debug) 2291 printf("gem_mii_readreg: PHY %d reg %d\n", phy, reg); 2292 #endif 2293 2294 /* Construct the frame command */ 2295 v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) | 2296 GEM_MIF_FRAME_READ; 2297 2298 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 2299 for (n = 0; n < 100; n++) { 2300 DELAY(1); 2301 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 2302 if (v & GEM_MIF_FRAME_TA0) 2303 return (v & GEM_MIF_FRAME_DATA); 2304 } 2305 2306 printf("%s: mii_read timeout\n", device_xname(sc->sc_dev)); 2307 return (0); 2308 } 2309 2310 static void 2311 gem_mii_writereg(device_t self, int phy, int reg, int val) 2312 { 2313 struct gem_softc *sc = device_private(self); 2314 bus_space_tag_t t = sc->sc_bustag; 2315 bus_space_handle_t mif = sc->sc_h1; 2316 int n; 2317 u_int32_t v; 2318 2319 #ifdef GEM_DEBUG1 2320 if (sc->sc_debug) 2321 printf("gem_mii_writereg: PHY %d reg %d val %x\n", 2322 phy, reg, val); 2323 #endif 2324 2325 /* Construct the frame command */ 2326 v = GEM_MIF_FRAME_WRITE | 2327 (phy << GEM_MIF_PHY_SHIFT) | 2328 (reg << GEM_MIF_REG_SHIFT) | 2329 (val & GEM_MIF_FRAME_DATA); 2330 2331 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 2332 for (n = 0; n < 100; n++) { 2333 DELAY(1); 2334 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 2335 if (v & GEM_MIF_FRAME_TA0) 2336 return; 2337 } 2338 2339 printf("%s: mii_write timeout\n", device_xname(sc->sc_dev)); 2340 } 2341 2342 static void 2343 gem_mii_statchg(device_t self) 2344 { 2345 struct gem_softc *sc = device_private(self); 2346 #ifdef GEM_DEBUG 2347 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 2348 #endif 2349 2350 #ifdef GEM_DEBUG 2351 if (sc->sc_debug) 2352 printf("gem_mii_statchg: status change: phy = %d\n", 2353 sc->sc_phys[instance]); 2354 #endif 2355 gem_statuschange(sc); 2356 } 2357 2358 /* 2359 * Common status change for gem_mii_statchg() and gem_pint() 2360 */ 2361 void 2362 gem_statuschange(struct gem_softc* sc) 2363 { 2364 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2365 bus_space_tag_t t = sc->sc_bustag; 2366 bus_space_handle_t mac = sc->sc_h1; 2367 int gigabit; 2368 u_int32_t rxcfg, txcfg, v; 2369 2370 if ((sc->sc_mii.mii_media_status & IFM_ACTIVE) != 0 && 2371 IFM_SUBTYPE(sc->sc_mii.mii_media_active) != IFM_NONE) 2372 sc->sc_flags |= GEM_LINK; 2373 else 2374 sc->sc_flags &= ~GEM_LINK; 2375 2376 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 2377 gigabit = 1; 2378 else 2379 gigabit = 0; 2380 2381 /* 2382 * The configuration done here corresponds to the steps F) and 2383 * G) and as far as enabling of RX and TX MAC goes also step H) 2384 * of the initialization sequence outlined in section 3.2.1 of 2385 * the GEM Gigabit Ethernet ASIC Specification. 2386 */ 2387 2388 rxcfg = bus_space_read_4(t, mac, GEM_MAC_RX_CONFIG); 2389 rxcfg &= ~(GEM_MAC_RX_CARR_EXTEND | GEM_MAC_RX_ENABLE); 2390 txcfg = GEM_MAC_TX_ENA_IPG0 | GEM_MAC_TX_NGU | GEM_MAC_TX_NGU_LIMIT; 2391 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 2392 txcfg |= GEM_MAC_TX_IGN_CARRIER | GEM_MAC_TX_IGN_COLLIS; 2393 else if (gigabit) { 2394 rxcfg |= GEM_MAC_RX_CARR_EXTEND; 2395 txcfg |= GEM_MAC_RX_CARR_EXTEND; 2396 } 2397 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0); 2398 bus_space_barrier(t, mac, GEM_MAC_TX_CONFIG, 4, 2399 BUS_SPACE_BARRIER_WRITE); 2400 if (!gem_bitwait(sc, mac, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)) 2401 aprint_normal_dev(sc->sc_dev, "cannot disable TX MAC\n"); 2402 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, txcfg); 2403 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, 0); 2404 bus_space_barrier(t, mac, GEM_MAC_RX_CONFIG, 4, 2405 BUS_SPACE_BARRIER_WRITE); 2406 if (!gem_bitwait(sc, mac, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)) 2407 aprint_normal_dev(sc->sc_dev, "cannot disable RX MAC\n"); 2408 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, rxcfg); 2409 2410 v = bus_space_read_4(t, mac, GEM_MAC_CONTROL_CONFIG) & 2411 ~(GEM_MAC_CC_RX_PAUSE | GEM_MAC_CC_TX_PAUSE); 2412 bus_space_write_4(t, mac, GEM_MAC_CONTROL_CONFIG, v); 2413 2414 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) == 0 && 2415 gigabit != 0) 2416 bus_space_write_4(t, mac, GEM_MAC_SLOT_TIME, 2417 GEM_MAC_SLOT_TIME_CARR_EXTEND); 2418 else 2419 bus_space_write_4(t, mac, GEM_MAC_SLOT_TIME, 2420 GEM_MAC_SLOT_TIME_NORMAL); 2421 2422 /* XIF Configuration */ 2423 if (sc->sc_flags & GEM_LINK) 2424 v = GEM_MAC_XIF_LINK_LED; 2425 else 2426 v = 0; 2427 v |= GEM_MAC_XIF_TX_MII_ENA; 2428 2429 /* If an external transceiver is connected, enable its MII drivers */ 2430 sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG); 2431 if ((sc->sc_flags &(GEM_SERDES | GEM_SERIAL)) == 0) { 2432 if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) { 2433 /* External MII needs echo disable if half duplex. */ 2434 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & 2435 IFM_FDX) != 0) 2436 /* turn on full duplex LED */ 2437 v |= GEM_MAC_XIF_FDPLX_LED; 2438 else 2439 /* half duplex -- disable echo */ 2440 v |= GEM_MAC_XIF_ECHO_DISABL; 2441 if (gigabit) 2442 v |= GEM_MAC_XIF_GMII_MODE; 2443 else 2444 v &= ~GEM_MAC_XIF_GMII_MODE; 2445 } else 2446 /* Internal MII needs buf enable */ 2447 v |= GEM_MAC_XIF_MII_BUF_ENA; 2448 } else { 2449 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 2450 v |= GEM_MAC_XIF_FDPLX_LED; 2451 v |= GEM_MAC_XIF_GMII_MODE; 2452 } 2453 bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v); 2454 2455 if ((ifp->if_flags & IFF_RUNNING) != 0 && 2456 (sc->sc_flags & GEM_LINK) != 0) { 2457 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 2458 txcfg | GEM_MAC_TX_ENABLE); 2459 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, 2460 rxcfg | GEM_MAC_RX_ENABLE); 2461 } 2462 } 2463 2464 int 2465 gem_ser_mediachange(struct ifnet *ifp) 2466 { 2467 struct gem_softc *sc = ifp->if_softc; 2468 u_int s, t; 2469 2470 if (IFM_TYPE(sc->sc_mii.mii_media.ifm_media) != IFM_ETHER) 2471 return EINVAL; 2472 2473 s = IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media); 2474 if (s == IFM_AUTO) { 2475 if (sc->sc_mii_media != s) { 2476 #ifdef GEM_DEBUG 2477 aprint_debug_dev(sc->sc_dev, "setting media to auto\n"); 2478 #endif 2479 sc->sc_mii_media = s; 2480 if (ifp->if_flags & IFF_UP) { 2481 gem_pcs_stop(sc, 0); 2482 gem_pcs_start(sc); 2483 } 2484 } 2485 return 0; 2486 } 2487 if (s == IFM_1000_SX) { 2488 t = IFM_OPTIONS(sc->sc_mii.mii_media.ifm_media); 2489 if (t == IFM_FDX || t == IFM_HDX) { 2490 if (sc->sc_mii_media != t) { 2491 sc->sc_mii_media = t; 2492 #ifdef GEM_DEBUG 2493 aprint_debug_dev(sc->sc_dev, 2494 "setting media to 1000baseSX-%s\n", 2495 t == IFM_FDX ? "FDX" : "HDX"); 2496 #endif 2497 if (ifp->if_flags & IFF_UP) { 2498 gem_pcs_stop(sc, 0); 2499 gem_pcs_start(sc); 2500 } 2501 } 2502 return 0; 2503 } 2504 } 2505 return EINVAL; 2506 } 2507 2508 void 2509 gem_ser_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2510 { 2511 struct gem_softc *sc = ifp->if_softc; 2512 2513 if ((ifp->if_flags & IFF_UP) == 0) 2514 return; 2515 ifmr->ifm_active = sc->sc_mii.mii_media_active; 2516 ifmr->ifm_status = sc->sc_mii.mii_media_status; 2517 } 2518 2519 static int 2520 gem_ifflags_cb(struct ethercom *ec) 2521 { 2522 struct ifnet *ifp = &ec->ec_if; 2523 struct gem_softc *sc = ifp->if_softc; 2524 int change = ifp->if_flags ^ sc->sc_if_flags; 2525 2526 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 2527 return ENETRESET; 2528 else if ((change & IFF_PROMISC) != 0) 2529 gem_setladrf(sc); 2530 return 0; 2531 } 2532 2533 /* 2534 * Process an ioctl request. 2535 */ 2536 int 2537 gem_ioctl(struct ifnet *ifp, unsigned long cmd, void *data) 2538 { 2539 struct gem_softc *sc = ifp->if_softc; 2540 int s, error = 0; 2541 2542 s = splnet(); 2543 2544 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2545 error = 0; 2546 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 2547 ; 2548 else if (ifp->if_flags & IFF_RUNNING) { 2549 /* 2550 * Multicast list has changed; set the hardware filter 2551 * accordingly. 2552 */ 2553 gem_setladrf(sc); 2554 } 2555 } 2556 2557 /* Try to get things going again */ 2558 if (ifp->if_flags & IFF_UP) 2559 gem_start(ifp); 2560 splx(s); 2561 return (error); 2562 } 2563 2564 static void 2565 gem_inten(struct gem_softc *sc) 2566 { 2567 bus_space_tag_t t = sc->sc_bustag; 2568 bus_space_handle_t h = sc->sc_h1; 2569 uint32_t v; 2570 2571 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 2572 v = GEM_INTR_PCS; 2573 else 2574 v = GEM_INTR_MIF; 2575 bus_space_write_4(t, h, GEM_INTMASK, 2576 ~(GEM_INTR_TX_INTME | 2577 GEM_INTR_TX_EMPTY | 2578 GEM_INTR_TX_MAC | 2579 GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF| 2580 GEM_INTR_RX_TAG_ERR | GEM_INTR_MAC_CONTROL| 2581 GEM_INTR_BERR | v)); 2582 } 2583 2584 bool 2585 gem_resume(device_t self PMF_FN_ARGS) 2586 { 2587 struct gem_softc *sc = device_private(self); 2588 2589 gem_inten(sc); 2590 2591 return true; 2592 } 2593 2594 bool 2595 gem_suspend(device_t self PMF_FN_ARGS) 2596 { 2597 struct gem_softc *sc = device_private(self); 2598 bus_space_tag_t t = sc->sc_bustag; 2599 bus_space_handle_t h = sc->sc_h1; 2600 2601 bus_space_write_4(t, h, GEM_INTMASK, ~(uint32_t)0); 2602 2603 return true; 2604 } 2605 2606 bool 2607 gem_shutdown(device_t self, int howto) 2608 { 2609 struct gem_softc *sc = device_private(self); 2610 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2611 2612 gem_stop(ifp, 1); 2613 2614 return true; 2615 } 2616 2617 /* 2618 * Set up the logical address filter. 2619 */ 2620 void 2621 gem_setladrf(struct gem_softc *sc) 2622 { 2623 struct ethercom *ec = &sc->sc_ethercom; 2624 struct ifnet *ifp = &ec->ec_if; 2625 struct ether_multi *enm; 2626 struct ether_multistep step; 2627 bus_space_tag_t t = sc->sc_bustag; 2628 bus_space_handle_t h = sc->sc_h1; 2629 u_int32_t crc; 2630 u_int32_t hash[16]; 2631 u_int32_t v; 2632 int i; 2633 2634 /* Get current RX configuration */ 2635 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 2636 2637 /* 2638 * Turn off promiscuous mode, promiscuous group mode (all multicast), 2639 * and hash filter. Depending on the case, the right bit will be 2640 * enabled. 2641 */ 2642 v &= ~(GEM_MAC_RX_PROMISCUOUS|GEM_MAC_RX_HASH_FILTER| 2643 GEM_MAC_RX_PROMISC_GRP); 2644 2645 if ((ifp->if_flags & IFF_PROMISC) != 0) { 2646 /* Turn on promiscuous mode */ 2647 v |= GEM_MAC_RX_PROMISCUOUS; 2648 ifp->if_flags |= IFF_ALLMULTI; 2649 goto chipit; 2650 } 2651 2652 /* 2653 * Set up multicast address filter by passing all multicast addresses 2654 * through a crc generator, and then using the high order 8 bits as an 2655 * index into the 256 bit logical address filter. The high order 4 2656 * bits selects the word, while the other 4 bits select the bit within 2657 * the word (where bit 0 is the MSB). 2658 */ 2659 2660 /* Clear hash table */ 2661 memset(hash, 0, sizeof(hash)); 2662 2663 ETHER_FIRST_MULTI(step, ec, enm); 2664 while (enm != NULL) { 2665 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2666 /* 2667 * We must listen to a range of multicast addresses. 2668 * For now, just accept all multicasts, rather than 2669 * trying to set only those filter bits needed to match 2670 * the range. (At this time, the only use of address 2671 * ranges is for IP multicast routing, for which the 2672 * range is big enough to require all bits set.) 2673 * XXX should use the address filters for this 2674 */ 2675 ifp->if_flags |= IFF_ALLMULTI; 2676 v |= GEM_MAC_RX_PROMISC_GRP; 2677 goto chipit; 2678 } 2679 2680 /* Get the LE CRC32 of the address */ 2681 crc = ether_crc32_le(enm->enm_addrlo, sizeof(enm->enm_addrlo)); 2682 2683 /* Just want the 8 most significant bits. */ 2684 crc >>= 24; 2685 2686 /* Set the corresponding bit in the filter. */ 2687 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 2688 2689 ETHER_NEXT_MULTI(step, enm); 2690 } 2691 2692 v |= GEM_MAC_RX_HASH_FILTER; 2693 ifp->if_flags &= ~IFF_ALLMULTI; 2694 2695 /* Now load the hash table into the chip (if we are using it) */ 2696 for (i = 0; i < 16; i++) { 2697 bus_space_write_4(t, h, 2698 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1-GEM_MAC_HASH0), 2699 hash[i]); 2700 } 2701 2702 chipit: 2703 sc->sc_if_flags = ifp->if_flags; 2704 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 2705 } 2706
Indexes created Tue Sep 23 14:10:03 GMT 2025