gem.c revision 1.88
1 /* $NetBSD: gem.c,v 1.88 2009/12/04 22:13:26 martin Exp $ */ 2 3 /* 4 * 5 * Copyright (C) 2001 Eduardo Horvath. 6 * Copyright (c) 2001-2003 Thomas Moestl 7 * All rights reserved. 8 * 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 */ 32 33 /* 34 * Driver for Apple GMAC, Sun ERI and Sun GEM Ethernet controllers 35 * See `GEM Gigabit Ethernet ASIC Specification' 36 * http://www.sun.com/processors/manuals/ge.pdf 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: gem.c,v 1.88 2009/12/04 22:13:26 martin Exp $"); 41 42 #include "opt_inet.h" 43 #include "bpfilter.h" 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/callout.h> 48 #include <sys/mbuf.h> 49 #include <sys/syslog.h> 50 #include <sys/malloc.h> 51 #include <sys/kernel.h> 52 #include <sys/socket.h> 53 #include <sys/ioctl.h> 54 #include <sys/errno.h> 55 #include <sys/device.h> 56 57 #include <machine/endian.h> 58 59 #include <uvm/uvm_extern.h> 60 61 #include <net/if.h> 62 #include <net/if_dl.h> 63 #include <net/if_media.h> 64 #include <net/if_ether.h> 65 66 #ifdef INET 67 #include <netinet/in.h> 68 #include <netinet/in_systm.h> 69 #include <netinet/in_var.h> 70 #include <netinet/ip.h> 71 #include <netinet/tcp.h> 72 #include <netinet/udp.h> 73 #endif 74 75 #if NBPFILTER > 0 76 #include <net/bpf.h> 77 #endif 78 79 #include <sys/bus.h> 80 #include <sys/intr.h> 81 82 #include <dev/mii/mii.h> 83 #include <dev/mii/miivar.h> 84 #include <dev/mii/mii_bitbang.h> 85 86 #include <dev/ic/gemreg.h> 87 #include <dev/ic/gemvar.h> 88 89 #define TRIES 10000 90 91 static void gem_inten(struct gem_softc *); 92 static void gem_start(struct ifnet *); 93 static void gem_stop(struct ifnet *, int); 94 int gem_ioctl(struct ifnet *, u_long, void *); 95 void gem_tick(void *); 96 void gem_watchdog(struct ifnet *); 97 void gem_pcs_start(struct gem_softc *sc); 98 void gem_pcs_stop(struct gem_softc *sc, int); 99 int gem_init(struct ifnet *); 100 void gem_init_regs(struct gem_softc *sc); 101 static int gem_ringsize(int sz); 102 static int gem_meminit(struct gem_softc *); 103 void gem_mifinit(struct gem_softc *); 104 static int gem_bitwait(struct gem_softc *sc, bus_space_handle_t, int, 105 u_int32_t, u_int32_t); 106 void gem_reset(struct gem_softc *); 107 int gem_reset_rx(struct gem_softc *sc); 108 static void gem_reset_rxdma(struct gem_softc *sc); 109 static void gem_rx_common(struct gem_softc *sc); 110 int gem_reset_tx(struct gem_softc *sc); 111 int gem_disable_rx(struct gem_softc *sc); 112 int gem_disable_tx(struct gem_softc *sc); 113 static void gem_rxdrain(struct gem_softc *sc); 114 int gem_add_rxbuf(struct gem_softc *sc, int idx); 115 void gem_setladrf(struct gem_softc *); 116 117 /* MII methods & callbacks */ 118 static int gem_mii_readreg(device_t, int, int); 119 static void gem_mii_writereg(device_t, int, int, int); 120 static void gem_mii_statchg(device_t); 121 122 static int gem_ifflags_cb(struct ethercom *); 123 124 void gem_statuschange(struct gem_softc *); 125 126 int gem_ser_mediachange(struct ifnet *); 127 void gem_ser_mediastatus(struct ifnet *, struct ifmediareq *); 128 129 static void gem_partial_detach(struct gem_softc *, enum gem_attach_stage); 130 131 struct mbuf *gem_get(struct gem_softc *, int, int); 132 int gem_put(struct gem_softc *, int, struct mbuf *); 133 void gem_read(struct gem_softc *, int, int); 134 int gem_pint(struct gem_softc *); 135 int gem_eint(struct gem_softc *, u_int); 136 int gem_rint(struct gem_softc *); 137 int gem_tint(struct gem_softc *); 138 void gem_power(int, void *); 139 140 #ifdef GEM_DEBUG 141 static void gem_txsoft_print(const struct gem_softc *, int, int); 142 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 143 printf x 144 #else 145 #define DPRINTF(sc, x) /* nothing */ 146 #endif 147 148 #define ETHER_MIN_TX (ETHERMIN + sizeof(struct ether_header)) 149 150 int 151 gem_detach(struct gem_softc *sc, int flags) 152 { 153 int i; 154 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 155 156 /* 157 * Free any resources we've allocated during the attach. 158 * Do this in reverse order and fall through. 159 */ 160 switch (sc->sc_att_stage) { 161 case GEM_ATT_BACKEND_2: 162 case GEM_ATT_BACKEND_1: 163 case GEM_ATT_FINISHED: 164 gem_stop(&sc->sc_ethercom.ec_if, 1); 165 166 #ifdef GEM_COUNTERS 167 for (i = __arraycount(sc->sc_ev_rxhist); --i >= 0; ) 168 evcnt_detach(&sc->sc_ev_rxhist[i]); 169 evcnt_detach(&sc->sc_ev_rxnobuf); 170 evcnt_detach(&sc->sc_ev_rxfull); 171 evcnt_detach(&sc->sc_ev_rxint); 172 evcnt_detach(&sc->sc_ev_txint); 173 #endif 174 evcnt_detach(&sc->sc_ev_intr); 175 176 #if NRND > 0 177 rnd_detach_source(&sc->rnd_source); 178 #endif 179 ether_ifdetach(ifp); 180 if_detach(ifp); 181 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 182 183 callout_destroy(&sc->sc_tick_ch); 184 185 /*FALLTHROUGH*/ 186 case GEM_ATT_MII: 187 sc->sc_att_stage = GEM_ATT_MII; 188 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 189 /*FALLTHROUGH*/ 190 case GEM_ATT_7: 191 for (i = 0; i < GEM_NRXDESC; i++) { 192 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 193 bus_dmamap_destroy(sc->sc_dmatag, 194 sc->sc_rxsoft[i].rxs_dmamap); 195 } 196 /*FALLTHROUGH*/ 197 case GEM_ATT_6: 198 for (i = 0; i < GEM_TXQUEUELEN; i++) { 199 if (sc->sc_txsoft[i].txs_dmamap != NULL) 200 bus_dmamap_destroy(sc->sc_dmatag, 201 sc->sc_txsoft[i].txs_dmamap); 202 } 203 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 204 /*FALLTHROUGH*/ 205 case GEM_ATT_5: 206 bus_dmamap_unload(sc->sc_dmatag, sc->sc_nulldmamap); 207 /*FALLTHROUGH*/ 208 case GEM_ATT_4: 209 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_nulldmamap); 210 /*FALLTHROUGH*/ 211 case GEM_ATT_3: 212 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 213 /*FALLTHROUGH*/ 214 case GEM_ATT_2: 215 bus_dmamem_unmap(sc->sc_dmatag, sc->sc_control_data, 216 sizeof(struct gem_control_data)); 217 /*FALLTHROUGH*/ 218 case GEM_ATT_1: 219 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 220 /*FALLTHROUGH*/ 221 case GEM_ATT_0: 222 sc->sc_att_stage = GEM_ATT_0; 223 /*FALLTHROUGH*/ 224 case GEM_ATT_BACKEND_0: 225 break; 226 } 227 return 0; 228 } 229 230 static void 231 gem_partial_detach(struct gem_softc *sc, enum gem_attach_stage stage) 232 { 233 cfattach_t ca = device_cfattach(sc->sc_dev); 234 235 sc->sc_att_stage = stage; 236 (*ca->ca_detach)(sc->sc_dev, 0); 237 } 238 239 /* 240 * gem_attach: 241 * 242 * Attach a Gem interface to the system. 243 */ 244 void 245 gem_attach(struct gem_softc *sc, const uint8_t *enaddr) 246 { 247 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 248 struct mii_data *mii = &sc->sc_mii; 249 bus_space_tag_t t = sc->sc_bustag; 250 bus_space_handle_t h = sc->sc_h1; 251 struct ifmedia_entry *ifm; 252 int i, error; 253 u_int32_t v; 254 char *nullbuf; 255 256 /* Make sure the chip is stopped. */ 257 ifp->if_softc = sc; 258 gem_reset(sc); 259 260 /* 261 * Allocate the control data structures, and create and load the 262 * DMA map for it. gem_control_data is 9216 bytes, we have space for 263 * the padding buffer in the bus_dmamem_alloc()'d memory. 264 */ 265 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 266 sizeof(struct gem_control_data) + ETHER_MIN_TX, PAGE_SIZE, 267 0, &sc->sc_cdseg, 1, &sc->sc_cdnseg, 0)) != 0) { 268 aprint_error_dev(sc->sc_dev, 269 "unable to allocate control data, error = %d\n", 270 error); 271 gem_partial_detach(sc, GEM_ATT_0); 272 return; 273 } 274 275 /* XXX should map this in with correct endianness */ 276 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg, 277 sizeof(struct gem_control_data), (void **)&sc->sc_control_data, 278 BUS_DMA_COHERENT)) != 0) { 279 aprint_error_dev(sc->sc_dev, 280 "unable to map control data, error = %d\n", error); 281 gem_partial_detach(sc, GEM_ATT_1); 282 return; 283 } 284 285 nullbuf = 286 (char *)sc->sc_control_data + sizeof(struct gem_control_data); 287 288 if ((error = bus_dmamap_create(sc->sc_dmatag, 289 sizeof(struct gem_control_data), 1, 290 sizeof(struct gem_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 291 aprint_error_dev(sc->sc_dev, 292 "unable to create control data DMA map, error = %d\n", 293 error); 294 gem_partial_detach(sc, GEM_ATT_2); 295 return; 296 } 297 298 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 299 sc->sc_control_data, sizeof(struct gem_control_data), NULL, 300 0)) != 0) { 301 aprint_error_dev(sc->sc_dev, 302 "unable to load control data DMA map, error = %d\n", 303 error); 304 gem_partial_detach(sc, GEM_ATT_3); 305 return; 306 } 307 308 memset(nullbuf, 0, ETHER_MIN_TX); 309 if ((error = bus_dmamap_create(sc->sc_dmatag, 310 ETHER_MIN_TX, 1, ETHER_MIN_TX, 0, 0, &sc->sc_nulldmamap)) != 0) { 311 aprint_error_dev(sc->sc_dev, 312 "unable to create padding DMA map, error = %d\n", error); 313 gem_partial_detach(sc, GEM_ATT_4); 314 return; 315 } 316 317 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_nulldmamap, 318 nullbuf, ETHER_MIN_TX, NULL, 0)) != 0) { 319 aprint_error_dev(sc->sc_dev, 320 "unable to load padding DMA map, error = %d\n", error); 321 gem_partial_detach(sc, GEM_ATT_5); 322 return; 323 } 324 325 bus_dmamap_sync(sc->sc_dmatag, sc->sc_nulldmamap, 0, ETHER_MIN_TX, 326 BUS_DMASYNC_PREWRITE); 327 328 /* 329 * Initialize the transmit job descriptors. 330 */ 331 SIMPLEQ_INIT(&sc->sc_txfreeq); 332 SIMPLEQ_INIT(&sc->sc_txdirtyq); 333 334 /* 335 * Create the transmit buffer DMA maps. 336 */ 337 for (i = 0; i < GEM_TXQUEUELEN; i++) { 338 struct gem_txsoft *txs; 339 340 txs = &sc->sc_txsoft[i]; 341 txs->txs_mbuf = NULL; 342 if ((error = bus_dmamap_create(sc->sc_dmatag, 343 ETHER_MAX_LEN_JUMBO, GEM_NTXSEGS, 344 ETHER_MAX_LEN_JUMBO, 0, 0, 345 &txs->txs_dmamap)) != 0) { 346 aprint_error_dev(sc->sc_dev, 347 "unable to create tx DMA map %d, error = %d\n", 348 i, error); 349 gem_partial_detach(sc, GEM_ATT_6); 350 return; 351 } 352 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 353 } 354 355 /* 356 * Create the receive buffer DMA maps. 357 */ 358 for (i = 0; i < GEM_NRXDESC; i++) { 359 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, 360 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 361 aprint_error_dev(sc->sc_dev, 362 "unable to create rx DMA map %d, error = %d\n", 363 i, error); 364 gem_partial_detach(sc, GEM_ATT_7); 365 return; 366 } 367 sc->sc_rxsoft[i].rxs_mbuf = NULL; 368 } 369 370 /* Initialize ifmedia structures and MII info */ 371 mii->mii_ifp = ifp; 372 mii->mii_readreg = gem_mii_readreg; 373 mii->mii_writereg = gem_mii_writereg; 374 mii->mii_statchg = gem_mii_statchg; 375 376 sc->sc_ethercom.ec_mii = mii; 377 378 /* 379 * Initialization based on `GEM Gigabit Ethernet ASIC Specification' 380 * Section 3.2.1 `Initialization Sequence'. 381 * However, we can't assume SERDES or Serialink if neither 382 * GEM_MIF_CONFIG_MDI0 nor GEM_MIF_CONFIG_MDI1 are set 383 * being set, as both are set on Sun X1141A (with SERDES). So, 384 * we rely on our bus attachment setting GEM_SERDES or GEM_SERIAL. 385 * Also, for Apple variants with 2 PHY's, we prefer the external 386 * PHY over the internal PHY. 387 */ 388 gem_mifinit(sc); 389 390 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) { 391 ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange, 392 ether_mediastatus); 393 mii_attach(sc->sc_dev, mii, 0xffffffff, 394 MII_PHY_ANY, MII_OFFSET_ANY, MIIF_FORCEANEG); 395 if (LIST_EMPTY(&mii->mii_phys)) { 396 /* No PHY attached */ 397 aprint_error_dev(sc->sc_dev, 398 "PHY probe failed\n"); 399 gem_partial_detach(sc, GEM_ATT_MII); 400 return; 401 } else { 402 struct mii_softc *child; 403 404 /* 405 * Walk along the list of attached MII devices and 406 * establish an `MII instance' to `PHY number' 407 * mapping. 408 */ 409 LIST_FOREACH(child, &mii->mii_phys, mii_list) { 410 /* 411 * Note: we support just one PHY: the internal 412 * or external MII is already selected for us 413 * by the GEM_MIF_CONFIG register. 414 */ 415 if (child->mii_phy > 1 || child->mii_inst > 0) { 416 aprint_error_dev(sc->sc_dev, 417 "cannot accommodate MII device" 418 " %s at PHY %d, instance %d\n", 419 device_xname(child->mii_dev), 420 child->mii_phy, child->mii_inst); 421 continue; 422 } 423 sc->sc_phys[child->mii_inst] = child->mii_phy; 424 } 425 426 /* 427 * Now select and activate the PHY we will use. 428 * 429 * The order of preference is External (MDI1), 430 * then Internal (MDI0), 431 */ 432 if (sc->sc_phys[1]) { 433 #ifdef GEM_DEBUG 434 aprint_debug_dev(sc->sc_dev, 435 "using external PHY\n"); 436 #endif 437 sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL; 438 } else { 439 #ifdef GEM_DEBUG 440 aprint_debug_dev(sc->sc_dev, 441 "using internal PHY\n"); 442 sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL; 443 #endif 444 } 445 bus_space_write_4(t, h, GEM_MIF_CONFIG, 446 sc->sc_mif_config); 447 if (sc->sc_variant != GEM_SUN_ERI) 448 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 449 GEM_MII_DATAPATH_MII); 450 451 /* 452 * XXX - we can really do the following ONLY if the 453 * PHY indeed has the auto negotiation capability!! 454 */ 455 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 456 } 457 } else { 458 ifmedia_init(&mii->mii_media, IFM_IMASK, gem_ser_mediachange, 459 gem_ser_mediastatus); 460 /* SERDES or Serialink */ 461 if (sc->sc_flags & GEM_SERDES) { 462 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 463 GEM_MII_DATAPATH_SERDES); 464 } else { 465 sc->sc_flags |= GEM_SERIAL; 466 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 467 GEM_MII_DATAPATH_SERIAL); 468 } 469 470 aprint_normal_dev(sc->sc_dev, "using external PCS %s: ", 471 sc->sc_flags & GEM_SERDES ? "SERDES" : "Serialink"); 472 473 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO, 0, NULL); 474 /* Check for FDX and HDX capabilities */ 475 sc->sc_mii_anar = bus_space_read_4(t, h, GEM_MII_ANAR); 476 if (sc->sc_mii_anar & GEM_MII_ANEG_FUL_DUPLX) { 477 ifmedia_add(&sc->sc_mii.mii_media, 478 IFM_ETHER|IFM_1000_SX|IFM_MANUAL|IFM_FDX, 0, NULL); 479 aprint_normal("1000baseSX-FDX, "); 480 } 481 if (sc->sc_mii_anar & GEM_MII_ANEG_HLF_DUPLX) { 482 ifmedia_add(&sc->sc_mii.mii_media, 483 IFM_ETHER|IFM_1000_SX|IFM_MANUAL|IFM_HDX, 0, NULL); 484 aprint_normal("1000baseSX-HDX, "); 485 } 486 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 487 sc->sc_mii_media = IFM_AUTO; 488 aprint_normal("auto\n"); 489 490 gem_pcs_stop(sc, 1); 491 } 492 493 /* 494 * From this point forward, the attachment cannot fail. A failure 495 * before this point releases all resources that may have been 496 * allocated. 497 */ 498 499 /* Announce ourselves. */ 500 aprint_normal_dev(sc->sc_dev, "Ethernet address %s", 501 ether_sprintf(enaddr)); 502 503 /* Get RX FIFO size */ 504 sc->sc_rxfifosize = 64 * 505 bus_space_read_4(t, h, GEM_RX_FIFO_SIZE); 506 aprint_normal(", %uKB RX fifo", sc->sc_rxfifosize / 1024); 507 508 /* Get TX FIFO size */ 509 v = bus_space_read_4(t, h, GEM_TX_FIFO_SIZE); 510 aprint_normal(", %uKB TX fifo\n", v / 16); 511 512 /* Initialize ifnet structure. */ 513 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 514 ifp->if_softc = sc; 515 ifp->if_flags = 516 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 517 sc->sc_if_flags = ifp->if_flags; 518 #if 0 519 /* 520 * The GEM hardware supports basic TCP checksum offloading only. 521 * Several (all?) revisions (Sun rev. 01 and Apple rev. 00 and 80) 522 * have bugs in the receive checksum, so don't enable it for now. 523 */ 524 if ((GEM_IS_SUN(sc) && sc->sc_chiprev != 1) || 525 (GEM_IS_APPLE(sc) && 526 (sc->sc_chiprev != 0 && sc->sc_chiprev != 0x80))) 527 ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Rx; 528 #endif 529 ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Tx; 530 ifp->if_start = gem_start; 531 ifp->if_ioctl = gem_ioctl; 532 ifp->if_watchdog = gem_watchdog; 533 ifp->if_stop = gem_stop; 534 ifp->if_init = gem_init; 535 IFQ_SET_READY(&ifp->if_snd); 536 537 /* 538 * If we support GigE media, we support jumbo frames too. 539 * Unless we are Apple. 540 */ 541 TAILQ_FOREACH(ifm, &sc->sc_mii.mii_media.ifm_list, ifm_list) { 542 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_T || 543 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_SX || 544 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_LX || 545 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_CX) { 546 if (!GEM_IS_APPLE(sc)) 547 sc->sc_ethercom.ec_capabilities 548 |= ETHERCAP_JUMBO_MTU; 549 sc->sc_flags |= GEM_GIGABIT; 550 break; 551 } 552 } 553 554 /* claim 802.1q capability */ 555 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 556 557 /* Attach the interface. */ 558 if_attach(ifp); 559 ether_ifattach(ifp, enaddr); 560 ether_set_ifflags_cb(&sc->sc_ethercom, gem_ifflags_cb); 561 562 #if NRND > 0 563 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 564 RND_TYPE_NET, 0); 565 #endif 566 567 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, 568 NULL, device_xname(sc->sc_dev), "interrupts"); 569 #ifdef GEM_COUNTERS 570 evcnt_attach_dynamic(&sc->sc_ev_txint, EVCNT_TYPE_INTR, 571 &sc->sc_ev_intr, device_xname(sc->sc_dev), "tx interrupts"); 572 evcnt_attach_dynamic(&sc->sc_ev_rxint, EVCNT_TYPE_INTR, 573 &sc->sc_ev_intr, device_xname(sc->sc_dev), "rx interrupts"); 574 evcnt_attach_dynamic(&sc->sc_ev_rxfull, EVCNT_TYPE_INTR, 575 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx ring full"); 576 evcnt_attach_dynamic(&sc->sc_ev_rxnobuf, EVCNT_TYPE_INTR, 577 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx malloc failure"); 578 evcnt_attach_dynamic(&sc->sc_ev_rxhist[0], EVCNT_TYPE_INTR, 579 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 0desc"); 580 evcnt_attach_dynamic(&sc->sc_ev_rxhist[1], EVCNT_TYPE_INTR, 581 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 1desc"); 582 evcnt_attach_dynamic(&sc->sc_ev_rxhist[2], EVCNT_TYPE_INTR, 583 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 2desc"); 584 evcnt_attach_dynamic(&sc->sc_ev_rxhist[3], EVCNT_TYPE_INTR, 585 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 3desc"); 586 evcnt_attach_dynamic(&sc->sc_ev_rxhist[4], EVCNT_TYPE_INTR, 587 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >3desc"); 588 evcnt_attach_dynamic(&sc->sc_ev_rxhist[5], EVCNT_TYPE_INTR, 589 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >7desc"); 590 evcnt_attach_dynamic(&sc->sc_ev_rxhist[6], EVCNT_TYPE_INTR, 591 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >15desc"); 592 evcnt_attach_dynamic(&sc->sc_ev_rxhist[7], EVCNT_TYPE_INTR, 593 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >31desc"); 594 evcnt_attach_dynamic(&sc->sc_ev_rxhist[8], EVCNT_TYPE_INTR, 595 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >63desc"); 596 #endif 597 598 callout_init(&sc->sc_tick_ch, 0); 599 600 sc->sc_att_stage = GEM_ATT_FINISHED; 601 602 return; 603 } 604 605 void 606 gem_tick(void *arg) 607 { 608 struct gem_softc *sc = arg; 609 int s; 610 611 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) { 612 /* 613 * We have to reset everything if we failed to get a 614 * PCS interrupt. Restarting the callout is handled 615 * in gem_pcs_start(). 616 */ 617 gem_init(&sc->sc_ethercom.ec_if); 618 } else { 619 s = splnet(); 620 mii_tick(&sc->sc_mii); 621 splx(s); 622 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 623 } 624 } 625 626 static int 627 gem_bitwait(struct gem_softc *sc, bus_space_handle_t h, int r, u_int32_t clr, u_int32_t set) 628 { 629 int i; 630 u_int32_t reg; 631 632 for (i = TRIES; i--; DELAY(100)) { 633 reg = bus_space_read_4(sc->sc_bustag, h, r); 634 if ((reg & clr) == 0 && (reg & set) == set) 635 return (1); 636 } 637 return (0); 638 } 639 640 void 641 gem_reset(struct gem_softc *sc) 642 { 643 bus_space_tag_t t = sc->sc_bustag; 644 bus_space_handle_t h = sc->sc_h2; 645 int s; 646 647 s = splnet(); 648 DPRINTF(sc, ("%s: gem_reset\n", device_xname(sc->sc_dev))); 649 gem_reset_rx(sc); 650 gem_reset_tx(sc); 651 652 /* Do a full reset */ 653 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX|GEM_RESET_TX); 654 if (!gem_bitwait(sc, h, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0)) 655 aprint_error_dev(sc->sc_dev, "cannot reset device\n"); 656 splx(s); 657 } 658 659 660 /* 661 * gem_rxdrain: 662 * 663 * Drain the receive queue. 664 */ 665 static void 666 gem_rxdrain(struct gem_softc *sc) 667 { 668 struct gem_rxsoft *rxs; 669 int i; 670 671 for (i = 0; i < GEM_NRXDESC; i++) { 672 rxs = &sc->sc_rxsoft[i]; 673 if (rxs->rxs_mbuf != NULL) { 674 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 675 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 676 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 677 m_freem(rxs->rxs_mbuf); 678 rxs->rxs_mbuf = NULL; 679 } 680 } 681 } 682 683 /* 684 * Reset the whole thing. 685 */ 686 static void 687 gem_stop(struct ifnet *ifp, int disable) 688 { 689 struct gem_softc *sc = ifp->if_softc; 690 struct gem_txsoft *txs; 691 692 DPRINTF(sc, ("%s: gem_stop\n", device_xname(sc->sc_dev))); 693 694 callout_stop(&sc->sc_tick_ch); 695 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 696 gem_pcs_stop(sc, disable); 697 else 698 mii_down(&sc->sc_mii); 699 700 /* XXX - Should we reset these instead? */ 701 gem_disable_tx(sc); 702 gem_disable_rx(sc); 703 704 /* 705 * Release any queued transmit buffers. 706 */ 707 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 708 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 709 if (txs->txs_mbuf != NULL) { 710 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 0, 711 txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 712 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 713 m_freem(txs->txs_mbuf); 714 txs->txs_mbuf = NULL; 715 } 716 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 717 } 718 719 /* 720 * Mark the interface down and cancel the watchdog timer. 721 */ 722 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 723 sc->sc_if_flags = ifp->if_flags; 724 ifp->if_timer = 0; 725 726 if (disable) 727 gem_rxdrain(sc); 728 } 729 730 731 /* 732 * Reset the receiver 733 */ 734 int 735 gem_reset_rx(struct gem_softc *sc) 736 { 737 bus_space_tag_t t = sc->sc_bustag; 738 bus_space_handle_t h = sc->sc_h1, h2 = sc->sc_h2; 739 740 /* 741 * Resetting while DMA is in progress can cause a bus hang, so we 742 * disable DMA first. 743 */ 744 gem_disable_rx(sc); 745 bus_space_write_4(t, h, GEM_RX_CONFIG, 0); 746 bus_space_barrier(t, h, GEM_RX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 747 /* Wait till it finishes */ 748 if (!gem_bitwait(sc, h, GEM_RX_CONFIG, 1, 0)) 749 aprint_error_dev(sc->sc_dev, "cannot disable read dma\n"); 750 751 /* Finally, reset the ERX */ 752 bus_space_write_4(t, h2, GEM_RESET, GEM_RESET_RX); 753 bus_space_barrier(t, h, GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE); 754 /* Wait till it finishes */ 755 if (!gem_bitwait(sc, h2, GEM_RESET, GEM_RESET_RX, 0)) { 756 aprint_error_dev(sc->sc_dev, "cannot reset receiver\n"); 757 return (1); 758 } 759 return (0); 760 } 761 762 763 /* 764 * Reset the receiver DMA engine. 765 * 766 * Intended to be used in case of GEM_INTR_RX_TAG_ERR, GEM_MAC_RX_OVERFLOW 767 * etc in order to reset the receiver DMA engine only and not do a full 768 * reset which amongst others also downs the link and clears the FIFOs. 769 */ 770 static void 771 gem_reset_rxdma(struct gem_softc *sc) 772 { 773 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 774 bus_space_tag_t t = sc->sc_bustag; 775 bus_space_handle_t h = sc->sc_h1; 776 int i; 777 778 if (gem_reset_rx(sc) != 0) { 779 gem_init(ifp); 780 return; 781 } 782 for (i = 0; i < GEM_NRXDESC; i++) 783 if (sc->sc_rxsoft[i].rxs_mbuf != NULL) 784 GEM_UPDATE_RXDESC(sc, i); 785 sc->sc_rxptr = 0; 786 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE); 787 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD); 788 789 /* Reprogram Descriptor Ring Base Addresses */ 790 /* NOTE: we use only 32-bit DMA addresses here. */ 791 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0); 792 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 793 794 /* Redo ERX Configuration */ 795 gem_rx_common(sc); 796 797 /* Give the reciever a swift kick */ 798 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC - 4); 799 } 800 801 /* 802 * Common RX configuration for gem_init() and gem_reset_rxdma(). 803 */ 804 static void 805 gem_rx_common(struct gem_softc *sc) 806 { 807 bus_space_tag_t t = sc->sc_bustag; 808 bus_space_handle_t h = sc->sc_h1; 809 u_int32_t v; 810 811 /* Encode Receive Descriptor ring size: four possible values */ 812 v = gem_ringsize(GEM_NRXDESC /*XXX*/); 813 814 /* Set receive h/w checksum offset */ 815 #ifdef INET 816 v |= (ETHER_HDR_LEN + sizeof(struct ip) + 817 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 818 ETHER_VLAN_ENCAP_LEN : 0)) << GEM_RX_CONFIG_CXM_START_SHFT; 819 #endif 820 821 /* Enable RX DMA */ 822 bus_space_write_4(t, h, GEM_RX_CONFIG, 823 v | (GEM_THRSH_1024 << GEM_RX_CONFIG_FIFO_THRS_SHIFT) | 824 (2 << GEM_RX_CONFIG_FBOFF_SHFT) | GEM_RX_CONFIG_RXDMA_EN); 825 826 /* 827 * The following value is for an OFF Threshold of about 3/4 full 828 * and an ON Threshold of 1/4 full. 829 */ 830 bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH, 831 (3 * sc->sc_rxfifosize / 256) | 832 ((sc->sc_rxfifosize / 256) << 12)); 833 bus_space_write_4(t, h, GEM_RX_BLANKING, 834 (6 << GEM_RX_BLANKING_TIME_SHIFT) | 6); 835 } 836 837 /* 838 * Reset the transmitter 839 */ 840 int 841 gem_reset_tx(struct gem_softc *sc) 842 { 843 bus_space_tag_t t = sc->sc_bustag; 844 bus_space_handle_t h = sc->sc_h1, h2 = sc->sc_h2; 845 846 /* 847 * Resetting while DMA is in progress can cause a bus hang, so we 848 * disable DMA first. 849 */ 850 gem_disable_tx(sc); 851 bus_space_write_4(t, h, GEM_TX_CONFIG, 0); 852 bus_space_barrier(t, h, GEM_TX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 853 /* Wait till it finishes */ 854 if (!gem_bitwait(sc, h, GEM_TX_CONFIG, 1, 0)) 855 aprint_error_dev(sc->sc_dev, "cannot disable read dma\n"); 856 /* Wait 5ms extra. */ 857 delay(5000); 858 859 /* Finally, reset the ETX */ 860 bus_space_write_4(t, h2, GEM_RESET, GEM_RESET_TX); 861 bus_space_barrier(t, h, GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE); 862 /* Wait till it finishes */ 863 if (!gem_bitwait(sc, h2, GEM_RESET, GEM_RESET_TX, 0)) { 864 aprint_error_dev(sc->sc_dev, "cannot reset receiver\n"); 865 return (1); 866 } 867 return (0); 868 } 869 870 /* 871 * disable receiver. 872 */ 873 int 874 gem_disable_rx(struct gem_softc *sc) 875 { 876 bus_space_tag_t t = sc->sc_bustag; 877 bus_space_handle_t h = sc->sc_h1; 878 u_int32_t cfg; 879 880 /* Flip the enable bit */ 881 cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 882 cfg &= ~GEM_MAC_RX_ENABLE; 883 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg); 884 bus_space_barrier(t, h, GEM_MAC_RX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 885 /* Wait for it to finish */ 886 return (gem_bitwait(sc, h, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)); 887 } 888 889 /* 890 * disable transmitter. 891 */ 892 int 893 gem_disable_tx(struct gem_softc *sc) 894 { 895 bus_space_tag_t t = sc->sc_bustag; 896 bus_space_handle_t h = sc->sc_h1; 897 u_int32_t cfg; 898 899 /* Flip the enable bit */ 900 cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG); 901 cfg &= ~GEM_MAC_TX_ENABLE; 902 bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg); 903 bus_space_barrier(t, h, GEM_MAC_TX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 904 /* Wait for it to finish */ 905 return (gem_bitwait(sc, h, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)); 906 } 907 908 /* 909 * Initialize interface. 910 */ 911 int 912 gem_meminit(struct gem_softc *sc) 913 { 914 struct gem_rxsoft *rxs; 915 int i, error; 916 917 /* 918 * Initialize the transmit descriptor ring. 919 */ 920 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 921 for (i = 0; i < GEM_NTXDESC; i++) { 922 sc->sc_txdescs[i].gd_flags = 0; 923 sc->sc_txdescs[i].gd_addr = 0; 924 } 925 GEM_CDTXSYNC(sc, 0, GEM_NTXDESC, 926 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 927 sc->sc_txfree = GEM_NTXDESC-1; 928 sc->sc_txnext = 0; 929 sc->sc_txwin = 0; 930 931 /* 932 * Initialize the receive descriptor and receive job 933 * descriptor rings. 934 */ 935 for (i = 0; i < GEM_NRXDESC; i++) { 936 rxs = &sc->sc_rxsoft[i]; 937 if (rxs->rxs_mbuf == NULL) { 938 if ((error = gem_add_rxbuf(sc, i)) != 0) { 939 aprint_error_dev(sc->sc_dev, 940 "unable to allocate or map rx " 941 "buffer %d, error = %d\n", 942 i, error); 943 /* 944 * XXX Should attempt to run with fewer receive 945 * XXX buffers instead of just failing. 946 */ 947 gem_rxdrain(sc); 948 return (1); 949 } 950 } else 951 GEM_INIT_RXDESC(sc, i); 952 } 953 sc->sc_rxptr = 0; 954 sc->sc_meminited = 1; 955 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE); 956 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD); 957 958 return (0); 959 } 960 961 static int 962 gem_ringsize(int sz) 963 { 964 switch (sz) { 965 case 32: 966 return GEM_RING_SZ_32; 967 case 64: 968 return GEM_RING_SZ_64; 969 case 128: 970 return GEM_RING_SZ_128; 971 case 256: 972 return GEM_RING_SZ_256; 973 case 512: 974 return GEM_RING_SZ_512; 975 case 1024: 976 return GEM_RING_SZ_1024; 977 case 2048: 978 return GEM_RING_SZ_2048; 979 case 4096: 980 return GEM_RING_SZ_4096; 981 case 8192: 982 return GEM_RING_SZ_8192; 983 default: 984 printf("gem: invalid Receive Descriptor ring size %d\n", sz); 985 return GEM_RING_SZ_32; 986 } 987 } 988 989 990 /* 991 * Start PCS 992 */ 993 void 994 gem_pcs_start(struct gem_softc *sc) 995 { 996 bus_space_tag_t t = sc->sc_bustag; 997 bus_space_handle_t h = sc->sc_h1; 998 uint32_t v; 999 1000 #ifdef GEM_DEBUG 1001 aprint_debug_dev(sc->sc_dev, "gem_pcs_start()\n"); 1002 #endif 1003 1004 /* 1005 * Set up. We must disable the MII before modifying the 1006 * GEM_MII_ANAR register 1007 */ 1008 if (sc->sc_flags & GEM_SERDES) { 1009 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 1010 GEM_MII_DATAPATH_SERDES); 1011 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 1012 GEM_MII_SLINK_LOOPBACK); 1013 } else { 1014 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 1015 GEM_MII_DATAPATH_SERIAL); 1016 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 0); 1017 } 1018 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 1019 v = bus_space_read_4(t, h, GEM_MII_ANAR); 1020 v |= (GEM_MII_ANEG_SYM_PAUSE | GEM_MII_ANEG_ASYM_PAUSE); 1021 if (sc->sc_mii_media == IFM_AUTO) 1022 v |= (GEM_MII_ANEG_FUL_DUPLX | GEM_MII_ANEG_HLF_DUPLX); 1023 else if (sc->sc_mii_media == IFM_FDX) { 1024 v |= GEM_MII_ANEG_FUL_DUPLX; 1025 v &= ~GEM_MII_ANEG_HLF_DUPLX; 1026 } else if (sc->sc_mii_media == IFM_HDX) { 1027 v &= ~GEM_MII_ANEG_FUL_DUPLX; 1028 v |= GEM_MII_ANEG_HLF_DUPLX; 1029 } 1030 1031 /* Configure link. */ 1032 bus_space_write_4(t, h, GEM_MII_ANAR, v); 1033 bus_space_write_4(t, h, GEM_MII_CONTROL, 1034 GEM_MII_CONTROL_AUTONEG | GEM_MII_CONTROL_RAN); 1035 bus_space_write_4(t, h, GEM_MII_CONFIG, GEM_MII_CONFIG_ENABLE); 1036 gem_bitwait(sc, h, GEM_MII_STATUS, 0, GEM_MII_STATUS_ANEG_CPT); 1037 1038 /* Start the 10 second timer */ 1039 callout_reset(&sc->sc_tick_ch, hz * 10, gem_tick, sc); 1040 } 1041 1042 /* 1043 * Stop PCS 1044 */ 1045 void 1046 gem_pcs_stop(struct gem_softc *sc, int disable) 1047 { 1048 bus_space_tag_t t = sc->sc_bustag; 1049 bus_space_handle_t h = sc->sc_h1; 1050 1051 #ifdef GEM_DEBUG 1052 aprint_debug_dev(sc->sc_dev, "gem_pcs_stop()\n"); 1053 #endif 1054 1055 /* Tell link partner that we're going away */ 1056 bus_space_write_4(t, h, GEM_MII_ANAR, GEM_MII_ANEG_RF); 1057 1058 /* 1059 * Disable PCS MII. The documentation suggests that setting 1060 * GEM_MII_CONFIG_ENABLE to zero and then restarting auto- 1061 * negotiation will shut down the link. However, it appears 1062 * that we also need to unset the datapath mode. 1063 */ 1064 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 1065 bus_space_write_4(t, h, GEM_MII_CONTROL, 1066 GEM_MII_CONTROL_AUTONEG | GEM_MII_CONTROL_RAN); 1067 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, GEM_MII_DATAPATH_MII); 1068 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 1069 1070 if (disable) { 1071 if (sc->sc_flags & GEM_SERDES) 1072 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 1073 GEM_MII_SLINK_POWER_OFF); 1074 else 1075 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 1076 GEM_MII_SLINK_LOOPBACK | GEM_MII_SLINK_POWER_OFF); 1077 } 1078 1079 sc->sc_flags &= ~GEM_LINK; 1080 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_NONE; 1081 sc->sc_mii.mii_media_status = IFM_AVALID; 1082 } 1083 1084 1085 /* 1086 * Initialization of interface; set up initialization block 1087 * and transmit/receive descriptor rings. 1088 */ 1089 int 1090 gem_init(struct ifnet *ifp) 1091 { 1092 struct gem_softc *sc = ifp->if_softc; 1093 bus_space_tag_t t = sc->sc_bustag; 1094 bus_space_handle_t h = sc->sc_h1; 1095 int rc = 0, s; 1096 u_int max_frame_size; 1097 u_int32_t v; 1098 1099 s = splnet(); 1100 1101 DPRINTF(sc, ("%s: gem_init: calling stop\n", device_xname(sc->sc_dev))); 1102 /* 1103 * Initialization sequence. The numbered steps below correspond 1104 * to the sequence outlined in section 6.3.5.1 in the Ethernet 1105 * Channel Engine manual (part of the PCIO manual). 1106 * See also the STP2002-STQ document from Sun Microsystems. 1107 */ 1108 1109 /* step 1 & 2. Reset the Ethernet Channel */ 1110 gem_stop(ifp, 0); 1111 gem_reset(sc); 1112 DPRINTF(sc, ("%s: gem_init: restarting\n", device_xname(sc->sc_dev))); 1113 1114 /* Re-initialize the MIF */ 1115 gem_mifinit(sc); 1116 1117 /* Set up correct datapath for non-SERDES/Serialink */ 1118 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0 && 1119 sc->sc_variant != GEM_SUN_ERI) 1120 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 1121 GEM_MII_DATAPATH_MII); 1122 1123 /* Call MI reset function if any */ 1124 if (sc->sc_hwreset) 1125 (*sc->sc_hwreset)(sc); 1126 1127 /* step 3. Setup data structures in host memory */ 1128 if (gem_meminit(sc) != 0) 1129 return 1; 1130 1131 /* step 4. TX MAC registers & counters */ 1132 gem_init_regs(sc); 1133 max_frame_size = max(sc->sc_ethercom.ec_if.if_mtu, ETHERMTU); 1134 max_frame_size += ETHER_HDR_LEN + ETHER_CRC_LEN; 1135 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1136 max_frame_size += ETHER_VLAN_ENCAP_LEN; 1137 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 1138 max_frame_size|/* burst size */(0x2000<<16)); 1139 1140 /* step 5. RX MAC registers & counters */ 1141 gem_setladrf(sc); 1142 1143 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 1144 /* NOTE: we use only 32-bit DMA addresses here. */ 1145 bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 0); 1146 bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 1147 1148 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0); 1149 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 1150 1151 /* step 8. Global Configuration & Interrupt Mask */ 1152 gem_inten(sc); 1153 bus_space_write_4(t, h, GEM_MAC_RX_MASK, 1154 GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT); 1155 bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXX */ 1156 bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 1157 GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME); 1158 1159 /* step 9. ETX Configuration: use mostly default values */ 1160 1161 /* Enable TX DMA */ 1162 v = gem_ringsize(GEM_NTXDESC /*XXX*/); 1163 bus_space_write_4(t, h, GEM_TX_CONFIG, 1164 v | GEM_TX_CONFIG_TXDMA_EN | 1165 (((sc->sc_flags & GEM_GIGABIT ? 0x4FF : 0x100) << 10) & 1166 GEM_TX_CONFIG_TXFIFO_TH)); 1167 bus_space_write_4(t, h, GEM_TX_KICK, sc->sc_txnext); 1168 1169 /* step 10. ERX Configuration */ 1170 gem_rx_common(sc); 1171 1172 /* step 11. Configure Media */ 1173 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0 && 1174 (rc = mii_ifmedia_change(&sc->sc_mii)) != 0) 1175 goto out; 1176 1177 /* step 12. RX_MAC Configuration Register */ 1178 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 1179 v |= GEM_MAC_RX_ENABLE | GEM_MAC_RX_STRIP_CRC; 1180 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 1181 1182 /* step 14. Issue Transmit Pending command */ 1183 1184 /* Call MI initialization function if any */ 1185 if (sc->sc_hwinit) 1186 (*sc->sc_hwinit)(sc); 1187 1188 1189 /* step 15. Give the reciever a swift kick */ 1190 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4); 1191 1192 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 1193 /* Configure PCS */ 1194 gem_pcs_start(sc); 1195 else 1196 /* Start the one second timer. */ 1197 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 1198 1199 sc->sc_flags &= ~GEM_LINK; 1200 ifp->if_flags |= IFF_RUNNING; 1201 ifp->if_flags &= ~IFF_OACTIVE; 1202 ifp->if_timer = 0; 1203 sc->sc_if_flags = ifp->if_flags; 1204 out: 1205 splx(s); 1206 1207 return (0); 1208 } 1209 1210 void 1211 gem_init_regs(struct gem_softc *sc) 1212 { 1213 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1214 bus_space_tag_t t = sc->sc_bustag; 1215 bus_space_handle_t h = sc->sc_h1; 1216 const u_char *laddr = CLLADDR(ifp->if_sadl); 1217 u_int32_t v; 1218 1219 /* These regs are not cleared on reset */ 1220 if (!sc->sc_inited) { 1221 1222 /* Load recommended values */ 1223 bus_space_write_4(t, h, GEM_MAC_IPG0, 0x00); 1224 bus_space_write_4(t, h, GEM_MAC_IPG1, 0x08); 1225 bus_space_write_4(t, h, GEM_MAC_IPG2, 0x04); 1226 1227 bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 1228 /* Max frame and max burst size */ 1229 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 1230 ETHER_MAX_LEN | (0x2000<<16)); 1231 1232 bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x07); 1233 bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x04); 1234 bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10); 1235 bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088); 1236 bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED, 1237 ((laddr[5]<<8)|laddr[4])&0x3ff); 1238 1239 /* Secondary MAC addr set to 0:0:0:0:0:0 */ 1240 bus_space_write_4(t, h, GEM_MAC_ADDR3, 0); 1241 bus_space_write_4(t, h, GEM_MAC_ADDR4, 0); 1242 bus_space_write_4(t, h, GEM_MAC_ADDR5, 0); 1243 1244 /* MAC control addr set to 01:80:c2:00:00:01 */ 1245 bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001); 1246 bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200); 1247 bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180); 1248 1249 /* MAC filter addr set to 0:0:0:0:0:0 */ 1250 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0); 1251 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0); 1252 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0); 1253 1254 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0); 1255 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0); 1256 1257 sc->sc_inited = 1; 1258 } 1259 1260 /* Counters need to be zeroed */ 1261 bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0); 1262 bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0); 1263 bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0); 1264 bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0); 1265 bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0); 1266 bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0); 1267 bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0); 1268 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 1269 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 1270 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 1271 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 1272 1273 /* Set XOFF PAUSE time. */ 1274 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); 1275 1276 /* 1277 * Set the internal arbitration to "infinite" bursts of the 1278 * maximum length of 31 * 64 bytes so DMA transfers aren't 1279 * split up in cache line size chunks. This greatly improves 1280 * especially RX performance. 1281 * Enable silicon bug workarounds for the Apple variants. 1282 */ 1283 bus_space_write_4(t, h, GEM_CONFIG, 1284 GEM_CONFIG_TXDMA_LIMIT | GEM_CONFIG_RXDMA_LIMIT | 1285 ((sc->sc_flags & GEM_PCI) ? 1286 GEM_CONFIG_BURST_INF : GEM_CONFIG_BURST_64) | (GEM_IS_APPLE(sc) ? 1287 GEM_CONFIG_RONPAULBIT | GEM_CONFIG_BUG2FIX : 0)); 1288 1289 /* 1290 * Set the station address. 1291 */ 1292 bus_space_write_4(t, h, GEM_MAC_ADDR0, (laddr[4]<<8)|laddr[5]); 1293 bus_space_write_4(t, h, GEM_MAC_ADDR1, (laddr[2]<<8)|laddr[3]); 1294 bus_space_write_4(t, h, GEM_MAC_ADDR2, (laddr[0]<<8)|laddr[1]); 1295 1296 /* 1297 * Enable MII outputs. Enable GMII if there is a gigabit PHY. 1298 */ 1299 sc->sc_mif_config = bus_space_read_4(t, h, GEM_MIF_CONFIG); 1300 v = GEM_MAC_XIF_TX_MII_ENA; 1301 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) { 1302 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) { 1303 v |= GEM_MAC_XIF_FDPLX_LED; 1304 if (sc->sc_flags & GEM_GIGABIT) 1305 v |= GEM_MAC_XIF_GMII_MODE; 1306 } 1307 } else { 1308 v |= GEM_MAC_XIF_GMII_MODE; 1309 } 1310 bus_space_write_4(t, h, GEM_MAC_XIF_CONFIG, v); 1311 } 1312 1313 #ifdef GEM_DEBUG 1314 static void 1315 gem_txsoft_print(const struct gem_softc *sc, int firstdesc, int lastdesc) 1316 { 1317 int i; 1318 1319 for (i = firstdesc;; i = GEM_NEXTTX(i)) { 1320 printf("descriptor %d:\t", i); 1321 printf("gd_flags: 0x%016" PRIx64 "\t", 1322 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags)); 1323 printf("gd_addr: 0x%016" PRIx64 "\n", 1324 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr)); 1325 if (i == lastdesc) 1326 break; 1327 } 1328 } 1329 #endif 1330 1331 static void 1332 gem_start(struct ifnet *ifp) 1333 { 1334 struct gem_softc *sc = ifp->if_softc; 1335 struct mbuf *m0, *m; 1336 struct gem_txsoft *txs; 1337 bus_dmamap_t dmamap; 1338 int error, firsttx, nexttx = -1, lasttx = -1, ofree, seg; 1339 uint64_t flags = 0; 1340 1341 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1342 return; 1343 1344 /* 1345 * Remember the previous number of free descriptors and 1346 * the first descriptor we'll use. 1347 */ 1348 ofree = sc->sc_txfree; 1349 firsttx = sc->sc_txnext; 1350 1351 DPRINTF(sc, ("%s: gem_start: txfree %d, txnext %d\n", 1352 device_xname(sc->sc_dev), ofree, firsttx)); 1353 1354 /* 1355 * Loop through the send queue, setting up transmit descriptors 1356 * until we drain the queue, or use up all available transmit 1357 * descriptors. 1358 */ 1359 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 1360 sc->sc_txfree != 0) { 1361 /* 1362 * Grab a packet off the queue. 1363 */ 1364 IFQ_POLL(&ifp->if_snd, m0); 1365 if (m0 == NULL) 1366 break; 1367 m = NULL; 1368 1369 dmamap = txs->txs_dmamap; 1370 1371 /* 1372 * Load the DMA map. If this fails, the packet either 1373 * didn't fit in the alloted number of segments, or we were 1374 * short on resources. In this case, we'll copy and try 1375 * again. 1376 */ 1377 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m0, 1378 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0 || 1379 (m0->m_pkthdr.len < ETHER_MIN_TX && 1380 dmamap->dm_nsegs == GEM_NTXSEGS)) { 1381 if (m0->m_pkthdr.len > MCLBYTES) { 1382 aprint_error_dev(sc->sc_dev, 1383 "unable to allocate jumbo Tx cluster\n"); 1384 IFQ_DEQUEUE(&ifp->if_snd, m0); 1385 m_freem(m0); 1386 continue; 1387 } 1388 MGETHDR(m, M_DONTWAIT, MT_DATA); 1389 if (m == NULL) { 1390 aprint_error_dev(sc->sc_dev, 1391 "unable to allocate Tx mbuf\n"); 1392 break; 1393 } 1394 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1395 if (m0->m_pkthdr.len > MHLEN) { 1396 MCLGET(m, M_DONTWAIT); 1397 if ((m->m_flags & M_EXT) == 0) { 1398 aprint_error_dev(sc->sc_dev, 1399 "unable to allocate Tx cluster\n"); 1400 m_freem(m); 1401 break; 1402 } 1403 } 1404 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1405 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1406 error = bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, 1407 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1408 if (error) { 1409 aprint_error_dev(sc->sc_dev, 1410 "unable to load Tx buffer, error = %d\n", 1411 error); 1412 break; 1413 } 1414 } 1415 1416 /* 1417 * Ensure we have enough descriptors free to describe 1418 * the packet. 1419 */ 1420 if (dmamap->dm_nsegs > ((m0->m_pkthdr.len < ETHER_MIN_TX) ? 1421 (sc->sc_txfree - 1) : sc->sc_txfree)) { 1422 /* 1423 * Not enough free descriptors to transmit this 1424 * packet. We haven't committed to anything yet, 1425 * so just unload the DMA map, put the packet 1426 * back on the queue, and punt. Notify the upper 1427 * layer that there are no more slots left. 1428 * 1429 * XXX We could allocate an mbuf and copy, but 1430 * XXX it is worth it? 1431 */ 1432 ifp->if_flags |= IFF_OACTIVE; 1433 sc->sc_if_flags = ifp->if_flags; 1434 bus_dmamap_unload(sc->sc_dmatag, dmamap); 1435 if (m != NULL) 1436 m_freem(m); 1437 break; 1438 } 1439 1440 IFQ_DEQUEUE(&ifp->if_snd, m0); 1441 if (m != NULL) { 1442 m_freem(m0); 1443 m0 = m; 1444 } 1445 1446 /* 1447 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1448 */ 1449 1450 /* Sync the DMA map. */ 1451 bus_dmamap_sync(sc->sc_dmatag, dmamap, 0, dmamap->dm_mapsize, 1452 BUS_DMASYNC_PREWRITE); 1453 1454 /* 1455 * Initialize the transmit descriptors. 1456 */ 1457 for (nexttx = sc->sc_txnext, seg = 0; 1458 seg < dmamap->dm_nsegs; 1459 seg++, nexttx = GEM_NEXTTX(nexttx)) { 1460 1461 /* 1462 * If this is the first descriptor we're 1463 * enqueueing, set the start of packet flag, 1464 * and the checksum stuff if we want the hardware 1465 * to do it. 1466 */ 1467 sc->sc_txdescs[nexttx].gd_addr = 1468 GEM_DMA_WRITE(sc, dmamap->dm_segs[seg].ds_addr); 1469 flags = dmamap->dm_segs[seg].ds_len & GEM_TD_BUFSIZE; 1470 if (nexttx == firsttx) { 1471 flags |= GEM_TD_START_OF_PACKET; 1472 if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) { 1473 sc->sc_txwin = 0; 1474 flags |= GEM_TD_INTERRUPT_ME; 1475 } 1476 1477 #ifdef INET 1478 /* h/w checksum */ 1479 if (ifp->if_csum_flags_tx & M_CSUM_TCPv4 && 1480 m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1481 struct ether_header *eh; 1482 uint16_t offset, start; 1483 1484 eh = mtod(m0, struct ether_header *); 1485 switch (ntohs(eh->ether_type)) { 1486 case ETHERTYPE_IP: 1487 start = ETHER_HDR_LEN; 1488 break; 1489 case ETHERTYPE_VLAN: 1490 start = ETHER_HDR_LEN + 1491 ETHER_VLAN_ENCAP_LEN; 1492 break; 1493 default: 1494 /* unsupported, drop it */ 1495 m_free(m0); 1496 continue; 1497 } 1498 start += M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 1499 offset = M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data) + start; 1500 flags |= (start << 1501 GEM_TD_CXSUM_STARTSHFT) | 1502 (offset << 1503 GEM_TD_CXSUM_STUFFSHFT) | 1504 GEM_TD_CXSUM_ENABLE; 1505 } 1506 #endif 1507 } 1508 if (seg == dmamap->dm_nsegs - 1) { 1509 flags |= GEM_TD_END_OF_PACKET; 1510 } else { 1511 /* last flag set outside of loop */ 1512 sc->sc_txdescs[nexttx].gd_flags = 1513 GEM_DMA_WRITE(sc, flags); 1514 } 1515 lasttx = nexttx; 1516 } 1517 if (m0->m_pkthdr.len < ETHER_MIN_TX) { 1518 /* add padding buffer at end of chain */ 1519 flags &= ~GEM_TD_END_OF_PACKET; 1520 sc->sc_txdescs[lasttx].gd_flags = 1521 GEM_DMA_WRITE(sc, flags); 1522 1523 sc->sc_txdescs[nexttx].gd_addr = 1524 GEM_DMA_WRITE(sc, 1525 sc->sc_nulldmamap->dm_segs[0].ds_addr); 1526 flags = ((ETHER_MIN_TX - m0->m_pkthdr.len) & 1527 GEM_TD_BUFSIZE) | GEM_TD_END_OF_PACKET; 1528 lasttx = nexttx; 1529 nexttx = GEM_NEXTTX(nexttx); 1530 seg++; 1531 } 1532 sc->sc_txdescs[lasttx].gd_flags = GEM_DMA_WRITE(sc, flags); 1533 1534 KASSERT(lasttx != -1); 1535 1536 /* 1537 * Store a pointer to the packet so we can free it later, 1538 * and remember what txdirty will be once the packet is 1539 * done. 1540 */ 1541 txs->txs_mbuf = m0; 1542 txs->txs_firstdesc = sc->sc_txnext; 1543 txs->txs_lastdesc = lasttx; 1544 txs->txs_ndescs = seg; 1545 1546 #ifdef GEM_DEBUG 1547 if (ifp->if_flags & IFF_DEBUG) { 1548 printf(" gem_start %p transmit chain:\n", txs); 1549 gem_txsoft_print(sc, txs->txs_firstdesc, 1550 txs->txs_lastdesc); 1551 } 1552 #endif 1553 1554 /* Sync the descriptors we're using. */ 1555 GEM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndescs, 1556 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1557 1558 /* Advance the tx pointer. */ 1559 sc->sc_txfree -= txs->txs_ndescs; 1560 sc->sc_txnext = nexttx; 1561 1562 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1563 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1564 1565 #if NBPFILTER > 0 1566 /* 1567 * Pass the packet to any BPF listeners. 1568 */ 1569 if (ifp->if_bpf) 1570 bpf_mtap(ifp->if_bpf, m0); 1571 #endif /* NBPFILTER > 0 */ 1572 } 1573 1574 if (txs == NULL || sc->sc_txfree == 0) { 1575 /* No more slots left; notify upper layer. */ 1576 ifp->if_flags |= IFF_OACTIVE; 1577 sc->sc_if_flags = ifp->if_flags; 1578 } 1579 1580 if (sc->sc_txfree != ofree) { 1581 DPRINTF(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 1582 device_xname(sc->sc_dev), lasttx, firsttx)); 1583 /* 1584 * The entire packet chain is set up. 1585 * Kick the transmitter. 1586 */ 1587 DPRINTF(sc, ("%s: gem_start: kicking tx %d\n", 1588 device_xname(sc->sc_dev), nexttx)); 1589 bus_space_write_4(sc->sc_bustag, sc->sc_h1, GEM_TX_KICK, 1590 sc->sc_txnext); 1591 1592 /* Set a watchdog timer in case the chip flakes out. */ 1593 ifp->if_timer = 5; 1594 DPRINTF(sc, ("%s: gem_start: watchdog %d\n", 1595 device_xname(sc->sc_dev), ifp->if_timer)); 1596 } 1597 } 1598 1599 /* 1600 * Transmit interrupt. 1601 */ 1602 int 1603 gem_tint(struct gem_softc *sc) 1604 { 1605 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1606 bus_space_tag_t t = sc->sc_bustag; 1607 bus_space_handle_t mac = sc->sc_h1; 1608 struct gem_txsoft *txs; 1609 int txlast; 1610 int progress = 0; 1611 u_int32_t v; 1612 1613 DPRINTF(sc, ("%s: gem_tint\n", device_xname(sc->sc_dev))); 1614 1615 /* Unload collision counters ... */ 1616 v = bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) + 1617 bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT); 1618 ifp->if_collisions += v + 1619 bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) + 1620 bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT); 1621 ifp->if_oerrors += v; 1622 1623 /* ... then clear the hardware counters. */ 1624 bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0); 1625 bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0); 1626 bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0); 1627 bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0); 1628 1629 /* 1630 * Go through our Tx list and free mbufs for those 1631 * frames that have been transmitted. 1632 */ 1633 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1634 /* 1635 * In theory, we could harvest some descriptors before 1636 * the ring is empty, but that's a bit complicated. 1637 * 1638 * GEM_TX_COMPLETION points to the last descriptor 1639 * processed +1. 1640 * 1641 * Let's assume that the NIC writes back to the Tx 1642 * descriptors before it updates the completion 1643 * register. If the NIC has posted writes to the 1644 * Tx descriptors, PCI ordering requires that the 1645 * posted writes flush to RAM before the register-read 1646 * finishes. So let's read the completion register, 1647 * before syncing the descriptors, so that we 1648 * examine Tx descriptors that are at least as 1649 * current as the completion register. 1650 */ 1651 txlast = bus_space_read_4(t, mac, GEM_TX_COMPLETION); 1652 DPRINTF(sc, 1653 ("gem_tint: txs->txs_lastdesc = %d, txlast = %d\n", 1654 txs->txs_lastdesc, txlast)); 1655 if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1656 if (txlast >= txs->txs_firstdesc && 1657 txlast <= txs->txs_lastdesc) 1658 break; 1659 } else if (txlast >= txs->txs_firstdesc || 1660 txlast <= txs->txs_lastdesc) 1661 break; 1662 1663 GEM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndescs, 1664 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1665 1666 #ifdef GEM_DEBUG /* XXX DMA synchronization? */ 1667 if (ifp->if_flags & IFF_DEBUG) { 1668 printf(" txsoft %p transmit chain:\n", txs); 1669 gem_txsoft_print(sc, txs->txs_firstdesc, 1670 txs->txs_lastdesc); 1671 } 1672 #endif 1673 1674 1675 DPRINTF(sc, ("gem_tint: releasing a desc\n")); 1676 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1677 1678 sc->sc_txfree += txs->txs_ndescs; 1679 1680 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 1681 0, txs->txs_dmamap->dm_mapsize, 1682 BUS_DMASYNC_POSTWRITE); 1683 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 1684 if (txs->txs_mbuf != NULL) { 1685 m_freem(txs->txs_mbuf); 1686 txs->txs_mbuf = NULL; 1687 } 1688 1689 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1690 1691 ifp->if_opackets++; 1692 progress = 1; 1693 } 1694 1695 #if 0 1696 DPRINTF(sc, ("gem_tint: GEM_TX_STATE_MACHINE %x " 1697 "GEM_TX_DATA_PTR %" PRIx64 "GEM_TX_COMPLETION %" PRIx32 "\n", 1698 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_TX_STATE_MACHINE), 1699 ((uint64_t)bus_space_read_4(sc->sc_bustag, sc->sc_h1, 1700 GEM_TX_DATA_PTR_HI) << 32) | 1701 bus_space_read_4(sc->sc_bustag, sc->sc_h1, 1702 GEM_TX_DATA_PTR_LO), 1703 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_TX_COMPLETION))); 1704 #endif 1705 1706 if (progress) { 1707 if (sc->sc_txfree == GEM_NTXDESC - 1) 1708 sc->sc_txwin = 0; 1709 1710 /* Freed some descriptors, so reset IFF_OACTIVE and restart. */ 1711 ifp->if_flags &= ~IFF_OACTIVE; 1712 sc->sc_if_flags = ifp->if_flags; 1713 ifp->if_timer = SIMPLEQ_EMPTY(&sc->sc_txdirtyq) ? 0 : 5; 1714 gem_start(ifp); 1715 } 1716 DPRINTF(sc, ("%s: gem_tint: watchdog %d\n", 1717 device_xname(sc->sc_dev), ifp->if_timer)); 1718 1719 return (1); 1720 } 1721 1722 /* 1723 * Receive interrupt. 1724 */ 1725 int 1726 gem_rint(struct gem_softc *sc) 1727 { 1728 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1729 bus_space_tag_t t = sc->sc_bustag; 1730 bus_space_handle_t h = sc->sc_h1; 1731 struct gem_rxsoft *rxs; 1732 struct mbuf *m; 1733 u_int64_t rxstat; 1734 u_int32_t rxcomp; 1735 int i, len, progress = 0; 1736 1737 DPRINTF(sc, ("%s: gem_rint\n", device_xname(sc->sc_dev))); 1738 1739 /* 1740 * Ignore spurious interrupt that sometimes occurs before 1741 * we are set up when we network boot. 1742 */ 1743 if (!sc->sc_meminited) 1744 return 1; 1745 1746 /* 1747 * Read the completion register once. This limits 1748 * how long the following loop can execute. 1749 */ 1750 rxcomp = bus_space_read_4(t, h, GEM_RX_COMPLETION); 1751 1752 /* 1753 * XXX Read the lastrx only once at the top for speed. 1754 */ 1755 DPRINTF(sc, ("gem_rint: sc->rxptr %d, complete %d\n", 1756 sc->sc_rxptr, rxcomp)); 1757 1758 /* 1759 * Go into the loop at least once. 1760 */ 1761 for (i = sc->sc_rxptr; i == sc->sc_rxptr || i != rxcomp; 1762 i = GEM_NEXTRX(i)) { 1763 rxs = &sc->sc_rxsoft[i]; 1764 1765 GEM_CDRXSYNC(sc, i, 1766 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1767 1768 rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags); 1769 1770 if (rxstat & GEM_RD_OWN) { 1771 GEM_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); 1772 /* 1773 * We have processed all of the receive buffers. 1774 */ 1775 break; 1776 } 1777 1778 progress++; 1779 ifp->if_ipackets++; 1780 1781 if (rxstat & GEM_RD_BAD_CRC) { 1782 ifp->if_ierrors++; 1783 aprint_error_dev(sc->sc_dev, 1784 "receive error: CRC error\n"); 1785 GEM_INIT_RXDESC(sc, i); 1786 continue; 1787 } 1788 1789 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1790 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1791 #ifdef GEM_DEBUG 1792 if (ifp->if_flags & IFF_DEBUG) { 1793 printf(" rxsoft %p descriptor %d: ", rxs, i); 1794 printf("gd_flags: 0x%016llx\t", (long long) 1795 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags)); 1796 printf("gd_addr: 0x%016llx\n", (long long) 1797 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr)); 1798 } 1799 #endif 1800 1801 /* No errors; receive the packet. */ 1802 len = GEM_RD_BUFLEN(rxstat); 1803 1804 /* 1805 * Allocate a new mbuf cluster. If that fails, we are 1806 * out of memory, and must drop the packet and recycle 1807 * the buffer that's already attached to this descriptor. 1808 */ 1809 m = rxs->rxs_mbuf; 1810 if (gem_add_rxbuf(sc, i) != 0) { 1811 GEM_COUNTER_INCR(sc, sc_ev_rxnobuf); 1812 ifp->if_ierrors++; 1813 GEM_INIT_RXDESC(sc, i); 1814 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1815 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1816 continue; 1817 } 1818 m->m_data += 2; /* We're already off by two */ 1819 1820 m->m_pkthdr.rcvif = ifp; 1821 m->m_pkthdr.len = m->m_len = len; 1822 1823 #if NBPFILTER > 0 1824 /* 1825 * Pass this up to any BPF listeners, but only 1826 * pass it up the stack if it's for us. 1827 */ 1828 if (ifp->if_bpf) 1829 bpf_mtap(ifp->if_bpf, m); 1830 #endif /* NBPFILTER > 0 */ 1831 1832 #ifdef INET 1833 /* hardware checksum */ 1834 if (ifp->if_csum_flags_rx & M_CSUM_TCPv4) { 1835 struct ether_header *eh; 1836 struct ip *ip; 1837 int32_t hlen, pktlen; 1838 1839 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1840 pktlen = m->m_pkthdr.len - ETHER_HDR_LEN - 1841 ETHER_VLAN_ENCAP_LEN; 1842 eh = (struct ether_header *) (mtod(m, char *) + 1843 ETHER_VLAN_ENCAP_LEN); 1844 } else { 1845 pktlen = m->m_pkthdr.len - ETHER_HDR_LEN; 1846 eh = mtod(m, struct ether_header *); 1847 } 1848 if (ntohs(eh->ether_type) != ETHERTYPE_IP) 1849 goto swcsum; 1850 ip = (struct ip *) ((char *)eh + ETHER_HDR_LEN); 1851 1852 /* IPv4 only */ 1853 if (ip->ip_v != IPVERSION) 1854 goto swcsum; 1855 1856 hlen = ip->ip_hl << 2; 1857 if (hlen < sizeof(struct ip)) 1858 goto swcsum; 1859 1860 /* 1861 * bail if too short, has random trailing garbage, 1862 * truncated, fragment, or has ethernet pad. 1863 */ 1864 if ((ntohs(ip->ip_len) < hlen) || 1865 (ntohs(ip->ip_len) != pktlen) || 1866 (ntohs(ip->ip_off) & (IP_MF | IP_OFFMASK))) 1867 goto swcsum; 1868 1869 switch (ip->ip_p) { 1870 case IPPROTO_TCP: 1871 if (! (ifp->if_csum_flags_rx & M_CSUM_TCPv4)) 1872 goto swcsum; 1873 if (pktlen < (hlen + sizeof(struct tcphdr))) 1874 goto swcsum; 1875 m->m_pkthdr.csum_flags = M_CSUM_TCPv4; 1876 break; 1877 case IPPROTO_UDP: 1878 /* FALLTHROUGH */ 1879 default: 1880 goto swcsum; 1881 } 1882 1883 /* the uncomplemented sum is expected */ 1884 m->m_pkthdr.csum_data = (~rxstat) & GEM_RD_CHECKSUM; 1885 1886 /* if the pkt had ip options, we have to deduct them */ 1887 if (hlen > sizeof(struct ip)) { 1888 uint16_t *opts; 1889 uint32_t optsum, temp; 1890 1891 optsum = 0; 1892 temp = hlen - sizeof(struct ip); 1893 opts = (uint16_t *) ((char *) ip + 1894 sizeof(struct ip)); 1895 1896 while (temp > 1) { 1897 optsum += ntohs(*opts++); 1898 temp -= 2; 1899 } 1900 while (optsum >> 16) 1901 optsum = (optsum >> 16) + 1902 (optsum & 0xffff); 1903 1904 /* Deduct ip opts sum from hwsum. */ 1905 m->m_pkthdr.csum_data += (uint16_t)~optsum; 1906 1907 while (m->m_pkthdr.csum_data >> 16) 1908 m->m_pkthdr.csum_data = 1909 (m->m_pkthdr.csum_data >> 16) + 1910 (m->m_pkthdr.csum_data & 1911 0xffff); 1912 } 1913 1914 m->m_pkthdr.csum_flags |= M_CSUM_DATA | 1915 M_CSUM_NO_PSEUDOHDR; 1916 } else 1917 swcsum: 1918 m->m_pkthdr.csum_flags = 0; 1919 #endif 1920 /* Pass it on. */ 1921 (*ifp->if_input)(ifp, m); 1922 } 1923 1924 if (progress) { 1925 /* Update the receive pointer. */ 1926 if (i == sc->sc_rxptr) { 1927 GEM_COUNTER_INCR(sc, sc_ev_rxfull); 1928 #ifdef GEM_DEBUG 1929 if (ifp->if_flags & IFF_DEBUG) 1930 printf("%s: rint: ring wrap\n", 1931 device_xname(sc->sc_dev)); 1932 #endif 1933 } 1934 sc->sc_rxptr = i; 1935 bus_space_write_4(t, h, GEM_RX_KICK, GEM_PREVRX(i)); 1936 } 1937 #ifdef GEM_COUNTERS 1938 if (progress <= 4) { 1939 GEM_COUNTER_INCR(sc, sc_ev_rxhist[progress]); 1940 } else if (progress < 32) { 1941 if (progress < 16) 1942 GEM_COUNTER_INCR(sc, sc_ev_rxhist[5]); 1943 else 1944 GEM_COUNTER_INCR(sc, sc_ev_rxhist[6]); 1945 1946 } else { 1947 if (progress < 64) 1948 GEM_COUNTER_INCR(sc, sc_ev_rxhist[7]); 1949 else 1950 GEM_COUNTER_INCR(sc, sc_ev_rxhist[8]); 1951 } 1952 #endif 1953 1954 DPRINTF(sc, ("gem_rint: done sc->rxptr %d, complete %d\n", 1955 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION))); 1956 1957 /* Read error counters ... */ 1958 ifp->if_ierrors += 1959 bus_space_read_4(t, h, GEM_MAC_RX_LEN_ERR_CNT) + 1960 bus_space_read_4(t, h, GEM_MAC_RX_ALIGN_ERR) + 1961 bus_space_read_4(t, h, GEM_MAC_RX_CRC_ERR_CNT) + 1962 bus_space_read_4(t, h, GEM_MAC_RX_CODE_VIOL); 1963 1964 /* ... then clear the hardware counters. */ 1965 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 1966 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 1967 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 1968 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 1969 1970 return (1); 1971 } 1972 1973 1974 /* 1975 * gem_add_rxbuf: 1976 * 1977 * Add a receive buffer to the indicated descriptor. 1978 */ 1979 int 1980 gem_add_rxbuf(struct gem_softc *sc, int idx) 1981 { 1982 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1983 struct mbuf *m; 1984 int error; 1985 1986 MGETHDR(m, M_DONTWAIT, MT_DATA); 1987 if (m == NULL) 1988 return (ENOBUFS); 1989 1990 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1991 MCLGET(m, M_DONTWAIT); 1992 if ((m->m_flags & M_EXT) == 0) { 1993 m_freem(m); 1994 return (ENOBUFS); 1995 } 1996 1997 #ifdef GEM_DEBUG 1998 /* bzero the packet to check DMA */ 1999 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 2000 #endif 2001 2002 if (rxs->rxs_mbuf != NULL) 2003 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 2004 2005 rxs->rxs_mbuf = m; 2006 2007 error = bus_dmamap_load(sc->sc_dmatag, rxs->rxs_dmamap, 2008 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2009 BUS_DMA_READ|BUS_DMA_NOWAIT); 2010 if (error) { 2011 aprint_error_dev(sc->sc_dev, 2012 "can't load rx DMA map %d, error = %d\n", idx, error); 2013 panic("gem_add_rxbuf"); /* XXX */ 2014 } 2015 2016 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 2017 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2018 2019 GEM_INIT_RXDESC(sc, idx); 2020 2021 return (0); 2022 } 2023 2024 2025 int 2026 gem_eint(struct gem_softc *sc, u_int status) 2027 { 2028 char bits[128]; 2029 u_int32_t r, v; 2030 2031 if ((status & GEM_INTR_MIF) != 0) { 2032 printf("%s: XXXlink status changed\n", device_xname(sc->sc_dev)); 2033 return (1); 2034 } 2035 2036 if ((status & GEM_INTR_RX_TAG_ERR) != 0) { 2037 gem_reset_rxdma(sc); 2038 return (1); 2039 } 2040 2041 if (status & GEM_INTR_BERR) { 2042 if (sc->sc_flags & GEM_PCI) 2043 r = GEM_ERROR_STATUS; 2044 else 2045 r = GEM_SBUS_ERROR_STATUS; 2046 bus_space_read_4(sc->sc_bustag, sc->sc_h2, r); 2047 v = bus_space_read_4(sc->sc_bustag, sc->sc_h2, r); 2048 aprint_error_dev(sc->sc_dev, "bus error interrupt: 0x%02x\n", 2049 v); 2050 return (1); 2051 } 2052 snprintb(bits, sizeof(bits), GEM_INTR_BITS, status); 2053 printf("%s: status=%s\n", device_xname(sc->sc_dev), bits); 2054 2055 return (1); 2056 } 2057 2058 2059 /* 2060 * PCS interrupts. 2061 * We should receive these when the link status changes, but sometimes 2062 * we don't receive them for link up. We compensate for this in the 2063 * gem_tick() callout. 2064 */ 2065 int 2066 gem_pint(struct gem_softc *sc) 2067 { 2068 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2069 bus_space_tag_t t = sc->sc_bustag; 2070 bus_space_handle_t h = sc->sc_h1; 2071 u_int32_t v, v2; 2072 2073 /* 2074 * Clear the PCS interrupt from GEM_STATUS. The PCS register is 2075 * latched, so we have to read it twice. There is only one bit in 2076 * use, so the value is meaningless. 2077 */ 2078 bus_space_read_4(t, h, GEM_MII_INTERRUP_STATUS); 2079 bus_space_read_4(t, h, GEM_MII_INTERRUP_STATUS); 2080 2081 if ((ifp->if_flags & IFF_UP) == 0) 2082 return 1; 2083 2084 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) 2085 return 1; 2086 2087 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2088 /* If we see remote fault, our link partner is probably going away */ 2089 if ((v & GEM_MII_STATUS_REM_FLT) != 0) { 2090 gem_bitwait(sc, h, GEM_MII_STATUS, GEM_MII_STATUS_REM_FLT, 0); 2091 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2092 /* Otherwise, we may need to wait after auto-negotiation completes */ 2093 } else if ((v & (GEM_MII_STATUS_LINK_STS | GEM_MII_STATUS_ANEG_CPT)) == 2094 GEM_MII_STATUS_ANEG_CPT) { 2095 gem_bitwait(sc, h, GEM_MII_STATUS, 0, GEM_MII_STATUS_LINK_STS); 2096 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2097 } 2098 if ((v & GEM_MII_STATUS_LINK_STS) != 0) { 2099 if (sc->sc_flags & GEM_LINK) { 2100 return 1; 2101 } 2102 callout_stop(&sc->sc_tick_ch); 2103 v = bus_space_read_4(t, h, GEM_MII_ANAR); 2104 v2 = bus_space_read_4(t, h, GEM_MII_ANLPAR); 2105 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_1000_SX; 2106 sc->sc_mii.mii_media_status = IFM_AVALID | IFM_ACTIVE; 2107 v &= v2; 2108 if (v & GEM_MII_ANEG_FUL_DUPLX) { 2109 sc->sc_mii.mii_media_active |= IFM_FDX; 2110 #ifdef GEM_DEBUG 2111 aprint_debug_dev(sc->sc_dev, "link up: full duplex\n"); 2112 #endif 2113 } else if (v & GEM_MII_ANEG_HLF_DUPLX) { 2114 sc->sc_mii.mii_media_active |= IFM_HDX; 2115 #ifdef GEM_DEBUG 2116 aprint_debug_dev(sc->sc_dev, "link up: half duplex\n"); 2117 #endif 2118 } else { 2119 #ifdef GEM_DEBUG 2120 aprint_debug_dev(sc->sc_dev, "duplex mismatch\n"); 2121 #endif 2122 } 2123 gem_statuschange(sc); 2124 } else { 2125 if ((sc->sc_flags & GEM_LINK) == 0) { 2126 return 1; 2127 } 2128 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_NONE; 2129 sc->sc_mii.mii_media_status = IFM_AVALID; 2130 #ifdef GEM_DEBUG 2131 aprint_debug_dev(sc->sc_dev, "link down\n"); 2132 #endif 2133 gem_statuschange(sc); 2134 2135 /* Start the 10 second timer */ 2136 callout_reset(&sc->sc_tick_ch, hz * 10, gem_tick, sc); 2137 } 2138 return 1; 2139 } 2140 2141 2142 2143 int 2144 gem_intr(void *v) 2145 { 2146 struct gem_softc *sc = v; 2147 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2148 bus_space_tag_t t = sc->sc_bustag; 2149 bus_space_handle_t h = sc->sc_h1; 2150 u_int32_t status; 2151 int r = 0; 2152 #ifdef GEM_DEBUG 2153 char bits[128]; 2154 #endif 2155 2156 /* XXX We should probably mask out interrupts until we're done */ 2157 2158 sc->sc_ev_intr.ev_count++; 2159 2160 status = bus_space_read_4(t, h, GEM_STATUS); 2161 #ifdef GEM_DEBUG 2162 snprintb(bits, sizeof(bits), GEM_INTR_BITS, status); 2163 #endif 2164 DPRINTF(sc, ("%s: gem_intr: cplt 0x%x status %s\n", 2165 device_xname(sc->sc_dev), (status >> 19), bits)); 2166 2167 2168 if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0) 2169 r |= gem_eint(sc, status); 2170 2171 /* We don't bother with GEM_INTR_TX_DONE */ 2172 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) { 2173 GEM_COUNTER_INCR(sc, sc_ev_txint); 2174 r |= gem_tint(sc); 2175 } 2176 2177 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) { 2178 GEM_COUNTER_INCR(sc, sc_ev_rxint); 2179 r |= gem_rint(sc); 2180 } 2181 2182 /* We should eventually do more than just print out error stats. */ 2183 if (status & GEM_INTR_TX_MAC) { 2184 int txstat = bus_space_read_4(t, h, GEM_MAC_TX_STATUS); 2185 if (txstat & ~GEM_MAC_TX_XMIT_DONE) 2186 printf("%s: MAC tx fault, status %x\n", 2187 device_xname(sc->sc_dev), txstat); 2188 if (txstat & (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG)) 2189 gem_init(ifp); 2190 } 2191 if (status & GEM_INTR_RX_MAC) { 2192 int rxstat = bus_space_read_4(t, h, GEM_MAC_RX_STATUS); 2193 /* 2194 * At least with GEM_SUN_GEM and some GEM_SUN_ERI 2195 * revisions GEM_MAC_RX_OVERFLOW happen often due to a 2196 * silicon bug so handle them silently. Moreover, it's 2197 * likely that the receiver has hung so we reset it. 2198 */ 2199 if (rxstat & GEM_MAC_RX_OVERFLOW) { 2200 ifp->if_ierrors++; 2201 gem_reset_rxdma(sc); 2202 } else if (rxstat & ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT)) 2203 printf("%s: MAC rx fault, status 0x%02x\n", 2204 device_xname(sc->sc_dev), rxstat); 2205 } 2206 if (status & GEM_INTR_PCS) { 2207 r |= gem_pint(sc); 2208 } 2209 2210 /* Do we need to do anything with these? 2211 if ((status & GEM_MAC_CONTROL_STATUS) != 0) { 2212 status2 = bus_read_4(sc->sc_res[0], GEM_MAC_CONTROL_STATUS); 2213 if ((status2 & GEM_MAC_PAUSED) != 0) 2214 aprintf_debug_dev(sc->sc_dev, "PAUSE received (%d slots)\n", 2215 GEM_MAC_PAUSE_TIME(status2)); 2216 if ((status2 & GEM_MAC_PAUSE) != 0) 2217 aprintf_debug_dev(sc->sc_dev, "transited to PAUSE state\n"); 2218 if ((status2 & GEM_MAC_RESUME) != 0) 2219 aprintf_debug_dev(sc->sc_dev, "transited to non-PAUSE state\n"); 2220 } 2221 if ((status & GEM_INTR_MIF) != 0) 2222 aprintf_debug_dev(sc->sc_dev, "MIF interrupt\n"); 2223 */ 2224 #if NRND > 0 2225 rnd_add_uint32(&sc->rnd_source, status); 2226 #endif 2227 return (r); 2228 } 2229 2230 2231 void 2232 gem_watchdog(struct ifnet *ifp) 2233 { 2234 struct gem_softc *sc = ifp->if_softc; 2235 2236 DPRINTF(sc, ("gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x " 2237 "GEM_MAC_RX_CONFIG %x\n", 2238 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_RX_CONFIG), 2239 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_MAC_RX_STATUS), 2240 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_MAC_RX_CONFIG))); 2241 2242 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 2243 ++ifp->if_oerrors; 2244 2245 /* Try to get more packets going. */ 2246 gem_start(ifp); 2247 } 2248 2249 /* 2250 * Initialize the MII Management Interface 2251 */ 2252 void 2253 gem_mifinit(struct gem_softc *sc) 2254 { 2255 bus_space_tag_t t = sc->sc_bustag; 2256 bus_space_handle_t mif = sc->sc_h1; 2257 2258 /* Configure the MIF in frame mode */ 2259 sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 2260 sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA; 2261 bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config); 2262 } 2263 2264 /* 2265 * MII interface 2266 * 2267 * The GEM MII interface supports at least three different operating modes: 2268 * 2269 * Bitbang mode is implemented using data, clock and output enable registers. 2270 * 2271 * Frame mode is implemented by loading a complete frame into the frame 2272 * register and polling the valid bit for completion. 2273 * 2274 * Polling mode uses the frame register but completion is indicated by 2275 * an interrupt. 2276 * 2277 */ 2278 static int 2279 gem_mii_readreg(device_t self, int phy, int reg) 2280 { 2281 struct gem_softc *sc = device_private(self); 2282 bus_space_tag_t t = sc->sc_bustag; 2283 bus_space_handle_t mif = sc->sc_h1; 2284 int n; 2285 u_int32_t v; 2286 2287 #ifdef GEM_DEBUG1 2288 if (sc->sc_debug) 2289 printf("gem_mii_readreg: PHY %d reg %d\n", phy, reg); 2290 #endif 2291 2292 /* Construct the frame command */ 2293 v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) | 2294 GEM_MIF_FRAME_READ; 2295 2296 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 2297 for (n = 0; n < 100; n++) { 2298 DELAY(1); 2299 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 2300 if (v & GEM_MIF_FRAME_TA0) 2301 return (v & GEM_MIF_FRAME_DATA); 2302 } 2303 2304 printf("%s: mii_read timeout\n", device_xname(sc->sc_dev)); 2305 return (0); 2306 } 2307 2308 static void 2309 gem_mii_writereg(device_t self, int phy, int reg, int val) 2310 { 2311 struct gem_softc *sc = device_private(self); 2312 bus_space_tag_t t = sc->sc_bustag; 2313 bus_space_handle_t mif = sc->sc_h1; 2314 int n; 2315 u_int32_t v; 2316 2317 #ifdef GEM_DEBUG1 2318 if (sc->sc_debug) 2319 printf("gem_mii_writereg: PHY %d reg %d val %x\n", 2320 phy, reg, val); 2321 #endif 2322 2323 /* Construct the frame command */ 2324 v = GEM_MIF_FRAME_WRITE | 2325 (phy << GEM_MIF_PHY_SHIFT) | 2326 (reg << GEM_MIF_REG_SHIFT) | 2327 (val & GEM_MIF_FRAME_DATA); 2328 2329 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 2330 for (n = 0; n < 100; n++) { 2331 DELAY(1); 2332 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 2333 if (v & GEM_MIF_FRAME_TA0) 2334 return; 2335 } 2336 2337 printf("%s: mii_write timeout\n", device_xname(sc->sc_dev)); 2338 } 2339 2340 static void 2341 gem_mii_statchg(device_t self) 2342 { 2343 struct gem_softc *sc = device_private(self); 2344 #ifdef GEM_DEBUG 2345 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 2346 #endif 2347 2348 #ifdef GEM_DEBUG 2349 if (sc->sc_debug) 2350 printf("gem_mii_statchg: status change: phy = %d\n", 2351 sc->sc_phys[instance]); 2352 #endif 2353 gem_statuschange(sc); 2354 } 2355 2356 /* 2357 * Common status change for gem_mii_statchg() and gem_pint() 2358 */ 2359 void 2360 gem_statuschange(struct gem_softc* sc) 2361 { 2362 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2363 bus_space_tag_t t = sc->sc_bustag; 2364 bus_space_handle_t mac = sc->sc_h1; 2365 int gigabit; 2366 u_int32_t rxcfg, txcfg, v; 2367 2368 if ((sc->sc_mii.mii_media_status & IFM_ACTIVE) != 0 && 2369 IFM_SUBTYPE(sc->sc_mii.mii_media_active) != IFM_NONE) 2370 sc->sc_flags |= GEM_LINK; 2371 else 2372 sc->sc_flags &= ~GEM_LINK; 2373 2374 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 2375 gigabit = 1; 2376 else 2377 gigabit = 0; 2378 2379 /* 2380 * The configuration done here corresponds to the steps F) and 2381 * G) and as far as enabling of RX and TX MAC goes also step H) 2382 * of the initialization sequence outlined in section 3.2.1 of 2383 * the GEM Gigabit Ethernet ASIC Specification. 2384 */ 2385 2386 rxcfg = bus_space_read_4(t, mac, GEM_MAC_RX_CONFIG); 2387 rxcfg &= ~(GEM_MAC_RX_CARR_EXTEND | GEM_MAC_RX_ENABLE); 2388 txcfg = GEM_MAC_TX_ENA_IPG0 | GEM_MAC_TX_NGU | GEM_MAC_TX_NGU_LIMIT; 2389 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 2390 txcfg |= GEM_MAC_TX_IGN_CARRIER | GEM_MAC_TX_IGN_COLLIS; 2391 else if (gigabit) { 2392 rxcfg |= GEM_MAC_RX_CARR_EXTEND; 2393 txcfg |= GEM_MAC_RX_CARR_EXTEND; 2394 } 2395 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0); 2396 bus_space_barrier(t, mac, GEM_MAC_TX_CONFIG, 4, 2397 BUS_SPACE_BARRIER_WRITE); 2398 if (!gem_bitwait(sc, mac, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)) 2399 aprint_normal_dev(sc->sc_dev, "cannot disable TX MAC\n"); 2400 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, txcfg); 2401 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, 0); 2402 bus_space_barrier(t, mac, GEM_MAC_RX_CONFIG, 4, 2403 BUS_SPACE_BARRIER_WRITE); 2404 if (!gem_bitwait(sc, mac, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)) 2405 aprint_normal_dev(sc->sc_dev, "cannot disable RX MAC\n"); 2406 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, rxcfg); 2407 2408 v = bus_space_read_4(t, mac, GEM_MAC_CONTROL_CONFIG) & 2409 ~(GEM_MAC_CC_RX_PAUSE | GEM_MAC_CC_TX_PAUSE); 2410 bus_space_write_4(t, mac, GEM_MAC_CONTROL_CONFIG, v); 2411 2412 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) == 0 && 2413 gigabit != 0) 2414 bus_space_write_4(t, mac, GEM_MAC_SLOT_TIME, 2415 GEM_MAC_SLOT_TIME_CARR_EXTEND); 2416 else 2417 bus_space_write_4(t, mac, GEM_MAC_SLOT_TIME, 2418 GEM_MAC_SLOT_TIME_NORMAL); 2419 2420 /* XIF Configuration */ 2421 if (sc->sc_flags & GEM_LINK) 2422 v = GEM_MAC_XIF_LINK_LED; 2423 else 2424 v = 0; 2425 v |= GEM_MAC_XIF_TX_MII_ENA; 2426 2427 /* If an external transceiver is connected, enable its MII drivers */ 2428 sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG); 2429 if ((sc->sc_flags &(GEM_SERDES | GEM_SERIAL)) == 0) { 2430 if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) { 2431 /* External MII needs echo disable if half duplex. */ 2432 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & 2433 IFM_FDX) != 0) 2434 /* turn on full duplex LED */ 2435 v |= GEM_MAC_XIF_FDPLX_LED; 2436 else 2437 /* half duplex -- disable echo */ 2438 v |= GEM_MAC_XIF_ECHO_DISABL; 2439 if (gigabit) 2440 v |= GEM_MAC_XIF_GMII_MODE; 2441 else 2442 v &= ~GEM_MAC_XIF_GMII_MODE; 2443 } else 2444 /* Internal MII needs buf enable */ 2445 v |= GEM_MAC_XIF_MII_BUF_ENA; 2446 } else { 2447 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 2448 v |= GEM_MAC_XIF_FDPLX_LED; 2449 v |= GEM_MAC_XIF_GMII_MODE; 2450 } 2451 bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v); 2452 2453 if ((ifp->if_flags & IFF_RUNNING) != 0 && 2454 (sc->sc_flags & GEM_LINK) != 0) { 2455 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 2456 txcfg | GEM_MAC_TX_ENABLE); 2457 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, 2458 rxcfg | GEM_MAC_RX_ENABLE); 2459 } 2460 } 2461 2462 int 2463 gem_ser_mediachange(struct ifnet *ifp) 2464 { 2465 struct gem_softc *sc = ifp->if_softc; 2466 u_int s, t; 2467 2468 if (IFM_TYPE(sc->sc_mii.mii_media.ifm_media) != IFM_ETHER) 2469 return EINVAL; 2470 2471 s = IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media); 2472 if (s == IFM_AUTO) { 2473 if (sc->sc_mii_media != s) { 2474 #ifdef GEM_DEBUG 2475 aprint_debug_dev(sc->sc_dev, "setting media to auto\n"); 2476 #endif 2477 sc->sc_mii_media = s; 2478 if (ifp->if_flags & IFF_UP) { 2479 gem_pcs_stop(sc, 0); 2480 gem_pcs_start(sc); 2481 } 2482 } 2483 return 0; 2484 } 2485 if (s == IFM_1000_SX) { 2486 t = IFM_OPTIONS(sc->sc_mii.mii_media.ifm_media); 2487 if (t == IFM_FDX || t == IFM_HDX) { 2488 if (sc->sc_mii_media != t) { 2489 sc->sc_mii_media = t; 2490 #ifdef GEM_DEBUG 2491 aprint_debug_dev(sc->sc_dev, 2492 "setting media to 1000baseSX-%s\n", 2493 t == IFM_FDX ? "FDX" : "HDX"); 2494 #endif 2495 if (ifp->if_flags & IFF_UP) { 2496 gem_pcs_stop(sc, 0); 2497 gem_pcs_start(sc); 2498 } 2499 } 2500 return 0; 2501 } 2502 } 2503 return EINVAL; 2504 } 2505 2506 void 2507 gem_ser_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2508 { 2509 struct gem_softc *sc = ifp->if_softc; 2510 2511 if ((ifp->if_flags & IFF_UP) == 0) 2512 return; 2513 ifmr->ifm_active = sc->sc_mii.mii_media_active; 2514 ifmr->ifm_status = sc->sc_mii.mii_media_status; 2515 } 2516 2517 static int 2518 gem_ifflags_cb(struct ethercom *ec) 2519 { 2520 struct ifnet *ifp = &ec->ec_if; 2521 struct gem_softc *sc = ifp->if_softc; 2522 int change = ifp->if_flags ^ sc->sc_if_flags; 2523 2524 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 2525 return ENETRESET; 2526 else if ((change & IFF_PROMISC) != 0) 2527 gem_setladrf(sc); 2528 return 0; 2529 } 2530 2531 /* 2532 * Process an ioctl request. 2533 */ 2534 int 2535 gem_ioctl(struct ifnet *ifp, unsigned long cmd, void *data) 2536 { 2537 struct gem_softc *sc = ifp->if_softc; 2538 int s, error = 0; 2539 2540 s = splnet(); 2541 2542 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2543 error = 0; 2544 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 2545 ; 2546 else if (ifp->if_flags & IFF_RUNNING) { 2547 /* 2548 * Multicast list has changed; set the hardware filter 2549 * accordingly. 2550 */ 2551 gem_setladrf(sc); 2552 } 2553 } 2554 2555 /* Try to get things going again */ 2556 if (ifp->if_flags & IFF_UP) 2557 gem_start(ifp); 2558 splx(s); 2559 return (error); 2560 } 2561 2562 static void 2563 gem_inten(struct gem_softc *sc) 2564 { 2565 bus_space_tag_t t = sc->sc_bustag; 2566 bus_space_handle_t h = sc->sc_h1; 2567 uint32_t v; 2568 2569 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 2570 v = GEM_INTR_PCS; 2571 else 2572 v = GEM_INTR_MIF; 2573 bus_space_write_4(t, h, GEM_INTMASK, 2574 ~(GEM_INTR_TX_INTME | 2575 GEM_INTR_TX_EMPTY | 2576 GEM_INTR_TX_MAC | 2577 GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF| 2578 GEM_INTR_RX_TAG_ERR | GEM_INTR_MAC_CONTROL| 2579 GEM_INTR_BERR | v)); 2580 } 2581 2582 bool 2583 gem_resume(device_t self PMF_FN_ARGS) 2584 { 2585 struct gem_softc *sc = device_private(self); 2586 2587 gem_inten(sc); 2588 2589 return true; 2590 } 2591 2592 bool 2593 gem_suspend(device_t self PMF_FN_ARGS) 2594 { 2595 struct gem_softc *sc = device_private(self); 2596 bus_space_tag_t t = sc->sc_bustag; 2597 bus_space_handle_t h = sc->sc_h1; 2598 2599 bus_space_write_4(t, h, GEM_INTMASK, ~(uint32_t)0); 2600 2601 return true; 2602 } 2603 2604 bool 2605 gem_shutdown(device_t self, int howto) 2606 { 2607 struct gem_softc *sc = device_private(self); 2608 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2609 2610 gem_stop(ifp, 1); 2611 2612 return true; 2613 } 2614 2615 /* 2616 * Set up the logical address filter. 2617 */ 2618 void 2619 gem_setladrf(struct gem_softc *sc) 2620 { 2621 struct ethercom *ec = &sc->sc_ethercom; 2622 struct ifnet *ifp = &ec->ec_if; 2623 struct ether_multi *enm; 2624 struct ether_multistep step; 2625 bus_space_tag_t t = sc->sc_bustag; 2626 bus_space_handle_t h = sc->sc_h1; 2627 u_int32_t crc; 2628 u_int32_t hash[16]; 2629 u_int32_t v; 2630 int i; 2631 2632 /* Get current RX configuration */ 2633 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 2634 2635 /* 2636 * Turn off promiscuous mode, promiscuous group mode (all multicast), 2637 * and hash filter. Depending on the case, the right bit will be 2638 * enabled. 2639 */ 2640 v &= ~(GEM_MAC_RX_PROMISCUOUS|GEM_MAC_RX_HASH_FILTER| 2641 GEM_MAC_RX_PROMISC_GRP); 2642 2643 if ((ifp->if_flags & IFF_PROMISC) != 0) { 2644 /* Turn on promiscuous mode */ 2645 v |= GEM_MAC_RX_PROMISCUOUS; 2646 ifp->if_flags |= IFF_ALLMULTI; 2647 goto chipit; 2648 } 2649 2650 /* 2651 * Set up multicast address filter by passing all multicast addresses 2652 * through a crc generator, and then using the high order 8 bits as an 2653 * index into the 256 bit logical address filter. The high order 4 2654 * bits selects the word, while the other 4 bits select the bit within 2655 * the word (where bit 0 is the MSB). 2656 */ 2657 2658 /* Clear hash table */ 2659 memset(hash, 0, sizeof(hash)); 2660 2661 ETHER_FIRST_MULTI(step, ec, enm); 2662 while (enm != NULL) { 2663 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2664 /* 2665 * We must listen to a range of multicast addresses. 2666 * For now, just accept all multicasts, rather than 2667 * trying to set only those filter bits needed to match 2668 * the range. (At this time, the only use of address 2669 * ranges is for IP multicast routing, for which the 2670 * range is big enough to require all bits set.) 2671 * XXX should use the address filters for this 2672 */ 2673 ifp->if_flags |= IFF_ALLMULTI; 2674 v |= GEM_MAC_RX_PROMISC_GRP; 2675 goto chipit; 2676 } 2677 2678 /* Get the LE CRC32 of the address */ 2679 crc = ether_crc32_le(enm->enm_addrlo, sizeof(enm->enm_addrlo)); 2680 2681 /* Just want the 8 most significant bits. */ 2682 crc >>= 24; 2683 2684 /* Set the corresponding bit in the filter. */ 2685 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 2686 2687 ETHER_NEXT_MULTI(step, enm); 2688 } 2689 2690 v |= GEM_MAC_RX_HASH_FILTER; 2691 ifp->if_flags &= ~IFF_ALLMULTI; 2692 2693 /* Now load the hash table into the chip (if we are using it) */ 2694 for (i = 0; i < 16; i++) { 2695 bus_space_write_4(t, h, 2696 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1-GEM_MAC_HASH0), 2697 hash[i]); 2698 } 2699 2700 chipit: 2701 sc->sc_if_flags = ifp->if_flags; 2702 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 2703 } 2704
Indexes created Tue Sep 23 07:09:52 GMT 2025