gem.c revision 1.91
1 /* $NetBSD: gem.c,v 1.91 2010/01/11 09:30:41 jdc Exp $ */ 2 3 /* 4 * 5 * Copyright (C) 2001 Eduardo Horvath. 6 * Copyright (c) 2001-2003 Thomas Moestl 7 * All rights reserved. 8 * 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 */ 32 33 /* 34 * Driver for Apple GMAC, Sun ERI and Sun GEM Ethernet controllers 35 * See `GEM Gigabit Ethernet ASIC Specification' 36 * http://www.sun.com/processors/manuals/ge.pdf 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: gem.c,v 1.91 2010/01/11 09:30:41 jdc Exp $"); 41 42 #include "opt_inet.h" 43 #include "bpfilter.h" 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/callout.h> 48 #include <sys/mbuf.h> 49 #include <sys/syslog.h> 50 #include <sys/malloc.h> 51 #include <sys/kernel.h> 52 #include <sys/socket.h> 53 #include <sys/ioctl.h> 54 #include <sys/errno.h> 55 #include <sys/device.h> 56 57 #include <machine/endian.h> 58 59 #include <uvm/uvm_extern.h> 60 61 #include <net/if.h> 62 #include <net/if_dl.h> 63 #include <net/if_media.h> 64 #include <net/if_ether.h> 65 66 #ifdef INET 67 #include <netinet/in.h> 68 #include <netinet/in_systm.h> 69 #include <netinet/in_var.h> 70 #include <netinet/ip.h> 71 #include <netinet/tcp.h> 72 #include <netinet/udp.h> 73 #endif 74 75 #if NBPFILTER > 0 76 #include <net/bpf.h> 77 #endif 78 79 #include <sys/bus.h> 80 #include <sys/intr.h> 81 82 #include <dev/mii/mii.h> 83 #include <dev/mii/miivar.h> 84 #include <dev/mii/mii_bitbang.h> 85 86 #include <dev/ic/gemreg.h> 87 #include <dev/ic/gemvar.h> 88 89 #define TRIES 10000 90 91 static void gem_inten(struct gem_softc *); 92 static void gem_start(struct ifnet *); 93 static void gem_stop(struct ifnet *, int); 94 int gem_ioctl(struct ifnet *, u_long, void *); 95 void gem_tick(void *); 96 void gem_watchdog(struct ifnet *); 97 void gem_pcs_start(struct gem_softc *sc); 98 void gem_pcs_stop(struct gem_softc *sc, int); 99 int gem_init(struct ifnet *); 100 void gem_init_regs(struct gem_softc *sc); 101 static int gem_ringsize(int sz); 102 static int gem_meminit(struct gem_softc *); 103 void gem_mifinit(struct gem_softc *); 104 static int gem_bitwait(struct gem_softc *sc, bus_space_handle_t, int, 105 u_int32_t, u_int32_t); 106 void gem_reset(struct gem_softc *); 107 int gem_reset_rx(struct gem_softc *sc); 108 static void gem_reset_rxdma(struct gem_softc *sc); 109 static void gem_rx_common(struct gem_softc *sc); 110 int gem_reset_tx(struct gem_softc *sc); 111 int gem_disable_rx(struct gem_softc *sc); 112 int gem_disable_tx(struct gem_softc *sc); 113 static void gem_rxdrain(struct gem_softc *sc); 114 int gem_add_rxbuf(struct gem_softc *sc, int idx); 115 void gem_setladrf(struct gem_softc *); 116 117 /* MII methods & callbacks */ 118 static int gem_mii_readreg(device_t, int, int); 119 static void gem_mii_writereg(device_t, int, int, int); 120 static void gem_mii_statchg(device_t); 121 122 static int gem_ifflags_cb(struct ethercom *); 123 124 void gem_statuschange(struct gem_softc *); 125 126 int gem_ser_mediachange(struct ifnet *); 127 void gem_ser_mediastatus(struct ifnet *, struct ifmediareq *); 128 129 static void gem_partial_detach(struct gem_softc *, enum gem_attach_stage); 130 131 struct mbuf *gem_get(struct gem_softc *, int, int); 132 int gem_put(struct gem_softc *, int, struct mbuf *); 133 void gem_read(struct gem_softc *, int, int); 134 int gem_pint(struct gem_softc *); 135 int gem_eint(struct gem_softc *, u_int); 136 int gem_rint(struct gem_softc *); 137 int gem_tint(struct gem_softc *); 138 void gem_power(int, void *); 139 140 #ifdef GEM_DEBUG 141 static void gem_txsoft_print(const struct gem_softc *, int, int); 142 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 143 printf x 144 #else 145 #define DPRINTF(sc, x) /* nothing */ 146 #endif 147 148 #define ETHER_MIN_TX (ETHERMIN + sizeof(struct ether_header)) 149 150 int 151 gem_detach(struct gem_softc *sc, int flags) 152 { 153 int i; 154 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 155 bus_space_tag_t t = sc->sc_bustag; 156 bus_space_handle_t h = sc->sc_h1; 157 158 /* 159 * Free any resources we've allocated during the attach. 160 * Do this in reverse order and fall through. 161 */ 162 switch (sc->sc_att_stage) { 163 case GEM_ATT_BACKEND_2: 164 case GEM_ATT_BACKEND_1: 165 case GEM_ATT_FINISHED: 166 bus_space_write_4(t, h, GEM_INTMASK, ~(uint32_t)0); 167 gem_stop(&sc->sc_ethercom.ec_if, 1); 168 169 #ifdef GEM_COUNTERS 170 for (i = __arraycount(sc->sc_ev_rxhist); --i >= 0; ) 171 evcnt_detach(&sc->sc_ev_rxhist[i]); 172 evcnt_detach(&sc->sc_ev_rxnobuf); 173 evcnt_detach(&sc->sc_ev_rxfull); 174 evcnt_detach(&sc->sc_ev_rxint); 175 evcnt_detach(&sc->sc_ev_txint); 176 #endif 177 evcnt_detach(&sc->sc_ev_intr); 178 179 #if NRND > 0 180 rnd_detach_source(&sc->rnd_source); 181 #endif 182 ether_ifdetach(ifp); 183 if_detach(ifp); 184 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 185 186 callout_destroy(&sc->sc_tick_ch); 187 188 /*FALLTHROUGH*/ 189 case GEM_ATT_MII: 190 sc->sc_att_stage = GEM_ATT_MII; 191 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 192 /*FALLTHROUGH*/ 193 case GEM_ATT_7: 194 for (i = 0; i < GEM_NRXDESC; i++) { 195 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 196 bus_dmamap_destroy(sc->sc_dmatag, 197 sc->sc_rxsoft[i].rxs_dmamap); 198 } 199 /*FALLTHROUGH*/ 200 case GEM_ATT_6: 201 for (i = 0; i < GEM_TXQUEUELEN; i++) { 202 if (sc->sc_txsoft[i].txs_dmamap != NULL) 203 bus_dmamap_destroy(sc->sc_dmatag, 204 sc->sc_txsoft[i].txs_dmamap); 205 } 206 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 207 /*FALLTHROUGH*/ 208 case GEM_ATT_5: 209 bus_dmamap_unload(sc->sc_dmatag, sc->sc_nulldmamap); 210 /*FALLTHROUGH*/ 211 case GEM_ATT_4: 212 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_nulldmamap); 213 /*FALLTHROUGH*/ 214 case GEM_ATT_3: 215 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 216 /*FALLTHROUGH*/ 217 case GEM_ATT_2: 218 bus_dmamem_unmap(sc->sc_dmatag, sc->sc_control_data, 219 sizeof(struct gem_control_data)); 220 /*FALLTHROUGH*/ 221 case GEM_ATT_1: 222 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 223 /*FALLTHROUGH*/ 224 case GEM_ATT_0: 225 sc->sc_att_stage = GEM_ATT_0; 226 /*FALLTHROUGH*/ 227 case GEM_ATT_BACKEND_0: 228 break; 229 } 230 return 0; 231 } 232 233 static void 234 gem_partial_detach(struct gem_softc *sc, enum gem_attach_stage stage) 235 { 236 cfattach_t ca = device_cfattach(sc->sc_dev); 237 238 sc->sc_att_stage = stage; 239 (*ca->ca_detach)(sc->sc_dev, 0); 240 } 241 242 /* 243 * gem_attach: 244 * 245 * Attach a Gem interface to the system. 246 */ 247 void 248 gem_attach(struct gem_softc *sc, const uint8_t *enaddr) 249 { 250 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 251 struct mii_data *mii = &sc->sc_mii; 252 bus_space_tag_t t = sc->sc_bustag; 253 bus_space_handle_t h = sc->sc_h1; 254 struct ifmedia_entry *ifm; 255 int i, error, phyaddr; 256 u_int32_t v; 257 char *nullbuf; 258 259 /* Make sure the chip is stopped. */ 260 ifp->if_softc = sc; 261 gem_reset(sc); 262 263 /* 264 * Allocate the control data structures, and create and load the 265 * DMA map for it. gem_control_data is 9216 bytes, we have space for 266 * the padding buffer in the bus_dmamem_alloc()'d memory. 267 */ 268 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 269 sizeof(struct gem_control_data) + ETHER_MIN_TX, PAGE_SIZE, 270 0, &sc->sc_cdseg, 1, &sc->sc_cdnseg, 0)) != 0) { 271 aprint_error_dev(sc->sc_dev, 272 "unable to allocate control data, error = %d\n", 273 error); 274 gem_partial_detach(sc, GEM_ATT_0); 275 return; 276 } 277 278 /* XXX should map this in with correct endianness */ 279 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg, 280 sizeof(struct gem_control_data), (void **)&sc->sc_control_data, 281 BUS_DMA_COHERENT)) != 0) { 282 aprint_error_dev(sc->sc_dev, 283 "unable to map control data, error = %d\n", error); 284 gem_partial_detach(sc, GEM_ATT_1); 285 return; 286 } 287 288 nullbuf = 289 (char *)sc->sc_control_data + sizeof(struct gem_control_data); 290 291 if ((error = bus_dmamap_create(sc->sc_dmatag, 292 sizeof(struct gem_control_data), 1, 293 sizeof(struct gem_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 294 aprint_error_dev(sc->sc_dev, 295 "unable to create control data DMA map, error = %d\n", 296 error); 297 gem_partial_detach(sc, GEM_ATT_2); 298 return; 299 } 300 301 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 302 sc->sc_control_data, sizeof(struct gem_control_data), NULL, 303 0)) != 0) { 304 aprint_error_dev(sc->sc_dev, 305 "unable to load control data DMA map, error = %d\n", 306 error); 307 gem_partial_detach(sc, GEM_ATT_3); 308 return; 309 } 310 311 memset(nullbuf, 0, ETHER_MIN_TX); 312 if ((error = bus_dmamap_create(sc->sc_dmatag, 313 ETHER_MIN_TX, 1, ETHER_MIN_TX, 0, 0, &sc->sc_nulldmamap)) != 0) { 314 aprint_error_dev(sc->sc_dev, 315 "unable to create padding DMA map, error = %d\n", error); 316 gem_partial_detach(sc, GEM_ATT_4); 317 return; 318 } 319 320 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_nulldmamap, 321 nullbuf, ETHER_MIN_TX, NULL, 0)) != 0) { 322 aprint_error_dev(sc->sc_dev, 323 "unable to load padding DMA map, error = %d\n", error); 324 gem_partial_detach(sc, GEM_ATT_5); 325 return; 326 } 327 328 bus_dmamap_sync(sc->sc_dmatag, sc->sc_nulldmamap, 0, ETHER_MIN_TX, 329 BUS_DMASYNC_PREWRITE); 330 331 /* 332 * Initialize the transmit job descriptors. 333 */ 334 SIMPLEQ_INIT(&sc->sc_txfreeq); 335 SIMPLEQ_INIT(&sc->sc_txdirtyq); 336 337 /* 338 * Create the transmit buffer DMA maps. 339 */ 340 for (i = 0; i < GEM_TXQUEUELEN; i++) { 341 struct gem_txsoft *txs; 342 343 txs = &sc->sc_txsoft[i]; 344 txs->txs_mbuf = NULL; 345 if ((error = bus_dmamap_create(sc->sc_dmatag, 346 ETHER_MAX_LEN_JUMBO, GEM_NTXSEGS, 347 ETHER_MAX_LEN_JUMBO, 0, 0, 348 &txs->txs_dmamap)) != 0) { 349 aprint_error_dev(sc->sc_dev, 350 "unable to create tx DMA map %d, error = %d\n", 351 i, error); 352 gem_partial_detach(sc, GEM_ATT_6); 353 return; 354 } 355 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 356 } 357 358 /* 359 * Create the receive buffer DMA maps. 360 */ 361 for (i = 0; i < GEM_NRXDESC; i++) { 362 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, 363 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 364 aprint_error_dev(sc->sc_dev, 365 "unable to create rx DMA map %d, error = %d\n", 366 i, error); 367 gem_partial_detach(sc, GEM_ATT_7); 368 return; 369 } 370 sc->sc_rxsoft[i].rxs_mbuf = NULL; 371 } 372 373 /* Initialize ifmedia structures and MII info */ 374 mii->mii_ifp = ifp; 375 mii->mii_readreg = gem_mii_readreg; 376 mii->mii_writereg = gem_mii_writereg; 377 mii->mii_statchg = gem_mii_statchg; 378 379 sc->sc_ethercom.ec_mii = mii; 380 381 /* 382 * Initialization based on `GEM Gigabit Ethernet ASIC Specification' 383 * Section 3.2.1 `Initialization Sequence'. 384 * However, we can't assume SERDES or Serialink if neither 385 * GEM_MIF_CONFIG_MDI0 nor GEM_MIF_CONFIG_MDI1 are set 386 * being set, as both are set on Sun X1141A (with SERDES). So, 387 * we rely on our bus attachment setting GEM_SERDES or GEM_SERIAL. 388 * Also, for variants that report 2 PHY's, we prefer the external 389 * PHY over the internal PHY, so we look for that first. 390 */ 391 gem_mifinit(sc); 392 393 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) { 394 ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange, 395 ether_mediastatus); 396 /* Look for external PHY */ 397 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) { 398 sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL; 399 bus_space_write_4(t, h, GEM_MIF_CONFIG, 400 sc->sc_mif_config); 401 switch (sc->sc_variant) { 402 case GEM_SUN_ERI: 403 phyaddr = GEM_PHYAD_EXTERNAL; 404 break; 405 default: 406 phyaddr = MII_PHY_ANY; 407 break; 408 } 409 mii_attach(sc->sc_dev, mii, 0xffffffff, phyaddr, 410 MII_OFFSET_ANY, MIIF_FORCEANEG); 411 } 412 #ifdef GEM_DEBUG 413 else 414 aprint_debug_dev(sc->sc_dev, "using external PHY\n"); 415 #endif 416 /* Look for internal PHY if no external PHY was found */ 417 if (LIST_EMPTY(&mii->mii_phys) && 418 sc->sc_mif_config & GEM_MIF_CONFIG_MDI0) { 419 sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL; 420 bus_space_write_4(t, h, GEM_MIF_CONFIG, 421 sc->sc_mif_config); 422 switch (sc->sc_variant) { 423 case GEM_SUN_ERI: 424 case GEM_APPLE_K2_GMAC: 425 phyaddr = GEM_PHYAD_INTERNAL; 426 break; 427 case GEM_APPLE_GMAC: 428 phyaddr = GEM_PHYAD_EXTERNAL; 429 break; 430 default: 431 phyaddr = MII_PHY_ANY; 432 break; 433 } 434 mii_attach(sc->sc_dev, mii, 0xffffffff, phyaddr, 435 MII_OFFSET_ANY, MIIF_FORCEANEG); 436 #ifdef GEM_DEBUG 437 if (!LIST_EMPTY(&mii->mii_phys)) 438 aprint_debug_dev(sc->sc_dev, 439 "using internal PHY\n"); 440 #endif 441 } 442 if (LIST_EMPTY(&mii->mii_phys)) { 443 /* No PHY attached */ 444 aprint_error_dev(sc->sc_dev, 445 "PHY probe failed\n"); 446 gem_partial_detach(sc, GEM_ATT_MII); 447 return; 448 } else { 449 struct mii_softc *child; 450 451 /* 452 * Walk along the list of attached MII devices and 453 * establish an `MII instance' to `PHY number' 454 * mapping. 455 */ 456 LIST_FOREACH(child, &mii->mii_phys, mii_list) { 457 /* 458 * Note: we support just one PHY: the internal 459 * or external MII is already selected for us 460 * by the GEM_MIF_CONFIG register. 461 */ 462 if (child->mii_phy > 1 || child->mii_inst > 0) { 463 aprint_error_dev(sc->sc_dev, 464 "cannot accommodate MII device" 465 " %s at PHY %d, instance %d\n", 466 device_xname(child->mii_dev), 467 child->mii_phy, child->mii_inst); 468 continue; 469 } 470 sc->sc_phys[child->mii_inst] = child->mii_phy; 471 } 472 473 if (sc->sc_variant != GEM_SUN_ERI) 474 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 475 GEM_MII_DATAPATH_MII); 476 477 /* 478 * XXX - we can really do the following ONLY if the 479 * PHY indeed has the auto negotiation capability!! 480 */ 481 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 482 } 483 } else { 484 ifmedia_init(&mii->mii_media, IFM_IMASK, gem_ser_mediachange, 485 gem_ser_mediastatus); 486 /* SERDES or Serialink */ 487 if (sc->sc_flags & GEM_SERDES) { 488 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 489 GEM_MII_DATAPATH_SERDES); 490 } else { 491 sc->sc_flags |= GEM_SERIAL; 492 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 493 GEM_MII_DATAPATH_SERIAL); 494 } 495 496 aprint_normal_dev(sc->sc_dev, "using external PCS %s: ", 497 sc->sc_flags & GEM_SERDES ? "SERDES" : "Serialink"); 498 499 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO, 0, NULL); 500 /* Check for FDX and HDX capabilities */ 501 sc->sc_mii_anar = bus_space_read_4(t, h, GEM_MII_ANAR); 502 if (sc->sc_mii_anar & GEM_MII_ANEG_FUL_DUPLX) { 503 ifmedia_add(&sc->sc_mii.mii_media, 504 IFM_ETHER|IFM_1000_SX|IFM_MANUAL|IFM_FDX, 0, NULL); 505 aprint_normal("1000baseSX-FDX, "); 506 } 507 if (sc->sc_mii_anar & GEM_MII_ANEG_HLF_DUPLX) { 508 ifmedia_add(&sc->sc_mii.mii_media, 509 IFM_ETHER|IFM_1000_SX|IFM_MANUAL|IFM_HDX, 0, NULL); 510 aprint_normal("1000baseSX-HDX, "); 511 } 512 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 513 sc->sc_mii_media = IFM_AUTO; 514 aprint_normal("auto\n"); 515 516 gem_pcs_stop(sc, 1); 517 } 518 519 /* 520 * From this point forward, the attachment cannot fail. A failure 521 * before this point releases all resources that may have been 522 * allocated. 523 */ 524 525 /* Announce ourselves. */ 526 aprint_normal_dev(sc->sc_dev, "Ethernet address %s", 527 ether_sprintf(enaddr)); 528 529 /* Get RX FIFO size */ 530 sc->sc_rxfifosize = 64 * 531 bus_space_read_4(t, h, GEM_RX_FIFO_SIZE); 532 aprint_normal(", %uKB RX fifo", sc->sc_rxfifosize / 1024); 533 534 /* Get TX FIFO size */ 535 v = bus_space_read_4(t, h, GEM_TX_FIFO_SIZE); 536 aprint_normal(", %uKB TX fifo\n", v / 16); 537 538 /* Initialize ifnet structure. */ 539 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 540 ifp->if_softc = sc; 541 ifp->if_flags = 542 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 543 sc->sc_if_flags = ifp->if_flags; 544 #if 0 545 /* 546 * The GEM hardware supports basic TCP checksum offloading only. 547 * Several (all?) revisions (Sun rev. 01 and Apple rev. 00 and 80) 548 * have bugs in the receive checksum, so don't enable it for now. 549 */ 550 if ((GEM_IS_SUN(sc) && sc->sc_chiprev != 1) || 551 (GEM_IS_APPLE(sc) && 552 (sc->sc_chiprev != 0 && sc->sc_chiprev != 0x80))) 553 ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Rx; 554 #endif 555 ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Tx; 556 ifp->if_start = gem_start; 557 ifp->if_ioctl = gem_ioctl; 558 ifp->if_watchdog = gem_watchdog; 559 ifp->if_stop = gem_stop; 560 ifp->if_init = gem_init; 561 IFQ_SET_READY(&ifp->if_snd); 562 563 /* 564 * If we support GigE media, we support jumbo frames too. 565 * Unless we are Apple. 566 */ 567 TAILQ_FOREACH(ifm, &sc->sc_mii.mii_media.ifm_list, ifm_list) { 568 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_T || 569 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_SX || 570 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_LX || 571 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_CX) { 572 if (!GEM_IS_APPLE(sc)) 573 sc->sc_ethercom.ec_capabilities 574 |= ETHERCAP_JUMBO_MTU; 575 sc->sc_flags |= GEM_GIGABIT; 576 break; 577 } 578 } 579 580 /* claim 802.1q capability */ 581 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 582 583 /* Attach the interface. */ 584 if_attach(ifp); 585 ether_ifattach(ifp, enaddr); 586 ether_set_ifflags_cb(&sc->sc_ethercom, gem_ifflags_cb); 587 588 #if NRND > 0 589 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 590 RND_TYPE_NET, 0); 591 #endif 592 593 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, 594 NULL, device_xname(sc->sc_dev), "interrupts"); 595 #ifdef GEM_COUNTERS 596 evcnt_attach_dynamic(&sc->sc_ev_txint, EVCNT_TYPE_INTR, 597 &sc->sc_ev_intr, device_xname(sc->sc_dev), "tx interrupts"); 598 evcnt_attach_dynamic(&sc->sc_ev_rxint, EVCNT_TYPE_INTR, 599 &sc->sc_ev_intr, device_xname(sc->sc_dev), "rx interrupts"); 600 evcnt_attach_dynamic(&sc->sc_ev_rxfull, EVCNT_TYPE_INTR, 601 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx ring full"); 602 evcnt_attach_dynamic(&sc->sc_ev_rxnobuf, EVCNT_TYPE_INTR, 603 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx malloc failure"); 604 evcnt_attach_dynamic(&sc->sc_ev_rxhist[0], EVCNT_TYPE_INTR, 605 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 0desc"); 606 evcnt_attach_dynamic(&sc->sc_ev_rxhist[1], EVCNT_TYPE_INTR, 607 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 1desc"); 608 evcnt_attach_dynamic(&sc->sc_ev_rxhist[2], EVCNT_TYPE_INTR, 609 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 2desc"); 610 evcnt_attach_dynamic(&sc->sc_ev_rxhist[3], EVCNT_TYPE_INTR, 611 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 3desc"); 612 evcnt_attach_dynamic(&sc->sc_ev_rxhist[4], EVCNT_TYPE_INTR, 613 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >3desc"); 614 evcnt_attach_dynamic(&sc->sc_ev_rxhist[5], EVCNT_TYPE_INTR, 615 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >7desc"); 616 evcnt_attach_dynamic(&sc->sc_ev_rxhist[6], EVCNT_TYPE_INTR, 617 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >15desc"); 618 evcnt_attach_dynamic(&sc->sc_ev_rxhist[7], EVCNT_TYPE_INTR, 619 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >31desc"); 620 evcnt_attach_dynamic(&sc->sc_ev_rxhist[8], EVCNT_TYPE_INTR, 621 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >63desc"); 622 #endif 623 624 callout_init(&sc->sc_tick_ch, 0); 625 626 sc->sc_att_stage = GEM_ATT_FINISHED; 627 628 return; 629 } 630 631 void 632 gem_tick(void *arg) 633 { 634 struct gem_softc *sc = arg; 635 int s; 636 637 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) { 638 /* 639 * We have to reset everything if we failed to get a 640 * PCS interrupt. Restarting the callout is handled 641 * in gem_pcs_start(). 642 */ 643 gem_init(&sc->sc_ethercom.ec_if); 644 } else { 645 s = splnet(); 646 mii_tick(&sc->sc_mii); 647 splx(s); 648 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 649 } 650 } 651 652 static int 653 gem_bitwait(struct gem_softc *sc, bus_space_handle_t h, int r, u_int32_t clr, u_int32_t set) 654 { 655 int i; 656 u_int32_t reg; 657 658 for (i = TRIES; i--; DELAY(100)) { 659 reg = bus_space_read_4(sc->sc_bustag, h, r); 660 if ((reg & clr) == 0 && (reg & set) == set) 661 return (1); 662 } 663 return (0); 664 } 665 666 void 667 gem_reset(struct gem_softc *sc) 668 { 669 bus_space_tag_t t = sc->sc_bustag; 670 bus_space_handle_t h = sc->sc_h2; 671 int s; 672 673 s = splnet(); 674 DPRINTF(sc, ("%s: gem_reset\n", device_xname(sc->sc_dev))); 675 gem_reset_rx(sc); 676 gem_reset_tx(sc); 677 678 /* Do a full reset */ 679 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX|GEM_RESET_TX); 680 if (!gem_bitwait(sc, h, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0)) 681 aprint_error_dev(sc->sc_dev, "cannot reset device\n"); 682 splx(s); 683 } 684 685 686 /* 687 * gem_rxdrain: 688 * 689 * Drain the receive queue. 690 */ 691 static void 692 gem_rxdrain(struct gem_softc *sc) 693 { 694 struct gem_rxsoft *rxs; 695 int i; 696 697 for (i = 0; i < GEM_NRXDESC; i++) { 698 rxs = &sc->sc_rxsoft[i]; 699 if (rxs->rxs_mbuf != NULL) { 700 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 701 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 702 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 703 m_freem(rxs->rxs_mbuf); 704 rxs->rxs_mbuf = NULL; 705 } 706 } 707 } 708 709 /* 710 * Reset the whole thing. 711 */ 712 static void 713 gem_stop(struct ifnet *ifp, int disable) 714 { 715 struct gem_softc *sc = ifp->if_softc; 716 struct gem_txsoft *txs; 717 718 DPRINTF(sc, ("%s: gem_stop\n", device_xname(sc->sc_dev))); 719 720 callout_stop(&sc->sc_tick_ch); 721 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 722 gem_pcs_stop(sc, disable); 723 else 724 mii_down(&sc->sc_mii); 725 726 /* XXX - Should we reset these instead? */ 727 gem_disable_tx(sc); 728 gem_disable_rx(sc); 729 730 /* 731 * Release any queued transmit buffers. 732 */ 733 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 734 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 735 if (txs->txs_mbuf != NULL) { 736 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 0, 737 txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 738 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 739 m_freem(txs->txs_mbuf); 740 txs->txs_mbuf = NULL; 741 } 742 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 743 } 744 745 /* 746 * Mark the interface down and cancel the watchdog timer. 747 */ 748 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 749 sc->sc_if_flags = ifp->if_flags; 750 ifp->if_timer = 0; 751 752 if (disable) 753 gem_rxdrain(sc); 754 } 755 756 757 /* 758 * Reset the receiver 759 */ 760 int 761 gem_reset_rx(struct gem_softc *sc) 762 { 763 bus_space_tag_t t = sc->sc_bustag; 764 bus_space_handle_t h = sc->sc_h1, h2 = sc->sc_h2; 765 766 /* 767 * Resetting while DMA is in progress can cause a bus hang, so we 768 * disable DMA first. 769 */ 770 gem_disable_rx(sc); 771 bus_space_write_4(t, h, GEM_RX_CONFIG, 0); 772 bus_space_barrier(t, h, GEM_RX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 773 /* Wait till it finishes */ 774 if (!gem_bitwait(sc, h, GEM_RX_CONFIG, 1, 0)) 775 aprint_error_dev(sc->sc_dev, "cannot disable read dma\n"); 776 777 /* Finally, reset the ERX */ 778 bus_space_write_4(t, h2, GEM_RESET, GEM_RESET_RX); 779 bus_space_barrier(t, h, GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE); 780 /* Wait till it finishes */ 781 if (!gem_bitwait(sc, h2, GEM_RESET, GEM_RESET_RX, 0)) { 782 aprint_error_dev(sc->sc_dev, "cannot reset receiver\n"); 783 return (1); 784 } 785 return (0); 786 } 787 788 789 /* 790 * Reset the receiver DMA engine. 791 * 792 * Intended to be used in case of GEM_INTR_RX_TAG_ERR, GEM_MAC_RX_OVERFLOW 793 * etc in order to reset the receiver DMA engine only and not do a full 794 * reset which amongst others also downs the link and clears the FIFOs. 795 */ 796 static void 797 gem_reset_rxdma(struct gem_softc *sc) 798 { 799 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 800 bus_space_tag_t t = sc->sc_bustag; 801 bus_space_handle_t h = sc->sc_h1; 802 int i; 803 804 if (gem_reset_rx(sc) != 0) { 805 gem_init(ifp); 806 return; 807 } 808 for (i = 0; i < GEM_NRXDESC; i++) 809 if (sc->sc_rxsoft[i].rxs_mbuf != NULL) 810 GEM_UPDATE_RXDESC(sc, i); 811 sc->sc_rxptr = 0; 812 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE); 813 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD); 814 815 /* Reprogram Descriptor Ring Base Addresses */ 816 /* NOTE: we use only 32-bit DMA addresses here. */ 817 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0); 818 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 819 820 /* Redo ERX Configuration */ 821 gem_rx_common(sc); 822 823 /* Give the reciever a swift kick */ 824 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC - 4); 825 } 826 827 /* 828 * Common RX configuration for gem_init() and gem_reset_rxdma(). 829 */ 830 static void 831 gem_rx_common(struct gem_softc *sc) 832 { 833 bus_space_tag_t t = sc->sc_bustag; 834 bus_space_handle_t h = sc->sc_h1; 835 u_int32_t v; 836 837 /* Encode Receive Descriptor ring size: four possible values */ 838 v = gem_ringsize(GEM_NRXDESC /*XXX*/); 839 840 /* Set receive h/w checksum offset */ 841 #ifdef INET 842 v |= (ETHER_HDR_LEN + sizeof(struct ip) + 843 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 844 ETHER_VLAN_ENCAP_LEN : 0)) << GEM_RX_CONFIG_CXM_START_SHFT; 845 #endif 846 847 /* Enable RX DMA */ 848 bus_space_write_4(t, h, GEM_RX_CONFIG, 849 v | (GEM_THRSH_1024 << GEM_RX_CONFIG_FIFO_THRS_SHIFT) | 850 (2 << GEM_RX_CONFIG_FBOFF_SHFT) | GEM_RX_CONFIG_RXDMA_EN); 851 852 /* 853 * The following value is for an OFF Threshold of about 3/4 full 854 * and an ON Threshold of 1/4 full. 855 */ 856 bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH, 857 (3 * sc->sc_rxfifosize / 256) | 858 ((sc->sc_rxfifosize / 256) << 12)); 859 bus_space_write_4(t, h, GEM_RX_BLANKING, 860 (6 << GEM_RX_BLANKING_TIME_SHIFT) | 6); 861 } 862 863 /* 864 * Reset the transmitter 865 */ 866 int 867 gem_reset_tx(struct gem_softc *sc) 868 { 869 bus_space_tag_t t = sc->sc_bustag; 870 bus_space_handle_t h = sc->sc_h1, h2 = sc->sc_h2; 871 872 /* 873 * Resetting while DMA is in progress can cause a bus hang, so we 874 * disable DMA first. 875 */ 876 gem_disable_tx(sc); 877 bus_space_write_4(t, h, GEM_TX_CONFIG, 0); 878 bus_space_barrier(t, h, GEM_TX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 879 /* Wait till it finishes */ 880 if (!gem_bitwait(sc, h, GEM_TX_CONFIG, 1, 0)) 881 aprint_error_dev(sc->sc_dev, "cannot disable read dma\n"); 882 /* Wait 5ms extra. */ 883 delay(5000); 884 885 /* Finally, reset the ETX */ 886 bus_space_write_4(t, h2, GEM_RESET, GEM_RESET_TX); 887 bus_space_barrier(t, h, GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE); 888 /* Wait till it finishes */ 889 if (!gem_bitwait(sc, h2, GEM_RESET, GEM_RESET_TX, 0)) { 890 aprint_error_dev(sc->sc_dev, "cannot reset receiver\n"); 891 return (1); 892 } 893 return (0); 894 } 895 896 /* 897 * disable receiver. 898 */ 899 int 900 gem_disable_rx(struct gem_softc *sc) 901 { 902 bus_space_tag_t t = sc->sc_bustag; 903 bus_space_handle_t h = sc->sc_h1; 904 u_int32_t cfg; 905 906 /* Flip the enable bit */ 907 cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 908 cfg &= ~GEM_MAC_RX_ENABLE; 909 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg); 910 bus_space_barrier(t, h, GEM_MAC_RX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 911 /* Wait for it to finish */ 912 return (gem_bitwait(sc, h, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)); 913 } 914 915 /* 916 * disable transmitter. 917 */ 918 int 919 gem_disable_tx(struct gem_softc *sc) 920 { 921 bus_space_tag_t t = sc->sc_bustag; 922 bus_space_handle_t h = sc->sc_h1; 923 u_int32_t cfg; 924 925 /* Flip the enable bit */ 926 cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG); 927 cfg &= ~GEM_MAC_TX_ENABLE; 928 bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg); 929 bus_space_barrier(t, h, GEM_MAC_TX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 930 /* Wait for it to finish */ 931 return (gem_bitwait(sc, h, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)); 932 } 933 934 /* 935 * Initialize interface. 936 */ 937 int 938 gem_meminit(struct gem_softc *sc) 939 { 940 struct gem_rxsoft *rxs; 941 int i, error; 942 943 /* 944 * Initialize the transmit descriptor ring. 945 */ 946 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 947 for (i = 0; i < GEM_NTXDESC; i++) { 948 sc->sc_txdescs[i].gd_flags = 0; 949 sc->sc_txdescs[i].gd_addr = 0; 950 } 951 GEM_CDTXSYNC(sc, 0, GEM_NTXDESC, 952 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 953 sc->sc_txfree = GEM_NTXDESC-1; 954 sc->sc_txnext = 0; 955 sc->sc_txwin = 0; 956 957 /* 958 * Initialize the receive descriptor and receive job 959 * descriptor rings. 960 */ 961 for (i = 0; i < GEM_NRXDESC; i++) { 962 rxs = &sc->sc_rxsoft[i]; 963 if (rxs->rxs_mbuf == NULL) { 964 if ((error = gem_add_rxbuf(sc, i)) != 0) { 965 aprint_error_dev(sc->sc_dev, 966 "unable to allocate or map rx " 967 "buffer %d, error = %d\n", 968 i, error); 969 /* 970 * XXX Should attempt to run with fewer receive 971 * XXX buffers instead of just failing. 972 */ 973 gem_rxdrain(sc); 974 return (1); 975 } 976 } else 977 GEM_INIT_RXDESC(sc, i); 978 } 979 sc->sc_rxptr = 0; 980 sc->sc_meminited = 1; 981 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE); 982 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD); 983 984 return (0); 985 } 986 987 static int 988 gem_ringsize(int sz) 989 { 990 switch (sz) { 991 case 32: 992 return GEM_RING_SZ_32; 993 case 64: 994 return GEM_RING_SZ_64; 995 case 128: 996 return GEM_RING_SZ_128; 997 case 256: 998 return GEM_RING_SZ_256; 999 case 512: 1000 return GEM_RING_SZ_512; 1001 case 1024: 1002 return GEM_RING_SZ_1024; 1003 case 2048: 1004 return GEM_RING_SZ_2048; 1005 case 4096: 1006 return GEM_RING_SZ_4096; 1007 case 8192: 1008 return GEM_RING_SZ_8192; 1009 default: 1010 printf("gem: invalid Receive Descriptor ring size %d\n", sz); 1011 return GEM_RING_SZ_32; 1012 } 1013 } 1014 1015 1016 /* 1017 * Start PCS 1018 */ 1019 void 1020 gem_pcs_start(struct gem_softc *sc) 1021 { 1022 bus_space_tag_t t = sc->sc_bustag; 1023 bus_space_handle_t h = sc->sc_h1; 1024 uint32_t v; 1025 1026 #ifdef GEM_DEBUG 1027 aprint_debug_dev(sc->sc_dev, "gem_pcs_start()\n"); 1028 #endif 1029 1030 /* 1031 * Set up. We must disable the MII before modifying the 1032 * GEM_MII_ANAR register 1033 */ 1034 if (sc->sc_flags & GEM_SERDES) { 1035 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 1036 GEM_MII_DATAPATH_SERDES); 1037 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 1038 GEM_MII_SLINK_LOOPBACK); 1039 } else { 1040 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 1041 GEM_MII_DATAPATH_SERIAL); 1042 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 0); 1043 } 1044 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 1045 v = bus_space_read_4(t, h, GEM_MII_ANAR); 1046 v |= (GEM_MII_ANEG_SYM_PAUSE | GEM_MII_ANEG_ASYM_PAUSE); 1047 if (sc->sc_mii_media == IFM_AUTO) 1048 v |= (GEM_MII_ANEG_FUL_DUPLX | GEM_MII_ANEG_HLF_DUPLX); 1049 else if (sc->sc_mii_media == IFM_FDX) { 1050 v |= GEM_MII_ANEG_FUL_DUPLX; 1051 v &= ~GEM_MII_ANEG_HLF_DUPLX; 1052 } else if (sc->sc_mii_media == IFM_HDX) { 1053 v &= ~GEM_MII_ANEG_FUL_DUPLX; 1054 v |= GEM_MII_ANEG_HLF_DUPLX; 1055 } 1056 1057 /* Configure link. */ 1058 bus_space_write_4(t, h, GEM_MII_ANAR, v); 1059 bus_space_write_4(t, h, GEM_MII_CONTROL, 1060 GEM_MII_CONTROL_AUTONEG | GEM_MII_CONTROL_RAN); 1061 bus_space_write_4(t, h, GEM_MII_CONFIG, GEM_MII_CONFIG_ENABLE); 1062 gem_bitwait(sc, h, GEM_MII_STATUS, 0, GEM_MII_STATUS_ANEG_CPT); 1063 1064 /* Start the 10 second timer */ 1065 callout_reset(&sc->sc_tick_ch, hz * 10, gem_tick, sc); 1066 } 1067 1068 /* 1069 * Stop PCS 1070 */ 1071 void 1072 gem_pcs_stop(struct gem_softc *sc, int disable) 1073 { 1074 bus_space_tag_t t = sc->sc_bustag; 1075 bus_space_handle_t h = sc->sc_h1; 1076 1077 #ifdef GEM_DEBUG 1078 aprint_debug_dev(sc->sc_dev, "gem_pcs_stop()\n"); 1079 #endif 1080 1081 /* Tell link partner that we're going away */ 1082 bus_space_write_4(t, h, GEM_MII_ANAR, GEM_MII_ANEG_RF); 1083 1084 /* 1085 * Disable PCS MII. The documentation suggests that setting 1086 * GEM_MII_CONFIG_ENABLE to zero and then restarting auto- 1087 * negotiation will shut down the link. However, it appears 1088 * that we also need to unset the datapath mode. 1089 */ 1090 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 1091 bus_space_write_4(t, h, GEM_MII_CONTROL, 1092 GEM_MII_CONTROL_AUTONEG | GEM_MII_CONTROL_RAN); 1093 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, GEM_MII_DATAPATH_MII); 1094 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 1095 1096 if (disable) { 1097 if (sc->sc_flags & GEM_SERDES) 1098 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 1099 GEM_MII_SLINK_POWER_OFF); 1100 else 1101 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 1102 GEM_MII_SLINK_LOOPBACK | GEM_MII_SLINK_POWER_OFF); 1103 } 1104 1105 sc->sc_flags &= ~GEM_LINK; 1106 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_NONE; 1107 sc->sc_mii.mii_media_status = IFM_AVALID; 1108 } 1109 1110 1111 /* 1112 * Initialization of interface; set up initialization block 1113 * and transmit/receive descriptor rings. 1114 */ 1115 int 1116 gem_init(struct ifnet *ifp) 1117 { 1118 struct gem_softc *sc = ifp->if_softc; 1119 bus_space_tag_t t = sc->sc_bustag; 1120 bus_space_handle_t h = sc->sc_h1; 1121 int rc = 0, s; 1122 u_int max_frame_size; 1123 u_int32_t v; 1124 1125 s = splnet(); 1126 1127 DPRINTF(sc, ("%s: gem_init: calling stop\n", device_xname(sc->sc_dev))); 1128 /* 1129 * Initialization sequence. The numbered steps below correspond 1130 * to the sequence outlined in section 6.3.5.1 in the Ethernet 1131 * Channel Engine manual (part of the PCIO manual). 1132 * See also the STP2002-STQ document from Sun Microsystems. 1133 */ 1134 1135 /* step 1 & 2. Reset the Ethernet Channel */ 1136 gem_stop(ifp, 0); 1137 gem_reset(sc); 1138 DPRINTF(sc, ("%s: gem_init: restarting\n", device_xname(sc->sc_dev))); 1139 1140 /* Re-initialize the MIF */ 1141 gem_mifinit(sc); 1142 1143 /* Set up correct datapath for non-SERDES/Serialink */ 1144 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0 && 1145 sc->sc_variant != GEM_SUN_ERI) 1146 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 1147 GEM_MII_DATAPATH_MII); 1148 1149 /* Call MI reset function if any */ 1150 if (sc->sc_hwreset) 1151 (*sc->sc_hwreset)(sc); 1152 1153 /* step 3. Setup data structures in host memory */ 1154 if (gem_meminit(sc) != 0) 1155 return 1; 1156 1157 /* step 4. TX MAC registers & counters */ 1158 gem_init_regs(sc); 1159 max_frame_size = max(sc->sc_ethercom.ec_if.if_mtu, ETHERMTU); 1160 max_frame_size += ETHER_HDR_LEN + ETHER_CRC_LEN; 1161 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1162 max_frame_size += ETHER_VLAN_ENCAP_LEN; 1163 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 1164 max_frame_size|/* burst size */(0x2000<<16)); 1165 1166 /* step 5. RX MAC registers & counters */ 1167 gem_setladrf(sc); 1168 1169 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 1170 /* NOTE: we use only 32-bit DMA addresses here. */ 1171 bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 0); 1172 bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 1173 1174 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0); 1175 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 1176 1177 /* step 8. Global Configuration & Interrupt Mask */ 1178 gem_inten(sc); 1179 bus_space_write_4(t, h, GEM_MAC_RX_MASK, 1180 GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT); 1181 bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXX */ 1182 bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 1183 GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME); 1184 1185 /* step 9. ETX Configuration: use mostly default values */ 1186 1187 /* Enable TX DMA */ 1188 v = gem_ringsize(GEM_NTXDESC /*XXX*/); 1189 bus_space_write_4(t, h, GEM_TX_CONFIG, 1190 v | GEM_TX_CONFIG_TXDMA_EN | 1191 (((sc->sc_flags & GEM_GIGABIT ? 0x4FF : 0x100) << 10) & 1192 GEM_TX_CONFIG_TXFIFO_TH)); 1193 bus_space_write_4(t, h, GEM_TX_KICK, sc->sc_txnext); 1194 1195 /* step 10. ERX Configuration */ 1196 gem_rx_common(sc); 1197 1198 /* step 11. Configure Media */ 1199 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0 && 1200 (rc = mii_ifmedia_change(&sc->sc_mii)) != 0) 1201 goto out; 1202 1203 /* step 12. RX_MAC Configuration Register */ 1204 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 1205 v |= GEM_MAC_RX_ENABLE | GEM_MAC_RX_STRIP_CRC; 1206 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 1207 1208 /* step 14. Issue Transmit Pending command */ 1209 1210 /* Call MI initialization function if any */ 1211 if (sc->sc_hwinit) 1212 (*sc->sc_hwinit)(sc); 1213 1214 1215 /* step 15. Give the reciever a swift kick */ 1216 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4); 1217 1218 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 1219 /* Configure PCS */ 1220 gem_pcs_start(sc); 1221 else 1222 /* Start the one second timer. */ 1223 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 1224 1225 sc->sc_flags &= ~GEM_LINK; 1226 ifp->if_flags |= IFF_RUNNING; 1227 ifp->if_flags &= ~IFF_OACTIVE; 1228 ifp->if_timer = 0; 1229 sc->sc_if_flags = ifp->if_flags; 1230 out: 1231 splx(s); 1232 1233 return (0); 1234 } 1235 1236 void 1237 gem_init_regs(struct gem_softc *sc) 1238 { 1239 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1240 bus_space_tag_t t = sc->sc_bustag; 1241 bus_space_handle_t h = sc->sc_h1; 1242 const u_char *laddr = CLLADDR(ifp->if_sadl); 1243 u_int32_t v; 1244 1245 /* These regs are not cleared on reset */ 1246 if (!sc->sc_inited) { 1247 1248 /* Load recommended values */ 1249 bus_space_write_4(t, h, GEM_MAC_IPG0, 0x00); 1250 bus_space_write_4(t, h, GEM_MAC_IPG1, 0x08); 1251 bus_space_write_4(t, h, GEM_MAC_IPG2, 0x04); 1252 1253 bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 1254 /* Max frame and max burst size */ 1255 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 1256 ETHER_MAX_LEN | (0x2000<<16)); 1257 1258 bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x07); 1259 bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x04); 1260 bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10); 1261 bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088); 1262 bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED, 1263 ((laddr[5]<<8)|laddr[4])&0x3ff); 1264 1265 /* Secondary MAC addr set to 0:0:0:0:0:0 */ 1266 bus_space_write_4(t, h, GEM_MAC_ADDR3, 0); 1267 bus_space_write_4(t, h, GEM_MAC_ADDR4, 0); 1268 bus_space_write_4(t, h, GEM_MAC_ADDR5, 0); 1269 1270 /* MAC control addr set to 01:80:c2:00:00:01 */ 1271 bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001); 1272 bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200); 1273 bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180); 1274 1275 /* MAC filter addr set to 0:0:0:0:0:0 */ 1276 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0); 1277 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0); 1278 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0); 1279 1280 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0); 1281 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0); 1282 1283 sc->sc_inited = 1; 1284 } 1285 1286 /* Counters need to be zeroed */ 1287 bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0); 1288 bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0); 1289 bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0); 1290 bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0); 1291 bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0); 1292 bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0); 1293 bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0); 1294 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 1295 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 1296 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 1297 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 1298 1299 /* Set XOFF PAUSE time. */ 1300 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); 1301 1302 /* 1303 * Set the internal arbitration to "infinite" bursts of the 1304 * maximum length of 31 * 64 bytes so DMA transfers aren't 1305 * split up in cache line size chunks. This greatly improves 1306 * especially RX performance. 1307 * Enable silicon bug workarounds for the Apple variants. 1308 */ 1309 bus_space_write_4(t, h, GEM_CONFIG, 1310 GEM_CONFIG_TXDMA_LIMIT | GEM_CONFIG_RXDMA_LIMIT | 1311 ((sc->sc_flags & GEM_PCI) ? 1312 GEM_CONFIG_BURST_INF : GEM_CONFIG_BURST_64) | (GEM_IS_APPLE(sc) ? 1313 GEM_CONFIG_RONPAULBIT | GEM_CONFIG_BUG2FIX : 0)); 1314 1315 /* 1316 * Set the station address. 1317 */ 1318 bus_space_write_4(t, h, GEM_MAC_ADDR0, (laddr[4]<<8)|laddr[5]); 1319 bus_space_write_4(t, h, GEM_MAC_ADDR1, (laddr[2]<<8)|laddr[3]); 1320 bus_space_write_4(t, h, GEM_MAC_ADDR2, (laddr[0]<<8)|laddr[1]); 1321 1322 /* 1323 * Enable MII outputs. Enable GMII if there is a gigabit PHY. 1324 */ 1325 sc->sc_mif_config = bus_space_read_4(t, h, GEM_MIF_CONFIG); 1326 v = GEM_MAC_XIF_TX_MII_ENA; 1327 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) { 1328 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) { 1329 v |= GEM_MAC_XIF_FDPLX_LED; 1330 if (sc->sc_flags & GEM_GIGABIT) 1331 v |= GEM_MAC_XIF_GMII_MODE; 1332 } 1333 } else { 1334 v |= GEM_MAC_XIF_GMII_MODE; 1335 } 1336 bus_space_write_4(t, h, GEM_MAC_XIF_CONFIG, v); 1337 } 1338 1339 #ifdef GEM_DEBUG 1340 static void 1341 gem_txsoft_print(const struct gem_softc *sc, int firstdesc, int lastdesc) 1342 { 1343 int i; 1344 1345 for (i = firstdesc;; i = GEM_NEXTTX(i)) { 1346 printf("descriptor %d:\t", i); 1347 printf("gd_flags: 0x%016" PRIx64 "\t", 1348 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags)); 1349 printf("gd_addr: 0x%016" PRIx64 "\n", 1350 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr)); 1351 if (i == lastdesc) 1352 break; 1353 } 1354 } 1355 #endif 1356 1357 static void 1358 gem_start(struct ifnet *ifp) 1359 { 1360 struct gem_softc *sc = ifp->if_softc; 1361 struct mbuf *m0, *m; 1362 struct gem_txsoft *txs; 1363 bus_dmamap_t dmamap; 1364 int error, firsttx, nexttx = -1, lasttx = -1, ofree, seg; 1365 uint64_t flags = 0; 1366 1367 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1368 return; 1369 1370 /* 1371 * Remember the previous number of free descriptors and 1372 * the first descriptor we'll use. 1373 */ 1374 ofree = sc->sc_txfree; 1375 firsttx = sc->sc_txnext; 1376 1377 DPRINTF(sc, ("%s: gem_start: txfree %d, txnext %d\n", 1378 device_xname(sc->sc_dev), ofree, firsttx)); 1379 1380 /* 1381 * Loop through the send queue, setting up transmit descriptors 1382 * until we drain the queue, or use up all available transmit 1383 * descriptors. 1384 */ 1385 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 1386 sc->sc_txfree != 0) { 1387 /* 1388 * Grab a packet off the queue. 1389 */ 1390 IFQ_POLL(&ifp->if_snd, m0); 1391 if (m0 == NULL) 1392 break; 1393 m = NULL; 1394 1395 dmamap = txs->txs_dmamap; 1396 1397 /* 1398 * Load the DMA map. If this fails, the packet either 1399 * didn't fit in the alloted number of segments, or we were 1400 * short on resources. In this case, we'll copy and try 1401 * again. 1402 */ 1403 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m0, 1404 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0 || 1405 (m0->m_pkthdr.len < ETHER_MIN_TX && 1406 dmamap->dm_nsegs == GEM_NTXSEGS)) { 1407 if (m0->m_pkthdr.len > MCLBYTES) { 1408 aprint_error_dev(sc->sc_dev, 1409 "unable to allocate jumbo Tx cluster\n"); 1410 IFQ_DEQUEUE(&ifp->if_snd, m0); 1411 m_freem(m0); 1412 continue; 1413 } 1414 MGETHDR(m, M_DONTWAIT, MT_DATA); 1415 if (m == NULL) { 1416 aprint_error_dev(sc->sc_dev, 1417 "unable to allocate Tx mbuf\n"); 1418 break; 1419 } 1420 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1421 if (m0->m_pkthdr.len > MHLEN) { 1422 MCLGET(m, M_DONTWAIT); 1423 if ((m->m_flags & M_EXT) == 0) { 1424 aprint_error_dev(sc->sc_dev, 1425 "unable to allocate Tx cluster\n"); 1426 m_freem(m); 1427 break; 1428 } 1429 } 1430 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1431 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1432 error = bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, 1433 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1434 if (error) { 1435 aprint_error_dev(sc->sc_dev, 1436 "unable to load Tx buffer, error = %d\n", 1437 error); 1438 break; 1439 } 1440 } 1441 1442 /* 1443 * Ensure we have enough descriptors free to describe 1444 * the packet. 1445 */ 1446 if (dmamap->dm_nsegs > ((m0->m_pkthdr.len < ETHER_MIN_TX) ? 1447 (sc->sc_txfree - 1) : sc->sc_txfree)) { 1448 /* 1449 * Not enough free descriptors to transmit this 1450 * packet. We haven't committed to anything yet, 1451 * so just unload the DMA map, put the packet 1452 * back on the queue, and punt. Notify the upper 1453 * layer that there are no more slots left. 1454 * 1455 * XXX We could allocate an mbuf and copy, but 1456 * XXX it is worth it? 1457 */ 1458 ifp->if_flags |= IFF_OACTIVE; 1459 sc->sc_if_flags = ifp->if_flags; 1460 bus_dmamap_unload(sc->sc_dmatag, dmamap); 1461 if (m != NULL) 1462 m_freem(m); 1463 break; 1464 } 1465 1466 IFQ_DEQUEUE(&ifp->if_snd, m0); 1467 if (m != NULL) { 1468 m_freem(m0); 1469 m0 = m; 1470 } 1471 1472 /* 1473 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1474 */ 1475 1476 /* Sync the DMA map. */ 1477 bus_dmamap_sync(sc->sc_dmatag, dmamap, 0, dmamap->dm_mapsize, 1478 BUS_DMASYNC_PREWRITE); 1479 1480 /* 1481 * Initialize the transmit descriptors. 1482 */ 1483 for (nexttx = sc->sc_txnext, seg = 0; 1484 seg < dmamap->dm_nsegs; 1485 seg++, nexttx = GEM_NEXTTX(nexttx)) { 1486 1487 /* 1488 * If this is the first descriptor we're 1489 * enqueueing, set the start of packet flag, 1490 * and the checksum stuff if we want the hardware 1491 * to do it. 1492 */ 1493 sc->sc_txdescs[nexttx].gd_addr = 1494 GEM_DMA_WRITE(sc, dmamap->dm_segs[seg].ds_addr); 1495 flags = dmamap->dm_segs[seg].ds_len & GEM_TD_BUFSIZE; 1496 if (nexttx == firsttx) { 1497 flags |= GEM_TD_START_OF_PACKET; 1498 if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) { 1499 sc->sc_txwin = 0; 1500 flags |= GEM_TD_INTERRUPT_ME; 1501 } 1502 1503 #ifdef INET 1504 /* h/w checksum */ 1505 if (ifp->if_csum_flags_tx & M_CSUM_TCPv4 && 1506 m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1507 struct ether_header *eh; 1508 uint16_t offset, start; 1509 1510 eh = mtod(m0, struct ether_header *); 1511 switch (ntohs(eh->ether_type)) { 1512 case ETHERTYPE_IP: 1513 start = ETHER_HDR_LEN; 1514 break; 1515 case ETHERTYPE_VLAN: 1516 start = ETHER_HDR_LEN + 1517 ETHER_VLAN_ENCAP_LEN; 1518 break; 1519 default: 1520 /* unsupported, drop it */ 1521 m_free(m0); 1522 continue; 1523 } 1524 start += M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 1525 offset = M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data) + start; 1526 flags |= (start << 1527 GEM_TD_CXSUM_STARTSHFT) | 1528 (offset << 1529 GEM_TD_CXSUM_STUFFSHFT) | 1530 GEM_TD_CXSUM_ENABLE; 1531 } 1532 #endif 1533 } 1534 if (seg == dmamap->dm_nsegs - 1) { 1535 flags |= GEM_TD_END_OF_PACKET; 1536 } else { 1537 /* last flag set outside of loop */ 1538 sc->sc_txdescs[nexttx].gd_flags = 1539 GEM_DMA_WRITE(sc, flags); 1540 } 1541 lasttx = nexttx; 1542 } 1543 if (m0->m_pkthdr.len < ETHER_MIN_TX) { 1544 /* add padding buffer at end of chain */ 1545 flags &= ~GEM_TD_END_OF_PACKET; 1546 sc->sc_txdescs[lasttx].gd_flags = 1547 GEM_DMA_WRITE(sc, flags); 1548 1549 sc->sc_txdescs[nexttx].gd_addr = 1550 GEM_DMA_WRITE(sc, 1551 sc->sc_nulldmamap->dm_segs[0].ds_addr); 1552 flags = ((ETHER_MIN_TX - m0->m_pkthdr.len) & 1553 GEM_TD_BUFSIZE) | GEM_TD_END_OF_PACKET; 1554 lasttx = nexttx; 1555 nexttx = GEM_NEXTTX(nexttx); 1556 seg++; 1557 } 1558 sc->sc_txdescs[lasttx].gd_flags = GEM_DMA_WRITE(sc, flags); 1559 1560 KASSERT(lasttx != -1); 1561 1562 /* 1563 * Store a pointer to the packet so we can free it later, 1564 * and remember what txdirty will be once the packet is 1565 * done. 1566 */ 1567 txs->txs_mbuf = m0; 1568 txs->txs_firstdesc = sc->sc_txnext; 1569 txs->txs_lastdesc = lasttx; 1570 txs->txs_ndescs = seg; 1571 1572 #ifdef GEM_DEBUG 1573 if (ifp->if_flags & IFF_DEBUG) { 1574 printf(" gem_start %p transmit chain:\n", txs); 1575 gem_txsoft_print(sc, txs->txs_firstdesc, 1576 txs->txs_lastdesc); 1577 } 1578 #endif 1579 1580 /* Sync the descriptors we're using. */ 1581 GEM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndescs, 1582 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1583 1584 /* Advance the tx pointer. */ 1585 sc->sc_txfree -= txs->txs_ndescs; 1586 sc->sc_txnext = nexttx; 1587 1588 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1589 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1590 1591 #if NBPFILTER > 0 1592 /* 1593 * Pass the packet to any BPF listeners. 1594 */ 1595 if (ifp->if_bpf) 1596 bpf_mtap(ifp->if_bpf, m0); 1597 #endif /* NBPFILTER > 0 */ 1598 } 1599 1600 if (txs == NULL || sc->sc_txfree == 0) { 1601 /* No more slots left; notify upper layer. */ 1602 ifp->if_flags |= IFF_OACTIVE; 1603 sc->sc_if_flags = ifp->if_flags; 1604 } 1605 1606 if (sc->sc_txfree != ofree) { 1607 DPRINTF(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 1608 device_xname(sc->sc_dev), lasttx, firsttx)); 1609 /* 1610 * The entire packet chain is set up. 1611 * Kick the transmitter. 1612 */ 1613 DPRINTF(sc, ("%s: gem_start: kicking tx %d\n", 1614 device_xname(sc->sc_dev), nexttx)); 1615 bus_space_write_4(sc->sc_bustag, sc->sc_h1, GEM_TX_KICK, 1616 sc->sc_txnext); 1617 1618 /* Set a watchdog timer in case the chip flakes out. */ 1619 ifp->if_timer = 5; 1620 DPRINTF(sc, ("%s: gem_start: watchdog %d\n", 1621 device_xname(sc->sc_dev), ifp->if_timer)); 1622 } 1623 } 1624 1625 /* 1626 * Transmit interrupt. 1627 */ 1628 int 1629 gem_tint(struct gem_softc *sc) 1630 { 1631 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1632 bus_space_tag_t t = sc->sc_bustag; 1633 bus_space_handle_t mac = sc->sc_h1; 1634 struct gem_txsoft *txs; 1635 int txlast; 1636 int progress = 0; 1637 u_int32_t v; 1638 1639 DPRINTF(sc, ("%s: gem_tint\n", device_xname(sc->sc_dev))); 1640 1641 /* Unload collision counters ... */ 1642 v = bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) + 1643 bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT); 1644 ifp->if_collisions += v + 1645 bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) + 1646 bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT); 1647 ifp->if_oerrors += v; 1648 1649 /* ... then clear the hardware counters. */ 1650 bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0); 1651 bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0); 1652 bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0); 1653 bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0); 1654 1655 /* 1656 * Go through our Tx list and free mbufs for those 1657 * frames that have been transmitted. 1658 */ 1659 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1660 /* 1661 * In theory, we could harvest some descriptors before 1662 * the ring is empty, but that's a bit complicated. 1663 * 1664 * GEM_TX_COMPLETION points to the last descriptor 1665 * processed +1. 1666 * 1667 * Let's assume that the NIC writes back to the Tx 1668 * descriptors before it updates the completion 1669 * register. If the NIC has posted writes to the 1670 * Tx descriptors, PCI ordering requires that the 1671 * posted writes flush to RAM before the register-read 1672 * finishes. So let's read the completion register, 1673 * before syncing the descriptors, so that we 1674 * examine Tx descriptors that are at least as 1675 * current as the completion register. 1676 */ 1677 txlast = bus_space_read_4(t, mac, GEM_TX_COMPLETION); 1678 DPRINTF(sc, 1679 ("gem_tint: txs->txs_lastdesc = %d, txlast = %d\n", 1680 txs->txs_lastdesc, txlast)); 1681 if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1682 if (txlast >= txs->txs_firstdesc && 1683 txlast <= txs->txs_lastdesc) 1684 break; 1685 } else if (txlast >= txs->txs_firstdesc || 1686 txlast <= txs->txs_lastdesc) 1687 break; 1688 1689 GEM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndescs, 1690 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1691 1692 #ifdef GEM_DEBUG /* XXX DMA synchronization? */ 1693 if (ifp->if_flags & IFF_DEBUG) { 1694 printf(" txsoft %p transmit chain:\n", txs); 1695 gem_txsoft_print(sc, txs->txs_firstdesc, 1696 txs->txs_lastdesc); 1697 } 1698 #endif 1699 1700 1701 DPRINTF(sc, ("gem_tint: releasing a desc\n")); 1702 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1703 1704 sc->sc_txfree += txs->txs_ndescs; 1705 1706 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 1707 0, txs->txs_dmamap->dm_mapsize, 1708 BUS_DMASYNC_POSTWRITE); 1709 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 1710 if (txs->txs_mbuf != NULL) { 1711 m_freem(txs->txs_mbuf); 1712 txs->txs_mbuf = NULL; 1713 } 1714 1715 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1716 1717 ifp->if_opackets++; 1718 progress = 1; 1719 } 1720 1721 #if 0 1722 DPRINTF(sc, ("gem_tint: GEM_TX_STATE_MACHINE %x " 1723 "GEM_TX_DATA_PTR %" PRIx64 "GEM_TX_COMPLETION %" PRIx32 "\n", 1724 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_TX_STATE_MACHINE), 1725 ((uint64_t)bus_space_read_4(sc->sc_bustag, sc->sc_h1, 1726 GEM_TX_DATA_PTR_HI) << 32) | 1727 bus_space_read_4(sc->sc_bustag, sc->sc_h1, 1728 GEM_TX_DATA_PTR_LO), 1729 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_TX_COMPLETION))); 1730 #endif 1731 1732 if (progress) { 1733 if (sc->sc_txfree == GEM_NTXDESC - 1) 1734 sc->sc_txwin = 0; 1735 1736 /* Freed some descriptors, so reset IFF_OACTIVE and restart. */ 1737 ifp->if_flags &= ~IFF_OACTIVE; 1738 sc->sc_if_flags = ifp->if_flags; 1739 ifp->if_timer = SIMPLEQ_EMPTY(&sc->sc_txdirtyq) ? 0 : 5; 1740 gem_start(ifp); 1741 } 1742 DPRINTF(sc, ("%s: gem_tint: watchdog %d\n", 1743 device_xname(sc->sc_dev), ifp->if_timer)); 1744 1745 return (1); 1746 } 1747 1748 /* 1749 * Receive interrupt. 1750 */ 1751 int 1752 gem_rint(struct gem_softc *sc) 1753 { 1754 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1755 bus_space_tag_t t = sc->sc_bustag; 1756 bus_space_handle_t h = sc->sc_h1; 1757 struct gem_rxsoft *rxs; 1758 struct mbuf *m; 1759 u_int64_t rxstat; 1760 u_int32_t rxcomp; 1761 int i, len, progress = 0; 1762 1763 DPRINTF(sc, ("%s: gem_rint\n", device_xname(sc->sc_dev))); 1764 1765 /* 1766 * Ignore spurious interrupt that sometimes occurs before 1767 * we are set up when we network boot. 1768 */ 1769 if (!sc->sc_meminited) 1770 return 1; 1771 1772 /* 1773 * Read the completion register once. This limits 1774 * how long the following loop can execute. 1775 */ 1776 rxcomp = bus_space_read_4(t, h, GEM_RX_COMPLETION); 1777 1778 /* 1779 * XXX Read the lastrx only once at the top for speed. 1780 */ 1781 DPRINTF(sc, ("gem_rint: sc->rxptr %d, complete %d\n", 1782 sc->sc_rxptr, rxcomp)); 1783 1784 /* 1785 * Go into the loop at least once. 1786 */ 1787 for (i = sc->sc_rxptr; i == sc->sc_rxptr || i != rxcomp; 1788 i = GEM_NEXTRX(i)) { 1789 rxs = &sc->sc_rxsoft[i]; 1790 1791 GEM_CDRXSYNC(sc, i, 1792 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1793 1794 rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags); 1795 1796 if (rxstat & GEM_RD_OWN) { 1797 GEM_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); 1798 /* 1799 * We have processed all of the receive buffers. 1800 */ 1801 break; 1802 } 1803 1804 progress++; 1805 ifp->if_ipackets++; 1806 1807 if (rxstat & GEM_RD_BAD_CRC) { 1808 ifp->if_ierrors++; 1809 aprint_error_dev(sc->sc_dev, 1810 "receive error: CRC error\n"); 1811 GEM_INIT_RXDESC(sc, i); 1812 continue; 1813 } 1814 1815 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1816 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1817 #ifdef GEM_DEBUG 1818 if (ifp->if_flags & IFF_DEBUG) { 1819 printf(" rxsoft %p descriptor %d: ", rxs, i); 1820 printf("gd_flags: 0x%016llx\t", (long long) 1821 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags)); 1822 printf("gd_addr: 0x%016llx\n", (long long) 1823 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr)); 1824 } 1825 #endif 1826 1827 /* No errors; receive the packet. */ 1828 len = GEM_RD_BUFLEN(rxstat); 1829 1830 /* 1831 * Allocate a new mbuf cluster. If that fails, we are 1832 * out of memory, and must drop the packet and recycle 1833 * the buffer that's already attached to this descriptor. 1834 */ 1835 m = rxs->rxs_mbuf; 1836 if (gem_add_rxbuf(sc, i) != 0) { 1837 GEM_COUNTER_INCR(sc, sc_ev_rxnobuf); 1838 ifp->if_ierrors++; 1839 GEM_INIT_RXDESC(sc, i); 1840 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1841 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1842 continue; 1843 } 1844 m->m_data += 2; /* We're already off by two */ 1845 1846 m->m_pkthdr.rcvif = ifp; 1847 m->m_pkthdr.len = m->m_len = len; 1848 1849 #if NBPFILTER > 0 1850 /* 1851 * Pass this up to any BPF listeners, but only 1852 * pass it up the stack if it's for us. 1853 */ 1854 if (ifp->if_bpf) 1855 bpf_mtap(ifp->if_bpf, m); 1856 #endif /* NBPFILTER > 0 */ 1857 1858 #ifdef INET 1859 /* hardware checksum */ 1860 if (ifp->if_csum_flags_rx & M_CSUM_TCPv4) { 1861 struct ether_header *eh; 1862 struct ip *ip; 1863 int32_t hlen, pktlen; 1864 1865 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1866 pktlen = m->m_pkthdr.len - ETHER_HDR_LEN - 1867 ETHER_VLAN_ENCAP_LEN; 1868 eh = (struct ether_header *) (mtod(m, char *) + 1869 ETHER_VLAN_ENCAP_LEN); 1870 } else { 1871 pktlen = m->m_pkthdr.len - ETHER_HDR_LEN; 1872 eh = mtod(m, struct ether_header *); 1873 } 1874 if (ntohs(eh->ether_type) != ETHERTYPE_IP) 1875 goto swcsum; 1876 ip = (struct ip *) ((char *)eh + ETHER_HDR_LEN); 1877 1878 /* IPv4 only */ 1879 if (ip->ip_v != IPVERSION) 1880 goto swcsum; 1881 1882 hlen = ip->ip_hl << 2; 1883 if (hlen < sizeof(struct ip)) 1884 goto swcsum; 1885 1886 /* 1887 * bail if too short, has random trailing garbage, 1888 * truncated, fragment, or has ethernet pad. 1889 */ 1890 if ((ntohs(ip->ip_len) < hlen) || 1891 (ntohs(ip->ip_len) != pktlen) || 1892 (ntohs(ip->ip_off) & (IP_MF | IP_OFFMASK))) 1893 goto swcsum; 1894 1895 switch (ip->ip_p) { 1896 case IPPROTO_TCP: 1897 if (! (ifp->if_csum_flags_rx & M_CSUM_TCPv4)) 1898 goto swcsum; 1899 if (pktlen < (hlen + sizeof(struct tcphdr))) 1900 goto swcsum; 1901 m->m_pkthdr.csum_flags = M_CSUM_TCPv4; 1902 break; 1903 case IPPROTO_UDP: 1904 /* FALLTHROUGH */ 1905 default: 1906 goto swcsum; 1907 } 1908 1909 /* the uncomplemented sum is expected */ 1910 m->m_pkthdr.csum_data = (~rxstat) & GEM_RD_CHECKSUM; 1911 1912 /* if the pkt had ip options, we have to deduct them */ 1913 if (hlen > sizeof(struct ip)) { 1914 uint16_t *opts; 1915 uint32_t optsum, temp; 1916 1917 optsum = 0; 1918 temp = hlen - sizeof(struct ip); 1919 opts = (uint16_t *) ((char *) ip + 1920 sizeof(struct ip)); 1921 1922 while (temp > 1) { 1923 optsum += ntohs(*opts++); 1924 temp -= 2; 1925 } 1926 while (optsum >> 16) 1927 optsum = (optsum >> 16) + 1928 (optsum & 0xffff); 1929 1930 /* Deduct ip opts sum from hwsum. */ 1931 m->m_pkthdr.csum_data += (uint16_t)~optsum; 1932 1933 while (m->m_pkthdr.csum_data >> 16) 1934 m->m_pkthdr.csum_data = 1935 (m->m_pkthdr.csum_data >> 16) + 1936 (m->m_pkthdr.csum_data & 1937 0xffff); 1938 } 1939 1940 m->m_pkthdr.csum_flags |= M_CSUM_DATA | 1941 M_CSUM_NO_PSEUDOHDR; 1942 } else 1943 swcsum: 1944 m->m_pkthdr.csum_flags = 0; 1945 #endif 1946 /* Pass it on. */ 1947 (*ifp->if_input)(ifp, m); 1948 } 1949 1950 if (progress) { 1951 /* Update the receive pointer. */ 1952 if (i == sc->sc_rxptr) { 1953 GEM_COUNTER_INCR(sc, sc_ev_rxfull); 1954 #ifdef GEM_DEBUG 1955 if (ifp->if_flags & IFF_DEBUG) 1956 printf("%s: rint: ring wrap\n", 1957 device_xname(sc->sc_dev)); 1958 #endif 1959 } 1960 sc->sc_rxptr = i; 1961 bus_space_write_4(t, h, GEM_RX_KICK, GEM_PREVRX(i)); 1962 } 1963 #ifdef GEM_COUNTERS 1964 if (progress <= 4) { 1965 GEM_COUNTER_INCR(sc, sc_ev_rxhist[progress]); 1966 } else if (progress < 32) { 1967 if (progress < 16) 1968 GEM_COUNTER_INCR(sc, sc_ev_rxhist[5]); 1969 else 1970 GEM_COUNTER_INCR(sc, sc_ev_rxhist[6]); 1971 1972 } else { 1973 if (progress < 64) 1974 GEM_COUNTER_INCR(sc, sc_ev_rxhist[7]); 1975 else 1976 GEM_COUNTER_INCR(sc, sc_ev_rxhist[8]); 1977 } 1978 #endif 1979 1980 DPRINTF(sc, ("gem_rint: done sc->rxptr %d, complete %d\n", 1981 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION))); 1982 1983 /* Read error counters ... */ 1984 ifp->if_ierrors += 1985 bus_space_read_4(t, h, GEM_MAC_RX_LEN_ERR_CNT) + 1986 bus_space_read_4(t, h, GEM_MAC_RX_ALIGN_ERR) + 1987 bus_space_read_4(t, h, GEM_MAC_RX_CRC_ERR_CNT) + 1988 bus_space_read_4(t, h, GEM_MAC_RX_CODE_VIOL); 1989 1990 /* ... then clear the hardware counters. */ 1991 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 1992 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 1993 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 1994 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 1995 1996 return (1); 1997 } 1998 1999 2000 /* 2001 * gem_add_rxbuf: 2002 * 2003 * Add a receive buffer to the indicated descriptor. 2004 */ 2005 int 2006 gem_add_rxbuf(struct gem_softc *sc, int idx) 2007 { 2008 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2009 struct mbuf *m; 2010 int error; 2011 2012 MGETHDR(m, M_DONTWAIT, MT_DATA); 2013 if (m == NULL) 2014 return (ENOBUFS); 2015 2016 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2017 MCLGET(m, M_DONTWAIT); 2018 if ((m->m_flags & M_EXT) == 0) { 2019 m_freem(m); 2020 return (ENOBUFS); 2021 } 2022 2023 #ifdef GEM_DEBUG 2024 /* bzero the packet to check DMA */ 2025 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 2026 #endif 2027 2028 if (rxs->rxs_mbuf != NULL) 2029 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 2030 2031 rxs->rxs_mbuf = m; 2032 2033 error = bus_dmamap_load(sc->sc_dmatag, rxs->rxs_dmamap, 2034 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2035 BUS_DMA_READ|BUS_DMA_NOWAIT); 2036 if (error) { 2037 aprint_error_dev(sc->sc_dev, 2038 "can't load rx DMA map %d, error = %d\n", idx, error); 2039 panic("gem_add_rxbuf"); /* XXX */ 2040 } 2041 2042 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 2043 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2044 2045 GEM_INIT_RXDESC(sc, idx); 2046 2047 return (0); 2048 } 2049 2050 2051 int 2052 gem_eint(struct gem_softc *sc, u_int status) 2053 { 2054 char bits[128]; 2055 u_int32_t r, v; 2056 2057 if ((status & GEM_INTR_MIF) != 0) { 2058 printf("%s: XXXlink status changed\n", device_xname(sc->sc_dev)); 2059 return (1); 2060 } 2061 2062 if ((status & GEM_INTR_RX_TAG_ERR) != 0) { 2063 gem_reset_rxdma(sc); 2064 return (1); 2065 } 2066 2067 if (status & GEM_INTR_BERR) { 2068 if (sc->sc_flags & GEM_PCI) 2069 r = GEM_ERROR_STATUS; 2070 else 2071 r = GEM_SBUS_ERROR_STATUS; 2072 bus_space_read_4(sc->sc_bustag, sc->sc_h2, r); 2073 v = bus_space_read_4(sc->sc_bustag, sc->sc_h2, r); 2074 aprint_error_dev(sc->sc_dev, "bus error interrupt: 0x%02x\n", 2075 v); 2076 return (1); 2077 } 2078 snprintb(bits, sizeof(bits), GEM_INTR_BITS, status); 2079 printf("%s: status=%s\n", device_xname(sc->sc_dev), bits); 2080 2081 return (1); 2082 } 2083 2084 2085 /* 2086 * PCS interrupts. 2087 * We should receive these when the link status changes, but sometimes 2088 * we don't receive them for link up. We compensate for this in the 2089 * gem_tick() callout. 2090 */ 2091 int 2092 gem_pint(struct gem_softc *sc) 2093 { 2094 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2095 bus_space_tag_t t = sc->sc_bustag; 2096 bus_space_handle_t h = sc->sc_h1; 2097 u_int32_t v, v2; 2098 2099 /* 2100 * Clear the PCS interrupt from GEM_STATUS. The PCS register is 2101 * latched, so we have to read it twice. There is only one bit in 2102 * use, so the value is meaningless. 2103 */ 2104 bus_space_read_4(t, h, GEM_MII_INTERRUP_STATUS); 2105 bus_space_read_4(t, h, GEM_MII_INTERRUP_STATUS); 2106 2107 if ((ifp->if_flags & IFF_UP) == 0) 2108 return 1; 2109 2110 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) 2111 return 1; 2112 2113 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2114 /* If we see remote fault, our link partner is probably going away */ 2115 if ((v & GEM_MII_STATUS_REM_FLT) != 0) { 2116 gem_bitwait(sc, h, GEM_MII_STATUS, GEM_MII_STATUS_REM_FLT, 0); 2117 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2118 /* Otherwise, we may need to wait after auto-negotiation completes */ 2119 } else if ((v & (GEM_MII_STATUS_LINK_STS | GEM_MII_STATUS_ANEG_CPT)) == 2120 GEM_MII_STATUS_ANEG_CPT) { 2121 gem_bitwait(sc, h, GEM_MII_STATUS, 0, GEM_MII_STATUS_LINK_STS); 2122 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2123 } 2124 if ((v & GEM_MII_STATUS_LINK_STS) != 0) { 2125 if (sc->sc_flags & GEM_LINK) { 2126 return 1; 2127 } 2128 callout_stop(&sc->sc_tick_ch); 2129 v = bus_space_read_4(t, h, GEM_MII_ANAR); 2130 v2 = bus_space_read_4(t, h, GEM_MII_ANLPAR); 2131 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_1000_SX; 2132 sc->sc_mii.mii_media_status = IFM_AVALID | IFM_ACTIVE; 2133 v &= v2; 2134 if (v & GEM_MII_ANEG_FUL_DUPLX) { 2135 sc->sc_mii.mii_media_active |= IFM_FDX; 2136 #ifdef GEM_DEBUG 2137 aprint_debug_dev(sc->sc_dev, "link up: full duplex\n"); 2138 #endif 2139 } else if (v & GEM_MII_ANEG_HLF_DUPLX) { 2140 sc->sc_mii.mii_media_active |= IFM_HDX; 2141 #ifdef GEM_DEBUG 2142 aprint_debug_dev(sc->sc_dev, "link up: half duplex\n"); 2143 #endif 2144 } else { 2145 #ifdef GEM_DEBUG 2146 aprint_debug_dev(sc->sc_dev, "duplex mismatch\n"); 2147 #endif 2148 } 2149 gem_statuschange(sc); 2150 } else { 2151 if ((sc->sc_flags & GEM_LINK) == 0) { 2152 return 1; 2153 } 2154 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_NONE; 2155 sc->sc_mii.mii_media_status = IFM_AVALID; 2156 #ifdef GEM_DEBUG 2157 aprint_debug_dev(sc->sc_dev, "link down\n"); 2158 #endif 2159 gem_statuschange(sc); 2160 2161 /* Start the 10 second timer */ 2162 callout_reset(&sc->sc_tick_ch, hz * 10, gem_tick, sc); 2163 } 2164 return 1; 2165 } 2166 2167 2168 2169 int 2170 gem_intr(void *v) 2171 { 2172 struct gem_softc *sc = v; 2173 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2174 bus_space_tag_t t = sc->sc_bustag; 2175 bus_space_handle_t h = sc->sc_h1; 2176 u_int32_t status; 2177 int r = 0; 2178 #ifdef GEM_DEBUG 2179 char bits[128]; 2180 #endif 2181 2182 /* XXX We should probably mask out interrupts until we're done */ 2183 2184 sc->sc_ev_intr.ev_count++; 2185 2186 status = bus_space_read_4(t, h, GEM_STATUS); 2187 #ifdef GEM_DEBUG 2188 snprintb(bits, sizeof(bits), GEM_INTR_BITS, status); 2189 #endif 2190 DPRINTF(sc, ("%s: gem_intr: cplt 0x%x status %s\n", 2191 device_xname(sc->sc_dev), (status >> 19), bits)); 2192 2193 2194 if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0) 2195 r |= gem_eint(sc, status); 2196 2197 /* We don't bother with GEM_INTR_TX_DONE */ 2198 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) { 2199 GEM_COUNTER_INCR(sc, sc_ev_txint); 2200 r |= gem_tint(sc); 2201 } 2202 2203 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) { 2204 GEM_COUNTER_INCR(sc, sc_ev_rxint); 2205 r |= gem_rint(sc); 2206 } 2207 2208 /* We should eventually do more than just print out error stats. */ 2209 if (status & GEM_INTR_TX_MAC) { 2210 int txstat = bus_space_read_4(t, h, GEM_MAC_TX_STATUS); 2211 if (txstat & ~GEM_MAC_TX_XMIT_DONE) 2212 printf("%s: MAC tx fault, status %x\n", 2213 device_xname(sc->sc_dev), txstat); 2214 if (txstat & (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG)) 2215 gem_init(ifp); 2216 } 2217 if (status & GEM_INTR_RX_MAC) { 2218 int rxstat = bus_space_read_4(t, h, GEM_MAC_RX_STATUS); 2219 /* 2220 * At least with GEM_SUN_GEM and some GEM_SUN_ERI 2221 * revisions GEM_MAC_RX_OVERFLOW happen often due to a 2222 * silicon bug so handle them silently. Moreover, it's 2223 * likely that the receiver has hung so we reset it. 2224 */ 2225 if (rxstat & GEM_MAC_RX_OVERFLOW) { 2226 ifp->if_ierrors++; 2227 gem_reset_rxdma(sc); 2228 } else if (rxstat & ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT)) 2229 printf("%s: MAC rx fault, status 0x%02x\n", 2230 device_xname(sc->sc_dev), rxstat); 2231 } 2232 if (status & GEM_INTR_PCS) { 2233 r |= gem_pint(sc); 2234 } 2235 2236 /* Do we need to do anything with these? 2237 if ((status & GEM_MAC_CONTROL_STATUS) != 0) { 2238 status2 = bus_read_4(sc->sc_res[0], GEM_MAC_CONTROL_STATUS); 2239 if ((status2 & GEM_MAC_PAUSED) != 0) 2240 aprintf_debug_dev(sc->sc_dev, "PAUSE received (%d slots)\n", 2241 GEM_MAC_PAUSE_TIME(status2)); 2242 if ((status2 & GEM_MAC_PAUSE) != 0) 2243 aprintf_debug_dev(sc->sc_dev, "transited to PAUSE state\n"); 2244 if ((status2 & GEM_MAC_RESUME) != 0) 2245 aprintf_debug_dev(sc->sc_dev, "transited to non-PAUSE state\n"); 2246 } 2247 if ((status & GEM_INTR_MIF) != 0) 2248 aprintf_debug_dev(sc->sc_dev, "MIF interrupt\n"); 2249 */ 2250 #if NRND > 0 2251 rnd_add_uint32(&sc->rnd_source, status); 2252 #endif 2253 return (r); 2254 } 2255 2256 2257 void 2258 gem_watchdog(struct ifnet *ifp) 2259 { 2260 struct gem_softc *sc = ifp->if_softc; 2261 2262 DPRINTF(sc, ("gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x " 2263 "GEM_MAC_RX_CONFIG %x\n", 2264 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_RX_CONFIG), 2265 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_MAC_RX_STATUS), 2266 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_MAC_RX_CONFIG))); 2267 2268 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 2269 ++ifp->if_oerrors; 2270 2271 /* Try to get more packets going. */ 2272 gem_start(ifp); 2273 } 2274 2275 /* 2276 * Initialize the MII Management Interface 2277 */ 2278 void 2279 gem_mifinit(struct gem_softc *sc) 2280 { 2281 bus_space_tag_t t = sc->sc_bustag; 2282 bus_space_handle_t mif = sc->sc_h1; 2283 2284 /* Configure the MIF in frame mode */ 2285 sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 2286 sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA; 2287 bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config); 2288 } 2289 2290 /* 2291 * MII interface 2292 * 2293 * The GEM MII interface supports at least three different operating modes: 2294 * 2295 * Bitbang mode is implemented using data, clock and output enable registers. 2296 * 2297 * Frame mode is implemented by loading a complete frame into the frame 2298 * register and polling the valid bit for completion. 2299 * 2300 * Polling mode uses the frame register but completion is indicated by 2301 * an interrupt. 2302 * 2303 */ 2304 static int 2305 gem_mii_readreg(device_t self, int phy, int reg) 2306 { 2307 struct gem_softc *sc = device_private(self); 2308 bus_space_tag_t t = sc->sc_bustag; 2309 bus_space_handle_t mif = sc->sc_h1; 2310 int n; 2311 u_int32_t v; 2312 2313 #ifdef GEM_DEBUG1 2314 if (sc->sc_debug) 2315 printf("gem_mii_readreg: PHY %d reg %d\n", phy, reg); 2316 #endif 2317 2318 /* Construct the frame command */ 2319 v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) | 2320 GEM_MIF_FRAME_READ; 2321 2322 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 2323 for (n = 0; n < 100; n++) { 2324 DELAY(1); 2325 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 2326 if (v & GEM_MIF_FRAME_TA0) 2327 return (v & GEM_MIF_FRAME_DATA); 2328 } 2329 2330 printf("%s: mii_read timeout\n", device_xname(sc->sc_dev)); 2331 return (0); 2332 } 2333 2334 static void 2335 gem_mii_writereg(device_t self, int phy, int reg, int val) 2336 { 2337 struct gem_softc *sc = device_private(self); 2338 bus_space_tag_t t = sc->sc_bustag; 2339 bus_space_handle_t mif = sc->sc_h1; 2340 int n; 2341 u_int32_t v; 2342 2343 #ifdef GEM_DEBUG1 2344 if (sc->sc_debug) 2345 printf("gem_mii_writereg: PHY %d reg %d val %x\n", 2346 phy, reg, val); 2347 #endif 2348 2349 /* Construct the frame command */ 2350 v = GEM_MIF_FRAME_WRITE | 2351 (phy << GEM_MIF_PHY_SHIFT) | 2352 (reg << GEM_MIF_REG_SHIFT) | 2353 (val & GEM_MIF_FRAME_DATA); 2354 2355 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 2356 for (n = 0; n < 100; n++) { 2357 DELAY(1); 2358 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 2359 if (v & GEM_MIF_FRAME_TA0) 2360 return; 2361 } 2362 2363 printf("%s: mii_write timeout\n", device_xname(sc->sc_dev)); 2364 } 2365 2366 static void 2367 gem_mii_statchg(device_t self) 2368 { 2369 struct gem_softc *sc = device_private(self); 2370 #ifdef GEM_DEBUG 2371 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 2372 #endif 2373 2374 #ifdef GEM_DEBUG 2375 if (sc->sc_debug) 2376 printf("gem_mii_statchg: status change: phy = %d\n", 2377 sc->sc_phys[instance]); 2378 #endif 2379 gem_statuschange(sc); 2380 } 2381 2382 /* 2383 * Common status change for gem_mii_statchg() and gem_pint() 2384 */ 2385 void 2386 gem_statuschange(struct gem_softc* sc) 2387 { 2388 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2389 bus_space_tag_t t = sc->sc_bustag; 2390 bus_space_handle_t mac = sc->sc_h1; 2391 int gigabit; 2392 u_int32_t rxcfg, txcfg, v; 2393 2394 if ((sc->sc_mii.mii_media_status & IFM_ACTIVE) != 0 && 2395 IFM_SUBTYPE(sc->sc_mii.mii_media_active) != IFM_NONE) 2396 sc->sc_flags |= GEM_LINK; 2397 else 2398 sc->sc_flags &= ~GEM_LINK; 2399 2400 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 2401 gigabit = 1; 2402 else 2403 gigabit = 0; 2404 2405 /* 2406 * The configuration done here corresponds to the steps F) and 2407 * G) and as far as enabling of RX and TX MAC goes also step H) 2408 * of the initialization sequence outlined in section 3.2.1 of 2409 * the GEM Gigabit Ethernet ASIC Specification. 2410 */ 2411 2412 rxcfg = bus_space_read_4(t, mac, GEM_MAC_RX_CONFIG); 2413 rxcfg &= ~(GEM_MAC_RX_CARR_EXTEND | GEM_MAC_RX_ENABLE); 2414 txcfg = GEM_MAC_TX_ENA_IPG0 | GEM_MAC_TX_NGU | GEM_MAC_TX_NGU_LIMIT; 2415 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 2416 txcfg |= GEM_MAC_TX_IGN_CARRIER | GEM_MAC_TX_IGN_COLLIS; 2417 else if (gigabit) { 2418 rxcfg |= GEM_MAC_RX_CARR_EXTEND; 2419 txcfg |= GEM_MAC_RX_CARR_EXTEND; 2420 } 2421 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0); 2422 bus_space_barrier(t, mac, GEM_MAC_TX_CONFIG, 4, 2423 BUS_SPACE_BARRIER_WRITE); 2424 if (!gem_bitwait(sc, mac, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)) 2425 aprint_normal_dev(sc->sc_dev, "cannot disable TX MAC\n"); 2426 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, txcfg); 2427 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, 0); 2428 bus_space_barrier(t, mac, GEM_MAC_RX_CONFIG, 4, 2429 BUS_SPACE_BARRIER_WRITE); 2430 if (!gem_bitwait(sc, mac, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)) 2431 aprint_normal_dev(sc->sc_dev, "cannot disable RX MAC\n"); 2432 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, rxcfg); 2433 2434 v = bus_space_read_4(t, mac, GEM_MAC_CONTROL_CONFIG) & 2435 ~(GEM_MAC_CC_RX_PAUSE | GEM_MAC_CC_TX_PAUSE); 2436 bus_space_write_4(t, mac, GEM_MAC_CONTROL_CONFIG, v); 2437 2438 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) == 0 && 2439 gigabit != 0) 2440 bus_space_write_4(t, mac, GEM_MAC_SLOT_TIME, 2441 GEM_MAC_SLOT_TIME_CARR_EXTEND); 2442 else 2443 bus_space_write_4(t, mac, GEM_MAC_SLOT_TIME, 2444 GEM_MAC_SLOT_TIME_NORMAL); 2445 2446 /* XIF Configuration */ 2447 if (sc->sc_flags & GEM_LINK) 2448 v = GEM_MAC_XIF_LINK_LED; 2449 else 2450 v = 0; 2451 v |= GEM_MAC_XIF_TX_MII_ENA; 2452 2453 /* If an external transceiver is connected, enable its MII drivers */ 2454 sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG); 2455 if ((sc->sc_flags &(GEM_SERDES | GEM_SERIAL)) == 0) { 2456 if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) { 2457 /* External MII needs echo disable if half duplex. */ 2458 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & 2459 IFM_FDX) != 0) 2460 /* turn on full duplex LED */ 2461 v |= GEM_MAC_XIF_FDPLX_LED; 2462 else 2463 /* half duplex -- disable echo */ 2464 v |= GEM_MAC_XIF_ECHO_DISABL; 2465 if (gigabit) 2466 v |= GEM_MAC_XIF_GMII_MODE; 2467 else 2468 v &= ~GEM_MAC_XIF_GMII_MODE; 2469 } else 2470 /* Internal MII needs buf enable */ 2471 v |= GEM_MAC_XIF_MII_BUF_ENA; 2472 } else { 2473 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 2474 v |= GEM_MAC_XIF_FDPLX_LED; 2475 v |= GEM_MAC_XIF_GMII_MODE; 2476 } 2477 bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v); 2478 2479 if ((ifp->if_flags & IFF_RUNNING) != 0 && 2480 (sc->sc_flags & GEM_LINK) != 0) { 2481 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 2482 txcfg | GEM_MAC_TX_ENABLE); 2483 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, 2484 rxcfg | GEM_MAC_RX_ENABLE); 2485 } 2486 } 2487 2488 int 2489 gem_ser_mediachange(struct ifnet *ifp) 2490 { 2491 struct gem_softc *sc = ifp->if_softc; 2492 u_int s, t; 2493 2494 if (IFM_TYPE(sc->sc_mii.mii_media.ifm_media) != IFM_ETHER) 2495 return EINVAL; 2496 2497 s = IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media); 2498 if (s == IFM_AUTO) { 2499 if (sc->sc_mii_media != s) { 2500 #ifdef GEM_DEBUG 2501 aprint_debug_dev(sc->sc_dev, "setting media to auto\n"); 2502 #endif 2503 sc->sc_mii_media = s; 2504 if (ifp->if_flags & IFF_UP) { 2505 gem_pcs_stop(sc, 0); 2506 gem_pcs_start(sc); 2507 } 2508 } 2509 return 0; 2510 } 2511 if (s == IFM_1000_SX) { 2512 t = IFM_OPTIONS(sc->sc_mii.mii_media.ifm_media); 2513 if (t == IFM_FDX || t == IFM_HDX) { 2514 if (sc->sc_mii_media != t) { 2515 sc->sc_mii_media = t; 2516 #ifdef GEM_DEBUG 2517 aprint_debug_dev(sc->sc_dev, 2518 "setting media to 1000baseSX-%s\n", 2519 t == IFM_FDX ? "FDX" : "HDX"); 2520 #endif 2521 if (ifp->if_flags & IFF_UP) { 2522 gem_pcs_stop(sc, 0); 2523 gem_pcs_start(sc); 2524 } 2525 } 2526 return 0; 2527 } 2528 } 2529 return EINVAL; 2530 } 2531 2532 void 2533 gem_ser_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2534 { 2535 struct gem_softc *sc = ifp->if_softc; 2536 2537 if ((ifp->if_flags & IFF_UP) == 0) 2538 return; 2539 ifmr->ifm_active = sc->sc_mii.mii_media_active; 2540 ifmr->ifm_status = sc->sc_mii.mii_media_status; 2541 } 2542 2543 static int 2544 gem_ifflags_cb(struct ethercom *ec) 2545 { 2546 struct ifnet *ifp = &ec->ec_if; 2547 struct gem_softc *sc = ifp->if_softc; 2548 int change = ifp->if_flags ^ sc->sc_if_flags; 2549 2550 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 2551 return ENETRESET; 2552 else if ((change & IFF_PROMISC) != 0) 2553 gem_setladrf(sc); 2554 return 0; 2555 } 2556 2557 /* 2558 * Process an ioctl request. 2559 */ 2560 int 2561 gem_ioctl(struct ifnet *ifp, unsigned long cmd, void *data) 2562 { 2563 struct gem_softc *sc = ifp->if_softc; 2564 int s, error = 0; 2565 2566 s = splnet(); 2567 2568 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2569 error = 0; 2570 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 2571 ; 2572 else if (ifp->if_flags & IFF_RUNNING) { 2573 /* 2574 * Multicast list has changed; set the hardware filter 2575 * accordingly. 2576 */ 2577 gem_setladrf(sc); 2578 } 2579 } 2580 2581 /* Try to get things going again */ 2582 if (ifp->if_flags & IFF_UP) 2583 gem_start(ifp); 2584 splx(s); 2585 return (error); 2586 } 2587 2588 static void 2589 gem_inten(struct gem_softc *sc) 2590 { 2591 bus_space_tag_t t = sc->sc_bustag; 2592 bus_space_handle_t h = sc->sc_h1; 2593 uint32_t v; 2594 2595 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 2596 v = GEM_INTR_PCS; 2597 else 2598 v = GEM_INTR_MIF; 2599 bus_space_write_4(t, h, GEM_INTMASK, 2600 ~(GEM_INTR_TX_INTME | 2601 GEM_INTR_TX_EMPTY | 2602 GEM_INTR_TX_MAC | 2603 GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF| 2604 GEM_INTR_RX_TAG_ERR | GEM_INTR_MAC_CONTROL| 2605 GEM_INTR_BERR | v)); 2606 } 2607 2608 bool 2609 gem_resume(device_t self, pmf_qual_t qual) 2610 { 2611 struct gem_softc *sc = device_private(self); 2612 2613 gem_inten(sc); 2614 2615 return true; 2616 } 2617 2618 bool 2619 gem_suspend(device_t self, pmf_qual_t qual) 2620 { 2621 struct gem_softc *sc = device_private(self); 2622 bus_space_tag_t t = sc->sc_bustag; 2623 bus_space_handle_t h = sc->sc_h1; 2624 2625 bus_space_write_4(t, h, GEM_INTMASK, ~(uint32_t)0); 2626 2627 return true; 2628 } 2629 2630 bool 2631 gem_shutdown(device_t self, int howto) 2632 { 2633 struct gem_softc *sc = device_private(self); 2634 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2635 2636 gem_stop(ifp, 1); 2637 2638 return true; 2639 } 2640 2641 /* 2642 * Set up the logical address filter. 2643 */ 2644 void 2645 gem_setladrf(struct gem_softc *sc) 2646 { 2647 struct ethercom *ec = &sc->sc_ethercom; 2648 struct ifnet *ifp = &ec->ec_if; 2649 struct ether_multi *enm; 2650 struct ether_multistep step; 2651 bus_space_tag_t t = sc->sc_bustag; 2652 bus_space_handle_t h = sc->sc_h1; 2653 u_int32_t crc; 2654 u_int32_t hash[16]; 2655 u_int32_t v; 2656 int i; 2657 2658 /* Get current RX configuration */ 2659 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 2660 2661 /* 2662 * Turn off promiscuous mode, promiscuous group mode (all multicast), 2663 * and hash filter. Depending on the case, the right bit will be 2664 * enabled. 2665 */ 2666 v &= ~(GEM_MAC_RX_PROMISCUOUS|GEM_MAC_RX_HASH_FILTER| 2667 GEM_MAC_RX_PROMISC_GRP); 2668 2669 if ((ifp->if_flags & IFF_PROMISC) != 0) { 2670 /* Turn on promiscuous mode */ 2671 v |= GEM_MAC_RX_PROMISCUOUS; 2672 ifp->if_flags |= IFF_ALLMULTI; 2673 goto chipit; 2674 } 2675 2676 /* 2677 * Set up multicast address filter by passing all multicast addresses 2678 * through a crc generator, and then using the high order 8 bits as an 2679 * index into the 256 bit logical address filter. The high order 4 2680 * bits selects the word, while the other 4 bits select the bit within 2681 * the word (where bit 0 is the MSB). 2682 */ 2683 2684 /* Clear hash table */ 2685 memset(hash, 0, sizeof(hash)); 2686 2687 ETHER_FIRST_MULTI(step, ec, enm); 2688 while (enm != NULL) { 2689 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2690 /* 2691 * We must listen to a range of multicast addresses. 2692 * For now, just accept all multicasts, rather than 2693 * trying to set only those filter bits needed to match 2694 * the range. (At this time, the only use of address 2695 * ranges is for IP multicast routing, for which the 2696 * range is big enough to require all bits set.) 2697 * XXX should use the address filters for this 2698 */ 2699 ifp->if_flags |= IFF_ALLMULTI; 2700 v |= GEM_MAC_RX_PROMISC_GRP; 2701 goto chipit; 2702 } 2703 2704 /* Get the LE CRC32 of the address */ 2705 crc = ether_crc32_le(enm->enm_addrlo, sizeof(enm->enm_addrlo)); 2706 2707 /* Just want the 8 most significant bits. */ 2708 crc >>= 24; 2709 2710 /* Set the corresponding bit in the filter. */ 2711 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 2712 2713 ETHER_NEXT_MULTI(step, enm); 2714 } 2715 2716 v |= GEM_MAC_RX_HASH_FILTER; 2717 ifp->if_flags &= ~IFF_ALLMULTI; 2718 2719 /* Now load the hash table into the chip (if we are using it) */ 2720 for (i = 0; i < 16; i++) { 2721 bus_space_write_4(t, h, 2722 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1-GEM_MAC_HASH0), 2723 hash[i]); 2724 } 2725 2726 chipit: 2727 sc->sc_if_flags = ifp->if_flags; 2728 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 2729 } 2730
Indexes created Mon Sep 22 21:09:42 GMT 2025