gem.c revision 1.94
1 /* $NetBSD: gem.c,v 1.94 2010/04/05 07:19:34 joerg Exp $ */ 2 3 /* 4 * 5 * Copyright (C) 2001 Eduardo Horvath. 6 * Copyright (c) 2001-2003 Thomas Moestl 7 * All rights reserved. 8 * 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 */ 32 33 /* 34 * Driver for Apple GMAC, Sun ERI and Sun GEM Ethernet controllers 35 * See `GEM Gigabit Ethernet ASIC Specification' 36 * http://www.sun.com/processors/manuals/ge.pdf 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: gem.c,v 1.94 2010/04/05 07:19:34 joerg Exp $"); 41 42 #include "opt_inet.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/callout.h> 47 #include <sys/mbuf.h> 48 #include <sys/syslog.h> 49 #include <sys/malloc.h> 50 #include <sys/kernel.h> 51 #include <sys/socket.h> 52 #include <sys/ioctl.h> 53 #include <sys/errno.h> 54 #include <sys/device.h> 55 56 #include <machine/endian.h> 57 58 #include <uvm/uvm_extern.h> 59 60 #include <net/if.h> 61 #include <net/if_dl.h> 62 #include <net/if_media.h> 63 #include <net/if_ether.h> 64 65 #ifdef INET 66 #include <netinet/in.h> 67 #include <netinet/in_systm.h> 68 #include <netinet/in_var.h> 69 #include <netinet/ip.h> 70 #include <netinet/tcp.h> 71 #include <netinet/udp.h> 72 #endif 73 74 #include <net/bpf.h> 75 76 #include <sys/bus.h> 77 #include <sys/intr.h> 78 79 #include <dev/mii/mii.h> 80 #include <dev/mii/miivar.h> 81 #include <dev/mii/mii_bitbang.h> 82 83 #include <dev/ic/gemreg.h> 84 #include <dev/ic/gemvar.h> 85 86 #define TRIES 10000 87 88 static void gem_inten(struct gem_softc *); 89 static void gem_start(struct ifnet *); 90 static void gem_stop(struct ifnet *, int); 91 int gem_ioctl(struct ifnet *, u_long, void *); 92 void gem_tick(void *); 93 void gem_watchdog(struct ifnet *); 94 void gem_pcs_start(struct gem_softc *sc); 95 void gem_pcs_stop(struct gem_softc *sc, int); 96 int gem_init(struct ifnet *); 97 void gem_init_regs(struct gem_softc *sc); 98 static int gem_ringsize(int sz); 99 static int gem_meminit(struct gem_softc *); 100 void gem_mifinit(struct gem_softc *); 101 static int gem_bitwait(struct gem_softc *sc, bus_space_handle_t, int, 102 u_int32_t, u_int32_t); 103 void gem_reset(struct gem_softc *); 104 int gem_reset_rx(struct gem_softc *sc); 105 static void gem_reset_rxdma(struct gem_softc *sc); 106 static void gem_rx_common(struct gem_softc *sc); 107 int gem_reset_tx(struct gem_softc *sc); 108 int gem_disable_rx(struct gem_softc *sc); 109 int gem_disable_tx(struct gem_softc *sc); 110 static void gem_rxdrain(struct gem_softc *sc); 111 int gem_add_rxbuf(struct gem_softc *sc, int idx); 112 void gem_setladrf(struct gem_softc *); 113 114 /* MII methods & callbacks */ 115 static int gem_mii_readreg(device_t, int, int); 116 static void gem_mii_writereg(device_t, int, int, int); 117 static void gem_mii_statchg(device_t); 118 119 static int gem_ifflags_cb(struct ethercom *); 120 121 void gem_statuschange(struct gem_softc *); 122 123 int gem_ser_mediachange(struct ifnet *); 124 void gem_ser_mediastatus(struct ifnet *, struct ifmediareq *); 125 126 static void gem_partial_detach(struct gem_softc *, enum gem_attach_stage); 127 128 struct mbuf *gem_get(struct gem_softc *, int, int); 129 int gem_put(struct gem_softc *, int, struct mbuf *); 130 void gem_read(struct gem_softc *, int, int); 131 int gem_pint(struct gem_softc *); 132 int gem_eint(struct gem_softc *, u_int); 133 int gem_rint(struct gem_softc *); 134 int gem_tint(struct gem_softc *); 135 void gem_power(int, void *); 136 137 #ifdef GEM_DEBUG 138 static void gem_txsoft_print(const struct gem_softc *, int, int); 139 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 140 printf x 141 #else 142 #define DPRINTF(sc, x) /* nothing */ 143 #endif 144 145 #define ETHER_MIN_TX (ETHERMIN + sizeof(struct ether_header)) 146 147 int 148 gem_detach(struct gem_softc *sc, int flags) 149 { 150 int i; 151 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 152 bus_space_tag_t t = sc->sc_bustag; 153 bus_space_handle_t h = sc->sc_h1; 154 155 /* 156 * Free any resources we've allocated during the attach. 157 * Do this in reverse order and fall through. 158 */ 159 switch (sc->sc_att_stage) { 160 case GEM_ATT_BACKEND_2: 161 case GEM_ATT_BACKEND_1: 162 case GEM_ATT_FINISHED: 163 bus_space_write_4(t, h, GEM_INTMASK, ~(uint32_t)0); 164 gem_stop(&sc->sc_ethercom.ec_if, 1); 165 166 #ifdef GEM_COUNTERS 167 for (i = __arraycount(sc->sc_ev_rxhist); --i >= 0; ) 168 evcnt_detach(&sc->sc_ev_rxhist[i]); 169 evcnt_detach(&sc->sc_ev_rxnobuf); 170 evcnt_detach(&sc->sc_ev_rxfull); 171 evcnt_detach(&sc->sc_ev_rxint); 172 evcnt_detach(&sc->sc_ev_txint); 173 #endif 174 evcnt_detach(&sc->sc_ev_intr); 175 176 #if NRND > 0 177 rnd_detach_source(&sc->rnd_source); 178 #endif 179 ether_ifdetach(ifp); 180 if_detach(ifp); 181 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 182 183 callout_destroy(&sc->sc_tick_ch); 184 185 /*FALLTHROUGH*/ 186 case GEM_ATT_MII: 187 sc->sc_att_stage = GEM_ATT_MII; 188 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 189 /*FALLTHROUGH*/ 190 case GEM_ATT_7: 191 for (i = 0; i < GEM_NRXDESC; i++) { 192 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 193 bus_dmamap_destroy(sc->sc_dmatag, 194 sc->sc_rxsoft[i].rxs_dmamap); 195 } 196 /*FALLTHROUGH*/ 197 case GEM_ATT_6: 198 for (i = 0; i < GEM_TXQUEUELEN; i++) { 199 if (sc->sc_txsoft[i].txs_dmamap != NULL) 200 bus_dmamap_destroy(sc->sc_dmatag, 201 sc->sc_txsoft[i].txs_dmamap); 202 } 203 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 204 /*FALLTHROUGH*/ 205 case GEM_ATT_5: 206 bus_dmamap_unload(sc->sc_dmatag, sc->sc_nulldmamap); 207 /*FALLTHROUGH*/ 208 case GEM_ATT_4: 209 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_nulldmamap); 210 /*FALLTHROUGH*/ 211 case GEM_ATT_3: 212 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 213 /*FALLTHROUGH*/ 214 case GEM_ATT_2: 215 bus_dmamem_unmap(sc->sc_dmatag, sc->sc_control_data, 216 sizeof(struct gem_control_data)); 217 /*FALLTHROUGH*/ 218 case GEM_ATT_1: 219 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 220 /*FALLTHROUGH*/ 221 case GEM_ATT_0: 222 sc->sc_att_stage = GEM_ATT_0; 223 /*FALLTHROUGH*/ 224 case GEM_ATT_BACKEND_0: 225 break; 226 } 227 return 0; 228 } 229 230 static void 231 gem_partial_detach(struct gem_softc *sc, enum gem_attach_stage stage) 232 { 233 cfattach_t ca = device_cfattach(sc->sc_dev); 234 235 sc->sc_att_stage = stage; 236 (*ca->ca_detach)(sc->sc_dev, 0); 237 } 238 239 /* 240 * gem_attach: 241 * 242 * Attach a Gem interface to the system. 243 */ 244 void 245 gem_attach(struct gem_softc *sc, const uint8_t *enaddr) 246 { 247 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 248 struct mii_data *mii = &sc->sc_mii; 249 bus_space_tag_t t = sc->sc_bustag; 250 bus_space_handle_t h = sc->sc_h1; 251 struct ifmedia_entry *ifm; 252 int i, error, phyaddr; 253 u_int32_t v; 254 char *nullbuf; 255 256 /* Make sure the chip is stopped. */ 257 ifp->if_softc = sc; 258 gem_reset(sc); 259 260 /* 261 * Allocate the control data structures, and create and load the 262 * DMA map for it. gem_control_data is 9216 bytes, we have space for 263 * the padding buffer in the bus_dmamem_alloc()'d memory. 264 */ 265 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 266 sizeof(struct gem_control_data) + ETHER_MIN_TX, PAGE_SIZE, 267 0, &sc->sc_cdseg, 1, &sc->sc_cdnseg, 0)) != 0) { 268 aprint_error_dev(sc->sc_dev, 269 "unable to allocate control data, error = %d\n", 270 error); 271 gem_partial_detach(sc, GEM_ATT_0); 272 return; 273 } 274 275 /* XXX should map this in with correct endianness */ 276 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg, 277 sizeof(struct gem_control_data), (void **)&sc->sc_control_data, 278 BUS_DMA_COHERENT)) != 0) { 279 aprint_error_dev(sc->sc_dev, 280 "unable to map control data, error = %d\n", error); 281 gem_partial_detach(sc, GEM_ATT_1); 282 return; 283 } 284 285 nullbuf = 286 (char *)sc->sc_control_data + sizeof(struct gem_control_data); 287 288 if ((error = bus_dmamap_create(sc->sc_dmatag, 289 sizeof(struct gem_control_data), 1, 290 sizeof(struct gem_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 291 aprint_error_dev(sc->sc_dev, 292 "unable to create control data DMA map, error = %d\n", 293 error); 294 gem_partial_detach(sc, GEM_ATT_2); 295 return; 296 } 297 298 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 299 sc->sc_control_data, sizeof(struct gem_control_data), NULL, 300 0)) != 0) { 301 aprint_error_dev(sc->sc_dev, 302 "unable to load control data DMA map, error = %d\n", 303 error); 304 gem_partial_detach(sc, GEM_ATT_3); 305 return; 306 } 307 308 memset(nullbuf, 0, ETHER_MIN_TX); 309 if ((error = bus_dmamap_create(sc->sc_dmatag, 310 ETHER_MIN_TX, 1, ETHER_MIN_TX, 0, 0, &sc->sc_nulldmamap)) != 0) { 311 aprint_error_dev(sc->sc_dev, 312 "unable to create padding DMA map, error = %d\n", error); 313 gem_partial_detach(sc, GEM_ATT_4); 314 return; 315 } 316 317 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_nulldmamap, 318 nullbuf, ETHER_MIN_TX, NULL, 0)) != 0) { 319 aprint_error_dev(sc->sc_dev, 320 "unable to load padding DMA map, error = %d\n", error); 321 gem_partial_detach(sc, GEM_ATT_5); 322 return; 323 } 324 325 bus_dmamap_sync(sc->sc_dmatag, sc->sc_nulldmamap, 0, ETHER_MIN_TX, 326 BUS_DMASYNC_PREWRITE); 327 328 /* 329 * Initialize the transmit job descriptors. 330 */ 331 SIMPLEQ_INIT(&sc->sc_txfreeq); 332 SIMPLEQ_INIT(&sc->sc_txdirtyq); 333 334 /* 335 * Create the transmit buffer DMA maps. 336 */ 337 for (i = 0; i < GEM_TXQUEUELEN; i++) { 338 struct gem_txsoft *txs; 339 340 txs = &sc->sc_txsoft[i]; 341 txs->txs_mbuf = NULL; 342 if ((error = bus_dmamap_create(sc->sc_dmatag, 343 ETHER_MAX_LEN_JUMBO, GEM_NTXSEGS, 344 ETHER_MAX_LEN_JUMBO, 0, 0, 345 &txs->txs_dmamap)) != 0) { 346 aprint_error_dev(sc->sc_dev, 347 "unable to create tx DMA map %d, error = %d\n", 348 i, error); 349 gem_partial_detach(sc, GEM_ATT_6); 350 return; 351 } 352 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 353 } 354 355 /* 356 * Create the receive buffer DMA maps. 357 */ 358 for (i = 0; i < GEM_NRXDESC; i++) { 359 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, 360 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 361 aprint_error_dev(sc->sc_dev, 362 "unable to create rx DMA map %d, error = %d\n", 363 i, error); 364 gem_partial_detach(sc, GEM_ATT_7); 365 return; 366 } 367 sc->sc_rxsoft[i].rxs_mbuf = NULL; 368 } 369 370 /* Initialize ifmedia structures and MII info */ 371 mii->mii_ifp = ifp; 372 mii->mii_readreg = gem_mii_readreg; 373 mii->mii_writereg = gem_mii_writereg; 374 mii->mii_statchg = gem_mii_statchg; 375 376 sc->sc_ethercom.ec_mii = mii; 377 378 /* 379 * Initialization based on `GEM Gigabit Ethernet ASIC Specification' 380 * Section 3.2.1 `Initialization Sequence'. 381 * However, we can't assume SERDES or Serialink if neither 382 * GEM_MIF_CONFIG_MDI0 nor GEM_MIF_CONFIG_MDI1 are set 383 * being set, as both are set on Sun X1141A (with SERDES). So, 384 * we rely on our bus attachment setting GEM_SERDES or GEM_SERIAL. 385 * Also, for variants that report 2 PHY's, we prefer the external 386 * PHY over the internal PHY, so we look for that first. 387 */ 388 gem_mifinit(sc); 389 390 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) { 391 ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange, 392 ether_mediastatus); 393 /* Look for external PHY */ 394 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) { 395 sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL; 396 bus_space_write_4(t, h, GEM_MIF_CONFIG, 397 sc->sc_mif_config); 398 switch (sc->sc_variant) { 399 case GEM_SUN_ERI: 400 phyaddr = GEM_PHYAD_EXTERNAL; 401 break; 402 default: 403 phyaddr = MII_PHY_ANY; 404 break; 405 } 406 mii_attach(sc->sc_dev, mii, 0xffffffff, phyaddr, 407 MII_OFFSET_ANY, MIIF_FORCEANEG); 408 } 409 #ifdef GEM_DEBUG 410 else 411 aprint_debug_dev(sc->sc_dev, "using external PHY\n"); 412 #endif 413 /* Look for internal PHY if no external PHY was found */ 414 if (LIST_EMPTY(&mii->mii_phys) && 415 sc->sc_mif_config & GEM_MIF_CONFIG_MDI0) { 416 sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL; 417 bus_space_write_4(t, h, GEM_MIF_CONFIG, 418 sc->sc_mif_config); 419 switch (sc->sc_variant) { 420 case GEM_SUN_ERI: 421 case GEM_APPLE_K2_GMAC: 422 phyaddr = GEM_PHYAD_INTERNAL; 423 break; 424 case GEM_APPLE_GMAC: 425 phyaddr = GEM_PHYAD_EXTERNAL; 426 break; 427 default: 428 phyaddr = MII_PHY_ANY; 429 break; 430 } 431 mii_attach(sc->sc_dev, mii, 0xffffffff, phyaddr, 432 MII_OFFSET_ANY, MIIF_FORCEANEG); 433 #ifdef GEM_DEBUG 434 if (!LIST_EMPTY(&mii->mii_phys)) 435 aprint_debug_dev(sc->sc_dev, 436 "using internal PHY\n"); 437 #endif 438 } 439 if (LIST_EMPTY(&mii->mii_phys)) { 440 /* No PHY attached */ 441 aprint_error_dev(sc->sc_dev, 442 "PHY probe failed\n"); 443 gem_partial_detach(sc, GEM_ATT_MII); 444 return; 445 } else { 446 struct mii_softc *child; 447 448 /* 449 * Walk along the list of attached MII devices and 450 * establish an `MII instance' to `PHY number' 451 * mapping. 452 */ 453 LIST_FOREACH(child, &mii->mii_phys, mii_list) { 454 /* 455 * Note: we support just one PHY: the internal 456 * or external MII is already selected for us 457 * by the GEM_MIF_CONFIG register. 458 */ 459 if (child->mii_phy > 1 || child->mii_inst > 0) { 460 aprint_error_dev(sc->sc_dev, 461 "cannot accommodate MII device" 462 " %s at PHY %d, instance %d\n", 463 device_xname(child->mii_dev), 464 child->mii_phy, child->mii_inst); 465 continue; 466 } 467 sc->sc_phys[child->mii_inst] = child->mii_phy; 468 } 469 470 if (sc->sc_variant != GEM_SUN_ERI) 471 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 472 GEM_MII_DATAPATH_MII); 473 474 /* 475 * XXX - we can really do the following ONLY if the 476 * PHY indeed has the auto negotiation capability!! 477 */ 478 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 479 } 480 } else { 481 ifmedia_init(&mii->mii_media, IFM_IMASK, gem_ser_mediachange, 482 gem_ser_mediastatus); 483 /* SERDES or Serialink */ 484 if (sc->sc_flags & GEM_SERDES) { 485 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 486 GEM_MII_DATAPATH_SERDES); 487 } else { 488 sc->sc_flags |= GEM_SERIAL; 489 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 490 GEM_MII_DATAPATH_SERIAL); 491 } 492 493 aprint_normal_dev(sc->sc_dev, "using external PCS %s: ", 494 sc->sc_flags & GEM_SERDES ? "SERDES" : "Serialink"); 495 496 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO, 0, NULL); 497 /* Check for FDX and HDX capabilities */ 498 sc->sc_mii_anar = bus_space_read_4(t, h, GEM_MII_ANAR); 499 if (sc->sc_mii_anar & GEM_MII_ANEG_FUL_DUPLX) { 500 ifmedia_add(&sc->sc_mii.mii_media, 501 IFM_ETHER|IFM_1000_SX|IFM_MANUAL|IFM_FDX, 0, NULL); 502 aprint_normal("1000baseSX-FDX, "); 503 } 504 if (sc->sc_mii_anar & GEM_MII_ANEG_HLF_DUPLX) { 505 ifmedia_add(&sc->sc_mii.mii_media, 506 IFM_ETHER|IFM_1000_SX|IFM_MANUAL|IFM_HDX, 0, NULL); 507 aprint_normal("1000baseSX-HDX, "); 508 } 509 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 510 sc->sc_mii_media = IFM_AUTO; 511 aprint_normal("auto\n"); 512 513 gem_pcs_stop(sc, 1); 514 } 515 516 /* 517 * From this point forward, the attachment cannot fail. A failure 518 * before this point releases all resources that may have been 519 * allocated. 520 */ 521 522 /* Announce ourselves. */ 523 aprint_normal_dev(sc->sc_dev, "Ethernet address %s", 524 ether_sprintf(enaddr)); 525 526 /* Get RX FIFO size */ 527 sc->sc_rxfifosize = 64 * 528 bus_space_read_4(t, h, GEM_RX_FIFO_SIZE); 529 aprint_normal(", %uKB RX fifo", sc->sc_rxfifosize / 1024); 530 531 /* Get TX FIFO size */ 532 v = bus_space_read_4(t, h, GEM_TX_FIFO_SIZE); 533 aprint_normal(", %uKB TX fifo\n", v / 16); 534 535 /* Initialize ifnet structure. */ 536 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 537 ifp->if_softc = sc; 538 ifp->if_flags = 539 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 540 sc->sc_if_flags = ifp->if_flags; 541 #if 0 542 /* 543 * The GEM hardware supports basic TCP checksum offloading only. 544 * Several (all?) revisions (Sun rev. 01 and Apple rev. 00 and 80) 545 * have bugs in the receive checksum, so don't enable it for now. 546 */ 547 if ((GEM_IS_SUN(sc) && sc->sc_chiprev != 1) || 548 (GEM_IS_APPLE(sc) && 549 (sc->sc_chiprev != 0 && sc->sc_chiprev != 0x80))) 550 ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Rx; 551 #endif 552 ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Tx; 553 ifp->if_start = gem_start; 554 ifp->if_ioctl = gem_ioctl; 555 ifp->if_watchdog = gem_watchdog; 556 ifp->if_stop = gem_stop; 557 ifp->if_init = gem_init; 558 IFQ_SET_READY(&ifp->if_snd); 559 560 /* 561 * If we support GigE media, we support jumbo frames too. 562 * Unless we are Apple. 563 */ 564 TAILQ_FOREACH(ifm, &sc->sc_mii.mii_media.ifm_list, ifm_list) { 565 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_T || 566 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_SX || 567 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_LX || 568 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_CX) { 569 if (!GEM_IS_APPLE(sc)) 570 sc->sc_ethercom.ec_capabilities 571 |= ETHERCAP_JUMBO_MTU; 572 sc->sc_flags |= GEM_GIGABIT; 573 break; 574 } 575 } 576 577 /* claim 802.1q capability */ 578 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 579 580 /* Attach the interface. */ 581 if_attach(ifp); 582 ether_ifattach(ifp, enaddr); 583 ether_set_ifflags_cb(&sc->sc_ethercom, gem_ifflags_cb); 584 585 #if NRND > 0 586 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 587 RND_TYPE_NET, 0); 588 #endif 589 590 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, 591 NULL, device_xname(sc->sc_dev), "interrupts"); 592 #ifdef GEM_COUNTERS 593 evcnt_attach_dynamic(&sc->sc_ev_txint, EVCNT_TYPE_INTR, 594 &sc->sc_ev_intr, device_xname(sc->sc_dev), "tx interrupts"); 595 evcnt_attach_dynamic(&sc->sc_ev_rxint, EVCNT_TYPE_INTR, 596 &sc->sc_ev_intr, device_xname(sc->sc_dev), "rx interrupts"); 597 evcnt_attach_dynamic(&sc->sc_ev_rxfull, EVCNT_TYPE_INTR, 598 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx ring full"); 599 evcnt_attach_dynamic(&sc->sc_ev_rxnobuf, EVCNT_TYPE_INTR, 600 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx malloc failure"); 601 evcnt_attach_dynamic(&sc->sc_ev_rxhist[0], EVCNT_TYPE_INTR, 602 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 0desc"); 603 evcnt_attach_dynamic(&sc->sc_ev_rxhist[1], EVCNT_TYPE_INTR, 604 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 1desc"); 605 evcnt_attach_dynamic(&sc->sc_ev_rxhist[2], EVCNT_TYPE_INTR, 606 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 2desc"); 607 evcnt_attach_dynamic(&sc->sc_ev_rxhist[3], EVCNT_TYPE_INTR, 608 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 3desc"); 609 evcnt_attach_dynamic(&sc->sc_ev_rxhist[4], EVCNT_TYPE_INTR, 610 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >3desc"); 611 evcnt_attach_dynamic(&sc->sc_ev_rxhist[5], EVCNT_TYPE_INTR, 612 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >7desc"); 613 evcnt_attach_dynamic(&sc->sc_ev_rxhist[6], EVCNT_TYPE_INTR, 614 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >15desc"); 615 evcnt_attach_dynamic(&sc->sc_ev_rxhist[7], EVCNT_TYPE_INTR, 616 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >31desc"); 617 evcnt_attach_dynamic(&sc->sc_ev_rxhist[8], EVCNT_TYPE_INTR, 618 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >63desc"); 619 #endif 620 621 callout_init(&sc->sc_tick_ch, 0); 622 623 sc->sc_att_stage = GEM_ATT_FINISHED; 624 625 return; 626 } 627 628 void 629 gem_tick(void *arg) 630 { 631 struct gem_softc *sc = arg; 632 int s; 633 634 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) { 635 /* 636 * We have to reset everything if we failed to get a 637 * PCS interrupt. Restarting the callout is handled 638 * in gem_pcs_start(). 639 */ 640 gem_init(&sc->sc_ethercom.ec_if); 641 } else { 642 s = splnet(); 643 mii_tick(&sc->sc_mii); 644 splx(s); 645 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 646 } 647 } 648 649 static int 650 gem_bitwait(struct gem_softc *sc, bus_space_handle_t h, int r, u_int32_t clr, u_int32_t set) 651 { 652 int i; 653 u_int32_t reg; 654 655 for (i = TRIES; i--; DELAY(100)) { 656 reg = bus_space_read_4(sc->sc_bustag, h, r); 657 if ((reg & clr) == 0 && (reg & set) == set) 658 return (1); 659 } 660 return (0); 661 } 662 663 void 664 gem_reset(struct gem_softc *sc) 665 { 666 bus_space_tag_t t = sc->sc_bustag; 667 bus_space_handle_t h = sc->sc_h2; 668 int s; 669 670 s = splnet(); 671 DPRINTF(sc, ("%s: gem_reset\n", device_xname(sc->sc_dev))); 672 gem_reset_rx(sc); 673 gem_reset_tx(sc); 674 675 /* Do a full reset */ 676 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX|GEM_RESET_TX); 677 if (!gem_bitwait(sc, h, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0)) 678 aprint_error_dev(sc->sc_dev, "cannot reset device\n"); 679 splx(s); 680 } 681 682 683 /* 684 * gem_rxdrain: 685 * 686 * Drain the receive queue. 687 */ 688 static void 689 gem_rxdrain(struct gem_softc *sc) 690 { 691 struct gem_rxsoft *rxs; 692 int i; 693 694 for (i = 0; i < GEM_NRXDESC; i++) { 695 rxs = &sc->sc_rxsoft[i]; 696 if (rxs->rxs_mbuf != NULL) { 697 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 698 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 699 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 700 m_freem(rxs->rxs_mbuf); 701 rxs->rxs_mbuf = NULL; 702 } 703 } 704 } 705 706 /* 707 * Reset the whole thing. 708 */ 709 static void 710 gem_stop(struct ifnet *ifp, int disable) 711 { 712 struct gem_softc *sc = ifp->if_softc; 713 struct gem_txsoft *txs; 714 715 DPRINTF(sc, ("%s: gem_stop\n", device_xname(sc->sc_dev))); 716 717 callout_stop(&sc->sc_tick_ch); 718 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 719 gem_pcs_stop(sc, disable); 720 else 721 mii_down(&sc->sc_mii); 722 723 /* XXX - Should we reset these instead? */ 724 gem_disable_tx(sc); 725 gem_disable_rx(sc); 726 727 /* 728 * Release any queued transmit buffers. 729 */ 730 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 731 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 732 if (txs->txs_mbuf != NULL) { 733 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 0, 734 txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 735 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 736 m_freem(txs->txs_mbuf); 737 txs->txs_mbuf = NULL; 738 } 739 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 740 } 741 742 /* 743 * Mark the interface down and cancel the watchdog timer. 744 */ 745 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 746 sc->sc_if_flags = ifp->if_flags; 747 ifp->if_timer = 0; 748 749 if (disable) 750 gem_rxdrain(sc); 751 } 752 753 754 /* 755 * Reset the receiver 756 */ 757 int 758 gem_reset_rx(struct gem_softc *sc) 759 { 760 bus_space_tag_t t = sc->sc_bustag; 761 bus_space_handle_t h = sc->sc_h1, h2 = sc->sc_h2; 762 763 /* 764 * Resetting while DMA is in progress can cause a bus hang, so we 765 * disable DMA first. 766 */ 767 gem_disable_rx(sc); 768 bus_space_write_4(t, h, GEM_RX_CONFIG, 0); 769 bus_space_barrier(t, h, GEM_RX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 770 /* Wait till it finishes */ 771 if (!gem_bitwait(sc, h, GEM_RX_CONFIG, 1, 0)) 772 aprint_error_dev(sc->sc_dev, "cannot disable read dma\n"); 773 774 /* Finally, reset the ERX */ 775 bus_space_write_4(t, h2, GEM_RESET, GEM_RESET_RX); 776 bus_space_barrier(t, h, GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE); 777 /* Wait till it finishes */ 778 if (!gem_bitwait(sc, h2, GEM_RESET, GEM_RESET_RX, 0)) { 779 aprint_error_dev(sc->sc_dev, "cannot reset receiver\n"); 780 return (1); 781 } 782 return (0); 783 } 784 785 786 /* 787 * Reset the receiver DMA engine. 788 * 789 * Intended to be used in case of GEM_INTR_RX_TAG_ERR, GEM_MAC_RX_OVERFLOW 790 * etc in order to reset the receiver DMA engine only and not do a full 791 * reset which amongst others also downs the link and clears the FIFOs. 792 */ 793 static void 794 gem_reset_rxdma(struct gem_softc *sc) 795 { 796 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 797 bus_space_tag_t t = sc->sc_bustag; 798 bus_space_handle_t h = sc->sc_h1; 799 int i; 800 801 if (gem_reset_rx(sc) != 0) { 802 gem_init(ifp); 803 return; 804 } 805 for (i = 0; i < GEM_NRXDESC; i++) 806 if (sc->sc_rxsoft[i].rxs_mbuf != NULL) 807 GEM_UPDATE_RXDESC(sc, i); 808 sc->sc_rxptr = 0; 809 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE); 810 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD); 811 812 /* Reprogram Descriptor Ring Base Addresses */ 813 /* NOTE: we use only 32-bit DMA addresses here. */ 814 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0); 815 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 816 817 /* Redo ERX Configuration */ 818 gem_rx_common(sc); 819 820 /* Give the reciever a swift kick */ 821 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC - 4); 822 } 823 824 /* 825 * Common RX configuration for gem_init() and gem_reset_rxdma(). 826 */ 827 static void 828 gem_rx_common(struct gem_softc *sc) 829 { 830 bus_space_tag_t t = sc->sc_bustag; 831 bus_space_handle_t h = sc->sc_h1; 832 u_int32_t v; 833 834 /* Encode Receive Descriptor ring size: four possible values */ 835 v = gem_ringsize(GEM_NRXDESC /*XXX*/); 836 837 /* Set receive h/w checksum offset */ 838 #ifdef INET 839 v |= (ETHER_HDR_LEN + sizeof(struct ip) + 840 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 841 ETHER_VLAN_ENCAP_LEN : 0)) << GEM_RX_CONFIG_CXM_START_SHFT; 842 #endif 843 844 /* Enable RX DMA */ 845 bus_space_write_4(t, h, GEM_RX_CONFIG, 846 v | (GEM_THRSH_1024 << GEM_RX_CONFIG_FIFO_THRS_SHIFT) | 847 (2 << GEM_RX_CONFIG_FBOFF_SHFT) | GEM_RX_CONFIG_RXDMA_EN); 848 849 /* 850 * The following value is for an OFF Threshold of about 3/4 full 851 * and an ON Threshold of 1/4 full. 852 */ 853 bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH, 854 (3 * sc->sc_rxfifosize / 256) | 855 ((sc->sc_rxfifosize / 256) << 12)); 856 bus_space_write_4(t, h, GEM_RX_BLANKING, 857 (6 << GEM_RX_BLANKING_TIME_SHIFT) | 6); 858 } 859 860 /* 861 * Reset the transmitter 862 */ 863 int 864 gem_reset_tx(struct gem_softc *sc) 865 { 866 bus_space_tag_t t = sc->sc_bustag; 867 bus_space_handle_t h = sc->sc_h1, h2 = sc->sc_h2; 868 869 /* 870 * Resetting while DMA is in progress can cause a bus hang, so we 871 * disable DMA first. 872 */ 873 gem_disable_tx(sc); 874 bus_space_write_4(t, h, GEM_TX_CONFIG, 0); 875 bus_space_barrier(t, h, GEM_TX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 876 /* Wait till it finishes */ 877 if (!gem_bitwait(sc, h, GEM_TX_CONFIG, 1, 0)) 878 aprint_error_dev(sc->sc_dev, "cannot disable read dma\n"); 879 /* Wait 5ms extra. */ 880 delay(5000); 881 882 /* Finally, reset the ETX */ 883 bus_space_write_4(t, h2, GEM_RESET, GEM_RESET_TX); 884 bus_space_barrier(t, h, GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE); 885 /* Wait till it finishes */ 886 if (!gem_bitwait(sc, h2, GEM_RESET, GEM_RESET_TX, 0)) { 887 aprint_error_dev(sc->sc_dev, "cannot reset receiver\n"); 888 return (1); 889 } 890 return (0); 891 } 892 893 /* 894 * disable receiver. 895 */ 896 int 897 gem_disable_rx(struct gem_softc *sc) 898 { 899 bus_space_tag_t t = sc->sc_bustag; 900 bus_space_handle_t h = sc->sc_h1; 901 u_int32_t cfg; 902 903 /* Flip the enable bit */ 904 cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 905 cfg &= ~GEM_MAC_RX_ENABLE; 906 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg); 907 bus_space_barrier(t, h, GEM_MAC_RX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 908 /* Wait for it to finish */ 909 return (gem_bitwait(sc, h, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)); 910 } 911 912 /* 913 * disable transmitter. 914 */ 915 int 916 gem_disable_tx(struct gem_softc *sc) 917 { 918 bus_space_tag_t t = sc->sc_bustag; 919 bus_space_handle_t h = sc->sc_h1; 920 u_int32_t cfg; 921 922 /* Flip the enable bit */ 923 cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG); 924 cfg &= ~GEM_MAC_TX_ENABLE; 925 bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg); 926 bus_space_barrier(t, h, GEM_MAC_TX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 927 /* Wait for it to finish */ 928 return (gem_bitwait(sc, h, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)); 929 } 930 931 /* 932 * Initialize interface. 933 */ 934 int 935 gem_meminit(struct gem_softc *sc) 936 { 937 struct gem_rxsoft *rxs; 938 int i, error; 939 940 /* 941 * Initialize the transmit descriptor ring. 942 */ 943 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 944 for (i = 0; i < GEM_NTXDESC; i++) { 945 sc->sc_txdescs[i].gd_flags = 0; 946 sc->sc_txdescs[i].gd_addr = 0; 947 } 948 GEM_CDTXSYNC(sc, 0, GEM_NTXDESC, 949 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 950 sc->sc_txfree = GEM_NTXDESC-1; 951 sc->sc_txnext = 0; 952 sc->sc_txwin = 0; 953 954 /* 955 * Initialize the receive descriptor and receive job 956 * descriptor rings. 957 */ 958 for (i = 0; i < GEM_NRXDESC; i++) { 959 rxs = &sc->sc_rxsoft[i]; 960 if (rxs->rxs_mbuf == NULL) { 961 if ((error = gem_add_rxbuf(sc, i)) != 0) { 962 aprint_error_dev(sc->sc_dev, 963 "unable to allocate or map rx " 964 "buffer %d, error = %d\n", 965 i, error); 966 /* 967 * XXX Should attempt to run with fewer receive 968 * XXX buffers instead of just failing. 969 */ 970 gem_rxdrain(sc); 971 return (1); 972 } 973 } else 974 GEM_INIT_RXDESC(sc, i); 975 } 976 sc->sc_rxptr = 0; 977 sc->sc_meminited = 1; 978 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE); 979 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD); 980 981 return (0); 982 } 983 984 static int 985 gem_ringsize(int sz) 986 { 987 switch (sz) { 988 case 32: 989 return GEM_RING_SZ_32; 990 case 64: 991 return GEM_RING_SZ_64; 992 case 128: 993 return GEM_RING_SZ_128; 994 case 256: 995 return GEM_RING_SZ_256; 996 case 512: 997 return GEM_RING_SZ_512; 998 case 1024: 999 return GEM_RING_SZ_1024; 1000 case 2048: 1001 return GEM_RING_SZ_2048; 1002 case 4096: 1003 return GEM_RING_SZ_4096; 1004 case 8192: 1005 return GEM_RING_SZ_8192; 1006 default: 1007 printf("gem: invalid Receive Descriptor ring size %d\n", sz); 1008 return GEM_RING_SZ_32; 1009 } 1010 } 1011 1012 1013 /* 1014 * Start PCS 1015 */ 1016 void 1017 gem_pcs_start(struct gem_softc *sc) 1018 { 1019 bus_space_tag_t t = sc->sc_bustag; 1020 bus_space_handle_t h = sc->sc_h1; 1021 uint32_t v; 1022 1023 #ifdef GEM_DEBUG 1024 aprint_debug_dev(sc->sc_dev, "gem_pcs_start()\n"); 1025 #endif 1026 1027 /* 1028 * Set up. We must disable the MII before modifying the 1029 * GEM_MII_ANAR register 1030 */ 1031 if (sc->sc_flags & GEM_SERDES) { 1032 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 1033 GEM_MII_DATAPATH_SERDES); 1034 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 1035 GEM_MII_SLINK_LOOPBACK); 1036 } else { 1037 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 1038 GEM_MII_DATAPATH_SERIAL); 1039 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 0); 1040 } 1041 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 1042 v = bus_space_read_4(t, h, GEM_MII_ANAR); 1043 v |= (GEM_MII_ANEG_SYM_PAUSE | GEM_MII_ANEG_ASYM_PAUSE); 1044 if (sc->sc_mii_media == IFM_AUTO) 1045 v |= (GEM_MII_ANEG_FUL_DUPLX | GEM_MII_ANEG_HLF_DUPLX); 1046 else if (sc->sc_mii_media == IFM_FDX) { 1047 v |= GEM_MII_ANEG_FUL_DUPLX; 1048 v &= ~GEM_MII_ANEG_HLF_DUPLX; 1049 } else if (sc->sc_mii_media == IFM_HDX) { 1050 v &= ~GEM_MII_ANEG_FUL_DUPLX; 1051 v |= GEM_MII_ANEG_HLF_DUPLX; 1052 } 1053 1054 /* Configure link. */ 1055 bus_space_write_4(t, h, GEM_MII_ANAR, v); 1056 bus_space_write_4(t, h, GEM_MII_CONTROL, 1057 GEM_MII_CONTROL_AUTONEG | GEM_MII_CONTROL_RAN); 1058 bus_space_write_4(t, h, GEM_MII_CONFIG, GEM_MII_CONFIG_ENABLE); 1059 gem_bitwait(sc, h, GEM_MII_STATUS, 0, GEM_MII_STATUS_ANEG_CPT); 1060 1061 /* Start the 10 second timer */ 1062 callout_reset(&sc->sc_tick_ch, hz * 10, gem_tick, sc); 1063 } 1064 1065 /* 1066 * Stop PCS 1067 */ 1068 void 1069 gem_pcs_stop(struct gem_softc *sc, int disable) 1070 { 1071 bus_space_tag_t t = sc->sc_bustag; 1072 bus_space_handle_t h = sc->sc_h1; 1073 1074 #ifdef GEM_DEBUG 1075 aprint_debug_dev(sc->sc_dev, "gem_pcs_stop()\n"); 1076 #endif 1077 1078 /* Tell link partner that we're going away */ 1079 bus_space_write_4(t, h, GEM_MII_ANAR, GEM_MII_ANEG_RF); 1080 1081 /* 1082 * Disable PCS MII. The documentation suggests that setting 1083 * GEM_MII_CONFIG_ENABLE to zero and then restarting auto- 1084 * negotiation will shut down the link. However, it appears 1085 * that we also need to unset the datapath mode. 1086 */ 1087 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 1088 bus_space_write_4(t, h, GEM_MII_CONTROL, 1089 GEM_MII_CONTROL_AUTONEG | GEM_MII_CONTROL_RAN); 1090 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, GEM_MII_DATAPATH_MII); 1091 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 1092 1093 if (disable) { 1094 if (sc->sc_flags & GEM_SERDES) 1095 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 1096 GEM_MII_SLINK_POWER_OFF); 1097 else 1098 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 1099 GEM_MII_SLINK_LOOPBACK | GEM_MII_SLINK_POWER_OFF); 1100 } 1101 1102 sc->sc_flags &= ~GEM_LINK; 1103 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_NONE; 1104 sc->sc_mii.mii_media_status = IFM_AVALID; 1105 } 1106 1107 1108 /* 1109 * Initialization of interface; set up initialization block 1110 * and transmit/receive descriptor rings. 1111 */ 1112 int 1113 gem_init(struct ifnet *ifp) 1114 { 1115 struct gem_softc *sc = ifp->if_softc; 1116 bus_space_tag_t t = sc->sc_bustag; 1117 bus_space_handle_t h = sc->sc_h1; 1118 int rc = 0, s; 1119 u_int max_frame_size; 1120 u_int32_t v; 1121 1122 s = splnet(); 1123 1124 DPRINTF(sc, ("%s: gem_init: calling stop\n", device_xname(sc->sc_dev))); 1125 /* 1126 * Initialization sequence. The numbered steps below correspond 1127 * to the sequence outlined in section 6.3.5.1 in the Ethernet 1128 * Channel Engine manual (part of the PCIO manual). 1129 * See also the STP2002-STQ document from Sun Microsystems. 1130 */ 1131 1132 /* step 1 & 2. Reset the Ethernet Channel */ 1133 gem_stop(ifp, 0); 1134 gem_reset(sc); 1135 DPRINTF(sc, ("%s: gem_init: restarting\n", device_xname(sc->sc_dev))); 1136 1137 /* Re-initialize the MIF */ 1138 gem_mifinit(sc); 1139 1140 /* Set up correct datapath for non-SERDES/Serialink */ 1141 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0 && 1142 sc->sc_variant != GEM_SUN_ERI) 1143 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 1144 GEM_MII_DATAPATH_MII); 1145 1146 /* Call MI reset function if any */ 1147 if (sc->sc_hwreset) 1148 (*sc->sc_hwreset)(sc); 1149 1150 /* step 3. Setup data structures in host memory */ 1151 if (gem_meminit(sc) != 0) 1152 return 1; 1153 1154 /* step 4. TX MAC registers & counters */ 1155 gem_init_regs(sc); 1156 max_frame_size = max(sc->sc_ethercom.ec_if.if_mtu, ETHERMTU); 1157 max_frame_size += ETHER_HDR_LEN + ETHER_CRC_LEN; 1158 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1159 max_frame_size += ETHER_VLAN_ENCAP_LEN; 1160 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 1161 max_frame_size|/* burst size */(0x2000<<16)); 1162 1163 /* step 5. RX MAC registers & counters */ 1164 gem_setladrf(sc); 1165 1166 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 1167 /* NOTE: we use only 32-bit DMA addresses here. */ 1168 bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 0); 1169 bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 1170 1171 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0); 1172 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 1173 1174 /* step 8. Global Configuration & Interrupt Mask */ 1175 gem_inten(sc); 1176 bus_space_write_4(t, h, GEM_MAC_RX_MASK, 1177 GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT); 1178 bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXX */ 1179 bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 1180 GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME); 1181 1182 /* step 9. ETX Configuration: use mostly default values */ 1183 1184 /* Enable TX DMA */ 1185 v = gem_ringsize(GEM_NTXDESC /*XXX*/); 1186 bus_space_write_4(t, h, GEM_TX_CONFIG, 1187 v | GEM_TX_CONFIG_TXDMA_EN | 1188 (((sc->sc_flags & GEM_GIGABIT ? 0x4FF : 0x100) << 10) & 1189 GEM_TX_CONFIG_TXFIFO_TH)); 1190 bus_space_write_4(t, h, GEM_TX_KICK, sc->sc_txnext); 1191 1192 /* step 10. ERX Configuration */ 1193 gem_rx_common(sc); 1194 1195 /* step 11. Configure Media */ 1196 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0 && 1197 (rc = mii_ifmedia_change(&sc->sc_mii)) != 0) 1198 goto out; 1199 1200 /* step 12. RX_MAC Configuration Register */ 1201 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 1202 v |= GEM_MAC_RX_ENABLE | GEM_MAC_RX_STRIP_CRC; 1203 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 1204 1205 /* step 14. Issue Transmit Pending command */ 1206 1207 /* Call MI initialization function if any */ 1208 if (sc->sc_hwinit) 1209 (*sc->sc_hwinit)(sc); 1210 1211 1212 /* step 15. Give the reciever a swift kick */ 1213 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4); 1214 1215 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 1216 /* Configure PCS */ 1217 gem_pcs_start(sc); 1218 else 1219 /* Start the one second timer. */ 1220 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 1221 1222 sc->sc_flags &= ~GEM_LINK; 1223 ifp->if_flags |= IFF_RUNNING; 1224 ifp->if_flags &= ~IFF_OACTIVE; 1225 ifp->if_timer = 0; 1226 sc->sc_if_flags = ifp->if_flags; 1227 out: 1228 splx(s); 1229 1230 return (0); 1231 } 1232 1233 void 1234 gem_init_regs(struct gem_softc *sc) 1235 { 1236 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1237 bus_space_tag_t t = sc->sc_bustag; 1238 bus_space_handle_t h = sc->sc_h1; 1239 const u_char *laddr = CLLADDR(ifp->if_sadl); 1240 u_int32_t v; 1241 1242 /* These regs are not cleared on reset */ 1243 if (!sc->sc_inited) { 1244 1245 /* Load recommended values */ 1246 bus_space_write_4(t, h, GEM_MAC_IPG0, 0x00); 1247 bus_space_write_4(t, h, GEM_MAC_IPG1, 0x08); 1248 bus_space_write_4(t, h, GEM_MAC_IPG2, 0x04); 1249 1250 bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 1251 /* Max frame and max burst size */ 1252 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 1253 ETHER_MAX_LEN | (0x2000<<16)); 1254 1255 bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x07); 1256 bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x04); 1257 bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10); 1258 bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088); 1259 bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED, 1260 ((laddr[5]<<8)|laddr[4])&0x3ff); 1261 1262 /* Secondary MAC addr set to 0:0:0:0:0:0 */ 1263 bus_space_write_4(t, h, GEM_MAC_ADDR3, 0); 1264 bus_space_write_4(t, h, GEM_MAC_ADDR4, 0); 1265 bus_space_write_4(t, h, GEM_MAC_ADDR5, 0); 1266 1267 /* MAC control addr set to 01:80:c2:00:00:01 */ 1268 bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001); 1269 bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200); 1270 bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180); 1271 1272 /* MAC filter addr set to 0:0:0:0:0:0 */ 1273 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0); 1274 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0); 1275 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0); 1276 1277 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0); 1278 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0); 1279 1280 sc->sc_inited = 1; 1281 } 1282 1283 /* Counters need to be zeroed */ 1284 bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0); 1285 bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0); 1286 bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0); 1287 bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0); 1288 bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0); 1289 bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0); 1290 bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0); 1291 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 1292 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 1293 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 1294 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 1295 1296 /* Set XOFF PAUSE time. */ 1297 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); 1298 1299 /* 1300 * Set the internal arbitration to "infinite" bursts of the 1301 * maximum length of 31 * 64 bytes so DMA transfers aren't 1302 * split up in cache line size chunks. This greatly improves 1303 * especially RX performance. 1304 * Enable silicon bug workarounds for the Apple variants. 1305 */ 1306 bus_space_write_4(t, h, GEM_CONFIG, 1307 GEM_CONFIG_TXDMA_LIMIT | GEM_CONFIG_RXDMA_LIMIT | 1308 ((sc->sc_flags & GEM_PCI) ? 1309 GEM_CONFIG_BURST_INF : GEM_CONFIG_BURST_64) | (GEM_IS_APPLE(sc) ? 1310 GEM_CONFIG_RONPAULBIT | GEM_CONFIG_BUG2FIX : 0)); 1311 1312 /* 1313 * Set the station address. 1314 */ 1315 bus_space_write_4(t, h, GEM_MAC_ADDR0, (laddr[4]<<8)|laddr[5]); 1316 bus_space_write_4(t, h, GEM_MAC_ADDR1, (laddr[2]<<8)|laddr[3]); 1317 bus_space_write_4(t, h, GEM_MAC_ADDR2, (laddr[0]<<8)|laddr[1]); 1318 1319 /* 1320 * Enable MII outputs. Enable GMII if there is a gigabit PHY. 1321 */ 1322 sc->sc_mif_config = bus_space_read_4(t, h, GEM_MIF_CONFIG); 1323 v = GEM_MAC_XIF_TX_MII_ENA; 1324 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) { 1325 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) { 1326 v |= GEM_MAC_XIF_FDPLX_LED; 1327 if (sc->sc_flags & GEM_GIGABIT) 1328 v |= GEM_MAC_XIF_GMII_MODE; 1329 } 1330 } else { 1331 v |= GEM_MAC_XIF_GMII_MODE; 1332 } 1333 bus_space_write_4(t, h, GEM_MAC_XIF_CONFIG, v); 1334 } 1335 1336 #ifdef GEM_DEBUG 1337 static void 1338 gem_txsoft_print(const struct gem_softc *sc, int firstdesc, int lastdesc) 1339 { 1340 int i; 1341 1342 for (i = firstdesc;; i = GEM_NEXTTX(i)) { 1343 printf("descriptor %d:\t", i); 1344 printf("gd_flags: 0x%016" PRIx64 "\t", 1345 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags)); 1346 printf("gd_addr: 0x%016" PRIx64 "\n", 1347 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr)); 1348 if (i == lastdesc) 1349 break; 1350 } 1351 } 1352 #endif 1353 1354 static void 1355 gem_start(struct ifnet *ifp) 1356 { 1357 struct gem_softc *sc = ifp->if_softc; 1358 struct mbuf *m0, *m; 1359 struct gem_txsoft *txs; 1360 bus_dmamap_t dmamap; 1361 int error, firsttx, nexttx = -1, lasttx = -1, ofree, seg; 1362 uint64_t flags = 0; 1363 1364 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1365 return; 1366 1367 /* 1368 * Remember the previous number of free descriptors and 1369 * the first descriptor we'll use. 1370 */ 1371 ofree = sc->sc_txfree; 1372 firsttx = sc->sc_txnext; 1373 1374 DPRINTF(sc, ("%s: gem_start: txfree %d, txnext %d\n", 1375 device_xname(sc->sc_dev), ofree, firsttx)); 1376 1377 /* 1378 * Loop through the send queue, setting up transmit descriptors 1379 * until we drain the queue, or use up all available transmit 1380 * descriptors. 1381 */ 1382 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 1383 sc->sc_txfree != 0) { 1384 /* 1385 * Grab a packet off the queue. 1386 */ 1387 IFQ_POLL(&ifp->if_snd, m0); 1388 if (m0 == NULL) 1389 break; 1390 m = NULL; 1391 1392 dmamap = txs->txs_dmamap; 1393 1394 /* 1395 * Load the DMA map. If this fails, the packet either 1396 * didn't fit in the alloted number of segments, or we were 1397 * short on resources. In this case, we'll copy and try 1398 * again. 1399 */ 1400 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m0, 1401 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0 || 1402 (m0->m_pkthdr.len < ETHER_MIN_TX && 1403 dmamap->dm_nsegs == GEM_NTXSEGS)) { 1404 if (m0->m_pkthdr.len > MCLBYTES) { 1405 aprint_error_dev(sc->sc_dev, 1406 "unable to allocate jumbo Tx cluster\n"); 1407 IFQ_DEQUEUE(&ifp->if_snd, m0); 1408 m_freem(m0); 1409 continue; 1410 } 1411 MGETHDR(m, M_DONTWAIT, MT_DATA); 1412 if (m == NULL) { 1413 aprint_error_dev(sc->sc_dev, 1414 "unable to allocate Tx mbuf\n"); 1415 break; 1416 } 1417 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1418 if (m0->m_pkthdr.len > MHLEN) { 1419 MCLGET(m, M_DONTWAIT); 1420 if ((m->m_flags & M_EXT) == 0) { 1421 aprint_error_dev(sc->sc_dev, 1422 "unable to allocate Tx cluster\n"); 1423 m_freem(m); 1424 break; 1425 } 1426 } 1427 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1428 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1429 error = bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, 1430 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1431 if (error) { 1432 aprint_error_dev(sc->sc_dev, 1433 "unable to load Tx buffer, error = %d\n", 1434 error); 1435 break; 1436 } 1437 } 1438 1439 /* 1440 * Ensure we have enough descriptors free to describe 1441 * the packet. 1442 */ 1443 if (dmamap->dm_nsegs > ((m0->m_pkthdr.len < ETHER_MIN_TX) ? 1444 (sc->sc_txfree - 1) : sc->sc_txfree)) { 1445 /* 1446 * Not enough free descriptors to transmit this 1447 * packet. We haven't committed to anything yet, 1448 * so just unload the DMA map, put the packet 1449 * back on the queue, and punt. Notify the upper 1450 * layer that there are no more slots left. 1451 * 1452 * XXX We could allocate an mbuf and copy, but 1453 * XXX it is worth it? 1454 */ 1455 ifp->if_flags |= IFF_OACTIVE; 1456 sc->sc_if_flags = ifp->if_flags; 1457 bus_dmamap_unload(sc->sc_dmatag, dmamap); 1458 if (m != NULL) 1459 m_freem(m); 1460 break; 1461 } 1462 1463 IFQ_DEQUEUE(&ifp->if_snd, m0); 1464 if (m != NULL) { 1465 m_freem(m0); 1466 m0 = m; 1467 } 1468 1469 /* 1470 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1471 */ 1472 1473 /* Sync the DMA map. */ 1474 bus_dmamap_sync(sc->sc_dmatag, dmamap, 0, dmamap->dm_mapsize, 1475 BUS_DMASYNC_PREWRITE); 1476 1477 /* 1478 * Initialize the transmit descriptors. 1479 */ 1480 for (nexttx = sc->sc_txnext, seg = 0; 1481 seg < dmamap->dm_nsegs; 1482 seg++, nexttx = GEM_NEXTTX(nexttx)) { 1483 1484 /* 1485 * If this is the first descriptor we're 1486 * enqueueing, set the start of packet flag, 1487 * and the checksum stuff if we want the hardware 1488 * to do it. 1489 */ 1490 sc->sc_txdescs[nexttx].gd_addr = 1491 GEM_DMA_WRITE(sc, dmamap->dm_segs[seg].ds_addr); 1492 flags = dmamap->dm_segs[seg].ds_len & GEM_TD_BUFSIZE; 1493 if (nexttx == firsttx) { 1494 flags |= GEM_TD_START_OF_PACKET; 1495 if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) { 1496 sc->sc_txwin = 0; 1497 flags |= GEM_TD_INTERRUPT_ME; 1498 } 1499 1500 #ifdef INET 1501 /* h/w checksum */ 1502 if (ifp->if_csum_flags_tx & M_CSUM_TCPv4 && 1503 m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1504 struct ether_header *eh; 1505 uint16_t offset, start; 1506 1507 eh = mtod(m0, struct ether_header *); 1508 switch (ntohs(eh->ether_type)) { 1509 case ETHERTYPE_IP: 1510 start = ETHER_HDR_LEN; 1511 break; 1512 case ETHERTYPE_VLAN: 1513 start = ETHER_HDR_LEN + 1514 ETHER_VLAN_ENCAP_LEN; 1515 break; 1516 default: 1517 /* unsupported, drop it */ 1518 m_free(m0); 1519 continue; 1520 } 1521 start += M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 1522 offset = M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data) + start; 1523 flags |= (start << 1524 GEM_TD_CXSUM_STARTSHFT) | 1525 (offset << 1526 GEM_TD_CXSUM_STUFFSHFT) | 1527 GEM_TD_CXSUM_ENABLE; 1528 } 1529 #endif 1530 } 1531 if (seg == dmamap->dm_nsegs - 1) { 1532 flags |= GEM_TD_END_OF_PACKET; 1533 } else { 1534 /* last flag set outside of loop */ 1535 sc->sc_txdescs[nexttx].gd_flags = 1536 GEM_DMA_WRITE(sc, flags); 1537 } 1538 lasttx = nexttx; 1539 } 1540 if (m0->m_pkthdr.len < ETHER_MIN_TX) { 1541 /* add padding buffer at end of chain */ 1542 flags &= ~GEM_TD_END_OF_PACKET; 1543 sc->sc_txdescs[lasttx].gd_flags = 1544 GEM_DMA_WRITE(sc, flags); 1545 1546 sc->sc_txdescs[nexttx].gd_addr = 1547 GEM_DMA_WRITE(sc, 1548 sc->sc_nulldmamap->dm_segs[0].ds_addr); 1549 flags = ((ETHER_MIN_TX - m0->m_pkthdr.len) & 1550 GEM_TD_BUFSIZE) | GEM_TD_END_OF_PACKET; 1551 lasttx = nexttx; 1552 nexttx = GEM_NEXTTX(nexttx); 1553 seg++; 1554 } 1555 sc->sc_txdescs[lasttx].gd_flags = GEM_DMA_WRITE(sc, flags); 1556 1557 KASSERT(lasttx != -1); 1558 1559 /* 1560 * Store a pointer to the packet so we can free it later, 1561 * and remember what txdirty will be once the packet is 1562 * done. 1563 */ 1564 txs->txs_mbuf = m0; 1565 txs->txs_firstdesc = sc->sc_txnext; 1566 txs->txs_lastdesc = lasttx; 1567 txs->txs_ndescs = seg; 1568 1569 #ifdef GEM_DEBUG 1570 if (ifp->if_flags & IFF_DEBUG) { 1571 printf(" gem_start %p transmit chain:\n", txs); 1572 gem_txsoft_print(sc, txs->txs_firstdesc, 1573 txs->txs_lastdesc); 1574 } 1575 #endif 1576 1577 /* Sync the descriptors we're using. */ 1578 GEM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndescs, 1579 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1580 1581 /* Advance the tx pointer. */ 1582 sc->sc_txfree -= txs->txs_ndescs; 1583 sc->sc_txnext = nexttx; 1584 1585 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1586 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1587 1588 /* 1589 * Pass the packet to any BPF listeners. 1590 */ 1591 bpf_mtap(ifp, m0); 1592 } 1593 1594 if (txs == NULL || sc->sc_txfree == 0) { 1595 /* No more slots left; notify upper layer. */ 1596 ifp->if_flags |= IFF_OACTIVE; 1597 sc->sc_if_flags = ifp->if_flags; 1598 } 1599 1600 if (sc->sc_txfree != ofree) { 1601 DPRINTF(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 1602 device_xname(sc->sc_dev), lasttx, firsttx)); 1603 /* 1604 * The entire packet chain is set up. 1605 * Kick the transmitter. 1606 */ 1607 DPRINTF(sc, ("%s: gem_start: kicking tx %d\n", 1608 device_xname(sc->sc_dev), nexttx)); 1609 bus_space_write_4(sc->sc_bustag, sc->sc_h1, GEM_TX_KICK, 1610 sc->sc_txnext); 1611 1612 /* Set a watchdog timer in case the chip flakes out. */ 1613 ifp->if_timer = 5; 1614 DPRINTF(sc, ("%s: gem_start: watchdog %d\n", 1615 device_xname(sc->sc_dev), ifp->if_timer)); 1616 } 1617 } 1618 1619 /* 1620 * Transmit interrupt. 1621 */ 1622 int 1623 gem_tint(struct gem_softc *sc) 1624 { 1625 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1626 bus_space_tag_t t = sc->sc_bustag; 1627 bus_space_handle_t mac = sc->sc_h1; 1628 struct gem_txsoft *txs; 1629 int txlast; 1630 int progress = 0; 1631 u_int32_t v; 1632 1633 DPRINTF(sc, ("%s: gem_tint\n", device_xname(sc->sc_dev))); 1634 1635 /* Unload collision counters ... */ 1636 v = bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) + 1637 bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT); 1638 ifp->if_collisions += v + 1639 bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) + 1640 bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT); 1641 ifp->if_oerrors += v; 1642 1643 /* ... then clear the hardware counters. */ 1644 bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0); 1645 bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0); 1646 bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0); 1647 bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0); 1648 1649 /* 1650 * Go through our Tx list and free mbufs for those 1651 * frames that have been transmitted. 1652 */ 1653 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1654 /* 1655 * In theory, we could harvest some descriptors before 1656 * the ring is empty, but that's a bit complicated. 1657 * 1658 * GEM_TX_COMPLETION points to the last descriptor 1659 * processed +1. 1660 * 1661 * Let's assume that the NIC writes back to the Tx 1662 * descriptors before it updates the completion 1663 * register. If the NIC has posted writes to the 1664 * Tx descriptors, PCI ordering requires that the 1665 * posted writes flush to RAM before the register-read 1666 * finishes. So let's read the completion register, 1667 * before syncing the descriptors, so that we 1668 * examine Tx descriptors that are at least as 1669 * current as the completion register. 1670 */ 1671 txlast = bus_space_read_4(t, mac, GEM_TX_COMPLETION); 1672 DPRINTF(sc, 1673 ("gem_tint: txs->txs_lastdesc = %d, txlast = %d\n", 1674 txs->txs_lastdesc, txlast)); 1675 if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1676 if (txlast >= txs->txs_firstdesc && 1677 txlast <= txs->txs_lastdesc) 1678 break; 1679 } else if (txlast >= txs->txs_firstdesc || 1680 txlast <= txs->txs_lastdesc) 1681 break; 1682 1683 GEM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndescs, 1684 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1685 1686 #ifdef GEM_DEBUG /* XXX DMA synchronization? */ 1687 if (ifp->if_flags & IFF_DEBUG) { 1688 printf(" txsoft %p transmit chain:\n", txs); 1689 gem_txsoft_print(sc, txs->txs_firstdesc, 1690 txs->txs_lastdesc); 1691 } 1692 #endif 1693 1694 1695 DPRINTF(sc, ("gem_tint: releasing a desc\n")); 1696 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1697 1698 sc->sc_txfree += txs->txs_ndescs; 1699 1700 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 1701 0, txs->txs_dmamap->dm_mapsize, 1702 BUS_DMASYNC_POSTWRITE); 1703 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 1704 if (txs->txs_mbuf != NULL) { 1705 m_freem(txs->txs_mbuf); 1706 txs->txs_mbuf = NULL; 1707 } 1708 1709 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1710 1711 ifp->if_opackets++; 1712 progress = 1; 1713 } 1714 1715 #if 0 1716 DPRINTF(sc, ("gem_tint: GEM_TX_STATE_MACHINE %x " 1717 "GEM_TX_DATA_PTR %" PRIx64 "GEM_TX_COMPLETION %" PRIx32 "\n", 1718 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_TX_STATE_MACHINE), 1719 ((uint64_t)bus_space_read_4(sc->sc_bustag, sc->sc_h1, 1720 GEM_TX_DATA_PTR_HI) << 32) | 1721 bus_space_read_4(sc->sc_bustag, sc->sc_h1, 1722 GEM_TX_DATA_PTR_LO), 1723 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_TX_COMPLETION))); 1724 #endif 1725 1726 if (progress) { 1727 if (sc->sc_txfree == GEM_NTXDESC - 1) 1728 sc->sc_txwin = 0; 1729 1730 /* Freed some descriptors, so reset IFF_OACTIVE and restart. */ 1731 ifp->if_flags &= ~IFF_OACTIVE; 1732 sc->sc_if_flags = ifp->if_flags; 1733 ifp->if_timer = SIMPLEQ_EMPTY(&sc->sc_txdirtyq) ? 0 : 5; 1734 gem_start(ifp); 1735 } 1736 DPRINTF(sc, ("%s: gem_tint: watchdog %d\n", 1737 device_xname(sc->sc_dev), ifp->if_timer)); 1738 1739 return (1); 1740 } 1741 1742 /* 1743 * Receive interrupt. 1744 */ 1745 int 1746 gem_rint(struct gem_softc *sc) 1747 { 1748 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1749 bus_space_tag_t t = sc->sc_bustag; 1750 bus_space_handle_t h = sc->sc_h1; 1751 struct gem_rxsoft *rxs; 1752 struct mbuf *m; 1753 u_int64_t rxstat; 1754 u_int32_t rxcomp; 1755 int i, len, progress = 0; 1756 1757 DPRINTF(sc, ("%s: gem_rint\n", device_xname(sc->sc_dev))); 1758 1759 /* 1760 * Ignore spurious interrupt that sometimes occurs before 1761 * we are set up when we network boot. 1762 */ 1763 if (!sc->sc_meminited) 1764 return 1; 1765 1766 /* 1767 * Read the completion register once. This limits 1768 * how long the following loop can execute. 1769 */ 1770 rxcomp = bus_space_read_4(t, h, GEM_RX_COMPLETION); 1771 1772 /* 1773 * XXX Read the lastrx only once at the top for speed. 1774 */ 1775 DPRINTF(sc, ("gem_rint: sc->rxptr %d, complete %d\n", 1776 sc->sc_rxptr, rxcomp)); 1777 1778 /* 1779 * Go into the loop at least once. 1780 */ 1781 for (i = sc->sc_rxptr; i == sc->sc_rxptr || i != rxcomp; 1782 i = GEM_NEXTRX(i)) { 1783 rxs = &sc->sc_rxsoft[i]; 1784 1785 GEM_CDRXSYNC(sc, i, 1786 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1787 1788 rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags); 1789 1790 if (rxstat & GEM_RD_OWN) { 1791 GEM_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); 1792 /* 1793 * We have processed all of the receive buffers. 1794 */ 1795 break; 1796 } 1797 1798 progress++; 1799 ifp->if_ipackets++; 1800 1801 if (rxstat & GEM_RD_BAD_CRC) { 1802 ifp->if_ierrors++; 1803 aprint_error_dev(sc->sc_dev, 1804 "receive error: CRC error\n"); 1805 GEM_INIT_RXDESC(sc, i); 1806 continue; 1807 } 1808 1809 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1810 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1811 #ifdef GEM_DEBUG 1812 if (ifp->if_flags & IFF_DEBUG) { 1813 printf(" rxsoft %p descriptor %d: ", rxs, i); 1814 printf("gd_flags: 0x%016llx\t", (long long) 1815 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags)); 1816 printf("gd_addr: 0x%016llx\n", (long long) 1817 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr)); 1818 } 1819 #endif 1820 1821 /* No errors; receive the packet. */ 1822 len = GEM_RD_BUFLEN(rxstat); 1823 1824 /* 1825 * Allocate a new mbuf cluster. If that fails, we are 1826 * out of memory, and must drop the packet and recycle 1827 * the buffer that's already attached to this descriptor. 1828 */ 1829 m = rxs->rxs_mbuf; 1830 if (gem_add_rxbuf(sc, i) != 0) { 1831 GEM_COUNTER_INCR(sc, sc_ev_rxnobuf); 1832 ifp->if_ierrors++; 1833 GEM_INIT_RXDESC(sc, i); 1834 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1835 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1836 continue; 1837 } 1838 m->m_data += 2; /* We're already off by two */ 1839 1840 m->m_pkthdr.rcvif = ifp; 1841 m->m_pkthdr.len = m->m_len = len; 1842 1843 /* 1844 * Pass this up to any BPF listeners, but only 1845 * pass it up the stack if it's for us. 1846 */ 1847 bpf_mtap(ifp, m); 1848 1849 #ifdef INET 1850 /* hardware checksum */ 1851 if (ifp->if_csum_flags_rx & M_CSUM_TCPv4) { 1852 struct ether_header *eh; 1853 struct ip *ip; 1854 int32_t hlen, pktlen; 1855 1856 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1857 pktlen = m->m_pkthdr.len - ETHER_HDR_LEN - 1858 ETHER_VLAN_ENCAP_LEN; 1859 eh = (struct ether_header *) (mtod(m, char *) + 1860 ETHER_VLAN_ENCAP_LEN); 1861 } else { 1862 pktlen = m->m_pkthdr.len - ETHER_HDR_LEN; 1863 eh = mtod(m, struct ether_header *); 1864 } 1865 if (ntohs(eh->ether_type) != ETHERTYPE_IP) 1866 goto swcsum; 1867 ip = (struct ip *) ((char *)eh + ETHER_HDR_LEN); 1868 1869 /* IPv4 only */ 1870 if (ip->ip_v != IPVERSION) 1871 goto swcsum; 1872 1873 hlen = ip->ip_hl << 2; 1874 if (hlen < sizeof(struct ip)) 1875 goto swcsum; 1876 1877 /* 1878 * bail if too short, has random trailing garbage, 1879 * truncated, fragment, or has ethernet pad. 1880 */ 1881 if ((ntohs(ip->ip_len) < hlen) || 1882 (ntohs(ip->ip_len) != pktlen) || 1883 (ntohs(ip->ip_off) & (IP_MF | IP_OFFMASK))) 1884 goto swcsum; 1885 1886 switch (ip->ip_p) { 1887 case IPPROTO_TCP: 1888 if (! (ifp->if_csum_flags_rx & M_CSUM_TCPv4)) 1889 goto swcsum; 1890 if (pktlen < (hlen + sizeof(struct tcphdr))) 1891 goto swcsum; 1892 m->m_pkthdr.csum_flags = M_CSUM_TCPv4; 1893 break; 1894 case IPPROTO_UDP: 1895 /* FALLTHROUGH */ 1896 default: 1897 goto swcsum; 1898 } 1899 1900 /* the uncomplemented sum is expected */ 1901 m->m_pkthdr.csum_data = (~rxstat) & GEM_RD_CHECKSUM; 1902 1903 /* if the pkt had ip options, we have to deduct them */ 1904 if (hlen > sizeof(struct ip)) { 1905 uint16_t *opts; 1906 uint32_t optsum, temp; 1907 1908 optsum = 0; 1909 temp = hlen - sizeof(struct ip); 1910 opts = (uint16_t *) ((char *) ip + 1911 sizeof(struct ip)); 1912 1913 while (temp > 1) { 1914 optsum += ntohs(*opts++); 1915 temp -= 2; 1916 } 1917 while (optsum >> 16) 1918 optsum = (optsum >> 16) + 1919 (optsum & 0xffff); 1920 1921 /* Deduct ip opts sum from hwsum. */ 1922 m->m_pkthdr.csum_data += (uint16_t)~optsum; 1923 1924 while (m->m_pkthdr.csum_data >> 16) 1925 m->m_pkthdr.csum_data = 1926 (m->m_pkthdr.csum_data >> 16) + 1927 (m->m_pkthdr.csum_data & 1928 0xffff); 1929 } 1930 1931 m->m_pkthdr.csum_flags |= M_CSUM_DATA | 1932 M_CSUM_NO_PSEUDOHDR; 1933 } else 1934 swcsum: 1935 m->m_pkthdr.csum_flags = 0; 1936 #endif 1937 /* Pass it on. */ 1938 (*ifp->if_input)(ifp, m); 1939 } 1940 1941 if (progress) { 1942 /* Update the receive pointer. */ 1943 if (i == sc->sc_rxptr) { 1944 GEM_COUNTER_INCR(sc, sc_ev_rxfull); 1945 #ifdef GEM_DEBUG 1946 if (ifp->if_flags & IFF_DEBUG) 1947 printf("%s: rint: ring wrap\n", 1948 device_xname(sc->sc_dev)); 1949 #endif 1950 } 1951 sc->sc_rxptr = i; 1952 bus_space_write_4(t, h, GEM_RX_KICK, GEM_PREVRX(i)); 1953 } 1954 #ifdef GEM_COUNTERS 1955 if (progress <= 4) { 1956 GEM_COUNTER_INCR(sc, sc_ev_rxhist[progress]); 1957 } else if (progress < 32) { 1958 if (progress < 16) 1959 GEM_COUNTER_INCR(sc, sc_ev_rxhist[5]); 1960 else 1961 GEM_COUNTER_INCR(sc, sc_ev_rxhist[6]); 1962 1963 } else { 1964 if (progress < 64) 1965 GEM_COUNTER_INCR(sc, sc_ev_rxhist[7]); 1966 else 1967 GEM_COUNTER_INCR(sc, sc_ev_rxhist[8]); 1968 } 1969 #endif 1970 1971 DPRINTF(sc, ("gem_rint: done sc->rxptr %d, complete %d\n", 1972 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION))); 1973 1974 /* Read error counters ... */ 1975 ifp->if_ierrors += 1976 bus_space_read_4(t, h, GEM_MAC_RX_LEN_ERR_CNT) + 1977 bus_space_read_4(t, h, GEM_MAC_RX_ALIGN_ERR) + 1978 bus_space_read_4(t, h, GEM_MAC_RX_CRC_ERR_CNT) + 1979 bus_space_read_4(t, h, GEM_MAC_RX_CODE_VIOL); 1980 1981 /* ... then clear the hardware counters. */ 1982 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 1983 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 1984 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 1985 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 1986 1987 return (1); 1988 } 1989 1990 1991 /* 1992 * gem_add_rxbuf: 1993 * 1994 * Add a receive buffer to the indicated descriptor. 1995 */ 1996 int 1997 gem_add_rxbuf(struct gem_softc *sc, int idx) 1998 { 1999 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 2000 struct mbuf *m; 2001 int error; 2002 2003 MGETHDR(m, M_DONTWAIT, MT_DATA); 2004 if (m == NULL) 2005 return (ENOBUFS); 2006 2007 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2008 MCLGET(m, M_DONTWAIT); 2009 if ((m->m_flags & M_EXT) == 0) { 2010 m_freem(m); 2011 return (ENOBUFS); 2012 } 2013 2014 #ifdef GEM_DEBUG 2015 /* bzero the packet to check DMA */ 2016 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 2017 #endif 2018 2019 if (rxs->rxs_mbuf != NULL) 2020 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 2021 2022 rxs->rxs_mbuf = m; 2023 2024 error = bus_dmamap_load(sc->sc_dmatag, rxs->rxs_dmamap, 2025 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2026 BUS_DMA_READ|BUS_DMA_NOWAIT); 2027 if (error) { 2028 aprint_error_dev(sc->sc_dev, 2029 "can't load rx DMA map %d, error = %d\n", idx, error); 2030 panic("gem_add_rxbuf"); /* XXX */ 2031 } 2032 2033 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 2034 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2035 2036 GEM_INIT_RXDESC(sc, idx); 2037 2038 return (0); 2039 } 2040 2041 2042 int 2043 gem_eint(struct gem_softc *sc, u_int status) 2044 { 2045 char bits[128]; 2046 u_int32_t r, v; 2047 2048 if ((status & GEM_INTR_MIF) != 0) { 2049 printf("%s: XXXlink status changed\n", device_xname(sc->sc_dev)); 2050 return (1); 2051 } 2052 2053 if ((status & GEM_INTR_RX_TAG_ERR) != 0) { 2054 gem_reset_rxdma(sc); 2055 return (1); 2056 } 2057 2058 if (status & GEM_INTR_BERR) { 2059 if (sc->sc_flags & GEM_PCI) 2060 r = GEM_ERROR_STATUS; 2061 else 2062 r = GEM_SBUS_ERROR_STATUS; 2063 bus_space_read_4(sc->sc_bustag, sc->sc_h2, r); 2064 v = bus_space_read_4(sc->sc_bustag, sc->sc_h2, r); 2065 aprint_error_dev(sc->sc_dev, "bus error interrupt: 0x%02x\n", 2066 v); 2067 return (1); 2068 } 2069 snprintb(bits, sizeof(bits), GEM_INTR_BITS, status); 2070 printf("%s: status=%s\n", device_xname(sc->sc_dev), bits); 2071 2072 return (1); 2073 } 2074 2075 2076 /* 2077 * PCS interrupts. 2078 * We should receive these when the link status changes, but sometimes 2079 * we don't receive them for link up. We compensate for this in the 2080 * gem_tick() callout. 2081 */ 2082 int 2083 gem_pint(struct gem_softc *sc) 2084 { 2085 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2086 bus_space_tag_t t = sc->sc_bustag; 2087 bus_space_handle_t h = sc->sc_h1; 2088 u_int32_t v, v2; 2089 2090 /* 2091 * Clear the PCS interrupt from GEM_STATUS. The PCS register is 2092 * latched, so we have to read it twice. There is only one bit in 2093 * use, so the value is meaningless. 2094 */ 2095 bus_space_read_4(t, h, GEM_MII_INTERRUP_STATUS); 2096 bus_space_read_4(t, h, GEM_MII_INTERRUP_STATUS); 2097 2098 if ((ifp->if_flags & IFF_UP) == 0) 2099 return 1; 2100 2101 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) 2102 return 1; 2103 2104 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2105 /* If we see remote fault, our link partner is probably going away */ 2106 if ((v & GEM_MII_STATUS_REM_FLT) != 0) { 2107 gem_bitwait(sc, h, GEM_MII_STATUS, GEM_MII_STATUS_REM_FLT, 0); 2108 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2109 /* Otherwise, we may need to wait after auto-negotiation completes */ 2110 } else if ((v & (GEM_MII_STATUS_LINK_STS | GEM_MII_STATUS_ANEG_CPT)) == 2111 GEM_MII_STATUS_ANEG_CPT) { 2112 gem_bitwait(sc, h, GEM_MII_STATUS, 0, GEM_MII_STATUS_LINK_STS); 2113 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2114 } 2115 if ((v & GEM_MII_STATUS_LINK_STS) != 0) { 2116 if (sc->sc_flags & GEM_LINK) { 2117 return 1; 2118 } 2119 callout_stop(&sc->sc_tick_ch); 2120 v = bus_space_read_4(t, h, GEM_MII_ANAR); 2121 v2 = bus_space_read_4(t, h, GEM_MII_ANLPAR); 2122 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_1000_SX; 2123 sc->sc_mii.mii_media_status = IFM_AVALID | IFM_ACTIVE; 2124 v &= v2; 2125 if (v & GEM_MII_ANEG_FUL_DUPLX) { 2126 sc->sc_mii.mii_media_active |= IFM_FDX; 2127 #ifdef GEM_DEBUG 2128 aprint_debug_dev(sc->sc_dev, "link up: full duplex\n"); 2129 #endif 2130 } else if (v & GEM_MII_ANEG_HLF_DUPLX) { 2131 sc->sc_mii.mii_media_active |= IFM_HDX; 2132 #ifdef GEM_DEBUG 2133 aprint_debug_dev(sc->sc_dev, "link up: half duplex\n"); 2134 #endif 2135 } else { 2136 #ifdef GEM_DEBUG 2137 aprint_debug_dev(sc->sc_dev, "duplex mismatch\n"); 2138 #endif 2139 } 2140 gem_statuschange(sc); 2141 } else { 2142 if ((sc->sc_flags & GEM_LINK) == 0) { 2143 return 1; 2144 } 2145 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_NONE; 2146 sc->sc_mii.mii_media_status = IFM_AVALID; 2147 #ifdef GEM_DEBUG 2148 aprint_debug_dev(sc->sc_dev, "link down\n"); 2149 #endif 2150 gem_statuschange(sc); 2151 2152 /* Start the 10 second timer */ 2153 callout_reset(&sc->sc_tick_ch, hz * 10, gem_tick, sc); 2154 } 2155 return 1; 2156 } 2157 2158 2159 2160 int 2161 gem_intr(void *v) 2162 { 2163 struct gem_softc *sc = v; 2164 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2165 bus_space_tag_t t = sc->sc_bustag; 2166 bus_space_handle_t h = sc->sc_h1; 2167 u_int32_t status; 2168 int r = 0; 2169 #ifdef GEM_DEBUG 2170 char bits[128]; 2171 #endif 2172 2173 /* XXX We should probably mask out interrupts until we're done */ 2174 2175 sc->sc_ev_intr.ev_count++; 2176 2177 status = bus_space_read_4(t, h, GEM_STATUS); 2178 #ifdef GEM_DEBUG 2179 snprintb(bits, sizeof(bits), GEM_INTR_BITS, status); 2180 #endif 2181 DPRINTF(sc, ("%s: gem_intr: cplt 0x%x status %s\n", 2182 device_xname(sc->sc_dev), (status >> 19), bits)); 2183 2184 2185 if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0) 2186 r |= gem_eint(sc, status); 2187 2188 /* We don't bother with GEM_INTR_TX_DONE */ 2189 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) { 2190 GEM_COUNTER_INCR(sc, sc_ev_txint); 2191 r |= gem_tint(sc); 2192 } 2193 2194 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) { 2195 GEM_COUNTER_INCR(sc, sc_ev_rxint); 2196 r |= gem_rint(sc); 2197 } 2198 2199 /* We should eventually do more than just print out error stats. */ 2200 if (status & GEM_INTR_TX_MAC) { 2201 int txstat = bus_space_read_4(t, h, GEM_MAC_TX_STATUS); 2202 if (txstat & ~GEM_MAC_TX_XMIT_DONE) 2203 printf("%s: MAC tx fault, status %x\n", 2204 device_xname(sc->sc_dev), txstat); 2205 if (txstat & (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG)) 2206 gem_init(ifp); 2207 } 2208 if (status & GEM_INTR_RX_MAC) { 2209 int rxstat = bus_space_read_4(t, h, GEM_MAC_RX_STATUS); 2210 /* 2211 * At least with GEM_SUN_GEM and some GEM_SUN_ERI 2212 * revisions GEM_MAC_RX_OVERFLOW happen often due to a 2213 * silicon bug so handle them silently. Moreover, it's 2214 * likely that the receiver has hung so we reset it. 2215 */ 2216 if (rxstat & GEM_MAC_RX_OVERFLOW) { 2217 ifp->if_ierrors++; 2218 gem_reset_rxdma(sc); 2219 } else if (rxstat & ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT)) 2220 printf("%s: MAC rx fault, status 0x%02x\n", 2221 device_xname(sc->sc_dev), rxstat); 2222 } 2223 if (status & GEM_INTR_PCS) { 2224 r |= gem_pint(sc); 2225 } 2226 2227 /* Do we need to do anything with these? 2228 if ((status & GEM_MAC_CONTROL_STATUS) != 0) { 2229 status2 = bus_read_4(sc->sc_res[0], GEM_MAC_CONTROL_STATUS); 2230 if ((status2 & GEM_MAC_PAUSED) != 0) 2231 aprintf_debug_dev(sc->sc_dev, "PAUSE received (%d slots)\n", 2232 GEM_MAC_PAUSE_TIME(status2)); 2233 if ((status2 & GEM_MAC_PAUSE) != 0) 2234 aprintf_debug_dev(sc->sc_dev, "transited to PAUSE state\n"); 2235 if ((status2 & GEM_MAC_RESUME) != 0) 2236 aprintf_debug_dev(sc->sc_dev, "transited to non-PAUSE state\n"); 2237 } 2238 if ((status & GEM_INTR_MIF) != 0) 2239 aprintf_debug_dev(sc->sc_dev, "MIF interrupt\n"); 2240 */ 2241 #if NRND > 0 2242 rnd_add_uint32(&sc->rnd_source, status); 2243 #endif 2244 return (r); 2245 } 2246 2247 2248 void 2249 gem_watchdog(struct ifnet *ifp) 2250 { 2251 struct gem_softc *sc = ifp->if_softc; 2252 2253 DPRINTF(sc, ("gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x " 2254 "GEM_MAC_RX_CONFIG %x\n", 2255 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_RX_CONFIG), 2256 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_MAC_RX_STATUS), 2257 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_MAC_RX_CONFIG))); 2258 2259 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 2260 ++ifp->if_oerrors; 2261 2262 /* Try to get more packets going. */ 2263 gem_start(ifp); 2264 } 2265 2266 /* 2267 * Initialize the MII Management Interface 2268 */ 2269 void 2270 gem_mifinit(struct gem_softc *sc) 2271 { 2272 bus_space_tag_t t = sc->sc_bustag; 2273 bus_space_handle_t mif = sc->sc_h1; 2274 2275 /* Configure the MIF in frame mode */ 2276 sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 2277 sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA; 2278 bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config); 2279 } 2280 2281 /* 2282 * MII interface 2283 * 2284 * The GEM MII interface supports at least three different operating modes: 2285 * 2286 * Bitbang mode is implemented using data, clock and output enable registers. 2287 * 2288 * Frame mode is implemented by loading a complete frame into the frame 2289 * register and polling the valid bit for completion. 2290 * 2291 * Polling mode uses the frame register but completion is indicated by 2292 * an interrupt. 2293 * 2294 */ 2295 static int 2296 gem_mii_readreg(device_t self, int phy, int reg) 2297 { 2298 struct gem_softc *sc = device_private(self); 2299 bus_space_tag_t t = sc->sc_bustag; 2300 bus_space_handle_t mif = sc->sc_h1; 2301 int n; 2302 u_int32_t v; 2303 2304 #ifdef GEM_DEBUG1 2305 if (sc->sc_debug) 2306 printf("gem_mii_readreg: PHY %d reg %d\n", phy, reg); 2307 #endif 2308 2309 /* Construct the frame command */ 2310 v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) | 2311 GEM_MIF_FRAME_READ; 2312 2313 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 2314 for (n = 0; n < 100; n++) { 2315 DELAY(1); 2316 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 2317 if (v & GEM_MIF_FRAME_TA0) 2318 return (v & GEM_MIF_FRAME_DATA); 2319 } 2320 2321 printf("%s: mii_read timeout\n", device_xname(sc->sc_dev)); 2322 return (0); 2323 } 2324 2325 static void 2326 gem_mii_writereg(device_t self, int phy, int reg, int val) 2327 { 2328 struct gem_softc *sc = device_private(self); 2329 bus_space_tag_t t = sc->sc_bustag; 2330 bus_space_handle_t mif = sc->sc_h1; 2331 int n; 2332 u_int32_t v; 2333 2334 #ifdef GEM_DEBUG1 2335 if (sc->sc_debug) 2336 printf("gem_mii_writereg: PHY %d reg %d val %x\n", 2337 phy, reg, val); 2338 #endif 2339 2340 /* Construct the frame command */ 2341 v = GEM_MIF_FRAME_WRITE | 2342 (phy << GEM_MIF_PHY_SHIFT) | 2343 (reg << GEM_MIF_REG_SHIFT) | 2344 (val & GEM_MIF_FRAME_DATA); 2345 2346 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 2347 for (n = 0; n < 100; n++) { 2348 DELAY(1); 2349 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 2350 if (v & GEM_MIF_FRAME_TA0) 2351 return; 2352 } 2353 2354 printf("%s: mii_write timeout\n", device_xname(sc->sc_dev)); 2355 } 2356 2357 static void 2358 gem_mii_statchg(device_t self) 2359 { 2360 struct gem_softc *sc = device_private(self); 2361 #ifdef GEM_DEBUG 2362 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 2363 #endif 2364 2365 #ifdef GEM_DEBUG 2366 if (sc->sc_debug) 2367 printf("gem_mii_statchg: status change: phy = %d\n", 2368 sc->sc_phys[instance]); 2369 #endif 2370 gem_statuschange(sc); 2371 } 2372 2373 /* 2374 * Common status change for gem_mii_statchg() and gem_pint() 2375 */ 2376 void 2377 gem_statuschange(struct gem_softc* sc) 2378 { 2379 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2380 bus_space_tag_t t = sc->sc_bustag; 2381 bus_space_handle_t mac = sc->sc_h1; 2382 int gigabit; 2383 u_int32_t rxcfg, txcfg, v; 2384 2385 if ((sc->sc_mii.mii_media_status & IFM_ACTIVE) != 0 && 2386 IFM_SUBTYPE(sc->sc_mii.mii_media_active) != IFM_NONE) 2387 sc->sc_flags |= GEM_LINK; 2388 else 2389 sc->sc_flags &= ~GEM_LINK; 2390 2391 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 2392 gigabit = 1; 2393 else 2394 gigabit = 0; 2395 2396 /* 2397 * The configuration done here corresponds to the steps F) and 2398 * G) and as far as enabling of RX and TX MAC goes also step H) 2399 * of the initialization sequence outlined in section 3.2.1 of 2400 * the GEM Gigabit Ethernet ASIC Specification. 2401 */ 2402 2403 rxcfg = bus_space_read_4(t, mac, GEM_MAC_RX_CONFIG); 2404 rxcfg &= ~(GEM_MAC_RX_CARR_EXTEND | GEM_MAC_RX_ENABLE); 2405 txcfg = GEM_MAC_TX_ENA_IPG0 | GEM_MAC_TX_NGU | GEM_MAC_TX_NGU_LIMIT; 2406 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 2407 txcfg |= GEM_MAC_TX_IGN_CARRIER | GEM_MAC_TX_IGN_COLLIS; 2408 else if (gigabit) { 2409 rxcfg |= GEM_MAC_RX_CARR_EXTEND; 2410 txcfg |= GEM_MAC_RX_CARR_EXTEND; 2411 } 2412 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0); 2413 bus_space_barrier(t, mac, GEM_MAC_TX_CONFIG, 4, 2414 BUS_SPACE_BARRIER_WRITE); 2415 if (!gem_bitwait(sc, mac, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)) 2416 aprint_normal_dev(sc->sc_dev, "cannot disable TX MAC\n"); 2417 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, txcfg); 2418 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, 0); 2419 bus_space_barrier(t, mac, GEM_MAC_RX_CONFIG, 4, 2420 BUS_SPACE_BARRIER_WRITE); 2421 if (!gem_bitwait(sc, mac, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)) 2422 aprint_normal_dev(sc->sc_dev, "cannot disable RX MAC\n"); 2423 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, rxcfg); 2424 2425 v = bus_space_read_4(t, mac, GEM_MAC_CONTROL_CONFIG) & 2426 ~(GEM_MAC_CC_RX_PAUSE | GEM_MAC_CC_TX_PAUSE); 2427 bus_space_write_4(t, mac, GEM_MAC_CONTROL_CONFIG, v); 2428 2429 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) == 0 && 2430 gigabit != 0) 2431 bus_space_write_4(t, mac, GEM_MAC_SLOT_TIME, 2432 GEM_MAC_SLOT_TIME_CARR_EXTEND); 2433 else 2434 bus_space_write_4(t, mac, GEM_MAC_SLOT_TIME, 2435 GEM_MAC_SLOT_TIME_NORMAL); 2436 2437 /* XIF Configuration */ 2438 if (sc->sc_flags & GEM_LINK) 2439 v = GEM_MAC_XIF_LINK_LED; 2440 else 2441 v = 0; 2442 v |= GEM_MAC_XIF_TX_MII_ENA; 2443 2444 /* If an external transceiver is connected, enable its MII drivers */ 2445 sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG); 2446 if ((sc->sc_flags &(GEM_SERDES | GEM_SERIAL)) == 0) { 2447 if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) { 2448 /* External MII needs echo disable if half duplex. */ 2449 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & 2450 IFM_FDX) != 0) 2451 /* turn on full duplex LED */ 2452 v |= GEM_MAC_XIF_FDPLX_LED; 2453 else 2454 /* half duplex -- disable echo */ 2455 v |= GEM_MAC_XIF_ECHO_DISABL; 2456 if (gigabit) 2457 v |= GEM_MAC_XIF_GMII_MODE; 2458 else 2459 v &= ~GEM_MAC_XIF_GMII_MODE; 2460 } else 2461 /* Internal MII needs buf enable */ 2462 v |= GEM_MAC_XIF_MII_BUF_ENA; 2463 } else { 2464 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 2465 v |= GEM_MAC_XIF_FDPLX_LED; 2466 v |= GEM_MAC_XIF_GMII_MODE; 2467 } 2468 bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v); 2469 2470 if ((ifp->if_flags & IFF_RUNNING) != 0 && 2471 (sc->sc_flags & GEM_LINK) != 0) { 2472 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 2473 txcfg | GEM_MAC_TX_ENABLE); 2474 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, 2475 rxcfg | GEM_MAC_RX_ENABLE); 2476 } 2477 } 2478 2479 int 2480 gem_ser_mediachange(struct ifnet *ifp) 2481 { 2482 struct gem_softc *sc = ifp->if_softc; 2483 u_int s, t; 2484 2485 if (IFM_TYPE(sc->sc_mii.mii_media.ifm_media) != IFM_ETHER) 2486 return EINVAL; 2487 2488 s = IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media); 2489 if (s == IFM_AUTO) { 2490 if (sc->sc_mii_media != s) { 2491 #ifdef GEM_DEBUG 2492 aprint_debug_dev(sc->sc_dev, "setting media to auto\n"); 2493 #endif 2494 sc->sc_mii_media = s; 2495 if (ifp->if_flags & IFF_UP) { 2496 gem_pcs_stop(sc, 0); 2497 gem_pcs_start(sc); 2498 } 2499 } 2500 return 0; 2501 } 2502 if (s == IFM_1000_SX) { 2503 t = IFM_OPTIONS(sc->sc_mii.mii_media.ifm_media); 2504 if (t == IFM_FDX || t == IFM_HDX) { 2505 if (sc->sc_mii_media != t) { 2506 sc->sc_mii_media = t; 2507 #ifdef GEM_DEBUG 2508 aprint_debug_dev(sc->sc_dev, 2509 "setting media to 1000baseSX-%s\n", 2510 t == IFM_FDX ? "FDX" : "HDX"); 2511 #endif 2512 if (ifp->if_flags & IFF_UP) { 2513 gem_pcs_stop(sc, 0); 2514 gem_pcs_start(sc); 2515 } 2516 } 2517 return 0; 2518 } 2519 } 2520 return EINVAL; 2521 } 2522 2523 void 2524 gem_ser_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2525 { 2526 struct gem_softc *sc = ifp->if_softc; 2527 2528 if ((ifp->if_flags & IFF_UP) == 0) 2529 return; 2530 ifmr->ifm_active = sc->sc_mii.mii_media_active; 2531 ifmr->ifm_status = sc->sc_mii.mii_media_status; 2532 } 2533 2534 static int 2535 gem_ifflags_cb(struct ethercom *ec) 2536 { 2537 struct ifnet *ifp = &ec->ec_if; 2538 struct gem_softc *sc = ifp->if_softc; 2539 int change = ifp->if_flags ^ sc->sc_if_flags; 2540 2541 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 2542 return ENETRESET; 2543 else if ((change & IFF_PROMISC) != 0) 2544 gem_setladrf(sc); 2545 return 0; 2546 } 2547 2548 /* 2549 * Process an ioctl request. 2550 */ 2551 int 2552 gem_ioctl(struct ifnet *ifp, unsigned long cmd, void *data) 2553 { 2554 struct gem_softc *sc = ifp->if_softc; 2555 int s, error = 0; 2556 2557 s = splnet(); 2558 2559 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2560 error = 0; 2561 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 2562 ; 2563 else if (ifp->if_flags & IFF_RUNNING) { 2564 /* 2565 * Multicast list has changed; set the hardware filter 2566 * accordingly. 2567 */ 2568 gem_setladrf(sc); 2569 } 2570 } 2571 2572 /* Try to get things going again */ 2573 if (ifp->if_flags & IFF_UP) 2574 gem_start(ifp); 2575 splx(s); 2576 return (error); 2577 } 2578 2579 static void 2580 gem_inten(struct gem_softc *sc) 2581 { 2582 bus_space_tag_t t = sc->sc_bustag; 2583 bus_space_handle_t h = sc->sc_h1; 2584 uint32_t v; 2585 2586 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 2587 v = GEM_INTR_PCS; 2588 else 2589 v = GEM_INTR_MIF; 2590 bus_space_write_4(t, h, GEM_INTMASK, 2591 ~(GEM_INTR_TX_INTME | 2592 GEM_INTR_TX_EMPTY | 2593 GEM_INTR_TX_MAC | 2594 GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF| 2595 GEM_INTR_RX_TAG_ERR | GEM_INTR_MAC_CONTROL| 2596 GEM_INTR_BERR | v)); 2597 } 2598 2599 bool 2600 gem_resume(device_t self, const pmf_qual_t *qual) 2601 { 2602 struct gem_softc *sc = device_private(self); 2603 2604 gem_inten(sc); 2605 2606 return true; 2607 } 2608 2609 bool 2610 gem_suspend(device_t self, const pmf_qual_t *qual) 2611 { 2612 struct gem_softc *sc = device_private(self); 2613 bus_space_tag_t t = sc->sc_bustag; 2614 bus_space_handle_t h = sc->sc_h1; 2615 2616 bus_space_write_4(t, h, GEM_INTMASK, ~(uint32_t)0); 2617 2618 return true; 2619 } 2620 2621 bool 2622 gem_shutdown(device_t self, int howto) 2623 { 2624 struct gem_softc *sc = device_private(self); 2625 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2626 2627 gem_stop(ifp, 1); 2628 2629 return true; 2630 } 2631 2632 /* 2633 * Set up the logical address filter. 2634 */ 2635 void 2636 gem_setladrf(struct gem_softc *sc) 2637 { 2638 struct ethercom *ec = &sc->sc_ethercom; 2639 struct ifnet *ifp = &ec->ec_if; 2640 struct ether_multi *enm; 2641 struct ether_multistep step; 2642 bus_space_tag_t t = sc->sc_bustag; 2643 bus_space_handle_t h = sc->sc_h1; 2644 u_int32_t crc; 2645 u_int32_t hash[16]; 2646 u_int32_t v; 2647 int i; 2648 2649 /* Get current RX configuration */ 2650 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 2651 2652 /* 2653 * Turn off promiscuous mode, promiscuous group mode (all multicast), 2654 * and hash filter. Depending on the case, the right bit will be 2655 * enabled. 2656 */ 2657 v &= ~(GEM_MAC_RX_PROMISCUOUS|GEM_MAC_RX_HASH_FILTER| 2658 GEM_MAC_RX_PROMISC_GRP); 2659 2660 if ((ifp->if_flags & IFF_PROMISC) != 0) { 2661 /* Turn on promiscuous mode */ 2662 v |= GEM_MAC_RX_PROMISCUOUS; 2663 ifp->if_flags |= IFF_ALLMULTI; 2664 goto chipit; 2665 } 2666 2667 /* 2668 * Set up multicast address filter by passing all multicast addresses 2669 * through a crc generator, and then using the high order 8 bits as an 2670 * index into the 256 bit logical address filter. The high order 4 2671 * bits selects the word, while the other 4 bits select the bit within 2672 * the word (where bit 0 is the MSB). 2673 */ 2674 2675 /* Clear hash table */ 2676 memset(hash, 0, sizeof(hash)); 2677 2678 ETHER_FIRST_MULTI(step, ec, enm); 2679 while (enm != NULL) { 2680 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2681 /* 2682 * We must listen to a range of multicast addresses. 2683 * For now, just accept all multicasts, rather than 2684 * trying to set only those filter bits needed to match 2685 * the range. (At this time, the only use of address 2686 * ranges is for IP multicast routing, for which the 2687 * range is big enough to require all bits set.) 2688 * XXX should use the address filters for this 2689 */ 2690 ifp->if_flags |= IFF_ALLMULTI; 2691 v |= GEM_MAC_RX_PROMISC_GRP; 2692 goto chipit; 2693 } 2694 2695 /* Get the LE CRC32 of the address */ 2696 crc = ether_crc32_le(enm->enm_addrlo, sizeof(enm->enm_addrlo)); 2697 2698 /* Just want the 8 most significant bits. */ 2699 crc >>= 24; 2700 2701 /* Set the corresponding bit in the filter. */ 2702 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 2703 2704 ETHER_NEXT_MULTI(step, enm); 2705 } 2706 2707 v |= GEM_MAC_RX_HASH_FILTER; 2708 ifp->if_flags &= ~IFF_ALLMULTI; 2709 2710 /* Now load the hash table into the chip (if we are using it) */ 2711 for (i = 0; i < 16; i++) { 2712 bus_space_write_4(t, h, 2713 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1-GEM_MAC_HASH0), 2714 hash[i]); 2715 } 2716 2717 chipit: 2718 sc->sc_if_flags = ifp->if_flags; 2719 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 2720 } 2721
Indexes created Mon Sep 22 21:09:42 GMT 2025