gem.c revision 1.97
1 /* $NetBSD: gem.c,v 1.97 2011/05/22 11:19:23 jdc Exp $ */ 2 3 /* 4 * 5 * Copyright (C) 2001 Eduardo Horvath. 6 * Copyright (c) 2001-2003 Thomas Moestl 7 * All rights reserved. 8 * 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 */ 32 33 /* 34 * Driver for Apple GMAC, Sun ERI and Sun GEM Ethernet controllers 35 * See `GEM Gigabit Ethernet ASIC Specification' 36 * http://www.sun.com/processors/manuals/ge.pdf 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: gem.c,v 1.97 2011/05/22 11:19:23 jdc Exp $"); 41 42 #include "opt_inet.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/callout.h> 47 #include <sys/mbuf.h> 48 #include <sys/syslog.h> 49 #include <sys/malloc.h> 50 #include <sys/kernel.h> 51 #include <sys/socket.h> 52 #include <sys/ioctl.h> 53 #include <sys/errno.h> 54 #include <sys/device.h> 55 56 #include <machine/endian.h> 57 58 #include <net/if.h> 59 #include <net/if_dl.h> 60 #include <net/if_media.h> 61 #include <net/if_ether.h> 62 63 #ifdef INET 64 #include <netinet/in.h> 65 #include <netinet/in_systm.h> 66 #include <netinet/in_var.h> 67 #include <netinet/ip.h> 68 #include <netinet/tcp.h> 69 #include <netinet/udp.h> 70 #endif 71 72 #include <net/bpf.h> 73 74 #include <sys/bus.h> 75 #include <sys/intr.h> 76 77 #include <dev/mii/mii.h> 78 #include <dev/mii/miivar.h> 79 #include <dev/mii/mii_bitbang.h> 80 81 #include <dev/ic/gemreg.h> 82 #include <dev/ic/gemvar.h> 83 84 #define TRIES 10000 85 86 static void gem_inten(struct gem_softc *); 87 static void gem_start(struct ifnet *); 88 static void gem_stop(struct ifnet *, int); 89 int gem_ioctl(struct ifnet *, u_long, void *); 90 void gem_tick(void *); 91 void gem_watchdog(struct ifnet *); 92 void gem_pcs_start(struct gem_softc *sc); 93 void gem_pcs_stop(struct gem_softc *sc, int); 94 int gem_init(struct ifnet *); 95 void gem_init_regs(struct gem_softc *sc); 96 static int gem_ringsize(int sz); 97 static int gem_meminit(struct gem_softc *); 98 void gem_mifinit(struct gem_softc *); 99 static int gem_bitwait(struct gem_softc *sc, bus_space_handle_t, int, 100 u_int32_t, u_int32_t); 101 void gem_reset(struct gem_softc *); 102 int gem_reset_rx(struct gem_softc *sc); 103 static void gem_reset_rxdma(struct gem_softc *sc); 104 static void gem_rx_common(struct gem_softc *sc); 105 int gem_reset_tx(struct gem_softc *sc); 106 int gem_disable_rx(struct gem_softc *sc); 107 int gem_disable_tx(struct gem_softc *sc); 108 static void gem_rxdrain(struct gem_softc *sc); 109 int gem_add_rxbuf(struct gem_softc *sc, int idx); 110 void gem_setladrf(struct gem_softc *); 111 112 /* MII methods & callbacks */ 113 static int gem_mii_readreg(device_t, int, int); 114 static void gem_mii_writereg(device_t, int, int, int); 115 static void gem_mii_statchg(device_t); 116 117 static int gem_ifflags_cb(struct ethercom *); 118 119 void gem_statuschange(struct gem_softc *); 120 121 int gem_ser_mediachange(struct ifnet *); 122 void gem_ser_mediastatus(struct ifnet *, struct ifmediareq *); 123 124 static void gem_partial_detach(struct gem_softc *, enum gem_attach_stage); 125 126 struct mbuf *gem_get(struct gem_softc *, int, int); 127 int gem_put(struct gem_softc *, int, struct mbuf *); 128 void gem_read(struct gem_softc *, int, int); 129 int gem_pint(struct gem_softc *); 130 int gem_eint(struct gem_softc *, u_int); 131 int gem_rint(struct gem_softc *); 132 int gem_tint(struct gem_softc *); 133 void gem_power(int, void *); 134 135 #ifdef GEM_DEBUG 136 static void gem_txsoft_print(const struct gem_softc *, int, int); 137 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \ 138 printf x 139 #else 140 #define DPRINTF(sc, x) /* nothing */ 141 #endif 142 143 #define ETHER_MIN_TX (ETHERMIN + sizeof(struct ether_header)) 144 145 int 146 gem_detach(struct gem_softc *sc, int flags) 147 { 148 int i; 149 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 150 bus_space_tag_t t = sc->sc_bustag; 151 bus_space_handle_t h = sc->sc_h1; 152 153 /* 154 * Free any resources we've allocated during the attach. 155 * Do this in reverse order and fall through. 156 */ 157 switch (sc->sc_att_stage) { 158 case GEM_ATT_BACKEND_2: 159 case GEM_ATT_BACKEND_1: 160 case GEM_ATT_FINISHED: 161 bus_space_write_4(t, h, GEM_INTMASK, ~(uint32_t)0); 162 gem_stop(&sc->sc_ethercom.ec_if, 1); 163 164 #ifdef GEM_COUNTERS 165 for (i = __arraycount(sc->sc_ev_rxhist); --i >= 0; ) 166 evcnt_detach(&sc->sc_ev_rxhist[i]); 167 evcnt_detach(&sc->sc_ev_rxnobuf); 168 evcnt_detach(&sc->sc_ev_rxfull); 169 evcnt_detach(&sc->sc_ev_rxint); 170 evcnt_detach(&sc->sc_ev_txint); 171 #endif 172 evcnt_detach(&sc->sc_ev_intr); 173 174 #if NRND > 0 175 rnd_detach_source(&sc->rnd_source); 176 #endif 177 ether_ifdetach(ifp); 178 if_detach(ifp); 179 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 180 181 callout_destroy(&sc->sc_tick_ch); 182 183 /*FALLTHROUGH*/ 184 case GEM_ATT_MII: 185 sc->sc_att_stage = GEM_ATT_MII; 186 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 187 /*FALLTHROUGH*/ 188 case GEM_ATT_7: 189 for (i = 0; i < GEM_NRXDESC; i++) { 190 if (sc->sc_rxsoft[i].rxs_dmamap != NULL) 191 bus_dmamap_destroy(sc->sc_dmatag, 192 sc->sc_rxsoft[i].rxs_dmamap); 193 } 194 /*FALLTHROUGH*/ 195 case GEM_ATT_6: 196 for (i = 0; i < GEM_TXQUEUELEN; i++) { 197 if (sc->sc_txsoft[i].txs_dmamap != NULL) 198 bus_dmamap_destroy(sc->sc_dmatag, 199 sc->sc_txsoft[i].txs_dmamap); 200 } 201 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap); 202 /*FALLTHROUGH*/ 203 case GEM_ATT_5: 204 bus_dmamap_unload(sc->sc_dmatag, sc->sc_nulldmamap); 205 /*FALLTHROUGH*/ 206 case GEM_ATT_4: 207 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_nulldmamap); 208 /*FALLTHROUGH*/ 209 case GEM_ATT_3: 210 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap); 211 /*FALLTHROUGH*/ 212 case GEM_ATT_2: 213 bus_dmamem_unmap(sc->sc_dmatag, sc->sc_control_data, 214 sizeof(struct gem_control_data)); 215 /*FALLTHROUGH*/ 216 case GEM_ATT_1: 217 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg); 218 /*FALLTHROUGH*/ 219 case GEM_ATT_0: 220 sc->sc_att_stage = GEM_ATT_0; 221 /*FALLTHROUGH*/ 222 case GEM_ATT_BACKEND_0: 223 break; 224 } 225 return 0; 226 } 227 228 static void 229 gem_partial_detach(struct gem_softc *sc, enum gem_attach_stage stage) 230 { 231 cfattach_t ca = device_cfattach(sc->sc_dev); 232 233 sc->sc_att_stage = stage; 234 (*ca->ca_detach)(sc->sc_dev, 0); 235 } 236 237 /* 238 * gem_attach: 239 * 240 * Attach a Gem interface to the system. 241 */ 242 void 243 gem_attach(struct gem_softc *sc, const uint8_t *enaddr) 244 { 245 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 246 struct mii_data *mii = &sc->sc_mii; 247 bus_space_tag_t t = sc->sc_bustag; 248 bus_space_handle_t h = sc->sc_h1; 249 struct ifmedia_entry *ifm; 250 int i, error, phyaddr; 251 u_int32_t v; 252 char *nullbuf; 253 254 /* Make sure the chip is stopped. */ 255 ifp->if_softc = sc; 256 gem_reset(sc); 257 258 /* 259 * Allocate the control data structures, and create and load the 260 * DMA map for it. gem_control_data is 9216 bytes, we have space for 261 * the padding buffer in the bus_dmamem_alloc()'d memory. 262 */ 263 if ((error = bus_dmamem_alloc(sc->sc_dmatag, 264 sizeof(struct gem_control_data) + ETHER_MIN_TX, PAGE_SIZE, 265 0, &sc->sc_cdseg, 1, &sc->sc_cdnseg, 0)) != 0) { 266 aprint_error_dev(sc->sc_dev, 267 "unable to allocate control data, error = %d\n", 268 error); 269 gem_partial_detach(sc, GEM_ATT_0); 270 return; 271 } 272 273 /* XXX should map this in with correct endianness */ 274 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg, 275 sizeof(struct gem_control_data), (void **)&sc->sc_control_data, 276 BUS_DMA_COHERENT)) != 0) { 277 aprint_error_dev(sc->sc_dev, 278 "unable to map control data, error = %d\n", error); 279 gem_partial_detach(sc, GEM_ATT_1); 280 return; 281 } 282 283 nullbuf = 284 (char *)sc->sc_control_data + sizeof(struct gem_control_data); 285 286 if ((error = bus_dmamap_create(sc->sc_dmatag, 287 sizeof(struct gem_control_data), 1, 288 sizeof(struct gem_control_data), 0, 0, &sc->sc_cddmamap)) != 0) { 289 aprint_error_dev(sc->sc_dev, 290 "unable to create control data DMA map, error = %d\n", 291 error); 292 gem_partial_detach(sc, GEM_ATT_2); 293 return; 294 } 295 296 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap, 297 sc->sc_control_data, sizeof(struct gem_control_data), NULL, 298 0)) != 0) { 299 aprint_error_dev(sc->sc_dev, 300 "unable to load control data DMA map, error = %d\n", 301 error); 302 gem_partial_detach(sc, GEM_ATT_3); 303 return; 304 } 305 306 memset(nullbuf, 0, ETHER_MIN_TX); 307 if ((error = bus_dmamap_create(sc->sc_dmatag, 308 ETHER_MIN_TX, 1, ETHER_MIN_TX, 0, 0, &sc->sc_nulldmamap)) != 0) { 309 aprint_error_dev(sc->sc_dev, 310 "unable to create padding DMA map, error = %d\n", error); 311 gem_partial_detach(sc, GEM_ATT_4); 312 return; 313 } 314 315 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_nulldmamap, 316 nullbuf, ETHER_MIN_TX, NULL, 0)) != 0) { 317 aprint_error_dev(sc->sc_dev, 318 "unable to load padding DMA map, error = %d\n", error); 319 gem_partial_detach(sc, GEM_ATT_5); 320 return; 321 } 322 323 bus_dmamap_sync(sc->sc_dmatag, sc->sc_nulldmamap, 0, ETHER_MIN_TX, 324 BUS_DMASYNC_PREWRITE); 325 326 /* 327 * Initialize the transmit job descriptors. 328 */ 329 SIMPLEQ_INIT(&sc->sc_txfreeq); 330 SIMPLEQ_INIT(&sc->sc_txdirtyq); 331 332 /* 333 * Create the transmit buffer DMA maps. 334 */ 335 for (i = 0; i < GEM_TXQUEUELEN; i++) { 336 struct gem_txsoft *txs; 337 338 txs = &sc->sc_txsoft[i]; 339 txs->txs_mbuf = NULL; 340 if ((error = bus_dmamap_create(sc->sc_dmatag, 341 ETHER_MAX_LEN_JUMBO, GEM_NTXSEGS, 342 ETHER_MAX_LEN_JUMBO, 0, 0, 343 &txs->txs_dmamap)) != 0) { 344 aprint_error_dev(sc->sc_dev, 345 "unable to create tx DMA map %d, error = %d\n", 346 i, error); 347 gem_partial_detach(sc, GEM_ATT_6); 348 return; 349 } 350 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 351 } 352 353 /* 354 * Create the receive buffer DMA maps. 355 */ 356 for (i = 0; i < GEM_NRXDESC; i++) { 357 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, 358 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) { 359 aprint_error_dev(sc->sc_dev, 360 "unable to create rx DMA map %d, error = %d\n", 361 i, error); 362 gem_partial_detach(sc, GEM_ATT_7); 363 return; 364 } 365 sc->sc_rxsoft[i].rxs_mbuf = NULL; 366 } 367 368 /* Initialize ifmedia structures and MII info */ 369 mii->mii_ifp = ifp; 370 mii->mii_readreg = gem_mii_readreg; 371 mii->mii_writereg = gem_mii_writereg; 372 mii->mii_statchg = gem_mii_statchg; 373 374 sc->sc_ethercom.ec_mii = mii; 375 376 /* 377 * Initialization based on `GEM Gigabit Ethernet ASIC Specification' 378 * Section 3.2.1 `Initialization Sequence'. 379 * However, we can't assume SERDES or Serialink if neither 380 * GEM_MIF_CONFIG_MDI0 nor GEM_MIF_CONFIG_MDI1 are set 381 * being set, as both are set on Sun X1141A (with SERDES). So, 382 * we rely on our bus attachment setting GEM_SERDES or GEM_SERIAL. 383 * Also, for variants that report 2 PHY's, we prefer the external 384 * PHY over the internal PHY, so we look for that first. 385 */ 386 gem_mifinit(sc); 387 388 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) { 389 ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange, 390 ether_mediastatus); 391 /* Look for external PHY */ 392 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) { 393 sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL; 394 bus_space_write_4(t, h, GEM_MIF_CONFIG, 395 sc->sc_mif_config); 396 switch (sc->sc_variant) { 397 case GEM_SUN_ERI: 398 phyaddr = GEM_PHYAD_EXTERNAL; 399 break; 400 default: 401 phyaddr = MII_PHY_ANY; 402 break; 403 } 404 mii_attach(sc->sc_dev, mii, 0xffffffff, phyaddr, 405 MII_OFFSET_ANY, MIIF_FORCEANEG); 406 } 407 #ifdef GEM_DEBUG 408 else 409 aprint_debug_dev(sc->sc_dev, "using external PHY\n"); 410 #endif 411 /* Look for internal PHY if no external PHY was found */ 412 if (LIST_EMPTY(&mii->mii_phys) && 413 sc->sc_mif_config & GEM_MIF_CONFIG_MDI0) { 414 sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL; 415 bus_space_write_4(t, h, GEM_MIF_CONFIG, 416 sc->sc_mif_config); 417 switch (sc->sc_variant) { 418 case GEM_SUN_ERI: 419 case GEM_APPLE_K2_GMAC: 420 phyaddr = GEM_PHYAD_INTERNAL; 421 break; 422 case GEM_APPLE_GMAC: 423 phyaddr = GEM_PHYAD_EXTERNAL; 424 break; 425 default: 426 phyaddr = MII_PHY_ANY; 427 break; 428 } 429 mii_attach(sc->sc_dev, mii, 0xffffffff, phyaddr, 430 MII_OFFSET_ANY, MIIF_FORCEANEG); 431 #ifdef GEM_DEBUG 432 if (!LIST_EMPTY(&mii->mii_phys)) 433 aprint_debug_dev(sc->sc_dev, 434 "using internal PHY\n"); 435 #endif 436 } 437 if (LIST_EMPTY(&mii->mii_phys)) { 438 /* No PHY attached */ 439 aprint_error_dev(sc->sc_dev, 440 "PHY probe failed\n"); 441 gem_partial_detach(sc, GEM_ATT_MII); 442 return; 443 } else { 444 struct mii_softc *child; 445 446 /* 447 * Walk along the list of attached MII devices and 448 * establish an `MII instance' to `PHY number' 449 * mapping. 450 */ 451 LIST_FOREACH(child, &mii->mii_phys, mii_list) { 452 /* 453 * Note: we support just one PHY: the internal 454 * or external MII is already selected for us 455 * by the GEM_MIF_CONFIG register. 456 */ 457 if (child->mii_phy > 1 || child->mii_inst > 0) { 458 aprint_error_dev(sc->sc_dev, 459 "cannot accommodate MII device" 460 " %s at PHY %d, instance %d\n", 461 device_xname(child->mii_dev), 462 child->mii_phy, child->mii_inst); 463 continue; 464 } 465 sc->sc_phys[child->mii_inst] = child->mii_phy; 466 } 467 468 if (sc->sc_variant != GEM_SUN_ERI) 469 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 470 GEM_MII_DATAPATH_MII); 471 472 /* 473 * XXX - we can really do the following ONLY if the 474 * PHY indeed has the auto negotiation capability!! 475 */ 476 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 477 } 478 } else { 479 ifmedia_init(&mii->mii_media, IFM_IMASK, gem_ser_mediachange, 480 gem_ser_mediastatus); 481 /* SERDES or Serialink */ 482 if (sc->sc_flags & GEM_SERDES) { 483 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 484 GEM_MII_DATAPATH_SERDES); 485 } else { 486 sc->sc_flags |= GEM_SERIAL; 487 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 488 GEM_MII_DATAPATH_SERIAL); 489 } 490 491 aprint_normal_dev(sc->sc_dev, "using external PCS %s: ", 492 sc->sc_flags & GEM_SERDES ? "SERDES" : "Serialink"); 493 494 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO, 0, NULL); 495 /* Check for FDX and HDX capabilities */ 496 sc->sc_mii_anar = bus_space_read_4(t, h, GEM_MII_ANAR); 497 if (sc->sc_mii_anar & GEM_MII_ANEG_FUL_DUPLX) { 498 ifmedia_add(&sc->sc_mii.mii_media, 499 IFM_ETHER|IFM_1000_SX|IFM_MANUAL|IFM_FDX, 0, NULL); 500 aprint_normal("1000baseSX-FDX, "); 501 } 502 if (sc->sc_mii_anar & GEM_MII_ANEG_HLF_DUPLX) { 503 ifmedia_add(&sc->sc_mii.mii_media, 504 IFM_ETHER|IFM_1000_SX|IFM_MANUAL|IFM_HDX, 0, NULL); 505 aprint_normal("1000baseSX-HDX, "); 506 } 507 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 508 sc->sc_mii_media = IFM_AUTO; 509 aprint_normal("auto\n"); 510 511 gem_pcs_stop(sc, 1); 512 } 513 514 /* 515 * From this point forward, the attachment cannot fail. A failure 516 * before this point releases all resources that may have been 517 * allocated. 518 */ 519 520 /* Announce ourselves. */ 521 aprint_normal_dev(sc->sc_dev, "Ethernet address %s", 522 ether_sprintf(enaddr)); 523 524 /* Get RX FIFO size */ 525 sc->sc_rxfifosize = 64 * 526 bus_space_read_4(t, h, GEM_RX_FIFO_SIZE); 527 aprint_normal(", %uKB RX fifo", sc->sc_rxfifosize / 1024); 528 529 /* Get TX FIFO size */ 530 v = bus_space_read_4(t, h, GEM_TX_FIFO_SIZE); 531 aprint_normal(", %uKB TX fifo\n", v / 16); 532 533 /* Initialize ifnet structure. */ 534 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 535 ifp->if_softc = sc; 536 ifp->if_flags = 537 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 538 sc->sc_if_flags = ifp->if_flags; 539 #if 0 540 /* 541 * The GEM hardware supports basic TCP checksum offloading only. 542 * Several (all?) revisions (Sun rev. 01 and Apple rev. 00 and 80) 543 * have bugs in the receive checksum, so don't enable it for now. 544 */ 545 if ((GEM_IS_SUN(sc) && sc->sc_chiprev != 1) || 546 (GEM_IS_APPLE(sc) && 547 (sc->sc_chiprev != 0 && sc->sc_chiprev != 0x80))) 548 ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Rx; 549 #endif 550 ifp->if_capabilities |= IFCAP_CSUM_TCPv4_Tx; 551 ifp->if_start = gem_start; 552 ifp->if_ioctl = gem_ioctl; 553 ifp->if_watchdog = gem_watchdog; 554 ifp->if_stop = gem_stop; 555 ifp->if_init = gem_init; 556 IFQ_SET_READY(&ifp->if_snd); 557 558 /* 559 * If we support GigE media, we support jumbo frames too. 560 * Unless we are Apple. 561 */ 562 TAILQ_FOREACH(ifm, &sc->sc_mii.mii_media.ifm_list, ifm_list) { 563 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_T || 564 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_SX || 565 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_LX || 566 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_CX) { 567 if (!GEM_IS_APPLE(sc)) 568 sc->sc_ethercom.ec_capabilities 569 |= ETHERCAP_JUMBO_MTU; 570 sc->sc_flags |= GEM_GIGABIT; 571 break; 572 } 573 } 574 575 /* claim 802.1q capability */ 576 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 577 578 /* Attach the interface. */ 579 if_attach(ifp); 580 ether_ifattach(ifp, enaddr); 581 ether_set_ifflags_cb(&sc->sc_ethercom, gem_ifflags_cb); 582 583 #if NRND > 0 584 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 585 RND_TYPE_NET, 0); 586 #endif 587 588 evcnt_attach_dynamic(&sc->sc_ev_intr, EVCNT_TYPE_INTR, 589 NULL, device_xname(sc->sc_dev), "interrupts"); 590 #ifdef GEM_COUNTERS 591 evcnt_attach_dynamic(&sc->sc_ev_txint, EVCNT_TYPE_INTR, 592 &sc->sc_ev_intr, device_xname(sc->sc_dev), "tx interrupts"); 593 evcnt_attach_dynamic(&sc->sc_ev_rxint, EVCNT_TYPE_INTR, 594 &sc->sc_ev_intr, device_xname(sc->sc_dev), "rx interrupts"); 595 evcnt_attach_dynamic(&sc->sc_ev_rxfull, EVCNT_TYPE_INTR, 596 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx ring full"); 597 evcnt_attach_dynamic(&sc->sc_ev_rxnobuf, EVCNT_TYPE_INTR, 598 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx malloc failure"); 599 evcnt_attach_dynamic(&sc->sc_ev_rxhist[0], EVCNT_TYPE_INTR, 600 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 0desc"); 601 evcnt_attach_dynamic(&sc->sc_ev_rxhist[1], EVCNT_TYPE_INTR, 602 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 1desc"); 603 evcnt_attach_dynamic(&sc->sc_ev_rxhist[2], EVCNT_TYPE_INTR, 604 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 2desc"); 605 evcnt_attach_dynamic(&sc->sc_ev_rxhist[3], EVCNT_TYPE_INTR, 606 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx 3desc"); 607 evcnt_attach_dynamic(&sc->sc_ev_rxhist[4], EVCNT_TYPE_INTR, 608 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >3desc"); 609 evcnt_attach_dynamic(&sc->sc_ev_rxhist[5], EVCNT_TYPE_INTR, 610 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >7desc"); 611 evcnt_attach_dynamic(&sc->sc_ev_rxhist[6], EVCNT_TYPE_INTR, 612 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >15desc"); 613 evcnt_attach_dynamic(&sc->sc_ev_rxhist[7], EVCNT_TYPE_INTR, 614 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >31desc"); 615 evcnt_attach_dynamic(&sc->sc_ev_rxhist[8], EVCNT_TYPE_INTR, 616 &sc->sc_ev_rxint, device_xname(sc->sc_dev), "rx >63desc"); 617 #endif 618 619 callout_init(&sc->sc_tick_ch, 0); 620 621 sc->sc_att_stage = GEM_ATT_FINISHED; 622 623 return; 624 } 625 626 void 627 gem_tick(void *arg) 628 { 629 struct gem_softc *sc = arg; 630 int s; 631 632 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) { 633 /* 634 * We have to reset everything if we failed to get a 635 * PCS interrupt. Restarting the callout is handled 636 * in gem_pcs_start(). 637 */ 638 gem_init(&sc->sc_ethercom.ec_if); 639 } else { 640 s = splnet(); 641 mii_tick(&sc->sc_mii); 642 splx(s); 643 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 644 } 645 } 646 647 static int 648 gem_bitwait(struct gem_softc *sc, bus_space_handle_t h, int r, u_int32_t clr, u_int32_t set) 649 { 650 int i; 651 u_int32_t reg; 652 653 for (i = TRIES; i--; DELAY(100)) { 654 reg = bus_space_read_4(sc->sc_bustag, h, r); 655 if ((reg & clr) == 0 && (reg & set) == set) 656 return (1); 657 } 658 return (0); 659 } 660 661 void 662 gem_reset(struct gem_softc *sc) 663 { 664 bus_space_tag_t t = sc->sc_bustag; 665 bus_space_handle_t h = sc->sc_h2; 666 int s; 667 668 s = splnet(); 669 DPRINTF(sc, ("%s: gem_reset\n", device_xname(sc->sc_dev))); 670 gem_reset_rx(sc); 671 gem_reset_tx(sc); 672 673 /* Do a full reset */ 674 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX|GEM_RESET_TX); 675 if (!gem_bitwait(sc, h, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0)) 676 aprint_error_dev(sc->sc_dev, "cannot reset device\n"); 677 splx(s); 678 } 679 680 681 /* 682 * gem_rxdrain: 683 * 684 * Drain the receive queue. 685 */ 686 static void 687 gem_rxdrain(struct gem_softc *sc) 688 { 689 struct gem_rxsoft *rxs; 690 int i; 691 692 for (i = 0; i < GEM_NRXDESC; i++) { 693 rxs = &sc->sc_rxsoft[i]; 694 if (rxs->rxs_mbuf != NULL) { 695 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 696 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 697 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 698 m_freem(rxs->rxs_mbuf); 699 rxs->rxs_mbuf = NULL; 700 } 701 } 702 } 703 704 /* 705 * Reset the whole thing. 706 */ 707 static void 708 gem_stop(struct ifnet *ifp, int disable) 709 { 710 struct gem_softc *sc = ifp->if_softc; 711 struct gem_txsoft *txs; 712 713 DPRINTF(sc, ("%s: gem_stop\n", device_xname(sc->sc_dev))); 714 715 callout_halt(&sc->sc_tick_ch, NULL); 716 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 717 gem_pcs_stop(sc, disable); 718 else 719 mii_down(&sc->sc_mii); 720 721 /* XXX - Should we reset these instead? */ 722 gem_disable_tx(sc); 723 gem_disable_rx(sc); 724 725 /* 726 * Release any queued transmit buffers. 727 */ 728 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 729 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 730 if (txs->txs_mbuf != NULL) { 731 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 0, 732 txs->txs_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 733 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 734 m_freem(txs->txs_mbuf); 735 txs->txs_mbuf = NULL; 736 } 737 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 738 } 739 740 /* 741 * Mark the interface down and cancel the watchdog timer. 742 */ 743 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 744 sc->sc_if_flags = ifp->if_flags; 745 ifp->if_timer = 0; 746 747 if (disable) 748 gem_rxdrain(sc); 749 } 750 751 752 /* 753 * Reset the receiver 754 */ 755 int 756 gem_reset_rx(struct gem_softc *sc) 757 { 758 bus_space_tag_t t = sc->sc_bustag; 759 bus_space_handle_t h = sc->sc_h1, h2 = sc->sc_h2; 760 761 /* 762 * Resetting while DMA is in progress can cause a bus hang, so we 763 * disable DMA first. 764 */ 765 gem_disable_rx(sc); 766 bus_space_write_4(t, h, GEM_RX_CONFIG, 0); 767 bus_space_barrier(t, h, GEM_RX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 768 /* Wait till it finishes */ 769 if (!gem_bitwait(sc, h, GEM_RX_CONFIG, 1, 0)) 770 aprint_error_dev(sc->sc_dev, "cannot disable read dma\n"); 771 772 /* Finally, reset the ERX */ 773 bus_space_write_4(t, h2, GEM_RESET, GEM_RESET_RX); 774 bus_space_barrier(t, h, GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE); 775 /* Wait till it finishes */ 776 if (!gem_bitwait(sc, h2, GEM_RESET, GEM_RESET_RX, 0)) { 777 aprint_error_dev(sc->sc_dev, "cannot reset receiver\n"); 778 return (1); 779 } 780 return (0); 781 } 782 783 784 /* 785 * Reset the receiver DMA engine. 786 * 787 * Intended to be used in case of GEM_INTR_RX_TAG_ERR, GEM_MAC_RX_OVERFLOW 788 * etc in order to reset the receiver DMA engine only and not do a full 789 * reset which amongst others also downs the link and clears the FIFOs. 790 */ 791 static void 792 gem_reset_rxdma(struct gem_softc *sc) 793 { 794 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 795 bus_space_tag_t t = sc->sc_bustag; 796 bus_space_handle_t h = sc->sc_h1; 797 int i; 798 799 if (gem_reset_rx(sc) != 0) { 800 gem_init(ifp); 801 return; 802 } 803 for (i = 0; i < GEM_NRXDESC; i++) 804 if (sc->sc_rxsoft[i].rxs_mbuf != NULL) 805 GEM_UPDATE_RXDESC(sc, i); 806 sc->sc_rxptr = 0; 807 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE); 808 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD); 809 810 /* Reprogram Descriptor Ring Base Addresses */ 811 /* NOTE: we use only 32-bit DMA addresses here. */ 812 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0); 813 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 814 815 /* Redo ERX Configuration */ 816 gem_rx_common(sc); 817 818 /* Give the reciever a swift kick */ 819 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC - 4); 820 } 821 822 /* 823 * Common RX configuration for gem_init() and gem_reset_rxdma(). 824 */ 825 static void 826 gem_rx_common(struct gem_softc *sc) 827 { 828 bus_space_tag_t t = sc->sc_bustag; 829 bus_space_handle_t h = sc->sc_h1; 830 u_int32_t v; 831 832 /* Encode Receive Descriptor ring size: four possible values */ 833 v = gem_ringsize(GEM_NRXDESC /*XXX*/); 834 835 /* Set receive h/w checksum offset */ 836 #ifdef INET 837 v |= (ETHER_HDR_LEN + sizeof(struct ip) + 838 ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 839 ETHER_VLAN_ENCAP_LEN : 0)) << GEM_RX_CONFIG_CXM_START_SHFT; 840 #endif 841 842 /* Enable RX DMA */ 843 bus_space_write_4(t, h, GEM_RX_CONFIG, 844 v | (GEM_THRSH_1024 << GEM_RX_CONFIG_FIFO_THRS_SHIFT) | 845 (2 << GEM_RX_CONFIG_FBOFF_SHFT) | GEM_RX_CONFIG_RXDMA_EN); 846 847 /* 848 * The following value is for an OFF Threshold of about 3/4 full 849 * and an ON Threshold of 1/4 full. 850 */ 851 bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH, 852 (3 * sc->sc_rxfifosize / 256) | 853 ((sc->sc_rxfifosize / 256) << 12)); 854 bus_space_write_4(t, h, GEM_RX_BLANKING, 855 (6 << GEM_RX_BLANKING_TIME_SHIFT) | 6); 856 } 857 858 /* 859 * Reset the transmitter 860 */ 861 int 862 gem_reset_tx(struct gem_softc *sc) 863 { 864 bus_space_tag_t t = sc->sc_bustag; 865 bus_space_handle_t h = sc->sc_h1, h2 = sc->sc_h2; 866 867 /* 868 * Resetting while DMA is in progress can cause a bus hang, so we 869 * disable DMA first. 870 */ 871 gem_disable_tx(sc); 872 bus_space_write_4(t, h, GEM_TX_CONFIG, 0); 873 bus_space_barrier(t, h, GEM_TX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 874 /* Wait till it finishes */ 875 if (!gem_bitwait(sc, h, GEM_TX_CONFIG, 1, 0)) 876 aprint_error_dev(sc->sc_dev, "cannot disable read dma\n"); 877 /* Wait 5ms extra. */ 878 delay(5000); 879 880 /* Finally, reset the ETX */ 881 bus_space_write_4(t, h2, GEM_RESET, GEM_RESET_TX); 882 bus_space_barrier(t, h, GEM_RESET, 4, BUS_SPACE_BARRIER_WRITE); 883 /* Wait till it finishes */ 884 if (!gem_bitwait(sc, h2, GEM_RESET, GEM_RESET_TX, 0)) { 885 aprint_error_dev(sc->sc_dev, "cannot reset receiver\n"); 886 return (1); 887 } 888 return (0); 889 } 890 891 /* 892 * disable receiver. 893 */ 894 int 895 gem_disable_rx(struct gem_softc *sc) 896 { 897 bus_space_tag_t t = sc->sc_bustag; 898 bus_space_handle_t h = sc->sc_h1; 899 u_int32_t cfg; 900 901 /* Flip the enable bit */ 902 cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 903 cfg &= ~GEM_MAC_RX_ENABLE; 904 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg); 905 bus_space_barrier(t, h, GEM_MAC_RX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 906 /* Wait for it to finish */ 907 return (gem_bitwait(sc, h, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)); 908 } 909 910 /* 911 * disable transmitter. 912 */ 913 int 914 gem_disable_tx(struct gem_softc *sc) 915 { 916 bus_space_tag_t t = sc->sc_bustag; 917 bus_space_handle_t h = sc->sc_h1; 918 u_int32_t cfg; 919 920 /* Flip the enable bit */ 921 cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG); 922 cfg &= ~GEM_MAC_TX_ENABLE; 923 bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg); 924 bus_space_barrier(t, h, GEM_MAC_TX_CONFIG, 4, BUS_SPACE_BARRIER_WRITE); 925 /* Wait for it to finish */ 926 return (gem_bitwait(sc, h, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)); 927 } 928 929 /* 930 * Initialize interface. 931 */ 932 int 933 gem_meminit(struct gem_softc *sc) 934 { 935 struct gem_rxsoft *rxs; 936 int i, error; 937 938 /* 939 * Initialize the transmit descriptor ring. 940 */ 941 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs)); 942 for (i = 0; i < GEM_NTXDESC; i++) { 943 sc->sc_txdescs[i].gd_flags = 0; 944 sc->sc_txdescs[i].gd_addr = 0; 945 } 946 GEM_CDTXSYNC(sc, 0, GEM_NTXDESC, 947 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 948 sc->sc_txfree = GEM_NTXDESC-1; 949 sc->sc_txnext = 0; 950 sc->sc_txwin = 0; 951 952 /* 953 * Initialize the receive descriptor and receive job 954 * descriptor rings. 955 */ 956 for (i = 0; i < GEM_NRXDESC; i++) { 957 rxs = &sc->sc_rxsoft[i]; 958 if (rxs->rxs_mbuf == NULL) { 959 if ((error = gem_add_rxbuf(sc, i)) != 0) { 960 aprint_error_dev(sc->sc_dev, 961 "unable to allocate or map rx " 962 "buffer %d, error = %d\n", 963 i, error); 964 /* 965 * XXX Should attempt to run with fewer receive 966 * XXX buffers instead of just failing. 967 */ 968 gem_rxdrain(sc); 969 return (1); 970 } 971 } else 972 GEM_INIT_RXDESC(sc, i); 973 } 974 sc->sc_rxptr = 0; 975 sc->sc_meminited = 1; 976 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE); 977 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD); 978 979 return (0); 980 } 981 982 static int 983 gem_ringsize(int sz) 984 { 985 switch (sz) { 986 case 32: 987 return GEM_RING_SZ_32; 988 case 64: 989 return GEM_RING_SZ_64; 990 case 128: 991 return GEM_RING_SZ_128; 992 case 256: 993 return GEM_RING_SZ_256; 994 case 512: 995 return GEM_RING_SZ_512; 996 case 1024: 997 return GEM_RING_SZ_1024; 998 case 2048: 999 return GEM_RING_SZ_2048; 1000 case 4096: 1001 return GEM_RING_SZ_4096; 1002 case 8192: 1003 return GEM_RING_SZ_8192; 1004 default: 1005 printf("gem: invalid Receive Descriptor ring size %d\n", sz); 1006 return GEM_RING_SZ_32; 1007 } 1008 } 1009 1010 1011 /* 1012 * Start PCS 1013 */ 1014 void 1015 gem_pcs_start(struct gem_softc *sc) 1016 { 1017 bus_space_tag_t t = sc->sc_bustag; 1018 bus_space_handle_t h = sc->sc_h1; 1019 uint32_t v; 1020 1021 #ifdef GEM_DEBUG 1022 aprint_debug_dev(sc->sc_dev, "gem_pcs_start()\n"); 1023 #endif 1024 1025 /* 1026 * Set up. We must disable the MII before modifying the 1027 * GEM_MII_ANAR register 1028 */ 1029 if (sc->sc_flags & GEM_SERDES) { 1030 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 1031 GEM_MII_DATAPATH_SERDES); 1032 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 1033 GEM_MII_SLINK_LOOPBACK); 1034 } else { 1035 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 1036 GEM_MII_DATAPATH_SERIAL); 1037 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 0); 1038 } 1039 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 1040 v = bus_space_read_4(t, h, GEM_MII_ANAR); 1041 v |= (GEM_MII_ANEG_SYM_PAUSE | GEM_MII_ANEG_ASYM_PAUSE); 1042 if (sc->sc_mii_media == IFM_AUTO) 1043 v |= (GEM_MII_ANEG_FUL_DUPLX | GEM_MII_ANEG_HLF_DUPLX); 1044 else if (sc->sc_mii_media == IFM_FDX) { 1045 v |= GEM_MII_ANEG_FUL_DUPLX; 1046 v &= ~GEM_MII_ANEG_HLF_DUPLX; 1047 } else if (sc->sc_mii_media == IFM_HDX) { 1048 v &= ~GEM_MII_ANEG_FUL_DUPLX; 1049 v |= GEM_MII_ANEG_HLF_DUPLX; 1050 } 1051 1052 /* Configure link. */ 1053 bus_space_write_4(t, h, GEM_MII_ANAR, v); 1054 bus_space_write_4(t, h, GEM_MII_CONTROL, 1055 GEM_MII_CONTROL_AUTONEG | GEM_MII_CONTROL_RAN); 1056 bus_space_write_4(t, h, GEM_MII_CONFIG, GEM_MII_CONFIG_ENABLE); 1057 gem_bitwait(sc, h, GEM_MII_STATUS, 0, GEM_MII_STATUS_ANEG_CPT); 1058 1059 /* Start the 10 second timer */ 1060 callout_reset(&sc->sc_tick_ch, hz * 10, gem_tick, sc); 1061 } 1062 1063 /* 1064 * Stop PCS 1065 */ 1066 void 1067 gem_pcs_stop(struct gem_softc *sc, int disable) 1068 { 1069 bus_space_tag_t t = sc->sc_bustag; 1070 bus_space_handle_t h = sc->sc_h1; 1071 1072 #ifdef GEM_DEBUG 1073 aprint_debug_dev(sc->sc_dev, "gem_pcs_stop()\n"); 1074 #endif 1075 1076 /* Tell link partner that we're going away */ 1077 bus_space_write_4(t, h, GEM_MII_ANAR, GEM_MII_ANEG_RF); 1078 1079 /* 1080 * Disable PCS MII. The documentation suggests that setting 1081 * GEM_MII_CONFIG_ENABLE to zero and then restarting auto- 1082 * negotiation will shut down the link. However, it appears 1083 * that we also need to unset the datapath mode. 1084 */ 1085 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 1086 bus_space_write_4(t, h, GEM_MII_CONTROL, 1087 GEM_MII_CONTROL_AUTONEG | GEM_MII_CONTROL_RAN); 1088 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, GEM_MII_DATAPATH_MII); 1089 bus_space_write_4(t, h, GEM_MII_CONFIG, 0); 1090 1091 if (disable) { 1092 if (sc->sc_flags & GEM_SERDES) 1093 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 1094 GEM_MII_SLINK_POWER_OFF); 1095 else 1096 bus_space_write_4(t, h, GEM_MII_SLINK_CONTROL, 1097 GEM_MII_SLINK_LOOPBACK | GEM_MII_SLINK_POWER_OFF); 1098 } 1099 1100 sc->sc_flags &= ~GEM_LINK; 1101 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_NONE; 1102 sc->sc_mii.mii_media_status = IFM_AVALID; 1103 } 1104 1105 1106 /* 1107 * Initialization of interface; set up initialization block 1108 * and transmit/receive descriptor rings. 1109 */ 1110 int 1111 gem_init(struct ifnet *ifp) 1112 { 1113 struct gem_softc *sc = ifp->if_softc; 1114 bus_space_tag_t t = sc->sc_bustag; 1115 bus_space_handle_t h = sc->sc_h1; 1116 int rc = 0, s; 1117 u_int max_frame_size; 1118 u_int32_t v; 1119 1120 s = splnet(); 1121 1122 DPRINTF(sc, ("%s: gem_init: calling stop\n", device_xname(sc->sc_dev))); 1123 /* 1124 * Initialization sequence. The numbered steps below correspond 1125 * to the sequence outlined in section 6.3.5.1 in the Ethernet 1126 * Channel Engine manual (part of the PCIO manual). 1127 * See also the STP2002-STQ document from Sun Microsystems. 1128 */ 1129 1130 /* step 1 & 2. Reset the Ethernet Channel */ 1131 gem_stop(ifp, 0); 1132 gem_reset(sc); 1133 DPRINTF(sc, ("%s: gem_init: restarting\n", device_xname(sc->sc_dev))); 1134 1135 /* Re-initialize the MIF */ 1136 gem_mifinit(sc); 1137 1138 /* Set up correct datapath for non-SERDES/Serialink */ 1139 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0 && 1140 sc->sc_variant != GEM_SUN_ERI) 1141 bus_space_write_4(t, h, GEM_MII_DATAPATH_MODE, 1142 GEM_MII_DATAPATH_MII); 1143 1144 /* Call MI reset function if any */ 1145 if (sc->sc_hwreset) 1146 (*sc->sc_hwreset)(sc); 1147 1148 /* step 3. Setup data structures in host memory */ 1149 if (gem_meminit(sc) != 0) 1150 return 1; 1151 1152 /* step 4. TX MAC registers & counters */ 1153 gem_init_regs(sc); 1154 max_frame_size = max(sc->sc_ethercom.ec_if.if_mtu, ETHERMTU); 1155 max_frame_size += ETHER_HDR_LEN + ETHER_CRC_LEN; 1156 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) 1157 max_frame_size += ETHER_VLAN_ENCAP_LEN; 1158 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 1159 max_frame_size|/* burst size */(0x2000<<16)); 1160 1161 /* step 5. RX MAC registers & counters */ 1162 gem_setladrf(sc); 1163 1164 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 1165 /* NOTE: we use only 32-bit DMA addresses here. */ 1166 bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 0); 1167 bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); 1168 1169 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0); 1170 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); 1171 1172 /* step 8. Global Configuration & Interrupt Mask */ 1173 gem_inten(sc); 1174 bus_space_write_4(t, h, GEM_MAC_RX_MASK, 1175 GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT); 1176 bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXX */ 1177 bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 1178 GEM_MAC_PAUSED | GEM_MAC_PAUSE | GEM_MAC_RESUME); 1179 1180 /* step 9. ETX Configuration: use mostly default values */ 1181 1182 /* Enable TX DMA */ 1183 v = gem_ringsize(GEM_NTXDESC /*XXX*/); 1184 bus_space_write_4(t, h, GEM_TX_CONFIG, 1185 v | GEM_TX_CONFIG_TXDMA_EN | 1186 (((sc->sc_flags & GEM_GIGABIT ? 0x4FF : 0x100) << 10) & 1187 GEM_TX_CONFIG_TXFIFO_TH)); 1188 bus_space_write_4(t, h, GEM_TX_KICK, sc->sc_txnext); 1189 1190 /* step 10. ERX Configuration */ 1191 gem_rx_common(sc); 1192 1193 /* step 11. Configure Media */ 1194 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0 && 1195 (rc = mii_ifmedia_change(&sc->sc_mii)) != 0) 1196 goto out; 1197 1198 /* step 12. RX_MAC Configuration Register */ 1199 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 1200 v |= GEM_MAC_RX_ENABLE | GEM_MAC_RX_STRIP_CRC; 1201 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 1202 1203 /* step 14. Issue Transmit Pending command */ 1204 1205 /* Call MI initialization function if any */ 1206 if (sc->sc_hwinit) 1207 (*sc->sc_hwinit)(sc); 1208 1209 1210 /* step 15. Give the reciever a swift kick */ 1211 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4); 1212 1213 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 1214 /* Configure PCS */ 1215 gem_pcs_start(sc); 1216 else 1217 /* Start the one second timer. */ 1218 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 1219 1220 sc->sc_flags &= ~GEM_LINK; 1221 ifp->if_flags |= IFF_RUNNING; 1222 ifp->if_flags &= ~IFF_OACTIVE; 1223 ifp->if_timer = 0; 1224 sc->sc_if_flags = ifp->if_flags; 1225 out: 1226 splx(s); 1227 1228 return (0); 1229 } 1230 1231 void 1232 gem_init_regs(struct gem_softc *sc) 1233 { 1234 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1235 bus_space_tag_t t = sc->sc_bustag; 1236 bus_space_handle_t h = sc->sc_h1; 1237 const u_char *laddr = CLLADDR(ifp->if_sadl); 1238 u_int32_t v; 1239 1240 /* These regs are not cleared on reset */ 1241 if (!sc->sc_inited) { 1242 1243 /* Load recommended values */ 1244 bus_space_write_4(t, h, GEM_MAC_IPG0, 0x00); 1245 bus_space_write_4(t, h, GEM_MAC_IPG1, 0x08); 1246 bus_space_write_4(t, h, GEM_MAC_IPG2, 0x04); 1247 1248 bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); 1249 /* Max frame and max burst size */ 1250 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, 1251 ETHER_MAX_LEN | (0x2000<<16)); 1252 1253 bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x07); 1254 bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x04); 1255 bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10); 1256 bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088); 1257 bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED, 1258 ((laddr[5]<<8)|laddr[4])&0x3ff); 1259 1260 /* Secondary MAC addr set to 0:0:0:0:0:0 */ 1261 bus_space_write_4(t, h, GEM_MAC_ADDR3, 0); 1262 bus_space_write_4(t, h, GEM_MAC_ADDR4, 0); 1263 bus_space_write_4(t, h, GEM_MAC_ADDR5, 0); 1264 1265 /* MAC control addr set to 01:80:c2:00:00:01 */ 1266 bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001); 1267 bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200); 1268 bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180); 1269 1270 /* MAC filter addr set to 0:0:0:0:0:0 */ 1271 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0); 1272 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0); 1273 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0); 1274 1275 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0); 1276 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0); 1277 1278 sc->sc_inited = 1; 1279 } 1280 1281 /* Counters need to be zeroed */ 1282 bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0); 1283 bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0); 1284 bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0); 1285 bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0); 1286 bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0); 1287 bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0); 1288 bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0); 1289 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 1290 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 1291 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 1292 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 1293 1294 /* Set XOFF PAUSE time. */ 1295 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); 1296 1297 /* 1298 * Set the internal arbitration to "infinite" bursts of the 1299 * maximum length of 31 * 64 bytes so DMA transfers aren't 1300 * split up in cache line size chunks. This greatly improves 1301 * especially RX performance. 1302 * Enable silicon bug workarounds for the Apple variants. 1303 */ 1304 bus_space_write_4(t, h, GEM_CONFIG, 1305 GEM_CONFIG_TXDMA_LIMIT | GEM_CONFIG_RXDMA_LIMIT | 1306 ((sc->sc_flags & GEM_PCI) ? 1307 GEM_CONFIG_BURST_INF : GEM_CONFIG_BURST_64) | (GEM_IS_APPLE(sc) ? 1308 GEM_CONFIG_RONPAULBIT | GEM_CONFIG_BUG2FIX : 0)); 1309 1310 /* 1311 * Set the station address. 1312 */ 1313 bus_space_write_4(t, h, GEM_MAC_ADDR0, (laddr[4]<<8)|laddr[5]); 1314 bus_space_write_4(t, h, GEM_MAC_ADDR1, (laddr[2]<<8)|laddr[3]); 1315 bus_space_write_4(t, h, GEM_MAC_ADDR2, (laddr[0]<<8)|laddr[1]); 1316 1317 /* 1318 * Enable MII outputs. Enable GMII if there is a gigabit PHY. 1319 */ 1320 sc->sc_mif_config = bus_space_read_4(t, h, GEM_MIF_CONFIG); 1321 v = GEM_MAC_XIF_TX_MII_ENA; 1322 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) { 1323 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) { 1324 v |= GEM_MAC_XIF_FDPLX_LED; 1325 if (sc->sc_flags & GEM_GIGABIT) 1326 v |= GEM_MAC_XIF_GMII_MODE; 1327 } 1328 } else { 1329 v |= GEM_MAC_XIF_GMII_MODE; 1330 } 1331 bus_space_write_4(t, h, GEM_MAC_XIF_CONFIG, v); 1332 } 1333 1334 #ifdef GEM_DEBUG 1335 static void 1336 gem_txsoft_print(const struct gem_softc *sc, int firstdesc, int lastdesc) 1337 { 1338 int i; 1339 1340 for (i = firstdesc;; i = GEM_NEXTTX(i)) { 1341 printf("descriptor %d:\t", i); 1342 printf("gd_flags: 0x%016" PRIx64 "\t", 1343 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags)); 1344 printf("gd_addr: 0x%016" PRIx64 "\n", 1345 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr)); 1346 if (i == lastdesc) 1347 break; 1348 } 1349 } 1350 #endif 1351 1352 static void 1353 gem_start(struct ifnet *ifp) 1354 { 1355 struct gem_softc *sc = ifp->if_softc; 1356 struct mbuf *m0, *m; 1357 struct gem_txsoft *txs; 1358 bus_dmamap_t dmamap; 1359 int error, firsttx, nexttx = -1, lasttx = -1, ofree, seg; 1360 uint64_t flags = 0; 1361 1362 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1363 return; 1364 1365 /* 1366 * Remember the previous number of free descriptors and 1367 * the first descriptor we'll use. 1368 */ 1369 ofree = sc->sc_txfree; 1370 firsttx = sc->sc_txnext; 1371 1372 DPRINTF(sc, ("%s: gem_start: txfree %d, txnext %d\n", 1373 device_xname(sc->sc_dev), ofree, firsttx)); 1374 1375 /* 1376 * Loop through the send queue, setting up transmit descriptors 1377 * until we drain the queue, or use up all available transmit 1378 * descriptors. 1379 */ 1380 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL && 1381 sc->sc_txfree != 0) { 1382 /* 1383 * Grab a packet off the queue. 1384 */ 1385 IFQ_POLL(&ifp->if_snd, m0); 1386 if (m0 == NULL) 1387 break; 1388 m = NULL; 1389 1390 dmamap = txs->txs_dmamap; 1391 1392 /* 1393 * Load the DMA map. If this fails, the packet either 1394 * didn't fit in the alloted number of segments, or we were 1395 * short on resources. In this case, we'll copy and try 1396 * again. 1397 */ 1398 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m0, 1399 BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0 || 1400 (m0->m_pkthdr.len < ETHER_MIN_TX && 1401 dmamap->dm_nsegs == GEM_NTXSEGS)) { 1402 if (m0->m_pkthdr.len > MCLBYTES) { 1403 aprint_error_dev(sc->sc_dev, 1404 "unable to allocate jumbo Tx cluster\n"); 1405 IFQ_DEQUEUE(&ifp->if_snd, m0); 1406 m_freem(m0); 1407 continue; 1408 } 1409 MGETHDR(m, M_DONTWAIT, MT_DATA); 1410 if (m == NULL) { 1411 aprint_error_dev(sc->sc_dev, 1412 "unable to allocate Tx mbuf\n"); 1413 break; 1414 } 1415 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 1416 if (m0->m_pkthdr.len > MHLEN) { 1417 MCLGET(m, M_DONTWAIT); 1418 if ((m->m_flags & M_EXT) == 0) { 1419 aprint_error_dev(sc->sc_dev, 1420 "unable to allocate Tx cluster\n"); 1421 m_freem(m); 1422 break; 1423 } 1424 } 1425 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 1426 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 1427 error = bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, 1428 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1429 if (error) { 1430 aprint_error_dev(sc->sc_dev, 1431 "unable to load Tx buffer, error = %d\n", 1432 error); 1433 break; 1434 } 1435 } 1436 1437 /* 1438 * Ensure we have enough descriptors free to describe 1439 * the packet. 1440 */ 1441 if (dmamap->dm_nsegs > ((m0->m_pkthdr.len < ETHER_MIN_TX) ? 1442 (sc->sc_txfree - 1) : sc->sc_txfree)) { 1443 /* 1444 * Not enough free descriptors to transmit this 1445 * packet. We haven't committed to anything yet, 1446 * so just unload the DMA map, put the packet 1447 * back on the queue, and punt. Notify the upper 1448 * layer that there are no more slots left. 1449 * 1450 * XXX We could allocate an mbuf and copy, but 1451 * XXX it is worth it? 1452 */ 1453 ifp->if_flags |= IFF_OACTIVE; 1454 sc->sc_if_flags = ifp->if_flags; 1455 bus_dmamap_unload(sc->sc_dmatag, dmamap); 1456 if (m != NULL) 1457 m_freem(m); 1458 break; 1459 } 1460 1461 IFQ_DEQUEUE(&ifp->if_snd, m0); 1462 if (m != NULL) { 1463 m_freem(m0); 1464 m0 = m; 1465 } 1466 1467 /* 1468 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 1469 */ 1470 1471 /* Sync the DMA map. */ 1472 bus_dmamap_sync(sc->sc_dmatag, dmamap, 0, dmamap->dm_mapsize, 1473 BUS_DMASYNC_PREWRITE); 1474 1475 /* 1476 * Initialize the transmit descriptors. 1477 */ 1478 for (nexttx = sc->sc_txnext, seg = 0; 1479 seg < dmamap->dm_nsegs; 1480 seg++, nexttx = GEM_NEXTTX(nexttx)) { 1481 1482 /* 1483 * If this is the first descriptor we're 1484 * enqueueing, set the start of packet flag, 1485 * and the checksum stuff if we want the hardware 1486 * to do it. 1487 */ 1488 sc->sc_txdescs[nexttx].gd_addr = 1489 GEM_DMA_WRITE(sc, dmamap->dm_segs[seg].ds_addr); 1490 flags = dmamap->dm_segs[seg].ds_len & GEM_TD_BUFSIZE; 1491 if (nexttx == firsttx) { 1492 flags |= GEM_TD_START_OF_PACKET; 1493 if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) { 1494 sc->sc_txwin = 0; 1495 flags |= GEM_TD_INTERRUPT_ME; 1496 } 1497 1498 #ifdef INET 1499 /* h/w checksum */ 1500 if (ifp->if_csum_flags_tx & M_CSUM_TCPv4 && 1501 m0->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1502 struct ether_header *eh; 1503 uint16_t offset, start; 1504 1505 eh = mtod(m0, struct ether_header *); 1506 switch (ntohs(eh->ether_type)) { 1507 case ETHERTYPE_IP: 1508 start = ETHER_HDR_LEN; 1509 break; 1510 case ETHERTYPE_VLAN: 1511 start = ETHER_HDR_LEN + 1512 ETHER_VLAN_ENCAP_LEN; 1513 break; 1514 default: 1515 /* unsupported, drop it */ 1516 m_free(m0); 1517 continue; 1518 } 1519 start += M_CSUM_DATA_IPv4_IPHL(m0->m_pkthdr.csum_data); 1520 offset = M_CSUM_DATA_IPv4_OFFSET(m0->m_pkthdr.csum_data) + start; 1521 flags |= (start << 1522 GEM_TD_CXSUM_STARTSHFT) | 1523 (offset << 1524 GEM_TD_CXSUM_STUFFSHFT) | 1525 GEM_TD_CXSUM_ENABLE; 1526 } 1527 #endif 1528 } 1529 if (seg == dmamap->dm_nsegs - 1) { 1530 flags |= GEM_TD_END_OF_PACKET; 1531 } else { 1532 /* last flag set outside of loop */ 1533 sc->sc_txdescs[nexttx].gd_flags = 1534 GEM_DMA_WRITE(sc, flags); 1535 } 1536 lasttx = nexttx; 1537 } 1538 if (m0->m_pkthdr.len < ETHER_MIN_TX) { 1539 /* add padding buffer at end of chain */ 1540 flags &= ~GEM_TD_END_OF_PACKET; 1541 sc->sc_txdescs[lasttx].gd_flags = 1542 GEM_DMA_WRITE(sc, flags); 1543 1544 sc->sc_txdescs[nexttx].gd_addr = 1545 GEM_DMA_WRITE(sc, 1546 sc->sc_nulldmamap->dm_segs[0].ds_addr); 1547 flags = ((ETHER_MIN_TX - m0->m_pkthdr.len) & 1548 GEM_TD_BUFSIZE) | GEM_TD_END_OF_PACKET; 1549 lasttx = nexttx; 1550 nexttx = GEM_NEXTTX(nexttx); 1551 seg++; 1552 } 1553 sc->sc_txdescs[lasttx].gd_flags = GEM_DMA_WRITE(sc, flags); 1554 1555 KASSERT(lasttx != -1); 1556 1557 /* 1558 * Store a pointer to the packet so we can free it later, 1559 * and remember what txdirty will be once the packet is 1560 * done. 1561 */ 1562 txs->txs_mbuf = m0; 1563 txs->txs_firstdesc = sc->sc_txnext; 1564 txs->txs_lastdesc = lasttx; 1565 txs->txs_ndescs = seg; 1566 1567 #ifdef GEM_DEBUG 1568 if (ifp->if_flags & IFF_DEBUG) { 1569 printf(" gem_start %p transmit chain:\n", txs); 1570 gem_txsoft_print(sc, txs->txs_firstdesc, 1571 txs->txs_lastdesc); 1572 } 1573 #endif 1574 1575 /* Sync the descriptors we're using. */ 1576 GEM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndescs, 1577 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1578 1579 /* Advance the tx pointer. */ 1580 sc->sc_txfree -= txs->txs_ndescs; 1581 sc->sc_txnext = nexttx; 1582 1583 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1584 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1585 1586 /* 1587 * Pass the packet to any BPF listeners. 1588 */ 1589 bpf_mtap(ifp, m0); 1590 } 1591 1592 if (txs == NULL || sc->sc_txfree == 0) { 1593 /* No more slots left; notify upper layer. */ 1594 ifp->if_flags |= IFF_OACTIVE; 1595 sc->sc_if_flags = ifp->if_flags; 1596 } 1597 1598 if (sc->sc_txfree != ofree) { 1599 DPRINTF(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n", 1600 device_xname(sc->sc_dev), lasttx, firsttx)); 1601 /* 1602 * The entire packet chain is set up. 1603 * Kick the transmitter. 1604 */ 1605 DPRINTF(sc, ("%s: gem_start: kicking tx %d\n", 1606 device_xname(sc->sc_dev), nexttx)); 1607 bus_space_write_4(sc->sc_bustag, sc->sc_h1, GEM_TX_KICK, 1608 sc->sc_txnext); 1609 1610 /* Set a watchdog timer in case the chip flakes out. */ 1611 ifp->if_timer = 5; 1612 DPRINTF(sc, ("%s: gem_start: watchdog %d\n", 1613 device_xname(sc->sc_dev), ifp->if_timer)); 1614 } 1615 } 1616 1617 /* 1618 * Transmit interrupt. 1619 */ 1620 int 1621 gem_tint(struct gem_softc *sc) 1622 { 1623 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1624 bus_space_tag_t t = sc->sc_bustag; 1625 bus_space_handle_t mac = sc->sc_h1; 1626 struct gem_txsoft *txs; 1627 int txlast; 1628 int progress = 0; 1629 u_int32_t v; 1630 1631 DPRINTF(sc, ("%s: gem_tint\n", device_xname(sc->sc_dev))); 1632 1633 /* Unload collision counters ... */ 1634 v = bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) + 1635 bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT); 1636 ifp->if_collisions += v + 1637 bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) + 1638 bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT); 1639 ifp->if_oerrors += v; 1640 1641 /* ... then clear the hardware counters. */ 1642 bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0); 1643 bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0); 1644 bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0); 1645 bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0); 1646 1647 /* 1648 * Go through our Tx list and free mbufs for those 1649 * frames that have been transmitted. 1650 */ 1651 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1652 /* 1653 * In theory, we could harvest some descriptors before 1654 * the ring is empty, but that's a bit complicated. 1655 * 1656 * GEM_TX_COMPLETION points to the last descriptor 1657 * processed +1. 1658 * 1659 * Let's assume that the NIC writes back to the Tx 1660 * descriptors before it updates the completion 1661 * register. If the NIC has posted writes to the 1662 * Tx descriptors, PCI ordering requires that the 1663 * posted writes flush to RAM before the register-read 1664 * finishes. So let's read the completion register, 1665 * before syncing the descriptors, so that we 1666 * examine Tx descriptors that are at least as 1667 * current as the completion register. 1668 */ 1669 txlast = bus_space_read_4(t, mac, GEM_TX_COMPLETION); 1670 DPRINTF(sc, 1671 ("gem_tint: txs->txs_lastdesc = %d, txlast = %d\n", 1672 txs->txs_lastdesc, txlast)); 1673 if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1674 if (txlast >= txs->txs_firstdesc && 1675 txlast <= txs->txs_lastdesc) 1676 break; 1677 } else if (txlast >= txs->txs_firstdesc || 1678 txlast <= txs->txs_lastdesc) 1679 break; 1680 1681 GEM_CDTXSYNC(sc, txs->txs_firstdesc, txs->txs_ndescs, 1682 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1683 1684 #ifdef GEM_DEBUG /* XXX DMA synchronization? */ 1685 if (ifp->if_flags & IFF_DEBUG) { 1686 printf(" txsoft %p transmit chain:\n", txs); 1687 gem_txsoft_print(sc, txs->txs_firstdesc, 1688 txs->txs_lastdesc); 1689 } 1690 #endif 1691 1692 1693 DPRINTF(sc, ("gem_tint: releasing a desc\n")); 1694 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1695 1696 sc->sc_txfree += txs->txs_ndescs; 1697 1698 bus_dmamap_sync(sc->sc_dmatag, txs->txs_dmamap, 1699 0, txs->txs_dmamap->dm_mapsize, 1700 BUS_DMASYNC_POSTWRITE); 1701 bus_dmamap_unload(sc->sc_dmatag, txs->txs_dmamap); 1702 if (txs->txs_mbuf != NULL) { 1703 m_freem(txs->txs_mbuf); 1704 txs->txs_mbuf = NULL; 1705 } 1706 1707 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1708 1709 ifp->if_opackets++; 1710 progress = 1; 1711 } 1712 1713 #if 0 1714 DPRINTF(sc, ("gem_tint: GEM_TX_STATE_MACHINE %x " 1715 "GEM_TX_DATA_PTR %" PRIx64 "GEM_TX_COMPLETION %" PRIx32 "\n", 1716 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_TX_STATE_MACHINE), 1717 ((uint64_t)bus_space_read_4(sc->sc_bustag, sc->sc_h1, 1718 GEM_TX_DATA_PTR_HI) << 32) | 1719 bus_space_read_4(sc->sc_bustag, sc->sc_h1, 1720 GEM_TX_DATA_PTR_LO), 1721 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_TX_COMPLETION))); 1722 #endif 1723 1724 if (progress) { 1725 if (sc->sc_txfree == GEM_NTXDESC - 1) 1726 sc->sc_txwin = 0; 1727 1728 /* Freed some descriptors, so reset IFF_OACTIVE and restart. */ 1729 ifp->if_flags &= ~IFF_OACTIVE; 1730 sc->sc_if_flags = ifp->if_flags; 1731 ifp->if_timer = SIMPLEQ_EMPTY(&sc->sc_txdirtyq) ? 0 : 5; 1732 gem_start(ifp); 1733 } 1734 DPRINTF(sc, ("%s: gem_tint: watchdog %d\n", 1735 device_xname(sc->sc_dev), ifp->if_timer)); 1736 1737 return (1); 1738 } 1739 1740 /* 1741 * Receive interrupt. 1742 */ 1743 int 1744 gem_rint(struct gem_softc *sc) 1745 { 1746 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1747 bus_space_tag_t t = sc->sc_bustag; 1748 bus_space_handle_t h = sc->sc_h1; 1749 struct gem_rxsoft *rxs; 1750 struct mbuf *m; 1751 u_int64_t rxstat; 1752 u_int32_t rxcomp; 1753 int i, len, progress = 0; 1754 1755 DPRINTF(sc, ("%s: gem_rint\n", device_xname(sc->sc_dev))); 1756 1757 /* 1758 * Ignore spurious interrupt that sometimes occurs before 1759 * we are set up when we network boot. 1760 */ 1761 if (!sc->sc_meminited) 1762 return 1; 1763 1764 /* 1765 * Read the completion register once. This limits 1766 * how long the following loop can execute. 1767 */ 1768 rxcomp = bus_space_read_4(t, h, GEM_RX_COMPLETION); 1769 1770 /* 1771 * XXX Read the lastrx only once at the top for speed. 1772 */ 1773 DPRINTF(sc, ("gem_rint: sc->rxptr %d, complete %d\n", 1774 sc->sc_rxptr, rxcomp)); 1775 1776 /* 1777 * Go into the loop at least once. 1778 */ 1779 for (i = sc->sc_rxptr; i == sc->sc_rxptr || i != rxcomp; 1780 i = GEM_NEXTRX(i)) { 1781 rxs = &sc->sc_rxsoft[i]; 1782 1783 GEM_CDRXSYNC(sc, i, 1784 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1785 1786 rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags); 1787 1788 if (rxstat & GEM_RD_OWN) { 1789 GEM_CDRXSYNC(sc, i, BUS_DMASYNC_PREREAD); 1790 /* 1791 * We have processed all of the receive buffers. 1792 */ 1793 break; 1794 } 1795 1796 progress++; 1797 ifp->if_ipackets++; 1798 1799 if (rxstat & GEM_RD_BAD_CRC) { 1800 ifp->if_ierrors++; 1801 aprint_error_dev(sc->sc_dev, 1802 "receive error: CRC error\n"); 1803 GEM_INIT_RXDESC(sc, i); 1804 continue; 1805 } 1806 1807 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1808 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 1809 #ifdef GEM_DEBUG 1810 if (ifp->if_flags & IFF_DEBUG) { 1811 printf(" rxsoft %p descriptor %d: ", rxs, i); 1812 printf("gd_flags: 0x%016llx\t", (long long) 1813 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags)); 1814 printf("gd_addr: 0x%016llx\n", (long long) 1815 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr)); 1816 } 1817 #endif 1818 1819 /* No errors; receive the packet. */ 1820 len = GEM_RD_BUFLEN(rxstat); 1821 1822 /* 1823 * Allocate a new mbuf cluster. If that fails, we are 1824 * out of memory, and must drop the packet and recycle 1825 * the buffer that's already attached to this descriptor. 1826 */ 1827 m = rxs->rxs_mbuf; 1828 if (gem_add_rxbuf(sc, i) != 0) { 1829 GEM_COUNTER_INCR(sc, sc_ev_rxnobuf); 1830 ifp->if_ierrors++; 1831 GEM_INIT_RXDESC(sc, i); 1832 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 1833 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1834 continue; 1835 } 1836 m->m_data += 2; /* We're already off by two */ 1837 1838 m->m_pkthdr.rcvif = ifp; 1839 m->m_pkthdr.len = m->m_len = len; 1840 1841 /* 1842 * Pass this up to any BPF listeners, but only 1843 * pass it up the stack if it's for us. 1844 */ 1845 bpf_mtap(ifp, m); 1846 1847 #ifdef INET 1848 /* hardware checksum */ 1849 if (ifp->if_csum_flags_rx & M_CSUM_TCPv4) { 1850 struct ether_header *eh; 1851 struct ip *ip; 1852 int32_t hlen, pktlen; 1853 1854 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) { 1855 pktlen = m->m_pkthdr.len - ETHER_HDR_LEN - 1856 ETHER_VLAN_ENCAP_LEN; 1857 eh = (struct ether_header *) (mtod(m, char *) + 1858 ETHER_VLAN_ENCAP_LEN); 1859 } else { 1860 pktlen = m->m_pkthdr.len - ETHER_HDR_LEN; 1861 eh = mtod(m, struct ether_header *); 1862 } 1863 if (ntohs(eh->ether_type) != ETHERTYPE_IP) 1864 goto swcsum; 1865 ip = (struct ip *) ((char *)eh + ETHER_HDR_LEN); 1866 1867 /* IPv4 only */ 1868 if (ip->ip_v != IPVERSION) 1869 goto swcsum; 1870 1871 hlen = ip->ip_hl << 2; 1872 if (hlen < sizeof(struct ip)) 1873 goto swcsum; 1874 1875 /* 1876 * bail if too short, has random trailing garbage, 1877 * truncated, fragment, or has ethernet pad. 1878 */ 1879 if ((ntohs(ip->ip_len) < hlen) || 1880 (ntohs(ip->ip_len) != pktlen) || 1881 (ntohs(ip->ip_off) & (IP_MF | IP_OFFMASK))) 1882 goto swcsum; 1883 1884 switch (ip->ip_p) { 1885 case IPPROTO_TCP: 1886 if (! (ifp->if_csum_flags_rx & M_CSUM_TCPv4)) 1887 goto swcsum; 1888 if (pktlen < (hlen + sizeof(struct tcphdr))) 1889 goto swcsum; 1890 m->m_pkthdr.csum_flags = M_CSUM_TCPv4; 1891 break; 1892 case IPPROTO_UDP: 1893 /* FALLTHROUGH */ 1894 default: 1895 goto swcsum; 1896 } 1897 1898 /* the uncomplemented sum is expected */ 1899 m->m_pkthdr.csum_data = (~rxstat) & GEM_RD_CHECKSUM; 1900 1901 /* if the pkt had ip options, we have to deduct them */ 1902 if (hlen > sizeof(struct ip)) { 1903 uint16_t *opts; 1904 uint32_t optsum, temp; 1905 1906 optsum = 0; 1907 temp = hlen - sizeof(struct ip); 1908 opts = (uint16_t *) ((char *) ip + 1909 sizeof(struct ip)); 1910 1911 while (temp > 1) { 1912 optsum += ntohs(*opts++); 1913 temp -= 2; 1914 } 1915 while (optsum >> 16) 1916 optsum = (optsum >> 16) + 1917 (optsum & 0xffff); 1918 1919 /* Deduct ip opts sum from hwsum. */ 1920 m->m_pkthdr.csum_data += (uint16_t)~optsum; 1921 1922 while (m->m_pkthdr.csum_data >> 16) 1923 m->m_pkthdr.csum_data = 1924 (m->m_pkthdr.csum_data >> 16) + 1925 (m->m_pkthdr.csum_data & 1926 0xffff); 1927 } 1928 1929 m->m_pkthdr.csum_flags |= M_CSUM_DATA | 1930 M_CSUM_NO_PSEUDOHDR; 1931 } else 1932 swcsum: 1933 m->m_pkthdr.csum_flags = 0; 1934 #endif 1935 /* Pass it on. */ 1936 (*ifp->if_input)(ifp, m); 1937 } 1938 1939 if (progress) { 1940 /* Update the receive pointer. */ 1941 if (i == sc->sc_rxptr) { 1942 GEM_COUNTER_INCR(sc, sc_ev_rxfull); 1943 #ifdef GEM_DEBUG 1944 if (ifp->if_flags & IFF_DEBUG) 1945 printf("%s: rint: ring wrap\n", 1946 device_xname(sc->sc_dev)); 1947 #endif 1948 } 1949 sc->sc_rxptr = i; 1950 bus_space_write_4(t, h, GEM_RX_KICK, GEM_PREVRX(i)); 1951 } 1952 #ifdef GEM_COUNTERS 1953 if (progress <= 4) { 1954 GEM_COUNTER_INCR(sc, sc_ev_rxhist[progress]); 1955 } else if (progress < 32) { 1956 if (progress < 16) 1957 GEM_COUNTER_INCR(sc, sc_ev_rxhist[5]); 1958 else 1959 GEM_COUNTER_INCR(sc, sc_ev_rxhist[6]); 1960 1961 } else { 1962 if (progress < 64) 1963 GEM_COUNTER_INCR(sc, sc_ev_rxhist[7]); 1964 else 1965 GEM_COUNTER_INCR(sc, sc_ev_rxhist[8]); 1966 } 1967 #endif 1968 1969 DPRINTF(sc, ("gem_rint: done sc->rxptr %d, complete %d\n", 1970 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION))); 1971 1972 /* Read error counters ... */ 1973 ifp->if_ierrors += 1974 bus_space_read_4(t, h, GEM_MAC_RX_LEN_ERR_CNT) + 1975 bus_space_read_4(t, h, GEM_MAC_RX_ALIGN_ERR) + 1976 bus_space_read_4(t, h, GEM_MAC_RX_CRC_ERR_CNT) + 1977 bus_space_read_4(t, h, GEM_MAC_RX_CODE_VIOL); 1978 1979 /* ... then clear the hardware counters. */ 1980 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0); 1981 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0); 1982 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0); 1983 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0); 1984 1985 return (1); 1986 } 1987 1988 1989 /* 1990 * gem_add_rxbuf: 1991 * 1992 * Add a receive buffer to the indicated descriptor. 1993 */ 1994 int 1995 gem_add_rxbuf(struct gem_softc *sc, int idx) 1996 { 1997 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx]; 1998 struct mbuf *m; 1999 int error; 2000 2001 MGETHDR(m, M_DONTWAIT, MT_DATA); 2002 if (m == NULL) 2003 return (ENOBUFS); 2004 2005 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 2006 MCLGET(m, M_DONTWAIT); 2007 if ((m->m_flags & M_EXT) == 0) { 2008 m_freem(m); 2009 return (ENOBUFS); 2010 } 2011 2012 #ifdef GEM_DEBUG 2013 /* bzero the packet to check DMA */ 2014 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size); 2015 #endif 2016 2017 if (rxs->rxs_mbuf != NULL) 2018 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap); 2019 2020 rxs->rxs_mbuf = m; 2021 2022 error = bus_dmamap_load(sc->sc_dmatag, rxs->rxs_dmamap, 2023 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 2024 BUS_DMA_READ|BUS_DMA_NOWAIT); 2025 if (error) { 2026 aprint_error_dev(sc->sc_dev, 2027 "can't load rx DMA map %d, error = %d\n", idx, error); 2028 panic("gem_add_rxbuf"); /* XXX */ 2029 } 2030 2031 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0, 2032 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 2033 2034 GEM_INIT_RXDESC(sc, idx); 2035 2036 return (0); 2037 } 2038 2039 2040 int 2041 gem_eint(struct gem_softc *sc, u_int status) 2042 { 2043 char bits[128]; 2044 u_int32_t r, v; 2045 2046 if ((status & GEM_INTR_MIF) != 0) { 2047 printf("%s: XXXlink status changed\n", device_xname(sc->sc_dev)); 2048 return (1); 2049 } 2050 2051 if ((status & GEM_INTR_RX_TAG_ERR) != 0) { 2052 gem_reset_rxdma(sc); 2053 return (1); 2054 } 2055 2056 if (status & GEM_INTR_BERR) { 2057 if (sc->sc_flags & GEM_PCI) 2058 r = GEM_ERROR_STATUS; 2059 else 2060 r = GEM_SBUS_ERROR_STATUS; 2061 bus_space_read_4(sc->sc_bustag, sc->sc_h2, r); 2062 v = bus_space_read_4(sc->sc_bustag, sc->sc_h2, r); 2063 aprint_error_dev(sc->sc_dev, "bus error interrupt: 0x%02x\n", 2064 v); 2065 return (1); 2066 } 2067 snprintb(bits, sizeof(bits), GEM_INTR_BITS, status); 2068 printf("%s: status=%s\n", device_xname(sc->sc_dev), bits); 2069 2070 return (1); 2071 } 2072 2073 2074 /* 2075 * PCS interrupts. 2076 * We should receive these when the link status changes, but sometimes 2077 * we don't receive them for link up. We compensate for this in the 2078 * gem_tick() callout. 2079 */ 2080 int 2081 gem_pint(struct gem_softc *sc) 2082 { 2083 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2084 bus_space_tag_t t = sc->sc_bustag; 2085 bus_space_handle_t h = sc->sc_h1; 2086 u_int32_t v, v2; 2087 2088 /* 2089 * Clear the PCS interrupt from GEM_STATUS. The PCS register is 2090 * latched, so we have to read it twice. There is only one bit in 2091 * use, so the value is meaningless. 2092 */ 2093 bus_space_read_4(t, h, GEM_MII_INTERRUP_STATUS); 2094 bus_space_read_4(t, h, GEM_MII_INTERRUP_STATUS); 2095 2096 if ((ifp->if_flags & IFF_UP) == 0) 2097 return 1; 2098 2099 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) == 0) 2100 return 1; 2101 2102 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2103 /* If we see remote fault, our link partner is probably going away */ 2104 if ((v & GEM_MII_STATUS_REM_FLT) != 0) { 2105 gem_bitwait(sc, h, GEM_MII_STATUS, GEM_MII_STATUS_REM_FLT, 0); 2106 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2107 /* Otherwise, we may need to wait after auto-negotiation completes */ 2108 } else if ((v & (GEM_MII_STATUS_LINK_STS | GEM_MII_STATUS_ANEG_CPT)) == 2109 GEM_MII_STATUS_ANEG_CPT) { 2110 gem_bitwait(sc, h, GEM_MII_STATUS, 0, GEM_MII_STATUS_LINK_STS); 2111 v = bus_space_read_4(t, h, GEM_MII_STATUS); 2112 } 2113 if ((v & GEM_MII_STATUS_LINK_STS) != 0) { 2114 if (sc->sc_flags & GEM_LINK) { 2115 return 1; 2116 } 2117 callout_stop(&sc->sc_tick_ch); 2118 v = bus_space_read_4(t, h, GEM_MII_ANAR); 2119 v2 = bus_space_read_4(t, h, GEM_MII_ANLPAR); 2120 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_1000_SX; 2121 sc->sc_mii.mii_media_status = IFM_AVALID | IFM_ACTIVE; 2122 v &= v2; 2123 if (v & GEM_MII_ANEG_FUL_DUPLX) { 2124 sc->sc_mii.mii_media_active |= IFM_FDX; 2125 #ifdef GEM_DEBUG 2126 aprint_debug_dev(sc->sc_dev, "link up: full duplex\n"); 2127 #endif 2128 } else if (v & GEM_MII_ANEG_HLF_DUPLX) { 2129 sc->sc_mii.mii_media_active |= IFM_HDX; 2130 #ifdef GEM_DEBUG 2131 aprint_debug_dev(sc->sc_dev, "link up: half duplex\n"); 2132 #endif 2133 } else { 2134 #ifdef GEM_DEBUG 2135 aprint_debug_dev(sc->sc_dev, "duplex mismatch\n"); 2136 #endif 2137 } 2138 gem_statuschange(sc); 2139 } else { 2140 if ((sc->sc_flags & GEM_LINK) == 0) { 2141 return 1; 2142 } 2143 sc->sc_mii.mii_media_active = IFM_ETHER | IFM_NONE; 2144 sc->sc_mii.mii_media_status = IFM_AVALID; 2145 #ifdef GEM_DEBUG 2146 aprint_debug_dev(sc->sc_dev, "link down\n"); 2147 #endif 2148 gem_statuschange(sc); 2149 2150 /* Start the 10 second timer */ 2151 callout_reset(&sc->sc_tick_ch, hz * 10, gem_tick, sc); 2152 } 2153 return 1; 2154 } 2155 2156 2157 2158 int 2159 gem_intr(void *v) 2160 { 2161 struct gem_softc *sc = v; 2162 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2163 bus_space_tag_t t = sc->sc_bustag; 2164 bus_space_handle_t h = sc->sc_h1; 2165 u_int32_t status; 2166 int r = 0; 2167 #ifdef GEM_DEBUG 2168 char bits[128]; 2169 #endif 2170 2171 /* XXX We should probably mask out interrupts until we're done */ 2172 2173 sc->sc_ev_intr.ev_count++; 2174 2175 status = bus_space_read_4(t, h, GEM_STATUS); 2176 #ifdef GEM_DEBUG 2177 snprintb(bits, sizeof(bits), GEM_INTR_BITS, status); 2178 #endif 2179 DPRINTF(sc, ("%s: gem_intr: cplt 0x%x status %s\n", 2180 device_xname(sc->sc_dev), (status >> 19), bits)); 2181 2182 2183 if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0) 2184 r |= gem_eint(sc, status); 2185 2186 /* We don't bother with GEM_INTR_TX_DONE */ 2187 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) { 2188 GEM_COUNTER_INCR(sc, sc_ev_txint); 2189 r |= gem_tint(sc); 2190 } 2191 2192 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) { 2193 GEM_COUNTER_INCR(sc, sc_ev_rxint); 2194 r |= gem_rint(sc); 2195 } 2196 2197 /* We should eventually do more than just print out error stats. */ 2198 if (status & GEM_INTR_TX_MAC) { 2199 int txstat = bus_space_read_4(t, h, GEM_MAC_TX_STATUS); 2200 if (txstat & ~GEM_MAC_TX_XMIT_DONE) 2201 printf("%s: MAC tx fault, status %x\n", 2202 device_xname(sc->sc_dev), txstat); 2203 if (txstat & (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG)) 2204 gem_init(ifp); 2205 } 2206 if (status & GEM_INTR_RX_MAC) { 2207 int rxstat = bus_space_read_4(t, h, GEM_MAC_RX_STATUS); 2208 /* 2209 * At least with GEM_SUN_GEM and some GEM_SUN_ERI 2210 * revisions GEM_MAC_RX_OVERFLOW happen often due to a 2211 * silicon bug so handle them silently. Moreover, it's 2212 * likely that the receiver has hung so we reset it. 2213 */ 2214 if (rxstat & GEM_MAC_RX_OVERFLOW) { 2215 ifp->if_ierrors++; 2216 gem_reset_rxdma(sc); 2217 } else if (rxstat & ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT)) 2218 printf("%s: MAC rx fault, status 0x%02x\n", 2219 device_xname(sc->sc_dev), rxstat); 2220 } 2221 if (status & GEM_INTR_PCS) { 2222 r |= gem_pint(sc); 2223 } 2224 2225 /* Do we need to do anything with these? 2226 if ((status & GEM_MAC_CONTROL_STATUS) != 0) { 2227 status2 = bus_read_4(sc->sc_res[0], GEM_MAC_CONTROL_STATUS); 2228 if ((status2 & GEM_MAC_PAUSED) != 0) 2229 aprintf_debug_dev(sc->sc_dev, "PAUSE received (%d slots)\n", 2230 GEM_MAC_PAUSE_TIME(status2)); 2231 if ((status2 & GEM_MAC_PAUSE) != 0) 2232 aprintf_debug_dev(sc->sc_dev, "transited to PAUSE state\n"); 2233 if ((status2 & GEM_MAC_RESUME) != 0) 2234 aprintf_debug_dev(sc->sc_dev, "transited to non-PAUSE state\n"); 2235 } 2236 if ((status & GEM_INTR_MIF) != 0) 2237 aprintf_debug_dev(sc->sc_dev, "MIF interrupt\n"); 2238 */ 2239 #if NRND > 0 2240 rnd_add_uint32(&sc->rnd_source, status); 2241 #endif 2242 return (r); 2243 } 2244 2245 2246 void 2247 gem_watchdog(struct ifnet *ifp) 2248 { 2249 struct gem_softc *sc = ifp->if_softc; 2250 2251 DPRINTF(sc, ("gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x " 2252 "GEM_MAC_RX_CONFIG %x\n", 2253 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_RX_CONFIG), 2254 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_MAC_RX_STATUS), 2255 bus_space_read_4(sc->sc_bustag, sc->sc_h1, GEM_MAC_RX_CONFIG))); 2256 2257 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 2258 ++ifp->if_oerrors; 2259 2260 /* Try to get more packets going. */ 2261 gem_start(ifp); 2262 } 2263 2264 /* 2265 * Initialize the MII Management Interface 2266 */ 2267 void 2268 gem_mifinit(struct gem_softc *sc) 2269 { 2270 bus_space_tag_t t = sc->sc_bustag; 2271 bus_space_handle_t mif = sc->sc_h1; 2272 2273 /* Configure the MIF in frame mode */ 2274 sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG); 2275 sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA; 2276 bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config); 2277 } 2278 2279 /* 2280 * MII interface 2281 * 2282 * The GEM MII interface supports at least three different operating modes: 2283 * 2284 * Bitbang mode is implemented using data, clock and output enable registers. 2285 * 2286 * Frame mode is implemented by loading a complete frame into the frame 2287 * register and polling the valid bit for completion. 2288 * 2289 * Polling mode uses the frame register but completion is indicated by 2290 * an interrupt. 2291 * 2292 */ 2293 static int 2294 gem_mii_readreg(device_t self, int phy, int reg) 2295 { 2296 struct gem_softc *sc = device_private(self); 2297 bus_space_tag_t t = sc->sc_bustag; 2298 bus_space_handle_t mif = sc->sc_h1; 2299 int n; 2300 u_int32_t v; 2301 2302 #ifdef GEM_DEBUG1 2303 if (sc->sc_debug) 2304 printf("gem_mii_readreg: PHY %d reg %d\n", phy, reg); 2305 #endif 2306 2307 /* Construct the frame command */ 2308 v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) | 2309 GEM_MIF_FRAME_READ; 2310 2311 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 2312 for (n = 0; n < 100; n++) { 2313 DELAY(1); 2314 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 2315 if (v & GEM_MIF_FRAME_TA0) 2316 return (v & GEM_MIF_FRAME_DATA); 2317 } 2318 2319 printf("%s: mii_read timeout\n", device_xname(sc->sc_dev)); 2320 return (0); 2321 } 2322 2323 static void 2324 gem_mii_writereg(device_t self, int phy, int reg, int val) 2325 { 2326 struct gem_softc *sc = device_private(self); 2327 bus_space_tag_t t = sc->sc_bustag; 2328 bus_space_handle_t mif = sc->sc_h1; 2329 int n; 2330 u_int32_t v; 2331 2332 #ifdef GEM_DEBUG1 2333 if (sc->sc_debug) 2334 printf("gem_mii_writereg: PHY %d reg %d val %x\n", 2335 phy, reg, val); 2336 #endif 2337 2338 /* Construct the frame command */ 2339 v = GEM_MIF_FRAME_WRITE | 2340 (phy << GEM_MIF_PHY_SHIFT) | 2341 (reg << GEM_MIF_REG_SHIFT) | 2342 (val & GEM_MIF_FRAME_DATA); 2343 2344 bus_space_write_4(t, mif, GEM_MIF_FRAME, v); 2345 for (n = 0; n < 100; n++) { 2346 DELAY(1); 2347 v = bus_space_read_4(t, mif, GEM_MIF_FRAME); 2348 if (v & GEM_MIF_FRAME_TA0) 2349 return; 2350 } 2351 2352 printf("%s: mii_write timeout\n", device_xname(sc->sc_dev)); 2353 } 2354 2355 static void 2356 gem_mii_statchg(device_t self) 2357 { 2358 struct gem_softc *sc = device_private(self); 2359 #ifdef GEM_DEBUG 2360 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 2361 #endif 2362 2363 #ifdef GEM_DEBUG 2364 if (sc->sc_debug) 2365 printf("gem_mii_statchg: status change: phy = %d\n", 2366 sc->sc_phys[instance]); 2367 #endif 2368 gem_statuschange(sc); 2369 } 2370 2371 /* 2372 * Common status change for gem_mii_statchg() and gem_pint() 2373 */ 2374 void 2375 gem_statuschange(struct gem_softc* sc) 2376 { 2377 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2378 bus_space_tag_t t = sc->sc_bustag; 2379 bus_space_handle_t mac = sc->sc_h1; 2380 int gigabit; 2381 u_int32_t rxcfg, txcfg, v; 2382 2383 if ((sc->sc_mii.mii_media_status & IFM_ACTIVE) != 0 && 2384 IFM_SUBTYPE(sc->sc_mii.mii_media_active) != IFM_NONE) 2385 sc->sc_flags |= GEM_LINK; 2386 else 2387 sc->sc_flags &= ~GEM_LINK; 2388 2389 if (sc->sc_ethercom.ec_if.if_baudrate == IF_Mbps(1000)) 2390 gigabit = 1; 2391 else 2392 gigabit = 0; 2393 2394 /* 2395 * The configuration done here corresponds to the steps F) and 2396 * G) and as far as enabling of RX and TX MAC goes also step H) 2397 * of the initialization sequence outlined in section 3.2.1 of 2398 * the GEM Gigabit Ethernet ASIC Specification. 2399 */ 2400 2401 rxcfg = bus_space_read_4(t, mac, GEM_MAC_RX_CONFIG); 2402 rxcfg &= ~(GEM_MAC_RX_CARR_EXTEND | GEM_MAC_RX_ENABLE); 2403 txcfg = GEM_MAC_TX_ENA_IPG0 | GEM_MAC_TX_NGU | GEM_MAC_TX_NGU_LIMIT; 2404 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 2405 txcfg |= GEM_MAC_TX_IGN_CARRIER | GEM_MAC_TX_IGN_COLLIS; 2406 else if (gigabit) { 2407 rxcfg |= GEM_MAC_RX_CARR_EXTEND; 2408 txcfg |= GEM_MAC_RX_CARR_EXTEND; 2409 } 2410 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0); 2411 bus_space_barrier(t, mac, GEM_MAC_TX_CONFIG, 4, 2412 BUS_SPACE_BARRIER_WRITE); 2413 if (!gem_bitwait(sc, mac, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)) 2414 aprint_normal_dev(sc->sc_dev, "cannot disable TX MAC\n"); 2415 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, txcfg); 2416 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, 0); 2417 bus_space_barrier(t, mac, GEM_MAC_RX_CONFIG, 4, 2418 BUS_SPACE_BARRIER_WRITE); 2419 if (!gem_bitwait(sc, mac, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)) 2420 aprint_normal_dev(sc->sc_dev, "cannot disable RX MAC\n"); 2421 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, rxcfg); 2422 2423 v = bus_space_read_4(t, mac, GEM_MAC_CONTROL_CONFIG) & 2424 ~(GEM_MAC_CC_RX_PAUSE | GEM_MAC_CC_TX_PAUSE); 2425 bus_space_write_4(t, mac, GEM_MAC_CONTROL_CONFIG, v); 2426 2427 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) == 0 && 2428 gigabit != 0) 2429 bus_space_write_4(t, mac, GEM_MAC_SLOT_TIME, 2430 GEM_MAC_SLOT_TIME_CARR_EXTEND); 2431 else 2432 bus_space_write_4(t, mac, GEM_MAC_SLOT_TIME, 2433 GEM_MAC_SLOT_TIME_NORMAL); 2434 2435 /* XIF Configuration */ 2436 if (sc->sc_flags & GEM_LINK) 2437 v = GEM_MAC_XIF_LINK_LED; 2438 else 2439 v = 0; 2440 v |= GEM_MAC_XIF_TX_MII_ENA; 2441 2442 /* If an external transceiver is connected, enable its MII drivers */ 2443 sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG); 2444 if ((sc->sc_flags &(GEM_SERDES | GEM_SERIAL)) == 0) { 2445 if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) { 2446 if (gigabit) 2447 v |= GEM_MAC_XIF_GMII_MODE; 2448 else 2449 v &= ~GEM_MAC_XIF_GMII_MODE; 2450 } else 2451 /* Internal MII needs buf enable */ 2452 v |= GEM_MAC_XIF_MII_BUF_ENA; 2453 /* MII needs echo disable if half duplex. */ 2454 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 2455 /* turn on full duplex LED */ 2456 v |= GEM_MAC_XIF_FDPLX_LED; 2457 else 2458 /* half duplex -- disable echo */ 2459 v |= GEM_MAC_XIF_ECHO_DISABL; 2460 } else { 2461 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 2462 v |= GEM_MAC_XIF_FDPLX_LED; 2463 v |= GEM_MAC_XIF_GMII_MODE; 2464 } 2465 bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v); 2466 2467 if ((ifp->if_flags & IFF_RUNNING) != 0 && 2468 (sc->sc_flags & GEM_LINK) != 0) { 2469 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 2470 txcfg | GEM_MAC_TX_ENABLE); 2471 bus_space_write_4(t, mac, GEM_MAC_RX_CONFIG, 2472 rxcfg | GEM_MAC_RX_ENABLE); 2473 } 2474 } 2475 2476 int 2477 gem_ser_mediachange(struct ifnet *ifp) 2478 { 2479 struct gem_softc *sc = ifp->if_softc; 2480 u_int s, t; 2481 2482 if (IFM_TYPE(sc->sc_mii.mii_media.ifm_media) != IFM_ETHER) 2483 return EINVAL; 2484 2485 s = IFM_SUBTYPE(sc->sc_mii.mii_media.ifm_media); 2486 if (s == IFM_AUTO) { 2487 if (sc->sc_mii_media != s) { 2488 #ifdef GEM_DEBUG 2489 aprint_debug_dev(sc->sc_dev, "setting media to auto\n"); 2490 #endif 2491 sc->sc_mii_media = s; 2492 if (ifp->if_flags & IFF_UP) { 2493 gem_pcs_stop(sc, 0); 2494 gem_pcs_start(sc); 2495 } 2496 } 2497 return 0; 2498 } 2499 if (s == IFM_1000_SX) { 2500 t = IFM_OPTIONS(sc->sc_mii.mii_media.ifm_media); 2501 if (t == IFM_FDX || t == IFM_HDX) { 2502 if (sc->sc_mii_media != t) { 2503 sc->sc_mii_media = t; 2504 #ifdef GEM_DEBUG 2505 aprint_debug_dev(sc->sc_dev, 2506 "setting media to 1000baseSX-%s\n", 2507 t == IFM_FDX ? "FDX" : "HDX"); 2508 #endif 2509 if (ifp->if_flags & IFF_UP) { 2510 gem_pcs_stop(sc, 0); 2511 gem_pcs_start(sc); 2512 } 2513 } 2514 return 0; 2515 } 2516 } 2517 return EINVAL; 2518 } 2519 2520 void 2521 gem_ser_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2522 { 2523 struct gem_softc *sc = ifp->if_softc; 2524 2525 if ((ifp->if_flags & IFF_UP) == 0) 2526 return; 2527 ifmr->ifm_active = sc->sc_mii.mii_media_active; 2528 ifmr->ifm_status = sc->sc_mii.mii_media_status; 2529 } 2530 2531 static int 2532 gem_ifflags_cb(struct ethercom *ec) 2533 { 2534 struct ifnet *ifp = &ec->ec_if; 2535 struct gem_softc *sc = ifp->if_softc; 2536 int change = ifp->if_flags ^ sc->sc_if_flags; 2537 2538 if ((change & ~(IFF_CANTCHANGE|IFF_DEBUG)) != 0) 2539 return ENETRESET; 2540 else if ((change & IFF_PROMISC) != 0) 2541 gem_setladrf(sc); 2542 return 0; 2543 } 2544 2545 /* 2546 * Process an ioctl request. 2547 */ 2548 int 2549 gem_ioctl(struct ifnet *ifp, unsigned long cmd, void *data) 2550 { 2551 struct gem_softc *sc = ifp->if_softc; 2552 int s, error = 0; 2553 2554 s = splnet(); 2555 2556 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 2557 error = 0; 2558 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 2559 ; 2560 else if (ifp->if_flags & IFF_RUNNING) { 2561 /* 2562 * Multicast list has changed; set the hardware filter 2563 * accordingly. 2564 */ 2565 gem_setladrf(sc); 2566 } 2567 } 2568 2569 /* Try to get things going again */ 2570 if (ifp->if_flags & IFF_UP) 2571 gem_start(ifp); 2572 splx(s); 2573 return (error); 2574 } 2575 2576 static void 2577 gem_inten(struct gem_softc *sc) 2578 { 2579 bus_space_tag_t t = sc->sc_bustag; 2580 bus_space_handle_t h = sc->sc_h1; 2581 uint32_t v; 2582 2583 if ((sc->sc_flags & (GEM_SERDES | GEM_SERIAL)) != 0) 2584 v = GEM_INTR_PCS; 2585 else 2586 v = GEM_INTR_MIF; 2587 bus_space_write_4(t, h, GEM_INTMASK, 2588 ~(GEM_INTR_TX_INTME | 2589 GEM_INTR_TX_EMPTY | 2590 GEM_INTR_TX_MAC | 2591 GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF| 2592 GEM_INTR_RX_TAG_ERR | GEM_INTR_MAC_CONTROL| 2593 GEM_INTR_BERR | v)); 2594 } 2595 2596 bool 2597 gem_resume(device_t self, const pmf_qual_t *qual) 2598 { 2599 struct gem_softc *sc = device_private(self); 2600 2601 gem_inten(sc); 2602 2603 return true; 2604 } 2605 2606 bool 2607 gem_suspend(device_t self, const pmf_qual_t *qual) 2608 { 2609 struct gem_softc *sc = device_private(self); 2610 bus_space_tag_t t = sc->sc_bustag; 2611 bus_space_handle_t h = sc->sc_h1; 2612 2613 bus_space_write_4(t, h, GEM_INTMASK, ~(uint32_t)0); 2614 2615 return true; 2616 } 2617 2618 bool 2619 gem_shutdown(device_t self, int howto) 2620 { 2621 struct gem_softc *sc = device_private(self); 2622 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2623 2624 gem_stop(ifp, 1); 2625 2626 return true; 2627 } 2628 2629 /* 2630 * Set up the logical address filter. 2631 */ 2632 void 2633 gem_setladrf(struct gem_softc *sc) 2634 { 2635 struct ethercom *ec = &sc->sc_ethercom; 2636 struct ifnet *ifp = &ec->ec_if; 2637 struct ether_multi *enm; 2638 struct ether_multistep step; 2639 bus_space_tag_t t = sc->sc_bustag; 2640 bus_space_handle_t h = sc->sc_h1; 2641 u_int32_t crc; 2642 u_int32_t hash[16]; 2643 u_int32_t v; 2644 int i; 2645 2646 /* Get current RX configuration */ 2647 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG); 2648 2649 /* 2650 * Turn off promiscuous mode, promiscuous group mode (all multicast), 2651 * and hash filter. Depending on the case, the right bit will be 2652 * enabled. 2653 */ 2654 v &= ~(GEM_MAC_RX_PROMISCUOUS|GEM_MAC_RX_HASH_FILTER| 2655 GEM_MAC_RX_PROMISC_GRP); 2656 2657 if ((ifp->if_flags & IFF_PROMISC) != 0) { 2658 /* Turn on promiscuous mode */ 2659 v |= GEM_MAC_RX_PROMISCUOUS; 2660 ifp->if_flags |= IFF_ALLMULTI; 2661 goto chipit; 2662 } 2663 2664 /* 2665 * Set up multicast address filter by passing all multicast addresses 2666 * through a crc generator, and then using the high order 8 bits as an 2667 * index into the 256 bit logical address filter. The high order 4 2668 * bits selects the word, while the other 4 bits select the bit within 2669 * the word (where bit 0 is the MSB). 2670 */ 2671 2672 /* Clear hash table */ 2673 memset(hash, 0, sizeof(hash)); 2674 2675 ETHER_FIRST_MULTI(step, ec, enm); 2676 while (enm != NULL) { 2677 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 2678 /* 2679 * We must listen to a range of multicast addresses. 2680 * For now, just accept all multicasts, rather than 2681 * trying to set only those filter bits needed to match 2682 * the range. (At this time, the only use of address 2683 * ranges is for IP multicast routing, for which the 2684 * range is big enough to require all bits set.) 2685 * XXX should use the address filters for this 2686 */ 2687 ifp->if_flags |= IFF_ALLMULTI; 2688 v |= GEM_MAC_RX_PROMISC_GRP; 2689 goto chipit; 2690 } 2691 2692 /* Get the LE CRC32 of the address */ 2693 crc = ether_crc32_le(enm->enm_addrlo, sizeof(enm->enm_addrlo)); 2694 2695 /* Just want the 8 most significant bits. */ 2696 crc >>= 24; 2697 2698 /* Set the corresponding bit in the filter. */ 2699 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 2700 2701 ETHER_NEXT_MULTI(step, enm); 2702 } 2703 2704 v |= GEM_MAC_RX_HASH_FILTER; 2705 ifp->if_flags &= ~IFF_ALLMULTI; 2706 2707 /* Now load the hash table into the chip (if we are using it) */ 2708 for (i = 0; i < 16; i++) { 2709 bus_space_write_4(t, h, 2710 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1-GEM_MAC_HASH0), 2711 hash[i]); 2712 } 2713 2714 chipit: 2715 sc->sc_if_flags = ifp->if_flags; 2716 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v); 2717 } 2718
Indexes created Wed Sep 24 05:09:52 GMT 2025