gemreg.h revision 1.12
1 /* $NetBSD: gemreg.h,v 1.12 2008/05/06 21:09:34 jdc Exp $ */ 2 3 /* 4 * 5 * Copyright (C) 2001 Eduardo Horvath. 6 * All rights reserved. 7 * 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 */ 31 32 #ifndef _IF_GEMREG_H 33 #define _IF_GEMREG_H 34 35 /* 36 * Register definitions for Sun GEM Gigabit Ethernet 37 * See `GEM Gigabit Ethernet ASIC Specification' 38 * http://www.sun.com/processors/manuals/ge.pdf 39 * Section 3.1.3 GEM Register Space (from Rev 1.2) 40 */ 41 42 /* 43 * Global Resources 44 * Section 3.1.4.1 45 * 46 * First bank: this registers live at the start of the PCI 47 * mapping, and at the start of the second bank of the SBUS 48 * version. 49 */ 50 #define GEM_SEB_STATE 0x0000 /* SEB State (R/O) */ 51 #define GEM_CONFIG 0x0004 /* Configuration */ 52 #define GEM_STATUS 0x000c /* Status */ 53 /* Note: Reading the status register auto-clears bits 0-6 */ 54 #define GEM_INTMASK 0x0010 /* Interrupt Mask */ 55 #define GEM_INTACK 0x0014 /* Interrupt Acknowledge (W/O) */ 56 #define GEM_STATUS_ALIAS 0x001c /* Status Alias */ 57 /* This is the same as GEM_STATUS but reading it does not auto-clear bits. */ 58 59 /* 60 * Second bank: this registers live at offset 0x1000 of the PCI 61 * mapping, and at the start of the first bank of the SBUS 62 * version. 63 */ 64 #define GEM_PCI_BANK2_OFFSET 0x1000 65 #define GEM_PCI_BANK2_SIZE 0x14 66 #define GEM_ERROR_STATUS 0x0000 /* PCI Error Status */ 67 #define GEM_ERROR_MASK 0x0004 /* PCI Error Mask */ 68 #define GEM_BIF_CONFIG 0x0008 /* PCI BIF Configuration */ 69 #define GEM_BIF_DIAG 0x000c /* PCI BIF Diagnostic */ 70 #define GEM_RESET 0x0010 /* PCI Software Reset */ 71 72 #define GEM_SBUS_RESET 0x0000 /* Sbus Reset */ 73 #define GEM_SBUS_CONFIG 0x0004 /* Sbus Burst-Size Configuration */ 74 #define GEM_SBUS_ERROR_STATUS 0x0008 /* Sbus Fatal Error */ 75 #define GEM_SBUS_SOFT_RESET 0x000c /* Sbus Software Reset */ 76 #define GEM_SBUS_SOFT_RESET2 0x0010 /* Sbus Software Reset */ 77 78 /* 79 * Bits in GEM_SEB_STATE register 80 * For diagnostic use 81 */ 82 #define GEM_SEB_ARB 0x000000002 /* Arbitration status */ 83 #define GEM_SEB_RXWON 0x000000004 84 85 /* 86 * Bits in GEM_CONFIG register 87 * Default: 0x00042 88 */ 89 #define GEM_CONFIG_BURST_64 0x000000000 /* 0->infinity, 1->64KB */ 90 #define GEM_CONFIG_BURST_INF 0x000000001 /* 0->infinity, 1->64KB */ 91 #define GEM_CONFIG_TXDMA_LIMIT 0x00000003e 92 #define GEM_CONFIG_RXDMA_LIMIT 0x0000007c0 93 /* GEM_CONFIG_RONPAULBIT and GEM_CONFIG_BUG2FIX are Apple only. */ 94 #define GEM_CONFIG_RONPAULBIT 0x000000800 /* after infinite burst use 95 * memory read multiple for 96 * PCI commands */ 97 #define GEM_CONFIG_BUG2FIX 0x000001000 /* fix RX hang after overflow */ 98 99 #define GEM_CONFIG_TXDMA_LIMIT_SHIFT 1 100 #define GEM_CONFIG_RXDMA_LIMIT_SHIFT 6 101 102 103 /* 104 * Interrupt bits, for both the GEM_STATUS and GEM_INTMASK regs. 105 * Bits 0-6 auto-clear when read. 106 */ 107 #define GEM_INTR_TX_INTME 0x000000001 /* Frame w/INTME bit set sent */ 108 #define GEM_INTR_TX_EMPTY 0x000000002 /* TX ring empty */ 109 #define GEM_INTR_TX_DONE 0x000000004 /* TX complete */ 110 #define GEM_INTR_RX_DONE 0x000000010 /* Got a packet */ 111 #define GEM_INTR_RX_NOBUF 0x000000020 /* No free receive buffers */ 112 #define GEM_INTR_RX_TAG_ERR 0x000000040 /* RX Tag framing error */ 113 #define GEM_INTR_PERR 0x000000080 /* Parity error */ 114 #define GEM_INTR_PCS 0x000002000 /* PCS interrupt */ 115 #define GEM_INTR_TX_MAC 0x000004000 /* TX MAC interrupt */ 116 #define GEM_INTR_RX_MAC 0x000008000 /* RX MAC interrupt */ 117 #define GEM_INTR_MAC_CONTROL 0x000010000 /* MAC control interrupt */ 118 #define GEM_INTR_MIF 0x000020000 /* MIF interrupt */ 119 #define GEM_INTR_BERR 0x000040000 /* Bus error interrupt */ 120 #define GEM_INTR_BITS "\177\020" \ 121 "b\0INTME\0b\1TXEMPTY\0b\2TXDONE\0" \ 122 "b\4RXDONE\0b\5RXNOBUF\0b\6RX_TAG_ERR\0" \ 123 "b\xdPCS\0b\xeTXMAC\0b\xfRXMAC\0" \ 124 "b\x10MAC_CONTROL\0b\x11MIF\0b\x12IBERR\0\0" 125 126 /* Top part (bits 19-31) of GEM_STATUS has TX completion information */ 127 #define GEM_STATUS_TX_COMPL 0xfff800000 /* TX completion reg. */ 128 129 130 /* 131 * Bits in GEM_ERROR_STATUS and GEM_ERROR_MASK PCI registers 132 */ 133 #define GEM_ERROR_STAT_BADACK 0x000000001 /* No ACK64# */ 134 #define GEM_ERROR_STAT_DTRTO 0x000000002 /* Delayed xaction timeout */ 135 #define GEM_ERROR_STAT_OTHERS 0x000000004 /* Other PCI errors. Read PCI 136 Status Register in PCI 137 Configuration space */ 138 #define GEM_ERROR_BITS "\177\020b\0ACKBAD\0b\1DTRTO\0b\2OTHER\0\0" 139 140 141 /* 142 * Bits in GEM_SBUS_CONFIG register 143 */ 144 #define GEM_SBUS_CFG_BSIZE32 0x00000001 145 #define GEM_SBUS_CFG_BSIZE64 0x00000002 146 #define GEM_SBUS_CFG_BSIZE128 0x00000004 147 #define GEM_SBUS_CFG_BMODE64 0x00000008 148 #define GEM_SBUS_CFG_PARITY 0x00000200 149 150 151 /* 152 * Bits in GEM_BIF_CONFIG register 153 * Default: 0x0 154 */ 155 #define GEM_BIF_CONFIG_SLOWCLK 0x000000001 /* Parity error timing */ 156 #define GEM_BIF_CONFIG_HOST_64 0x000000002 /* 64-bit host */ 157 #define GEM_BIF_CONFIG_B64D_DIS 0x000000004 /* no 64-bit data cycle */ 158 #define GEM_BIF_CONFIG_M66EN 0x000000008 159 #define GEM_BIF_CONFIG_BITS "\177\020b\0SLOWCLK\0b\1HOST64\0" \ 160 "b\2B64DIS\0b\3M66EN\0\0" 161 162 163 /* 164 * Bits in GEM_BIF_DIAG register 165 * Default: 0x00000000 166 */ 167 #define GEN_BIF_DIAG_PCIBURST 0x007f0000 /* PCI Burst Controller state 168 * machine */ 169 #define GEN_BIF_DIAG_STATE 0xff000000 /* BIF state machine */ 170 171 /* 172 * Bits in GEM_RESET register 173 * RESET_TX and RESET_RX self clear when complete. 174 */ 175 #define GEM_RESET_TX 0x000000001 /* Reset TX half */ 176 #define GEM_RESET_RX 0x000000002 /* Reset RX half */ 177 #define GEM_RESET_GLOBAL 0x000000003 /* Global Reset */ 178 #define GEM_RESET_RSTOUT 0x000000004 /* Force PCI RSTOUT# */ 179 180 181 /* 182 * TX DMA Programmable Resources 183 * Section 3.1.4.2 184 * The 53 most significant bits of the Descriptor Base Low/High registers 185 * are used as the TX descriptor ring base address. The ring base must be 186 * initialized to a 2KByte-aligned address after power-on or software reset. 187 */ 188 #define GEM_TX_KICK 0x2000 /* TX Kick */ 189 /* Note: Write last valid desc + 1 */ 190 #define GEM_TX_CONFIG 0x2004 /* TX Configuration */ 191 #define GEM_TX_RING_PTR_LO 0x2008 /* TX Descriptor Base Low */ 192 #define GEM_TX_RING_PTR_HI 0x200c /* TX Descriptor Base High */ 193 /* 0x2010 Reserved */ 194 #define GEM_TX_FIFO_WR_PTR 0x2014 /* TX FIFO Write Pointer */ 195 #define GEM_TX_FIFO_SDWR_PTR 0x2018 /* TX FIFO Shadow Write Ptr */ 196 #define GEM_TX_FIFO_RD_PTR 0x201c /* TX FIFO Read Pointer */ 197 #define GEM_TX_FIFO_SDRD_PTR 0x2020 /* TX FIFO Shadow Read Ptr */ 198 #define GEM_TX_FIFO_PKT_CNT 0x2024 /* TX FIFO Packet Counter */ 199 #define GEM_TX_STATE_MACHINE 0x2028 /* TX State Machine */ 200 /* 0x202c Unknown */ 201 #define GEM_TX_DATA_PTR_LO 0x2030 /* TX Data Pointer Low */ 202 #define GEM_TX_DATA_PTR_HI 0x2034 /* TX Data Pointer High */ 203 204 #define GEM_TX_COMPLETION 0x2100 /* TX Completion */ 205 #define GEM_TX_FIFO_ADDRESS 0x2104 /* TX FIFO Address */ 206 #define GEM_TX_FIFO_TAG 0x2108 /* TX FIFO Tag */ 207 #define GEM_TX_FIFO_DATA_LO 0x210c /* TX FIFO Data Low */ 208 #define GEM_TX_FIFO_DATA_HI_T1 0x2110 /* TX FIFO Data HighT1 */ 209 #define GEM_TX_FIFO_DATA_HI_T0 0x2114 /* TX FIFO Data HighT0 */ 210 #define GEM_TX_FIFO_SIZE 0x2118 /* TX FIFO Size */ 211 #define GEM_TX_DEBUG 0x3028 212 213 214 /* 215 * Bits in GEM_TX_CONFIG register 216 * Default: 0x118c10 217 * TX FIFO Threshold should be set to 0x4ff 218 */ 219 #define GEM_TX_CONFIG_TXDMA_EN 0x00000001 /* TX DMA enable */ 220 #define GEM_TX_CONFIG_TXRING_SZ 0x0000001e /* TX ring size */ 221 #define GEM_TX_CONFIG_TXFIFO_SL 0x00000020 /* TX DMA FIFO PIO select */ 222 #define GEM_TX_CONFIG_TXFIFO_TH 0x001ffc00 /* TX fifo threshold */ 223 #define GEM_TX_CONFIG_PACED 0x00200000 /* TX_all_int modifier */ 224 225 #define GEM_RING_SZ_32 (0<<1) /* 32 descriptors */ 226 #define GEM_RING_SZ_64 (1<<1) 227 #define GEM_RING_SZ_128 (2<<1) 228 #define GEM_RING_SZ_256 (3<<1) 229 #define GEM_RING_SZ_512 (4<<1) 230 #define GEM_RING_SZ_1024 (5<<1) 231 #define GEM_RING_SZ_2048 (6<<1) 232 #define GEM_RING_SZ_4096 (7<<1) 233 #define GEM_RING_SZ_8192 (8<<1) /* Default */ 234 235 236 /* 237 * Bits in GEM_TX_COMPLETION register 238 */ 239 #define GEM_TX_COMPLETION_MASK 0x00001fff /* # of last descriptor */ 240 241 242 /* 243 * RX DMA Programmable Resources 244 * Section 3.1.4.3 245 * The 53 most significant bits of the Descriptor Base Low/High registers 246 * are used as the RX descriptor ring base address. The ring base must be 247 * initialized to a 2KByte-aligned address after power-on or software reset. 248 */ 249 #define GEM_RX_CONFIG 0x4000 /* RX Configuration */ 250 #define GEM_RX_RING_PTR_LO 0x4004 /* RX Descriptor Base Low */ 251 #define GEM_RX_RING_PTR_HI 0x4008 /* RX Descriptor Base High */ 252 #define GEM_RX_FIFO_WR_PTR 0x400c /* RX FIFO Write Pointer */ 253 #define GEM_RX_FIFO_SDWR_PTR 0x4010 /* RX FIFO Shadow Write Ptr */ 254 #define GEM_RX_FIFO_RD_PTR 0x4014 /* RX FIFO Read Pointer */ 255 #define GEM_RX_FIFO_PKT_CNT 0x4018 /* RX FIFO Packet Counter */ 256 #define GEM_RX_STATE_MACHINE 0x401c /* RX State Machine */ 257 #define GEM_RX_PAUSE_THRESH 0x4020 /* Pause Thresholds */ 258 #define GEM_RX_DATA_PTR_LO 0x4024 /* RX Data Pointer Low */ 259 #define GEM_RX_DATA_PTR_HI 0x4028 /* RX Data Pointer High */ 260 261 #define GEM_RX_KICK 0x4100 /* RX Kick */ 262 /* Note: Write last valid desc + 1. Must be a multiple of 4 */ 263 #define GEM_RX_COMPLETION 0x4104 /* RX Completion */ 264 #define GEM_RX_BLANKING 0x4108 /* RX Blanking */ 265 #define GEM_RX_FIFO_ADDRESS 0x410c /* RX FIFO Address */ 266 #define GEM_RX_FIFO_TAG 0x4110 /* RX FIFO Tag */ 267 #define GEM_RX_FIFO_DATA_LO 0x4114 /* RX FIFO Data Low */ 268 #define GEM_RX_FIFO_DATA_HI_T1 0x4118 /* RX FIFO Data HighT0 */ 269 #define GEM_RX_FIFO_DATA_HI_T0 0x411c /* RX FIFO Data HighT1 */ 270 #define GEM_RX_FIFO_SIZE 0x4120 /* RX FIFO Size */ 271 272 273 /* 274 * Bits in GEM_RX_CONFIG register 275 * Default: 0x1000010 276 */ 277 #define GEM_RX_CONFIG_RXDMA_EN 0x00000001 /* RX DMA enable */ 278 #define GEM_RX_CONFIG_RXRING_SZ 0x0000001e /* RX ring size */ 279 #define GEM_RX_CONFIG_BATCH_DIS 0x00000020 /* desc batching disable */ 280 #define GEM_RX_CONFIG_FBOFF 0x00001c00 /* first byte offset */ 281 #define GEM_RX_CONFIG_CXM_START 0x000fe000 /* cksum start offset bytes */ 282 #define GEM_RX_CONFIG_FIFO_THRS 0x07000000 /* fifo threshold size */ 283 284 #define GEM_THRSH_64 0 285 #define GEM_THRSH_128 1 286 #define GEM_THRSH_256 2 287 #define GEM_THRSH_512 3 288 #define GEM_THRSH_1024 4 289 #define GEM_THRSH_2048 5 290 291 #define GEM_RX_CONFIG_FIFO_THRS_SHIFT 24 292 #define GEM_RX_CONFIG_FBOFF_SHFT 10 293 #define GEM_RX_CONFIG_CXM_START_SHFT 13 294 295 296 /* GEM_RX_PAUSE_THRESH register bits -- sizes in multiples of 64 bytes */ 297 #define GEM_RX_PTH_XOFF_THRESH 0x000001ff 298 #define GEM_RX_PTH_XON_THRESH 0x001ff000 299 300 301 /* GEM_RX_BLANKING register bits */ 302 #define GEM_RX_BLANKING_PACKETS 0x000001ff /* Delay intr for x packets */ 303 #define GEM_RX_BLANKING_TIME 0x000ff000 /* Delay intr for x ticks */ 304 #define GEM_RX_BLANKING_TIME_SHIFT 12 305 /* One tick is 2048 PCI clocks, or 16us at 66MHz */ 306 307 308 /* 309 * MAC Programmable Resources 310 * Section 3.1.5 311 */ 312 #define GEM_MAC_TXRESET 0x6000 /* TX MAC Software Reset Cmd */ 313 #define GEM_MAC_RXRESET 0x6004 /* RX MAC Software Reset Cmd */ 314 /* Note: Store 1, cleared when done for TXRESET and RXRESET */ 315 #define GEM_MAC_SEND_PAUSE_CMD 0x6008 /* Send Pause Command */ 316 #define GEM_MAC_TX_STATUS 0x6010 /* TX MAC Status */ 317 #define GEM_MAC_RX_STATUS 0x6014 /* RX MAC Status */ 318 #define GEM_MAC_CONTROL_STATUS 0x6018 /* MAC Control Status */ 319 #define GEM_MAC_TX_MASK 0x6020 /* TX MAC Mask */ 320 #define GEM_MAC_RX_MASK 0x6024 /* RX MAC Mask */ 321 #define GEM_MAC_CONTROL_MASK 0x6028 /* MAC Control Mask */ 322 #define GEM_MAC_TX_CONFIG 0x6030 /* TX MAC Configuration */ 323 #define GEM_MAC_RX_CONFIG 0x6034 /* XX MAC Configuration */ 324 #define GEM_MAC_CONTROL_CONFIG 0x6038 /* MAC Control Configuration */ 325 #define GEM_MAC_XIF_CONFIG 0x603c /* XIF Configuration */ 326 #define GEM_MAC_IPG0 0x6040 /* InterPacketGap0 */ 327 #define GEM_MAC_IPG1 0x6044 /* InterPacketGap1 */ 328 #define GEM_MAC_IPG2 0x6048 /* InterPacketGap2 */ 329 #define GEM_MAC_SLOT_TIME 0x604c /* SlotTime, bits 0-7 */ 330 #define GEM_MAC_MAC_MIN_FRAME 0x6050 /* MinFrameSize */ 331 #define GEM_MAC_MAC_MAX_FRAME 0x6054 /* MaxFrameSize */ 332 #define GEM_MAC_PREAMBLE_LEN 0x6058 /* PA Size */ 333 #define GEM_MAC_JAM_SIZE 0x605c /* JamSize */ 334 #define GEM_MAC_ATTEMPT_LIMIT 0x6060 /* Attempt Limit */ 335 #define GEM_MAC_CONTROL_TYPE 0x6064 /* MAC Control Type */ 336 337 #define GEM_MAC_ADDR0 0x6080 /* Normal MAC address 0 */ 338 #define GEM_MAC_ADDR1 0x6084 339 #define GEM_MAC_ADDR2 0x6088 340 #define GEM_MAC_ADDR3 0x608c /* Alternate MAC address 0 */ 341 #define GEM_MAC_ADDR4 0x6090 342 #define GEM_MAC_ADDR5 0x6094 343 #define GEM_MAC_ADDR6 0x6098 /* Control MAC address 0 */ 344 #define GEM_MAC_ADDR7 0x609c 345 #define GEM_MAC_ADDR8 0x60a0 346 347 #define GEM_MAC_ADDR_FILTER0 0x60a4 /* Address Filter */ 348 #define GEM_MAC_ADDR_FILTER1 0x60a8 349 #define GEM_MAC_ADDR_FILTER2 0x60ac 350 #define GEM_MAC_ADR_FLT_MASK1_2 0x60b0 /* Address Filter Mask 2&1 */ 351 #define GEM_MAC_ADR_FLT_MASK0 0x60b4 /* Address Filter Mask 0 */ 352 353 #define GEM_MAC_HASH0 0x60c0 /* Hash table 0 */ 354 #define GEM_MAC_HASH1 0x60c4 355 #define GEM_MAC_HASH2 0x60c8 356 #define GEM_MAC_HASH3 0x60cc 357 #define GEM_MAC_HASH4 0x60d0 358 #define GEM_MAC_HASH5 0x60d4 359 #define GEM_MAC_HASH6 0x60d8 360 #define GEM_MAC_HASH7 0x60dc 361 #define GEM_MAC_HASH8 0x60e0 362 #define GEM_MAC_HASH9 0x60e4 363 #define GEM_MAC_HASH10 0x60e8 364 #define GEM_MAC_HASH11 0x60ec 365 #define GEM_MAC_HASH12 0x60f0 366 #define GEM_MAC_HASH13 0x60f4 367 #define GEM_MAC_HASH14 0x60f8 368 #define GEM_MAC_HASH15 0x60fc 369 370 #define GEM_MAC_NORM_COLL_CNT 0x6100 /* Normal Collision Counter */ 371 #define GEM_MAC_FIRST_COLL_CNT 0x6104 /* First Attempt Successful 372 Collision Counter */ 373 #define GEM_MAC_EXCESS_COLL_CNT 0x6108 /* Excess Collision Counter */ 374 #define GEM_MAC_LATE_COLL_CNT 0x610c /* Late Collision Counter */ 375 #define GEM_MAC_DEFER_TMR_CNT 0x6110 /* Defer Timer */ 376 #define GEM_MAC_PEAK_ATTEMPTS 0x6114 /* Peak Attempts */ 377 #define GEM_MAC_RX_FRAME_COUNT 0x6118 /* Receive Frame Counter */ 378 #define GEM_MAC_RX_LEN_ERR_CNT 0x611c /* Length Error Counter */ 379 #define GEM_MAC_RX_ALIGN_ERR 0x6120 /* Alignment Error Counter */ 380 #define GEM_MAC_RX_CRC_ERR_CNT 0x6124 /* FCS Error Counter */ 381 #define GEM_MAC_RX_CODE_VIOL 0x6128 /* RX Code Violation Error 382 Counter */ 383 384 #define GEM_MAC_RANDOM_SEED 0x6130 /* Random Number Seed */ 385 #define GEM_MAC_MAC_STATE 0x6134 /* State Machine */ 386 387 388 /* 389 * Bits in GEM_MAC_SEND_PAUSE_CMD register 390 * Pause time is in units of Slot Times. 391 */ 392 #define GEM_MAC_PAUSE_CMD_TIME 0x0000ffff 393 #define GEM_MAC_PAUSE_CMD_SEND 0x00010000 394 395 396 /* 397 * Bits in GEM_MAC_TX_STATUS and _MASK register 398 * Interrupt bits are auto-cleared when the status register is read and 399 * the corresponding bit is set in the mask register. 400 */ 401 #define GEM_MAC_TX_XMIT_DONE 0x00000001 /* Successful transmission */ 402 #define GEM_MAC_TX_UNDERRUN 0x00000002 /* TX "data starvation" */ 403 #define GEM_MAC_TX_PKT_TOO_LONG 0x00000004 /* Frame exceeds max. length */ 404 #define GEM_MAC_TX_NCC_EXP 0x00000008 /* Normal collision counter has 405 rolled over */ 406 #define GEM_MAC_TX_ECC_EXP 0x00000010 /* Excessive coll cnt rolled */ 407 #define GEM_MAC_TX_LCC_EXP 0x00000020 /* Late coll cnt rolled */ 408 #define GEM_MAC_TX_FCC_EXP 0x00000040 /* First coll cnt rolled */ 409 #define GEM_MAC_TX_DEFER_EXP 0x00000080 /* Defer timer cnt rolled */ 410 #define GEM_MAC_TX_PEAK_EXP 0x00000100 /* Peak attempts cnt rolled */ 411 412 413 /* 414 * Bits in GEM_MAC_RX_STATUS and _MASK register 415 */ 416 #define GEM_MAC_RX_DONE 0x00000001 /* Successful reception */ 417 #define GEM_MAC_RX_OVERFLOW 0x00000002 /* RX resource lack */ 418 #define GEM_MAC_RX_FRAME_CNT 0x00000004 /* Receive frame counter has 419 rolled over */ 420 #define GEM_MAC_RX_ALIGN_EXP 0x00000008 /* Alignment error cnt rolled */ 421 #define GEM_MAC_RX_CRC_EXP 0x00000010 /* CRC error cnt rolled */ 422 #define GEM_MAC_RX_LEN_EXP 0x00000020 /* Length error cnt rolled */ 423 #define GEM_MAC_RX_CVI_EXP 0x00000040 /* Code violation err rolled */ 424 425 426 /* 427 * Bits in GEM_MAC_CONTROL_STATUS and GEM_MAC_CONTROL_MASK register 428 */ 429 #define GEM_MAC_PAUSED 0x00000001 /* Pause received */ 430 #define GEM_MAC_PAUSE 0x00000002 /* enter pause state */ 431 #define GEM_MAC_RESUME 0x00000004 /* exit pause state */ 432 #define GEM_MAC_PAUSE_TIME 0xffff0000 /* Pause time received */ 433 #define GEM_MAC_STATUS_BITS "\177\020b\0PAUSED\0b\1PAUSE\0b\2RESUME\0\0" 434 435 436 /* 437 * Bits in GEM_MAC_XIF_CONFIG register 438 * Default: 0x00 439 */ 440 #define GEM_MAC_XIF_TX_MII_ENA 0x00000001 /* Enable MII output */ 441 #define GEM_MAC_XIF_MII_LOOPBK 0x00000002 /* Enable (G)MII loopback */ 442 #define GEM_MAC_XIF_ECHO_DISABL 0x00000004 /* Disable echo */ 443 #define GEM_MAC_XIF_GMII_MODE 0x00000008 /* Select GMII/MII mode */ 444 #define GEM_MAC_XIF_MII_BUF_ENA 0x00000010 /* Enable MII recv buffers */ 445 #define GEM_MAC_XIF_LINK_LED 0x00000020 /* force link LED active */ 446 #define GEM_MAC_XIF_FDPLX_LED 0x00000040 /* force FDPLX LED active */ 447 #define GEM_MAC_XIF_BITS "\177\020b\0TXMIIENA\0b\1MIILOOP\0b\2NOECHO" \ 448 "\0b\3GMII\0b\4MIIBUFENA\0b\5LINKLED\0" \ 449 "b\6FDLED\0\0" 450 451 452 /* 453 * Bits in GEM_MAC_TX_CONFIG register 454 * GEM_MAC_TX_ENABLE must be cleared and a delay imposed before writing to 455 * other bits in this register or any of the MAC parameters registers. 456 * The GEM_MAC_TX_ENABLE bit will read 0 when the transmitter has stopped. 457 * Carrier Extension must be set when operating in Half-Duplex at 1Gbps, 458 * and disabled otherwise. To enable this GEM_MAC_TX_CARR_EXTEND and 459 * GEM_MAC_RX_CARR_EXTEND must be set to 1 and the Slot Time register must 460 * be set to 0x200. 461 */ 462 #define GEM_MAC_TX_ENABLE 0x00000001 /* TX enable */ 463 #define GEM_MAC_TX_IGN_CARRIER 0x00000002 /* Ignore carrier sense */ 464 #define GEM_MAC_TX_IGN_COLLIS 0x00000004 /* ignore collisions */ 465 #define GEM_MAC_TX_ENA_IPG0 0x00000008 /* extend Rx-to-TX IPG */ 466 #define GEM_MAC_TX_NGU 0x00000010 /* Never give up */ 467 #define GEM_MAC_TX_NGU_LIMIT 0x00000020 /* Never give up limit */ 468 #define GEM_MAC_TX_NO_BACKOFF 0x00000040 /* Never backoff on coll */ 469 #define GEM_MAC_TX_SLOWDOWN 0x00000080 /* Watch carrier sense */ 470 #define GEM_MAC_TX_NO_FCS 0x00000100 /* no FCS will be generated */ 471 #define GEM_MAC_TX_CARR_EXTEND 0x00000200 /* Ena TX Carrier Extension */ 472 #define GEM_MAC_TX_CONFIG_BITS "\177\020" \ 473 "b\0TXENA\0b\1IGNCAR\0b\2IGNCOLLIS\0" \ 474 "b\3IPG0ENA\0b\4TXNGU\0b\5TXNGULIM\0" \ 475 "b\6NOBKOFF\0b\7SLOWDN\0b\x8NOFCS\0" \ 476 "b\x9TXCARREXT\0\0" 477 478 479 /* 480 * Bits in GEM_MAC_RX_CONFIG register 481 * The GEM_MAC_RX_ENABLE bit must be cleared and a delay of 3.2ms imposed 482 * before writing to other bits in this register or any of the MAC 483 * parameters registers. The GEM_MAC_RX_ENABLE bit will read 0 when the 484 * receiver has stopped. 485 * The GEM_MAC_RX_HASH_FILTER bit must be cleared and a delay of 3.2ms 486 * imposed before writing to any of the Hash Table registers. The 487 * GEM_MAC_RX_HASH_FILTER bit will read 0 when the registers may be written. 488 * The GEM_MAC_RX_ADDR_FILTER bit must be cleared and a delay of 3.2ms 489 * imposed before writing to any of the Address Filter registers. The 490 * GEM_MAC_RX_ADDR_FILTER bit will read 0 when the registers may be written. 491 * See "Carrier Extension" above. 492 */ 493 #define GEM_MAC_RX_ENABLE 0x00000001 /* RX enable */ 494 #define GEM_MAC_RX_STRIP_PAD 0x00000002 /* strip pad bytes */ 495 #define GEM_MAC_RX_STRIP_CRC 0x00000004 496 #define GEM_MAC_RX_PROMISCUOUS 0x00000008 /* promiscuous mode */ 497 #define GEM_MAC_RX_PROMISC_GRP 0x00000010 /* promiscuous group mode */ 498 #define GEM_MAC_RX_HASH_FILTER 0x00000020 /* enable hash filter */ 499 #define GEM_MAC_RX_ADDR_FILTER 0x00000040 /* enable address filter */ 500 #define GEM_MAC_RX_ERRCHK_DIS 0x00000080 /* disable error discard */ 501 #define GEM_MAC_RX_CARR_EXTEND 0x00000100 /* Ena RX Carrier Extension */ 502 #define GEM_MAC_RX_CONFIG_BITS "\177\020" \ 503 "b\0RXENA\0b\1STRPAD\0b\2STRCRC\0" \ 504 "b\3PROMIS\0b\4PROMISCGRP\0b\5HASHFLTR\0" \ 505 "b\6ADDRFLTR\0b\7ERRCHKDIS\0b\x9TXCARREXT\0\0" 506 507 508 /* 509 * Bits in GEM_MAC_CONTROL_CONFIG 510 * Default; 0x0 511 */ 512 #define GEM_MAC_CC_TX_PAUSE 0x00000001 /* send pause enabled */ 513 #define GEM_MAC_CC_RX_PAUSE 0x00000002 /* receive pause enabled */ 514 #define GEM_MAC_CC_PASS_PAUSE 0x00000004 /* pass pause up */ 515 #define GEM_MAC_CC_BITS "\177\020b\0TXPAUSE\0b\1RXPAUSE\0b\2NOPAUSE\0\0" 516 517 518 /* 519 * Bits in GEM_MAC_SLOT_TIME register 520 * The slot time is used as PAUSE time unit, value depends on whether carrier 521 * extension is enabled. 522 */ 523 #define GEM_MAC_SLOT_TIME_CARR_EXTEND 0x200 524 #define GEM_MAC_SLOT_TIME_NORMAL 0x40 525 526 527 /* 528 * Recommended values for MAC registers: 529 * GEM_MAC_IPG0 0x00 530 * GEM_MAC_IPG1 0x08 531 * GEM_MAC_IPG2 0x04 532 * GEM_MAC_SLOT_TIME 0x40 (see "Carrier Extension" above) 533 * Bits in GEM_MAC_MAC_MAX_FRAME register 534 * max burst size 0x7fff0000 535 * max frame size 0x00007fff 536 * GEM_MAC_MAC_MIN_FRAME 0x40 537 * GEM_MAC_MAC_MAX_FRAME 0x200005ee 538 * GEM_MAC_PREAMBLE_LEN 0x07 (minimum of 0x02) 539 * GEM_MAC_JAM_SIZE 0x04 540 * GEM_MAC_ATTEMPT_LIMIT 0x10 541 * GEM_MAC_CONTROL_TYPE 0x8808 542 */ 543 544 545 /* 546 * Address detection and filtering registers (16-bit unless noted): 547 * GEM_MAC_ADDR0 normal priority MAC address bits 32-47 548 * GEM_MAC_ADDR1 normal priority MAC address bits 16-31 549 * GEM_MAC_ADDR2 normal priority MAC address bits 0-15 550 * GEM_MAC_ADDR3 alternate MAC address bits 32-47 551 * GEM_MAC_ADDR4 alternate MAC address bits 16-31 552 * GEM_MAC_ADDR5 alternate MAC address bits 0-15 553 * GEM_MAC_ADDR6 MAC control address bits 32-47 554 * GEM_MAC_ADDR7 MAC control address bits 16-31 555 * GEM_MAC_ADDR8 MAC control address bits 0-15 556 * GEM_MAC_ADDR_FILTER0 address filter bits 32-47 557 * GEM_MAC_ADDR_FILTER1 address filter bits 16-31 558 * GEM_MAC_ADDR_FILTER2 address filter bits 0-15 559 * GEM_MAC_ADR_FLT_MASK1_2 mask for GEM_MAC_ADDR_FILTER1 and 2 (8-bit) 560 * GEM_MAC_ADR_FLT_MASK0 mask for GEM_MAC_ADDR_FILTER0 561 * GEM_MAC_HASH0 hash table bits 240-255 562 * GEM_MAC_HASH1 hash table bits 224-239 563 * GEM_MAC_HASH2 hash table bits 208-223 564 * GEM_MAC_HASH3 hash table bits 192-207 565 * GEM_MAC_HASH4 hash table bits 176-191 566 * GEM_MAC_HASH5 hash table bits 160-175 567 * GEM_MAC_HASH6 hash table bits 144-159 568 * GEM_MAC_HASH7 hash table bits 128-143 569 * GEM_MAC_HASH8 hash table bits 112-127 570 * GEM_MAC_HASH9 hash table bits 96-111 571 * GEM_MAC_HASH10 hash table bits 80-95 572 * GEM_MAC_HASH11 hash table bits 64-79 573 * GEM_MAC_HASH12 hash table bits 48-63 574 * GEM_MAC_HASH13 hash table bits 32-47 575 * GEM_MAC_HASH14 hash table bits 16-31 576 * GEM_MAC_HASH15 hash table bits 0-15 577 */ 578 579 /* 580 * Recommended values for statistic registers: 581 * GEM_MAC_NORM_COLL_CNT 0x0000 582 * GEM_MAC_FIRST_COLL_CNT 0x0000 583 * GEM_MAC_EXCESS_COLL_CNT 0x0000 584 * GEM_MAC_LATE_COLL_CNT 0x0000 585 * GEM_MAC_DEFER_TMR_CNT 0x0000 586 * GEM_MAC_PEAK_ATTEMPTS 0x0000 587 * GEM_MAC_RX_FRAME_COUNT 0x0000 588 * GEM_MAC_RX_LEN_ERR_CNT 0x0000 589 * GEM_MAC_RX_ALIGN_ERR 0x0000 590 * GEM_MAC_RX_CRC_ERR_CNT 0x0000 591 * GEM_MAC_RX_CODE_VIOL 0x0000 592 */ 593 594 595 /* 596 * MIF Programmable Resources 597 * Section 3.1.5.8 598 * Bit-bang registers use low bit only 599 */ 600 #define GEM_MIF_BB_CLOCK 0x6200 /* MIF Bit-Bang Clock */ 601 #define GEM_MIF_BB_DATA 0x6204 /* MIF Bit-Bang Data */ 602 #define GEM_MIF_BB_OUTPUT_ENAB 0x6208 /* MIF Bit-Bang Output Enable */ 603 #define GEM_MIF_FRAME 0x620c /* MIF Frame/Output */ 604 #define GEM_MIF_CONFIG 0x6210 /* MIF Configuration */ 605 #define GEM_MIF_INTERRUPT_MASK 0x6214 /* MIF Mask */ 606 #define GEM_MIF_BASIC_STATUS 0x6218 /* MIF Status */ 607 #define GEM_MIF_STATE_MACHINE 0x621c /* MIF State Machine */ 608 609 610 /* 611 * Bits in GEM_MIF_FRAME register 612 */ 613 #define GEM_MIF_FRAME_DATA 0x0000ffff /* Instruction payload */ 614 #define GEM_MIF_FRAME_TA0 0x00010000 /* TA bit, 1 for completion */ 615 #define GEM_MIF_FRAME_TA1 0x00020000 /* TA bits */ 616 #define GEM_MIF_FRAME_REG_ADDR 0x007c0000 /* Register address */ 617 #define GEM_MIF_FRAME_PHY_ADDR 0x0f800000 /* PHY address, should be 0 */ 618 #define GEM_MIF_FRAME_OP 0x30000000 /* operation - write/read */ 619 #define GEM_MIF_FRAME_START 0xc0000000 /* START bits */ 620 621 #define GEM_MIF_FRAME_READ 0x60020000 622 #define GEM_MIF_FRAME_WRITE 0x50020000 623 624 #define GEM_MIF_REG_SHIFT 18 625 #define GEM_MIF_PHY_SHIFT 23 626 627 628 /* 629 * Bits in GEM_MIF_CONFIG register 630 */ 631 #define GEM_MIF_CONFIG_PHY_SEL 0x00000001 /* PHY select, 0=MDIO_0 */ 632 #define GEM_MIF_CONFIG_POLL_ENA 0x00000002 /* poll enable */ 633 #define GEM_MIF_CONFIG_BB_ENA 0x00000004 /* bit bang enable */ 634 #define GEM_MIF_CONFIG_REG_ADR 0x000000f8 /* poll register address */ 635 #define GEM_MIF_CONFIG_MDI0 0x00000100 /* MDIO_0 B-B data/attached */ 636 #define GEM_MIF_CONFIG_MDI1 0x00000200 /* MDIO_1 B-B data/attached */ 637 #define GEM_MIF_CONFIG_PHY_ADR 0x00007c00 /* poll PHY address */ 638 /* MDIO_0 is onboard transceiver MDIO_1 is external, PHY addr for both is 0 */ 639 #define GEM_MIF_CONFIG_BITS "\177\020b\0PHYSEL\0b\1POLL\0b\2BBENA\0" \ 640 "b\x8MDIO0\0b\x9MDIO1\0\0" 641 642 643 /* 644 * Bits in GEM_MIF_BASIC_STATUS and GEM_MIF_INTERRUPT_MASK 645 * The Basic part is the last value read in the POLL field of the config 646 * register. 647 * The status part indicates the bits that have changed. 648 */ 649 #define GEM_MIF_STATUS 0x0000ffff 650 #define GEM_MIF_BASIC 0xffff0000 651 652 653 /* 654 * PCS/Serialink Registers 655 * Section 3.1.6 656 * DO NOT TOUCH THESE REGISTERS ON ERI -- IT HARD HANGS. 657 */ 658 #define GEM_MII_CONTROL 0x9000 /* PCS MII Control */ 659 #define GEM_MII_STATUS 0x9004 /* PCS MII Status */ 660 #define GEM_MII_ANAR 0x9008 /* PCS MII Advertisement */ 661 #define GEM_MII_ANLPAR 0x900c /* PCS MII Link Partner 662 Ability */ 663 #define GEM_MII_CONFIG 0x9010 /* PCS Configuration */ 664 #define GEM_MII_STATE_MACHINE 0x9014 /* PCS State Machine */ 665 #define GEM_MII_INTERRUP_STATUS 0x9018 /* PCS Interrupt Status */ 666 #define GEM_MII_DATAPATH_MODE 0x9050 /* Datapath Mode Register */ 667 #define GEM_MII_SLINK_CONTROL 0x9054 /* Serialink Control */ 668 #define GEM_MII_OUTPUT_SELECT 0x9058 /* Share Output Select */ 669 #define GEM_MII_SLINK_STATUS 0x905c /* Serialink Status */ 670 671 672 /* 673 * Bits in GEM_MII_CONTROL register 674 * PCS "BMCR" (Basic Mode Control Reg) 675 * Default: 0x1040 676 * AUTONEG and RESET self clear when relevant process is completed. 677 */ 678 #define GEM_MII_1GB_SPEED_SEL 0x00000040 /* 1000Mb/s, always 1 */ 679 #define GEM_MII_CONTROL_COL_TST 0x00000080 /* collision test */ 680 #define GEM_MII_CONTROL_FDUPLEX 0x00000100 /* full duplex, always 0 */ 681 #define GEM_MII_CONTROL_RAN 0x00000200 /* restart auto negotiation */ 682 #define GEM_MII_CONTROL_ISOLATE 0x00000400 /* isolate PHY, ignored */ 683 #define GEM_MII_CONTROL_POWERDN 0x00000800 /* power down, ignored */ 684 #define GEM_MII_CONTROL_AUTONEG 0x00001000 /* auto negotiation enabled */ 685 #define GEM_MII_CONTROL_SPEED 0x00002000 /* speed select, ignored */ 686 #define GEM_MII_CONTROL_LOOPBK 0x00004000 /* Serialink loopback */ 687 #define GEM_MII_CONTROL_RESET 0x00008000 /* Reset PCS */ 688 #define GEM_MII_CONTROL_BITS "\177\020b\7COLTST\0b\x8_FD\0b\x9RAN\0" \ 689 "b\xaISOLATE\0b\xbPWRDWN\0b\xc_ANEG\0" \ 690 "b\xdGIGE\0b\xeLOOP\0b\xfRESET\0\0" 691 692 693 /* 694 * Bits in GEM_MII_STATUS register. 695 * PCS "BMSR" (Basic Mode Status Reg) 696 * Default: 0x0108 697 */ 698 #define GEM_MII_STATUS_EXTCAP 0x00000001 /* extended capability, always 0 */ 699 #define GEM_MII_STATUS_JABBER 0x00000002 /* jabber detected, always 0 */ 700 #define GEM_MII_STATUS_LINK_STS 0x00000004 /* link status, 1=up */ 701 #define GEM_MII_STATUS_ACFG 0x00000008 /* can auto neg, always 1 */ 702 #define GEM_MII_STATUS_REM_FLT 0x00000010 /* remote fault detected */ 703 #define GEM_MII_STATUS_ANEG_CPT 0x00000020 /* auto negotiate complete */ 704 #define GEM_MII_STATUS_EXT_STS 0x00000100 /* Is 1000Base-X, always 1 */ 705 #define GEM_MII_STATUS_GB_HDX 0x00000200 /* can perform GBit HDX */ 706 #define GEM_MII_STATUS_GB_FDX 0x00000400 /* can perform GBit FDX */ 707 #define GEM_MII_STATUS_BITS "\177\020b\0EXTCAP\0b\1JABBER\0b\2LINKSTS\0" \ 708 "b\3ACFG\0b\4REMFLT\0b\5ANEGCPT\0b\x9GBHDX\0" \ 709 "b\xaGBFDX\0\0" 710 711 712 /* 713 * Bits in GEM_MII_ANAR and GEM_MII_ANLPAR registers 714 * GEM_MII_ANAR contains our capabilities for auto- negotiation 715 * (Default: 0x00e0) and GEM_MII_ANLPAR contains the link partners 716 * abilities and is only valid after auto-negotiation completes. 717 */ 718 #define GEM_MII_ANEG_FUL_DUPLX 0x00000020 /* can do 1000Base-X FDX */ 719 #define GEM_MII_ANEG_HLF_DUPLX 0x00000040 /* can do 1000Base-X HDX */ 720 #define GEM_MII_ANEG_SYM_PAUSE 0x00000080 /* can do symmetric pause */ 721 #define GEM_MII_ANEG_ASYM_PAUSE 0x00000100 /* can do asymmetric pause */ 722 #define GEM_MII_ANEG_RF 0x00003000 /* advertise remote fault */ 723 #define GEM_MII_ANEG_ACK 0x00004000 /* ack reception of 724 Link Partner Capability */ 725 #define GEM_MII_ANEG_NP 0x00008000 /* next page bit, always 0 */ 726 #define GEM_MII_ANEG_BITS "\177\020b\5FDX\0b\6HDX\0b\7SYMPAUSE\0" \ 727 "\b\x8_ASYMPAUSE\0\b\xdREMFLT\0\b\xeLPACK\0" \ 728 "\b\xfNPBIT\0\0" 729 730 731 /* 732 * Bits in GEM_MII_CONFIG register 733 * Default: 0x0 734 * GEM_MII_CONFIG_ENABLE must be 0 when modifiying the GEM_MII_ANAR 735 * register. To isolate the MC from the media, set this bit to 0 and 736 * restart auto-negotiation in GEM_MII_CONTROL. 737 */ 738 #define GEM_MII_CONFIG_ENABLE 0x00000001 /* Enable PCS */ 739 #define GEM_MII_CONFIG_SDO 0x00000002 /* Signal Detect Override */ 740 #define GEM_MII_CONFIG_SDL 0x00000004 /* Signal Detect active low */ 741 #define GEM_MII_CONFIG_TIMER 0x0000000e /* link monitor timer values */ 742 #define GEM_MII_CONFIG_JS 0x00000018 /* Jitter Study, 0 normal 743 * 1 high freq, 2 low freq */ 744 #define GEM_MII_CONFIG_ANTO 0x00000020 /* 10ms ANEG timer override */ 745 #define GEM_MII_CONFIG_BITS "\177\020b\0PCSENA\0\0" 746 747 748 /* 749 * Bits in GEM_MII_STATE_MACHINE register 750 * XXX These are best guesses from observed behavior. 751 */ 752 #define GEM_MII_FSM_STOP 0x00000000 /* stopped */ 753 #define GEM_MII_FSM_RUN 0x00000001 /* running */ 754 #define GEM_MII_FSM_UNKWN 0x00000100 /* unknown */ 755 #define GEM_MII_FSM_DONE 0x00000101 /* complete */ 756 757 758 /* 759 * Bits in GEM_MII_INTERRUP_STATUS register 760 * No mask register; mask with the global interrupt mask register. 761 */ 762 #define GEM_MII_INTERRUP_LINK 0x00000004 /* PCS link status change */ 763 764 765 /* 766 * Bits in GEM_MII_DATAPATH_MODE register 767 * Default: none 768 */ 769 #define GEM_MII_DATAPATH_SERIAL 0x00000001 /* Use internal Serialink */ 770 #define GEM_MII_DATAPATH_SERDES 0x00000002 /* Use PCS via 10bit interfac */ 771 #define GEM_MII_DATAPATH_MII 0x00000004 /* Use {G}MII, not PCS */ 772 #define GEM_MII_DATAPATH_MIIOUT 0x00000008 /* Set serial output on GMII */ 773 #define GEM_MII_DATAPATH_BITS "\177\020" \ 774 "b\0SERIAL\0b\1SERDES\0b\2MII\0b\3MIIOUT\0\0" 775 776 777 /* 778 * Bits in GEM_MII_SLINK_CONTROL register 779 * Default: 0x000 780 */ 781 #define GEM_MII_SLINK_LOOPBACK 0x00000001 /* enable loopback on Serialink 782 disable loopback on SERDES */ 783 #define GEM_MII_SLINK_EN_SYNC_D 0x00000002 /* enable sync detection */ 784 #define GEM_MII_SLINK_LOCK_REF 0x00000004 /* lock reference clock */ 785 #define GEM_MII_SLINK_EMPHASIS 0x00000018 /* enable emphasis */ 786 #define GEM_MII_SLINK_SELFTEST 0x000001c0 787 #define GEM_MII_SLINK_POWER_OFF 0x00000200 /* Power down Serialink block */ 788 #define GEM_MII_SLINK_RX_ZERO 0x00000c00 /* PLL input to Serialink */ 789 #define GEM_MII_SLINK_RX_POLL 0x00003000 /* PLL input to Serialink */ 790 #define GEM_MII_SLINK_TX_ZERO 0x0000c000 /* PLL input to Serialink */ 791 #define GEM_MII_SLINK_TX_POLL 0x00030000 /* PLL input to Serialink */ 792 #define GEM_MII_SLINK_CONTROL_BITS \ 793 "\177\020b\0LOOP\0b\1ENASYNC\0b\2LOCKREF" \ 794 "\0b\3EMPHASIS1\0b\4EMPHASIS2\0b\x9PWRDWN\0\0" 795 796 797 /* 798 * Bits in GEM_MII_OUTPUT_SELECT register 799 * Default: 0x0 800 */ 801 #define GEM_MII_PROM_ADDR 0x00000003 /* Test output multiplexor */ 802 803 804 /* 805 * Bits in GEM_MII_SLINK_STATUS register 806 * Default: 0x0 807 */ 808 #define GEM_MII_SLINK_TEST 0x00000000 /* undergoing test */ 809 #define GEM_MII_SLINK_LOCKED 0x00000001 /* waiting 500us lockrefn */ 810 #define GEM_MII_SLINK_COMMA 0x00000002 /* waiting for comma detect */ 811 #define GEM_MII_SLINK_SYNC 0x00000003 /* recv data synchronized */ 812 813 814 /* 815 * PCI Expansion ROM runtime access 816 * Sun GEMs map a 1MB space for the PCI Expansion ROM as the second half 817 * of the first register bank, although they only support up to 64KB ROMs. 818 */ 819 #define GEM_PCI_ROM_OFFSET 0x100000 820 #define GEM_PCI_ROM_SIZE 0x10000 821 822 823 /* Wired GEM PHY addresses */ 824 #define GEM_PHYAD_INTERNAL 1 825 #define GEM_PHYAD_EXTERNAL 0 826 827 /* 828 * GEM descriptor table structures. 829 */ 830 struct gem_desc { 831 volatile uint64_t gd_flags; 832 volatile uint64_t gd_addr; 833 }; 834 835 /* Transmit flags */ 836 #define GEM_TD_BUFSIZE 0x0000000000007fffLL 837 #define GEM_TD_CXSUM_START 0x00000000001f8000LL /* Cxsum start offset */ 838 #define GEM_TD_CXSUM_STARTSHFT 15 839 #define GEM_TD_CXSUM_STUFF 0x000000001fe00000LL /* Cxsum stuff offset */ 840 #define GEM_TD_CXSUM_STUFFSHFT 21 841 #define GEM_TD_CXSUM_ENABLE 0x0000000020000000LL /* Cxsum generation enable */ 842 #define GEM_TD_END_OF_PACKET 0x0000000040000000LL 843 #define GEM_TD_START_OF_PACKET 0x0000000080000000LL 844 #define GEM_TD_INTERRUPT_ME 0x0000000100000000LL /* Interrupt me now */ 845 #define GEM_TD_NO_CRC 0x0000000200000000LL /* do not insert crc */ 846 /* 847 * Only need to set GEM_TD_CXSUM_ENABLE, GEM_TD_CXSUM_STUFF, 848 * GEM_TD_CXSUM_START, and GEM_TD_INTERRUPT_ME in 1st descriptor of a group. 849 */ 850 851 /* Receive flags */ 852 #define GEM_RD_CHECKSUM 0x000000000000ffffLL /* is the complement */ 853 #define GEM_RD_BUFSIZE 0x000000007fff0000LL 854 #define GEM_RD_OWN 0x0000000080000000LL /* 1 - owned by h/w */ 855 #define GEM_RD_HASHVAL 0x0ffff00000000000LL 856 #define GEM_RD_HASH_PASS 0x1000000000000000LL /* passed hash filter */ 857 #define GEM_RD_ALTERNATE_MAC 0x2000000000000000LL /* Alternate MAC adrs */ 858 #define GEM_RD_BAD_CRC 0x4000000000000000LL 859 860 #define GEM_RD_BUFSHIFT 16 861 #define GEM_RD_BUFLEN(x) (((x)&GEM_RD_BUFSIZE)>>GEM_RD_BUFSHIFT) 862 863 #endif 864
Indexes created Mon Sep 29 15:09:53 GMT 2025