gemvar.h revision 1.17
1 /* $NetBSD: gemvar.h,v 1.17 2008/01/19 22:20:42 dyoung Exp $ */ 2 3 /* 4 * 5 * Copyright (C) 2001 Eduardo Horvath. 6 * All rights reserved. 7 * 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 */ 31 32 #ifndef _IF_GEMVAR_H 33 #define _IF_GEMVAR_H 34 35 36 #include "rnd.h" 37 38 #include <sys/queue.h> 39 #include <sys/callout.h> 40 41 #if NRND > 0 42 #include <sys/rnd.h> 43 #endif 44 45 /* 46 * Misc. definitions for the Sun ``Gem'' Ethernet controller family driver. 47 */ 48 49 /* 50 * Transmit descriptor list size. This is arbitrary, but allocate 51 * enough descriptors for 64 pending transmissions and 16 segments 52 * per packet. 53 */ 54 #define GEM_NTXSEGS 16 55 56 #define GEM_TXQUEUELEN 64 57 #define GEM_NTXDESC (GEM_TXQUEUELEN * GEM_NTXSEGS) 58 #define GEM_NTXDESC_MASK (GEM_NTXDESC - 1) 59 #define GEM_NEXTTX(x) ((x + 1) & GEM_NTXDESC_MASK) 60 61 /* 62 * Receive descriptor list size. We have one Rx buffer per incoming 63 * packet, so this logic is a little simpler. 64 */ 65 #define GEM_NRXDESC 128 66 #define GEM_NRXDESC_MASK (GEM_NRXDESC - 1) 67 #define GEM_PREVRX(x) ((x - 1) & GEM_NRXDESC_MASK) 68 #define GEM_NEXTRX(x) ((x + 1) & GEM_NRXDESC_MASK) 69 70 /* 71 * Control structures are DMA'd to the GEM chip. We allocate them in 72 * a single clump that maps to a single DMA segment to make several things 73 * easier. 74 */ 75 struct gem_control_data { 76 /* 77 * The transmit descriptors. 78 */ 79 struct gem_desc gcd_txdescs[GEM_NTXDESC]; 80 81 /* 82 * The receive descriptors. 83 */ 84 struct gem_desc gcd_rxdescs[GEM_NRXDESC]; 85 }; 86 87 #define GEM_CDOFF(x) offsetof(struct gem_control_data, x) 88 #define GEM_CDTXOFF(x) GEM_CDOFF(gcd_txdescs[(x)]) 89 #define GEM_CDRXOFF(x) GEM_CDOFF(gcd_rxdescs[(x)]) 90 91 /* 92 * Software state for transmit jobs. 93 */ 94 struct gem_txsoft { 95 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 96 bus_dmamap_t txs_dmamap; /* our DMA map */ 97 int txs_firstdesc; /* first descriptor in packet */ 98 int txs_lastdesc; /* last descriptor in packet */ 99 int txs_ndescs; /* number of descriptors */ 100 SIMPLEQ_ENTRY(gem_txsoft) txs_q; 101 }; 102 103 SIMPLEQ_HEAD(gem_txsq, gem_txsoft); 104 105 /* 106 * Software state for receive jobs. 107 */ 108 struct gem_rxsoft { 109 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 110 bus_dmamap_t rxs_dmamap; /* our DMA map */ 111 }; 112 113 /* 114 * Software state per device. 115 */ 116 struct gem_softc { 117 struct device sc_dev; /* generic device information */ 118 struct ethercom sc_ethercom; /* ethernet common data */ 119 struct mii_data sc_mii; /* MII media control */ 120 struct callout sc_tick_ch; /* tick callout */ 121 122 /* The following bus handles are to be provided by the bus front-end */ 123 bus_space_tag_t sc_bustag; /* bus tag */ 124 bus_dma_tag_t sc_dmatag; /* bus dma tag */ 125 bus_dmamap_t sc_dmamap; /* bus dma handle */ 126 bus_space_handle_t sc_h1; /* bus space handle for bank 1 regs */ 127 bus_space_handle_t sc_h2; /* bus space handle for bank 2 regs */ 128 129 int sc_phys[2]; /* MII instance -> PHY map */ 130 131 int sc_mif_config; /* Selected MII reg setting */ 132 uint32_t sc_mii_anar; /* copy of PCS GEM_MII_ANAR register */ 133 int sc_mii_media; /* Media selected for PCS MII */ 134 135 u_int sc_variant; /* which GEM are we dealing with? */ 136 #define GEM_UNKNOWN 0 /* don't know */ 137 #define GEM_SUN_GEM 1 /* Sun GEM variant */ 138 #define GEM_SUN_ERI 2 /* Sun ERI variant */ 139 #define GEM_APPLE_GMAC 3 /* Apple GMAC variant */ 140 #define GEM_APPLE_K2_GMAC 4 /* Apple K2 GMAC */ 141 142 #define GEM_IS_APPLE(sc) \ 143 ((sc)->sc_variant == GEM_APPLE_GMAC || \ 144 (sc)->sc_variant == GEM_APPLE_K2_GMAC) 145 146 u_int sc_flags; /* */ 147 short sc_if_flags; /* copy of ifp->if_flags */ 148 #define GEM_GIGABIT 0x0001 /* has a gigabit PHY */ 149 #define GEM_LINK 0x0002 /* link is up */ 150 #define GEM_PCI 0x0004 /* XXX PCI busses are little-endian */ 151 #define GEM_SERDES 0x0008 /* use the SERDES */ 152 #define GEM_SERIAL 0x0010 /* use the serial link */ 153 154 void *sc_sdhook; /* shutdown hook */ 155 void *sc_powerhook; /* power management hook */ 156 157 /* 158 * Ring buffer DMA stuff. 159 */ 160 bus_dma_segment_t sc_cdseg; /* control data memory */ 161 int sc_cdnseg; /* number of segments */ 162 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 163 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 164 165 bus_dmamap_t sc_nulldmamap; /* for small packets padding */ 166 167 /* 168 * Software state for transmit and receive descriptors. 169 */ 170 struct gem_txsoft sc_txsoft[GEM_TXQUEUELEN]; 171 struct gem_rxsoft sc_rxsoft[GEM_NRXDESC]; 172 173 /* 174 * Control data structures. 175 */ 176 struct gem_control_data *sc_control_data; 177 #define sc_txdescs sc_control_data->gcd_txdescs 178 #define sc_rxdescs sc_control_data->gcd_rxdescs 179 180 int sc_txfree; /* number of free Tx descriptors */ 181 int sc_txnext; /* next ready Tx descriptor */ 182 int sc_txwin; /* Tx descriptors since last Tx int */ 183 184 struct gem_txsq sc_txfreeq; /* free Tx descsofts */ 185 struct gem_txsq sc_txdirtyq; /* dirty Tx descsofts */ 186 187 int sc_rxptr; /* next ready RX descriptor/descsoft */ 188 int sc_rxfifosize; /* Rx FIFO size (bytes) */ 189 190 /* ========== */ 191 int sc_inited; 192 int sc_meminited; 193 int sc_debug; 194 void *sc_sh; /* shutdownhook cookie */ 195 196 /* Special hardware hooks */ 197 void (*sc_hwreset)(struct gem_softc *); 198 void (*sc_hwinit)(struct gem_softc *); 199 200 #if NRND > 0 201 rndsource_element_t rnd_source; 202 #endif 203 204 struct evcnt sc_ev_intr; 205 #ifdef GEM_COUNTERS 206 struct evcnt sc_ev_txint; 207 struct evcnt sc_ev_rxint; 208 struct evcnt sc_ev_rxnobuf; 209 struct evcnt sc_ev_rxfull; 210 struct evcnt sc_ev_rxhist[9]; 211 #endif 212 }; 213 214 #ifdef GEM_COUNTERS 215 #define GEM_COUNTER_INCR(sc, ctr) ((void) (sc->ctr.ev_count++)) 216 #else 217 #define GEM_COUNTER_INCR(sc, ctr) ((void) sc) 218 #endif 219 220 221 #define GEM_DMA_READ(sc, v) \ 222 (((sc)->sc_flags & GEM_PCI) ? le64toh(v) : be64toh(v)) 223 #define GEM_DMA_WRITE(sc, v) \ 224 (((sc)->sc_flags & GEM_PCI) ? htole64(v) : htobe64(v)) 225 226 #define GEM_CDTXADDR(sc, x) ((sc)->sc_cddma + GEM_CDTXOFF((x))) 227 #define GEM_CDRXADDR(sc, x) ((sc)->sc_cddma + GEM_CDRXOFF((x))) 228 229 #define GEM_CDADDR(sc) ((sc)->sc_cddma + GEM_CDOFF) 230 231 #define GEM_CDTXSYNC(sc, x, n, ops) \ 232 do { \ 233 int __x, __n; \ 234 \ 235 __x = (x); \ 236 __n = (n); \ 237 \ 238 /* If it will wrap around, sync to the end of the ring. */ \ 239 if ((__x + __n) > GEM_NTXDESC) { \ 240 bus_dmamap_sync((sc)->sc_dmatag, (sc)->sc_cddmamap, \ 241 GEM_CDTXOFF(__x), sizeof(struct gem_desc) * \ 242 (GEM_NTXDESC - __x), (ops)); \ 243 __n -= (GEM_NTXDESC - __x); \ 244 __x = 0; \ 245 } \ 246 \ 247 /* Now sync whatever is left. */ \ 248 bus_dmamap_sync((sc)->sc_dmatag, (sc)->sc_cddmamap, \ 249 GEM_CDTXOFF(__x), sizeof(struct gem_desc) * __n, (ops)); \ 250 } while (0) 251 252 #define GEM_CDRXSYNC(sc, x, ops) \ 253 bus_dmamap_sync((sc)->sc_dmatag, (sc)->sc_cddmamap, \ 254 GEM_CDRXOFF((x)), sizeof(struct gem_desc), (ops)) 255 256 #define GEM_CDSYNC(sc, ops) \ 257 bus_dmamap_sync((sc)->sc_dmatag, (sc)->sc_cddmamap, \ 258 0, sizeof(struct gem_control_data), (ops)) 259 260 #define GEM_INIT_RXDESC(sc, x) \ 261 do { \ 262 struct gem_rxsoft *__rxs = &sc->sc_rxsoft[(x)]; \ 263 struct gem_desc *__rxd = &sc->sc_rxdescs[(x)]; \ 264 struct mbuf *__m = __rxs->rxs_mbuf; \ 265 \ 266 __m->m_data = __m->m_ext.ext_buf; \ 267 __rxd->gd_addr = \ 268 GEM_DMA_WRITE((sc), __rxs->rxs_dmamap->dm_segs[0].ds_addr); \ 269 __rxd->gd_flags = \ 270 GEM_DMA_WRITE((sc), \ 271 (((__m->m_ext.ext_size)<<GEM_RD_BUFSHIFT) \ 272 & GEM_RD_BUFSIZE) | GEM_RD_OWN); \ 273 GEM_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 274 } while (0) 275 276 #define GEM_UPDATE_RXDESC(sc, x) \ 277 do { \ 278 struct gem_rxsoft *__rxs = &sc->sc_rxsoft[(x)]; \ 279 struct gem_desc *__rxd = &sc->sc_rxdescs[(x)]; \ 280 struct mbuf *__m = __rxs->rxs_mbuf; \ 281 \ 282 __rxd->gd_flags = \ 283 GEM_DMA_WRITE((sc), \ 284 (((__m->m_ext.ext_size)<<GEM_RD_BUFSHIFT) \ 285 & GEM_RD_BUFSIZE) | GEM_RD_OWN); \ 286 } while (0) 287 288 #ifdef _KERNEL 289 void gem_attach(struct gem_softc *, const uint8_t *); 290 int gem_intr(void *); 291 292 void gem_reset(struct gem_softc *); 293 #endif /* _KERNEL */ 294 295 296 #endif 297
Indexes created Sun Oct 19 18:09:56 GMT 2025