gemvar.h revision 1.7
1 /* $NetBSD: gemvar.h,v 1.7 2002/05/11 00:36:03 matt Exp $ */ 2 3 /* 4 * 5 * Copyright (C) 2001 Eduardo Horvath. 6 * All rights reserved. 7 * 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 */ 31 32 #ifndef _IF_GEMVAR_H 33 #define _IF_GEMVAR_H 34 35 36 #include "rnd.h" 37 38 #include <sys/queue.h> 39 #include <sys/callout.h> 40 41 #if NRND > 0 42 #include <sys/rnd.h> 43 #endif 44 45 /* 46 * Misc. definitions for the Sun ``Gem'' Ethernet controller family driver. 47 */ 48 49 /* 50 * Transmit descriptor list size. This is arbitrary, but allocate 51 * enough descriptors for 64 pending transmissions and 16 segments 52 * per packet. 53 */ 54 #define GEM_NTXSEGS 16 55 56 #define GEM_TXQUEUELEN 64 57 #define GEM_NTXDESC (GEM_TXQUEUELEN * GEM_NTXSEGS) 58 #define GEM_NTXDESC_MASK (GEM_NTXDESC - 1) 59 #define GEM_NEXTTX(x) ((x + 1) & GEM_NTXDESC_MASK) 60 61 /* 62 * Receive descriptor list size. We have one Rx buffer per incoming 63 * packet, so this logic is a little simpler. 64 */ 65 #define GEM_NRXDESC 128 66 #define GEM_NRXDESC_MASK (GEM_NRXDESC - 1) 67 #define GEM_NEXTRX(x) ((x + 1) & GEM_NRXDESC_MASK) 68 69 /* 70 * Control structures are DMA'd to the GEM chip. We allocate them in 71 * a single clump that maps to a single DMA segment to make several things 72 * easier. 73 */ 74 struct gem_control_data { 75 /* 76 * The transmit descriptors. 77 */ 78 struct gem_desc gcd_txdescs[GEM_NTXDESC]; 79 80 /* 81 * The receive descriptors. 82 */ 83 struct gem_desc gcd_rxdescs[GEM_NRXDESC]; 84 }; 85 86 #define GEM_CDOFF(x) offsetof(struct gem_control_data, x) 87 #define GEM_CDTXOFF(x) GEM_CDOFF(gcd_txdescs[(x)]) 88 #define GEM_CDRXOFF(x) GEM_CDOFF(gcd_rxdescs[(x)]) 89 90 /* 91 * Software state for transmit jobs. 92 */ 93 struct gem_txsoft { 94 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 95 bus_dmamap_t txs_dmamap; /* our DMA map */ 96 int txs_firstdesc; /* first descriptor in packet */ 97 int txs_lastdesc; /* last descriptor in packet */ 98 int txs_ndescs; /* number of descriptors */ 99 SIMPLEQ_ENTRY(gem_txsoft) txs_q; 100 }; 101 102 SIMPLEQ_HEAD(gem_txsq, gem_txsoft); 103 104 /* 105 * Software state for receive jobs. 106 */ 107 struct gem_rxsoft { 108 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 109 bus_dmamap_t rxs_dmamap; /* our DMA map */ 110 }; 111 112 /* 113 * Software state per device. 114 */ 115 struct gem_softc { 116 struct device sc_dev; /* generic device information */ 117 struct ethercom sc_ethercom; /* ethernet common data */ 118 struct mii_data sc_mii; /* MII media control */ 119 #define sc_media sc_mii.mii_media/* shorthand */ 120 struct callout sc_tick_ch; /* tick callout */ 121 122 /* The following bus handles are to be provided by the bus front-end */ 123 bus_space_tag_t sc_bustag; /* bus tag */ 124 bus_dma_tag_t sc_dmatag; /* bus dma tag */ 125 bus_dmamap_t sc_dmamap; /* bus dma handle */ 126 bus_space_handle_t sc_h; /* bus space handle for all regs */ 127 128 int sc_phys[2]; /* MII instance -> PHY map */ 129 130 int sc_mif_config; /* Selected MII reg setting */ 131 132 int sc_pci; /* XXXXX -- PCI buses are LE. */ 133 u_int sc_variant; /* which GEM are we dealing with? */ 134 #define GEM_UNKNOWN 0 /* don't know */ 135 #define GEM_SUN_GEM 1 /* Sun GEM variant */ 136 #define GEM_APPLE_GMAC 2 /* Apple GMAC variant */ 137 138 u_int sc_flags; /* */ 139 #define GEM_GIGABIT 0x0001 /* has a gigabit PHY */ 140 141 void *sc_sdhook; /* shutdown hook */ 142 void *sc_powerhook; /* power management hook */ 143 144 /* 145 * Ring buffer DMA stuff. 146 */ 147 bus_dma_segment_t sc_cdseg; /* control data memory */ 148 int sc_cdnseg; /* number of segments */ 149 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 150 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 151 152 /* 153 * Software state for transmit and receive descriptors. 154 */ 155 struct gem_txsoft sc_txsoft[GEM_TXQUEUELEN]; 156 struct gem_rxsoft sc_rxsoft[GEM_NRXDESC]; 157 158 /* 159 * Control data structures. 160 */ 161 struct gem_control_data *sc_control_data; 162 #define sc_txdescs sc_control_data->gcd_txdescs 163 #define sc_rxdescs sc_control_data->gcd_rxdescs 164 165 int sc_txfree; /* number of free Tx descriptors */ 166 int sc_txnext; /* next ready Tx descriptor */ 167 int sc_txwin; /* Tx descriptors since last Tx int */ 168 169 struct gem_txsq sc_txfreeq; /* free Tx descsofts */ 170 struct gem_txsq sc_txdirtyq; /* dirty Tx descsofts */ 171 172 int sc_rxptr; /* next ready RX descriptor/descsoft */ 173 int sc_rxfifosize; /* Rx FIFO size (bytes) */ 174 175 /* ========== */ 176 int sc_inited; 177 int sc_debug; 178 void *sc_sh; /* shutdownhook cookie */ 179 180 /* Special hardware hooks */ 181 void (*sc_hwreset) __P((struct gem_softc *)); 182 void (*sc_hwinit) __P((struct gem_softc *)); 183 184 #if NRND > 0 185 rndsource_element_t rnd_source; 186 #endif 187 }; 188 189 190 #define GEM_DMA_READ(sc, v) (((sc)->sc_pci) ? le64toh(v) : be64toh(v)) 191 #define GEM_DMA_WRITE(sc, v) (((sc)->sc_pci) ? htole64(v) : htobe64(v)) 192 193 #define GEM_CDTXADDR(sc, x) ((sc)->sc_cddma + GEM_CDTXOFF((x))) 194 #define GEM_CDRXADDR(sc, x) ((sc)->sc_cddma + GEM_CDRXOFF((x))) 195 196 #define GEM_CDSPADDR(sc) ((sc)->sc_cddma + GEM_CDSPOFF) 197 198 #define GEM_CDTXSYNC(sc, x, n, ops) \ 199 do { \ 200 int __x, __n; \ 201 \ 202 __x = (x); \ 203 __n = (n); \ 204 \ 205 /* If it will wrap around, sync to the end of the ring. */ \ 206 if ((__x + __n) > GEM_NTXDESC) { \ 207 bus_dmamap_sync((sc)->sc_dmatag, (sc)->sc_cddmamap, \ 208 GEM_CDTXOFF(__x), sizeof(struct gem_desc) * \ 209 (GEM_NTXDESC - __x), (ops)); \ 210 __n -= (GEM_NTXDESC - __x); \ 211 __x = 0; \ 212 } \ 213 \ 214 /* Now sync whatever is left. */ \ 215 bus_dmamap_sync((sc)->sc_dmatag, (sc)->sc_cddmamap, \ 216 GEM_CDTXOFF(__x), sizeof(struct gem_desc) * __n, (ops)); \ 217 } while (0) 218 219 #define GEM_CDRXSYNC(sc, x, ops) \ 220 bus_dmamap_sync((sc)->sc_dmatag, (sc)->sc_cddmamap, \ 221 GEM_CDRXOFF((x)), sizeof(struct gem_desc), (ops)) 222 223 #define GEM_CDSPSYNC(sc, ops) \ 224 bus_dmamap_sync((sc)->sc_dmatag, (sc)->sc_cddmamap, \ 225 GEM_CDSPOFF, GEM_SETUP_PACKET_LEN, (ops)) 226 227 #define GEM_INIT_RXDESC(sc, x) \ 228 do { \ 229 struct gem_rxsoft *__rxs = &sc->sc_rxsoft[(x)]; \ 230 struct gem_desc *__rxd = &sc->sc_rxdescs[(x)]; \ 231 struct mbuf *__m = __rxs->rxs_mbuf; \ 232 \ 233 __m->m_data = __m->m_ext.ext_buf; \ 234 __rxd->gd_addr = \ 235 GEM_DMA_WRITE((sc), __rxs->rxs_dmamap->dm_segs[0].ds_addr); \ 236 __rxd->gd_flags = \ 237 GEM_DMA_WRITE((sc), \ 238 (((__m->m_ext.ext_size)<<GEM_RD_BUFSHIFT) \ 239 & GEM_RD_BUFSIZE) | GEM_RD_OWN); \ 240 GEM_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 241 } while (0) 242 243 #ifdef _KERNEL 244 void gem_attach __P((struct gem_softc *, const uint8_t *)); 245 int gem_intr __P((void *)); 246 247 void gem_reset __P((struct gem_softc *)); 248 #endif /* _KERNEL */ 249 250 251 #endif 252
Indexes created Thu Sep 25 08:09:54 GMT 2025