hd64570.c revision 1.12
1 /* $NetBSD: hd64570.c,v 1.12 2000/12/12 18:00:23 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1999 Christian E. Hopps 5 * Copyright (c) 1998 Vixie Enterprises 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of Vixie Enterprises nor the names 18 * of its contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY VIXIE ENTERPRISES AND 22 * CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 23 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL VIXIE ENTERPRISES OR 26 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * This software has been written for Vixie Enterprises by Michael Graff 36 * <explorer (at) flame.org>. To learn more about Vixie Enterprises, see 37 * ``http://www.vix.com''. 38 */ 39 40 /* 41 * TODO: 42 * 43 * o teach the receive logic about errors, and about long frames that 44 * span more than one input buffer. (Right now, receive/transmit is 45 * limited to one descriptor's buffer space, which is MTU + 4 bytes. 46 * This is currently 1504, which is large enough to hold the HDLC 47 * header and the packet itself. Packets which are too long are 48 * silently dropped on transmit and silently dropped on receive. 49 * o write code to handle the msci interrupts, needed only for CD 50 * and CTS changes. 51 * o consider switching back to a "queue tx with DMA active" model which 52 * should help sustain outgoing traffic 53 * o through clever use of bus_dma*() functions, it should be possible 54 * to map the mbuf's data area directly into a descriptor transmit 55 * buffer, removing the need to allocate extra memory. If, however, 56 * we run out of descriptors for this, we will need to then allocate 57 * one large mbuf, copy the fragmented chain into it, and put it onto 58 * a single descriptor. 59 * o use bus_dmamap_sync() with the right offset and lengths, rather 60 * than cheating and always sync'ing the whole region. 61 * 62 * o perhaps allow rx and tx to be in more than one page 63 * if not using dma. currently the assumption is that 64 * rx uses a page and tx uses a page. 65 */ 66 67 #include "bpfilter.h" 68 #include "opt_inet.h" 69 #include "opt_iso.h" 70 71 #include <sys/param.h> 72 #include <sys/systm.h> 73 #include <sys/device.h> 74 #include <sys/mbuf.h> 75 #include <sys/socket.h> 76 #include <sys/sockio.h> 77 #include <sys/kernel.h> 78 79 #include <net/if.h> 80 #include <net/if_types.h> 81 #include <net/netisr.h> 82 83 #ifdef INET 84 #include <netinet/in.h> 85 #include <netinet/in_systm.h> 86 #include <netinet/in_var.h> 87 #include <netinet/ip.h> 88 #endif 89 90 #ifdef ISO 91 #include <net/if_llc.h> 92 #include <netiso/iso.h> 93 #include <netiso/iso_var.h> 94 #endif 95 96 #if NBPFILTER > 0 97 #include <net/bpf.h> 98 #endif 99 100 #include <machine/cpu.h> 101 #include <machine/bus.h> 102 #include <machine/intr.h> 103 104 #include <dev/pci/pcivar.h> 105 #include <dev/pci/pcireg.h> 106 #include <dev/pci/pcidevs.h> 107 108 #include <dev/ic/hd64570reg.h> 109 #include <dev/ic/hd64570var.h> 110 111 #define SCA_DEBUG_RX 0x0001 112 #define SCA_DEBUG_TX 0x0002 113 #define SCA_DEBUG_CISCO 0x0004 114 #define SCA_DEBUG_DMA 0x0008 115 #define SCA_DEBUG_RXPKT 0x0010 116 #define SCA_DEBUG_TXPKT 0x0020 117 #define SCA_DEBUG_INTR 0x0040 118 #define SCA_DEBUG_CLOCK 0x0080 119 120 #if 0 121 #define SCA_DEBUG_LEVEL ( 0xFFFF ) 122 #else 123 #define SCA_DEBUG_LEVEL 0 124 #endif 125 126 u_int32_t sca_debug = SCA_DEBUG_LEVEL; 127 128 #if SCA_DEBUG_LEVEL > 0 129 #define SCA_DPRINTF(l, x) do { \ 130 if ((l) & sca_debug) \ 131 printf x;\ 132 } while (0) 133 #else 134 #define SCA_DPRINTF(l, x) 135 #endif 136 137 #if 0 138 #define SCA_USE_FASTQ /* use a split queue, one for fast traffic */ 139 #endif 140 141 static inline void msci_write_1(sca_port_t *, u_int, u_int8_t); 142 static inline u_int8_t msci_read_1(sca_port_t *, u_int); 143 144 static inline void dmac_write_1(sca_port_t *, u_int, u_int8_t); 145 static inline void dmac_write_2(sca_port_t *, u_int, u_int16_t); 146 static inline u_int8_t dmac_read_1(sca_port_t *, u_int); 147 static inline u_int16_t dmac_read_2(sca_port_t *, u_int); 148 149 static void sca_msci_init(struct sca_softc *, sca_port_t *); 150 static void sca_dmac_init(struct sca_softc *, sca_port_t *); 151 static void sca_dmac_rxinit(sca_port_t *); 152 153 static int sca_dmac_intr(sca_port_t *, u_int8_t); 154 static int sca_msci_intr(sca_port_t *, u_int8_t); 155 156 static void sca_get_packets(sca_port_t *); 157 static int sca_frame_avail(sca_port_t *); 158 static void sca_frame_process(sca_port_t *); 159 static void sca_frame_read_done(sca_port_t *); 160 161 static void sca_port_starttx(sca_port_t *); 162 163 static void sca_port_up(sca_port_t *); 164 static void sca_port_down(sca_port_t *); 165 166 static int sca_output __P((struct ifnet *, struct mbuf *, struct sockaddr *, 167 struct rtentry *)); 168 static int sca_ioctl __P((struct ifnet *, u_long, caddr_t)); 169 static void sca_start __P((struct ifnet *)); 170 static void sca_watchdog __P((struct ifnet *)); 171 172 static struct mbuf *sca_mbuf_alloc(struct sca_softc *, caddr_t, u_int); 173 174 #if SCA_DEBUG_LEVEL > 0 175 static void sca_frame_print(sca_port_t *, sca_desc_t *, u_int8_t *); 176 #endif 177 178 179 #define sca_read_1(sc, reg) (sc)->sc_read_1(sc, reg) 180 #define sca_read_2(sc, reg) (sc)->sc_read_2(sc, reg) 181 #define sca_write_1(sc, reg, val) (sc)->sc_write_1(sc, reg, val) 182 #define sca_write_2(sc, reg, val) (sc)->sc_write_2(sc, reg, val) 183 184 #define sca_page_addr(sc, addr) ((bus_addr_t)(addr) & (sc)->scu_pagemask) 185 186 static inline void 187 msci_write_1(sca_port_t *scp, u_int reg, u_int8_t val) 188 { 189 sca_write_1(scp->sca, scp->msci_off + reg, val); 190 } 191 192 static inline u_int8_t 193 msci_read_1(sca_port_t *scp, u_int reg) 194 { 195 return sca_read_1(scp->sca, scp->msci_off + reg); 196 } 197 198 static inline void 199 dmac_write_1(sca_port_t *scp, u_int reg, u_int8_t val) 200 { 201 sca_write_1(scp->sca, scp->dmac_off + reg, val); 202 } 203 204 static inline void 205 dmac_write_2(sca_port_t *scp, u_int reg, u_int16_t val) 206 { 207 sca_write_2(scp->sca, scp->dmac_off + reg, val); 208 } 209 210 static inline u_int8_t 211 dmac_read_1(sca_port_t *scp, u_int reg) 212 { 213 return sca_read_1(scp->sca, scp->dmac_off + reg); 214 } 215 216 static inline u_int16_t 217 dmac_read_2(sca_port_t *scp, u_int reg) 218 { 219 return sca_read_2(scp->sca, scp->dmac_off + reg); 220 } 221 222 /* 223 * read the chain pointer 224 */ 225 static inline u_int16_t 226 sca_desc_read_chainp(struct sca_softc *sc, struct sca_desc *dp) 227 { 228 if (sc->sc_usedma) 229 return ((dp)->sd_chainp); 230 return (bus_space_read_2(sc->scu_memt, sc->scu_memh, 231 sca_page_addr(sc, dp) + offsetof(struct sca_desc, sd_chainp))); 232 } 233 234 /* 235 * write the chain pointer 236 */ 237 static inline void 238 sca_desc_write_chainp(struct sca_softc *sc, struct sca_desc *dp, u_int16_t cp) 239 { 240 if (sc->sc_usedma) 241 (dp)->sd_chainp = cp; 242 else 243 bus_space_write_2(sc->scu_memt, sc->scu_memh, 244 sca_page_addr(sc, dp) 245 + offsetof(struct sca_desc, sd_chainp), cp); 246 } 247 248 /* 249 * read the buffer pointer 250 */ 251 static inline u_int32_t 252 sca_desc_read_bufp(struct sca_softc *sc, struct sca_desc *dp) 253 { 254 u_int32_t address; 255 256 if (sc->sc_usedma) 257 address = dp->sd_bufp | dp->sd_hbufp << 16; 258 else { 259 address = bus_space_read_2(sc->scu_memt, sc->scu_memh, 260 sca_page_addr(sc, dp) + offsetof(struct sca_desc, sd_bufp)); 261 address |= bus_space_read_1(sc->scu_memt, sc->scu_memh, 262 sca_page_addr(sc, dp) 263 + offsetof(struct sca_desc, sd_hbufp)) << 16; 264 } 265 return (address); 266 } 267 268 /* 269 * write the buffer pointer 270 */ 271 static inline void 272 sca_desc_write_bufp(struct sca_softc *sc, struct sca_desc *dp, u_int32_t bufp) 273 { 274 if (sc->sc_usedma) { 275 dp->sd_bufp = bufp & 0xFFFF; 276 dp->sd_hbufp = (bufp & 0x00FF0000) >> 16; 277 } else { 278 bus_space_write_2(sc->scu_memt, sc->scu_memh, 279 sca_page_addr(sc, dp) + offsetof(struct sca_desc, sd_bufp), 280 bufp & 0xFFFF); 281 bus_space_write_1(sc->scu_memt, sc->scu_memh, 282 sca_page_addr(sc, dp) + offsetof(struct sca_desc, sd_hbufp), 283 (bufp & 0x00FF0000) >> 16); 284 } 285 } 286 287 /* 288 * read the buffer length 289 */ 290 static inline u_int16_t 291 sca_desc_read_buflen(struct sca_softc *sc, struct sca_desc *dp) 292 { 293 if (sc->sc_usedma) 294 return ((dp)->sd_buflen); 295 return (bus_space_read_2(sc->scu_memt, sc->scu_memh, 296 sca_page_addr(sc, dp) + offsetof(struct sca_desc, sd_buflen))); 297 } 298 299 /* 300 * write the buffer length 301 */ 302 static inline void 303 sca_desc_write_buflen(struct sca_softc *sc, struct sca_desc *dp, u_int16_t len) 304 { 305 if (sc->sc_usedma) 306 (dp)->sd_buflen = len; 307 else 308 bus_space_write_2(sc->scu_memt, sc->scu_memh, 309 sca_page_addr(sc, dp) 310 + offsetof(struct sca_desc, sd_buflen), len); 311 } 312 313 /* 314 * read the descriptor status 315 */ 316 static inline u_int8_t 317 sca_desc_read_stat(struct sca_softc *sc, struct sca_desc *dp) 318 { 319 if (sc->sc_usedma) 320 return ((dp)->sd_stat); 321 return (bus_space_read_1(sc->scu_memt, sc->scu_memh, 322 sca_page_addr(sc, dp) + offsetof(struct sca_desc, sd_stat))); 323 } 324 325 /* 326 * write the descriptor status 327 */ 328 static inline void 329 sca_desc_write_stat(struct sca_softc *sc, struct sca_desc *dp, u_int8_t stat) 330 { 331 if (sc->sc_usedma) 332 (dp)->sd_stat = stat; 333 else 334 bus_space_write_1(sc->scu_memt, sc->scu_memh, 335 sca_page_addr(sc, dp) + offsetof(struct sca_desc, sd_stat), 336 stat); 337 } 338 339 void 340 sca_init(struct sca_softc *sc) 341 { 342 /* 343 * Do a little sanity check: check number of ports. 344 */ 345 if (sc->sc_numports < 1 || sc->sc_numports > 2) 346 panic("sca can\'t handle more than 2 or less than 1 ports"); 347 348 /* 349 * disable DMA and MSCI interrupts 350 */ 351 sca_write_1(sc, SCA_DMER, 0); 352 sca_write_1(sc, SCA_IER0, 0); 353 sca_write_1(sc, SCA_IER1, 0); 354 sca_write_1(sc, SCA_IER2, 0); 355 356 /* 357 * configure interrupt system 358 */ 359 sca_write_1(sc, SCA_ITCR, 360 SCA_ITCR_INTR_PRI_MSCI | SCA_ITCR_ACK_NONE | SCA_ITCR_VOUT_IVR); 361 #if 0 362 /* these are for the intrerrupt ack cycle which we don't use */ 363 sca_write_1(sc, SCA_IVR, 0x40); 364 sca_write_1(sc, SCA_IMVR, 0x40); 365 #endif 366 367 /* 368 * set wait control register to zero wait states 369 */ 370 sca_write_1(sc, SCA_PABR0, 0); 371 sca_write_1(sc, SCA_PABR1, 0); 372 sca_write_1(sc, SCA_WCRL, 0); 373 sca_write_1(sc, SCA_WCRM, 0); 374 sca_write_1(sc, SCA_WCRH, 0); 375 376 /* 377 * disable DMA and reset status 378 */ 379 sca_write_1(sc, SCA_PCR, SCA_PCR_PR2); 380 381 /* 382 * disable transmit DMA for all channels 383 */ 384 sca_write_1(sc, SCA_DSR0 + SCA_DMAC_OFF_0, 0); 385 sca_write_1(sc, SCA_DCR0 + SCA_DMAC_OFF_0, SCA_DCR_ABRT); 386 sca_write_1(sc, SCA_DSR1 + SCA_DMAC_OFF_0, 0); 387 sca_write_1(sc, SCA_DCR1 + SCA_DMAC_OFF_0, SCA_DCR_ABRT); 388 sca_write_1(sc, SCA_DSR0 + SCA_DMAC_OFF_1, 0); 389 sca_write_1(sc, SCA_DCR0 + SCA_DMAC_OFF_1, SCA_DCR_ABRT); 390 sca_write_1(sc, SCA_DSR1 + SCA_DMAC_OFF_1, 0); 391 sca_write_1(sc, SCA_DCR1 + SCA_DMAC_OFF_1, SCA_DCR_ABRT); 392 393 /* 394 * enable DMA based on channel enable flags for each channel 395 */ 396 sca_write_1(sc, SCA_DMER, SCA_DMER_EN); 397 398 /* 399 * Should check to see if the chip is responding, but for now 400 * assume it is. 401 */ 402 } 403 404 /* 405 * initialize the port and attach it to the networking layer 406 */ 407 void 408 sca_port_attach(struct sca_softc *sc, u_int port) 409 { 410 sca_port_t *scp = &sc->sc_ports[port]; 411 struct ifnet *ifp; 412 static u_int ntwo_unit = 0; 413 414 scp->sca = sc; /* point back to the parent */ 415 416 scp->sp_port = port; 417 418 if (port == 0) { 419 scp->msci_off = SCA_MSCI_OFF_0; 420 scp->dmac_off = SCA_DMAC_OFF_0; 421 if(sc->sc_parent != NULL) 422 ntwo_unit=sc->sc_parent->dv_unit * 2 + 0; 423 else 424 ntwo_unit = 0; /* XXX */ 425 } else { 426 scp->msci_off = SCA_MSCI_OFF_1; 427 scp->dmac_off = SCA_DMAC_OFF_1; 428 if(sc->sc_parent != NULL) 429 ntwo_unit=sc->sc_parent->dv_unit * 2 + 1; 430 else 431 ntwo_unit = 1; /* XXX */ 432 } 433 434 sca_msci_init(sc, scp); 435 sca_dmac_init(sc, scp); 436 437 /* 438 * attach to the network layer 439 */ 440 ifp = &scp->sp_if; 441 sprintf(ifp->if_xname, "ntwo%d", ntwo_unit); 442 ifp->if_softc = scp; 443 ifp->if_mtu = SCA_MTU; 444 ifp->if_flags = IFF_POINTOPOINT | IFF_MULTICAST; 445 ifp->if_type = IFT_PTPSERIAL; 446 ifp->if_hdrlen = HDLC_HDRLEN; 447 ifp->if_ioctl = sca_ioctl; 448 ifp->if_output = sca_output; 449 ifp->if_watchdog = sca_watchdog; 450 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 451 scp->linkq.ifq_maxlen = 5; /* if we exceed this we are hosed already */ 452 #ifdef SCA_USE_FASTQ 453 scp->fastq.ifq_maxlen = IFQ_MAXLEN; 454 #endif 455 if_attach(ifp); 456 457 #if NBPFILTER > 0 458 bpfattach(ifp, DLT_HDLC, HDLC_HDRLEN); 459 #endif 460 461 if (sc->sc_parent == NULL) 462 printf("%s: port %d\n", ifp->if_xname, port); 463 else 464 printf("%s at %s port %d\n", 465 ifp->if_xname, sc->sc_parent->dv_xname, port); 466 467 /* 468 * reset the last seen times on the cisco keepalive protocol 469 */ 470 scp->cka_lasttx = time.tv_usec; 471 scp->cka_lastrx = 0; 472 } 473 474 #if 0 475 /* 476 * returns log2(div), sets 'tmc' for the required freq 'hz' 477 */ 478 static u_int8_t 479 sca_msci_get_baud_rate_values(u_int32_t hz, u_int8_t *tmcp) 480 { 481 u_int32_t tmc, div; 482 u_int32_t clock; 483 484 /* clock hz = (chipclock / tmc) / 2^(div); */ 485 /* 486 * TD == tmc * 2^(n) 487 * 488 * note: 489 * 1 <= TD <= 256 TD is inc of 1 490 * 2 <= TD <= 512 TD is inc of 2 491 * 4 <= TD <= 1024 TD is inc of 4 492 * ... 493 * 512 <= TD <= 256*512 TD is inc of 512 494 * 495 * so note there are overlaps. We lose prec 496 * as div increases so we wish to minize div. 497 * 498 * basically we want to do 499 * 500 * tmc = chip / hz, but have tmc <= 256 501 */ 502 503 /* assume system clock is 9.8304Mhz or 9830400hz */ 504 clock = clock = 9830400 >> 1; 505 506 /* round down */ 507 div = 0; 508 while ((tmc = clock / hz) > 256 || (tmc == 256 && (clock / tmc) > hz)) { 509 clock >>= 1; 510 div++; 511 } 512 if (clock / tmc > hz) 513 tmc++; 514 if (!tmc) 515 tmc = 1; 516 517 if (div > SCA_RXS_DIV_512) { 518 /* set to maximums */ 519 div = SCA_RXS_DIV_512; 520 tmc = 0; 521 } 522 523 *tmcp = (tmc & 0xFF); /* 0 == 256 */ 524 return (div & 0xFF); 525 } 526 #endif 527 528 /* 529 * initialize the port's MSCI 530 */ 531 static void 532 sca_msci_init(struct sca_softc *sc, sca_port_t *scp) 533 { 534 /* reset the channel */ 535 msci_write_1(scp, SCA_CMD0, SCA_CMD_RESET); 536 537 msci_write_1(scp, SCA_MD00, 538 ( SCA_MD0_CRC_1 539 | SCA_MD0_CRC_CCITT 540 | SCA_MD0_CRC_ENABLE 541 | SCA_MD0_MODE_HDLC)); 542 #if 0 543 /* immediately send receive reset so the above takes */ 544 msci_write_1(scp, SCA_CMD0, SCA_CMD_RXRESET); 545 #endif 546 547 msci_write_1(scp, SCA_MD10, SCA_MD1_NOADDRCHK); 548 msci_write_1(scp, SCA_MD20, 549 (SCA_MD2_DUPLEX | SCA_MD2_ADPLLx8 | SCA_MD2_NRZ)); 550 551 /* be safe and do it again */ 552 msci_write_1(scp, SCA_CMD0, SCA_CMD_RXRESET); 553 554 /* setup underrun and idle control, and initial RTS state */ 555 msci_write_1(scp, SCA_CTL0, 556 (SCA_CTL_IDLC_PATTERN 557 | SCA_CTL_UDRNC_AFTER_FCS 558 | SCA_CTL_RTS_LOW)); 559 560 /* reset the transmitter */ 561 msci_write_1(scp, SCA_CMD0, SCA_CMD_TXRESET); 562 563 /* 564 * set the clock sources 565 */ 566 msci_write_1(scp, SCA_RXS0, scp->sp_rxs); 567 msci_write_1(scp, SCA_TXS0, scp->sp_txs); 568 msci_write_1(scp, SCA_TMC0, scp->sp_tmc); 569 570 /* set external clock generate as requested */ 571 sc->sc_clock_callback(sc->sc_aux, scp->sp_port, scp->sp_eclock); 572 573 /* 574 * XXX don't pay attention to CTS or CD changes right now. I can't 575 * simulate one, and the transmitter will try to transmit even if 576 * CD isn't there anyway, so nothing bad SHOULD happen. 577 */ 578 #if 0 579 msci_write_1(scp, SCA_IE00, 0); 580 msci_write_1(scp, SCA_IE10, 0); /* 0x0c == CD and CTS changes only */ 581 #else 582 /* this would deliver transmitter underrun to ST1/ISR1 */ 583 msci_write_1(scp, SCA_IE10, SCA_ST1_UDRN); 584 msci_write_1(scp, SCA_IE00, SCA_ST0_TXINT); 585 #endif 586 msci_write_1(scp, SCA_IE20, 0); 587 588 msci_write_1(scp, SCA_FIE0, 0); 589 590 msci_write_1(scp, SCA_SA00, 0); 591 msci_write_1(scp, SCA_SA10, 0); 592 593 msci_write_1(scp, SCA_IDL0, 0x7e); 594 595 msci_write_1(scp, SCA_RRC0, 0x0e); 596 /* msci_write_1(scp, SCA_TRC00, 0x10); */ 597 /* 598 * the correct values here are important for avoiding underruns 599 * for any value less than or equal to TRC0 txrdy is activated 600 * which will start the dmac transfer to the fifo. 601 * for buffer size >= TRC1 + 1 txrdy is cleared which will stop dma. 602 * 603 * thus if we are using a very fast clock that empties the fifo 604 * quickly, delays in the dmac starting to fill the fifo can 605 * lead to underruns so we want a fairly full fifo to still 606 * cause the dmac to start. for cards with on board ram this 607 * has no effect on system performance. For cards that dma 608 * to/from system memory it will cause more, shorter, 609 * bus accesses rather than fewer longer ones. 610 */ 611 msci_write_1(scp, SCA_TRC00, 0x00); 612 msci_write_1(scp, SCA_TRC10, 0x1f); 613 } 614 615 /* 616 * Take the memory for the port and construct two circular linked lists of 617 * descriptors (one tx, one rx) and set the pointers in these descriptors 618 * to point to the buffer space for this port. 619 */ 620 static void 621 sca_dmac_init(struct sca_softc *sc, sca_port_t *scp) 622 { 623 sca_desc_t *desc; 624 u_int32_t desc_p; 625 u_int32_t buf_p; 626 int i; 627 628 if (sc->sc_usedma) 629 bus_dmamap_sync(sc->scu_dmat, sc->scu_dmam, 0, sc->scu_allocsize, 630 BUS_DMASYNC_PREWRITE); 631 else { 632 /* 633 * XXX assumes that all tx desc and bufs in same page 634 */ 635 sc->scu_page_on(sc); 636 sc->scu_set_page(sc, scp->sp_txdesc_p); 637 } 638 639 desc = scp->sp_txdesc; 640 desc_p = scp->sp_txdesc_p; 641 buf_p = scp->sp_txbuf_p; 642 scp->sp_txcur = 0; 643 scp->sp_txinuse = 0; 644 645 #ifdef DEBUG 646 /* make sure that we won't wrap */ 647 if ((desc_p & 0xffff0000) != 648 ((desc_p + sizeof(*desc) * scp->sp_ntxdesc) & 0xffff0000)) 649 panic("sca: tx descriptors cross architecural boundry"); 650 if ((buf_p & 0xff000000) != 651 ((buf_p + SCA_BSIZE * scp->sp_ntxdesc) & 0xff000000)) 652 panic("sca: tx buffers cross architecural boundry"); 653 #endif 654 655 for (i = 0 ; i < scp->sp_ntxdesc ; i++) { 656 /* 657 * desc_p points to the physcial address of the NEXT desc 658 */ 659 desc_p += sizeof(sca_desc_t); 660 661 sca_desc_write_chainp(sc, desc, desc_p & 0x0000ffff); 662 sca_desc_write_bufp(sc, desc, buf_p); 663 sca_desc_write_buflen(sc, desc, SCA_BSIZE); 664 sca_desc_write_stat(sc, desc, 0); 665 666 desc++; /* point to the next descriptor */ 667 buf_p += SCA_BSIZE; 668 } 669 670 /* 671 * "heal" the circular list by making the last entry point to the 672 * first. 673 */ 674 sca_desc_write_chainp(sc, desc - 1, scp->sp_txdesc_p & 0x0000ffff); 675 676 /* 677 * Now, initialize the transmit DMA logic 678 * 679 * CPB == chain pointer base address 680 */ 681 dmac_write_1(scp, SCA_DSR1, 0); 682 dmac_write_1(scp, SCA_DCR1, SCA_DCR_ABRT); 683 dmac_write_1(scp, SCA_DMR1, SCA_DMR_TMOD | SCA_DMR_NF); 684 /* XXX1 685 dmac_write_1(scp, SCA_DIR1, 686 (SCA_DIR_EOT | SCA_DIR_BOF | SCA_DIR_COF)); 687 */ 688 dmac_write_1(scp, SCA_DIR1, 689 (SCA_DIR_EOM | SCA_DIR_EOT | SCA_DIR_BOF | SCA_DIR_COF)); 690 dmac_write_1(scp, SCA_CPB1, 691 (u_int8_t)((scp->sp_txdesc_p & 0x00ff0000) >> 16)); 692 693 /* 694 * now, do the same thing for receive descriptors 695 * 696 * XXX assumes that all rx desc and bufs in same page 697 */ 698 if (!sc->sc_usedma) 699 sc->scu_set_page(sc, scp->sp_rxdesc_p); 700 701 desc = scp->sp_rxdesc; 702 desc_p = scp->sp_rxdesc_p; 703 buf_p = scp->sp_rxbuf_p; 704 705 #ifdef DEBUG 706 /* make sure that we won't wrap */ 707 if ((desc_p & 0xffff0000) != 708 ((desc_p + sizeof(*desc) * scp->sp_nrxdesc) & 0xffff0000)) 709 panic("sca: rx descriptors cross architecural boundry"); 710 if ((buf_p & 0xff000000) != 711 ((buf_p + SCA_BSIZE * scp->sp_nrxdesc) & 0xff000000)) 712 panic("sca: rx buffers cross architecural boundry"); 713 #endif 714 715 for (i = 0 ; i < scp->sp_nrxdesc; i++) { 716 /* 717 * desc_p points to the physcial address of the NEXT desc 718 */ 719 desc_p += sizeof(sca_desc_t); 720 721 sca_desc_write_chainp(sc, desc, desc_p & 0x0000ffff); 722 sca_desc_write_bufp(sc, desc, buf_p); 723 /* sca_desc_write_buflen(sc, desc, SCA_BSIZE); */ 724 sca_desc_write_buflen(sc, desc, 0); 725 sca_desc_write_stat(sc, desc, 0); 726 727 desc++; /* point to the next descriptor */ 728 buf_p += SCA_BSIZE; 729 } 730 731 /* 732 * "heal" the circular list by making the last entry point to the 733 * first. 734 */ 735 sca_desc_write_chainp(sc, desc - 1, scp->sp_rxdesc_p & 0x0000ffff); 736 737 sca_dmac_rxinit(scp); 738 739 if (sc->sc_usedma) 740 bus_dmamap_sync(sc->scu_dmat, sc->scu_dmam, 741 0, sc->scu_allocsize, BUS_DMASYNC_POSTWRITE); 742 else 743 sc->scu_page_off(sc); 744 } 745 746 /* 747 * reset and reinitialize the receive DMA logic 748 */ 749 static void 750 sca_dmac_rxinit(sca_port_t *scp) 751 { 752 /* 753 * ... and the receive DMA logic ... 754 */ 755 dmac_write_1(scp, SCA_DSR0, 0); /* disable DMA */ 756 dmac_write_1(scp, SCA_DCR0, SCA_DCR_ABRT); 757 758 dmac_write_1(scp, SCA_DMR0, SCA_DMR_TMOD | SCA_DMR_NF); 759 dmac_write_2(scp, SCA_BFLL0, SCA_BSIZE); 760 761 /* reset descriptors to initial state */ 762 scp->sp_rxstart = 0; 763 scp->sp_rxend = scp->sp_nrxdesc - 1; 764 765 /* 766 * CPB == chain pointer base 767 * CDA == current descriptor address 768 * EDA == error descriptor address (overwrite position) 769 * because cda can't be eda when starting we always 770 * have a single buffer gap between cda and eda 771 */ 772 dmac_write_1(scp, SCA_CPB0, 773 (u_int8_t)((scp->sp_rxdesc_p & 0x00ff0000) >> 16)); 774 dmac_write_2(scp, SCA_CDAL0, (u_int16_t)(scp->sp_rxdesc_p & 0xffff)); 775 dmac_write_2(scp, SCA_EDAL0, (u_int16_t) 776 (scp->sp_rxdesc_p + (sizeof(sca_desc_t) * scp->sp_rxend))); 777 778 /* 779 * enable receiver DMA 780 */ 781 dmac_write_1(scp, SCA_DIR0, 782 (SCA_DIR_EOT | SCA_DIR_EOM | SCA_DIR_BOF | SCA_DIR_COF)); 783 dmac_write_1(scp, SCA_DSR0, SCA_DSR_DE); 784 } 785 786 /* 787 * Queue the packet for our start routine to transmit 788 */ 789 static int 790 sca_output(ifp, m, dst, rt0) 791 struct ifnet *ifp; 792 struct mbuf *m; 793 struct sockaddr *dst; 794 struct rtentry *rt0; 795 { 796 #ifdef ISO 797 struct hdlc_llc_header *llc; 798 #endif 799 struct hdlc_header *hdlc; 800 struct ifqueue *ifq; 801 int s, error; 802 803 error = 0; 804 ifp->if_lastchange = time; 805 806 if ((ifp->if_flags & IFF_UP) != IFF_UP) { 807 error = ENETDOWN; 808 goto bad; 809 } 810 811 ifq = &ifp->if_snd; 812 813 /* 814 * determine address family, and priority for this packet 815 */ 816 switch (dst->sa_family) { 817 #ifdef INET 818 case AF_INET: 819 #ifdef SCA_USE_FASTQ 820 if ((mtod(m, struct ip *)->ip_tos & IPTOS_LOWDELAY) 821 == IPTOS_LOWDELAY) 822 ifq = &((sca_port_t *)ifp->if_softc)->fastq; 823 #endif 824 /* 825 * Add cisco serial line header. If there is no 826 * space in the first mbuf, allocate another. 827 */ 828 M_PREPEND(m, sizeof(struct hdlc_header), M_DONTWAIT); 829 if (m == 0) 830 return (ENOBUFS); 831 hdlc = mtod(m, struct hdlc_header *); 832 hdlc->h_proto = htons(HDLC_PROTOCOL_IP); 833 break; 834 #endif 835 #ifdef ISO 836 case AF_ISO: 837 /* 838 * Add cisco llc serial line header. If there is no 839 * space in the first mbuf, allocate another. 840 */ 841 M_PREPEND(m, sizeof(struct hdlc_llc_header), M_DONTWAIT); 842 if (m == 0) 843 return (ENOBUFS); 844 hdlc = mtod(m, struct hdlc_header *); 845 llc = mtod(m, struct hdlc_llc_header *); 846 llc->hl_dsap = llc->hl_ssap = LLC_ISO_LSAP; 847 llc->hl_ffb = 0; 848 break; 849 #endif 850 default: 851 printf("%s: address family %d unsupported\n", 852 ifp->if_xname, dst->sa_family); 853 error = EAFNOSUPPORT; 854 goto bad; 855 } 856 857 /* finish */ 858 if ((m->m_flags & (M_BCAST | M_MCAST)) != 0) 859 hdlc->h_addr = CISCO_MULTICAST; 860 else 861 hdlc->h_addr = CISCO_UNICAST; 862 hdlc->h_resv = 0; 863 864 /* 865 * queue the packet. If interactive, use the fast queue. 866 */ 867 s = splnet(); 868 if (IF_QFULL(ifq)) { 869 IF_DROP(ifq); 870 ifp->if_oerrors++; 871 ifp->if_collisions++; 872 error = ENOBUFS; 873 splx(s); 874 goto bad; 875 } 876 ifp->if_obytes += m->m_pkthdr.len; 877 IF_ENQUEUE(ifq, m); 878 879 ifp->if_lastchange = time; 880 881 if (m->m_flags & M_MCAST) 882 ifp->if_omcasts++; 883 884 sca_start(ifp); 885 splx(s); 886 887 return (error); 888 889 bad: 890 if (m) 891 m_freem(m); 892 return (error); 893 } 894 895 static int 896 sca_ioctl(ifp, cmd, addr) 897 struct ifnet *ifp; 898 u_long cmd; 899 caddr_t addr; 900 { 901 struct ifreq *ifr; 902 struct ifaddr *ifa; 903 int error; 904 int s; 905 906 s = splnet(); 907 908 ifr = (struct ifreq *)addr; 909 ifa = (struct ifaddr *)addr; 910 error = 0; 911 912 switch (cmd) { 913 case SIOCSIFADDR: 914 #ifdef INET 915 if (ifa->ifa_addr->sa_family == AF_INET) { 916 ifp->if_flags |= IFF_UP; 917 sca_port_up(ifp->if_softc); 918 } else 919 #endif 920 error = EAFNOSUPPORT; 921 break; 922 923 case SIOCSIFDSTADDR: 924 #ifdef INET 925 if (ifa->ifa_addr->sa_family != AF_INET) 926 error = EAFNOSUPPORT; 927 #else 928 error = EAFNOSUPPORT; 929 #endif 930 break; 931 932 case SIOCADDMULTI: 933 case SIOCDELMULTI: 934 if (ifr == 0) { 935 error = EAFNOSUPPORT; /* XXX */ 936 break; 937 } 938 switch (ifr->ifr_addr.sa_family) { 939 #ifdef INET 940 case AF_INET: 941 break; 942 #endif 943 default: 944 error = EAFNOSUPPORT; 945 break; 946 } 947 break; 948 949 case SIOCSIFFLAGS: 950 if (ifr->ifr_flags & IFF_UP) { 951 ifp->if_flags |= IFF_UP; 952 sca_port_up(ifp->if_softc); 953 } else { 954 ifp->if_flags &= ~IFF_UP; 955 sca_port_down(ifp->if_softc); 956 } 957 958 break; 959 960 default: 961 error = EINVAL; 962 } 963 964 splx(s); 965 return error; 966 } 967 968 /* 969 * start packet transmission on the interface 970 * 971 * MUST BE CALLED AT splnet() 972 */ 973 static void 974 sca_start(ifp) 975 struct ifnet *ifp; 976 { 977 sca_port_t *scp = ifp->if_softc; 978 struct sca_softc *sc = scp->sca; 979 struct mbuf *m, *mb_head; 980 sca_desc_t *desc; 981 u_int8_t *buf, stat; 982 u_int32_t buf_p; 983 int nexttx; 984 int trigger_xmit; 985 u_int len; 986 987 SCA_DPRINTF(SCA_DEBUG_TX, ("TX: enter start\n")); 988 989 /* 990 * can't queue when we are full or transmitter is busy 991 */ 992 #ifdef oldcode 993 if ((scp->sp_txinuse >= (scp->sp_ntxdesc - 1)) 994 || ((ifp->if_flags & IFF_OACTIVE) == IFF_OACTIVE)) 995 return; 996 #else 997 if (scp->sp_txinuse 998 || ((ifp->if_flags & IFF_OACTIVE) == IFF_OACTIVE)) 999 return; 1000 #endif 1001 SCA_DPRINTF(SCA_DEBUG_TX, ("TX: txinuse %d\n", scp->sp_txinuse)); 1002 1003 /* 1004 * XXX assume that all tx desc and bufs in same page 1005 */ 1006 if (sc->sc_usedma) 1007 bus_dmamap_sync(sc->scu_dmat, sc->scu_dmam, 1008 0, sc->scu_allocsize, 1009 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1010 else { 1011 sc->scu_page_on(sc); 1012 sc->scu_set_page(sc, scp->sp_txdesc_p); 1013 } 1014 1015 trigger_xmit = 0; 1016 1017 txloop: 1018 IF_DEQUEUE(&scp->linkq, mb_head); 1019 if (mb_head == NULL) 1020 #ifdef SCA_USE_FASTQ 1021 IF_DEQUEUE(&scp->fastq, mb_head); 1022 if (mb_head == NULL) 1023 #endif 1024 IF_DEQUEUE(&ifp->if_snd, mb_head); 1025 if (mb_head == NULL) 1026 goto start_xmit; 1027 1028 SCA_DPRINTF(SCA_DEBUG_TX, ("TX: got mbuf\n")); 1029 #ifdef oldcode 1030 if (scp->txinuse != 0) { 1031 /* Kill EOT interrupts on the previous descriptor. */ 1032 desc = &scp->sp_txdesc[scp->txcur]; 1033 stat = sca_desc_read_stat(sc, desc); 1034 sca_desc_write_stat(sc, desc, stat & ~SCA_DESC_EOT); 1035 1036 /* Figure out what the next free descriptor is. */ 1037 nexttx = (scp->sp_txcur + 1) % scp->sp_ntxdesc; 1038 } else 1039 nexttx = 0; 1040 #endif /* oldcode */ 1041 1042 if (scp->sp_txinuse) 1043 nexttx = (scp->sp_txcur + 1) % scp->sp_ntxdesc; 1044 else 1045 nexttx = 0; 1046 1047 SCA_DPRINTF(SCA_DEBUG_TX, ("TX: nexttx %d\n", nexttx)); 1048 1049 buf = scp->sp_txbuf + SCA_BSIZE * nexttx; 1050 buf_p = scp->sp_txbuf_p + SCA_BSIZE * nexttx; 1051 1052 /* XXX hoping we can delay the desc write till after we don't drop. */ 1053 desc = &scp->sp_txdesc[nexttx]; 1054 1055 /* XXX isn't this set already?? */ 1056 sca_desc_write_bufp(sc, desc, buf_p); 1057 len = 0; 1058 1059 SCA_DPRINTF(SCA_DEBUG_TX, ("TX: buf %x buf_p %x\n", (u_int)buf, buf_p)); 1060 1061 #if 0 /* uncomment this for a core in cc1 */ 1062 X 1063 #endif 1064 /* 1065 * Run through the chain, copying data into the descriptor as we 1066 * go. If it won't fit in one transmission block, drop the packet. 1067 * No, this isn't nice, but most of the time it _will_ fit. 1068 */ 1069 for (m = mb_head ; m != NULL ; m = m->m_next) { 1070 if (m->m_len != 0) { 1071 len += m->m_len; 1072 if (len > SCA_BSIZE) { 1073 m_freem(mb_head); 1074 goto txloop; 1075 } 1076 SCA_DPRINTF(SCA_DEBUG_TX, 1077 ("TX: about to mbuf len %d\n", m->m_len)); 1078 1079 if (sc->sc_usedma) 1080 bcopy(mtod(m, u_int8_t *), buf, m->m_len); 1081 else 1082 bus_space_write_region_1(sc->scu_memt, 1083 sc->scu_memh, sca_page_addr(sc, buf_p), 1084 mtod(m, u_int8_t *), m->m_len); 1085 buf += m->m_len; 1086 buf_p += m->m_len; 1087 } 1088 } 1089 1090 /* set the buffer, the length, and mark end of frame and end of xfer */ 1091 sca_desc_write_buflen(sc, desc, len); 1092 sca_desc_write_stat(sc, desc, SCA_DESC_EOM); 1093 1094 ifp->if_opackets++; 1095 1096 #if NBPFILTER > 0 1097 /* 1098 * Pass packet to bpf if there is a listener. 1099 */ 1100 if (ifp->if_bpf) 1101 bpf_mtap(ifp->if_bpf, mb_head); 1102 #endif 1103 1104 m_freem(mb_head); 1105 1106 scp->sp_txcur = nexttx; 1107 scp->sp_txinuse++; 1108 trigger_xmit = 1; 1109 1110 SCA_DPRINTF(SCA_DEBUG_TX, 1111 ("TX: inuse %d index %d\n", scp->sp_txinuse, scp->sp_txcur)); 1112 1113 /* 1114 * XXX so didn't this used to limit us to 1?! - multi may be untested 1115 * sp_ntxdesc used to be hard coded to 2 with claim of a too hard 1116 * to find bug 1117 */ 1118 #ifdef oldcode 1119 if (scp->sp_txinuse < (scp->sp_ntxdesc - 1)) 1120 #endif 1121 if (scp->sp_txinuse < scp->sp_ntxdesc) 1122 goto txloop; 1123 1124 start_xmit: 1125 SCA_DPRINTF(SCA_DEBUG_TX, ("TX: trigger_xmit %d\n", trigger_xmit)); 1126 1127 if (trigger_xmit != 0) { 1128 /* set EOT on final descriptor */ 1129 desc = &scp->sp_txdesc[scp->sp_txcur]; 1130 stat = sca_desc_read_stat(sc, desc); 1131 sca_desc_write_stat(sc, desc, stat | SCA_DESC_EOT); 1132 } 1133 1134 if (sc->sc_usedma) 1135 bus_dmamap_sync(sc->scu_dmat, sc->scu_dmam, 0, 1136 sc->scu_allocsize, 1137 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1138 1139 if (trigger_xmit != 0) 1140 sca_port_starttx(scp); 1141 1142 if (!sc->sc_usedma) 1143 sc->scu_page_off(sc); 1144 } 1145 1146 static void 1147 sca_watchdog(ifp) 1148 struct ifnet *ifp; 1149 { 1150 } 1151 1152 int 1153 sca_hardintr(struct sca_softc *sc) 1154 { 1155 u_int8_t isr0, isr1, isr2; 1156 int ret; 1157 1158 ret = 0; /* non-zero means we processed at least one interrupt */ 1159 1160 SCA_DPRINTF(SCA_DEBUG_INTR, ("sca_hardintr entered\n")); 1161 1162 while (1) { 1163 /* 1164 * read SCA interrupts 1165 */ 1166 isr0 = sca_read_1(sc, SCA_ISR0); 1167 isr1 = sca_read_1(sc, SCA_ISR1); 1168 isr2 = sca_read_1(sc, SCA_ISR2); 1169 1170 if (isr0 == 0 && isr1 == 0 && isr2 == 0) 1171 break; 1172 1173 SCA_DPRINTF(SCA_DEBUG_INTR, 1174 ("isr0 = %02x, isr1 = %02x, isr2 = %02x\n", 1175 isr0, isr1, isr2)); 1176 1177 /* 1178 * check DMAC interrupt 1179 */ 1180 if (isr1 & 0x0f) 1181 ret += sca_dmac_intr(&sc->sc_ports[0], 1182 isr1 & 0x0f); 1183 1184 if (isr1 & 0xf0) 1185 ret += sca_dmac_intr(&sc->sc_ports[1], 1186 (isr1 & 0xf0) >> 4); 1187 1188 /* 1189 * mcsi intterupts 1190 */ 1191 if (isr0 & 0x0f) 1192 ret += sca_msci_intr(&sc->sc_ports[0], isr0 & 0x0f); 1193 1194 if (isr0 & 0xf0) 1195 ret += sca_msci_intr(&sc->sc_ports[1], 1196 (isr0 & 0xf0) >> 4); 1197 1198 #if 0 /* We don't GET timer interrupts, we have them disabled (msci IE20) */ 1199 if (isr2) 1200 ret += sca_timer_intr(sc, isr2); 1201 #endif 1202 } 1203 1204 return (ret); 1205 } 1206 1207 static int 1208 sca_dmac_intr(sca_port_t *scp, u_int8_t isr) 1209 { 1210 u_int8_t dsr; 1211 int ret; 1212 1213 ret = 0; 1214 1215 /* 1216 * Check transmit channel 1217 */ 1218 if (isr & (SCA_ISR1_DMAC_TX0A | SCA_ISR1_DMAC_TX0B)) { 1219 SCA_DPRINTF(SCA_DEBUG_INTR, 1220 ("TX INTERRUPT port %d\n", scp->sp_port)); 1221 1222 dsr = 1; 1223 while (dsr != 0) { 1224 ret++; 1225 /* 1226 * reset interrupt 1227 */ 1228 dsr = dmac_read_1(scp, SCA_DSR1); 1229 dmac_write_1(scp, SCA_DSR1, 1230 dsr | SCA_DSR_DEWD); 1231 1232 /* 1233 * filter out the bits we don't care about 1234 */ 1235 dsr &= ( SCA_DSR_COF | SCA_DSR_BOF | SCA_DSR_EOT); 1236 if (dsr == 0) 1237 break; 1238 1239 /* 1240 * check for counter overflow 1241 */ 1242 if (dsr & SCA_DSR_COF) { 1243 printf("%s: TXDMA counter overflow\n", 1244 scp->sp_if.if_xname); 1245 1246 scp->sp_if.if_flags &= ~IFF_OACTIVE; 1247 scp->sp_txcur = 0; 1248 scp->sp_txinuse = 0; 1249 } 1250 1251 /* 1252 * check for buffer overflow 1253 */ 1254 if (dsr & SCA_DSR_BOF) { 1255 printf("%s: TXDMA buffer overflow, cda 0x%04x, eda 0x%04x, cpb 0x%02x\n", 1256 scp->sp_if.if_xname, 1257 dmac_read_2(scp, SCA_CDAL1), 1258 dmac_read_2(scp, SCA_EDAL1), 1259 dmac_read_1(scp, SCA_CPB1)); 1260 1261 /* 1262 * Yikes. Arrange for a full 1263 * transmitter restart. 1264 */ 1265 scp->sp_if.if_flags &= ~IFF_OACTIVE; 1266 scp->sp_txcur = 0; 1267 scp->sp_txinuse = 0; 1268 } 1269 1270 /* 1271 * check for end of transfer, which is not 1272 * an error. It means that all data queued 1273 * was transmitted, and we mark ourself as 1274 * not in use and stop the watchdog timer. 1275 */ 1276 if (dsr & SCA_DSR_EOT) { 1277 SCA_DPRINTF(SCA_DEBUG_TX, 1278 ("Transmit completed. cda %x eda %x dsr %x\n", 1279 dmac_read_2(scp, SCA_CDAL1), 1280 dmac_read_2(scp, SCA_EDAL1), 1281 dsr)); 1282 1283 scp->sp_if.if_flags &= ~IFF_OACTIVE; 1284 scp->sp_txcur = 0; 1285 scp->sp_txinuse = 0; 1286 1287 /* 1288 * check for more packets 1289 */ 1290 sca_start(&scp->sp_if); 1291 } 1292 } 1293 } 1294 /* 1295 * receive channel check 1296 */ 1297 if (isr & (SCA_ISR1_DMAC_RX0A | SCA_ISR1_DMAC_RX0B)) { 1298 SCA_DPRINTF(SCA_DEBUG_INTR, ("RX INTERRUPT port %d\n", 1299 (scp == &scp->sca->sc_ports[0] ? 0 : 1))); 1300 1301 dsr = 1; 1302 while (dsr != 0) { 1303 ret++; 1304 1305 dsr = dmac_read_1(scp, SCA_DSR0); 1306 dmac_write_1(scp, SCA_DSR0, dsr | SCA_DSR_DEWD); 1307 1308 /* 1309 * filter out the bits we don't care about 1310 */ 1311 dsr &= (SCA_DSR_EOM | SCA_DSR_COF 1312 | SCA_DSR_BOF | SCA_DSR_EOT); 1313 if (dsr == 0) 1314 break; 1315 1316 /* 1317 * End of frame 1318 */ 1319 if (dsr & SCA_DSR_EOM) { 1320 SCA_DPRINTF(SCA_DEBUG_RX, ("Got a frame!\n")); 1321 1322 sca_get_packets(scp); 1323 } 1324 1325 /* 1326 * check for counter overflow 1327 */ 1328 if (dsr & SCA_DSR_COF) { 1329 printf("%s: RXDMA counter overflow\n", 1330 scp->sp_if.if_xname); 1331 1332 sca_dmac_rxinit(scp); 1333 } 1334 1335 /* 1336 * check for end of transfer, which means we 1337 * ran out of descriptors to receive into. 1338 * This means the line is much faster than 1339 * we can handle. 1340 */ 1341 if (dsr & (SCA_DSR_BOF | SCA_DSR_EOT)) { 1342 printf("%s: RXDMA buffer overflow\n", 1343 scp->sp_if.if_xname); 1344 1345 sca_dmac_rxinit(scp); 1346 } 1347 } 1348 } 1349 1350 return ret; 1351 } 1352 1353 static int 1354 sca_msci_intr(sca_port_t *scp, u_int8_t isr) 1355 { 1356 u_int8_t st1, trc0; 1357 1358 /* get and clear the specific interrupt -- should act on it :)*/ 1359 if ((st1 = msci_read_1(scp, SCA_ST10))) { 1360 /* clear the interrupt */ 1361 msci_write_1(scp, SCA_ST10, st1); 1362 1363 if (st1 & SCA_ST1_UDRN) { 1364 /* underrun -- try to increase ready control */ 1365 trc0 = msci_read_1(scp, SCA_TRC00); 1366 if (trc0 == 0x1f) 1367 printf("TX: underun - fifo depth maxed\n"); 1368 else { 1369 if ((trc0 += 2) > 0x1f) 1370 trc0 = 0x1f; 1371 SCA_DPRINTF(SCA_DEBUG_TX, 1372 ("TX: udrn - incr fifo to %d\n", trc0)); 1373 msci_write_1(scp, SCA_TRC00, trc0); 1374 } 1375 } 1376 } 1377 return (0); 1378 } 1379 1380 static void 1381 sca_get_packets(sca_port_t *scp) 1382 { 1383 struct sca_softc *sc; 1384 1385 SCA_DPRINTF(SCA_DEBUG_RX, ("RX: sca_get_packets\n")); 1386 1387 sc = scp->sca; 1388 if (sc->sc_usedma) 1389 bus_dmamap_sync(sc->scu_dmat, sc->scu_dmam, 1390 0, sc->scu_allocsize, 1391 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1392 else { 1393 /* 1394 * XXX this code is unable to deal with rx stuff 1395 * in more than 1 page 1396 */ 1397 sc->scu_page_on(sc); 1398 sc->scu_set_page(sc, scp->sp_rxdesc_p); 1399 } 1400 1401 /* process as many frames as are available */ 1402 while (sca_frame_avail(scp)) { 1403 sca_frame_process(scp); 1404 sca_frame_read_done(scp); 1405 } 1406 1407 if (sc->sc_usedma) 1408 bus_dmamap_sync(sc->scu_dmat, sc->scu_dmam, 1409 0, sc->scu_allocsize, 1410 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1411 else 1412 sc->scu_page_off(sc); 1413 } 1414 1415 /* 1416 * Starting with the first descriptor we wanted to read into, up to but 1417 * not including the current SCA read descriptor, look for a packet. 1418 * 1419 * must be called at splnet() 1420 */ 1421 static int 1422 sca_frame_avail(sca_port_t *scp) 1423 { 1424 struct sca_softc *sc; 1425 u_int16_t cda; 1426 u_int32_t desc_p; /* physical address (lower 16 bits) */ 1427 sca_desc_t *desc; 1428 u_int8_t rxstat; 1429 int cdaidx, toolong; 1430 1431 /* 1432 * Read the current descriptor from the SCA. 1433 */ 1434 sc = scp->sca; 1435 cda = dmac_read_2(scp, SCA_CDAL0); 1436 1437 /* 1438 * calculate the index of the current descriptor 1439 */ 1440 desc_p = (scp->sp_rxdesc_p & 0xFFFF); 1441 desc_p = cda - desc_p; 1442 cdaidx = desc_p / sizeof(sca_desc_t); 1443 1444 SCA_DPRINTF(SCA_DEBUG_RX, 1445 ("RX: cda %x desc_p %x cdaidx %u, nrxdesc %d rxstart %d\n", 1446 cda, desc_p, cdaidx, scp->sp_nrxdesc, scp->sp_rxstart)); 1447 1448 /* note confusion */ 1449 if (cdaidx >= scp->sp_nrxdesc) 1450 panic("current descriptor index out of range"); 1451 1452 /* see if we have a valid frame available */ 1453 toolong = 0; 1454 for (; scp->sp_rxstart != cdaidx; sca_frame_read_done(scp)) { 1455 /* 1456 * We might have a valid descriptor. Set up a pointer 1457 * to the kva address for it so we can more easily examine 1458 * the contents. 1459 */ 1460 desc = &scp->sp_rxdesc[scp->sp_rxstart]; 1461 rxstat = sca_desc_read_stat(scp->sca, desc); 1462 1463 SCA_DPRINTF(SCA_DEBUG_RX, ("port %d RX: idx %d rxstat %x\n", 1464 scp->sp_port, scp->sp_rxstart, rxstat)); 1465 1466 SCA_DPRINTF(SCA_DEBUG_RX, ("port %d RX: buflen %d\n", 1467 scp->sp_port, sca_desc_read_buflen(scp->sca, desc))); 1468 1469 /* 1470 * check for errors 1471 */ 1472 if (rxstat & SCA_DESC_ERRORS) { 1473 /* 1474 * consider an error condition the end 1475 * of a frame 1476 */ 1477 scp->sp_if.if_ierrors++; 1478 toolong = 0; 1479 continue; 1480 } 1481 1482 /* 1483 * if we aren't skipping overlong frames 1484 * we are done, otherwise reset and look for 1485 * another good frame 1486 */ 1487 if (rxstat & SCA_DESC_EOM) { 1488 if (!toolong) 1489 return (1); 1490 toolong = 0; 1491 } else if (!toolong) { 1492 /* 1493 * we currently don't deal with frames 1494 * larger than a single buffer (fixed MTU) 1495 */ 1496 scp->sp_if.if_ierrors++; 1497 toolong = 1; 1498 } 1499 SCA_DPRINTF(SCA_DEBUG_RX, ("RX: idx %d no EOM\n", 1500 scp->sp_rxstart)); 1501 } 1502 1503 SCA_DPRINTF(SCA_DEBUG_RX, ("RX: returning none\n")); 1504 return 0; 1505 } 1506 1507 /* 1508 * Pass the packet up to the kernel if it is a packet we want to pay 1509 * attention to. 1510 * 1511 * MUST BE CALLED AT splnet() 1512 */ 1513 static void 1514 sca_frame_process(sca_port_t *scp) 1515 { 1516 struct ifqueue *ifq; 1517 struct hdlc_header *hdlc; 1518 struct cisco_pkt *cisco; 1519 sca_desc_t *desc; 1520 struct mbuf *m; 1521 u_int8_t *bufp; 1522 u_int16_t len; 1523 u_int32_t t; 1524 1525 t = (time.tv_sec - boottime.tv_sec) * 1000; 1526 desc = &scp->sp_rxdesc[scp->sp_rxstart]; 1527 bufp = scp->sp_rxbuf + SCA_BSIZE * scp->sp_rxstart; 1528 len = sca_desc_read_buflen(scp->sca, desc); 1529 1530 SCA_DPRINTF(SCA_DEBUG_RX, 1531 ("RX: desc %lx bufp %lx len %d\n", (bus_addr_t)desc, 1532 (bus_addr_t)bufp, len)); 1533 1534 #if SCA_DEBUG_LEVEL > 0 1535 if (sca_debug & SCA_DEBUG_RXPKT) 1536 sca_frame_print(scp, desc, bufp); 1537 #endif 1538 /* 1539 * skip packets that are too short 1540 */ 1541 if (len < sizeof(struct hdlc_header)) { 1542 scp->sp_if.if_ierrors++; 1543 return; 1544 } 1545 1546 m = sca_mbuf_alloc(scp->sca, bufp, len); 1547 if (m == NULL) { 1548 SCA_DPRINTF(SCA_DEBUG_RX, ("RX: no mbuf!\n")); 1549 return; 1550 } 1551 1552 /* 1553 * read and then strip off the HDLC information 1554 */ 1555 m = m_pullup(m, sizeof(struct hdlc_header)); 1556 if (m == NULL) { 1557 SCA_DPRINTF(SCA_DEBUG_RX, ("RX: no m_pullup!\n")); 1558 return; 1559 } 1560 1561 #if NBPFILTER > 0 1562 if (scp->sp_if.if_bpf) 1563 bpf_mtap(scp->sp_if.if_bpf, m); 1564 #endif 1565 1566 scp->sp_if.if_ipackets++; 1567 scp->sp_if.if_lastchange = time; 1568 1569 hdlc = mtod(m, struct hdlc_header *); 1570 switch (ntohs(hdlc->h_proto)) { 1571 #ifdef INET 1572 case HDLC_PROTOCOL_IP: 1573 SCA_DPRINTF(SCA_DEBUG_RX, ("Received IP packet\n")); 1574 m->m_pkthdr.rcvif = &scp->sp_if; 1575 m->m_pkthdr.len -= sizeof(struct hdlc_header); 1576 m->m_data += sizeof(struct hdlc_header); 1577 m->m_len -= sizeof(struct hdlc_header); 1578 ifq = &ipintrq; 1579 schednetisr(NETISR_IP); 1580 break; 1581 #endif /* INET */ 1582 #ifdef ISO 1583 case HDLC_PROTOCOL_ISO: 1584 if (m->m_pkthdr.len < sizeof(struct hdlc_llc_header)) 1585 goto dropit; 1586 m->m_pkthdr.rcvif = &scp->sp_if; 1587 m->m_pkthdr.len -= sizeof(struct hdlc_llc_header); 1588 m->m_data += sizeof(struct hdlc_llc_header); 1589 m->m_len -= sizeof(struct hdlc_llc_header); 1590 ifq = &clnlintrq; 1591 schednetisr(NETISR_ISO); 1592 break; 1593 #endif /* ISO */ 1594 case CISCO_KEEPALIVE: 1595 SCA_DPRINTF(SCA_DEBUG_CISCO, 1596 ("Received CISCO keepalive packet\n")); 1597 1598 if (len < CISCO_PKT_LEN) { 1599 SCA_DPRINTF(SCA_DEBUG_CISCO, 1600 ("short CISCO packet %d, wanted %d\n", 1601 len, CISCO_PKT_LEN)); 1602 scp->sp_if.if_ierrors++; 1603 goto dropit; 1604 } 1605 1606 m = m_pullup(m, sizeof(struct cisco_pkt)); 1607 if (m == NULL) { 1608 SCA_DPRINTF(SCA_DEBUG_RX, ("RX: no m_pullup!\n")); 1609 return; 1610 } 1611 1612 cisco = (struct cisco_pkt *) 1613 (mtod(m, u_int8_t *) + HDLC_HDRLEN); 1614 m->m_pkthdr.rcvif = &scp->sp_if; 1615 1616 switch (ntohl(cisco->type)) { 1617 case CISCO_ADDR_REQ: 1618 printf("Got CISCO addr_req, ignoring\n"); 1619 scp->sp_if.if_ierrors++; 1620 goto dropit; 1621 1622 case CISCO_ADDR_REPLY: 1623 printf("Got CISCO addr_reply, ignoring\n"); 1624 scp->sp_if.if_ierrors++; 1625 goto dropit; 1626 1627 case CISCO_KEEPALIVE_REQ: 1628 1629 SCA_DPRINTF(SCA_DEBUG_CISCO, 1630 ("Received KA, mseq %d," 1631 " yseq %d, rel 0x%04x, t0" 1632 " %04x, t1 %04x\n", 1633 ntohl(cisco->par1), ntohl(cisco->par2), 1634 ntohs(cisco->rel), ntohs(cisco->time0), 1635 ntohs(cisco->time1))); 1636 1637 scp->cka_lastrx = ntohl(cisco->par1); 1638 scp->cka_lasttx++; 1639 1640 /* 1641 * schedule the transmit right here. 1642 */ 1643 cisco->par2 = cisco->par1; 1644 cisco->par1 = htonl(scp->cka_lasttx); 1645 cisco->time0 = htons((u_int16_t)(t >> 16)); 1646 cisco->time1 = htons((u_int16_t)(t & 0x0000ffff)); 1647 1648 ifq = &scp->linkq; 1649 if (IF_QFULL(ifq)) { 1650 IF_DROP(ifq); 1651 goto dropit; 1652 } 1653 IF_ENQUEUE(ifq, m); 1654 1655 sca_start(&scp->sp_if); 1656 1657 /* since start may have reset this fix */ 1658 if (!scp->sca->sc_usedma) { 1659 scp->sca->scu_set_page(scp->sca, 1660 scp->sp_rxdesc_p); 1661 scp->sca->scu_page_on(scp->sca); 1662 } 1663 return; 1664 default: 1665 SCA_DPRINTF(SCA_DEBUG_CISCO, 1666 ("Unknown CISCO keepalive protocol 0x%04x\n", 1667 ntohl(cisco->type))); 1668 1669 scp->sp_if.if_noproto++; 1670 goto dropit; 1671 } 1672 return; 1673 default: 1674 SCA_DPRINTF(SCA_DEBUG_RX, 1675 ("Unknown/unexpected ethertype 0x%04x\n", 1676 ntohs(hdlc->h_proto))); 1677 scp->sp_if.if_noproto++; 1678 goto dropit; 1679 } 1680 1681 /* queue the packet */ 1682 if (!IF_QFULL(ifq)) { 1683 IF_ENQUEUE(ifq, m); 1684 } else { 1685 IF_DROP(ifq); 1686 scp->sp_if.if_iqdrops++; 1687 goto dropit; 1688 } 1689 return; 1690 dropit: 1691 if (m) 1692 m_freem(m); 1693 return; 1694 } 1695 1696 #if SCA_DEBUG_LEVEL > 0 1697 /* 1698 * do a hex dump of the packet received into descriptor "desc" with 1699 * data buffer "p" 1700 */ 1701 static void 1702 sca_frame_print(sca_port_t *scp, sca_desc_t *desc, u_int8_t *p) 1703 { 1704 int i; 1705 int nothing_yet = 1; 1706 struct sca_softc *sc; 1707 u_int len; 1708 1709 sc = scp->sca; 1710 printf("desc va %p: chainp 0x%x bufp 0x%0x stat 0x%0x len %d\n", 1711 desc, 1712 sca_desc_read_chainp(sc, desc), 1713 sca_desc_read_bufp(sc, desc), 1714 sca_desc_read_stat(sc, desc), 1715 (len = sca_desc_read_buflen(sc, desc))); 1716 1717 for (i = 0 ; i < len && i < 256; i++) { 1718 if (nothing_yet == 1 && 1719 (sc->sc_usedma ? *p 1720 : bus_space_read_1(sc->scu_memt, sc->scu_memh, 1721 sca_page_addr(sc, p))) == 0) { 1722 p++; 1723 continue; 1724 } 1725 nothing_yet = 0; 1726 if (i % 16 == 0) 1727 printf("\n"); 1728 printf("%02x ", 1729 (sc->sc_usedma ? *p 1730 : bus_space_read_1(sc->scu_memt, sc->scu_memh, 1731 sca_page_addr(sc, p)))); 1732 p++; 1733 } 1734 1735 if (i % 16 != 1) 1736 printf("\n"); 1737 } 1738 #endif 1739 1740 /* 1741 * adjust things becuase we have just read the current starting 1742 * frame 1743 * 1744 * must be called at splnet() 1745 */ 1746 static void 1747 sca_frame_read_done(sca_port_t *scp) 1748 { 1749 u_int16_t edesc_p; 1750 1751 /* update where our indicies are */ 1752 scp->sp_rxend = scp->sp_rxstart; 1753 scp->sp_rxstart = (scp->sp_rxstart + 1) % scp->sp_nrxdesc; 1754 1755 /* update the error [end] descriptor */ 1756 edesc_p = (u_int16_t)scp->sp_rxdesc_p + 1757 (sizeof(sca_desc_t) * scp->sp_rxend); 1758 dmac_write_2(scp, SCA_EDAL0, edesc_p); 1759 } 1760 1761 /* 1762 * set a port to the "up" state 1763 */ 1764 static void 1765 sca_port_up(sca_port_t *scp) 1766 { 1767 struct sca_softc *sc = scp->sca; 1768 #if 0 1769 u_int8_t ier0, ier1; 1770 #endif 1771 1772 /* 1773 * reset things 1774 */ 1775 #if 0 1776 msci_write_1(scp, SCA_CMD0, SCA_CMD_TXRESET); 1777 msci_write_1(scp, SCA_CMD0, SCA_CMD_RXRESET); 1778 #endif 1779 /* 1780 * clear in-use flag 1781 */ 1782 scp->sp_if.if_flags &= ~IFF_OACTIVE; 1783 scp->sp_if.if_flags |= IFF_RUNNING; 1784 1785 /* 1786 * raise DTR 1787 */ 1788 sc->sc_dtr_callback(sc->sc_aux, scp->sp_port, 1); 1789 1790 /* 1791 * raise RTS 1792 */ 1793 msci_write_1(scp, SCA_CTL0, 1794 (msci_read_1(scp, SCA_CTL0) & ~SCA_CTL_RTS_MASK) 1795 | SCA_CTL_RTS_HIGH); 1796 1797 #if 0 1798 /* 1799 * enable interrupts (no timer IER2) 1800 */ 1801 ier0 = SCA_IER0_MSCI_RXRDY0 | SCA_IER0_MSCI_TXRDY0 1802 | SCA_IER0_MSCI_RXINT0 | SCA_IER0_MSCI_TXINT0; 1803 ier1 = SCA_IER1_DMAC_RX0A | SCA_IER1_DMAC_RX0B 1804 | SCA_IER1_DMAC_TX0A | SCA_IER1_DMAC_TX0B; 1805 if (scp->sp_port == 1) { 1806 ier0 <<= 4; 1807 ier1 <<= 4; 1808 } 1809 sca_write_1(sc, SCA_IER0, sca_read_1(sc, SCA_IER0) | ier0); 1810 sca_write_1(sc, SCA_IER1, sca_read_1(sc, SCA_IER1) | ier1); 1811 #else 1812 if (scp->sp_port == 0) { 1813 sca_write_1(sc, SCA_IER0, sca_read_1(sc, SCA_IER0) | 0x0f); 1814 sca_write_1(sc, SCA_IER1, sca_read_1(sc, SCA_IER1) | 0x0f); 1815 } else { 1816 sca_write_1(sc, SCA_IER0, sca_read_1(sc, SCA_IER0) | 0xf0); 1817 sca_write_1(sc, SCA_IER1, sca_read_1(sc, SCA_IER1) | 0xf0); 1818 } 1819 #endif 1820 1821 /* 1822 * enable transmit and receive 1823 */ 1824 msci_write_1(scp, SCA_CMD0, SCA_CMD_TXENABLE); 1825 msci_write_1(scp, SCA_CMD0, SCA_CMD_RXENABLE); 1826 1827 /* 1828 * reset internal state 1829 */ 1830 scp->sp_txinuse = 0; 1831 scp->sp_txcur = 0; 1832 scp->cka_lasttx = time.tv_usec; 1833 scp->cka_lastrx = 0; 1834 } 1835 1836 /* 1837 * set a port to the "down" state 1838 */ 1839 static void 1840 sca_port_down(sca_port_t *scp) 1841 { 1842 struct sca_softc *sc = scp->sca; 1843 #if 0 1844 u_int8_t ier0, ier1; 1845 #endif 1846 1847 /* 1848 * lower DTR 1849 */ 1850 sc->sc_dtr_callback(sc->sc_aux, scp->sp_port, 0); 1851 1852 /* 1853 * lower RTS 1854 */ 1855 msci_write_1(scp, SCA_CTL0, 1856 (msci_read_1(scp, SCA_CTL0) & ~SCA_CTL_RTS_MASK) 1857 | SCA_CTL_RTS_LOW); 1858 1859 /* 1860 * disable interrupts 1861 */ 1862 #if 0 1863 ier0 = SCA_IER0_MSCI_RXRDY0 | SCA_IER0_MSCI_TXRDY0 1864 | SCA_IER0_MSCI_RXINT0 | SCA_IER0_MSCI_TXINT0; 1865 ier1 = SCA_IER1_DMAC_RX0A | SCA_IER1_DMAC_RX0B 1866 | SCA_IER1_DMAC_TX0A | SCA_IER1_DMAC_TX0B; 1867 if (scp->sp_port == 1) { 1868 ier0 <<= 4; 1869 ier1 <<= 4; 1870 } 1871 sca_write_1(sc, SCA_IER0, sca_read_1(sc, SCA_IER0) & ~ier0); 1872 sca_write_1(sc, SCA_IER1, sca_read_1(sc, SCA_IER1) & ~ier1); 1873 #else 1874 if (scp->sp_port == 0) { 1875 sca_write_1(sc, SCA_IER0, sca_read_1(sc, SCA_IER0) & 0xf0); 1876 sca_write_1(sc, SCA_IER1, sca_read_1(sc, SCA_IER1) & 0xf0); 1877 } else { 1878 sca_write_1(sc, SCA_IER0, sca_read_1(sc, SCA_IER0) & 0x0f); 1879 sca_write_1(sc, SCA_IER1, sca_read_1(sc, SCA_IER1) & 0x0f); 1880 } 1881 #endif 1882 1883 /* 1884 * disable transmit and receive 1885 */ 1886 msci_write_1(scp, SCA_CMD0, SCA_CMD_RXDISABLE); 1887 msci_write_1(scp, SCA_CMD0, SCA_CMD_TXDISABLE); 1888 1889 /* 1890 * no, we're not in use anymore 1891 */ 1892 scp->sp_if.if_flags &= ~(IFF_OACTIVE|IFF_RUNNING); 1893 } 1894 1895 /* 1896 * disable all DMA and interrupts for all ports at once. 1897 */ 1898 void 1899 sca_shutdown(struct sca_softc *sca) 1900 { 1901 /* 1902 * disable DMA and interrupts 1903 */ 1904 sca_write_1(sca, SCA_DMER, 0); 1905 sca_write_1(sca, SCA_IER0, 0); 1906 sca_write_1(sca, SCA_IER1, 0); 1907 } 1908 1909 /* 1910 * If there are packets to transmit, start the transmit DMA logic. 1911 */ 1912 static void 1913 sca_port_starttx(sca_port_t *scp) 1914 { 1915 struct sca_softc *sc; 1916 u_int32_t startdesc_p, enddesc_p; 1917 int enddesc; 1918 1919 sc = scp->sca; 1920 1921 SCA_DPRINTF(SCA_DEBUG_TX, ("TX: starttx\n")); 1922 1923 if (((scp->sp_if.if_flags & IFF_OACTIVE) == IFF_OACTIVE) 1924 || scp->sp_txinuse == 0) 1925 return; 1926 1927 SCA_DPRINTF(SCA_DEBUG_TX, ("TX: setting oactive\n")); 1928 1929 scp->sp_if.if_flags |= IFF_OACTIVE; 1930 1931 /* 1932 * We have something to do, since we have at least one packet 1933 * waiting, and we are not already marked as active. 1934 */ 1935 enddesc = (scp->sp_txcur + 1) % scp->sp_ntxdesc; 1936 startdesc_p = scp->sp_txdesc_p; 1937 enddesc_p = scp->sp_txdesc_p + sizeof(sca_desc_t) * enddesc; 1938 1939 SCA_DPRINTF(SCA_DEBUG_TX, ("TX: start %x end %x\n", 1940 startdesc_p, enddesc_p)); 1941 1942 dmac_write_2(scp, SCA_EDAL1, (u_int16_t)(enddesc_p & 0x0000ffff)); 1943 dmac_write_2(scp, SCA_CDAL1, 1944 (u_int16_t)(startdesc_p & 0x0000ffff)); 1945 1946 /* 1947 * enable the DMA 1948 */ 1949 dmac_write_1(scp, SCA_DSR1, SCA_DSR_DE); 1950 } 1951 1952 /* 1953 * allocate an mbuf at least long enough to hold "len" bytes. 1954 * If "p" is non-NULL, copy "len" bytes from it into the new mbuf, 1955 * otherwise let the caller handle copying the data in. 1956 */ 1957 static struct mbuf * 1958 sca_mbuf_alloc(struct sca_softc *sc, caddr_t p, u_int len) 1959 { 1960 struct mbuf *m; 1961 1962 /* 1963 * allocate an mbuf and copy the important bits of data 1964 * into it. If the packet won't fit in the header, 1965 * allocate a cluster for it and store it there. 1966 */ 1967 MGETHDR(m, M_DONTWAIT, MT_DATA); 1968 if (m == NULL) 1969 return NULL; 1970 if (len > MHLEN) { 1971 if (len > MCLBYTES) { 1972 m_freem(m); 1973 return NULL; 1974 } 1975 MCLGET(m, M_DONTWAIT); 1976 if ((m->m_flags & M_EXT) == 0) { 1977 m_freem(m); 1978 return NULL; 1979 } 1980 } 1981 if (p != NULL) { 1982 /* XXX do we need to sync here? */ 1983 if (sc->sc_usedma) 1984 bcopy(p, mtod(m, caddr_t), len); 1985 else 1986 bus_space_read_region_1(sc->scu_memt, sc->scu_memh, 1987 sca_page_addr(sc, p), mtod(m, u_int8_t *), len); 1988 } 1989 m->m_len = len; 1990 m->m_pkthdr.len = len; 1991 1992 return (m); 1993 } 1994 1995 /* 1996 * get the base clock 1997 */ 1998 void 1999 sca_get_base_clock(struct sca_softc *sc) 2000 { 2001 struct timeval btv, ctv, dtv; 2002 u_int64_t bcnt; 2003 u_int32_t cnt; 2004 u_int16_t subcnt; 2005 2006 /* disable the timer, set prescale to 0 */ 2007 sca_write_1(sc, SCA_TCSR0, 0); 2008 sca_write_1(sc, SCA_TEPR0, 0); 2009 2010 /* reset the counter */ 2011 (void)sca_read_1(sc, SCA_TCSR0); 2012 subcnt = sca_read_2(sc, SCA_TCNTL0); 2013 2014 /* count to max */ 2015 sca_write_2(sc, SCA_TCONRL0, 0xffff); 2016 2017 cnt = 0; 2018 microtime(&btv); 2019 /* start the timer -- no interrupt enable */ 2020 sca_write_1(sc, SCA_TCSR0, SCA_TCSR_TME); 2021 for (;;) { 2022 microtime(&ctv); 2023 2024 /* end around 3/4 of a second */ 2025 timersub(&ctv, &btv, &dtv); 2026 if (dtv.tv_usec >= 750000) 2027 break; 2028 2029 /* spin */ 2030 while (!(sca_read_1(sc, SCA_TCSR0) & SCA_TCSR_CMF)) 2031 ; 2032 /* reset the timer */ 2033 (void)sca_read_2(sc, SCA_TCNTL0); 2034 cnt++; 2035 } 2036 2037 /* stop the timer */ 2038 sca_write_1(sc, SCA_TCSR0, 0); 2039 2040 subcnt = sca_read_2(sc, SCA_TCNTL0); 2041 /* add the slop in and get the total timer ticks */ 2042 cnt = (cnt << 16) | subcnt; 2043 2044 /* cnt is 1/8 the actual time */ 2045 bcnt = cnt * 8; 2046 /* make it proportional to 3/4 of a second */ 2047 bcnt *= (u_int64_t)750000; 2048 bcnt /= (u_int64_t)dtv.tv_usec; 2049 cnt = bcnt; 2050 2051 /* make it Hz */ 2052 cnt *= 4; 2053 cnt /= 3; 2054 2055 SCA_DPRINTF(SCA_DEBUG_CLOCK, 2056 ("sca: unadjusted base %lu Hz\n", (u_long)cnt)); 2057 2058 /* 2059 * round to the nearest 200 -- this allows for +-3 ticks error 2060 */ 2061 sc->sc_baseclock = ((cnt + 100) / 200) * 200; 2062 } 2063 2064 /* 2065 * print the information about the clock on the ports 2066 */ 2067 void 2068 sca_print_clock_info(struct sca_softc *sc) 2069 { 2070 struct sca_port *scp; 2071 u_int32_t mhz, div; 2072 int i; 2073 2074 printf("%s: base clock %d Hz\n", sc->sc_parent->dv_xname, 2075 sc->sc_baseclock); 2076 2077 /* print the information about the port clock selection */ 2078 for (i = 0; i < sc->sc_numports; i++) { 2079 scp = &sc->sc_ports[i]; 2080 mhz = sc->sc_baseclock / (scp->sp_tmc ? scp->sp_tmc : 256); 2081 div = scp->sp_rxs & SCA_RXS_DIV_MASK; 2082 2083 printf("%s: rx clock: ", scp->sp_if.if_xname); 2084 switch (scp->sp_rxs & SCA_RXS_CLK_MASK) { 2085 case SCA_RXS_CLK_LINE: 2086 printf("line"); 2087 break; 2088 case SCA_RXS_CLK_LINE_SN: 2089 printf("line with noise suppression"); 2090 break; 2091 case SCA_RXS_CLK_INTERNAL: 2092 printf("internal %d Hz", (mhz >> div)); 2093 break; 2094 case SCA_RXS_CLK_ADPLL_OUT: 2095 printf("adpll using internal %d Hz", (mhz >> div)); 2096 break; 2097 case SCA_RXS_CLK_ADPLL_IN: 2098 printf("adpll using line clock"); 2099 break; 2100 } 2101 printf(" tx clock: "); 2102 div = scp->sp_txs & SCA_TXS_DIV_MASK; 2103 switch (scp->sp_txs & SCA_TXS_CLK_MASK) { 2104 case SCA_TXS_CLK_LINE: 2105 printf("line\n"); 2106 break; 2107 case SCA_TXS_CLK_INTERNAL: 2108 printf("internal %d Hz\n", (mhz >> div)); 2109 break; 2110 case SCA_TXS_CLK_RXCLK: 2111 printf("rxclock\n"); 2112 break; 2113 } 2114 if (scp->sp_eclock) 2115 printf("%s: outputting line clock\n", 2116 scp->sp_if.if_xname); 2117 } 2118 } 2119 2120
Indexes created Sun Sep 28 16:09:52 GMT 2025