hd64570.c revision 1.4
1 /* $NetBSD: hd64570.c,v 1.4 1998/12/09 23:25:41 tls Exp $ */ 2 3 /* 4 * Copyright (c) 1998 Vixie Enterprises 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of Vixie Enterprises nor the names 17 * of its contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY VIXIE ENTERPRISES AND 21 * CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 22 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL VIXIE ENTERPRISES OR 25 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 29 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * This software has been written for Vixie Enterprises by Michael Graff 35 * <explorer (at) flame.org>. To learn more about Vixie Enterprises, see 36 * ``http://www.vix.com''. 37 */ 38 39 /* 40 * TODO: 41 * 42 * o teach the receive logic about errors, and about long frames that 43 * span more than one input buffer. (Right now, receive/transmit is 44 * limited to one descriptor's buffer space, which is MTU + 4 bytes. 45 * This is currently 1504, which is large enough to hold the HDLC 46 * header and the packet itself. Packets which are too long are 47 * silently dropped on transmit and silently dropped on receive. 48 * o write code to handle the msci interrupts, needed only for CD 49 * and CTS changes. 50 * o consider switching back to a "queue tx with DMA active" model which 51 * should help sustain outgoing traffic 52 * o through clever use of bus_dma*() functions, it should be possible 53 * to map the mbuf's data area directly into a descriptor transmit 54 * buffer, removing the need to allocate extra memory. If, however, 55 * we run out of descriptors for this, we will need to then allocate 56 * one large mbuf, copy the fragmented chain into it, and put it onto 57 * a single descriptor. 58 * o use bus_dmamap_sync() with the right offset and lengths, rather 59 * than cheating and always sync'ing the whole region. 60 */ 61 62 #include "bpfilter.h" 63 64 #include <sys/param.h> 65 #include <sys/systm.h> 66 #include <sys/device.h> 67 #include <sys/mbuf.h> 68 #include <sys/socket.h> 69 #include <sys/sockio.h> 70 #include <sys/kernel.h> 71 72 #include <net/if.h> 73 #include <net/if_types.h> 74 #include <net/netisr.h> 75 76 #include <netinet/in.h> 77 #include <netinet/in_systm.h> 78 #include <netinet/in_var.h> 79 #include <netinet/ip.h> 80 81 #if NBPFILTER > 0 82 #include <net/bpf.h> 83 #endif 84 85 #include <machine/cpu.h> 86 #include <machine/bus.h> 87 #include <machine/intr.h> 88 89 #include <dev/pci/pcivar.h> 90 #include <dev/pci/pcireg.h> 91 #include <dev/pci/pcidevs.h> 92 93 #include <dev/ic/hd64570reg.h> 94 #include <dev/ic/hd64570var.h> 95 96 #define SCA_DEBUG_RX 0x0001 97 #define SCA_DEBUG_TX 0x0002 98 #define SCA_DEBUG_CISCO 0x0004 99 #define SCA_DEBUG_DMA 0x0008 100 #define SCA_DEBUG_RXPKT 0x0010 101 #define SCA_DEBUG_TXPKT 0x0020 102 #define SCA_DEBUG_INTR 0x0040 103 104 #if 0 105 #define SCA_DEBUG_LEVEL ( SCA_DEBUG_TX ) 106 #else 107 #define SCA_DEBUG_LEVEL 0 108 #endif 109 110 u_int32_t sca_debug = SCA_DEBUG_LEVEL; 111 112 #if SCA_DEBUG_LEVEL > 0 113 #define SCA_DPRINTF(l, x) do { \ 114 if ((l) & sca_debug) \ 115 printf x;\ 116 } while (0) 117 #else 118 #define SCA_DPRINTF(l, x) 119 #endif 120 121 #define SCA_MTU 1500 /* hard coded */ 122 123 /* 124 * buffers per tx and rx channels, per port, and the size of each. 125 * Don't use these constants directly, as they are really only hints. 126 * Use the calculated values stored in struct sca_softc instead. 127 * 128 * Each must be at least 2, receive would be better at around 20 or so. 129 * 130 * XXX Due to a damned near impossible to track down bug, transmit buffers 131 * MUST be 2, no more, no less. 132 */ 133 #ifndef SCA_NtxBUFS 134 #define SCA_NtxBUFS 2 135 #endif 136 #ifndef SCA_NrxBUFS 137 #define SCA_NrxBUFS 20 138 #endif 139 #ifndef SCA_BSIZE 140 #define SCA_BSIZE (SCA_MTU + 4) /* room for HDLC as well */ 141 #endif 142 143 #if 0 144 #define SCA_USE_FASTQ /* use a split queue, one for fast traffic */ 145 #endif 146 147 static inline void sca_write_1(struct sca_softc *, u_int, u_int8_t); 148 static inline void sca_write_2(struct sca_softc *, u_int, u_int16_t); 149 static inline u_int8_t sca_read_1(struct sca_softc *, u_int); 150 static inline u_int16_t sca_read_2(struct sca_softc *, u_int); 151 152 static inline void msci_write_1(sca_port_t *, u_int, u_int8_t); 153 static inline u_int8_t msci_read_1(sca_port_t *, u_int); 154 155 static inline void dmac_write_1(sca_port_t *, u_int, u_int8_t); 156 static inline void dmac_write_2(sca_port_t *, u_int, u_int16_t); 157 static inline u_int8_t dmac_read_1(sca_port_t *, u_int); 158 static inline u_int16_t dmac_read_2(sca_port_t *, u_int); 159 160 static int sca_alloc_dma(struct sca_softc *); 161 static void sca_setup_dma_memory(struct sca_softc *); 162 static void sca_msci_init(struct sca_softc *, sca_port_t *); 163 static void sca_dmac_init(struct sca_softc *, sca_port_t *); 164 static void sca_dmac_rxinit(sca_port_t *); 165 166 static int sca_dmac_intr(sca_port_t *, u_int8_t); 167 static int sca_msci_intr(struct sca_softc *, u_int8_t); 168 169 static void sca_get_packets(sca_port_t *); 170 static void sca_frame_process(sca_port_t *, sca_desc_t *, u_int8_t *); 171 static int sca_frame_avail(sca_port_t *, int *); 172 static void sca_frame_skip(sca_port_t *, int); 173 174 static void sca_port_starttx(sca_port_t *); 175 176 static void sca_port_up(sca_port_t *); 177 static void sca_port_down(sca_port_t *); 178 179 static int sca_output __P((struct ifnet *, struct mbuf *, struct sockaddr *, 180 struct rtentry *)); 181 static int sca_ioctl __P((struct ifnet *, u_long, caddr_t)); 182 static void sca_start __P((struct ifnet *)); 183 static void sca_watchdog __P((struct ifnet *)); 184 185 static struct mbuf *sca_mbuf_alloc(caddr_t, u_int); 186 187 #if SCA_DEBUG_LEVEL > 0 188 static void sca_frame_print(sca_port_t *, sca_desc_t *, u_int8_t *); 189 #endif 190 191 static inline void 192 sca_write_1(struct sca_softc *sc, u_int reg, u_int8_t val) 193 { 194 bus_space_write_1(sc->sc_iot, sc->sc_ioh, SCADDR(reg), val); 195 } 196 197 static inline void 198 sca_write_2(struct sca_softc *sc, u_int reg, u_int16_t val) 199 { 200 bus_space_write_2(sc->sc_iot, sc->sc_ioh, SCADDR(reg), val); 201 } 202 203 static inline u_int8_t 204 sca_read_1(struct sca_softc *sc, u_int reg) 205 { 206 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, SCADDR(reg)); 207 } 208 209 static inline u_int16_t 210 sca_read_2(struct sca_softc *sc, u_int reg) 211 { 212 return bus_space_read_2(sc->sc_iot, sc->sc_ioh, SCADDR(reg)); 213 } 214 215 static inline void 216 msci_write_1(sca_port_t *scp, u_int reg, u_int8_t val) 217 { 218 sca_write_1(scp->sca, scp->msci_off + reg, val); 219 } 220 221 static inline u_int8_t 222 msci_read_1(sca_port_t *scp, u_int reg) 223 { 224 return sca_read_1(scp->sca, scp->msci_off + reg); 225 } 226 227 static inline void 228 dmac_write_1(sca_port_t *scp, u_int reg, u_int8_t val) 229 { 230 sca_write_1(scp->sca, scp->dmac_off + reg, val); 231 } 232 233 static inline void 234 dmac_write_2(sca_port_t *scp, u_int reg, u_int16_t val) 235 { 236 sca_write_2(scp->sca, scp->dmac_off + reg, val); 237 } 238 239 static inline u_int8_t 240 dmac_read_1(sca_port_t *scp, u_int reg) 241 { 242 return sca_read_1(scp->sca, scp->dmac_off + reg); 243 } 244 245 static inline u_int16_t 246 dmac_read_2(sca_port_t *scp, u_int reg) 247 { 248 return sca_read_2(scp->sca, scp->dmac_off + reg); 249 } 250 251 int 252 sca_init(struct sca_softc *sc, u_int nports) 253 { 254 /* 255 * Do a little sanity check: check number of ports. 256 */ 257 if (nports < 1 || nports > 2) 258 return 1; 259 260 /* 261 * remember the details 262 */ 263 sc->sc_numports = nports; 264 265 /* 266 * allocate the memory and chop it into bits. 267 */ 268 if (sca_alloc_dma(sc) != 0) 269 return 1; 270 sca_setup_dma_memory(sc); 271 272 /* 273 * disable DMA and MSCI interrupts 274 */ 275 sca_write_1(sc, SCA_DMER, 0); 276 sca_write_1(sc, SCA_IER0, 0); 277 sca_write_1(sc, SCA_IER1, 0); 278 sca_write_1(sc, SCA_IER2, 0); 279 280 /* 281 * configure interrupt system 282 */ 283 sca_write_1(sc, SCA_ITCR, 0); /* use ivr, no int ack */ 284 sca_write_1(sc, SCA_IVR, 0x40); 285 sca_write_1(sc, SCA_IMVR, 0x40); 286 287 /* 288 * set wait control register to zero wait states 289 */ 290 sca_write_1(sc, SCA_PABR0, 0); 291 sca_write_1(sc, SCA_PABR1, 0); 292 sca_write_1(sc, SCA_WCRL, 0); 293 sca_write_1(sc, SCA_WCRM, 0); 294 sca_write_1(sc, SCA_WCRH, 0); 295 296 /* 297 * disable DMA and reset status 298 */ 299 sca_write_1(sc, SCA_PCR, SCA_PCR_PR2); 300 301 /* 302 * disable transmit DMA for all channels 303 */ 304 sca_write_1(sc, SCA_DSR0 + SCA_DMAC_OFF_0, 0); 305 sca_write_1(sc, SCA_DCR0 + SCA_DMAC_OFF_0, SCA_DCR_ABRT); 306 sca_write_1(sc, SCA_DSR1 + SCA_DMAC_OFF_0, 0); 307 sca_write_1(sc, SCA_DCR1 + SCA_DMAC_OFF_0, SCA_DCR_ABRT); 308 sca_write_1(sc, SCA_DSR0 + SCA_DMAC_OFF_1, 0); 309 sca_write_1(sc, SCA_DCR0 + SCA_DMAC_OFF_1, SCA_DCR_ABRT); 310 sca_write_1(sc, SCA_DSR1 + SCA_DMAC_OFF_1, 0); 311 sca_write_1(sc, SCA_DCR1 + SCA_DMAC_OFF_1, SCA_DCR_ABRT); 312 313 /* 314 * enable DMA based on channel enable flags for each channel 315 */ 316 sca_write_1(sc, SCA_DMER, SCA_DMER_EN); 317 318 /* 319 * Should check to see if the chip is responding, but for now 320 * assume it is. 321 */ 322 return 0; 323 } 324 325 /* 326 * initialize the port and attach it to the networking layer 327 */ 328 void 329 sca_port_attach(struct sca_softc *sc, u_int port) 330 { 331 sca_port_t *scp = &sc->sc_ports[port]; 332 struct ifnet *ifp; 333 static u_int ntwo_unit = 0; 334 335 scp->sca = sc; /* point back to the parent */ 336 337 scp->sp_port = port; 338 339 if (port == 0) { 340 scp->msci_off = SCA_MSCI_OFF_0; 341 scp->dmac_off = SCA_DMAC_OFF_0; 342 if(sc->parent != NULL) 343 ntwo_unit=sc->parent->dv_unit * 2 + 0; 344 else 345 ntwo_unit = 0; /* XXX */ 346 } else { 347 scp->msci_off = SCA_MSCI_OFF_1; 348 scp->dmac_off = SCA_DMAC_OFF_1; 349 if(sc->parent != NULL) 350 ntwo_unit=sc->parent->dv_unit * 2 + 1; 351 else 352 ntwo_unit = 1; /* XXX */ 353 } 354 355 sca_msci_init(sc, scp); 356 sca_dmac_init(sc, scp); 357 358 /* 359 * attach to the network layer 360 */ 361 ifp = &scp->sp_if; 362 sprintf(ifp->if_xname, "ntwo%d", ntwo_unit); 363 ifp->if_softc = scp; 364 ifp->if_mtu = SCA_MTU; 365 ifp->if_flags = IFF_POINTOPOINT | IFF_MULTICAST; 366 ifp->if_type = IFT_OTHER; /* Should be HDLC, but... */ 367 ifp->if_hdrlen = HDLC_HDRLEN; 368 ifp->if_ioctl = sca_ioctl; 369 ifp->if_output = sca_output; 370 ifp->if_watchdog = sca_watchdog; 371 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 372 scp->linkq.ifq_maxlen = 5; /* if we exceed this we are hosed already */ 373 #ifdef SCA_USE_FASTQ 374 scp->fastq.ifq_maxlen = IFQ_MAXLEN; 375 #endif 376 if_attach(ifp); 377 378 #if NBPFILTER > 0 379 bpfattach(&scp->sp_bpf, ifp, DLT_HDLC, HDLC_HDRLEN); 380 #endif 381 382 if (sc->parent == NULL) 383 printf("%s: port %d\n", ifp->if_xname, port); 384 else 385 printf("%s at %s port %d\n", 386 ifp->if_xname, sc->parent->dv_xname, port); 387 388 /* 389 * reset the last seen times on the cisco keepalive protocol 390 */ 391 scp->cka_lasttx = time.tv_usec; 392 scp->cka_lastrx = 0; 393 } 394 395 /* 396 * initialize the port's MSCI 397 */ 398 static void 399 sca_msci_init(struct sca_softc *sc, sca_port_t *scp) 400 { 401 msci_write_1(scp, SCA_CMD0, SCA_CMD_RESET); 402 msci_write_1(scp, SCA_MD00, 403 ( SCA_MD0_CRC_1 404 | SCA_MD0_CRC_CCITT 405 | SCA_MD0_CRC_ENABLE 406 | SCA_MD0_MODE_HDLC)); 407 msci_write_1(scp, SCA_MD10, SCA_MD1_NOADDRCHK); 408 msci_write_1(scp, SCA_MD20, 409 (SCA_MD2_DUPLEX | SCA_MD2_NRZ)); 410 411 /* 412 * reset the port (and lower RTS) 413 */ 414 msci_write_1(scp, SCA_CMD0, SCA_CMD_RXRESET); 415 msci_write_1(scp, SCA_CTL0, 416 (SCA_CTL_IDLPAT | SCA_CTL_UDRNC | SCA_CTL_RTS)); 417 msci_write_1(scp, SCA_CMD0, SCA_CMD_TXRESET); 418 419 /* 420 * select the RX clock as the TX clock, and set for external 421 * clock source. 422 */ 423 msci_write_1(scp, SCA_RXS0, 0); 424 msci_write_1(scp, SCA_TXS0, 0); 425 426 /* 427 * XXX don't pay attention to CTS or CD changes right now. I can't 428 * simulate one, and the transmitter will try to transmit even if 429 * CD isn't there anyway, so nothing bad SHOULD happen. 430 */ 431 msci_write_1(scp, SCA_IE00, 0); 432 msci_write_1(scp, SCA_IE10, 0); /* 0x0c == CD and CTS changes only */ 433 msci_write_1(scp, SCA_IE20, 0); 434 msci_write_1(scp, SCA_FIE0, 0); 435 436 msci_write_1(scp, SCA_SA00, 0); 437 msci_write_1(scp, SCA_SA10, 0); 438 439 msci_write_1(scp, SCA_IDL0, 0x7e); 440 441 msci_write_1(scp, SCA_RRC0, 0x0e); 442 msci_write_1(scp, SCA_TRC00, 0x10); 443 msci_write_1(scp, SCA_TRC10, 0x1f); 444 } 445 446 /* 447 * Take the memory for the port and construct two circular linked lists of 448 * descriptors (one tx, one rx) and set the pointers in these descriptors 449 * to point to the buffer space for this port. 450 */ 451 static void 452 sca_dmac_init(struct sca_softc *sc, sca_port_t *scp) 453 { 454 sca_desc_t *desc; 455 u_int32_t desc_p; 456 u_int32_t buf_p; 457 int i; 458 459 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmam, 460 0, sc->sc_allocsize, BUS_DMASYNC_PREWRITE); 461 462 desc = scp->txdesc; 463 desc_p = scp->txdesc_p; 464 buf_p = scp->txbuf_p; 465 scp->txcur = 0; 466 scp->txinuse = 0; 467 468 for (i = 0 ; i < SCA_NtxBUFS ; i++) { 469 /* 470 * desc_p points to the physcial address of the NEXT desc 471 */ 472 desc_p += sizeof(sca_desc_t); 473 474 desc->cp = desc_p & 0x0000ffff; 475 desc->bp = buf_p & 0x0000ffff; 476 desc->bpb = (buf_p & 0x00ff0000) >> 16; 477 desc->len = SCA_BSIZE; 478 desc->stat = 0; 479 480 desc++; /* point to the next descriptor */ 481 buf_p += SCA_BSIZE; 482 } 483 484 /* 485 * "heal" the circular list by making the last entry point to the 486 * first. 487 */ 488 desc--; 489 desc->cp = scp->txdesc_p & 0x0000ffff; 490 491 /* 492 * Now, initialize the transmit DMA logic 493 * 494 * CPB == chain pointer base address 495 */ 496 dmac_write_1(scp, SCA_DSR1, 0); 497 dmac_write_1(scp, SCA_DCR1, SCA_DCR_ABRT); 498 dmac_write_1(scp, SCA_DMR1, SCA_DMR_TMOD | SCA_DMR_NF); 499 dmac_write_1(scp, SCA_DIR1, 500 (SCA_DIR_EOT | SCA_DIR_BOF | SCA_DIR_COF)); 501 dmac_write_1(scp, SCA_CPB1, 502 (u_int8_t)((scp->txdesc_p & 0x00ff0000) >> 16)); 503 504 /* 505 * now, do the same thing for receive descriptors 506 */ 507 desc = scp->rxdesc; 508 desc_p = scp->rxdesc_p; 509 buf_p = scp->rxbuf_p; 510 scp->rxstart = 0; 511 scp->rxend = SCA_NrxBUFS - 1; 512 513 for (i = 0 ; i < SCA_NrxBUFS ; i++) { 514 /* 515 * desc_p points to the physcial address of the NEXT desc 516 */ 517 desc_p += sizeof(sca_desc_t); 518 519 desc->cp = desc_p & 0x0000ffff; 520 desc->bp = buf_p & 0x0000ffff; 521 desc->bpb = (buf_p & 0x00ff0000) >> 16; 522 desc->len = SCA_BSIZE; 523 desc->stat = 0x00; 524 525 desc++; /* point to the next descriptor */ 526 buf_p += SCA_BSIZE; 527 } 528 529 /* 530 * "heal" the circular list by making the last entry point to the 531 * first. 532 */ 533 desc--; 534 desc->cp = scp->rxdesc_p & 0x0000ffff; 535 536 sca_dmac_rxinit(scp); 537 538 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmam, 539 0, sc->sc_allocsize, BUS_DMASYNC_POSTWRITE); 540 } 541 542 /* 543 * reset and reinitialize the receive DMA logic 544 */ 545 static void 546 sca_dmac_rxinit(sca_port_t *scp) 547 { 548 /* 549 * ... and the receive DMA logic ... 550 */ 551 dmac_write_1(scp, SCA_DSR0, 0); /* disable DMA */ 552 dmac_write_1(scp, SCA_DCR0, SCA_DCR_ABRT); 553 554 dmac_write_1(scp, SCA_DMR0, SCA_DMR_TMOD | SCA_DMR_NF); 555 dmac_write_2(scp, SCA_BFLL0, SCA_BSIZE); 556 557 /* 558 * CPB == chain pointer base 559 * CDA == current descriptor address 560 * EDA == error descriptor address (overwrite position) 561 */ 562 dmac_write_1(scp, SCA_CPB0, 563 (u_int8_t)((scp->rxdesc_p & 0x00ff0000) >> 16)); 564 dmac_write_2(scp, SCA_CDAL0, 565 (u_int16_t)(scp->rxdesc_p & 0xffff)); 566 dmac_write_2(scp, SCA_EDAL0, 567 (u_int16_t)(scp->rxdesc_p 568 + sizeof(sca_desc_t) * SCA_NrxBUFS)); 569 570 /* 571 * enable receiver DMA 572 */ 573 dmac_write_1(scp, SCA_DIR0, 574 (SCA_DIR_EOT | SCA_DIR_EOM | SCA_DIR_BOF | SCA_DIR_COF)); 575 dmac_write_1(scp, SCA_DSR0, SCA_DSR_DE); 576 } 577 578 static int 579 sca_alloc_dma(struct sca_softc *sc) 580 { 581 u_int allocsize; 582 int err; 583 int rsegs; 584 u_int bpp; 585 586 SCA_DPRINTF(SCA_DEBUG_DMA, 587 ("sizeof sca_desc_t: %d bytes\n", sizeof (sca_desc_t))); 588 589 bpp = sc->sc_numports * (SCA_NtxBUFS + SCA_NrxBUFS); 590 591 allocsize = bpp * (SCA_BSIZE + sizeof (sca_desc_t)); 592 593 /* 594 * sanity checks: 595 * 596 * Check the total size of the data buffers, and so on. The total 597 * DMAable space needs to fit within a single 16M region, and the 598 * descriptors need to fit within a 64K region. 599 */ 600 if (allocsize > 16 * 1024 * 1024) 601 return 1; 602 if (bpp * sizeof (sca_desc_t) > 64 * 1024) 603 return 1; 604 605 sc->sc_allocsize = allocsize; 606 607 /* 608 * Allocate one huge chunk of memory. 609 */ 610 if (bus_dmamem_alloc(sc->sc_dmat, 611 allocsize, 612 SCA_DMA_ALIGNMENT, 613 SCA_DMA_BOUNDRY, 614 &sc->sc_seg, 1, &rsegs, BUS_DMA_NOWAIT) != 0) { 615 printf("Could not allocate DMA memory\n"); 616 return 1; 617 } 618 SCA_DPRINTF(SCA_DEBUG_DMA, 619 ("DMA memory allocated: %d bytes\n", allocsize)); 620 621 if (bus_dmamem_map(sc->sc_dmat, &sc->sc_seg, 1, allocsize, 622 &sc->sc_dma_addr, BUS_DMA_NOWAIT) != 0) { 623 printf("Could not map DMA memory into kernel space\n"); 624 return 1; 625 } 626 SCA_DPRINTF(SCA_DEBUG_DMA, ("DMA memory mapped\n")); 627 628 if (bus_dmamap_create(sc->sc_dmat, allocsize, 2, 629 allocsize, SCA_DMA_BOUNDRY, 630 BUS_DMA_NOWAIT, &sc->sc_dmam) != 0) { 631 printf("Could not create DMA map\n"); 632 return 1; 633 } 634 SCA_DPRINTF(SCA_DEBUG_DMA, ("DMA map created\n")); 635 636 err = bus_dmamap_load(sc->sc_dmat, sc->sc_dmam, sc->sc_dma_addr, 637 allocsize, NULL, BUS_DMA_NOWAIT); 638 if (err != 0) { 639 printf("Could not load DMA segment: %d\n", err); 640 return 1; 641 } 642 SCA_DPRINTF(SCA_DEBUG_DMA, ("DMA map loaded\n")); 643 644 return 0; 645 } 646 647 /* 648 * Take the memory allocated with sca_alloc_dma() and divide it among the 649 * two ports. 650 */ 651 static void 652 sca_setup_dma_memory(struct sca_softc *sc) 653 { 654 sca_port_t *scp0, *scp1; 655 u_int8_t *vaddr0; 656 u_int32_t paddr0; 657 u_long addroff; 658 659 /* 660 * remember the physical address to 24 bits only, since the upper 661 * 8 bits is programed into the device at a different layer. 662 */ 663 paddr0 = (sc->sc_dmam->dm_segs[0].ds_addr & 0x00ffffff); 664 vaddr0 = sc->sc_dma_addr; 665 666 /* 667 * if we have only one port it gets the full range. If we have 668 * two we need to do a little magic to divide things up. 669 * 670 * The descriptors will all end up in the front of the area, while 671 * the remainder of the buffer is used for transmit and receive 672 * data. 673 * 674 * -------------------- start of memory 675 * tx desc port 0 676 * rx desc port 0 677 * tx desc port 1 678 * rx desc port 1 679 * tx buffer port 0 680 * rx buffer port 0 681 * tx buffer port 1 682 * rx buffer port 1 683 * -------------------- end of memory 684 */ 685 scp0 = &sc->sc_ports[0]; 686 scp1 = &sc->sc_ports[1]; 687 688 scp0->txdesc_p = paddr0; 689 scp0->txdesc = (sca_desc_t *)vaddr0; 690 addroff = sizeof(sca_desc_t) * SCA_NtxBUFS; 691 692 /* 693 * point to the range following the tx descriptors, and 694 * set the rx descriptors there. 695 */ 696 scp0->rxdesc_p = paddr0 + addroff; 697 scp0->rxdesc = (sca_desc_t *)(vaddr0 + addroff); 698 addroff += sizeof(sca_desc_t) * SCA_NrxBUFS; 699 700 if (sc->sc_numports == 2) { 701 scp1->txdesc_p = paddr0 + addroff; 702 scp1->txdesc = (sca_desc_t *)(vaddr0 + addroff); 703 addroff += sizeof(sca_desc_t) * SCA_NtxBUFS; 704 705 scp1->rxdesc_p = paddr0 + addroff; 706 scp1->rxdesc = (sca_desc_t *)(vaddr0 + addroff); 707 addroff += sizeof(sca_desc_t) * SCA_NrxBUFS; 708 } 709 710 /* 711 * point to the memory following the descriptors, and set the 712 * transmit buffer there. 713 */ 714 scp0->txbuf_p = paddr0 + addroff; 715 scp0->txbuf = vaddr0 + addroff; 716 addroff += SCA_BSIZE * SCA_NtxBUFS; 717 718 /* 719 * lastly, skip over the transmit buffer and set up pointers into 720 * the receive buffer. 721 */ 722 scp0->rxbuf_p = paddr0 + addroff; 723 scp0->rxbuf = vaddr0 + addroff; 724 addroff += SCA_BSIZE * SCA_NrxBUFS; 725 726 if (sc->sc_numports == 2) { 727 scp1->txbuf_p = paddr0 + addroff; 728 scp1->txbuf = vaddr0 + addroff; 729 addroff += SCA_BSIZE * SCA_NtxBUFS; 730 731 scp1->rxbuf_p = paddr0 + addroff; 732 scp1->rxbuf = vaddr0 + addroff; 733 addroff += SCA_BSIZE * SCA_NrxBUFS; 734 } 735 736 /* 737 * as a consistancy check, addroff should be equal to the allocation 738 * size. 739 */ 740 if (sc->sc_allocsize != addroff) 741 printf("ERROR: sc_allocsize != addroff: %lu != %lu\n", 742 sc->sc_allocsize, addroff); 743 } 744 745 /* 746 * Queue the packet for our start routine to transmit 747 */ 748 static int 749 sca_output(ifp, m, dst, rt0) 750 struct ifnet *ifp; 751 struct mbuf *m; 752 struct sockaddr *dst; 753 struct rtentry *rt0; 754 { 755 int error; 756 int s; 757 u_int16_t protocol; 758 hdlc_header_t *hdlc; 759 struct ifqueue *ifq; 760 #ifdef SCA_USE_FASTQ 761 struct ip *ip; 762 sca_port_t *scp = ifp->if_softc; 763 int highpri; 764 #endif 765 766 error = 0; 767 ifp->if_lastchange = time; 768 769 if ((ifp->if_flags & IFF_UP) != IFF_UP) { 770 error = ENETDOWN; 771 goto bad; 772 } 773 774 if (dst->sa_family != AF_INET) { 775 error = EAFNOSUPPORT; 776 goto bad; 777 } 778 779 #ifdef SCA_USE_FASTQ 780 highpri = 0; 781 #endif 782 783 /* 784 * determine address family, and priority for this packet 785 */ 786 switch (dst->sa_family) { 787 case AF_INET: 788 protocol = HDLC_PROTOCOL_IP; 789 790 #ifdef SCA_USE_FASTQ 791 ip = mtod(m, struct ip *); 792 if ((ip->ip_tos & IPTOS_LOWDELAY) == IPTOS_LOWDELAY) 793 highpri = 1; 794 #endif 795 break; 796 797 default: 798 printf("%s: address family %d unsupported\n", 799 ifp->if_xname, dst->sa_family); 800 error = EAFNOSUPPORT; 801 goto bad; 802 } 803 804 if (M_LEADINGSPACE(m) < HDLC_HDRLEN) { 805 m = m_prepend(m, HDLC_HDRLEN, M_DONTWAIT); 806 if (m == NULL) { 807 error = ENOBUFS; 808 goto bad; 809 } 810 m->m_len = 0; 811 } else { 812 m->m_data -= HDLC_HDRLEN; 813 } 814 815 hdlc = mtod(m, hdlc_header_t *); 816 if ((m->m_flags & (M_BCAST | M_MCAST)) != 0) 817 hdlc->addr = CISCO_MULTICAST; 818 else 819 hdlc->addr = CISCO_UNICAST; 820 hdlc->control = 0; 821 hdlc->protocol = htons(protocol); 822 m->m_len += HDLC_HDRLEN; 823 824 /* 825 * queue the packet. If interactive, use the fast queue. 826 */ 827 s = splnet(); 828 #ifdef SCA_USE_FASTQ 829 ifq = (highpri == 1 ? &scp->fastq : &ifp->if_snd); 830 #else 831 ifq = &ifp->if_snd; 832 #endif 833 if (IF_QFULL(ifq)) { 834 IF_DROP(ifq); 835 ifp->if_oerrors++; 836 ifp->if_collisions++; 837 error = ENOBUFS; 838 splx(s); 839 goto bad; 840 } 841 ifp->if_obytes += m->m_pkthdr.len; 842 IF_ENQUEUE(ifq, m); 843 844 ifp->if_lastchange = time; 845 846 if (m->m_flags & M_MCAST) 847 ifp->if_omcasts++; 848 849 sca_start(ifp); 850 splx(s); 851 852 return (error); 853 854 bad: 855 if (m) 856 m_freem(m); 857 return (error); 858 } 859 860 static int 861 sca_ioctl(ifp, cmd, addr) 862 struct ifnet *ifp; 863 u_long cmd; 864 caddr_t addr; 865 { 866 struct ifreq *ifr; 867 struct ifaddr *ifa; 868 int error; 869 int s; 870 871 s = splnet(); 872 873 ifr = (struct ifreq *)addr; 874 ifa = (struct ifaddr *)addr; 875 error = 0; 876 877 switch (cmd) { 878 case SIOCSIFADDR: 879 if (ifa->ifa_addr->sa_family == AF_INET) 880 sca_port_up(ifp->if_softc); 881 else 882 error = EAFNOSUPPORT; 883 break; 884 885 case SIOCSIFDSTADDR: 886 if (ifa->ifa_addr->sa_family != AF_INET) 887 error = EAFNOSUPPORT; 888 break; 889 890 case SIOCADDMULTI: 891 case SIOCDELMULTI: 892 if (ifr == 0) { 893 error = EAFNOSUPPORT; /* XXX */ 894 break; 895 } 896 switch (ifr->ifr_addr.sa_family) { 897 898 #ifdef INET 899 case AF_INET: 900 break; 901 #endif 902 903 default: 904 error = EAFNOSUPPORT; 905 break; 906 } 907 break; 908 909 case SIOCSIFFLAGS: 910 if (ifr->ifr_flags & IFF_UP) 911 sca_port_up(ifp->if_softc); 912 else 913 sca_port_down(ifp->if_softc); 914 915 break; 916 917 default: 918 error = EINVAL; 919 } 920 921 splx(s); 922 return error; 923 } 924 925 /* 926 * start packet transmission on the interface 927 * 928 * MUST BE CALLED AT splnet() 929 */ 930 static void 931 sca_start(ifp) 932 struct ifnet *ifp; 933 { 934 sca_port_t *scp = ifp->if_softc; 935 struct sca_softc *sc = scp->sca; 936 struct mbuf *m, *mb_head; 937 sca_desc_t *desc; 938 u_int8_t *buf, *obuf; 939 u_int32_t buf_p; 940 int trigger_xmit; 941 942 /* 943 * can't queue when we are full or transmitter is busy 944 */ 945 if ((scp->txinuse >= (SCA_NtxBUFS - 1)) 946 || ((ifp->if_flags & IFF_OACTIVE) == IFF_OACTIVE)) 947 return; 948 949 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmam, 950 0, sc->sc_allocsize, 951 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 952 953 trigger_xmit = 0; 954 955 txloop: 956 IF_DEQUEUE(&scp->linkq, mb_head); 957 if (mb_head == NULL) 958 #ifdef SCA_USE_FASTQ 959 IF_DEQUEUE(&scp->fastq, mb_head); 960 if (mb_head == NULL) 961 #endif 962 IF_DEQUEUE(&ifp->if_snd, mb_head); 963 if (mb_head == NULL) 964 goto start_xmit; 965 966 desc = &scp->txdesc[scp->txcur]; 967 if (scp->txinuse != 0) { 968 desc->stat &= ~SCA_DESC_EOT; 969 desc = &scp->txdesc[scp->txcur]; 970 } 971 buf = scp->txbuf + SCA_BSIZE * scp->txcur; 972 obuf = buf; 973 buf_p = scp->txbuf_p + SCA_BSIZE * scp->txcur; 974 975 desc->bp = (u_int16_t)(buf_p & 0x0000ffff); 976 desc->bpb = (u_int8_t)((buf_p & 0x00ff0000) >> 16); 977 desc->stat = SCA_DESC_EOT | SCA_DESC_EOM; /* end of frame and xfer */ 978 desc->len = 0; 979 980 /* 981 * Run through the chain, copying data into the descriptor as we 982 * go. If it won't fit in one transmission block, drop the packet. 983 * No, this isn't nice, but most of the time it _will_ fit. 984 */ 985 for (m = mb_head ; m != NULL ; m = m->m_next) { 986 if (m->m_len != 0) { 987 desc->len += m->m_len; 988 if (desc->len > SCA_BSIZE) { 989 m_freem(mb_head); 990 goto txloop; 991 } 992 bcopy(mtod(m, u_int8_t *), buf, m->m_len); 993 buf += m->m_len; 994 } 995 } 996 997 ifp->if_opackets++; 998 999 #if NBPFILTER > 0 1000 /* 1001 * Pass packet to bpf if there is a listener. 1002 */ 1003 if (scp->sp_bpf) 1004 bpf_mtap(scp->sp_bpf, mb_head); 1005 #endif 1006 1007 m_freem(mb_head); 1008 1009 if (scp->txinuse != 0) { 1010 scp->txcur++; 1011 if (scp->txcur == SCA_NtxBUFS) 1012 scp->txcur = 0; 1013 } 1014 scp->txinuse++; 1015 trigger_xmit = 1; 1016 1017 SCA_DPRINTF(SCA_DEBUG_TX, 1018 ("TX: inuse %d index %d\n", scp->txinuse, scp->txcur)); 1019 1020 if (scp->txinuse < (SCA_NtxBUFS - 1)) 1021 goto txloop; 1022 1023 start_xmit: 1024 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmam, 1025 0, sc->sc_allocsize, 1026 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1027 1028 if (trigger_xmit != 0) 1029 sca_port_starttx(scp); 1030 } 1031 1032 static void 1033 sca_watchdog(ifp) 1034 struct ifnet *ifp; 1035 { 1036 } 1037 1038 int 1039 sca_hardintr(struct sca_softc *sc) 1040 { 1041 u_int8_t isr0, isr1, isr2; 1042 int ret; 1043 1044 ret = 0; /* non-zero means we processed at least one interrupt */ 1045 1046 while (1) { 1047 /* 1048 * read SCA interrupts 1049 */ 1050 isr0 = sca_read_1(sc, SCA_ISR0); 1051 isr1 = sca_read_1(sc, SCA_ISR1); 1052 isr2 = sca_read_1(sc, SCA_ISR2); 1053 1054 if (isr0 == 0 && isr1 == 0 && isr2 == 0) 1055 break; 1056 1057 SCA_DPRINTF(SCA_DEBUG_INTR, 1058 ("isr0 = %02x, isr1 = %02x, isr2 = %02x\n", 1059 isr0, isr1, isr2)); 1060 1061 /* 1062 * check DMA interrupt 1063 */ 1064 if (isr1 & 0x0f) 1065 ret += sca_dmac_intr(&sc->sc_ports[0], 1066 isr1 & 0x0f); 1067 if (isr1 & 0xf0) 1068 ret += sca_dmac_intr(&sc->sc_ports[1], 1069 (isr1 & 0xf0) >> 4); 1070 1071 if (isr0) 1072 ret += sca_msci_intr(sc, isr0); 1073 1074 #if 0 /* We don't GET timer interrupts, we have them disabled (msci IE20) */ 1075 if (isr2) 1076 ret += sca_timer_intr(sc, isr2); 1077 #endif 1078 } 1079 1080 return (ret); 1081 } 1082 1083 static int 1084 sca_dmac_intr(sca_port_t *scp, u_int8_t isr) 1085 { 1086 u_int8_t dsr; 1087 int ret; 1088 1089 ret = 0; 1090 1091 /* 1092 * Check transmit channel 1093 */ 1094 if (isr & 0x0c) { 1095 SCA_DPRINTF(SCA_DEBUG_INTR, 1096 ("TX INTERRUPT port %d\n", scp->sp_port)); 1097 1098 dsr = 1; 1099 while (dsr != 0) { 1100 ret++; 1101 /* 1102 * reset interrupt 1103 */ 1104 dsr = dmac_read_1(scp, SCA_DSR1); 1105 dmac_write_1(scp, SCA_DSR1, 1106 dsr | SCA_DSR_DEWD); 1107 1108 /* 1109 * filter out the bits we don't care about 1110 */ 1111 dsr &= ( SCA_DSR_COF | SCA_DSR_BOF | SCA_DSR_EOT); 1112 if (dsr == 0) 1113 break; 1114 1115 /* 1116 * check for counter overflow 1117 */ 1118 if (dsr & SCA_DSR_COF) { 1119 printf("%s: TXDMA counter overflow\n", 1120 scp->sp_if.if_xname); 1121 1122 scp->sp_if.if_flags &= ~IFF_OACTIVE; 1123 scp->txcur = 0; 1124 scp->txinuse = 0; 1125 } 1126 1127 /* 1128 * check for buffer overflow 1129 */ 1130 if (dsr & SCA_DSR_BOF) { 1131 printf("%s: TXDMA buffer overflow, cda 0x%04x, eda 0x%04x, cpb 0x%02x\n", 1132 scp->sp_if.if_xname, 1133 dmac_read_2(scp, SCA_CDAL1), 1134 dmac_read_2(scp, SCA_EDAL1), 1135 dmac_read_1(scp, SCA_CPB1)); 1136 1137 /* 1138 * Yikes. Arrange for a full 1139 * transmitter restart. 1140 */ 1141 scp->sp_if.if_flags &= ~IFF_OACTIVE; 1142 scp->txcur = 0; 1143 scp->txinuse = 0; 1144 } 1145 1146 /* 1147 * check for end of transfer, which is not 1148 * an error. It means that all data queued 1149 * was transmitted, and we mark ourself as 1150 * not in use and stop the watchdog timer. 1151 */ 1152 if (dsr & SCA_DSR_EOT) { 1153 SCA_DPRINTF(SCA_DEBUG_TX, 1154 ("Transmit completed.\n")); 1155 1156 scp->sp_if.if_flags &= ~IFF_OACTIVE; 1157 scp->txcur = 0; 1158 scp->txinuse = 0; 1159 1160 /* 1161 * check for more packets 1162 */ 1163 sca_start(&scp->sp_if); 1164 } 1165 } 1166 } 1167 /* 1168 * receive channel check 1169 */ 1170 if (isr & 0x03) { 1171 SCA_DPRINTF(SCA_DEBUG_INTR, 1172 ("RX INTERRUPT port %d\n", mch)); 1173 1174 dsr = 1; 1175 while (dsr != 0) { 1176 ret++; 1177 1178 dsr = dmac_read_1(scp, SCA_DSR0); 1179 dmac_write_1(scp, SCA_DSR0, dsr | SCA_DSR_DEWD); 1180 1181 /* 1182 * filter out the bits we don't care about 1183 */ 1184 dsr &= (SCA_DSR_EOM | SCA_DSR_COF 1185 | SCA_DSR_BOF | SCA_DSR_EOT); 1186 if (dsr == 0) 1187 break; 1188 1189 /* 1190 * End of frame 1191 */ 1192 if (dsr & SCA_DSR_EOM) { 1193 SCA_DPRINTF(SCA_DEBUG_RX, ("Got a frame!\n")); 1194 1195 sca_get_packets(scp); 1196 } 1197 1198 /* 1199 * check for counter overflow 1200 */ 1201 if (dsr & SCA_DSR_COF) { 1202 printf("%s: RXDMA counter overflow\n", 1203 scp->sp_if.if_xname); 1204 1205 sca_dmac_rxinit(scp); 1206 } 1207 1208 /* 1209 * check for end of transfer, which means we 1210 * ran out of descriptors to receive into. 1211 * This means the line is much faster than 1212 * we can handle. 1213 */ 1214 if (dsr & (SCA_DSR_BOF | SCA_DSR_EOT)) { 1215 printf("%s: RXDMA buffer overflow\n", 1216 scp->sp_if.if_xname); 1217 1218 sca_dmac_rxinit(scp); 1219 } 1220 } 1221 } 1222 1223 return ret; 1224 } 1225 1226 static int 1227 sca_msci_intr(struct sca_softc *sc, u_int8_t isr) 1228 { 1229 printf("Got msci interrupt XXX\n"); 1230 1231 return 0; 1232 } 1233 1234 static void 1235 sca_get_packets(sca_port_t *scp) 1236 { 1237 int descidx; 1238 sca_desc_t *desc; 1239 u_int8_t *buf; 1240 1241 bus_dmamap_sync(scp->sca->sc_dmat, scp->sca->sc_dmam, 1242 0, scp->sca->sc_allocsize, 1243 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1244 1245 /* 1246 * Loop while there are packets to receive. After each is processed, 1247 * call sca_frame_skip() to update the DMA registers to the new 1248 * state. 1249 */ 1250 while (sca_frame_avail(scp, &descidx)) { 1251 desc = &scp->rxdesc[descidx]; 1252 buf = scp->rxbuf + SCA_BSIZE * descidx; 1253 1254 sca_frame_process(scp, desc, buf); 1255 #if SCA_DEBUG_LEVEL > 0 1256 if (sca_debug & SCA_DEBUG_RXPKT) 1257 sca_frame_print(scp, desc, buf); 1258 #endif 1259 sca_frame_skip(scp, descidx); 1260 } 1261 1262 bus_dmamap_sync(scp->sca->sc_dmat, scp->sca->sc_dmam, 1263 0, scp->sca->sc_allocsize, 1264 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1265 } 1266 1267 /* 1268 * Starting with the first descriptor we wanted to read into, up to but 1269 * not including the current SCA read descriptor, look for a packet. 1270 */ 1271 static int 1272 sca_frame_avail(sca_port_t *scp, int *descindx) 1273 { 1274 u_int16_t cda; 1275 int cdaidx; 1276 u_int32_t desc_p; /* physical address (lower 16 bits) */ 1277 sca_desc_t *desc; 1278 u_int8_t rxstat; 1279 1280 /* 1281 * Read the current descriptor from the SCA. 1282 */ 1283 cda = dmac_read_2(scp, SCA_CDAL0); 1284 1285 /* 1286 * calculate the index of the current descriptor 1287 */ 1288 desc_p = cda - (u_int16_t)(scp->rxdesc_p & 0x0000ffff); 1289 cdaidx = desc_p / sizeof(sca_desc_t); 1290 1291 if (cdaidx >= SCA_NrxBUFS) 1292 return 0; 1293 1294 for (;;) { 1295 /* 1296 * if the SCA is reading into the first descriptor, we somehow 1297 * got this interrupt incorrectly. Just return that there are 1298 * no packets ready. 1299 */ 1300 if (cdaidx == scp->rxstart) 1301 return 0; 1302 1303 /* 1304 * We might have a valid descriptor. Set up a pointer 1305 * to the kva address for it so we can more easily examine 1306 * the contents. 1307 */ 1308 desc = &scp->rxdesc[scp->rxstart]; 1309 1310 rxstat = desc->stat; 1311 1312 /* 1313 * check for errors 1314 */ 1315 if (rxstat & SCA_DESC_ERRORS) 1316 goto nextpkt; 1317 1318 /* 1319 * full packet? Good. 1320 */ 1321 if (rxstat & SCA_DESC_EOM) { 1322 *descindx = scp->rxstart; 1323 return 1; 1324 } 1325 1326 /* 1327 * increment the rxstart address, since this frame is 1328 * somehow damaged. Skip over it in later calls. 1329 * XXX This breaks multidescriptor receives, so each 1330 * frame HAS to fit within one descriptor's buffer 1331 * space now... 1332 */ 1333 nextpkt: 1334 scp->rxstart++; 1335 if (scp->rxstart == SCA_NrxBUFS) 1336 scp->rxstart = 0; 1337 } 1338 1339 return 0; 1340 } 1341 1342 /* 1343 * Pass the packet up to the kernel if it is a packet we want to pay 1344 * attention to. 1345 * 1346 * MUST BE CALLED AT splnet() 1347 */ 1348 static void 1349 sca_frame_process(sca_port_t *scp, sca_desc_t *desc, u_int8_t *p) 1350 { 1351 hdlc_header_t *hdlc; 1352 cisco_pkt_t *cisco, *ncisco; 1353 u_int16_t len; 1354 struct mbuf *m; 1355 u_int8_t *nbuf; 1356 u_int32_t t = (time.tv_sec - boottime.tv_sec) * 1000; 1357 struct ifqueue *ifq; 1358 1359 len = desc->len; 1360 1361 /* 1362 * skip packets that are too short 1363 */ 1364 if (len < sizeof(hdlc_header_t)) 1365 return; 1366 1367 #if NBPFILTER > 0 1368 if (scp->sp_bpf) 1369 bpf_tap(scp->sp_bpf, p, len); 1370 #endif 1371 1372 /* 1373 * read and then strip off the HDLC information 1374 */ 1375 hdlc = (hdlc_header_t *)p; 1376 1377 scp->sp_if.if_ipackets++; 1378 scp->sp_if.if_lastchange = time; 1379 1380 switch (ntohs(hdlc->protocol)) { 1381 case HDLC_PROTOCOL_IP: 1382 SCA_DPRINTF(SCA_DEBUG_RX, ("Received IP packet\n")); 1383 1384 m = sca_mbuf_alloc(p, len); 1385 if (m == NULL) { 1386 scp->sp_if.if_iqdrops++; 1387 return; 1388 } 1389 m->m_pkthdr.rcvif = &scp->sp_if; 1390 1391 if (IF_QFULL(&ipintrq)) { 1392 IF_DROP(&ipintrq); 1393 scp->sp_if.if_ierrors++; 1394 scp->sp_if.if_iqdrops++; 1395 m_freem(m); 1396 } else { 1397 /* 1398 * strip off the HDLC header and hand off to IP stack 1399 */ 1400 m->m_pkthdr.len -= HDLC_HDRLEN; 1401 m->m_data += HDLC_HDRLEN; 1402 m->m_len -= HDLC_HDRLEN; 1403 IF_ENQUEUE(&ipintrq, m); 1404 schednetisr(NETISR_IP); 1405 } 1406 1407 break; 1408 1409 case CISCO_KEEPALIVE: 1410 SCA_DPRINTF(SCA_DEBUG_CISCO, 1411 ("Received CISCO keepalive packet\n")); 1412 1413 if (len < CISCO_PKT_LEN) { 1414 SCA_DPRINTF(SCA_DEBUG_CISCO, 1415 ("short CISCO packet %d, wanted %d\n", 1416 len, CISCO_PKT_LEN)); 1417 return; 1418 } 1419 1420 /* 1421 * allocate an mbuf and copy the important bits of data 1422 * into it. 1423 */ 1424 m = sca_mbuf_alloc(p, HDLC_HDRLEN + CISCO_PKT_LEN); 1425 if (m == NULL) 1426 return; 1427 1428 nbuf = mtod(m, u_int8_t *); 1429 ncisco = (cisco_pkt_t *)(nbuf + HDLC_HDRLEN); 1430 m->m_pkthdr.rcvif = &scp->sp_if; 1431 1432 cisco = (cisco_pkt_t *)(p + HDLC_HDRLEN); 1433 1434 switch (ntohl(cisco->type)) { 1435 case CISCO_ADDR_REQ: 1436 printf("Got CISCO addr_req, ignoring\n"); 1437 m_freem(m); 1438 break; 1439 1440 case CISCO_ADDR_REPLY: 1441 printf("Got CISCO addr_reply, ignoring\n"); 1442 m_freem(m); 1443 break; 1444 1445 case CISCO_KEEPALIVE_REQ: 1446 SCA_DPRINTF(SCA_DEBUG_CISCO, 1447 ("Received KA, mseq %d," 1448 " yseq %d, rel 0x%04x, t0" 1449 " %04x, t1 %04x\n", 1450 ntohl(cisco->par1), ntohl(cisco->par2), 1451 ntohs(cisco->rel), ntohs(cisco->time0), 1452 ntohs(cisco->time1))); 1453 1454 scp->cka_lastrx = ntohl(cisco->par1); 1455 scp->cka_lasttx++; 1456 1457 /* 1458 * schedule the transmit right here. 1459 */ 1460 ncisco->par2 = cisco->par1; 1461 ncisco->par1 = htonl(scp->cka_lasttx); 1462 ncisco->time0 = htons((u_int16_t)(t >> 16)); 1463 ncisco->time1 = htons((u_int16_t)(t & 0x0000ffff)); 1464 1465 ifq = &scp->linkq; 1466 if (IF_QFULL(ifq)) { 1467 IF_DROP(ifq); 1468 m_freem(m); 1469 return; 1470 } 1471 IF_ENQUEUE(ifq, m); 1472 1473 sca_start(&scp->sp_if); 1474 1475 break; 1476 1477 default: 1478 m_freem(m); 1479 SCA_DPRINTF(SCA_DEBUG_CISCO, 1480 ("Unknown CISCO keepalive protocol 0x%04x\n", 1481 ntohl(cisco->type))); 1482 return; 1483 } 1484 1485 break; 1486 1487 default: 1488 SCA_DPRINTF(SCA_DEBUG_RX, 1489 ("Unknown/unexpected ethertype 0x%04x\n", 1490 ntohs(hdlc->protocol))); 1491 } 1492 } 1493 1494 #if SCA_DEBUG_LEVEL > 0 1495 /* 1496 * do a hex dump of the packet received into descriptor "desc" with 1497 * data buffer "p" 1498 */ 1499 static void 1500 sca_frame_print(sca_port_t *scp, sca_desc_t *desc, u_int8_t *p) 1501 { 1502 int i; 1503 int nothing_yet = 1; 1504 1505 printf("descriptor va %p: cp 0x%x bpb 0x%0x bp 0x%0x stat 0x%0x len %d\n", 1506 desc, desc->cp, desc->bpb, desc->bp, desc->stat, desc->len); 1507 1508 for (i = 0 ; i < desc->len ; i++) { 1509 if (nothing_yet == 1 && *p == 0) { 1510 p++; 1511 continue; 1512 } 1513 nothing_yet = 0; 1514 if (i % 16 == 0) 1515 printf("\n"); 1516 printf("%02x ", *p++); 1517 } 1518 1519 if (i % 16 != 1) 1520 printf("\n"); 1521 } 1522 #endif 1523 1524 /* 1525 * skip all frames before the descriptor index "indx" -- we do this by 1526 * moving the rxstart pointer to the index following this one, and 1527 * setting the end descriptor to this index. 1528 */ 1529 static void 1530 sca_frame_skip(sca_port_t *scp, int indx) 1531 { 1532 u_int32_t desc_p; 1533 1534 scp->rxstart++; 1535 if (scp->rxstart == SCA_NrxBUFS) 1536 scp->rxstart = 0; 1537 1538 desc_p = scp->rxdesc_p * sizeof(sca_desc_t) * indx; 1539 dmac_write_2(scp, SCA_EDAL0, 1540 (u_int16_t)(desc_p & 0x0000ffff)); 1541 } 1542 1543 /* 1544 * set a port to the "up" state 1545 */ 1546 static void 1547 sca_port_up(sca_port_t *scp) 1548 { 1549 struct sca_softc *sc = scp->sca; 1550 1551 /* 1552 * reset things 1553 */ 1554 #if 0 1555 msci_write_1(scp, SCA_CMD0, SCA_CMD_TXRESET); 1556 msci_write_1(scp, SCA_CMD0, SCA_CMD_RXRESET); 1557 #endif 1558 /* 1559 * clear in-use flag 1560 */ 1561 scp->sp_if.if_flags &= ~IFF_OACTIVE; 1562 1563 /* 1564 * raise DTR 1565 */ 1566 sc->dtr_callback(sc->dtr_aux, scp->sp_port, 1); 1567 1568 /* 1569 * raise RTS 1570 */ 1571 msci_write_1(scp, SCA_CTL0, 1572 msci_read_1(scp, SCA_CTL0) & ~SCA_CTL_RTS); 1573 1574 /* 1575 * enable interrupts 1576 */ 1577 if (scp->sp_port == 0) { 1578 sca_write_1(sc, SCA_IER0, sca_read_1(sc, SCA_IER0) | 0x0f); 1579 sca_write_1(sc, SCA_IER1, sca_read_1(sc, SCA_IER1) | 0x0f); 1580 } else { 1581 sca_write_1(sc, SCA_IER0, sca_read_1(sc, SCA_IER0) | 0xf0); 1582 sca_write_1(sc, SCA_IER1, sca_read_1(sc, SCA_IER1) | 0xf0); 1583 } 1584 1585 /* 1586 * enable transmit and receive 1587 */ 1588 msci_write_1(scp, SCA_CMD0, SCA_CMD_TXENABLE); 1589 msci_write_1(scp, SCA_CMD0, SCA_CMD_RXENABLE); 1590 1591 /* 1592 * reset internal state 1593 */ 1594 scp->txinuse = 0; 1595 scp->txcur = 0; 1596 scp->cka_lasttx = time.tv_usec; 1597 scp->cka_lastrx = 0; 1598 } 1599 1600 /* 1601 * set a port to the "down" state 1602 */ 1603 static void 1604 sca_port_down(sca_port_t *scp) 1605 { 1606 struct sca_softc *sc = scp->sca; 1607 1608 /* 1609 * lower DTR 1610 */ 1611 sc->dtr_callback(sc->dtr_aux, scp->sp_port, 0); 1612 1613 /* 1614 * lower RTS 1615 */ 1616 msci_write_1(scp, SCA_CTL0, 1617 msci_read_1(scp, SCA_CTL0) | SCA_CTL_RTS); 1618 1619 /* 1620 * disable interrupts 1621 */ 1622 if (scp->sp_port == 0) { 1623 sca_write_1(sc, SCA_IER0, sca_read_1(sc, SCA_IER0) & 0xf0); 1624 sca_write_1(sc, SCA_IER1, sca_read_1(sc, SCA_IER1) & 0xf0); 1625 } else { 1626 sca_write_1(sc, SCA_IER0, sca_read_1(sc, SCA_IER0) & 0x0f); 1627 sca_write_1(sc, SCA_IER1, sca_read_1(sc, SCA_IER1) & 0x0f); 1628 } 1629 1630 /* 1631 * disable transmit and receive 1632 */ 1633 msci_write_1(scp, SCA_CMD0, SCA_CMD_RXDISABLE); 1634 msci_write_1(scp, SCA_CMD0, SCA_CMD_TXDISABLE); 1635 1636 /* 1637 * no, we're not in use anymore 1638 */ 1639 scp->sp_if.if_flags &= ~IFF_OACTIVE; 1640 } 1641 1642 /* 1643 * disable all DMA and interrupts for all ports at once. 1644 */ 1645 void 1646 sca_shutdown(struct sca_softc *sca) 1647 { 1648 /* 1649 * disable DMA and interrupts 1650 */ 1651 sca_write_1(sca, SCA_DMER, 0); 1652 sca_write_1(sca, SCA_IER0, 0); 1653 sca_write_1(sca, SCA_IER1, 0); 1654 } 1655 1656 /* 1657 * If there are packets to transmit, start the transmit DMA logic. 1658 */ 1659 static void 1660 sca_port_starttx(sca_port_t *scp) 1661 { 1662 struct sca_softc *sc; 1663 u_int32_t startdesc_p, enddesc_p; 1664 int enddesc; 1665 1666 sc = scp->sca; 1667 1668 if (((scp->sp_if.if_flags & IFF_OACTIVE) == IFF_OACTIVE) 1669 || scp->txinuse == 0) 1670 return; 1671 scp->sp_if.if_flags |= IFF_OACTIVE; 1672 1673 /* 1674 * We have something to do, since we have at least one packet 1675 * waiting, and we are not already marked as active. 1676 */ 1677 enddesc = scp->txcur; 1678 enddesc++; 1679 if (enddesc == SCA_NtxBUFS) 1680 enddesc = 0; 1681 1682 startdesc_p = scp->txdesc_p; 1683 enddesc_p = scp->txdesc_p + sizeof(sca_desc_t) * enddesc; 1684 1685 dmac_write_2(scp, SCA_EDAL1, (u_int16_t)(enddesc_p & 0x0000ffff)); 1686 dmac_write_2(scp, SCA_CDAL1, 1687 (u_int16_t)(startdesc_p & 0x0000ffff)); 1688 1689 /* 1690 * enable the DMA 1691 */ 1692 dmac_write_1(scp, SCA_DSR1, SCA_DSR_DE); 1693 } 1694 1695 /* 1696 * allocate an mbuf at least long enough to hold "len" bytes. 1697 * If "p" is non-NULL, copy "len" bytes from it into the new mbuf, 1698 * otherwise let the caller handle copying the data in. 1699 */ 1700 static struct mbuf * 1701 sca_mbuf_alloc(caddr_t p, u_int len) 1702 { 1703 struct mbuf *m; 1704 1705 /* 1706 * allocate an mbuf and copy the important bits of data 1707 * into it. If the packet won't fit in the header, 1708 * allocate a cluster for it and store it there. 1709 */ 1710 MGETHDR(m, M_DONTWAIT, MT_DATA); 1711 if (m == NULL) 1712 return NULL; 1713 if (len > MHLEN) { 1714 if (len > MCLBYTES) { 1715 m_freem(m); 1716 return NULL; 1717 } 1718 MCLGET(m, M_DONTWAIT); 1719 if ((m->m_flags & M_EXT) == 0) { 1720 m_freem(m); 1721 return NULL; 1722 } 1723 } 1724 if (p != NULL) 1725 bcopy(p, mtod(m, caddr_t), len); 1726 m->m_len = len; 1727 m->m_pkthdr.len = len; 1728 1729 return (m); 1730 } 1731
Indexes created Fri Sep 26 20:09:58 GMT 2025