hd64570.c revision 1.9
1 /* $NetBSD: hd64570.c,v 1.9 2000/01/08 20:46:29 chopps Exp $ */ 2 3 /* 4 * Copyright (c) 1999 Christian E. Hopps 5 * Copyright (c) 1998 Vixie Enterprises 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of Vixie Enterprises nor the names 18 * of its contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY VIXIE ENTERPRISES AND 22 * CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 23 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL VIXIE ENTERPRISES OR 26 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 28 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * This software has been written for Vixie Enterprises by Michael Graff 36 * <explorer (at) flame.org>. To learn more about Vixie Enterprises, see 37 * ``http://www.vix.com''. 38 */ 39 40 /* 41 * TODO: 42 * 43 * o teach the receive logic about errors, and about long frames that 44 * span more than one input buffer. (Right now, receive/transmit is 45 * limited to one descriptor's buffer space, which is MTU + 4 bytes. 46 * This is currently 1504, which is large enough to hold the HDLC 47 * header and the packet itself. Packets which are too long are 48 * silently dropped on transmit and silently dropped on receive. 49 * o write code to handle the msci interrupts, needed only for CD 50 * and CTS changes. 51 * o consider switching back to a "queue tx with DMA active" model which 52 * should help sustain outgoing traffic 53 * o through clever use of bus_dma*() functions, it should be possible 54 * to map the mbuf's data area directly into a descriptor transmit 55 * buffer, removing the need to allocate extra memory. If, however, 56 * we run out of descriptors for this, we will need to then allocate 57 * one large mbuf, copy the fragmented chain into it, and put it onto 58 * a single descriptor. 59 * o use bus_dmamap_sync() with the right offset and lengths, rather 60 * than cheating and always sync'ing the whole region. 61 * 62 * o perhaps allow rx and tx to be in more than one page 63 * if not using dma. currently the assumption is that 64 * rx uses a page and tx uses a page. 65 */ 66 67 #include "bpfilter.h" 68 #include "opt_inet.h" 69 #include "opt_iso.h" 70 71 #include <sys/param.h> 72 #include <sys/systm.h> 73 #include <sys/device.h> 74 #include <sys/mbuf.h> 75 #include <sys/socket.h> 76 #include <sys/sockio.h> 77 #include <sys/kernel.h> 78 79 #include <net/if.h> 80 #include <net/if_types.h> 81 #include <net/netisr.h> 82 83 #ifdef INET 84 #include <netinet/in.h> 85 #include <netinet/in_systm.h> 86 #include <netinet/in_var.h> 87 #include <netinet/ip.h> 88 #endif 89 90 #ifdef ISO 91 #include <net/if_llc.h> 92 #include <netiso/iso.h> 93 #include <netiso/iso_var.h> 94 #endif 95 96 #if NBPFILTER > 0 97 #include <net/bpf.h> 98 #endif 99 100 #include <machine/cpu.h> 101 #include <machine/bus.h> 102 #include <machine/intr.h> 103 104 #include <dev/pci/pcivar.h> 105 #include <dev/pci/pcireg.h> 106 #include <dev/pci/pcidevs.h> 107 108 #include <dev/ic/hd64570reg.h> 109 #include <dev/ic/hd64570var.h> 110 111 #define SCA_DEBUG_RX 0x0001 112 #define SCA_DEBUG_TX 0x0002 113 #define SCA_DEBUG_CISCO 0x0004 114 #define SCA_DEBUG_DMA 0x0008 115 #define SCA_DEBUG_RXPKT 0x0010 116 #define SCA_DEBUG_TXPKT 0x0020 117 #define SCA_DEBUG_INTR 0x0040 118 #define SCA_DEBUG_CLOCK 0x0080 119 120 #if 0 121 #define SCA_DEBUG_LEVEL ( 0xFFFF ) 122 #else 123 #define SCA_DEBUG_LEVEL 0 124 #endif 125 126 u_int32_t sca_debug = SCA_DEBUG_LEVEL; 127 128 #if SCA_DEBUG_LEVEL > 0 129 #define SCA_DPRINTF(l, x) do { \ 130 if ((l) & sca_debug) \ 131 printf x;\ 132 } while (0) 133 #else 134 #define SCA_DPRINTF(l, x) 135 #endif 136 137 #if 0 138 #define SCA_USE_FASTQ /* use a split queue, one for fast traffic */ 139 #endif 140 141 static inline void msci_write_1(sca_port_t *, u_int, u_int8_t); 142 static inline u_int8_t msci_read_1(sca_port_t *, u_int); 143 144 static inline void dmac_write_1(sca_port_t *, u_int, u_int8_t); 145 static inline void dmac_write_2(sca_port_t *, u_int, u_int16_t); 146 static inline u_int8_t dmac_read_1(sca_port_t *, u_int); 147 static inline u_int16_t dmac_read_2(sca_port_t *, u_int); 148 149 static void sca_msci_init(struct sca_softc *, sca_port_t *); 150 static void sca_dmac_init(struct sca_softc *, sca_port_t *); 151 static void sca_dmac_rxinit(sca_port_t *); 152 153 static int sca_dmac_intr(sca_port_t *, u_int8_t); 154 static int sca_msci_intr(sca_port_t *, u_int8_t); 155 156 static void sca_get_packets(sca_port_t *); 157 static int sca_frame_avail(sca_port_t *); 158 static void sca_frame_process(sca_port_t *); 159 static void sca_frame_read_done(sca_port_t *); 160 161 static void sca_port_starttx(sca_port_t *); 162 163 static void sca_port_up(sca_port_t *); 164 static void sca_port_down(sca_port_t *); 165 166 static int sca_output __P((struct ifnet *, struct mbuf *, struct sockaddr *, 167 struct rtentry *)); 168 static int sca_ioctl __P((struct ifnet *, u_long, caddr_t)); 169 static void sca_start __P((struct ifnet *)); 170 static void sca_watchdog __P((struct ifnet *)); 171 172 static struct mbuf *sca_mbuf_alloc(struct sca_softc *, caddr_t, u_int); 173 174 #if SCA_DEBUG_LEVEL > 0 175 static void sca_frame_print(sca_port_t *, sca_desc_t *, u_int8_t *); 176 #endif 177 178 179 #define sca_read_1(sc, reg) (sc)->sc_read_1(sc, reg) 180 #define sca_read_2(sc, reg) (sc)->sc_read_2(sc, reg) 181 #define sca_write_1(sc, reg, val) (sc)->sc_write_1(sc, reg, val) 182 #define sca_write_2(sc, reg, val) (sc)->sc_write_2(sc, reg, val) 183 184 #define sca_page_addr(sc, addr) ((bus_addr_t)(addr) & (sc)->scu_pagemask) 185 186 static inline void 187 msci_write_1(sca_port_t *scp, u_int reg, u_int8_t val) 188 { 189 sca_write_1(scp->sca, scp->msci_off + reg, val); 190 } 191 192 static inline u_int8_t 193 msci_read_1(sca_port_t *scp, u_int reg) 194 { 195 return sca_read_1(scp->sca, scp->msci_off + reg); 196 } 197 198 static inline void 199 dmac_write_1(sca_port_t *scp, u_int reg, u_int8_t val) 200 { 201 sca_write_1(scp->sca, scp->dmac_off + reg, val); 202 } 203 204 static inline void 205 dmac_write_2(sca_port_t *scp, u_int reg, u_int16_t val) 206 { 207 sca_write_2(scp->sca, scp->dmac_off + reg, val); 208 } 209 210 static inline u_int8_t 211 dmac_read_1(sca_port_t *scp, u_int reg) 212 { 213 return sca_read_1(scp->sca, scp->dmac_off + reg); 214 } 215 216 static inline u_int16_t 217 dmac_read_2(sca_port_t *scp, u_int reg) 218 { 219 return sca_read_2(scp->sca, scp->dmac_off + reg); 220 } 221 222 /* 223 * read the chain pointer 224 */ 225 static inline u_int16_t 226 sca_desc_read_chainp(struct sca_softc *sc, struct sca_desc *dp) 227 { 228 if (sc->sc_usedma) 229 return ((dp)->sd_chainp); 230 return (bus_space_read_2(sc->scu_memt, sc->scu_memh, 231 sca_page_addr(sc, dp) + offsetof(struct sca_desc, sd_chainp))); 232 } 233 234 /* 235 * write the chain pointer 236 */ 237 static inline void 238 sca_desc_write_chainp(struct sca_softc *sc, struct sca_desc *dp, u_int16_t cp) 239 { 240 if (sc->sc_usedma) 241 (dp)->sd_chainp = cp; 242 else 243 bus_space_write_2(sc->scu_memt, sc->scu_memh, 244 sca_page_addr(sc, dp) 245 + offsetof(struct sca_desc, sd_chainp), cp); 246 } 247 248 /* 249 * read the buffer pointer 250 */ 251 static inline u_int32_t 252 sca_desc_read_bufp(struct sca_softc *sc, struct sca_desc *dp) 253 { 254 u_int32_t address; 255 256 if (sc->sc_usedma) 257 address = dp->sd_bufp | dp->sd_hbufp << 16; 258 else { 259 address = bus_space_read_2(sc->scu_memt, sc->scu_memh, 260 sca_page_addr(sc, dp) + offsetof(struct sca_desc, sd_bufp)); 261 address |= bus_space_read_1(sc->scu_memt, sc->scu_memh, 262 sca_page_addr(sc, dp) 263 + offsetof(struct sca_desc, sd_hbufp)) << 16; 264 } 265 return (address); 266 } 267 268 /* 269 * write the buffer pointer 270 */ 271 static inline void 272 sca_desc_write_bufp(struct sca_softc *sc, struct sca_desc *dp, u_int32_t bufp) 273 { 274 if (sc->sc_usedma) { 275 dp->sd_bufp = bufp & 0xFFFF; 276 dp->sd_hbufp = (bufp & 0x00FF0000) >> 16; 277 } else { 278 bus_space_write_2(sc->scu_memt, sc->scu_memh, 279 sca_page_addr(sc, dp) + offsetof(struct sca_desc, sd_bufp), 280 bufp & 0xFFFF); 281 bus_space_write_1(sc->scu_memt, sc->scu_memh, 282 sca_page_addr(sc, dp) + offsetof(struct sca_desc, sd_hbufp), 283 (bufp & 0x00FF0000) >> 16); 284 } 285 } 286 287 /* 288 * read the buffer length 289 */ 290 static inline u_int16_t 291 sca_desc_read_buflen(struct sca_softc *sc, struct sca_desc *dp) 292 { 293 if (sc->sc_usedma) 294 return ((dp)->sd_buflen); 295 return (bus_space_read_2(sc->scu_memt, sc->scu_memh, 296 sca_page_addr(sc, dp) + offsetof(struct sca_desc, sd_buflen))); 297 } 298 299 /* 300 * write the buffer length 301 */ 302 static inline void 303 sca_desc_write_buflen(struct sca_softc *sc, struct sca_desc *dp, u_int16_t len) 304 { 305 if (sc->sc_usedma) 306 (dp)->sd_buflen = len; 307 else 308 bus_space_write_2(sc->scu_memt, sc->scu_memh, 309 sca_page_addr(sc, dp) 310 + offsetof(struct sca_desc, sd_buflen), len); 311 } 312 313 /* 314 * read the descriptor status 315 */ 316 static inline u_int8_t 317 sca_desc_read_stat(struct sca_softc *sc, struct sca_desc *dp) 318 { 319 if (sc->sc_usedma) 320 return ((dp)->sd_stat); 321 return (bus_space_read_1(sc->scu_memt, sc->scu_memh, 322 sca_page_addr(sc, dp) + offsetof(struct sca_desc, sd_stat))); 323 } 324 325 /* 326 * write the descriptor status 327 */ 328 static inline void 329 sca_desc_write_stat(struct sca_softc *sc, struct sca_desc *dp, u_int8_t stat) 330 { 331 if (sc->sc_usedma) 332 (dp)->sd_stat = stat; 333 else 334 bus_space_write_1(sc->scu_memt, sc->scu_memh, 335 sca_page_addr(sc, dp) + offsetof(struct sca_desc, sd_stat), 336 stat); 337 } 338 339 void 340 sca_init(struct sca_softc *sc) 341 { 342 /* 343 * Do a little sanity check: check number of ports. 344 */ 345 if (sc->sc_numports < 1 || sc->sc_numports > 2) 346 panic("sca can\'t handle more than 2 or less than 1 ports"); 347 348 /* 349 * disable DMA and MSCI interrupts 350 */ 351 sca_write_1(sc, SCA_DMER, 0); 352 sca_write_1(sc, SCA_IER0, 0); 353 sca_write_1(sc, SCA_IER1, 0); 354 sca_write_1(sc, SCA_IER2, 0); 355 356 /* 357 * configure interrupt system 358 */ 359 sca_write_1(sc, SCA_ITCR, 360 SCA_ITCR_INTR_PRI_MSCI | SCA_ITCR_ACK_NONE | SCA_ITCR_VOUT_IVR); 361 #if 0 362 /* these are for the intrerrupt ack cycle which we don't use */ 363 sca_write_1(sc, SCA_IVR, 0x40); 364 sca_write_1(sc, SCA_IMVR, 0x40); 365 #endif 366 367 /* 368 * set wait control register to zero wait states 369 */ 370 sca_write_1(sc, SCA_PABR0, 0); 371 sca_write_1(sc, SCA_PABR1, 0); 372 sca_write_1(sc, SCA_WCRL, 0); 373 sca_write_1(sc, SCA_WCRM, 0); 374 sca_write_1(sc, SCA_WCRH, 0); 375 376 /* 377 * disable DMA and reset status 378 */ 379 sca_write_1(sc, SCA_PCR, SCA_PCR_PR2); 380 381 /* 382 * disable transmit DMA for all channels 383 */ 384 sca_write_1(sc, SCA_DSR0 + SCA_DMAC_OFF_0, 0); 385 sca_write_1(sc, SCA_DCR0 + SCA_DMAC_OFF_0, SCA_DCR_ABRT); 386 sca_write_1(sc, SCA_DSR1 + SCA_DMAC_OFF_0, 0); 387 sca_write_1(sc, SCA_DCR1 + SCA_DMAC_OFF_0, SCA_DCR_ABRT); 388 sca_write_1(sc, SCA_DSR0 + SCA_DMAC_OFF_1, 0); 389 sca_write_1(sc, SCA_DCR0 + SCA_DMAC_OFF_1, SCA_DCR_ABRT); 390 sca_write_1(sc, SCA_DSR1 + SCA_DMAC_OFF_1, 0); 391 sca_write_1(sc, SCA_DCR1 + SCA_DMAC_OFF_1, SCA_DCR_ABRT); 392 393 /* 394 * enable DMA based on channel enable flags for each channel 395 */ 396 sca_write_1(sc, SCA_DMER, SCA_DMER_EN); 397 398 /* 399 * Should check to see if the chip is responding, but for now 400 * assume it is. 401 */ 402 } 403 404 /* 405 * initialize the port and attach it to the networking layer 406 */ 407 void 408 sca_port_attach(struct sca_softc *sc, u_int port) 409 { 410 sca_port_t *scp = &sc->sc_ports[port]; 411 struct ifnet *ifp; 412 static u_int ntwo_unit = 0; 413 414 scp->sca = sc; /* point back to the parent */ 415 416 scp->sp_port = port; 417 418 if (port == 0) { 419 scp->msci_off = SCA_MSCI_OFF_0; 420 scp->dmac_off = SCA_DMAC_OFF_0; 421 if(sc->sc_parent != NULL) 422 ntwo_unit=sc->sc_parent->dv_unit * 2 + 0; 423 else 424 ntwo_unit = 0; /* XXX */ 425 } else { 426 scp->msci_off = SCA_MSCI_OFF_1; 427 scp->dmac_off = SCA_DMAC_OFF_1; 428 if(sc->sc_parent != NULL) 429 ntwo_unit=sc->sc_parent->dv_unit * 2 + 1; 430 else 431 ntwo_unit = 1; /* XXX */ 432 } 433 434 sca_msci_init(sc, scp); 435 sca_dmac_init(sc, scp); 436 437 /* 438 * attach to the network layer 439 */ 440 ifp = &scp->sp_if; 441 sprintf(ifp->if_xname, "ntwo%d", ntwo_unit); 442 ifp->if_softc = scp; 443 ifp->if_mtu = SCA_MTU; 444 ifp->if_flags = IFF_POINTOPOINT | IFF_MULTICAST; 445 ifp->if_type = IFT_PTPSERIAL; 446 ifp->if_hdrlen = HDLC_HDRLEN; 447 ifp->if_ioctl = sca_ioctl; 448 ifp->if_output = sca_output; 449 ifp->if_watchdog = sca_watchdog; 450 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 451 scp->linkq.ifq_maxlen = 5; /* if we exceed this we are hosed already */ 452 #ifdef SCA_USE_FASTQ 453 scp->fastq.ifq_maxlen = IFQ_MAXLEN; 454 #endif 455 if_attach(ifp); 456 457 #if NBPFILTER > 0 458 bpfattach(&scp->sp_bpf, ifp, DLT_HDLC, HDLC_HDRLEN); 459 #endif 460 461 if (sc->sc_parent == NULL) 462 printf("%s: port %d\n", ifp->if_xname, port); 463 else 464 printf("%s at %s port %d\n", 465 ifp->if_xname, sc->sc_parent->dv_xname, port); 466 467 /* 468 * reset the last seen times on the cisco keepalive protocol 469 */ 470 scp->cka_lasttx = time.tv_usec; 471 scp->cka_lastrx = 0; 472 } 473 474 #if 0 475 /* 476 * returns log2(div), sets 'tmc' for the required freq 'hz' 477 */ 478 static u_int8_t 479 sca_msci_get_baud_rate_values(u_int32_t hz, u_int8_t *tmcp) 480 { 481 u_int32_t tmc, div; 482 u_int32_t clock; 483 484 /* clock hz = (chipclock / tmc) / 2^(div); */ 485 /* 486 * TD == tmc * 2^(n) 487 * 488 * note: 489 * 1 <= TD <= 256 TD is inc of 1 490 * 2 <= TD <= 512 TD is inc of 2 491 * 4 <= TD <= 1024 TD is inc of 4 492 * ... 493 * 512 <= TD <= 256*512 TD is inc of 512 494 * 495 * so note there are overlaps. We lose prec 496 * as div increases so we wish to minize div. 497 * 498 * basically we want to do 499 * 500 * tmc = chip / hz, but have tmc <= 256 501 */ 502 503 /* assume system clock is 9.8304Mhz or 9830400hz */ 504 clock = clock = 9830400 >> 1; 505 506 /* round down */ 507 div = 0; 508 while ((tmc = clock / hz) > 256 || (tmc == 256 && (clock / tmc) > hz)) { 509 clock >>= 1; 510 div++; 511 } 512 if (clock / tmc > hz) 513 tmc++; 514 if (!tmc) 515 tmc = 1; 516 517 if (div > SCA_RXS_DIV_512) { 518 /* set to maximums */ 519 div = SCA_RXS_DIV_512; 520 tmc = 0; 521 } 522 523 *tmcp = (tmc & 0xFF); /* 0 == 256 */ 524 return (div & 0xFF); 525 } 526 #endif 527 528 /* 529 * initialize the port's MSCI 530 */ 531 static void 532 sca_msci_init(struct sca_softc *sc, sca_port_t *scp) 533 { 534 /* reset the channel */ 535 msci_write_1(scp, SCA_CMD0, SCA_CMD_RESET); 536 537 msci_write_1(scp, SCA_MD00, 538 ( SCA_MD0_CRC_1 539 | SCA_MD0_CRC_CCITT 540 | SCA_MD0_CRC_ENABLE 541 | SCA_MD0_MODE_HDLC)); 542 #if 0 543 /* immediately send receive reset so the above takes */ 544 msci_write_1(scp, SCA_CMD0, SCA_CMD_RXRESET); 545 #endif 546 547 msci_write_1(scp, SCA_MD10, SCA_MD1_NOADDRCHK); 548 msci_write_1(scp, SCA_MD20, 549 (SCA_MD2_DUPLEX | SCA_MD2_ADPLLx8 | SCA_MD2_NRZ)); 550 551 /* be safe and do it again */ 552 msci_write_1(scp, SCA_CMD0, SCA_CMD_RXRESET); 553 554 /* setup underrun and idle control, and initial RTS state */ 555 msci_write_1(scp, SCA_CTL0, 556 (SCA_CTL_IDLC_PATTERN 557 | SCA_CTL_UDRNC_AFTER_FCS 558 | SCA_CTL_RTS_LOW)); 559 560 /* reset the transmitter */ 561 msci_write_1(scp, SCA_CMD0, SCA_CMD_TXRESET); 562 563 /* 564 * set the clock sources 565 */ 566 msci_write_1(scp, SCA_RXS0, scp->sp_rxs); 567 msci_write_1(scp, SCA_TXS0, scp->sp_txs); 568 msci_write_1(scp, SCA_TMC0, scp->sp_tmc); 569 570 /* set external clock generate as requested */ 571 sc->sc_clock_callback(sc->sc_aux, scp->sp_port, scp->sp_eclock); 572 573 /* 574 * XXX don't pay attention to CTS or CD changes right now. I can't 575 * simulate one, and the transmitter will try to transmit even if 576 * CD isn't there anyway, so nothing bad SHOULD happen. 577 */ 578 #if 0 579 msci_write_1(scp, SCA_IE00, 0); 580 msci_write_1(scp, SCA_IE10, 0); /* 0x0c == CD and CTS changes only */ 581 #else 582 /* this would deliver transmitter underrun to ST1/ISR1 */ 583 msci_write_1(scp, SCA_IE10, SCA_ST1_UDRN); 584 msci_write_1(scp, SCA_IE00, SCA_ST0_TXINT); 585 #endif 586 msci_write_1(scp, SCA_IE20, 0); 587 588 msci_write_1(scp, SCA_FIE0, 0); 589 590 msci_write_1(scp, SCA_SA00, 0); 591 msci_write_1(scp, SCA_SA10, 0); 592 593 msci_write_1(scp, SCA_IDL0, 0x7e); 594 595 msci_write_1(scp, SCA_RRC0, 0x0e); 596 /* msci_write_1(scp, SCA_TRC00, 0x10); */ 597 /* 598 * the correct values here are important for avoiding underruns 599 * for any value less than or equal to TRC0 txrdy is activated 600 * which will start the dmac transfer to the fifo. 601 * for buffer size >= TRC1 + 1 txrdy is cleared which will stop dma. 602 * 603 * thus if we are using a very fast clock that empties the fifo 604 * quickly, delays in the dmac starting to fill the fifo can 605 * lead to underruns so we want a fairly full fifo to still 606 * cause the dmac to start. for cards with on board ram this 607 * has no effect on system performance. For cards that dma 608 * to/from system memory it will cause more, shorter, 609 * bus accesses rather than fewer longer ones. 610 */ 611 msci_write_1(scp, SCA_TRC00, 0x00); 612 msci_write_1(scp, SCA_TRC10, 0x1f); 613 } 614 615 /* 616 * Take the memory for the port and construct two circular linked lists of 617 * descriptors (one tx, one rx) and set the pointers in these descriptors 618 * to point to the buffer space for this port. 619 */ 620 static void 621 sca_dmac_init(struct sca_softc *sc, sca_port_t *scp) 622 { 623 sca_desc_t *desc; 624 u_int32_t desc_p; 625 u_int32_t buf_p; 626 int i; 627 628 if (sc->sc_usedma) 629 bus_dmamap_sync(sc->scu_dmat, sc->scu_dmam, 0, sc->scu_allocsize, 630 BUS_DMASYNC_PREWRITE); 631 else { 632 /* 633 * XXX assumes that all tx desc and bufs in same page 634 */ 635 sc->scu_page_on(sc); 636 sc->scu_set_page(sc, scp->sp_txdesc_p); 637 } 638 639 desc = scp->sp_txdesc; 640 desc_p = scp->sp_txdesc_p; 641 buf_p = scp->sp_txbuf_p; 642 scp->sp_txcur = 0; 643 scp->sp_txinuse = 0; 644 645 #ifdef DEBUG 646 /* make sure that we won't wrap */ 647 if ((desc_p & 0xffff0000) != 648 ((desc_p + sizeof(*desc) * scp->sp_ntxdesc) & 0xffff0000)) 649 panic("sca: tx descriptors cross architecural boundry"); 650 if ((buf_p & 0xff000000) != 651 ((buf_p + SCA_BSIZE * scp->sp_ntxdesc) & 0xff000000)) 652 panic("sca: tx buffers cross architecural boundry"); 653 #endif 654 655 for (i = 0 ; i < scp->sp_ntxdesc ; i++) { 656 /* 657 * desc_p points to the physcial address of the NEXT desc 658 */ 659 desc_p += sizeof(sca_desc_t); 660 661 sca_desc_write_chainp(sc, desc, desc_p & 0x0000ffff); 662 sca_desc_write_bufp(sc, desc, buf_p); 663 sca_desc_write_buflen(sc, desc, SCA_BSIZE); 664 sca_desc_write_stat(sc, desc, 0); 665 666 desc++; /* point to the next descriptor */ 667 buf_p += SCA_BSIZE; 668 } 669 670 /* 671 * "heal" the circular list by making the last entry point to the 672 * first. 673 */ 674 sca_desc_write_chainp(sc, desc - 1, scp->sp_txdesc_p & 0x0000ffff); 675 676 /* 677 * Now, initialize the transmit DMA logic 678 * 679 * CPB == chain pointer base address 680 */ 681 dmac_write_1(scp, SCA_DSR1, 0); 682 dmac_write_1(scp, SCA_DCR1, SCA_DCR_ABRT); 683 dmac_write_1(scp, SCA_DMR1, SCA_DMR_TMOD | SCA_DMR_NF); 684 /* XXX1 685 dmac_write_1(scp, SCA_DIR1, 686 (SCA_DIR_EOT | SCA_DIR_BOF | SCA_DIR_COF)); 687 */ 688 dmac_write_1(scp, SCA_DIR1, 689 (SCA_DIR_EOM | SCA_DIR_EOT | SCA_DIR_BOF | SCA_DIR_COF)); 690 dmac_write_1(scp, SCA_CPB1, 691 (u_int8_t)((scp->sp_txdesc_p & 0x00ff0000) >> 16)); 692 693 /* 694 * now, do the same thing for receive descriptors 695 * 696 * XXX assumes that all rx desc and bufs in same page 697 */ 698 if (!sc->sc_usedma) 699 sc->scu_set_page(sc, scp->sp_rxdesc_p); 700 701 desc = scp->sp_rxdesc; 702 desc_p = scp->sp_rxdesc_p; 703 buf_p = scp->sp_rxbuf_p; 704 705 #ifdef DEBUG 706 /* make sure that we won't wrap */ 707 if ((desc_p & 0xffff0000) != 708 ((desc_p + sizeof(*desc) * scp->sp_nrxdesc) & 0xffff0000)) 709 panic("sca: rx descriptors cross architecural boundry"); 710 if ((buf_p & 0xff000000) != 711 ((buf_p + SCA_BSIZE * scp->sp_nrxdesc) & 0xff000000)) 712 panic("sca: rx buffers cross architecural boundry"); 713 #endif 714 715 for (i = 0 ; i < scp->sp_nrxdesc; i++) { 716 /* 717 * desc_p points to the physcial address of the NEXT desc 718 */ 719 desc_p += sizeof(sca_desc_t); 720 721 sca_desc_write_chainp(sc, desc, desc_p & 0x0000ffff); 722 sca_desc_write_bufp(sc, desc, buf_p); 723 /* sca_desc_write_buflen(sc, desc, SCA_BSIZE); */ 724 sca_desc_write_buflen(sc, desc, 0); 725 sca_desc_write_stat(sc, desc, 0); 726 727 desc++; /* point to the next descriptor */ 728 buf_p += SCA_BSIZE; 729 } 730 731 /* 732 * "heal" the circular list by making the last entry point to the 733 * first. 734 */ 735 sca_desc_write_chainp(sc, desc - 1, scp->sp_rxdesc_p & 0x0000ffff); 736 737 sca_dmac_rxinit(scp); 738 739 if (sc->sc_usedma) 740 bus_dmamap_sync(sc->scu_dmat, sc->scu_dmam, 741 0, sc->scu_allocsize, BUS_DMASYNC_POSTWRITE); 742 else 743 sc->scu_page_off(sc); 744 } 745 746 /* 747 * reset and reinitialize the receive DMA logic 748 */ 749 static void 750 sca_dmac_rxinit(sca_port_t *scp) 751 { 752 /* 753 * ... and the receive DMA logic ... 754 */ 755 dmac_write_1(scp, SCA_DSR0, 0); /* disable DMA */ 756 dmac_write_1(scp, SCA_DCR0, SCA_DCR_ABRT); 757 758 dmac_write_1(scp, SCA_DMR0, SCA_DMR_TMOD | SCA_DMR_NF); 759 dmac_write_2(scp, SCA_BFLL0, SCA_BSIZE); 760 761 /* reset descriptors to initial state */ 762 scp->sp_rxstart = 0; 763 scp->sp_rxend = scp->sp_nrxdesc - 1; 764 765 /* 766 * CPB == chain pointer base 767 * CDA == current descriptor address 768 * EDA == error descriptor address (overwrite position) 769 * because cda can't be eda when starting we always 770 * have a single buffer gap between cda and eda 771 */ 772 dmac_write_1(scp, SCA_CPB0, 773 (u_int8_t)((scp->sp_rxdesc_p & 0x00ff0000) >> 16)); 774 dmac_write_2(scp, SCA_CDAL0, (u_int16_t)(scp->sp_rxdesc_p & 0xffff)); 775 dmac_write_2(scp, SCA_EDAL0, (u_int16_t) 776 (scp->sp_rxdesc_p + (sizeof(sca_desc_t) * scp->sp_rxend))); 777 778 /* 779 * enable receiver DMA 780 */ 781 dmac_write_1(scp, SCA_DIR0, 782 (SCA_DIR_EOT | SCA_DIR_EOM | SCA_DIR_BOF | SCA_DIR_COF)); 783 dmac_write_1(scp, SCA_DSR0, SCA_DSR_DE); 784 } 785 786 /* 787 * Queue the packet for our start routine to transmit 788 */ 789 static int 790 sca_output(ifp, m, dst, rt0) 791 struct ifnet *ifp; 792 struct mbuf *m; 793 struct sockaddr *dst; 794 struct rtentry *rt0; 795 { 796 struct hdlc_llc_header *llc; 797 struct hdlc_header *hdlc; 798 struct ifqueue *ifq; 799 int s, error; 800 801 error = 0; 802 ifp->if_lastchange = time; 803 804 if ((ifp->if_flags & IFF_UP) != IFF_UP) { 805 error = ENETDOWN; 806 goto bad; 807 } 808 809 ifq = &ifp->if_snd; 810 811 /* 812 * determine address family, and priority for this packet 813 */ 814 switch (dst->sa_family) { 815 #ifdef INET 816 case AF_INET: 817 #ifdef SCA_USE_FASTQ 818 if ((mtod(m, struct ip *)->ip_tos & IPTOS_LOWDELAY) 819 == IPTOS_LOWDELAY) 820 ifq = &((sca_port_t *)ifp->if_softc)->fastq; 821 #endif 822 /* 823 * Add cisco serial line header. If there is no 824 * space in the first mbuf, allocate another. 825 */ 826 M_PREPEND(m, sizeof(struct hdlc_header), M_DONTWAIT); 827 if (m == 0) 828 return (ENOBUFS); 829 hdlc = mtod(m, struct hdlc_header *); 830 hdlc->h_proto = htons(HDLC_PROTOCOL_IP); 831 break; 832 #endif 833 #ifdef ISO 834 case AF_ISO: 835 /* 836 * Add cisco llc serial line header. If there is no 837 * space in the first mbuf, allocate another. 838 */ 839 M_PREPEND(m, sizeof(struct hdlc_llc_header), M_DONTWAIT); 840 if (m == 0) 841 return (ENOBUFS); 842 hdlc = mtod(m, struct hdlc_header *); 843 llc = mtod(m, struct hdlc_llc_header *); 844 llc->hl_dsap = llc->hl_ssap = LLC_ISO_LSAP; 845 llc->hl_control = 0; /* XXX */ 846 break; 847 #endif 848 default: 849 printf("%s: address family %d unsupported\n", 850 ifp->if_xname, dst->sa_family); 851 error = EAFNOSUPPORT; 852 goto bad; 853 } 854 855 /* finish */ 856 if ((m->m_flags & (M_BCAST | M_MCAST)) != 0) 857 hdlc->h_addr = CISCO_MULTICAST; 858 else 859 hdlc->h_addr = CISCO_UNICAST; 860 hdlc->h_resv = 0; 861 862 /* 863 * queue the packet. If interactive, use the fast queue. 864 */ 865 s = splnet(); 866 if (IF_QFULL(ifq)) { 867 IF_DROP(ifq); 868 ifp->if_oerrors++; 869 ifp->if_collisions++; 870 error = ENOBUFS; 871 splx(s); 872 goto bad; 873 } 874 ifp->if_obytes += m->m_pkthdr.len; 875 IF_ENQUEUE(ifq, m); 876 877 ifp->if_lastchange = time; 878 879 if (m->m_flags & M_MCAST) 880 ifp->if_omcasts++; 881 882 sca_start(ifp); 883 splx(s); 884 885 return (error); 886 887 bad: 888 if (m) 889 m_freem(m); 890 return (error); 891 } 892 893 static int 894 sca_ioctl(ifp, cmd, addr) 895 struct ifnet *ifp; 896 u_long cmd; 897 caddr_t addr; 898 { 899 struct ifreq *ifr; 900 struct ifaddr *ifa; 901 int error; 902 int s; 903 904 s = splnet(); 905 906 ifr = (struct ifreq *)addr; 907 ifa = (struct ifaddr *)addr; 908 error = 0; 909 910 switch (cmd) { 911 case SIOCSIFADDR: 912 #ifdef INET 913 if (ifa->ifa_addr->sa_family == AF_INET) { 914 ifp->if_flags |= IFF_UP; 915 sca_port_up(ifp->if_softc); 916 } else 917 #endif 918 error = EAFNOSUPPORT; 919 break; 920 921 case SIOCSIFDSTADDR: 922 #ifdef INET 923 if (ifa->ifa_addr->sa_family != AF_INET) 924 error = EAFNOSUPPORT; 925 #else 926 error = EAFNOSUPPORT; 927 #endif 928 break; 929 930 case SIOCADDMULTI: 931 case SIOCDELMULTI: 932 if (ifr == 0) { 933 error = EAFNOSUPPORT; /* XXX */ 934 break; 935 } 936 switch (ifr->ifr_addr.sa_family) { 937 #ifdef INET 938 case AF_INET: 939 break; 940 #endif 941 default: 942 error = EAFNOSUPPORT; 943 break; 944 } 945 break; 946 947 case SIOCSIFFLAGS: 948 if (ifr->ifr_flags & IFF_UP) { 949 ifp->if_flags |= IFF_UP; 950 sca_port_up(ifp->if_softc); 951 } else { 952 ifp->if_flags &= ~IFF_UP; 953 sca_port_down(ifp->if_softc); 954 } 955 956 break; 957 958 default: 959 error = EINVAL; 960 } 961 962 splx(s); 963 return error; 964 } 965 966 /* 967 * start packet transmission on the interface 968 * 969 * MUST BE CALLED AT splnet() 970 */ 971 static void 972 sca_start(ifp) 973 struct ifnet *ifp; 974 { 975 sca_port_t *scp = ifp->if_softc; 976 struct sca_softc *sc = scp->sca; 977 struct mbuf *m, *mb_head; 978 sca_desc_t *desc; 979 u_int8_t *buf, stat; 980 u_int32_t buf_p; 981 int nexttx; 982 int trigger_xmit; 983 u_int len; 984 985 SCA_DPRINTF(SCA_DEBUG_TX, ("TX: enter start\n")); 986 987 /* 988 * can't queue when we are full or transmitter is busy 989 */ 990 #ifdef oldcode 991 if ((scp->sp_txinuse >= (scp->sp_ntxdesc - 1)) 992 || ((ifp->if_flags & IFF_OACTIVE) == IFF_OACTIVE)) 993 return; 994 #else 995 if (scp->sp_txinuse 996 || ((ifp->if_flags & IFF_OACTIVE) == IFF_OACTIVE)) 997 return; 998 #endif 999 SCA_DPRINTF(SCA_DEBUG_TX, ("TX: txinuse %d\n", scp->sp_txinuse)); 1000 1001 /* 1002 * XXX assume that all tx desc and bufs in same page 1003 */ 1004 if (sc->sc_usedma) 1005 bus_dmamap_sync(sc->scu_dmat, sc->scu_dmam, 1006 0, sc->scu_allocsize, 1007 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1008 else { 1009 sc->scu_page_on(sc); 1010 sc->scu_set_page(sc, scp->sp_txdesc_p); 1011 } 1012 1013 trigger_xmit = 0; 1014 1015 txloop: 1016 IF_DEQUEUE(&scp->linkq, mb_head); 1017 if (mb_head == NULL) 1018 #ifdef SCA_USE_FASTQ 1019 IF_DEQUEUE(&scp->fastq, mb_head); 1020 if (mb_head == NULL) 1021 #endif 1022 IF_DEQUEUE(&ifp->if_snd, mb_head); 1023 if (mb_head == NULL) 1024 goto start_xmit; 1025 1026 SCA_DPRINTF(SCA_DEBUG_TX, ("TX: got mbuf\n")); 1027 #ifdef oldcode 1028 if (scp->txinuse != 0) { 1029 /* Kill EOT interrupts on the previous descriptor. */ 1030 desc = &scp->sp_txdesc[scp->txcur]; 1031 stat = sca_desc_read_stat(sc, desc); 1032 sca_desc_write_stat(sc, desc, stat & ~SCA_DESC_EOT); 1033 1034 /* Figure out what the next free descriptor is. */ 1035 nexttx = (scp->sp_txcur + 1) % scp->sp_ntxdesc; 1036 } else 1037 nexttx = 0; 1038 #endif /* oldcode */ 1039 1040 if (scp->sp_txinuse) 1041 nexttx = (scp->sp_txcur + 1) % scp->sp_ntxdesc; 1042 else 1043 nexttx = 0; 1044 1045 SCA_DPRINTF(SCA_DEBUG_TX, ("TX: nexttx %d\n", nexttx)); 1046 1047 buf = scp->sp_txbuf + SCA_BSIZE * nexttx; 1048 buf_p = scp->sp_txbuf_p + SCA_BSIZE * nexttx; 1049 1050 /* XXX hoping we can delay the desc write till after we don't drop. */ 1051 desc = &scp->sp_txdesc[nexttx]; 1052 1053 /* XXX isn't this set already?? */ 1054 sca_desc_write_bufp(sc, desc, buf_p); 1055 len = 0; 1056 1057 SCA_DPRINTF(SCA_DEBUG_TX, ("TX: buf %x buf_p %x\n", (u_int)buf, buf_p)); 1058 1059 #if 0 /* uncomment this for a core in cc1 */ 1060 X 1061 #endif 1062 /* 1063 * Run through the chain, copying data into the descriptor as we 1064 * go. If it won't fit in one transmission block, drop the packet. 1065 * No, this isn't nice, but most of the time it _will_ fit. 1066 */ 1067 for (m = mb_head ; m != NULL ; m = m->m_next) { 1068 if (m->m_len != 0) { 1069 len += m->m_len; 1070 if (len > SCA_BSIZE) { 1071 m_freem(mb_head); 1072 goto txloop; 1073 } 1074 SCA_DPRINTF(SCA_DEBUG_TX, 1075 ("TX: about to mbuf len %d\n", m->m_len)); 1076 1077 if (sc->sc_usedma) 1078 bcopy(mtod(m, u_int8_t *), buf, m->m_len); 1079 else 1080 bus_space_write_region_1(sc->scu_memt, 1081 sc->scu_memh, sca_page_addr(sc, buf_p), 1082 mtod(m, u_int8_t *), m->m_len); 1083 buf += m->m_len; 1084 buf_p += m->m_len; 1085 } 1086 } 1087 1088 /* set the buffer, the length, and mark end of frame and end of xfer */ 1089 sca_desc_write_buflen(sc, desc, len); 1090 sca_desc_write_stat(sc, desc, SCA_DESC_EOM); 1091 1092 ifp->if_opackets++; 1093 1094 #if NBPFILTER > 0 1095 /* 1096 * Pass packet to bpf if there is a listener. 1097 */ 1098 if (scp->sp_bpf) 1099 bpf_mtap(scp->sp_bpf, mb_head); 1100 #endif 1101 1102 m_freem(mb_head); 1103 1104 scp->sp_txcur = nexttx; 1105 scp->sp_txinuse++; 1106 trigger_xmit = 1; 1107 1108 SCA_DPRINTF(SCA_DEBUG_TX, 1109 ("TX: inuse %d index %d\n", scp->sp_txinuse, scp->sp_txcur)); 1110 1111 /* 1112 * XXX so didn't this used to limit us to 1?! - multi may be untested 1113 * sp_ntxdesc used to be hard coded to 2 with claim of a too hard 1114 * to find bug 1115 */ 1116 #ifdef oldcode 1117 if (scp->sp_txinuse < (scp->sp_ntxdesc - 1)) 1118 #endif 1119 if (scp->sp_txinuse < scp->sp_ntxdesc) 1120 goto txloop; 1121 1122 start_xmit: 1123 SCA_DPRINTF(SCA_DEBUG_TX, ("TX: trigger_xmit %d\n", trigger_xmit)); 1124 1125 if (trigger_xmit != 0) { 1126 /* set EOT on final descriptor */ 1127 desc = &scp->sp_txdesc[scp->sp_txcur]; 1128 stat = sca_desc_read_stat(sc, desc); 1129 sca_desc_write_stat(sc, desc, stat | SCA_DESC_EOT); 1130 } 1131 1132 if (sc->sc_usedma) 1133 bus_dmamap_sync(sc->scu_dmat, sc->scu_dmam, 0, 1134 sc->scu_allocsize, 1135 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1136 1137 if (trigger_xmit != 0) 1138 sca_port_starttx(scp); 1139 1140 if (!sc->sc_usedma) 1141 sc->scu_page_off(sc); 1142 } 1143 1144 static void 1145 sca_watchdog(ifp) 1146 struct ifnet *ifp; 1147 { 1148 } 1149 1150 int 1151 sca_hardintr(struct sca_softc *sc) 1152 { 1153 u_int8_t isr0, isr1, isr2; 1154 int ret; 1155 1156 ret = 0; /* non-zero means we processed at least one interrupt */ 1157 1158 SCA_DPRINTF(SCA_DEBUG_INTR, ("sca_hardintr entered\n")); 1159 1160 while (1) { 1161 /* 1162 * read SCA interrupts 1163 */ 1164 isr0 = sca_read_1(sc, SCA_ISR0); 1165 isr1 = sca_read_1(sc, SCA_ISR1); 1166 isr2 = sca_read_1(sc, SCA_ISR2); 1167 1168 if (isr0 == 0 && isr1 == 0 && isr2 == 0) 1169 break; 1170 1171 SCA_DPRINTF(SCA_DEBUG_INTR, 1172 ("isr0 = %02x, isr1 = %02x, isr2 = %02x\n", 1173 isr0, isr1, isr2)); 1174 1175 /* 1176 * check DMAC interrupt 1177 */ 1178 if (isr1 & 0x0f) 1179 ret += sca_dmac_intr(&sc->sc_ports[0], 1180 isr1 & 0x0f); 1181 1182 if (isr1 & 0xf0) 1183 ret += sca_dmac_intr(&sc->sc_ports[1], 1184 (isr1 & 0xf0) >> 4); 1185 1186 /* 1187 * mcsi intterupts 1188 */ 1189 if (isr0 & 0x0f) 1190 ret += sca_msci_intr(&sc->sc_ports[0], isr0 & 0x0f); 1191 1192 if (isr0 & 0xf0) 1193 ret += sca_msci_intr(&sc->sc_ports[1], 1194 (isr0 & 0xf0) >> 4); 1195 1196 #if 0 /* We don't GET timer interrupts, we have them disabled (msci IE20) */ 1197 if (isr2) 1198 ret += sca_timer_intr(sc, isr2); 1199 #endif 1200 } 1201 1202 return (ret); 1203 } 1204 1205 static int 1206 sca_dmac_intr(sca_port_t *scp, u_int8_t isr) 1207 { 1208 u_int8_t dsr; 1209 int ret; 1210 1211 ret = 0; 1212 1213 /* 1214 * Check transmit channel 1215 */ 1216 if (isr & (SCA_ISR1_DMAC_TX0A | SCA_ISR1_DMAC_TX0B)) { 1217 SCA_DPRINTF(SCA_DEBUG_INTR, 1218 ("TX INTERRUPT port %d\n", scp->sp_port)); 1219 1220 dsr = 1; 1221 while (dsr != 0) { 1222 ret++; 1223 /* 1224 * reset interrupt 1225 */ 1226 dsr = dmac_read_1(scp, SCA_DSR1); 1227 dmac_write_1(scp, SCA_DSR1, 1228 dsr | SCA_DSR_DEWD); 1229 1230 /* 1231 * filter out the bits we don't care about 1232 */ 1233 dsr &= ( SCA_DSR_COF | SCA_DSR_BOF | SCA_DSR_EOT); 1234 if (dsr == 0) 1235 break; 1236 1237 /* 1238 * check for counter overflow 1239 */ 1240 if (dsr & SCA_DSR_COF) { 1241 printf("%s: TXDMA counter overflow\n", 1242 scp->sp_if.if_xname); 1243 1244 scp->sp_if.if_flags &= ~IFF_OACTIVE; 1245 scp->sp_txcur = 0; 1246 scp->sp_txinuse = 0; 1247 } 1248 1249 /* 1250 * check for buffer overflow 1251 */ 1252 if (dsr & SCA_DSR_BOF) { 1253 printf("%s: TXDMA buffer overflow, cda 0x%04x, eda 0x%04x, cpb 0x%02x\n", 1254 scp->sp_if.if_xname, 1255 dmac_read_2(scp, SCA_CDAL1), 1256 dmac_read_2(scp, SCA_EDAL1), 1257 dmac_read_1(scp, SCA_CPB1)); 1258 1259 /* 1260 * Yikes. Arrange for a full 1261 * transmitter restart. 1262 */ 1263 scp->sp_if.if_flags &= ~IFF_OACTIVE; 1264 scp->sp_txcur = 0; 1265 scp->sp_txinuse = 0; 1266 } 1267 1268 /* 1269 * check for end of transfer, which is not 1270 * an error. It means that all data queued 1271 * was transmitted, and we mark ourself as 1272 * not in use and stop the watchdog timer. 1273 */ 1274 if (dsr & SCA_DSR_EOT) { 1275 SCA_DPRINTF(SCA_DEBUG_TX, 1276 ("Transmit completed. cda %x eda %x dsr %x\n", 1277 dmac_read_2(scp, SCA_CDAL1), 1278 dmac_read_2(scp, SCA_EDAL1), 1279 dsr)); 1280 1281 scp->sp_if.if_flags &= ~IFF_OACTIVE; 1282 scp->sp_txcur = 0; 1283 scp->sp_txinuse = 0; 1284 1285 /* 1286 * check for more packets 1287 */ 1288 sca_start(&scp->sp_if); 1289 } 1290 } 1291 } 1292 /* 1293 * receive channel check 1294 */ 1295 if (isr & (SCA_ISR1_DMAC_RX0A | SCA_ISR1_DMAC_RX0B)) { 1296 SCA_DPRINTF(SCA_DEBUG_INTR, ("RX INTERRUPT port %d\n", 1297 (scp == &scp->sca->sc_ports[0] ? 0 : 1))); 1298 1299 dsr = 1; 1300 while (dsr != 0) { 1301 ret++; 1302 1303 dsr = dmac_read_1(scp, SCA_DSR0); 1304 dmac_write_1(scp, SCA_DSR0, dsr | SCA_DSR_DEWD); 1305 1306 /* 1307 * filter out the bits we don't care about 1308 */ 1309 dsr &= (SCA_DSR_EOM | SCA_DSR_COF 1310 | SCA_DSR_BOF | SCA_DSR_EOT); 1311 if (dsr == 0) 1312 break; 1313 1314 /* 1315 * End of frame 1316 */ 1317 if (dsr & SCA_DSR_EOM) { 1318 SCA_DPRINTF(SCA_DEBUG_RX, ("Got a frame!\n")); 1319 1320 sca_get_packets(scp); 1321 } 1322 1323 /* 1324 * check for counter overflow 1325 */ 1326 if (dsr & SCA_DSR_COF) { 1327 printf("%s: RXDMA counter overflow\n", 1328 scp->sp_if.if_xname); 1329 1330 sca_dmac_rxinit(scp); 1331 } 1332 1333 /* 1334 * check for end of transfer, which means we 1335 * ran out of descriptors to receive into. 1336 * This means the line is much faster than 1337 * we can handle. 1338 */ 1339 if (dsr & (SCA_DSR_BOF | SCA_DSR_EOT)) { 1340 printf("%s: RXDMA buffer overflow\n", 1341 scp->sp_if.if_xname); 1342 1343 sca_dmac_rxinit(scp); 1344 } 1345 } 1346 } 1347 1348 return ret; 1349 } 1350 1351 static int 1352 sca_msci_intr(sca_port_t *scp, u_int8_t isr) 1353 { 1354 u_int8_t st1, trc0; 1355 1356 /* get and clear the specific interrupt -- should act on it :)*/ 1357 if ((st1 = msci_read_1(scp, SCA_ST10))) { 1358 /* clear the interrupt */ 1359 msci_write_1(scp, SCA_ST10, st1); 1360 1361 if (st1 & SCA_ST1_UDRN) { 1362 /* underrun -- try to increase ready control */ 1363 trc0 = msci_read_1(scp, SCA_TRC00); 1364 if (trc0 == 0x1f) 1365 printf("TX: underun - fifo depth maxed\n"); 1366 else { 1367 if ((trc0 += 2) > 0x1f) 1368 trc0 = 0x1f; 1369 SCA_DPRINTF(SCA_DEBUG_TX, 1370 ("TX: udrn - incr fifo to %d\n", trc0)); 1371 msci_write_1(scp, SCA_TRC00, trc0); 1372 } 1373 } 1374 } 1375 return (0); 1376 } 1377 1378 static void 1379 sca_get_packets(sca_port_t *scp) 1380 { 1381 struct sca_softc *sc; 1382 1383 SCA_DPRINTF(SCA_DEBUG_RX, ("RX: sca_get_packets\n")); 1384 1385 sc = scp->sca; 1386 if (sc->sc_usedma) 1387 bus_dmamap_sync(sc->scu_dmat, sc->scu_dmam, 1388 0, sc->scu_allocsize, 1389 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1390 else { 1391 /* 1392 * XXX this code is unable to deal with rx stuff 1393 * in more than 1 page 1394 */ 1395 sc->scu_page_on(sc); 1396 sc->scu_set_page(sc, scp->sp_rxdesc_p); 1397 } 1398 1399 /* process as many frames as are available */ 1400 while (sca_frame_avail(scp)) { 1401 sca_frame_process(scp); 1402 sca_frame_read_done(scp); 1403 } 1404 1405 if (sc->sc_usedma) 1406 bus_dmamap_sync(sc->scu_dmat, sc->scu_dmam, 1407 0, sc->scu_allocsize, 1408 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1409 else 1410 sc->scu_page_off(sc); 1411 } 1412 1413 /* 1414 * Starting with the first descriptor we wanted to read into, up to but 1415 * not including the current SCA read descriptor, look for a packet. 1416 * 1417 * must be called at splnet() 1418 */ 1419 static int 1420 sca_frame_avail(sca_port_t *scp) 1421 { 1422 struct sca_softc *sc; 1423 u_int16_t cda; 1424 u_int32_t desc_p; /* physical address (lower 16 bits) */ 1425 sca_desc_t *desc; 1426 u_int8_t rxstat; 1427 int cdaidx, toolong; 1428 1429 /* 1430 * Read the current descriptor from the SCA. 1431 */ 1432 sc = scp->sca; 1433 cda = dmac_read_2(scp, SCA_CDAL0); 1434 1435 /* 1436 * calculate the index of the current descriptor 1437 */ 1438 desc_p = (scp->sp_rxdesc_p & 0xFFFF); 1439 desc_p = cda - desc_p; 1440 cdaidx = desc_p / sizeof(sca_desc_t); 1441 1442 SCA_DPRINTF(SCA_DEBUG_RX, 1443 ("RX: cda %x desc_p %x cdaidx %u, nrxdesc %d rxstart %d\n", 1444 cda, desc_p, cdaidx, scp->sp_nrxdesc, scp->sp_rxstart)); 1445 1446 /* note confusion */ 1447 if (cdaidx >= scp->sp_nrxdesc) 1448 panic("current descriptor index out of range"); 1449 1450 /* see if we have a valid frame available */ 1451 toolong = 0; 1452 for (; scp->sp_rxstart != cdaidx; sca_frame_read_done(scp)) { 1453 /* 1454 * We might have a valid descriptor. Set up a pointer 1455 * to the kva address for it so we can more easily examine 1456 * the contents. 1457 */ 1458 desc = &scp->sp_rxdesc[scp->sp_rxstart]; 1459 rxstat = sca_desc_read_stat(scp->sca, desc); 1460 1461 SCA_DPRINTF(SCA_DEBUG_RX, ("port %d RX: idx %d rxstat %x\n", 1462 scp->sp_port, scp->sp_rxstart, rxstat)); 1463 1464 SCA_DPRINTF(SCA_DEBUG_RX, ("port %d RX: buflen %d\n", 1465 scp->sp_port, sca_desc_read_buflen(scp->sca, desc))); 1466 1467 /* 1468 * check for errors 1469 */ 1470 if (rxstat & SCA_DESC_ERRORS) { 1471 /* 1472 * consider an error condition the end 1473 * of a frame 1474 */ 1475 scp->sp_if.if_ierrors++; 1476 toolong = 0; 1477 continue; 1478 } 1479 1480 /* 1481 * if we aren't skipping overlong frames 1482 * we are done, otherwise reset and look for 1483 * another good frame 1484 */ 1485 if (rxstat & SCA_DESC_EOM) { 1486 if (!toolong) 1487 return (1); 1488 toolong = 0; 1489 } else if (!toolong) { 1490 /* 1491 * we currently don't deal with frames 1492 * larger than a single buffer (fixed MTU) 1493 */ 1494 scp->sp_if.if_ierrors++; 1495 toolong = 1; 1496 } 1497 SCA_DPRINTF(SCA_DEBUG_RX, ("RX: idx %d no EOM\n", 1498 scp->sp_rxstart)); 1499 } 1500 1501 SCA_DPRINTF(SCA_DEBUG_RX, ("RX: returning none\n")); 1502 return 0; 1503 } 1504 1505 /* 1506 * Pass the packet up to the kernel if it is a packet we want to pay 1507 * attention to. 1508 * 1509 * MUST BE CALLED AT splnet() 1510 */ 1511 static void 1512 sca_frame_process(sca_port_t *scp) 1513 { 1514 struct ifqueue *ifq; 1515 struct hdlc_header *hdlc; 1516 struct hdlc_llc_header *llc; 1517 struct cisco_pkt *cisco; 1518 sca_desc_t *desc; 1519 struct mbuf *m; 1520 u_int8_t *bufp; 1521 u_int16_t len; 1522 u_int32_t t; 1523 1524 t = (time.tv_sec - boottime.tv_sec) * 1000; 1525 desc = &scp->sp_rxdesc[scp->sp_rxstart]; 1526 bufp = scp->sp_rxbuf + SCA_BSIZE * scp->sp_rxstart; 1527 len = sca_desc_read_buflen(scp->sca, desc); 1528 1529 SCA_DPRINTF(SCA_DEBUG_RX, 1530 ("RX: desc %lx bufp %lx len %d\n", (bus_addr_t)desc, 1531 (bus_addr_t)bufp, len)); 1532 1533 #if SCA_DEBUG_LEVEL > 0 1534 if (sca_debug & SCA_DEBUG_RXPKT) 1535 sca_frame_print(scp, desc, bufp); 1536 #endif 1537 /* 1538 * skip packets that are too short 1539 */ 1540 if (len < sizeof(struct hdlc_header)) { 1541 scp->sp_if.if_ierrors++; 1542 return; 1543 } 1544 1545 m = sca_mbuf_alloc(scp->sca, bufp, len); 1546 if (m == NULL) { 1547 SCA_DPRINTF(SCA_DEBUG_RX, ("RX: no mbuf!\n")); 1548 return; 1549 } 1550 1551 /* 1552 * read and then strip off the HDLC information 1553 */ 1554 m = m_pullup(m, sizeof(struct hdlc_header)); 1555 if (m == NULL) { 1556 SCA_DPRINTF(SCA_DEBUG_RX, ("RX: no m_pullup!\n")); 1557 return; 1558 } 1559 1560 #if NBPFILTER > 0 1561 if (scp->sp_bpf) 1562 bpf_mtap(scp->sp_bpf, m); 1563 #endif 1564 1565 scp->sp_if.if_ipackets++; 1566 scp->sp_if.if_lastchange = time; 1567 1568 hdlc = mtod(m, struct hdlc_header *); 1569 switch (ntohs(hdlc->h_proto)) { 1570 #ifdef INET 1571 case HDLC_PROTOCOL_IP: 1572 SCA_DPRINTF(SCA_DEBUG_RX, ("Received IP packet\n")); 1573 m->m_pkthdr.rcvif = &scp->sp_if; 1574 m->m_pkthdr.len -= sizeof(struct hdlc_header); 1575 m->m_data += sizeof(struct hdlc_header); 1576 m->m_len -= sizeof(struct hdlc_header); 1577 ifq = &ipintrq; 1578 schednetisr(NETISR_IP); 1579 break; 1580 #endif /* INET */ 1581 #ifdef ISO 1582 case HDLC_PROTOCOL_ISO: 1583 if (m->m_pkthdr.len < sizeof(struct hdlc_llc_header)) 1584 goto dropit; 1585 /* if not a std iso pdu drop it */ 1586 llc = (struct hdlc_llc_header *)hdlc; 1587 #if 0 1588 /* XXX cisco puts either 0 or the iso irpd here */ 1589 if (llc->hl_control != LLC_UI) { 1590 scp->sp_if.if_noproto++; 1591 goto dropit; 1592 } 1593 #endif 1594 m->m_pkthdr.rcvif = &scp->sp_if; 1595 m->m_pkthdr.len -= sizeof(struct hdlc_llc_header); 1596 m->m_data += sizeof(struct hdlc_llc_header); 1597 m->m_len -= sizeof(struct hdlc_llc_header); 1598 ifq = &clnlintrq; 1599 schednetisr(NETISR_ISO); 1600 break; 1601 #endif /* ISO */ 1602 case CISCO_KEEPALIVE: 1603 SCA_DPRINTF(SCA_DEBUG_CISCO, 1604 ("Received CISCO keepalive packet\n")); 1605 1606 if (len < CISCO_PKT_LEN) { 1607 SCA_DPRINTF(SCA_DEBUG_CISCO, 1608 ("short CISCO packet %d, wanted %d\n", 1609 len, CISCO_PKT_LEN)); 1610 scp->sp_if.if_ierrors++; 1611 goto dropit; 1612 } 1613 1614 m = m_pullup(m, sizeof(struct cisco_pkt)); 1615 if (m == NULL) { 1616 SCA_DPRINTF(SCA_DEBUG_RX, ("RX: no m_pullup!\n")); 1617 return; 1618 } 1619 1620 cisco = (struct cisco_pkt *) 1621 (mtod(m, u_int8_t *) + HDLC_HDRLEN); 1622 m->m_pkthdr.rcvif = &scp->sp_if; 1623 1624 switch (ntohl(cisco->type)) { 1625 case CISCO_ADDR_REQ: 1626 printf("Got CISCO addr_req, ignoring\n"); 1627 scp->sp_if.if_ierrors++; 1628 goto dropit; 1629 1630 case CISCO_ADDR_REPLY: 1631 printf("Got CISCO addr_reply, ignoring\n"); 1632 scp->sp_if.if_ierrors++; 1633 goto dropit; 1634 1635 case CISCO_KEEPALIVE_REQ: 1636 1637 SCA_DPRINTF(SCA_DEBUG_CISCO, 1638 ("Received KA, mseq %d," 1639 " yseq %d, rel 0x%04x, t0" 1640 " %04x, t1 %04x\n", 1641 ntohl(cisco->par1), ntohl(cisco->par2), 1642 ntohs(cisco->rel), ntohs(cisco->time0), 1643 ntohs(cisco->time1))); 1644 1645 scp->cka_lastrx = ntohl(cisco->par1); 1646 scp->cka_lasttx++; 1647 1648 /* 1649 * schedule the transmit right here. 1650 */ 1651 cisco->par2 = cisco->par1; 1652 cisco->par1 = htonl(scp->cka_lasttx); 1653 cisco->time0 = htons((u_int16_t)(t >> 16)); 1654 cisco->time1 = htons((u_int16_t)(t & 0x0000ffff)); 1655 1656 ifq = &scp->linkq; 1657 if (IF_QFULL(ifq)) { 1658 IF_DROP(ifq); 1659 goto dropit; 1660 } 1661 IF_ENQUEUE(ifq, m); 1662 1663 sca_start(&scp->sp_if); 1664 1665 /* since start may have reset this fix */ 1666 if (!scp->sca->sc_usedma) { 1667 scp->sca->scu_set_page(scp->sca, 1668 scp->sp_rxdesc_p); 1669 scp->sca->scu_page_on(scp->sca); 1670 } 1671 return; 1672 default: 1673 SCA_DPRINTF(SCA_DEBUG_CISCO, 1674 ("Unknown CISCO keepalive protocol 0x%04x\n", 1675 ntohl(cisco->type))); 1676 1677 scp->sp_if.if_noproto++; 1678 goto dropit; 1679 } 1680 return; 1681 default: 1682 SCA_DPRINTF(SCA_DEBUG_RX, 1683 ("Unknown/unexpected ethertype 0x%04x\n", 1684 ntohs(hdlc->h_proto))); 1685 scp->sp_if.if_noproto++; 1686 goto dropit; 1687 } 1688 1689 /* queue the packet */ 1690 if (!IF_QFULL(ifq)) { 1691 IF_ENQUEUE(ifq, m); 1692 } else { 1693 IF_DROP(ifq); 1694 scp->sp_if.if_iqdrops++; 1695 goto dropit; 1696 } 1697 return; 1698 dropit: 1699 if (m) 1700 m_freem(m); 1701 return; 1702 } 1703 1704 #if SCA_DEBUG_LEVEL > 0 1705 /* 1706 * do a hex dump of the packet received into descriptor "desc" with 1707 * data buffer "p" 1708 */ 1709 static void 1710 sca_frame_print(sca_port_t *scp, sca_desc_t *desc, u_int8_t *p) 1711 { 1712 int i; 1713 int nothing_yet = 1; 1714 struct sca_softc *sc; 1715 u_int len; 1716 1717 sc = scp->sca; 1718 printf("desc va %p: chainp 0x%x bufp 0x%0x stat 0x%0x len %d\n", 1719 desc, 1720 sca_desc_read_chainp(sc, desc), 1721 sca_desc_read_bufp(sc, desc), 1722 sca_desc_read_stat(sc, desc), 1723 (len = sca_desc_read_buflen(sc, desc))); 1724 1725 for (i = 0 ; i < len && i < 256; i++) { 1726 if (nothing_yet == 1 && 1727 (sc->sc_usedma ? *p 1728 : bus_space_read_1(sc->scu_memt, sc->scu_memh, 1729 sca_page_addr(sc, p))) == 0) { 1730 p++; 1731 continue; 1732 } 1733 nothing_yet = 0; 1734 if (i % 16 == 0) 1735 printf("\n"); 1736 printf("%02x ", 1737 (sc->sc_usedma ? *p 1738 : bus_space_read_1(sc->scu_memt, sc->scu_memh, 1739 sca_page_addr(sc, p)))); 1740 p++; 1741 } 1742 1743 if (i % 16 != 1) 1744 printf("\n"); 1745 } 1746 #endif 1747 1748 /* 1749 * adjust things becuase we have just read the current starting 1750 * frame 1751 * 1752 * must be called at splnet() 1753 */ 1754 static void 1755 sca_frame_read_done(sca_port_t *scp) 1756 { 1757 u_int16_t edesc_p; 1758 1759 /* update where our indicies are */ 1760 scp->sp_rxend = scp->sp_rxstart; 1761 scp->sp_rxstart = (scp->sp_rxstart + 1) % scp->sp_nrxdesc; 1762 1763 /* update the error [end] descriptor */ 1764 edesc_p = (u_int16_t)scp->sp_rxdesc_p + 1765 (sizeof(sca_desc_t) * scp->sp_rxend); 1766 dmac_write_2(scp, SCA_EDAL0, edesc_p); 1767 } 1768 1769 /* 1770 * set a port to the "up" state 1771 */ 1772 static void 1773 sca_port_up(sca_port_t *scp) 1774 { 1775 struct sca_softc *sc = scp->sca; 1776 #if 0 1777 u_int8_t ier0, ier1; 1778 #endif 1779 1780 /* 1781 * reset things 1782 */ 1783 #if 0 1784 msci_write_1(scp, SCA_CMD0, SCA_CMD_TXRESET); 1785 msci_write_1(scp, SCA_CMD0, SCA_CMD_RXRESET); 1786 #endif 1787 /* 1788 * clear in-use flag 1789 */ 1790 scp->sp_if.if_flags &= ~IFF_OACTIVE; 1791 scp->sp_if.if_flags |= IFF_RUNNING; 1792 1793 /* 1794 * raise DTR 1795 */ 1796 sc->sc_dtr_callback(sc->sc_aux, scp->sp_port, 1); 1797 1798 /* 1799 * raise RTS 1800 */ 1801 msci_write_1(scp, SCA_CTL0, 1802 (msci_read_1(scp, SCA_CTL0) & ~SCA_CTL_RTS_MASK) 1803 | SCA_CTL_RTS_HIGH); 1804 1805 #if 0 1806 /* 1807 * enable interrupts (no timer IER2) 1808 */ 1809 ier0 = SCA_IER0_MSCI_RXRDY0 | SCA_IER0_MSCI_TXRDY0 1810 | SCA_IER0_MSCI_RXINT0 | SCA_IER0_MSCI_TXINT0; 1811 ier1 = SCA_IER1_DMAC_RX0A | SCA_IER1_DMAC_RX0B 1812 | SCA_IER1_DMAC_TX0A | SCA_IER1_DMAC_TX0B; 1813 if (scp->sp_port == 1) { 1814 ier0 <<= 4; 1815 ier1 <<= 4; 1816 } 1817 sca_write_1(sc, SCA_IER0, sca_read_1(sc, SCA_IER0) | ier0); 1818 sca_write_1(sc, SCA_IER1, sca_read_1(sc, SCA_IER1) | ier1); 1819 #else 1820 if (scp->sp_port == 0) { 1821 sca_write_1(sc, SCA_IER0, sca_read_1(sc, SCA_IER0) | 0x0f); 1822 sca_write_1(sc, SCA_IER1, sca_read_1(sc, SCA_IER1) | 0x0f); 1823 } else { 1824 sca_write_1(sc, SCA_IER0, sca_read_1(sc, SCA_IER0) | 0xf0); 1825 sca_write_1(sc, SCA_IER1, sca_read_1(sc, SCA_IER1) | 0xf0); 1826 } 1827 #endif 1828 1829 /* 1830 * enable transmit and receive 1831 */ 1832 msci_write_1(scp, SCA_CMD0, SCA_CMD_TXENABLE); 1833 msci_write_1(scp, SCA_CMD0, SCA_CMD_RXENABLE); 1834 1835 /* 1836 * reset internal state 1837 */ 1838 scp->sp_txinuse = 0; 1839 scp->sp_txcur = 0; 1840 scp->cka_lasttx = time.tv_usec; 1841 scp->cka_lastrx = 0; 1842 } 1843 1844 /* 1845 * set a port to the "down" state 1846 */ 1847 static void 1848 sca_port_down(sca_port_t *scp) 1849 { 1850 struct sca_softc *sc = scp->sca; 1851 #if 0 1852 u_int8_t ier0, ier1; 1853 #endif 1854 1855 /* 1856 * lower DTR 1857 */ 1858 sc->sc_dtr_callback(sc->sc_aux, scp->sp_port, 0); 1859 1860 /* 1861 * lower RTS 1862 */ 1863 msci_write_1(scp, SCA_CTL0, 1864 (msci_read_1(scp, SCA_CTL0) & ~SCA_CTL_RTS_MASK) 1865 | SCA_CTL_RTS_LOW); 1866 1867 /* 1868 * disable interrupts 1869 */ 1870 #if 0 1871 ier0 = SCA_IER0_MSCI_RXRDY0 | SCA_IER0_MSCI_TXRDY0 1872 | SCA_IER0_MSCI_RXINT0 | SCA_IER0_MSCI_TXINT0; 1873 ier1 = SCA_IER1_DMAC_RX0A | SCA_IER1_DMAC_RX0B 1874 | SCA_IER1_DMAC_TX0A | SCA_IER1_DMAC_TX0B; 1875 if (scp->sp_port == 1) { 1876 ier0 <<= 4; 1877 ier1 <<= 4; 1878 } 1879 sca_write_1(sc, SCA_IER0, sca_read_1(sc, SCA_IER0) & ~ier0); 1880 sca_write_1(sc, SCA_IER1, sca_read_1(sc, SCA_IER1) & ~ier1); 1881 #else 1882 if (scp->sp_port == 0) { 1883 sca_write_1(sc, SCA_IER0, sca_read_1(sc, SCA_IER0) & 0xf0); 1884 sca_write_1(sc, SCA_IER1, sca_read_1(sc, SCA_IER1) & 0xf0); 1885 } else { 1886 sca_write_1(sc, SCA_IER0, sca_read_1(sc, SCA_IER0) & 0x0f); 1887 sca_write_1(sc, SCA_IER1, sca_read_1(sc, SCA_IER1) & 0x0f); 1888 } 1889 #endif 1890 1891 /* 1892 * disable transmit and receive 1893 */ 1894 msci_write_1(scp, SCA_CMD0, SCA_CMD_RXDISABLE); 1895 msci_write_1(scp, SCA_CMD0, SCA_CMD_TXDISABLE); 1896 1897 /* 1898 * no, we're not in use anymore 1899 */ 1900 scp->sp_if.if_flags &= ~(IFF_OACTIVE|IFF_RUNNING); 1901 } 1902 1903 /* 1904 * disable all DMA and interrupts for all ports at once. 1905 */ 1906 void 1907 sca_shutdown(struct sca_softc *sca) 1908 { 1909 /* 1910 * disable DMA and interrupts 1911 */ 1912 sca_write_1(sca, SCA_DMER, 0); 1913 sca_write_1(sca, SCA_IER0, 0); 1914 sca_write_1(sca, SCA_IER1, 0); 1915 } 1916 1917 /* 1918 * If there are packets to transmit, start the transmit DMA logic. 1919 */ 1920 static void 1921 sca_port_starttx(sca_port_t *scp) 1922 { 1923 struct sca_softc *sc; 1924 u_int32_t startdesc_p, enddesc_p; 1925 int enddesc; 1926 1927 sc = scp->sca; 1928 1929 SCA_DPRINTF(SCA_DEBUG_TX, ("TX: starttx\n")); 1930 1931 if (((scp->sp_if.if_flags & IFF_OACTIVE) == IFF_OACTIVE) 1932 || scp->sp_txinuse == 0) 1933 return; 1934 1935 SCA_DPRINTF(SCA_DEBUG_TX, ("TX: setting oactive\n")); 1936 1937 scp->sp_if.if_flags |= IFF_OACTIVE; 1938 1939 /* 1940 * We have something to do, since we have at least one packet 1941 * waiting, and we are not already marked as active. 1942 */ 1943 enddesc = (scp->sp_txcur + 1) % scp->sp_ntxdesc; 1944 startdesc_p = scp->sp_txdesc_p; 1945 enddesc_p = scp->sp_txdesc_p + sizeof(sca_desc_t) * enddesc; 1946 1947 SCA_DPRINTF(SCA_DEBUG_TX, ("TX: start %x end %x\n", 1948 startdesc_p, enddesc_p)); 1949 1950 dmac_write_2(scp, SCA_EDAL1, (u_int16_t)(enddesc_p & 0x0000ffff)); 1951 dmac_write_2(scp, SCA_CDAL1, 1952 (u_int16_t)(startdesc_p & 0x0000ffff)); 1953 1954 /* 1955 * enable the DMA 1956 */ 1957 dmac_write_1(scp, SCA_DSR1, SCA_DSR_DE); 1958 } 1959 1960 /* 1961 * allocate an mbuf at least long enough to hold "len" bytes. 1962 * If "p" is non-NULL, copy "len" bytes from it into the new mbuf, 1963 * otherwise let the caller handle copying the data in. 1964 */ 1965 static struct mbuf * 1966 sca_mbuf_alloc(struct sca_softc *sc, caddr_t p, u_int len) 1967 { 1968 struct mbuf *m; 1969 1970 /* 1971 * allocate an mbuf and copy the important bits of data 1972 * into it. If the packet won't fit in the header, 1973 * allocate a cluster for it and store it there. 1974 */ 1975 MGETHDR(m, M_DONTWAIT, MT_DATA); 1976 if (m == NULL) 1977 return NULL; 1978 if (len > MHLEN) { 1979 if (len > MCLBYTES) { 1980 m_freem(m); 1981 return NULL; 1982 } 1983 MCLGET(m, M_DONTWAIT); 1984 if ((m->m_flags & M_EXT) == 0) { 1985 m_freem(m); 1986 return NULL; 1987 } 1988 } 1989 if (p != NULL) { 1990 /* XXX do we need to sync here? */ 1991 if (sc->sc_usedma) 1992 bcopy(p, mtod(m, caddr_t), len); 1993 else 1994 bus_space_read_region_1(sc->scu_memt, sc->scu_memh, 1995 sca_page_addr(sc, p), mtod(m, u_int8_t *), len); 1996 } 1997 m->m_len = len; 1998 m->m_pkthdr.len = len; 1999 2000 return (m); 2001 } 2002 2003 /* 2004 * get the base clock 2005 */ 2006 void 2007 sca_get_base_clock(struct sca_softc *sc) 2008 { 2009 struct timeval btv, ctv, dtv; 2010 u_int64_t bcnt; 2011 u_int32_t cnt; 2012 u_int16_t subcnt; 2013 2014 /* disable the timer, set prescale to 0 */ 2015 sca_write_1(sc, SCA_TCSR0, 0); 2016 sca_write_1(sc, SCA_TEPR0, 0); 2017 2018 /* reset the counter */ 2019 (void)sca_read_1(sc, SCA_TCSR0); 2020 subcnt = sca_read_2(sc, SCA_TCNTL0); 2021 2022 /* count to max */ 2023 sca_write_2(sc, SCA_TCONRL0, 0xffff); 2024 2025 cnt = 0; 2026 microtime(&btv); 2027 /* start the timer -- no interrupt enable */ 2028 sca_write_1(sc, SCA_TCSR0, SCA_TCSR_TME); 2029 for (;;) { 2030 microtime(&ctv); 2031 2032 /* end around 3/4 of a second */ 2033 timersub(&ctv, &btv, &dtv); 2034 if (dtv.tv_usec >= 750000) 2035 break; 2036 2037 /* spin */ 2038 while (!(sca_read_1(sc, SCA_TCSR0) & SCA_TCSR_CMF)) 2039 ; 2040 /* reset the timer */ 2041 (void)sca_read_2(sc, SCA_TCNTL0); 2042 cnt++; 2043 } 2044 2045 /* stop the timer */ 2046 sca_write_1(sc, SCA_TCSR0, 0); 2047 2048 subcnt = sca_read_2(sc, SCA_TCNTL0); 2049 /* add the slop in and get the total timer ticks */ 2050 cnt = (cnt << 16) | subcnt; 2051 2052 /* cnt is 1/8 the actual time */ 2053 bcnt = cnt * 8; 2054 /* make it proportional to 3/4 of a second */ 2055 bcnt *= (u_int64_t)750000; 2056 bcnt /= (u_int64_t)dtv.tv_usec; 2057 cnt = bcnt; 2058 2059 /* make it Hz */ 2060 cnt *= 4; 2061 cnt /= 3; 2062 2063 SCA_DPRINTF(SCA_DEBUG_CLOCK, 2064 ("sca: unadjusted base %lu Hz\n", (u_long)cnt)); 2065 2066 /* 2067 * round to the nearest 200 -- this allows for +-3 ticks error 2068 */ 2069 sc->sc_baseclock = ((cnt + 100) / 200) * 200; 2070 } 2071 2072 /* 2073 * print the information about the clock on the ports 2074 */ 2075 void 2076 sca_print_clock_info(struct sca_softc *sc) 2077 { 2078 struct sca_port *scp; 2079 u_int32_t mhz, div; 2080 int i; 2081 2082 printf("%s: base clock %d Hz\n", sc->sc_parent->dv_xname, 2083 sc->sc_baseclock); 2084 2085 /* print the information about the port clock selection */ 2086 for (i = 0; i < sc->sc_numports; i++) { 2087 scp = &sc->sc_ports[i]; 2088 mhz = sc->sc_baseclock / (scp->sp_tmc ? scp->sp_tmc : 256); 2089 div = scp->sp_rxs & SCA_RXS_DIV_MASK; 2090 2091 printf("%s: rx clock: ", scp->sp_if.if_xname); 2092 switch (scp->sp_rxs & SCA_RXS_CLK_MASK) { 2093 case SCA_RXS_CLK_LINE: 2094 printf("line"); 2095 break; 2096 case SCA_RXS_CLK_LINE_SN: 2097 printf("line with noise suppression"); 2098 break; 2099 case SCA_RXS_CLK_INTERNAL: 2100 printf("internal %d Hz", (mhz >> div)); 2101 break; 2102 case SCA_RXS_CLK_ADPLL_OUT: 2103 printf("adpll using internal %d Hz", (mhz >> div)); 2104 break; 2105 case SCA_RXS_CLK_ADPLL_IN: 2106 printf("adpll using line clock"); 2107 break; 2108 } 2109 printf(" tx clock: "); 2110 div = scp->sp_txs & SCA_TXS_DIV_MASK; 2111 switch (scp->sp_txs & SCA_TXS_CLK_MASK) { 2112 case SCA_TXS_CLK_LINE: 2113 printf("line\n"); 2114 break; 2115 case SCA_TXS_CLK_INTERNAL: 2116 printf("internal %d Hz\n", (mhz >> div)); 2117 break; 2118 case SCA_TXS_CLK_RXCLK: 2119 printf("rxclock\n"); 2120 break; 2121 } 2122 if (scp->sp_eclock) 2123 printf("%s: outputting line clock\n", 2124 scp->sp_if.if_xname); 2125 } 2126 } 2127 2128
Indexes created Fri Sep 26 20:09:58 GMT 2025