hd64570reg.h revision 1.2
1 /* $NetBSD: hd64570reg.h,v 1.2 1998/10/28 16:26:01 kleink Exp $ */ 2 3 /* 4 * Copyright (c) 1998 Vixie Enterprises 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of Vixie Enterprises nor the names 17 * of its contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY VIXIE ENTERPRISES AND 21 * CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 22 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL VIXIE ENTERPRISES OR 25 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 29 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * This software has been written for Vixie Enterprises by Michael Graff 35 * <explorer (at) flame.org>. To learn more about Vixie Enterprises, see 36 * ``http://www.vix.com''. 37 */ 38 39 #ifndef _DEV_IC_HD64570REG_H_ 40 #define _DEV_IC_HD64570REG_H_ 41 42 /* XXX 43 * This is really HDLC specific stuff, but... 44 */ 45 #define CISCO_MULTICAST 0x8f /* Cisco multicast address */ 46 #define CISCO_UNICAST 0x0f /* Cisco unicast address */ 47 #define CISCO_KEEPALIVE 0x8035 /* Cisco keepalive protocol */ 48 #define CISCO_ADDR_REQ 0 /* Cisco address request */ 49 #define CISCO_ADDR_REPLY 1 /* Cisco address reply */ 50 #define CISCO_KEEPALIVE_REQ 2 /* Cisco keepalive request */ 51 52 typedef struct cisco_pkt { 53 u_int32_t type; 54 u_int32_t par1; 55 u_int32_t par2; 56 u_int16_t rel; 57 u_int16_t time0; 58 u_int16_t time1; 59 } cisco_pkt_t; 60 #define CISCO_PKT_LEN 18 /* sizeof doesn't work right... */ 61 62 #define HDLC_PROTOCOL_IP 0x0800 /* IP */ 63 64 typedef struct hdlc_header { 65 u_int8_t addr; 66 u_int8_t control; 67 u_int16_t protocol; 68 } hdlc_header_t; 69 #define HDLC_HDRLEN 4 70 71 /* 72 * Hitachi HD64570 defininitions 73 */ 74 75 /* 76 * At least one implementation uses a somewhat strange register address 77 * mapping. If a card doesn't, define this to be a pass-through 78 * macro. (The ntwo driver needs this...) 79 */ 80 #ifndef SCADDR 81 #define SCADDR(y) (((y) & 0x0002) ? (((y) & 0x00fd) + 0x100) : (y)) 82 #endif 83 84 /* SCA Control Registers */ 85 #define SCA_PABR0 2 86 #define SCA_PABR1 3 87 #define SCA_WCRL 4 /* Wait Control reg */ 88 #define SCA_WCRM 5 /* Wait Control reg */ 89 #define SCA_WCRH 6 /* Wait Control reg */ 90 #define SCA_PCR 8 /* DMA priority control reg */ 91 92 /* Interrupt registers */ 93 #define SCA_ISR0 0x10 /* Interrupt status register 0 */ 94 #define SCA_ISR1 0x11 /* Interrupt status register 1 */ 95 #define SCA_ISR2 0x12 /* Interrupt status register 2 */ 96 #define SCA_IER0 0x14 /* Interrupt enable register 0 */ 97 #define SCA_IER1 0x15 /* Interrupt enable register 1 */ 98 #define SCA_IER2 0x16 /* Interrupt enable register 2 */ 99 #define SCA_ITCR 0x18 /* interrupt control register */ 100 #define SCA_IVR 0x1a /* interrupt vector */ 101 #define SCA_IMVR 0x1c /* modified interrupt vector */ 102 103 /* MSCI Channel 0 Registers */ 104 #define SCA_TRBL0 0x20 /* TX/RX buffer reg */ 105 #define SCA_TRBH0 0x21 /* TX/RX buffer reg */ 106 #define SCA_ST00 0x22 /* Status reg 0 */ 107 #define SCA_ST10 0x23 /* Status reg 1 */ 108 #define SCA_ST20 0x24 /* Status reg 2 */ 109 #define SCA_ST30 0x25 /* Status reg 3 */ 110 #define SCA_FST0 0x26 /* frame Status reg */ 111 #define SCA_IE00 0x28 /* Interrupt enable reg 0 */ 112 #define SCA_IE10 0x29 /* Interrupt enable reg 1 */ 113 #define SCA_IE20 0x2a /* Interrupt enable reg 2 */ 114 #define SCA_FIE0 0x2b /* Frame Interrupt enable reg */ 115 #define SCA_CMD0 0x2c /* Command reg */ 116 #define SCA_MD00 0x2e /* Mode reg 0 */ 117 #define SCA_MD10 0x2f /* Mode reg 1 */ 118 #define SCA_MD20 0x30 /* Mode reg 2 */ 119 #define SCA_CTL0 0x31 /* Control reg */ 120 #define SCA_SA00 0x32 /* Syn Address reg 0 */ 121 #define SCA_SA10 0x33 /* Syn Address reg 1 */ 122 #define SCA_IDL0 0x34 /* Idle register */ 123 #define SCA_TMC0 0x35 /* Time constant */ 124 #define SCA_RXS0 0x36 /* RX clock source */ 125 #define SCA_TXS0 0x37 /* TX clock source */ 126 #define SCA_TRC00 0x38 /* TX Ready control reg 0 */ 127 #define SCA_TRC10 0x39 /* TX Ready control reg 1 */ 128 #define SCA_RRC0 0x3A /* RX Ready control reg */ 129 130 /* MSCI Channel 1 Registers */ 131 #define SCA_TRBL1 0x40 /* TX/RX buffer reg */ 132 #define SCA_TRBH1 0x41 /* TX/RX buffer reg */ 133 #define SCA_ST01 0x42 /* Status reg 0 */ 134 #define SCA_ST11 0x43 /* Status reg 1 */ 135 #define SCA_ST21 0x44 /* Status reg 2 */ 136 #define SCA_ST31 0x45 /* Status reg 3 */ 137 #define SCA_FST1 0x46 /* Frame Status reg */ 138 #define SCA_IE01 0x48 /* Interrupt enable reg 0 */ 139 #define SCA_IE11 0x49 /* Interrupt enable reg 1 */ 140 #define SCA_IE21 0x4a /* Interrupt enable reg 2 */ 141 #define SCA_FIE1 0x4b /* Frame Interrupt enable reg */ 142 #define SCA_CMD1 0x4c /* Command reg */ 143 #define SCA_MD01 0x4e /* Mode reg 0 */ 144 #define SCA_MD11 0x4f /* Mode reg 1 */ 145 #define SCA_MD21 0x50 /* Mode reg 2 */ 146 #define SCA_CTL1 0x51 /* Control reg */ 147 #define SCA_SA01 0x52 /* Syn Address reg 0 */ 148 #define SCA_SA11 0x53 /* Syn Address reg 1 */ 149 #define SCA_IDL1 0x54 /* Idle register */ 150 #define SCA_TMC1 0x55 /* Time constant */ 151 #define SCA_RXS1 0x56 /* RX clock source */ 152 #define SCA_TXS1 0x57 /* TX clock source */ 153 #define SCA_TRC01 0x58 /* TX Ready control reg 0 */ 154 #define SCA_TRC11 0x59 /* TX Ready control reg 1 */ 155 #define SCA_RRC1 0x5A /* RX Ready control reg */ 156 157 158 /* SCA DMA registers */ 159 160 #define SCA_DMER 0x9 /* DMA Master Enable reg */ 161 162 /* DMA Channel 0 Registers (MSCI -> memory, or rx) */ 163 #define SCA_BARL0 0x80 /* buffer address reg */ 164 #define SCA_BARH0 0x81 /* buffer address reg */ 165 #define SCA_BARB0 0x82 /* buffer address reg */ 166 #define SCA_DARL0 0x80 /* Dest. address reg */ 167 #define SCA_DARH0 0x81 /* Dest. address reg */ 168 #define SCA_DARB0 0x82 /* Dest. address reg */ 169 #define SCA_CPB0 0x86 /* Chain pointer base */ 170 #define SCA_CDAL0 0x88 /* Current descriptor address */ 171 #define SCA_CDAH0 0x89 /* Current descriptor address */ 172 #define SCA_EDAL0 0x8A /* Error descriptor address */ 173 #define SCA_EDAH0 0x8B /* Error descriptor address */ 174 #define SCA_BFLL0 0x8C /* RX buffer length Low */ 175 #define SCA_BFLH0 0x8D /* RX buffer length High */ 176 #define SCA_BCRL0 0x8E /* Byte Count reg */ 177 #define SCA_BCRH0 0x8F /* Byte Count reg */ 178 #define SCA_DSR0 0x90 /* DMA Status reg */ 179 #define SCA_DMR0 0x91 /* DMA Mode reg */ 180 #define SCA_FCT0 0x93 /* Frame end interrupt Counter */ 181 #define SCA_DIR0 0x94 /* DMA interrupt enable */ 182 #define SCA_DCR0 0x95 /* DMA Command reg */ 183 184 /* DMA Channel 1 Registers (memory -> MSCI, or tx) */ 185 #define SCA_BARL1 0xA0 /* buffer address reg */ 186 #define SCA_BARH1 0xA1 /* buffer address reg */ 187 #define SCA_BARB1 0xA2 /* buffer address reg */ 188 #define SCA_SARL1 0xA4 /* Source address reg */ 189 #define SCA_SARH1 0xA5 /* Source address reg */ 190 #define SCA_SARB1 0xA6 /* Source address reg */ 191 #define SCA_CPB1 0xA6 /* Chain pointer base */ 192 #define SCA_CDAL1 0xA8 /* Current descriptor address */ 193 #define SCA_CDAH1 0xA9 /* Current descriptor address */ 194 #define SCA_EDAL1 0xAA /* Error descriptor address */ 195 #define SCA_EDAH1 0xAB /* Error descriptor address */ 196 #define SCA_BCRL1 0xAE /* Byte Count reg */ 197 #define SCA_BCRH1 0xAF /* Byte Count reg */ 198 #define SCA_DSR1 0xB0 /* DMA Status reg */ 199 #define SCA_DMR1 0xB1 /* DMA Mode reg */ 200 #define SCA_FCT1 0xB3 /* Frame end interrupt Counter */ 201 #define SCA_DIR1 0xB4 /* DMA interrupt enable */ 202 #define SCA_DCR1 0xB5 /* DMA Command reg */ 203 204 /* DMA Channel 2 Registers (MSCI -> memory) */ 205 #define SCA_BARL2 0xC0 /* buffer address reg */ 206 #define SCA_BARH2 0xC1 /* buffer address reg */ 207 #define SCA_BARB2 0xC2 /* buffer address reg */ 208 #define SCA_DSR2 0xD0 /* DMA Status reg */ 209 210 /* DMA Channel 3 Registers (memory -> MSCI) */ 211 #define SCA_BARL3 0xE0 /* buffer address reg */ 212 #define SCA_BARH3 0xE1 /* buffer address reg */ 213 #define SCA_BARB3 0xE2 /* buffer address reg */ 214 #define SCA_DSR3 0xF0 /* DMA Status reg */ 215 216 /* 217 * SCA HD64570 Register Definitions 218 */ 219 220 #define ST3_CTS 8 /* modem input /CTS bit */ 221 #define ST3_DCD 4 /* modem input /DCD bit */ 222 223 /* 224 * SCA commands 225 */ 226 #define SCA_CMD_TXRESET 0x01 227 #define SCA_CMD_TXENABLE 0x02 228 #define SCA_CMD_TXDISABLE 0x03 229 #define SCA_CMD_TXCRCINIT 0x04 230 #define SCA_CMD_TXCRCEXCL 0x05 231 #define SCA_CMS_TXEOM 0x06 232 #define SCA_CMD_TXABORT 0x07 233 #define SCA_CMD_MPON 0x08 234 #define SCA_CMD_TXBCLEAR 0x09 235 236 #define SCA_CMD_RXRESET 0x11 237 #define SCA_CMD_RXENABLE 0x12 238 #define SCA_CMD_RXDISABLE 0x13 239 #define SCA_CMD_RXCRCINIT 0x14 240 #define SCA_CMD_RXMSGREJ 0x15 241 #define SCA_CMD_MPSEARCH 0x16 242 #define SCA_CMD_RXCRCEXCL 0x17 243 #define SCA_CMD_RXCRCCALC 0x18 244 245 #define SCA_CMD_NOP 0x00 246 #define SCA_CMD_RESET 0x21 247 #define SCA_CMD_SEARCH 0x31 248 249 #define SCA_MD0_CRC_1 0x01 250 #define SCA_MD0_CRC_CCITT 0x02 251 #define SCA_MD0_CRC_ENABLE 0x04 252 #define SCA_MD0_AUTO_ENABLE 0x10 253 #define SCA_MD0_MODE_ASYNC 0x00 254 #define SCA_MD0_MODE_BYTESYNC1 0x20 255 #define SCA_MD0_MODE_BISYNC 0x40 256 #define SCA_MD0_MODE_BYTESYNC2 0x60 257 #define SCA_MD0_MODE_HDLC 0x80 258 259 #define SCA_MD1_NOADDRCHK 0x00 260 #define SCA_MD1_SNGLADDR1 0x40 261 #define SCA_MD1_SNGLADDR2 0x80 262 #define SCA_MD1_DUALADDR 0xC0 263 264 #define SCA_MD2_DUPLEX 0x00 265 #define SCA_MD2_ECHO 0x01 266 #define SCA_MD2_LOOPBACK 0x03 267 #define SCA_MD2_ADPLLx8 0x00 268 #define SCA_MD2_ADPLLx16 0x08 269 #define SCA_MD2_ADPLLx32 0x10 270 #define SCA_MD2_NRZ 0x00 271 #define SCA_MD2_NRZI 0x20 272 #define SCA_MD2_MANCHESTER 0x80 273 #define SCA_MD2_FM0 0xC0 274 #define SCA_MD2_FM1 0xA0 275 276 #define SCA_CTL_RTS 0x01 277 #define SCA_CTL_IDLPAT 0x10 278 #define SCA_CTL_UDRNC 0x20 279 280 #define SCA_RXS_DIV_MASK 0x0F 281 #define SCA_RXS_DIV1 0x00 282 #define SCA_RXS_DIV2 0x01 283 #define SCA_RXS_DIV4 0x02 284 #define SCA_RXS_DIV8 0x03 285 #define SCA_RXS_DIV16 0x04 286 #define SCA_RXS_DIV32 0x05 287 #define SCA_RXS_DIV64 0x06 288 #define SCA_RXS_DIV128 0x07 289 #define SCA_RXS_DIV256 0x08 290 #define SCA_RXS_DIV512 0x09 291 #define SCA_RXS_CLK_RXC0 0x00 292 #define SCA_RXS_CLK_RXC1 0x20 293 #define SCA_RXS_CLK_INT 0x40 294 #define SCA_RXS_CLK_ADPLL_OUT 0x60 295 #define SCA_RXS_CLK_ADPLL_IN 0x70 296 297 #define SCA_TXS_DIV_MASK 0x0F 298 #define SCA_TXS_DIV1 0x00 299 #define SCA_TXS_DIV2 0x01 300 #define SCA_TXS_DIV4 0x02 301 #define SCA_TXS_DIV8 0x03 302 #define SCA_TXS_DIV16 0x04 303 #define SCA_TXS_DIV32 0x05 304 #define SCA_TXS_DIV64 0x06 305 #define SCA_TXS_DIV128 0x07 306 #define SCA_TXS_DIV256 0x08 307 #define SCA_TXS_DIV512 0x09 308 #define SCA_TXS_CLK_TXC 0x00 309 #define SCA_TXS_CLK_INT 0x40 310 #define SCA_TXS_CLK_RX 0x60 311 312 #define SCA_ST0_RXRDY 0x01 313 #define SCA_ST0_TXRDY 0x02 314 #define SCA_ST0_RXINT 0x40 315 #define SCA_ST0_TXINT 0x80 316 317 #define SCA_ST1_IDLST 0x01 318 #define SCA_ST1_ABTST 0x02 319 #define SCA_ST1_DCDCHG 0x04 320 #define SCA_ST1_CTSCHG 0x08 321 #define SCA_ST1_FLAG 0x10 322 #define SCA_ST1_TXIDL 0x40 323 #define SCA_ST1_UDRN 0x80 324 325 /* ST2 and FST look the same */ 326 #define SCA_FST_CRCERR 0x04 327 #define SCA_FST_OVRN 0x08 328 #define SCA_FST_RESFRM 0x10 329 #define SCA_FST_ABRT 0x20 330 #define SCA_FST_SHRT 0x40 331 #define SCA_FST_EOM 0x80 332 333 #define SCA_ST3_RXENA 0x01 334 #define SCA_ST3_TXENA 0x02 335 #define SCA_ST3_DCD 0x04 336 #define SCA_ST3_CTS 0x08 337 #define SCA_ST3_ADPLLSRCH 0x10 338 #define SCA_ST3_TXDATA 0x20 339 340 #define SCA_FIE_EOMFE 0x80 341 342 #define SCA_IE0_RXRDY 0x01 343 #define SCA_IE0_TXRDY 0x02 344 #define SCA_IE0_RXINT 0x40 345 #define SCA_IE0_TXINT 0x80 346 347 #define SCA_IE1_IDLDE 0x01 348 #define SCA_IE1_ABTDE 0x02 349 #define SCA_IE1_DCD 0x04 350 #define SCA_IE1_CTS 0x08 351 #define SCA_IE1_FLAG 0x10 352 #define SCA_IE1_IDL 0x40 353 #define SCA_IE1_UDRN 0x80 354 355 #define SCA_IE2_CRCERR 0x04 356 #define SCA_IE2_OVRN 0x08 357 #define SCA_IE2_RESFRM 0x10 358 #define SCA_IE2_ABRT 0x20 359 #define SCA_IE2_SHRT 0x40 360 #define SCA_IE2_EOM 0x80 361 362 /* This is for RRC, TRC0 and TRC1. */ 363 #define SCA_RCR_MASK 0x1F 364 365 #define SCA_IE1_ 366 367 #define SCA_IV_CHAN0 0x00 368 #define SCA_IV_CHAN1 0x20 369 370 #define SCA_IV_RXRDY 0x04 371 #define SCA_IV_TXRDY 0x06 372 #define SCA_IV_RXINT 0x08 373 #define SCA_IV_TXINT 0x0A 374 375 #define SCA_IV_DMACH0 0x00 376 #define SCA_IV_DMACH1 0x08 377 #define SCA_IV_DMACH2 0x20 378 #define SCA_IV_DMACH3 0x28 379 380 #define SCA_IV_DMIA 0x14 381 #define SCA_IV_DMIB 0x16 382 383 #define SCA_IV_TIMER0 0x1C 384 #define SCA_IV_TIMER1 0x1E 385 #define SCA_IV_TIMER2 0x3C 386 #define SCA_IV_TIMER3 0x3E 387 388 /* 389 * DMA registers 390 */ 391 #define SCA_DSR_EOT 0x80 392 #define SCA_DSR_EOM 0x40 393 #define SCA_DSR_BOF 0x20 394 #define SCA_DSR_COF 0x10 395 #define SCA_DSR_DE 0x02 396 #define SCA_DSR_DEWD 0x01 /* write DISABLE DE bit */ 397 398 #define SCA_DMR_TMOD 0x10 399 #define SCA_DMR_NF 0x04 400 #define SCA_DMR_CNTE 0x02 401 402 #define SCA_DMER_EN 0x80 403 404 #define SCA_DCR_ABRT 0x01 405 #define SCA_DCR_FCCLR 0x02 /* Clear frame end intr counter */ 406 407 #define SCA_DIR_EOT 0x80 408 #define SCA_DIR_EOM 0x40 409 #define SCA_DIR_BOF 0x20 410 #define SCA_DIR_COF 0x10 411 412 #define SCA_PCR_BRC 0x10 413 #define SCA_PCR_CCC 0x08 414 #define SCA_PCR_PR2 0x04 415 #define SCA_PCR_PR1 0x02 416 #define SCA_PCR_PR0 0x01 417 418 /* 419 * Descriptor Status byte bit definitions: 420 * 421 * Bit Receive Status Transmit Status 422 * ------------------------------------------------- 423 * 7 EOM EOM 424 * 6 Short Frame ... 425 * 5 Abort ... 426 * 4 Residual bit ... 427 * 3 Overrun ... 428 * 2 CRC ... 429 * 1 ... ... 430 * 0 ... EOT 431 * ------------------------------------------------- 432 */ 433 434 #define ST_EOM 0x80 /* End of frame */ 435 #define ST_SHRT 0x40 /* Short frame */ 436 #define ST_ABT 0x20 /* Abort detected */ 437 #define ST_RBIT 0x10 /* Residual bit detected */ 438 #define ST_OVRN 0x8 /* Overrun error */ 439 #define ST_CRCE 0x4 /* CRC Error */ 440 #define ST_OVFL 0x1 /* Buffer OverFlow error (software defined) */ 441 442 #define ST_EOT 1 /* End of transmit command */ 443 444 445 /* DMA Status register (DSR) bit definitions */ 446 #define DSR_EOT 0x80 /* end of transfer EOT bit */ 447 #define DSR_EOM 0x40 /* end of frame EOM bit */ 448 #define DSR_BOF 0x20 /* buffer overflow BOF bit */ 449 #define DSR_COF 0x10 /* counter overflow COF bit */ 450 #define DSR_DWE 1 /* write disable DWE bit */ 451 452 /* MSCI Status register 0 bits */ 453 454 #define RXRDY_BIT 1 /* RX ready */ 455 #define TXRDY_BIT 2 /* TX ready */ 456 457 #define ST3_CTS 8 /* modem input /CTS bit */ 458 #define ST3_DCD 4 /* modem input /DCD bit */ 459 460 461 /* TX and RX Clock Source */ 462 #define CLK_LINE 0x00 /* TX/RX line input */ 463 #define CLK_BRG 0x40 /* internal baud rate generator */ 464 #define CLK_RXC 0x60 /* receive clock */ 465 466 /* Clocking options */ 467 #define CLK_INT 0 /* Internal - Baud Rate generator output */ 468 #define CLK_EXT 1 /* External - both clocks */ 469 #define CLK_RXCI 2 /* External - Receive Clock only */ 470 #define CLK_EETC 3 /* EETC clock: TX = int. / RX = ext.*/ 471 472 #define SCA_DMAC_OFF_0 0x00 /* offset of DMAC for port 0 */ 473 #define SCA_DMAC_OFF_1 0x40 /* offset of DMAC for port 1 */ 474 #define SCA_MSCI_OFF_0 0x00 /* offset of MSCI for port 0 */ 475 #define SCA_MSCI_OFF_1 0x20 /* offset of MSCI for port 1 */ 476 477 /* 478 * DMA constraints 479 */ 480 #define SCA_DMA_ALIGNMENT (64 * 1024) /* 64 KB alignment */ 481 #define SCA_DMA_BOUNDRY (16 * 1024 * 1024) /* 16 MB region */ 482 483 #endif /* _DEV_IC_HD64570REG_H_ */ 484
Indexes created Tue Sep 30 11:09:46 GMT 2025