hd64570reg.h revision 1.3
1 /* $NetBSD: hd64570reg.h,v 1.3 2000/01/04 06:36:29 chopps Exp $ */ 2 3 /* 4 * Copyright (c) 1998 Vixie Enterprises 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of Vixie Enterprises nor the names 17 * of its contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY VIXIE ENTERPRISES AND 21 * CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 22 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL VIXIE ENTERPRISES OR 25 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 29 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * This software has been written for Vixie Enterprises by Michael Graff 35 * <explorer (at) flame.org>. To learn more about Vixie Enterprises, see 36 * ``http://www.vix.com''. 37 */ 38 39 #ifndef _DEV_IC_HD64570REG_H_ 40 #define _DEV_IC_HD64570REG_H_ 41 42 /* XXX 43 * This is really HDLC specific stuff, but... 44 */ 45 #define CISCO_MULTICAST 0x8f /* Cisco multicast address */ 46 #define CISCO_UNICAST 0x0f /* Cisco unicast address */ 47 #define CISCO_KEEPALIVE 0x8035 /* Cisco keepalive protocol */ 48 #define CISCO_ADDR_REQ 0 /* Cisco address request */ 49 #define CISCO_ADDR_REPLY 1 /* Cisco address reply */ 50 #define CISCO_KEEPALIVE_REQ 2 /* Cisco keepalive request */ 51 52 typedef struct cisco_pkt { 53 u_int32_t type; 54 u_int32_t par1; 55 u_int32_t par2; 56 u_int16_t rel; 57 u_int16_t time0; 58 u_int16_t time1; 59 } cisco_pkt_t; 60 #define CISCO_PKT_LEN 18 /* sizeof doesn't work right... */ 61 62 #define HDLC_PROTOCOL_IP 0x0800 /* IP */ 63 64 typedef struct hdlc_header { 65 u_int8_t addr; 66 u_int8_t control; 67 u_int16_t protocol; 68 } hdlc_header_t; 69 #define HDLC_HDRLEN 4 70 71 /* 72 * Hitachi HD64570 defininitions 73 */ 74 75 /* SCA Control Registers */ 76 #define SCA_PABR0 2 77 #define SCA_PABR1 3 78 #define SCA_WCRL 4 /* Wait Control reg */ 79 #define SCA_WCRM 5 /* Wait Control reg */ 80 #define SCA_WCRH 6 /* Wait Control reg */ 81 #define SCA_PCR 8 /* DMA priority control reg */ 82 83 /* Interrupt registers */ 84 #define SCA_ISR0 0x10 /* Interrupt status register 0 */ 85 #define SCA_ISR1 0x11 /* Interrupt status register 1 */ 86 #define SCA_ISR2 0x12 /* Interrupt status register 2 */ 87 #define SCA_IER0 0x14 /* Interrupt enable register 0 */ 88 #define SCA_IER1 0x15 /* Interrupt enable register 1 */ 89 #define SCA_IER2 0x16 /* Interrupt enable register 2 */ 90 #define SCA_ITCR 0x18 /* interrupt control register */ 91 #define SCA_IVR 0x1a /* interrupt vector */ 92 #define SCA_IMVR 0x1c /* modified interrupt vector */ 93 94 /* MSCI Channel 0 Registers */ 95 #define SCA_TRBL0 0x20 /* TX/RX buffer reg */ 96 #define SCA_TRBH0 0x21 /* TX/RX buffer reg */ 97 #define SCA_ST00 0x22 /* Status reg 0 */ 98 #define SCA_ST10 0x23 /* Status reg 1 */ 99 #define SCA_ST20 0x24 /* Status reg 2 */ 100 #define SCA_ST30 0x25 /* Status reg 3 */ 101 #define SCA_FST0 0x26 /* frame Status reg */ 102 #define SCA_IE00 0x28 /* Interrupt enable reg 0 */ 103 #define SCA_IE10 0x29 /* Interrupt enable reg 1 */ 104 #define SCA_IE20 0x2a /* Interrupt enable reg 2 */ 105 #define SCA_FIE0 0x2b /* Frame Interrupt enable reg */ 106 #define SCA_CMD0 0x2c /* Command reg */ 107 #define SCA_MD00 0x2e /* Mode reg 0 */ 108 #define SCA_MD10 0x2f /* Mode reg 1 */ 109 #define SCA_MD20 0x30 /* Mode reg 2 */ 110 #define SCA_CTL0 0x31 /* Control reg */ 111 #define SCA_SA00 0x32 /* Syn Address reg 0 */ 112 #define SCA_SA10 0x33 /* Syn Address reg 1 */ 113 #define SCA_IDL0 0x34 /* Idle register */ 114 #define SCA_TMC0 0x35 /* Time constant */ 115 #define SCA_RXS0 0x36 /* RX clock source */ 116 #define SCA_TXS0 0x37 /* TX clock source */ 117 #define SCA_TRC00 0x38 /* TX Ready control reg 0 */ 118 #define SCA_TRC10 0x39 /* TX Ready control reg 1 */ 119 #define SCA_RRC0 0x3A /* RX Ready control reg */ 120 121 /* MSCI Channel 1 Registers */ 122 #define SCA_TRBL1 0x40 /* TX/RX buffer reg */ 123 #define SCA_TRBH1 0x41 /* TX/RX buffer reg */ 124 #define SCA_ST01 0x42 /* Status reg 0 */ 125 #define SCA_ST11 0x43 /* Status reg 1 */ 126 #define SCA_ST21 0x44 /* Status reg 2 */ 127 #define SCA_ST31 0x45 /* Status reg 3 */ 128 #define SCA_FST1 0x46 /* Frame Status reg */ 129 #define SCA_IE01 0x48 /* Interrupt enable reg 0 */ 130 #define SCA_IE11 0x49 /* Interrupt enable reg 1 */ 131 #define SCA_IE21 0x4a /* Interrupt enable reg 2 */ 132 #define SCA_FIE1 0x4b /* Frame Interrupt enable reg */ 133 #define SCA_CMD1 0x4c /* Command reg */ 134 #define SCA_MD01 0x4e /* Mode reg 0 */ 135 #define SCA_MD11 0x4f /* Mode reg 1 */ 136 #define SCA_MD21 0x50 /* Mode reg 2 */ 137 #define SCA_CTL1 0x51 /* Control reg */ 138 #define SCA_SA01 0x52 /* Syn Address reg 0 */ 139 #define SCA_SA11 0x53 /* Syn Address reg 1 */ 140 #define SCA_IDL1 0x54 /* Idle register */ 141 #define SCA_TMC1 0x55 /* Time constant */ 142 #define SCA_RXS1 0x56 /* RX clock source */ 143 #define SCA_TXS1 0x57 /* TX clock source */ 144 #define SCA_TRC01 0x58 /* TX Ready control reg 0 */ 145 #define SCA_TRC11 0x59 /* TX Ready control reg 1 */ 146 #define SCA_RRC1 0x5A /* RX Ready control reg */ 147 148 149 /* SCA DMA registers */ 150 151 #define SCA_DMER 0x9 /* DMA Master Enable reg */ 152 153 /* DMA Channel 0 Registers (MSCI -> memory, or rx) */ 154 #define SCA_BARL0 0x80 /* buffer address reg */ 155 #define SCA_BARH0 0x81 /* buffer address reg */ 156 #define SCA_BARB0 0x82 /* buffer address reg */ 157 #define SCA_DARL0 0x80 /* Dest. address reg */ 158 #define SCA_DARH0 0x81 /* Dest. address reg */ 159 #define SCA_DARB0 0x82 /* Dest. address reg */ 160 #define SCA_CPB0 0x86 /* Chain pointer base */ 161 #define SCA_CDAL0 0x88 /* Current descriptor address */ 162 #define SCA_CDAH0 0x89 /* Current descriptor address */ 163 #define SCA_EDAL0 0x8A /* Error descriptor address */ 164 #define SCA_EDAH0 0x8B /* Error descriptor address */ 165 #define SCA_BFLL0 0x8C /* RX buffer length Low */ 166 #define SCA_BFLH0 0x8D /* RX buffer length High */ 167 #define SCA_BCRL0 0x8E /* Byte Count reg */ 168 #define SCA_BCRH0 0x8F /* Byte Count reg */ 169 #define SCA_DSR0 0x90 /* DMA Status reg */ 170 #define SCA_DMR0 0x91 /* DMA Mode reg */ 171 #define SCA_FCT0 0x93 /* Frame end interrupt Counter */ 172 #define SCA_DIR0 0x94 /* DMA interrupt enable */ 173 #define SCA_DCR0 0x95 /* DMA Command reg */ 174 175 /* DMA Channel 1 Registers (memory -> MSCI, or tx) */ 176 #define SCA_BARL1 0xA0 /* buffer address reg */ 177 #define SCA_BARH1 0xA1 /* buffer address reg */ 178 #define SCA_BARB1 0xA2 /* buffer address reg */ 179 #define SCA_SARL1 0xA4 /* Source address reg */ 180 #define SCA_SARH1 0xA5 /* Source address reg */ 181 #define SCA_SARB1 0xA6 /* Source address reg */ 182 #define SCA_CPB1 0xA6 /* Chain pointer base */ 183 #define SCA_CDAL1 0xA8 /* Current descriptor address */ 184 #define SCA_CDAH1 0xA9 /* Current descriptor address */ 185 #define SCA_EDAL1 0xAA /* Error descriptor address */ 186 #define SCA_EDAH1 0xAB /* Error descriptor address */ 187 #define SCA_BCRL1 0xAE /* Byte Count reg */ 188 #define SCA_BCRH1 0xAF /* Byte Count reg */ 189 #define SCA_DSR1 0xB0 /* DMA Status reg */ 190 #define SCA_DMR1 0xB1 /* DMA Mode reg */ 191 #define SCA_FCT1 0xB3 /* Frame end interrupt Counter */ 192 #define SCA_DIR1 0xB4 /* DMA interrupt enable */ 193 #define SCA_DCR1 0xB5 /* DMA Command reg */ 194 195 /* DMA Channel 2 Registers (MSCI -> memory) */ 196 #define SCA_BARL2 0xC0 /* buffer address reg */ 197 #define SCA_BARH2 0xC1 /* buffer address reg */ 198 #define SCA_BARB2 0xC2 /* buffer address reg */ 199 #define SCA_CDAL2 0xC8 200 #define SCA_DSR2 0xD0 /* DMA Status reg */ 201 202 /* DMA Channel 3 Registers (memory -> MSCI) */ 203 #define SCA_BARL3 0xE0 /* buffer address reg */ 204 #define SCA_BARH3 0xE1 /* buffer address reg */ 205 #define SCA_BARB3 0xE2 /* buffer address reg */ 206 #define SCA_CDAL3 0xE8 207 #define SCA_DSR3 0xF0 /* DMA Status reg */ 208 209 /* 210 * Timer Registers 211 */ 212 213 /* Timer up-counter */ 214 #define SCA_TCNTL0 0x60 /* channel 0 */ 215 #define SCA_TCNTH0 0x61 /* channel 0 */ 216 #define SCA_TCNTL1 0x68 /* channel 1 */ 217 #define SCA_TCNTH1 0x69 /* channel 1 */ 218 #define SCA_TCNTL2 0x70 /* channel 2 */ 219 #define SCA_TCNTH2 0x71 /* channel 2 */ 220 #define SCA_TCNTL3 0x78 /* channel 3 */ 221 #define SCA_TCNTH3 0x79 /* channel 3 */ 222 223 /* Timer constant register */ 224 #define SCA_TCONRL0 0x62 /* channel 0 */ 225 #define SCA_TCONRH0 0x63 /* channel 0 */ 226 #define SCA_TCONRL1 0x6a /* channel 1 */ 227 #define SCA_TCONRH1 0x6b /* channel 1 */ 228 #define SCA_TCONRL2 0x72 /* channel 2 */ 229 #define SCA_TCONRH2 0x73 /* channel 2 */ 230 #define SCA_TCONRL3 0x7a /* channel 3 */ 231 #define SCA_TCONRH3 0x7b /* channel 3 */ 232 233 /* Timer control/status register */ 234 #define SCA_TCSR0 0x64 /* channel 0 */ 235 #define SCA_TCSR1 0x6c /* channel 1 */ 236 #define SCA_TCSR2 0x74 /* channel 2 */ 237 #define SCA_TCSR3 0x7c /* channel 3 */ 238 239 /* Timer expand prescale register */ 240 #define SCA_TEPR0 0x65 /* channel 0 */ 241 #define SCA_TEPR1 0x6d /* channel 1 */ 242 #define SCA_TEPR2 0x75 /* channel 2 */ 243 #define SCA_TEPR3 0x7d /* channel 3 */ 244 245 /* 246 * SCA HD64570 Register Definitions 247 */ 248 249 #define ST3_CTS 8 /* modem input /CTS bit */ 250 #define ST3_DCD 4 /* modem input /DCD bit */ 251 252 /* 253 * SCA commands 254 */ 255 #define SCA_CMD_TXRESET 0x01 256 #define SCA_CMD_TXENABLE 0x02 257 #define SCA_CMD_TXDISABLE 0x03 258 #define SCA_CMD_TXCRCINIT 0x04 259 #define SCA_CMD_TXCRCEXCL 0x05 260 #define SCA_CMS_TXEOM 0x06 261 #define SCA_CMD_TXABORT 0x07 262 #define SCA_CMD_MPON 0x08 263 #define SCA_CMD_TXBCLEAR 0x09 264 265 #define SCA_CMD_RXRESET 0x11 266 #define SCA_CMD_RXENABLE 0x12 267 #define SCA_CMD_RXDISABLE 0x13 268 #define SCA_CMD_RXCRCINIT 0x14 269 #define SCA_CMD_RXMSGREJ 0x15 270 #define SCA_CMD_MPSEARCH 0x16 271 #define SCA_CMD_RXCRCEXCL 0x17 272 #define SCA_CMD_RXCRCCALC 0x18 273 274 #define SCA_CMD_NOP 0x00 275 #define SCA_CMD_RESET 0x21 276 #define SCA_CMD_SEARCH 0x31 277 278 #define SCA_MD0_CRC_1 0x01 279 #define SCA_MD0_CRC_CCITT 0x02 280 #define SCA_MD0_CRC_ENABLE 0x04 281 #define SCA_MD0_AUTO_ENABLE 0x10 282 #define SCA_MD0_MODE_ASYNC 0x00 283 #define SCA_MD0_MODE_BYTESYNC1 0x20 284 #define SCA_MD0_MODE_BISYNC 0x40 285 #define SCA_MD0_MODE_BYTESYNC2 0x60 286 #define SCA_MD0_MODE_HDLC 0x80 287 288 #define SCA_MD1_NOADDRCHK 0x00 289 #define SCA_MD1_SNGLADDR1 0x40 290 #define SCA_MD1_SNGLADDR2 0x80 291 #define SCA_MD1_DUALADDR 0xC0 292 293 #define SCA_MD2_DUPLEX 0x00 294 #define SCA_MD2_ECHO 0x01 295 #define SCA_MD2_LOOPBACK 0x03 296 #define SCA_MD2_ADPLLx8 0x00 297 #define SCA_MD2_ADPLLx16 0x08 298 #define SCA_MD2_ADPLLx32 0x10 299 #define SCA_MD2_NRZ 0x00 300 #define SCA_MD2_NRZI 0x20 301 #define SCA_MD2_MANCHESTER 0x80 302 #define SCA_MD2_FM0 0xC0 303 #define SCA_MD2_FM1 0xA0 304 305 #define SCA_CTL_RTS_MASK 0x01 /* control state of RTS */ 306 #define SCA_CTL_RTS_HIGH 0x00 /* raise RTS (low !RTS) */ 307 #define SCA_CTL_RTS_LOW 0x01 /* lower RTS (raise !RTS) */ 308 #define SCA_CTL_IDLC_MASK 0x10 /* control idle state */ 309 #define SCA_CTL_IDLC_MARK 0x00 /* transmit mark in idle state */ 310 #define SCA_CTL_IDLC_PATTERN 0x10 /* tranmist idle pattern */ 311 #define SCA_CTL_UDRNC_MASK 0x20 /* control underun state */ 312 #define SCA_CTL_UDRNC_AFTER_ABORT 0x00 /* idle after aborting trans */ 313 #define SCA_CTL_UDRNC_AFTER_FCS 0x20 /* idle after FCS and flag trans */ 314 315 #define SCA_RXS_DIV_MASK 0x0F /* BRG divisor is 2^(value) */ 316 #define SCA_RXS_DIV_1 0x00 /* 1 */ 317 #define SCA_RXS_DIV_2 0x01 /* 2 */ 318 #define SCA_RXS_DIV_4 0x02 /* 4 */ 319 #define SCA_RXS_DIV_8 0x03 /* 8 */ 320 #define SCA_RXS_DIV_16 0x04 /* 16 */ 321 #define SCA_RXS_DIV_32 0x05 /* 32 */ 322 #define SCA_RXS_DIV_64 0x06 /* 64 */ 323 #define SCA_RXS_DIV_128 0x07 /* 128 */ 324 #define SCA_RXS_DIV_256 0x08 /* 256 */ 325 #define SCA_RXS_DIV_512 0x09 /* 512 */ 326 #define SCA_RXS_CLK_MASK 0x70 /* which clock source */ 327 #define SCA_RXS_CLK_LINE 0x00 /* RXC line input */ 328 #define SCA_RXS_CLK_LINE_SN 0x20 /* RXC line with noise suppression */ 329 #define SCA_RXS_CLK_INTERNAL 0x40 /* Baud Rate Gen. output */ 330 #define SCA_RXS_CLK_ADPLL_OUT 0x60 /* BRG out for ADPLL clock */ 331 #define SCA_RXS_CLK_ADPLL_IN 0x70 /* line input for ADPLL clock */ 332 333 #define SCA_TXS_DIV_MASK 0x0F /* BRG divisor is 2^(valud) */ 334 #define SCA_TXS_DIV_1 0x00 /* 1 */ 335 #define SCA_TXS_DIV_2 0x01 /* 2 */ 336 #define SCA_TXS_DIV_4 0x02 /* 4 */ 337 #define SCA_TXS_DIV_8 0x03 /* 8 */ 338 #define SCA_TXS_DIV_16 0x04 /* 16 */ 339 #define SCA_TXS_DIV_32 0x05 /* 32 */ 340 #define SCA_TXS_DIV_64 0x06 /* 64 */ 341 #define SCA_TXS_DIV_128 0x07 /* 128 */ 342 #define SCA_TXS_DIV_256 0x08 /* 256 */ 343 #define SCA_TXS_DIV_512 0x09 /* 512 */ 344 #define SCA_TXS_CLK_MASK 0x70 /* which clock source */ 345 #define SCA_TXS_CLK_LINE 0x00 /* TXC line input */ 346 #define SCA_TXS_CLK_INTERNAL 0x40 /* Baud Rate Gen. output */ 347 #define SCA_TXS_CLK_RXCLK 0x60 /* Recieve clock */ 348 349 #define SCA_ST0_RXRDY 0x01 350 #define SCA_ST0_TXRDY 0x02 351 #define SCA_ST0_RXINT 0x40 352 #define SCA_ST0_TXINT 0x80 353 354 #define SCA_ST1_IDLST 0x01 355 #define SCA_ST1_ABTST 0x02 356 #define SCA_ST1_DCDCHG 0x04 357 #define SCA_ST1_CTSCHG 0x08 358 #define SCA_ST1_FLAG 0x10 359 #define SCA_ST1_TXIDL 0x40 360 #define SCA_ST1_UDRN 0x80 361 362 /* ST2 and FST look the same */ 363 #define SCA_FST_CRCERR 0x04 364 #define SCA_FST_OVRN 0x08 365 #define SCA_FST_RESFRM 0x10 366 #define SCA_FST_ABRT 0x20 367 #define SCA_FST_SHRT 0x40 368 #define SCA_FST_EOM 0x80 369 370 #define SCA_ST3_RXENA 0x01 371 #define SCA_ST3_TXENA 0x02 372 #define SCA_ST3_DCD 0x04 373 #define SCA_ST3_CTS 0x08 374 #define SCA_ST3_ADPLLSRCH 0x10 375 #define SCA_ST3_TXDATA 0x20 376 377 #define SCA_FIE_EOMFE 0x80 378 379 #define SCA_IE0_RXRDY 0x01 380 #define SCA_IE0_TXRDY 0x02 381 #define SCA_IE0_RXINT 0x40 382 #define SCA_IE0_TXINT 0x80 383 384 #define SCA_IE1_IDLDE 0x01 385 #define SCA_IE1_ABTDE 0x02 386 #define SCA_IE1_DCD 0x04 387 #define SCA_IE1_CTS 0x08 388 #define SCA_IE1_FLAG 0x10 389 #define SCA_IE1_IDL 0x40 390 #define SCA_IE1_UDRN 0x80 391 392 #define SCA_IE2_CRCERR 0x04 393 #define SCA_IE2_OVRN 0x08 394 #define SCA_IE2_RESFRM 0x10 395 #define SCA_IE2_ABRT 0x20 396 #define SCA_IE2_SHRT 0x40 397 #define SCA_IE2_EOM 0x80 398 399 400 /* 401 * Interrupt status register bits 402 */ 403 #define SCA_ISR0_MSCI_RXRDY0 0x01 /* rx ready port 0 int */ 404 #define SCA_ISR0_MSCI_TXRDY0 0x02 /* tx ready port 0 int */ 405 #define SCA_ISR0_MSCI_RXINT0 0x04 /* rx error port 0 int */ 406 #define SCA_ISR0_MSCI_TXINT0 0x08 /* tx error port 0 int */ 407 #define SCA_ISR0_MSCI_RXRDY1 0x10 /* rx ready port 1 int */ 408 #define SCA_ISR0_MSCI_TXRDY1 0x20 /* tx ready port 1 int */ 409 #define SCA_ISR0_MSCI_RXINT1 0x40 /* rx error port 1 int */ 410 #define SCA_ISR0_MSCI_TXINT1 0x80 /* tx error port 1 int */ 411 412 #define SCA_ISR1_DMAC_RX0A 0x01 /* dmac channel 0 int a */ 413 #define SCA_ISR1_DMAC_RX0B 0x02 /* dmac channel 0 int b */ 414 #define SCA_ISR1_DMAC_TX0A 0x04 /* dmac channel 1 int a */ 415 #define SCA_ISR1_DMAC_TX0B 0x08 /* dmac channel 1 int b */ 416 #define SCA_ISR1_DMAC_RX1A 0x10 /* dmac channel 2 int a */ 417 #define SCA_ISR1_DMAC_RX1B 0x20 /* dmac channel 2 int b */ 418 #define SCA_ISR1_DMAC_TX1A 0x40 /* dmac channel 3 int a */ 419 #define SCA_ISR1_DMAC_TX1B 0x80 /* dmac channel 3 int b */ 420 421 #define SCA_ISR2_TIMER_IRQ0 0x10 /* timer channel 0 int */ 422 #define SCA_ISR2_TIMER_IRQ1 0x20 /* timer channel 1 int */ 423 #define SCA_ISR2_TIMER_IRQ2 0x40 /* timer channel 2 int */ 424 #define SCA_ISR2_TIMER_IRQ3 0x80 /* timer channel 3 int */ 425 426 /* masks/values for the Interrupt Control Register (ITCR) */ 427 #define SCA_ITCR_INTR_PRI_MASK 0x80 /* priority of intrerrupts */ 428 #define SCA_ITCR_INTR_PRI_MSCI 0x00 /* msci over dmac */ 429 #define SCA_ITCR_INTR_PRI_DMAC 0x80 /* dmac over msci */ 430 #define SCA_ITCR_ACK_MASK 0x60 /* mask for intr ack cycle setting */ 431 #define SCA_ITCR_ACK_NONE 0x00 /* no intr ack cycle */ 432 #define SCA_ITCR_ACK_SINGLE 0x20 /* single intr ack cycle */ 433 #define SCA_ITCR_ACK_DOUBLE 0x40 /* double intr ack cycle */ 434 #define SCA_ITCR_ACK_RESV 0x60 /* reserverd */ 435 #define SCA_ITCR_VOUT_MASK 0x10 /* vector output */ 436 #define SCA_ITCR_VOUT_IVR 0x00 /* use IVR */ 437 #define SCA_ITCR_VOUT_IMVR 0x10 /* use IMVR */ 438 439 /* 440 * Interrupt enable register bits 441 */ 442 #define SCA_IER0_MSCI_RXRDY0 0x01 /* enable rx ready port 0 int */ 443 #define SCA_IER0_MSCI_TXRDY0 0x02 /* enable tx ready port 0 int */ 444 #define SCA_IER0_MSCI_RXINT0 0x04 /* enable rx error port 0 int */ 445 #define SCA_IER0_MSCI_TXINT0 0x08 /* enable tx error port 0 int */ 446 #define SCA_IER0_MSCI_RXRDY1 0x10 /* enable rx ready port 1 int */ 447 #define SCA_IER0_MSCI_TXRDY1 0x20 /* enable tx ready port 1 int */ 448 #define SCA_IER0_MSCI_RXINT1 0x40 /* enable rx error port 1 int */ 449 #define SCA_IER0_MSCI_TXINT1 0x80 /* enable tx error port 1 int */ 450 451 #define SCA_IER1_DMAC_RX0A 0x01 /* enable dmac channel 0 int a */ 452 #define SCA_IER1_DMAC_RX0B 0x02 /* enable dmac channel 0 int b */ 453 #define SCA_IER1_DMAC_TX0A 0x04 /* enable dmac channel 1 int a */ 454 #define SCA_IER1_DMAC_TX0B 0x08 /* enable dmac channel 1 int b */ 455 #define SCA_IER1_DMAC_RX1A 0x10 /* enable dmac channel 2 int a */ 456 #define SCA_IER1_DMAC_RX1B 0x20 /* enable dmac channel 2 int b */ 457 #define SCA_IER1_DMAC_TX1A 0x40 /* enable dmac channel 3 int a */ 458 #define SCA_IER1_DMAC_TX1B 0x80 /* enable dmac channel 3 int b */ 459 460 #define SCA_IER2_TIMER_IRQ0 0x10 /* enable timer channel 0 int */ 461 #define SCA_IER2_TIMER_IRQ1 0x20 /* enable timer channel 1 int */ 462 #define SCA_IER2_TIMER_IRQ2 0x40 /* enable timer channel 2 int */ 463 #define SCA_IER2_TIMER_IRQ3 0x80 /* enable timer channel 3 int */ 464 465 /* This is for RRC, TRC0 and TRC1. */ 466 #define SCA_RCR_MASK 0x1F 467 468 #define SCA_IE1_ 469 470 #define SCA_IV_CHAN0 0x00 471 #define SCA_IV_CHAN1 0x20 472 473 #define SCA_IV_RXRDY 0x04 474 #define SCA_IV_TXRDY 0x06 475 #define SCA_IV_RXINT 0x08 476 #define SCA_IV_TXINT 0x0A 477 478 #define SCA_IV_DMACH0 0x00 479 #define SCA_IV_DMACH1 0x08 480 #define SCA_IV_DMACH2 0x20 481 #define SCA_IV_DMACH3 0x28 482 483 #define SCA_IV_DMIA 0x14 484 #define SCA_IV_DMIB 0x16 485 486 #define SCA_IV_TIMER0 0x1C 487 #define SCA_IV_TIMER1 0x1E 488 #define SCA_IV_TIMER2 0x3C 489 #define SCA_IV_TIMER3 0x3E 490 491 /* 492 * DMA registers 493 */ 494 #define SCA_DSR_EOT 0x80 495 #define SCA_DSR_EOM 0x40 496 #define SCA_DSR_BOF 0x20 497 #define SCA_DSR_COF 0x10 498 #define SCA_DSR_DE 0x02 499 #define SCA_DSR_DEWD 0x01 /* write DISABLE DE bit */ 500 501 #define SCA_DMR_TMOD 0x10 502 #define SCA_DMR_NF 0x04 503 #define SCA_DMR_CNTE 0x02 504 505 #define SCA_DMER_EN 0x80 506 507 #define SCA_DCR_ABRT 0x01 508 #define SCA_DCR_FCCLR 0x02 /* Clear frame end intr counter */ 509 510 #define SCA_DIR_EOT 0x80 511 #define SCA_DIR_EOM 0x40 512 #define SCA_DIR_BOF 0x20 513 #define SCA_DIR_COF 0x10 514 515 #define SCA_PCR_BRC 0x10 516 #define SCA_PCR_CCC 0x08 517 #define SCA_PCR_PR2 0x04 518 #define SCA_PCR_PR1 0x02 519 #define SCA_PCR_PR0 0x01 520 521 /* 522 * Descriptor Status byte bit definitions: 523 * 524 * Bit Receive Status Transmit Status 525 * ------------------------------------------------- 526 * 7 EOM EOM 527 * 6 Short Frame ... 528 * 5 Abort ... 529 * 4 Residual bit ... 530 * 3 Overrun ... 531 * 2 CRC ... 532 * 1 ... ... 533 * 0 ... EOT 534 * ------------------------------------------------- 535 */ 536 537 #define ST_EOM 0x80 /* End of frame */ 538 #define ST_SHRT 0x40 /* Short frame */ 539 #define ST_ABT 0x20 /* Abort detected */ 540 #define ST_RBIT 0x10 /* Residual bit detected */ 541 #define ST_OVRN 0x8 /* Overrun error */ 542 #define ST_CRCE 0x4 /* CRC Error */ 543 #define ST_OVFL 0x1 /* Buffer OverFlow error (software defined) */ 544 545 #define ST_EOT 1 /* End of transmit command */ 546 547 548 /* DMA Status register (DSR) bit definitions */ 549 #define DSR_EOT 0x80 /* end of transfer EOT bit */ 550 #define DSR_EOM 0x40 /* end of frame EOM bit */ 551 #define DSR_BOF 0x20 /* buffer overflow BOF bit */ 552 #define DSR_COF 0x10 /* counter overflow COF bit */ 553 #define DSR_DWE 1 /* write disable DWE bit */ 554 555 /* MSCI Status register 0 bits */ 556 557 #define RXRDY_BIT 1 /* RX ready */ 558 #define TXRDY_BIT 2 /* TX ready */ 559 560 #define ST3_CTS 8 /* modem input /CTS bit */ 561 #define ST3_DCD 4 /* modem input /DCD bit */ 562 563 /* 564 * timer register values 565 */ 566 #define SCA_TCSR_TME 0x10 /* timer enable */ 567 #define SCA_TCSR_ECMI 0x40 /* interrupt enable */ 568 #define SCA_TCSR_CMF 0x80 /* timer complete */ 569 570 #define SCA_TEPR_DIV_1 0x00 /* 2^(n) prescale divisor */ 571 #define SCA_TEPR_DIV_2 0x01 572 #define SCA_TEPR_DIV_4 0x02 573 #define SCA_TEPR_DIV_8 0x03 574 #define SCA_TEPR_DIV_16 0x04 575 #define SCA_TEPR_DIV_32 0x05 576 #define SCA_TEPR_DIV_64 0x06 577 #define SCA_TEPR_DIV_128 0x06 578 579 580 /* TX and RX Clock Source */ 581 #define CLK_LINE 0x00 /* TX/RX line input */ 582 #define CLK_BRG 0x40 /* internal baud rate generator */ 583 #define CLK_RXC 0x60 /* receive clock */ 584 585 /* Clocking options */ 586 #define CLK_INT 0 /* Internal - Baud Rate generator output */ 587 #define CLK_EXT 1 /* External - both clocks */ 588 #define CLK_RXCI 2 /* External - Receive Clock only */ 589 #define CLK_EETC 3 /* EETC clock: TX = int. / RX = ext.*/ 590 591 #define SCA_DMAC_OFF_0 0x00 /* offset of DMAC for port 0 */ 592 #define SCA_DMAC_OFF_1 0x40 /* offset of DMAC for port 1 */ 593 #define SCA_MSCI_OFF_0 0x00 /* offset of MSCI for port 0 */ 594 #define SCA_MSCI_OFF_1 0x20 /* offset of MSCI for port 1 */ 595 596 /* 597 * DMA constraints 598 */ 599 #define SCA_DMA_ALIGNMENT (64 * 1024) /* 64 KB alignment */ 600 #define SCA_DMA_BOUNDRY (16 * 1024 * 1024) /* 16 MB region */ 601 602 #endif /* _DEV_IC_HD64570REG_H_ */ 603
Indexes created Tue Sep 30 11:09:46 GMT 2025