dev/ic/hfa3861areg.h

1.2  dyoung /* $NetBSD: hfa3861areg.h,v 1.2 2007/11/16 04:31:34 dyoung Exp $ */
1.2  dyoung /* $Id: hfa3861areg.h,v 1.2 2007/11/16 04:31:34 dyoung Exp $ */
1.2  dyoung /*
1.2  dyoung  * Copyright (c) 2007 David Young.  All rights reserved.
1.2  dyoung  *
1.2  dyoung  * Written by David Young.
1.2  dyoung  *
1.2  dyoung  * Redistribution and use in source and binary forms, with or
1.2  dyoung  * without modification, are permitted provided that the following
1.2  dyoung  * conditions are met:
1.2  dyoung  * 1. Redistributions of source code must retain the above copyright
1.2  dyoung  *    notice, this list of conditions and the following disclaimer.
1.2  dyoung  * 2. Redistributions in binary form must reproduce the above
1.2  dyoung  *    copyright notice, this list of conditions and the following
1.2  dyoung  *    disclaimer in the documentation and/or other materials provided
1.2  dyoung  *    with the distribution.
1.2  dyoung  * 3. David Young's name may not be used to endorse or promote
1.2  dyoung  *    products derived from this software without specific prior
1.2  dyoung  *    written permission.
1.2  dyoung  *
1.2  dyoung  * THIS SOFTWARE IS PROVIDED BY DAVID YOUNG ``AS IS'' AND ANY
1.2  dyoung  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
1.2  dyoung  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
1.2  dyoung  * PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL DAVID
1.2  dyoung  * YOUNG BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
1.2  dyoung  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
1.2  dyoung  * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
1.2  dyoung  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
1.2  dyoung  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
1.2  dyoung  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
1.2  dyoung  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
1.2  dyoung  * OF SUCH DAMAGE.
1.2  dyoung  */
1.1  dyoung #ifndef _DEV_IC_HFA3861A_H_
1.1  dyoung #define _DEV_IC_HFA3861A_H_
1.1  dyoung
1.1  dyoung /* Register set for the Intersil HFA3861A. */
1.1  dyoung
1.1  dyoung #define	HFA3861A_CR49	0x62	/* Read-only register mux control */
1.1  dyoung #define	HFA3861A_CR49_SEL	__BIT(7)	/* 0: read-only register set 'b'
1.1  dyoung 						 * 1: read-only register set 'a'
1.1  dyoung 						 */
1.1  dyoung #define	HFA3861A_CR49_RSVD	__BITS(6, 0)
1.1  dyoung
1.1  dyoung #define	HFA3861A_CR61	0x7c	/* Rx status, read-only, sets 'a' & 'b' */
1.1  dyoung
1.2  dyoung #define	HFA3861A_CR62	0x7e	/* RSSI, read-only */
1.1  dyoung #define	HFA3861A_CR62_RSSI	__BITS(7, 0)	/* RSSI, sets 'a' & 'b' */
1.1  dyoung
1.1  dyoung #define	HFA3861A_CR63	0x80	/* Rx status, read-only */
1.1  dyoung #define	HFA3861A_CR63_SIGNAL	__BITS(7, 6)	/* signal field value,
1.1  dyoung 						 * sets 'a' & 'b' */
1.1  dyoung /* 1 Mbps */
1.1  dyoung #define	HFA3861A_CR63_SIGNAL_1MBPS	__SHIFTIN(0, HFA3861A_CR63_SIGNAL)
1.1  dyoung /* 2 Mbps */
1.1  dyoung #define	HFA3861A_CR63_SIGNAL_2MBPS	__SHIFTIN(2, HFA3861A_CR63_SIGNAL)
1.1  dyoung /* 5.5 or 11 Mbps */
1.1  dyoung #define	HFA3861A_CR63_SIGNAL_OTHER_MBPS	__SHIFTIN(1, HFA3861A_CR63_SIGNAL)
1.1  dyoung #define	HFA3861A_CR63_SFD	__BIT(5)	/* SFD found, sets 'a' & 'b' */
1.1  dyoung #define	HFA3861A_CR63_SHORTPRE	__BIT(4)	/* short preamble detected,
1.1  dyoung 						 * sets 'a' & 'b'
1.1  dyoung 						 */
1.1  dyoung #define	HFA3861A_CR63_SIGNAL_OK	__BIT(3)	/* valid signal field,
1.1  dyoung 						 * sets 'a' & 'b'
1.1  dyoung 						 */
1.1  dyoung #define	HFA3861A_CR63_CRC16_OK	__BIT(2)	/* valid CRC 16,
1.1  dyoung 						 * sets 'a' & 'b'
1.1  dyoung 						 */
1.1  dyoung #define	HFA3861A_CR63_ANTENNA	__BIT(1)	/* antenna used,
1.1  dyoung 						 * sets 'a' & 'b'
1.1  dyoung 						 */
1.1  dyoung #define	HFA3861A_CR63_RSVD	__BIT(0)	/* reserved, sets 'a' & 'b' */
1.1  dyoung
1.1  dyoung #endif /* _DEV_IC_HFA3861A_H_ */