hme.c revision 1.83
1 /* $NetBSD: hme.c,v 1.83 2009/09/19 04:55:45 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * HME Ethernet module driver. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: hme.c,v 1.83 2009/09/19 04:55:45 tsutsui Exp $"); 38 39 /* #define HMEDEBUG */ 40 41 #include "opt_inet.h" 42 #include "bpfilter.h" 43 #include "rnd.h" 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/kernel.h> 48 #include <sys/mbuf.h> 49 #include <sys/syslog.h> 50 #include <sys/socket.h> 51 #include <sys/device.h> 52 #include <sys/malloc.h> 53 #include <sys/ioctl.h> 54 #include <sys/errno.h> 55 #if NRND > 0 56 #include <sys/rnd.h> 57 #endif 58 59 #include <net/if.h> 60 #include <net/if_dl.h> 61 #include <net/if_ether.h> 62 #include <net/if_media.h> 63 64 #ifdef INET 65 #include <net/if_vlanvar.h> 66 #include <netinet/in.h> 67 #include <netinet/if_inarp.h> 68 #include <netinet/in_systm.h> 69 #include <netinet/in_var.h> 70 #include <netinet/ip.h> 71 #include <netinet/tcp.h> 72 #include <netinet/udp.h> 73 #endif 74 75 76 #if NBPFILTER > 0 77 #include <net/bpf.h> 78 #include <net/bpfdesc.h> 79 #endif 80 81 #include <dev/mii/mii.h> 82 #include <dev/mii/miivar.h> 83 84 #include <sys/bus.h> 85 86 #include <dev/ic/hmereg.h> 87 #include <dev/ic/hmevar.h> 88 89 static void hme_start(struct ifnet *); 90 static void hme_stop(struct ifnet *, int); 91 static int hme_ioctl(struct ifnet *, u_long, void *); 92 static void hme_tick(void *); 93 static void hme_watchdog(struct ifnet *); 94 static bool hme_shutdown(device_t, int); 95 static int hme_init(struct hme_softc *); 96 static void hme_meminit(struct hme_softc *); 97 static void hme_mifinit(struct hme_softc *); 98 static void hme_reset(struct hme_softc *); 99 static void hme_chipreset(struct hme_softc *); 100 static void hme_setladrf(struct hme_softc *); 101 102 /* MII methods & callbacks */ 103 static int hme_mii_readreg(device_t, int, int); 104 static void hme_mii_writereg(device_t, int, int, int); 105 static void hme_mii_statchg(device_t); 106 107 static int hme_mediachange(struct ifnet *); 108 109 static struct mbuf *hme_get(struct hme_softc *, int, uint32_t); 110 static int hme_put(struct hme_softc *, int, struct mbuf *); 111 static void hme_read(struct hme_softc *, int, uint32_t); 112 static int hme_eint(struct hme_softc *, u_int); 113 static int hme_rint(struct hme_softc *); 114 static int hme_tint(struct hme_softc *); 115 116 #if 0 117 /* Default buffer copy routines */ 118 static void hme_copytobuf_contig(struct hme_softc *, void *, int, int); 119 static void hme_copyfrombuf_contig(struct hme_softc *, void *, int, int); 120 #endif 121 122 void 123 hme_config(struct hme_softc *sc) 124 { 125 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 126 struct mii_data *mii = &sc->sc_mii; 127 struct mii_softc *child; 128 bus_dma_tag_t dmatag = sc->sc_dmatag; 129 bus_dma_segment_t seg; 130 bus_size_t size; 131 int rseg, error; 132 133 /* 134 * HME common initialization. 135 * 136 * hme_softc fields that must be initialized by the front-end: 137 * 138 * the bus tag: 139 * sc_bustag 140 * 141 * the DMA bus tag: 142 * sc_dmatag 143 * 144 * the bus handles: 145 * sc_seb (Shared Ethernet Block registers) 146 * sc_erx (Receiver Unit registers) 147 * sc_etx (Transmitter Unit registers) 148 * sc_mac (MAC registers) 149 * sc_mif (Management Interface registers) 150 * 151 * the maximum bus burst size: 152 * sc_burst 153 * 154 * (notyet:DMA capable memory for the ring descriptors & packet buffers: 155 * rb_membase, rb_dmabase) 156 * 157 * the local Ethernet address: 158 * sc_enaddr 159 * 160 */ 161 162 /* Make sure the chip is stopped. */ 163 hme_chipreset(sc); 164 165 /* 166 * Allocate descriptors and buffers 167 * XXX - do all this differently.. and more configurably, 168 * eg. use things as `dma_load_mbuf()' on transmit, 169 * and a pool of `EXTMEM' mbufs (with buffers DMA-mapped 170 * all the time) on the receiver side. 171 * 172 * Note: receive buffers must be 64-byte aligned. 173 * Also, apparently, the buffers must extend to a DMA burst 174 * boundary beyond the maximum packet size. 175 */ 176 #define _HME_NDESC 128 177 #define _HME_BUFSZ 1600 178 179 /* Note: the # of descriptors must be a multiple of 16 */ 180 sc->sc_rb.rb_ntbuf = _HME_NDESC; 181 sc->sc_rb.rb_nrbuf = _HME_NDESC; 182 183 /* 184 * Allocate DMA capable memory 185 * Buffer descriptors must be aligned on a 2048 byte boundary; 186 * take this into account when calculating the size. Note that 187 * the maximum number of descriptors (256) occupies 2048 bytes, 188 * so we allocate that much regardless of _HME_NDESC. 189 */ 190 size = 2048 + /* TX descriptors */ 191 2048 + /* RX descriptors */ 192 sc->sc_rb.rb_ntbuf * _HME_BUFSZ + /* TX buffers */ 193 sc->sc_rb.rb_nrbuf * _HME_BUFSZ; /* RX buffers */ 194 195 /* Allocate DMA buffer */ 196 if ((error = bus_dmamem_alloc(dmatag, size, 197 2048, 0, 198 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 199 aprint_error_dev(sc->sc_dev, "DMA buffer alloc error %d\n", 200 error); 201 return; 202 } 203 204 /* Map DMA memory in CPU addressable space */ 205 if ((error = bus_dmamem_map(dmatag, &seg, rseg, size, 206 &sc->sc_rb.rb_membase, 207 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 208 aprint_error_dev(sc->sc_dev, "DMA buffer map error %d\n", 209 error); 210 bus_dmamap_unload(dmatag, sc->sc_dmamap); 211 bus_dmamem_free(dmatag, &seg, rseg); 212 return; 213 } 214 215 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0, 216 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 217 aprint_error_dev(sc->sc_dev, "DMA map create error %d\n", 218 error); 219 return; 220 } 221 222 /* Load the buffer */ 223 if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap, 224 sc->sc_rb.rb_membase, size, NULL, 225 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 226 aprint_error_dev(sc->sc_dev, "DMA buffer map load error %d\n", 227 error); 228 bus_dmamem_free(dmatag, &seg, rseg); 229 return; 230 } 231 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr; 232 233 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 234 ether_sprintf(sc->sc_enaddr)); 235 236 /* Initialize ifnet structure. */ 237 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 238 ifp->if_softc = sc; 239 ifp->if_start = hme_start; 240 ifp->if_stop = hme_stop; 241 ifp->if_ioctl = hme_ioctl; 242 ifp->if_watchdog = hme_watchdog; 243 ifp->if_flags = 244 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 245 sc->sc_if_flags = ifp->if_flags; 246 ifp->if_capabilities |= 247 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 248 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx; 249 IFQ_SET_READY(&ifp->if_snd); 250 251 /* Initialize ifmedia structures and MII info */ 252 mii->mii_ifp = ifp; 253 mii->mii_readreg = hme_mii_readreg; 254 mii->mii_writereg = hme_mii_writereg; 255 mii->mii_statchg = hme_mii_statchg; 256 257 sc->sc_ethercom.ec_mii = mii; 258 ifmedia_init(&mii->mii_media, 0, hme_mediachange, ether_mediastatus); 259 260 hme_mifinit(sc); 261 262 /* 263 * Some HME's have an MII connector, as well as RJ45. Try attaching 264 * the RJ45 (internal) PHY first, so that the MII PHY is always 265 * instance 1. 266 */ 267 mii_attach(sc->sc_dev, mii, 0xffffffff, 268 HME_PHYAD_INTERNAL, MII_OFFSET_ANY, MIIF_FORCEANEG); 269 mii_attach(sc->sc_dev, mii, 0xffffffff, 270 HME_PHYAD_EXTERNAL, MII_OFFSET_ANY, MIIF_FORCEANEG); 271 272 child = LIST_FIRST(&mii->mii_phys); 273 if (child == NULL) { 274 /* No PHY attached */ 275 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 0, NULL); 276 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 277 } else { 278 /* 279 * Walk along the list of attached MII devices and 280 * establish an `MII instance' to `phy number' 281 * mapping. We'll use this mapping in media change 282 * requests to determine which phy to use to program 283 * the MIF configuration register. 284 */ 285 for (; child != NULL; child = LIST_NEXT(child, mii_list)) { 286 /* 287 * Note: we support just two PHYs: the built-in 288 * internal device and an external on the MII 289 * connector. 290 */ 291 if (child->mii_phy > 1 || child->mii_inst > 1) { 292 aprint_error_dev(sc->sc_dev, 293 "cannot accommodate MII device %s" 294 " at phy %d, instance %d\n", 295 device_xname(child->mii_dev), 296 child->mii_phy, child->mii_inst); 297 continue; 298 } 299 300 sc->sc_phys[child->mii_inst] = child->mii_phy; 301 } 302 303 /* 304 * Set the default media to auto negotiation if the phy has 305 * the auto negotiation capability. 306 * XXX; What to do otherwise? 307 */ 308 if (ifmedia_match(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO, 0)) 309 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 310 /* 311 else 312 ifmedia_set(&sc->sc_mii.mii_media, sc->sc_defaultmedia); 313 */ 314 } 315 316 /* claim 802.1q capability */ 317 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 318 319 /* Attach the interface. */ 320 if_attach(ifp); 321 ether_ifattach(ifp, sc->sc_enaddr); 322 323 if (pmf_device_register1(sc->sc_dev, NULL, NULL, hme_shutdown)) 324 pmf_class_network_register(sc->sc_dev, ifp); 325 else 326 aprint_error_dev(sc->sc_dev, 327 "couldn't establish power handler\n"); 328 329 #if NRND > 0 330 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 331 RND_TYPE_NET, 0); 332 #endif 333 334 callout_init(&sc->sc_tick_ch, 0); 335 } 336 337 void 338 hme_tick(void *arg) 339 { 340 struct hme_softc *sc = arg; 341 int s; 342 343 s = splnet(); 344 mii_tick(&sc->sc_mii); 345 splx(s); 346 347 callout_reset(&sc->sc_tick_ch, hz, hme_tick, sc); 348 } 349 350 void 351 hme_reset(struct hme_softc *sc) 352 { 353 int s; 354 355 s = splnet(); 356 (void)hme_init(sc); 357 splx(s); 358 } 359 360 void 361 hme_chipreset(struct hme_softc *sc) 362 { 363 bus_space_tag_t t = sc->sc_bustag; 364 bus_space_handle_t seb = sc->sc_seb; 365 int n; 366 367 /* Mask all interrupts */ 368 bus_space_write_4(t, seb, HME_SEBI_IMASK, 0xffffffff); 369 370 /* Reset transmitter and receiver */ 371 bus_space_write_4(t, seb, HME_SEBI_RESET, 372 (HME_SEB_RESET_ETX | HME_SEB_RESET_ERX)); 373 374 for (n = 0; n < 20; n++) { 375 uint32_t v = bus_space_read_4(t, seb, HME_SEBI_RESET); 376 if ((v & (HME_SEB_RESET_ETX | HME_SEB_RESET_ERX)) == 0) 377 return; 378 DELAY(20); 379 } 380 381 printf("%s: %s: reset failed\n", device_xname(sc->sc_dev), __func__); 382 } 383 384 void 385 hme_stop(struct ifnet *ifp, int disable) 386 { 387 struct hme_softc *sc; 388 389 sc = ifp->if_softc; 390 391 ifp->if_timer = 0; 392 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 393 394 callout_stop(&sc->sc_tick_ch); 395 mii_down(&sc->sc_mii); 396 397 hme_chipreset(sc); 398 } 399 400 void 401 hme_meminit(struct hme_softc *sc) 402 { 403 bus_addr_t txbufdma, rxbufdma; 404 bus_addr_t dma; 405 char *p; 406 unsigned int ntbuf, nrbuf, i; 407 struct hme_ring *hr = &sc->sc_rb; 408 409 p = hr->rb_membase; 410 dma = hr->rb_dmabase; 411 412 ntbuf = hr->rb_ntbuf; 413 nrbuf = hr->rb_nrbuf; 414 415 /* 416 * Allocate transmit descriptors 417 */ 418 hr->rb_txd = p; 419 hr->rb_txddma = dma; 420 p += ntbuf * HME_XD_SIZE; 421 dma += ntbuf * HME_XD_SIZE; 422 /* We have reserved descriptor space until the next 2048 byte boundary.*/ 423 dma = (bus_addr_t)roundup((u_long)dma, 2048); 424 p = (void *)roundup((u_long)p, 2048); 425 426 /* 427 * Allocate receive descriptors 428 */ 429 hr->rb_rxd = p; 430 hr->rb_rxddma = dma; 431 p += nrbuf * HME_XD_SIZE; 432 dma += nrbuf * HME_XD_SIZE; 433 /* Again move forward to the next 2048 byte boundary.*/ 434 dma = (bus_addr_t)roundup((u_long)dma, 2048); 435 p = (void *)roundup((u_long)p, 2048); 436 437 438 /* 439 * Allocate transmit buffers 440 */ 441 hr->rb_txbuf = p; 442 txbufdma = dma; 443 p += ntbuf * _HME_BUFSZ; 444 dma += ntbuf * _HME_BUFSZ; 445 446 /* 447 * Allocate receive buffers 448 */ 449 hr->rb_rxbuf = p; 450 rxbufdma = dma; 451 p += nrbuf * _HME_BUFSZ; 452 dma += nrbuf * _HME_BUFSZ; 453 454 /* 455 * Initialize transmit buffer descriptors 456 */ 457 for (i = 0; i < ntbuf; i++) { 458 HME_XD_SETADDR(sc->sc_pci, hr->rb_txd, i, txbufdma + i * _HME_BUFSZ); 459 HME_XD_SETFLAGS(sc->sc_pci, hr->rb_txd, i, 0); 460 } 461 462 /* 463 * Initialize receive buffer descriptors 464 */ 465 for (i = 0; i < nrbuf; i++) { 466 HME_XD_SETADDR(sc->sc_pci, hr->rb_rxd, i, rxbufdma + i * _HME_BUFSZ); 467 HME_XD_SETFLAGS(sc->sc_pci, hr->rb_rxd, i, 468 HME_XD_OWN | HME_XD_ENCODE_RSIZE(_HME_BUFSZ)); 469 } 470 471 hr->rb_tdhead = hr->rb_tdtail = 0; 472 hr->rb_td_nbusy = 0; 473 hr->rb_rdtail = 0; 474 } 475 476 /* 477 * Initialization of interface; set up initialization block 478 * and transmit/receive descriptor rings. 479 */ 480 int 481 hme_init(struct hme_softc *sc) 482 { 483 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 484 bus_space_tag_t t = sc->sc_bustag; 485 bus_space_handle_t seb = sc->sc_seb; 486 bus_space_handle_t etx = sc->sc_etx; 487 bus_space_handle_t erx = sc->sc_erx; 488 bus_space_handle_t mac = sc->sc_mac; 489 uint8_t *ea; 490 uint32_t v; 491 int rc; 492 493 /* 494 * Initialization sequence. The numbered steps below correspond 495 * to the sequence outlined in section 6.3.5.1 in the Ethernet 496 * Channel Engine manual (part of the PCIO manual). 497 * See also the STP2002-STQ document from Sun Microsystems. 498 */ 499 500 /* step 1 & 2. Reset the Ethernet Channel */ 501 hme_stop(ifp, 0); 502 503 /* Re-initialize the MIF */ 504 hme_mifinit(sc); 505 506 /* Call MI reset function if any */ 507 if (sc->sc_hwreset) 508 (*sc->sc_hwreset)(sc); 509 510 #if 0 511 /* Mask all MIF interrupts, just in case */ 512 bus_space_write_4(t, mif, HME_MIFI_IMASK, 0xffff); 513 #endif 514 515 /* step 3. Setup data structures in host memory */ 516 hme_meminit(sc); 517 518 /* step 4. TX MAC registers & counters */ 519 bus_space_write_4(t, mac, HME_MACI_NCCNT, 0); 520 bus_space_write_4(t, mac, HME_MACI_FCCNT, 0); 521 bus_space_write_4(t, mac, HME_MACI_EXCNT, 0); 522 bus_space_write_4(t, mac, HME_MACI_LTCNT, 0); 523 bus_space_write_4(t, mac, HME_MACI_TXSIZE, 524 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 525 ETHER_VLAN_ENCAP_LEN + ETHER_MAX_LEN : ETHER_MAX_LEN); 526 sc->sc_ec_capenable = sc->sc_ethercom.ec_capenable; 527 528 /* Load station MAC address */ 529 ea = sc->sc_enaddr; 530 bus_space_write_4(t, mac, HME_MACI_MACADDR0, (ea[0] << 8) | ea[1]); 531 bus_space_write_4(t, mac, HME_MACI_MACADDR1, (ea[2] << 8) | ea[3]); 532 bus_space_write_4(t, mac, HME_MACI_MACADDR2, (ea[4] << 8) | ea[5]); 533 534 /* 535 * Init seed for backoff 536 * (source suggested by manual: low 10 bits of MAC address) 537 */ 538 v = ((ea[4] << 8) | ea[5]) & 0x3fff; 539 bus_space_write_4(t, mac, HME_MACI_RANDSEED, v); 540 541 542 /* Note: Accepting power-on default for other MAC registers here.. */ 543 544 545 /* step 5. RX MAC registers & counters */ 546 hme_setladrf(sc); 547 548 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 549 bus_space_write_4(t, etx, HME_ETXI_RING, sc->sc_rb.rb_txddma); 550 bus_space_write_4(t, etx, HME_ETXI_RSIZE, sc->sc_rb.rb_ntbuf); 551 552 bus_space_write_4(t, erx, HME_ERXI_RING, sc->sc_rb.rb_rxddma); 553 bus_space_write_4(t, mac, HME_MACI_RXSIZE, 554 (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 555 ETHER_VLAN_ENCAP_LEN + ETHER_MAX_LEN : ETHER_MAX_LEN); 556 557 /* step 8. Global Configuration & Interrupt Mask */ 558 bus_space_write_4(t, seb, HME_SEBI_IMASK, 559 ~( 560 /*HME_SEB_STAT_GOTFRAME | HME_SEB_STAT_SENTFRAME |*/ 561 HME_SEB_STAT_HOSTTOTX | 562 HME_SEB_STAT_RXTOHOST | 563 HME_SEB_STAT_TXALL | 564 HME_SEB_STAT_TXPERR | 565 HME_SEB_STAT_RCNTEXP | 566 HME_SEB_STAT_MIFIRQ | 567 HME_SEB_STAT_ALL_ERRORS )); 568 569 switch (sc->sc_burst) { 570 default: 571 v = 0; 572 break; 573 case 16: 574 v = HME_SEB_CFG_BURST16; 575 break; 576 case 32: 577 v = HME_SEB_CFG_BURST32; 578 break; 579 case 64: 580 v = HME_SEB_CFG_BURST64; 581 break; 582 } 583 bus_space_write_4(t, seb, HME_SEBI_CFG, v); 584 585 /* step 9. ETX Configuration: use mostly default values */ 586 587 /* Enable DMA */ 588 v = bus_space_read_4(t, etx, HME_ETXI_CFG); 589 v |= HME_ETX_CFG_DMAENABLE; 590 bus_space_write_4(t, etx, HME_ETXI_CFG, v); 591 592 /* Transmit Descriptor ring size: in increments of 16 */ 593 bus_space_write_4(t, etx, HME_ETXI_RSIZE, _HME_NDESC / 16 - 1); 594 595 596 /* step 10. ERX Configuration */ 597 v = bus_space_read_4(t, erx, HME_ERXI_CFG); 598 599 /* Encode Receive Descriptor ring size: four possible values */ 600 switch (_HME_NDESC /*XXX*/) { 601 case 32: 602 v |= HME_ERX_CFG_RINGSIZE32; 603 break; 604 case 64: 605 v |= HME_ERX_CFG_RINGSIZE64; 606 break; 607 case 128: 608 v |= HME_ERX_CFG_RINGSIZE128; 609 break; 610 case 256: 611 v |= HME_ERX_CFG_RINGSIZE256; 612 break; 613 default: 614 printf("hme: invalid Receive Descriptor ring size\n"); 615 break; 616 } 617 618 /* Enable DMA */ 619 v |= HME_ERX_CFG_DMAENABLE; 620 621 /* set h/w rx checksum start offset (# of half-words) */ 622 #ifdef INET 623 v |= (((ETHER_HDR_LEN + sizeof(struct ip)) / sizeof(uint16_t)) 624 << HME_ERX_CFG_CSUMSHIFT) & 625 HME_ERX_CFG_CSUMSTART; 626 #endif 627 bus_space_write_4(t, erx, HME_ERXI_CFG, v); 628 629 /* step 11. XIF Configuration */ 630 v = bus_space_read_4(t, mac, HME_MACI_XIF); 631 v |= HME_MAC_XIF_OE; 632 bus_space_write_4(t, mac, HME_MACI_XIF, v); 633 634 /* step 12. RX_MAC Configuration Register */ 635 v = bus_space_read_4(t, mac, HME_MACI_RXCFG); 636 v |= HME_MAC_RXCFG_ENABLE | HME_MAC_RXCFG_PSTRIP; 637 bus_space_write_4(t, mac, HME_MACI_RXCFG, v); 638 639 /* step 13. TX_MAC Configuration Register */ 640 v = bus_space_read_4(t, mac, HME_MACI_TXCFG); 641 v |= (HME_MAC_TXCFG_ENABLE | HME_MAC_TXCFG_DGIVEUP); 642 bus_space_write_4(t, mac, HME_MACI_TXCFG, v); 643 644 /* step 14. Issue Transmit Pending command */ 645 646 /* Call MI initialization function if any */ 647 if (sc->sc_hwinit) 648 (*sc->sc_hwinit)(sc); 649 650 /* Set the current media. */ 651 if ((rc = hme_mediachange(ifp)) != 0) 652 return rc; 653 654 /* Start the one second timer. */ 655 callout_reset(&sc->sc_tick_ch, hz, hme_tick, sc); 656 657 ifp->if_flags |= IFF_RUNNING; 658 ifp->if_flags &= ~IFF_OACTIVE; 659 sc->sc_if_flags = ifp->if_flags; 660 ifp->if_timer = 0; 661 hme_start(ifp); 662 return 0; 663 } 664 665 /* 666 * Routine to copy from mbuf chain to transmit buffer in 667 * network buffer memory. 668 * Returns the amount of data copied. 669 */ 670 int 671 hme_put(struct hme_softc *sc, int ri, struct mbuf *m) 672 /* ri: Ring index */ 673 { 674 struct mbuf *n; 675 int len, tlen = 0; 676 char *bp; 677 678 bp = (char *)sc->sc_rb.rb_txbuf + (ri % sc->sc_rb.rb_ntbuf) * _HME_BUFSZ; 679 for (; m; m = n) { 680 len = m->m_len; 681 if (len == 0) { 682 MFREE(m, n); 683 continue; 684 } 685 memcpy(bp, mtod(m, void *), len); 686 bp += len; 687 tlen += len; 688 MFREE(m, n); 689 } 690 return (tlen); 691 } 692 693 /* 694 * Pull data off an interface. 695 * Len is length of data, with local net header stripped. 696 * We copy the data into mbufs. When full cluster sized units are present 697 * we copy into clusters. 698 */ 699 struct mbuf * 700 hme_get(struct hme_softc *sc, int ri, uint32_t flags) 701 { 702 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 703 struct mbuf *m, *m0, *newm; 704 char *bp; 705 int len, totlen; 706 #ifdef INET 707 int csum_flags; 708 #endif 709 710 totlen = HME_XD_DECODE_RSIZE(flags); 711 MGETHDR(m0, M_DONTWAIT, MT_DATA); 712 if (m0 == 0) 713 return (0); 714 m0->m_pkthdr.rcvif = ifp; 715 m0->m_pkthdr.len = totlen; 716 len = MHLEN; 717 m = m0; 718 719 bp = (char *)sc->sc_rb.rb_rxbuf + (ri % sc->sc_rb.rb_nrbuf) * _HME_BUFSZ; 720 721 while (totlen > 0) { 722 if (totlen >= MINCLSIZE) { 723 MCLGET(m, M_DONTWAIT); 724 if ((m->m_flags & M_EXT) == 0) 725 goto bad; 726 len = MCLBYTES; 727 } 728 729 if (m == m0) { 730 char *newdata = (char *) 731 ALIGN(m->m_data + sizeof(struct ether_header)) - 732 sizeof(struct ether_header); 733 len -= newdata - m->m_data; 734 m->m_data = newdata; 735 } 736 737 m->m_len = len = min(totlen, len); 738 memcpy(mtod(m, void *), bp, len); 739 bp += len; 740 741 totlen -= len; 742 if (totlen > 0) { 743 MGET(newm, M_DONTWAIT, MT_DATA); 744 if (newm == 0) 745 goto bad; 746 len = MLEN; 747 m = m->m_next = newm; 748 } 749 } 750 751 #ifdef INET 752 /* hardware checksum */ 753 csum_flags = 0; 754 if (ifp->if_csum_flags_rx & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 755 struct ether_header *eh; 756 struct ether_vlan_header *evh; 757 struct ip *ip; 758 struct udphdr *uh; 759 uint16_t *opts; 760 int32_t hlen, pktlen; 761 uint32_t csum_data; 762 763 eh = mtod(m0, struct ether_header *); 764 if (ntohs(eh->ether_type) == ETHERTYPE_IP) { 765 ip = (struct ip *)((char *)eh + ETHER_HDR_LEN); 766 pktlen = m0->m_pkthdr.len - ETHER_HDR_LEN; 767 } else if (ntohs(eh->ether_type) == ETHERTYPE_VLAN) { 768 evh = (struct ether_vlan_header *)eh; 769 if (ntohs(evh->evl_proto != ETHERTYPE_IP)) 770 goto swcsum; 771 ip = (struct ip *)((char *)eh + ETHER_HDR_LEN + 772 ETHER_VLAN_ENCAP_LEN); 773 pktlen = m0->m_pkthdr.len - 774 ETHER_HDR_LEN - ETHER_VLAN_ENCAP_LEN; 775 } else 776 goto swcsum; 777 778 /* IPv4 only */ 779 if (ip->ip_v != IPVERSION) 780 goto swcsum; 781 782 hlen = ip->ip_hl << 2; 783 if (hlen < sizeof(struct ip)) 784 goto swcsum; 785 786 /* 787 * bail if too short, has random trailing garbage, truncated, 788 * fragment, or has ethernet pad. 789 */ 790 if (ntohs(ip->ip_len) < hlen || 791 ntohs(ip->ip_len) != pktlen || 792 (ntohs(ip->ip_off) & (IP_MF | IP_OFFMASK)) != 0) 793 goto swcsum; 794 795 switch (ip->ip_p) { 796 case IPPROTO_TCP: 797 if ((ifp->if_csum_flags_rx & M_CSUM_TCPv4) == 0) 798 goto swcsum; 799 if (pktlen < (hlen + sizeof(struct tcphdr))) 800 goto swcsum; 801 csum_flags = 802 M_CSUM_TCPv4 | M_CSUM_DATA | M_CSUM_NO_PSEUDOHDR; 803 break; 804 case IPPROTO_UDP: 805 if ((ifp->if_csum_flags_rx & M_CSUM_UDPv4) == 0) 806 goto swcsum; 807 if (pktlen < (hlen + sizeof(struct udphdr))) 808 goto swcsum; 809 uh = (struct udphdr *)((char *)ip + hlen); 810 /* no checksum */ 811 if (uh->uh_sum == 0) 812 goto swcsum; 813 csum_flags = 814 M_CSUM_UDPv4 | M_CSUM_DATA | M_CSUM_NO_PSEUDOHDR; 815 break; 816 default: 817 goto swcsum; 818 } 819 820 /* w/ M_CSUM_NO_PSEUDOHDR, the uncomplemented sum is expected */ 821 csum_data = ~flags & HME_XD_RXCKSUM; 822 823 /* 824 * If data offset is different from RX cksum start offset, 825 * we have to deduct them. 826 */ 827 hlen = ((char *)ip + hlen) - 828 ((char *)eh + ETHER_HDR_LEN + sizeof(struct ip)); 829 if (hlen > 1) { 830 uint32_t optsum; 831 832 optsum = 0; 833 opts = (uint16_t *)((char *)eh + 834 ETHER_HDR_LEN + sizeof(struct ip)); 835 836 while (hlen > 1) { 837 optsum += ntohs(*opts++); 838 hlen -= 2; 839 } 840 while (optsum >> 16) 841 optsum = (optsum >> 16) + (optsum & 0xffff); 842 843 /* Deduct the ip opts sum from the hwsum. */ 844 csum_data += (uint16_t)~optsum; 845 846 while (csum_data >> 16) 847 csum_data = 848 (csum_data >> 16) + (csum_data & 0xffff); 849 } 850 m0->m_pkthdr.csum_data = csum_data; 851 } 852 swcsum: 853 m0->m_pkthdr.csum_flags = csum_flags; 854 #endif 855 856 return (m0); 857 858 bad: 859 m_freem(m0); 860 return (0); 861 } 862 863 /* 864 * Pass a packet to the higher levels. 865 */ 866 void 867 hme_read(struct hme_softc *sc, int ix, uint32_t flags) 868 { 869 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 870 struct mbuf *m; 871 int len; 872 873 len = HME_XD_DECODE_RSIZE(flags); 874 if (len <= sizeof(struct ether_header) || 875 len > ((sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU) ? 876 ETHER_VLAN_ENCAP_LEN + ETHERMTU + sizeof(struct ether_header) : 877 ETHERMTU + sizeof(struct ether_header))) { 878 #ifdef HMEDEBUG 879 printf("%s: invalid packet size %d; dropping\n", 880 device_xname(sc->sc_dev), len); 881 #endif 882 ifp->if_ierrors++; 883 return; 884 } 885 886 /* Pull packet off interface. */ 887 m = hme_get(sc, ix, flags); 888 if (m == 0) { 889 ifp->if_ierrors++; 890 return; 891 } 892 893 ifp->if_ipackets++; 894 895 #if NBPFILTER > 0 896 /* 897 * Check if there's a BPF listener on this interface. 898 * If so, hand off the raw packet to BPF. 899 */ 900 if (ifp->if_bpf) 901 bpf_mtap(ifp->if_bpf, m); 902 #endif 903 904 /* Pass the packet up. */ 905 (*ifp->if_input)(ifp, m); 906 } 907 908 void 909 hme_start(struct ifnet *ifp) 910 { 911 struct hme_softc *sc = ifp->if_softc; 912 void *txd = sc->sc_rb.rb_txd; 913 struct mbuf *m; 914 unsigned int txflags; 915 unsigned int ri, len, obusy; 916 unsigned int ntbuf = sc->sc_rb.rb_ntbuf; 917 918 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 919 return; 920 921 ri = sc->sc_rb.rb_tdhead; 922 obusy = sc->sc_rb.rb_td_nbusy; 923 924 for (;;) { 925 IFQ_DEQUEUE(&ifp->if_snd, m); 926 if (m == 0) 927 break; 928 929 #if NBPFILTER > 0 930 /* 931 * If BPF is listening on this interface, let it see the 932 * packet before we commit it to the wire. 933 */ 934 if (ifp->if_bpf) 935 bpf_mtap(ifp->if_bpf, m); 936 #endif 937 938 #ifdef INET 939 /* collect bits for h/w csum, before hme_put frees the mbuf */ 940 if (ifp->if_csum_flags_tx & (M_CSUM_TCPv4 | M_CSUM_UDPv4) && 941 m->m_pkthdr.csum_flags & (M_CSUM_TCPv4 | M_CSUM_UDPv4)) { 942 struct ether_header *eh; 943 uint16_t offset, start; 944 945 eh = mtod(m, struct ether_header *); 946 switch (ntohs(eh->ether_type)) { 947 case ETHERTYPE_IP: 948 start = ETHER_HDR_LEN; 949 break; 950 case ETHERTYPE_VLAN: 951 start = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 952 break; 953 default: 954 /* unsupported, drop it */ 955 m_free(m); 956 continue; 957 } 958 start += M_CSUM_DATA_IPv4_IPHL(m->m_pkthdr.csum_data); 959 offset = M_CSUM_DATA_IPv4_OFFSET(m->m_pkthdr.csum_data) 960 + start; 961 txflags = HME_XD_TXCKSUM | 962 (offset << HME_XD_TXCSSTUFFSHIFT) | 963 (start << HME_XD_TXCSSTARTSHIFT); 964 } else 965 #endif 966 txflags = 0; 967 968 /* 969 * Copy the mbuf chain into the transmit buffer. 970 */ 971 len = hme_put(sc, ri, m); 972 973 /* 974 * Initialize transmit registers and start transmission 975 */ 976 HME_XD_SETFLAGS(sc->sc_pci, txd, ri, 977 HME_XD_OWN | HME_XD_SOP | HME_XD_EOP | 978 HME_XD_ENCODE_TSIZE(len) | txflags); 979 980 /*if (sc->sc_rb.rb_td_nbusy <= 0)*/ 981 bus_space_write_4(sc->sc_bustag, sc->sc_etx, HME_ETXI_PENDING, 982 HME_ETX_TP_DMAWAKEUP); 983 984 if (++ri == ntbuf) 985 ri = 0; 986 987 if (++sc->sc_rb.rb_td_nbusy == ntbuf) { 988 ifp->if_flags |= IFF_OACTIVE; 989 break; 990 } 991 } 992 993 if (obusy != sc->sc_rb.rb_td_nbusy) { 994 sc->sc_rb.rb_tdhead = ri; 995 ifp->if_timer = 5; 996 } 997 } 998 999 /* 1000 * Transmit interrupt. 1001 */ 1002 int 1003 hme_tint(struct hme_softc *sc) 1004 { 1005 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1006 bus_space_tag_t t = sc->sc_bustag; 1007 bus_space_handle_t mac = sc->sc_mac; 1008 unsigned int ri, txflags; 1009 1010 /* 1011 * Unload collision counters 1012 */ 1013 ifp->if_collisions += 1014 bus_space_read_4(t, mac, HME_MACI_NCCNT) + 1015 bus_space_read_4(t, mac, HME_MACI_FCCNT); 1016 ifp->if_oerrors += 1017 bus_space_read_4(t, mac, HME_MACI_EXCNT) + 1018 bus_space_read_4(t, mac, HME_MACI_LTCNT); 1019 1020 /* 1021 * then clear the hardware counters. 1022 */ 1023 bus_space_write_4(t, mac, HME_MACI_NCCNT, 0); 1024 bus_space_write_4(t, mac, HME_MACI_FCCNT, 0); 1025 bus_space_write_4(t, mac, HME_MACI_EXCNT, 0); 1026 bus_space_write_4(t, mac, HME_MACI_LTCNT, 0); 1027 1028 /* Fetch current position in the transmit ring */ 1029 ri = sc->sc_rb.rb_tdtail; 1030 1031 for (;;) { 1032 if (sc->sc_rb.rb_td_nbusy <= 0) 1033 break; 1034 1035 txflags = HME_XD_GETFLAGS(sc->sc_pci, sc->sc_rb.rb_txd, ri); 1036 1037 if (txflags & HME_XD_OWN) 1038 break; 1039 1040 ifp->if_flags &= ~IFF_OACTIVE; 1041 ifp->if_opackets++; 1042 1043 if (++ri == sc->sc_rb.rb_ntbuf) 1044 ri = 0; 1045 1046 --sc->sc_rb.rb_td_nbusy; 1047 } 1048 1049 /* Update ring */ 1050 sc->sc_rb.rb_tdtail = ri; 1051 1052 hme_start(ifp); 1053 1054 if (sc->sc_rb.rb_td_nbusy == 0) 1055 ifp->if_timer = 0; 1056 1057 return (1); 1058 } 1059 1060 /* 1061 * Receive interrupt. 1062 */ 1063 int 1064 hme_rint(struct hme_softc *sc) 1065 { 1066 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1067 bus_space_tag_t t = sc->sc_bustag; 1068 bus_space_handle_t mac = sc->sc_mac; 1069 void *xdr = sc->sc_rb.rb_rxd; 1070 unsigned int nrbuf = sc->sc_rb.rb_nrbuf; 1071 unsigned int ri; 1072 uint32_t flags; 1073 1074 ri = sc->sc_rb.rb_rdtail; 1075 1076 /* 1077 * Process all buffers with valid data. 1078 */ 1079 for (;;) { 1080 flags = HME_XD_GETFLAGS(sc->sc_pci, xdr, ri); 1081 if (flags & HME_XD_OWN) 1082 break; 1083 1084 if (flags & HME_XD_OFL) { 1085 printf("%s: buffer overflow, ri=%d; flags=0x%x\n", 1086 device_xname(sc->sc_dev), ri, flags); 1087 } else 1088 hme_read(sc, ri, flags); 1089 1090 /* This buffer can be used by the hardware again */ 1091 HME_XD_SETFLAGS(sc->sc_pci, xdr, ri, 1092 HME_XD_OWN | HME_XD_ENCODE_RSIZE(_HME_BUFSZ)); 1093 1094 if (++ri == nrbuf) 1095 ri = 0; 1096 } 1097 1098 sc->sc_rb.rb_rdtail = ri; 1099 1100 /* Read error counters ... */ 1101 ifp->if_ierrors += 1102 bus_space_read_4(t, mac, HME_MACI_STAT_LCNT) + 1103 bus_space_read_4(t, mac, HME_MACI_STAT_ACNT) + 1104 bus_space_read_4(t, mac, HME_MACI_STAT_CCNT) + 1105 bus_space_read_4(t, mac, HME_MACI_STAT_CVCNT); 1106 1107 /* ... then clear the hardware counters. */ 1108 bus_space_write_4(t, mac, HME_MACI_STAT_LCNT, 0); 1109 bus_space_write_4(t, mac, HME_MACI_STAT_ACNT, 0); 1110 bus_space_write_4(t, mac, HME_MACI_STAT_CCNT, 0); 1111 bus_space_write_4(t, mac, HME_MACI_STAT_CVCNT, 0); 1112 return (1); 1113 } 1114 1115 int 1116 hme_eint(struct hme_softc *sc, u_int status) 1117 { 1118 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1119 char bits[128]; 1120 1121 if ((status & HME_SEB_STAT_MIFIRQ) != 0) { 1122 bus_space_tag_t t = sc->sc_bustag; 1123 bus_space_handle_t mif = sc->sc_mif; 1124 uint32_t cf, st, sm; 1125 cf = bus_space_read_4(t, mif, HME_MIFI_CFG); 1126 st = bus_space_read_4(t, mif, HME_MIFI_STAT); 1127 sm = bus_space_read_4(t, mif, HME_MIFI_SM); 1128 printf("%s: XXXlink status changed: cfg=%x, stat %x, sm %x\n", 1129 device_xname(sc->sc_dev), cf, st, sm); 1130 return (1); 1131 } 1132 1133 /* Receive error counters rolled over */ 1134 if (status & HME_SEB_STAT_ACNTEXP) 1135 ifp->if_ierrors += 0xff; 1136 if (status & HME_SEB_STAT_CCNTEXP) 1137 ifp->if_ierrors += 0xff; 1138 if (status & HME_SEB_STAT_LCNTEXP) 1139 ifp->if_ierrors += 0xff; 1140 if (status & HME_SEB_STAT_CVCNTEXP) 1141 ifp->if_ierrors += 0xff; 1142 1143 /* RXTERR locks up the interface, so do a reset */ 1144 if (status & HME_SEB_STAT_RXTERR) 1145 hme_reset(sc); 1146 1147 snprintb(bits, sizeof(bits), HME_SEB_STAT_BITS, status); 1148 printf("%s: status=%s\n", device_xname(sc->sc_dev), bits); 1149 1150 return (1); 1151 } 1152 1153 int 1154 hme_intr(void *v) 1155 { 1156 struct hme_softc *sc = v; 1157 bus_space_tag_t t = sc->sc_bustag; 1158 bus_space_handle_t seb = sc->sc_seb; 1159 uint32_t status; 1160 int r = 0; 1161 1162 status = bus_space_read_4(t, seb, HME_SEBI_STAT); 1163 1164 if ((status & HME_SEB_STAT_ALL_ERRORS) != 0) 1165 r |= hme_eint(sc, status); 1166 1167 if ((status & (HME_SEB_STAT_TXALL | HME_SEB_STAT_HOSTTOTX)) != 0) 1168 r |= hme_tint(sc); 1169 1170 if ((status & HME_SEB_STAT_RXTOHOST) != 0) 1171 r |= hme_rint(sc); 1172 1173 #if NRND > 0 1174 rnd_add_uint32(&sc->rnd_source, status); 1175 #endif 1176 1177 return (r); 1178 } 1179 1180 1181 void 1182 hme_watchdog(struct ifnet *ifp) 1183 { 1184 struct hme_softc *sc = ifp->if_softc; 1185 1186 log(LOG_ERR, "%s: device timeout\n", device_xname(sc->sc_dev)); 1187 ++ifp->if_oerrors; 1188 1189 hme_reset(sc); 1190 } 1191 1192 /* 1193 * Initialize the MII Management Interface 1194 */ 1195 void 1196 hme_mifinit(struct hme_softc *sc) 1197 { 1198 bus_space_tag_t t = sc->sc_bustag; 1199 bus_space_handle_t mif = sc->sc_mif; 1200 bus_space_handle_t mac = sc->sc_mac; 1201 int instance, phy; 1202 uint32_t v; 1203 1204 if (sc->sc_mii.mii_media.ifm_cur != NULL) { 1205 instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1206 phy = sc->sc_phys[instance]; 1207 } else 1208 /* No media set yet, pick phy arbitrarily.. */ 1209 phy = HME_PHYAD_EXTERNAL; 1210 1211 /* Configure the MIF in frame mode, no poll, current phy select */ 1212 v = 0; 1213 if (phy == HME_PHYAD_EXTERNAL) 1214 v |= HME_MIF_CFG_PHY; 1215 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1216 1217 /* If an external transceiver is selected, enable its MII drivers */ 1218 v = bus_space_read_4(t, mac, HME_MACI_XIF); 1219 v &= ~HME_MAC_XIF_MIIENABLE; 1220 if (phy == HME_PHYAD_EXTERNAL) 1221 v |= HME_MAC_XIF_MIIENABLE; 1222 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1223 } 1224 1225 /* 1226 * MII interface 1227 */ 1228 static int 1229 hme_mii_readreg(device_t self, int phy, int reg) 1230 { 1231 struct hme_softc *sc = device_private(self); 1232 bus_space_tag_t t = sc->sc_bustag; 1233 bus_space_handle_t mif = sc->sc_mif; 1234 bus_space_handle_t mac = sc->sc_mac; 1235 uint32_t v, xif_cfg, mifi_cfg; 1236 int n; 1237 1238 /* We can at most have two PHYs */ 1239 if (phy != HME_PHYAD_EXTERNAL && phy != HME_PHYAD_INTERNAL) 1240 return (0); 1241 1242 /* Select the desired PHY in the MIF configuration register */ 1243 v = mifi_cfg = bus_space_read_4(t, mif, HME_MIFI_CFG); 1244 v &= ~HME_MIF_CFG_PHY; 1245 if (phy == HME_PHYAD_EXTERNAL) 1246 v |= HME_MIF_CFG_PHY; 1247 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1248 1249 /* Enable MII drivers on external transceiver */ 1250 v = xif_cfg = bus_space_read_4(t, mac, HME_MACI_XIF); 1251 if (phy == HME_PHYAD_EXTERNAL) 1252 v |= HME_MAC_XIF_MIIENABLE; 1253 else 1254 v &= ~HME_MAC_XIF_MIIENABLE; 1255 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1256 1257 #if 0 1258 /* This doesn't work reliably; the MDIO_1 bit is off most of the time */ 1259 /* 1260 * Check whether a transceiver is connected by testing 1261 * the MIF configuration register's MDI_X bits. Note that 1262 * MDI_0 (int) == 0x100 and MDI_1 (ext) == 0x200; see hmereg.h 1263 */ 1264 mif_mdi_bit = 1 << (8 + (1 - phy)); 1265 delay(100); 1266 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1267 if ((v & mif_mdi_bit) == 0) 1268 return (0); 1269 #endif 1270 1271 /* Construct the frame command */ 1272 v = (MII_COMMAND_START << HME_MIF_FO_ST_SHIFT) | 1273 HME_MIF_FO_TAMSB | 1274 (MII_COMMAND_READ << HME_MIF_FO_OPC_SHIFT) | 1275 (phy << HME_MIF_FO_PHYAD_SHIFT) | 1276 (reg << HME_MIF_FO_REGAD_SHIFT); 1277 1278 bus_space_write_4(t, mif, HME_MIFI_FO, v); 1279 for (n = 0; n < 100; n++) { 1280 DELAY(1); 1281 v = bus_space_read_4(t, mif, HME_MIFI_FO); 1282 if (v & HME_MIF_FO_TALSB) { 1283 v &= HME_MIF_FO_DATA; 1284 goto out; 1285 } 1286 } 1287 1288 v = 0; 1289 printf("%s: mii_read timeout\n", device_xname(sc->sc_dev)); 1290 1291 out: 1292 /* Restore MIFI_CFG register */ 1293 bus_space_write_4(t, mif, HME_MIFI_CFG, mifi_cfg); 1294 /* Restore XIF register */ 1295 bus_space_write_4(t, mac, HME_MACI_XIF, xif_cfg); 1296 return (v); 1297 } 1298 1299 static void 1300 hme_mii_writereg(device_t self, int phy, int reg, int val) 1301 { 1302 struct hme_softc *sc = device_private(self); 1303 bus_space_tag_t t = sc->sc_bustag; 1304 bus_space_handle_t mif = sc->sc_mif; 1305 bus_space_handle_t mac = sc->sc_mac; 1306 uint32_t v, xif_cfg, mifi_cfg; 1307 int n; 1308 1309 /* We can at most have two PHYs */ 1310 if (phy != HME_PHYAD_EXTERNAL && phy != HME_PHYAD_INTERNAL) 1311 return; 1312 1313 /* Select the desired PHY in the MIF configuration register */ 1314 v = mifi_cfg = bus_space_read_4(t, mif, HME_MIFI_CFG); 1315 v &= ~HME_MIF_CFG_PHY; 1316 if (phy == HME_PHYAD_EXTERNAL) 1317 v |= HME_MIF_CFG_PHY; 1318 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1319 1320 /* Enable MII drivers on external transceiver */ 1321 v = xif_cfg = bus_space_read_4(t, mac, HME_MACI_XIF); 1322 if (phy == HME_PHYAD_EXTERNAL) 1323 v |= HME_MAC_XIF_MIIENABLE; 1324 else 1325 v &= ~HME_MAC_XIF_MIIENABLE; 1326 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1327 1328 #if 0 1329 /* This doesn't work reliably; the MDIO_1 bit is off most of the time */ 1330 /* 1331 * Check whether a transceiver is connected by testing 1332 * the MIF configuration register's MDI_X bits. Note that 1333 * MDI_0 (int) == 0x100 and MDI_1 (ext) == 0x200; see hmereg.h 1334 */ 1335 mif_mdi_bit = 1 << (8 + (1 - phy)); 1336 delay(100); 1337 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1338 if ((v & mif_mdi_bit) == 0) 1339 return; 1340 #endif 1341 1342 /* Construct the frame command */ 1343 v = (MII_COMMAND_START << HME_MIF_FO_ST_SHIFT) | 1344 HME_MIF_FO_TAMSB | 1345 (MII_COMMAND_WRITE << HME_MIF_FO_OPC_SHIFT) | 1346 (phy << HME_MIF_FO_PHYAD_SHIFT) | 1347 (reg << HME_MIF_FO_REGAD_SHIFT) | 1348 (val & HME_MIF_FO_DATA); 1349 1350 bus_space_write_4(t, mif, HME_MIFI_FO, v); 1351 for (n = 0; n < 100; n++) { 1352 DELAY(1); 1353 v = bus_space_read_4(t, mif, HME_MIFI_FO); 1354 if (v & HME_MIF_FO_TALSB) 1355 goto out; 1356 } 1357 1358 printf("%s: mii_write timeout\n", device_xname(sc->sc_dev)); 1359 out: 1360 /* Restore MIFI_CFG register */ 1361 bus_space_write_4(t, mif, HME_MIFI_CFG, mifi_cfg); 1362 /* Restore XIF register */ 1363 bus_space_write_4(t, mac, HME_MACI_XIF, xif_cfg); 1364 } 1365 1366 static void 1367 hme_mii_statchg(device_t dev) 1368 { 1369 struct hme_softc *sc = device_private(dev); 1370 bus_space_tag_t t = sc->sc_bustag; 1371 bus_space_handle_t mac = sc->sc_mac; 1372 uint32_t v; 1373 1374 #ifdef HMEDEBUG 1375 if (sc->sc_debug) 1376 printf("hme_mii_statchg: status change\n"); 1377 #endif 1378 1379 /* Set the MAC Full Duplex bit appropriately */ 1380 /* Apparently the hme chip is SIMPLEX if working in full duplex mode, 1381 but not otherwise. */ 1382 v = bus_space_read_4(t, mac, HME_MACI_TXCFG); 1383 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) { 1384 v |= HME_MAC_TXCFG_FULLDPLX; 1385 sc->sc_ethercom.ec_if.if_flags |= IFF_SIMPLEX; 1386 } else { 1387 v &= ~HME_MAC_TXCFG_FULLDPLX; 1388 sc->sc_ethercom.ec_if.if_flags &= ~IFF_SIMPLEX; 1389 } 1390 sc->sc_if_flags = sc->sc_ethercom.ec_if.if_flags; 1391 bus_space_write_4(t, mac, HME_MACI_TXCFG, v); 1392 } 1393 1394 int 1395 hme_mediachange(struct ifnet *ifp) 1396 { 1397 struct hme_softc *sc = ifp->if_softc; 1398 bus_space_tag_t t = sc->sc_bustag; 1399 bus_space_handle_t mif = sc->sc_mif; 1400 bus_space_handle_t mac = sc->sc_mac; 1401 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media); 1402 int phy = sc->sc_phys[instance]; 1403 int rc; 1404 uint32_t v; 1405 1406 #ifdef HMEDEBUG 1407 if (sc->sc_debug) 1408 printf("hme_mediachange: phy = %d\n", phy); 1409 #endif 1410 1411 /* Select the current PHY in the MIF configuration register */ 1412 v = bus_space_read_4(t, mif, HME_MIFI_CFG); 1413 v &= ~HME_MIF_CFG_PHY; 1414 if (phy == HME_PHYAD_EXTERNAL) 1415 v |= HME_MIF_CFG_PHY; 1416 bus_space_write_4(t, mif, HME_MIFI_CFG, v); 1417 1418 /* If an external transceiver is selected, enable its MII drivers */ 1419 v = bus_space_read_4(t, mac, HME_MACI_XIF); 1420 v &= ~HME_MAC_XIF_MIIENABLE; 1421 if (phy == HME_PHYAD_EXTERNAL) 1422 v |= HME_MAC_XIF_MIIENABLE; 1423 bus_space_write_4(t, mac, HME_MACI_XIF, v); 1424 1425 if ((rc = mii_mediachg(&sc->sc_mii)) == ENXIO) 1426 return 0; 1427 return rc; 1428 } 1429 1430 /* 1431 * Process an ioctl request. 1432 */ 1433 int 1434 hme_ioctl(struct ifnet *ifp, unsigned long cmd, void *data) 1435 { 1436 struct hme_softc *sc = ifp->if_softc; 1437 struct ifaddr *ifa = (struct ifaddr *)data; 1438 int s, error = 0; 1439 1440 s = splnet(); 1441 1442 switch (cmd) { 1443 1444 case SIOCINITIFADDR: 1445 switch (ifa->ifa_addr->sa_family) { 1446 #ifdef INET 1447 case AF_INET: 1448 if (ifp->if_flags & IFF_UP) 1449 hme_setladrf(sc); 1450 else { 1451 ifp->if_flags |= IFF_UP; 1452 error = hme_init(sc); 1453 } 1454 arp_ifinit(ifp, ifa); 1455 break; 1456 #endif 1457 default: 1458 ifp->if_flags |= IFF_UP; 1459 error = hme_init(sc); 1460 break; 1461 } 1462 break; 1463 1464 case SIOCSIFFLAGS: 1465 #ifdef HMEDEBUG 1466 { 1467 struct ifreq *ifr = data; 1468 sc->sc_debug = 1469 (ifr->ifr_flags & IFF_DEBUG) != 0 ? 1 : 0; 1470 } 1471 #endif 1472 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 1473 break; 1474 1475 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 1476 case IFF_RUNNING: 1477 /* 1478 * If interface is marked down and it is running, then 1479 * stop it. 1480 */ 1481 hme_stop(ifp, 0); 1482 ifp->if_flags &= ~IFF_RUNNING; 1483 break; 1484 case IFF_UP: 1485 /* 1486 * If interface is marked up and it is stopped, then 1487 * start it. 1488 */ 1489 error = hme_init(sc); 1490 break; 1491 case IFF_UP|IFF_RUNNING: 1492 /* 1493 * If setting debug or promiscuous mode, do not reset 1494 * the chip; for everything else, call hme_init() 1495 * which will trigger a reset. 1496 */ 1497 #define RESETIGN (IFF_CANTCHANGE | IFF_DEBUG) 1498 if (ifp->if_flags != sc->sc_if_flags) { 1499 if ((ifp->if_flags & (~RESETIGN)) 1500 == (sc->sc_if_flags & (~RESETIGN))) 1501 hme_setladrf(sc); 1502 else 1503 error = hme_init(sc); 1504 } 1505 #undef RESETIGN 1506 break; 1507 case 0: 1508 break; 1509 } 1510 1511 if (sc->sc_ec_capenable != sc->sc_ethercom.ec_capenable) 1512 error = hme_init(sc); 1513 1514 break; 1515 1516 default: 1517 if ((error = ether_ioctl(ifp, cmd, data)) != ENETRESET) 1518 break; 1519 1520 error = 0; 1521 1522 if (cmd != SIOCADDMULTI && cmd != SIOCDELMULTI) 1523 ; 1524 else if (ifp->if_flags & IFF_RUNNING) { 1525 /* 1526 * Multicast list has changed; set the hardware filter 1527 * accordingly. 1528 */ 1529 hme_setladrf(sc); 1530 } 1531 break; 1532 } 1533 1534 sc->sc_if_flags = ifp->if_flags; 1535 splx(s); 1536 return (error); 1537 } 1538 1539 bool 1540 hme_shutdown(device_t self, int howto) 1541 { 1542 struct hme_softc *sc; 1543 struct ifnet *ifp; 1544 1545 sc = device_private(self); 1546 ifp = &sc->sc_ethercom.ec_if; 1547 hme_stop(ifp, 1); 1548 1549 return true; 1550 } 1551 1552 /* 1553 * Set up the logical address filter. 1554 */ 1555 void 1556 hme_setladrf(struct hme_softc *sc) 1557 { 1558 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1559 struct ether_multi *enm; 1560 struct ether_multistep step; 1561 struct ethercom *ec = &sc->sc_ethercom; 1562 bus_space_tag_t t = sc->sc_bustag; 1563 bus_space_handle_t mac = sc->sc_mac; 1564 uint32_t v; 1565 uint32_t crc; 1566 uint32_t hash[4]; 1567 1568 /* Clear hash table */ 1569 hash[3] = hash[2] = hash[1] = hash[0] = 0; 1570 1571 /* Get current RX configuration */ 1572 v = bus_space_read_4(t, mac, HME_MACI_RXCFG); 1573 1574 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1575 /* Turn on promiscuous mode; turn off the hash filter */ 1576 v |= HME_MAC_RXCFG_PMISC; 1577 v &= ~HME_MAC_RXCFG_HENABLE; 1578 ifp->if_flags |= IFF_ALLMULTI; 1579 goto chipit; 1580 } 1581 1582 /* Turn off promiscuous mode; turn on the hash filter */ 1583 v &= ~HME_MAC_RXCFG_PMISC; 1584 v |= HME_MAC_RXCFG_HENABLE; 1585 1586 /* 1587 * Set up multicast address filter by passing all multicast addresses 1588 * through a crc generator, and then using the high order 6 bits as an 1589 * index into the 64 bit logical address filter. The high order bit 1590 * selects the word, while the rest of the bits select the bit within 1591 * the word. 1592 */ 1593 1594 ETHER_FIRST_MULTI(step, ec, enm); 1595 while (enm != NULL) { 1596 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1597 /* 1598 * We must listen to a range of multicast addresses. 1599 * For now, just accept all multicasts, rather than 1600 * trying to set only those filter bits needed to match 1601 * the range. (At this time, the only use of address 1602 * ranges is for IP multicast routing, for which the 1603 * range is big enough to require all bits set.) 1604 */ 1605 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 1606 ifp->if_flags |= IFF_ALLMULTI; 1607 goto chipit; 1608 } 1609 1610 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 1611 1612 /* Just want the 6 most significant bits. */ 1613 crc >>= 26; 1614 1615 /* Set the corresponding bit in the filter. */ 1616 hash[crc >> 4] |= 1 << (crc & 0xf); 1617 1618 ETHER_NEXT_MULTI(step, enm); 1619 } 1620 1621 ifp->if_flags &= ~IFF_ALLMULTI; 1622 1623 chipit: 1624 /* Now load the hash table into the chip */ 1625 bus_space_write_4(t, mac, HME_MACI_HASHTAB0, hash[0]); 1626 bus_space_write_4(t, mac, HME_MACI_HASHTAB1, hash[1]); 1627 bus_space_write_4(t, mac, HME_MACI_HASHTAB2, hash[2]); 1628 bus_space_write_4(t, mac, HME_MACI_HASHTAB3, hash[3]); 1629 bus_space_write_4(t, mac, HME_MACI_RXCFG, v); 1630 } 1631 1632 /* 1633 * Routines for accessing the transmit and receive buffers. 1634 * The various CPU and adapter configurations supported by this 1635 * driver require three different access methods for buffers 1636 * and descriptors: 1637 * (1) contig (contiguous data; no padding), 1638 * (2) gap2 (two bytes of data followed by two bytes of padding), 1639 * (3) gap16 (16 bytes of data followed by 16 bytes of padding). 1640 */ 1641 1642 #if 0 1643 /* 1644 * contig: contiguous data with no padding. 1645 * 1646 * Buffers may have any alignment. 1647 */ 1648 1649 void 1650 hme_copytobuf_contig(struct hme_softc *sc, void *from, int ri, int len) 1651 { 1652 volatile void *buf = sc->sc_rb.rb_txbuf + (ri * _HME_BUFSZ); 1653 1654 /* 1655 * Just call memcpy() to do the work. 1656 */ 1657 memcpy(buf, from, len); 1658 } 1659 1660 void 1661 hme_copyfrombuf_contig(struct hme_softc *sc, void *to, int boff, int len) 1662 { 1663 volatile void *buf = sc->sc_rb.rb_rxbuf + (ri * _HME_BUFSZ); 1664 1665 /* 1666 * Just call memcpy() to do the work. 1667 */ 1668 memcpy(to, buf, len); 1669 } 1670 #endif 1671
Indexes created Sun Sep 28 16:09:52 GMT 2025