i128reg.h revision 1.1
1 /* $NetBSD: i128reg.h,v 1.1 2007/08/26 00:34:34 macallan Exp $ */ 2 3 /*- 4 * Copyright (c) 2007 Michael Lorenz 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of The NetBSD Foundation nor the names of its 16 * contributors may be used to endorse or promote products derived 17 * from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: i128reg.h,v 1.1 2007/08/26 00:34:34 macallan Exp $"); 34 35 /* 36 * register definition for Number Nine Imagine 128 graphics controllers 37 * 38 * adapted from XFree86's i128 driver source 39 */ 40 41 #ifndef I128REG_H 42 #define I128REG_H 43 44 #define INTP 0x4000 45 #define INTP_DD_INT 0x01 /* drawing op completed */ 46 #define INTP_CL_INT 0x02 47 #define INTM 0x4004 48 #define INTM_DD_MSK 0x01 49 #define INTM_CL_MSK 0x02 50 #define FLOW 0x4008 51 #define FLOW_DEB 0x01 /* drawing engine busy */ 52 #define FLOW_MCB 0x02 /* mem controller busy */ 53 #define FLOW_CLP 0x04 54 #define FLOW_PRV 0x08 /* prev cmd still running or cache ready */ 55 #define BUSY 0x400C 56 #define BUSY_BUSY 0x01 /* command pipeline busy */ 57 #define XYW_AD 0x4010 58 #define Z_CTRL 0x4018 59 #define BUF_CTRL 0x4020 60 #define BC_AMV 0x02 61 #define BC_MP 0x04 62 #define BC_AMD 0x08 63 #define BC_SEN_MSK 0x0300 64 #define BC_SEN_DB 0x0000 65 #define BC_SEN_VB 0x0100 66 #define BC_SEN_MB 0x0200 67 #define BC_SEN_CB 0x0300 68 #define BC_DEN_MSK 0x0C00 69 #define BC_DEN_DB 0x0000 70 #define BC_DEN_VB 0x0400 71 #define BC_DEN_MB 0x0800 72 #define BC_DEN_CB 0x0C00 73 #define BC_DSE 0x1000 74 #define BC_VSE 0x2000 75 #define BC_MSE 0x4000 76 #define BC_PS_MSK 0x001F0000 77 #define BC_MDM_MSK 0x00600000 78 #define BC_MDM_KEY 0x00200000 79 #define BC_MDM_PLN 0x00400000 80 #define BC_BLK_ENA 0x00800000 81 #define BC_PSIZ_MSK 0x03000000 82 #define BC_PSIZ_8B 0x00000000 83 #define BC_PSIZ_16B 0x01000000 84 #define BC_PSIZ_32B 0x02000000 85 #define BC_PSIZ_NOB 0x03000000 86 #define BC_CO 0x40000000 87 #define BC_CR 0x80000000 88 #define DE_PGE 0x4024 89 #define DP_DVP_MSK 0x0000001F 90 #define DP_MP_MSK 0x000F0000 91 #define DE_SORG 0x4028 92 #define DE_DORG 0x402C 93 #define DE_MSRC 0x4030 94 #define DE_WKEY 0x4038 95 #define DE_KYDAT 0x403C 96 #define DE_ZPTCH 0x403C 97 #define DE_SPTCH 0x4040 98 #define DE_DPTCH 0x4044 99 #define CMD 0x4048 100 #define CMD_OPC_MSK 0x000000FF 101 #define CMD_ROP_MSK 0x0000FF00 102 #define CMD_STL_MSK 0x001F0000 103 #define CMD_CLP_MSK 0x00E00000 104 #define CMD_PAT_MSK 0x0F000000 105 #define CMD_HDF_MSK 0x70000000 106 #define CMD_OPC 0x4050 107 #define CO_NOOP 0x00 108 #define CO_BITBLT 0x01 109 #define CO_LINE 0x02 110 #define CO_ELINE 0x03 111 #define CO_TRIAN 0x04 112 #define CO_RXFER 0x06 113 #define CO_WXFER 0x07 114 #define CMD_ROP 0x4054 115 #define CR_CLEAR 0x00 116 #define CR_NOR 0x01 117 #define CR_AND_INV 0x02 118 #define CR_COPY_INV 0x03 119 #define CR_AND_REV 0x04 120 #define CR_INVERT 0x05 121 #define CR_XOR 0x06 122 #define CR_NAND 0x07 123 #define CR_AND 0x08 124 #define CR_EQUIV 0x09 125 #define CR_NOOP 0x0A 126 #define CR_OR_INV 0x0B 127 #define CR_COPY 0x0C 128 #define CR_OR_REV 0x0D 129 #define CR_OR 0x0E 130 #define CR_SET 0x0F 131 #define CMD_STYLE 0x4058 132 #define CS_SOLID 0x01 133 #define CS_TRNSP 0x02 134 #define CS_STP_NO 0x00 135 #define CS_STP_PL 0x04 136 #define CS_STP_PA32 0x08 137 #define CS_STP_PA8 0x0C 138 #define CS_EDI 0x10 139 #define CMD_PATRN 0x405C 140 #define CP_APAT_NO 0x00 141 #define CP_APAT_8X 0x01 142 #define CP_APAT_32X 0x02 143 #define CP_NLST 0x04 144 #define CP_PRST 0x08 145 #define CMD_CLP 0x4060 146 #define CC_NOCLP 0x00 147 #define CC_CLPRECI 0x02 148 #define CC_CLPRECO 0x03 149 #define CC_CLPSTOP 0x04 150 #define CMD_HDF 0x4064 151 #define CH_BIT_SWP 0x01 152 #define CH_BYT_SWP 0x02 153 #define CH_WRD_SWP 0x04 154 #define FORE 0x4068 155 #define BACK 0x406C 156 #define MASK 0x4070 157 #define RMSK 0x4074 158 #define LPAT 0x4078 159 #define PCTRL 0x407C 160 #define PC_PLEN_MSK 0x0000001F 161 #define PC_PSCL_MSK 0x000000E0 162 #define PC_SPTR_MSK 0x00001F00 163 #define PC_SSCL_MSK 0x0000E000 164 #define PC_STATE_MSK 0xFFFF0000 165 #define CLPTL 0x4080 166 #define CLPTLY_MSK 0x0000FFFF 167 #define CLPTLX_MSK 0xFFFF0000 168 #define CLPBR 0x4084 169 #define CLPBRY_MSK 0x0000FFFF 170 #define CLPBRX_MSK 0xFFFF0000 171 #define XY0_SRC 0x4088 172 #define XY1_DST 0x408C /* trigger */ 173 #define XY2_WH 0x4090 174 #define XY3_DIR 0x4094 175 #define DIR_LR_TB 0x00000000 176 #define DIR_LR_BT 0x00000001 177 #define DIR_RL_TB 0x00000002 178 #define DIR_RL_BT 0x00000003 179 #define DIR_BT 0x00000001 180 #define DIR_RL 0x00000002 181 #define XY4_ZM 0x4098 182 #define ZOOM_NONE 0x00000000 183 #define XY_Y_DATA 0x0000FFFF 184 #define XY_X_DATA 0xFFFF0000 185 #define XY_I_DATA1 0x0000FFFF 186 #define XY_I_DATA2 0xFFFF0000 187 #define DL_ADR 0x40F8 188 #define DL_CNTRL 0x40FC 189 #define ACNTRL 0x416C 190 191 /* wait until the blitter can accept another command */ 192 #define I128_READY(tag, regh) \ 193 do {} while ((bus_space_read_4(tag, regh, BUSY) & BUSY_BUSY) != 0); 194 195 /* wait until it's safe to access video memory */ 196 #define I128_DONE(tag, regh) \ 197 do {} while ((bus_space_read_4(tag, regh, FLOW) & 0x0f) != 0); 198 199 #endif /* I128REG_H */ 200
Indexes created Mon Sep 29 21:09:56 GMT 2025