i82365.c revision 1.72.2.3
1 1.72.2.3 skrll /* $NetBSD: i82365.c,v 1.72.2.3 2004/08/25 06:57:35 skrll Exp $ */ 2 1.72.2.3 skrll 3 1.72.2.3 skrll /* 4 1.72.2.3 skrll * Copyright (c) 2004 Charles M. Hannum. All rights reserved. 5 1.72.2.3 skrll * 6 1.72.2.3 skrll * Redistribution and use in source and binary forms, with or without 7 1.72.2.3 skrll * modification, are permitted provided that the following conditions 8 1.72.2.3 skrll * are met: 9 1.72.2.3 skrll * 1. Redistributions of source code must retain the above copyright 10 1.72.2.3 skrll * notice, this list of conditions and the following disclaimer. 11 1.72.2.3 skrll * 2. Redistributions in binary form must reproduce the above copyright 12 1.72.2.3 skrll * notice, this list of conditions and the following disclaimer in the 13 1.72.2.3 skrll * documentation and/or other materials provided with the distribution. 14 1.72.2.3 skrll * 3. All advertising materials mentioning features or use of this software 15 1.72.2.3 skrll * must display the following acknowledgement: 16 1.72.2.3 skrll * This product includes software developed by Charles M. Hannum. 17 1.72.2.3 skrll * 4. The name of the author may not be used to endorse or promote products 18 1.72.2.3 skrll * derived from this software without specific prior written permission. 19 1.72.2.3 skrll */ 20 1.2 thorpej 21 1.2 thorpej /* 22 1.33 chopps * Copyright (c) 2000 Christian E. Hopps. All rights reserved. 23 1.2 thorpej * Copyright (c) 1997 Marc Horowitz. All rights reserved. 24 1.2 thorpej * 25 1.2 thorpej * Redistribution and use in source and binary forms, with or without 26 1.2 thorpej * modification, are permitted provided that the following conditions 27 1.2 thorpej * are met: 28 1.2 thorpej * 1. Redistributions of source code must retain the above copyright 29 1.2 thorpej * notice, this list of conditions and the following disclaimer. 30 1.2 thorpej * 2. Redistributions in binary form must reproduce the above copyright 31 1.2 thorpej * notice, this list of conditions and the following disclaimer in the 32 1.2 thorpej * documentation and/or other materials provided with the distribution. 33 1.2 thorpej * 3. All advertising materials mentioning features or use of this software 34 1.2 thorpej * must display the following acknowledgement: 35 1.2 thorpej * This product includes software developed by Marc Horowitz. 36 1.2 thorpej * 4. The name of the author may not be used to endorse or promote products 37 1.2 thorpej * derived from this software without specific prior written permission. 38 1.2 thorpej * 39 1.2 thorpej * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 40 1.2 thorpej * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 41 1.2 thorpej * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 42 1.2 thorpej * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 43 1.2 thorpej * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 44 1.2 thorpej * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 45 1.2 thorpej * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 46 1.2 thorpej * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 47 1.2 thorpej * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 48 1.2 thorpej * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 49 1.2 thorpej */ 50 1.63 lukem 51 1.63 lukem #include <sys/cdefs.h> 52 1.72.2.3 skrll __KERNEL_RCSID(0, "$NetBSD: i82365.c,v 1.72.2.3 2004/08/25 06:57:35 skrll Exp $"); 53 1.63 lukem 54 1.63 lukem #define PCICDEBUG 55 1.2 thorpej 56 1.2 thorpej #include <sys/param.h> 57 1.2 thorpej #include <sys/systm.h> 58 1.2 thorpej #include <sys/device.h> 59 1.2 thorpej #include <sys/extent.h> 60 1.20 msaitoh #include <sys/kernel.h> 61 1.2 thorpej #include <sys/malloc.h> 62 1.14 thorpej #include <sys/kthread.h> 63 1.2 thorpej 64 1.2 thorpej #include <machine/bus.h> 65 1.2 thorpej #include <machine/intr.h> 66 1.2 thorpej 67 1.2 thorpej #include <dev/pcmcia/pcmciareg.h> 68 1.2 thorpej #include <dev/pcmcia/pcmciavar.h> 69 1.2 thorpej 70 1.2 thorpej #include <dev/ic/i82365reg.h> 71 1.2 thorpej #include <dev/ic/i82365var.h> 72 1.2 thorpej 73 1.2 thorpej #ifdef PCICDEBUG 74 1.2 thorpej int pcic_debug = 0; 75 1.2 thorpej #define DPRINTF(arg) if (pcic_debug) printf arg; 76 1.2 thorpej #else 77 1.2 thorpej #define DPRINTF(arg) 78 1.2 thorpej #endif 79 1.2 thorpej 80 1.2 thorpej /* 81 1.2 thorpej * Individual drivers will allocate their own memory and io regions. Memory 82 1.2 thorpej * regions must be a multiple of 4k, aligned on a 4k boundary. 83 1.2 thorpej */ 84 1.2 thorpej 85 1.2 thorpej #define PCIC_MEM_ALIGN PCIC_MEM_PAGESIZE 86 1.2 thorpej 87 1.2 thorpej void pcic_attach_socket __P((struct pcic_handle *)); 88 1.33 chopps void pcic_attach_socket_finish __P((struct pcic_handle *)); 89 1.2 thorpej 90 1.2 thorpej int pcic_submatch __P((struct device *, struct cfdata *, void *)); 91 1.2 thorpej int pcic_print __P((void *arg, const char *pnp)); 92 1.2 thorpej int pcic_intr_socket __P((struct pcic_handle *)); 93 1.33 chopps void pcic_poll_intr __P((void *)); 94 1.2 thorpej 95 1.2 thorpej void pcic_attach_card __P((struct pcic_handle *)); 96 1.15 thorpej void pcic_detach_card __P((struct pcic_handle *, int)); 97 1.15 thorpej void pcic_deactivate_card __P((struct pcic_handle *)); 98 1.2 thorpej 99 1.2 thorpej void pcic_chip_do_mem_map __P((struct pcic_handle *, int)); 100 1.2 thorpej void pcic_chip_do_io_map __P((struct pcic_handle *, int)); 101 1.2 thorpej 102 1.14 thorpej void pcic_create_event_thread __P((void *)); 103 1.14 thorpej void pcic_event_thread __P((void *)); 104 1.14 thorpej 105 1.14 thorpej void pcic_queue_event __P((struct pcic_handle *, int)); 106 1.26 sommerfe void pcic_power __P((int, void *)); 107 1.14 thorpej 108 1.72.2.3 skrll static int pcic_wait_ready __P((struct pcic_handle *)); 109 1.30 enami static void pcic_delay __P((struct pcic_handle *, int, const char *)); 110 1.8 marc 111 1.25 haya static u_int8_t st_pcic_read __P((struct pcic_handle *, int)); 112 1.25 haya static void st_pcic_write __P((struct pcic_handle *, int, u_int8_t)); 113 1.25 haya 114 1.2 thorpej int 115 1.2 thorpej pcic_ident_ok(ident) 116 1.2 thorpej int ident; 117 1.2 thorpej { 118 1.2 thorpej /* this is very empirical and heuristic */ 119 1.2 thorpej 120 1.2 thorpej if ((ident == 0) || (ident == 0xff) || (ident & PCIC_IDENT_ZERO)) 121 1.2 thorpej return (0); 122 1.2 thorpej 123 1.72.2.1 skrll if ((ident & PCIC_IDENT_REV_MASK) == 0) 124 1.72.2.1 skrll return (0); 125 1.72.2.1 skrll 126 1.2 thorpej if ((ident & PCIC_IDENT_IFTYPE_MASK) != PCIC_IDENT_IFTYPE_MEM_AND_IO) { 127 1.2 thorpej #ifdef DIAGNOSTIC 128 1.2 thorpej printf("pcic: does not support memory and I/O cards, " 129 1.2 thorpej "ignored (ident=%0x)\n", ident); 130 1.2 thorpej #endif 131 1.2 thorpej return (0); 132 1.2 thorpej } 133 1.72.2.1 skrll 134 1.2 thorpej return (1); 135 1.2 thorpej } 136 1.2 thorpej 137 1.2 thorpej int 138 1.2 thorpej pcic_vendor(h) 139 1.2 thorpej struct pcic_handle *h; 140 1.2 thorpej { 141 1.2 thorpej int reg; 142 1.69 takemura int vendor; 143 1.2 thorpej 144 1.2 thorpej reg = pcic_read(h, PCIC_IDENT); 145 1.2 thorpej 146 1.72.2.1 skrll if ((reg & PCIC_IDENT_REV_MASK) == 0) 147 1.72.2.1 skrll return (PCIC_VENDOR_NONE); 148 1.72.2.1 skrll 149 1.69 takemura switch (reg) { 150 1.72.2.1 skrll case 0x00: 151 1.72.2.1 skrll case 0xff: 152 1.72.2.1 skrll return (PCIC_VENDOR_NONE); 153 1.69 takemura case PCIC_IDENT_ID_INTEL0: 154 1.69 takemura vendor = PCIC_VENDOR_I82365SLR0; 155 1.69 takemura break; 156 1.69 takemura case PCIC_IDENT_ID_INTEL1: 157 1.69 takemura vendor = PCIC_VENDOR_I82365SLR1; 158 1.69 takemura break; 159 1.69 takemura case PCIC_IDENT_ID_INTEL2: 160 1.69 takemura vendor = PCIC_VENDOR_I82365SL_DF; 161 1.69 takemura break; 162 1.69 takemura case PCIC_IDENT_ID_IBM1: 163 1.69 takemura case PCIC_IDENT_ID_IBM2: 164 1.69 takemura vendor = PCIC_VENDOR_IBM; 165 1.69 takemura break; 166 1.69 takemura case PCIC_IDENT_ID_IBM3: 167 1.69 takemura vendor = PCIC_VENDOR_IBM_KING; 168 1.69 takemura break; 169 1.69 takemura default: 170 1.69 takemura vendor = PCIC_VENDOR_UNKNOWN; 171 1.69 takemura break; 172 1.69 takemura } 173 1.69 takemura 174 1.69 takemura if (vendor == PCIC_VENDOR_I82365SLR0 || 175 1.69 takemura vendor == PCIC_VENDOR_I82365SLR1) { 176 1.69 takemura /* 177 1.72.2.1 skrll * Check for Cirrus PD67xx. 178 1.72.2.1 skrll * the chip_id of the cirrus toggles between 11 and 00 after a 179 1.72.2.1 skrll * write. weird. 180 1.72.2.1 skrll */ 181 1.72.2.1 skrll pcic_write(h, PCIC_CIRRUS_CHIP_INFO, 0); 182 1.72.2.1 skrll reg = pcic_read(h, -1); 183 1.72.2.1 skrll if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) == 184 1.72.2.1 skrll PCIC_CIRRUS_CHIP_INFO_CHIP_ID) { 185 1.72.2.1 skrll reg = pcic_read(h, -1); 186 1.72.2.1 skrll if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) == 0) 187 1.72.2.1 skrll return (PCIC_VENDOR_CIRRUS_PD67XX); 188 1.72.2.1 skrll } 189 1.72.2.1 skrll 190 1.72.2.1 skrll /* 191 1.69 takemura * check for Ricoh RF5C[23]96 192 1.69 takemura */ 193 1.69 takemura reg = pcic_read(h, PCIC_RICOH_REG_CHIP_ID); 194 1.69 takemura switch (reg) { 195 1.69 takemura case PCIC_RICOH_CHIP_ID_5C296: 196 1.72.2.1 skrll return (PCIC_VENDOR_RICOH_5C296); 197 1.69 takemura case PCIC_RICOH_CHIP_ID_5C396: 198 1.72.2.1 skrll return (PCIC_VENDOR_RICOH_5C396); 199 1.69 takemura } 200 1.69 takemura } 201 1.69 takemura 202 1.72.2.1 skrll return (vendor); 203 1.2 thorpej } 204 1.2 thorpej 205 1.2 thorpej char * 206 1.2 thorpej pcic_vendor_to_string(vendor) 207 1.2 thorpej int vendor; 208 1.2 thorpej { 209 1.2 thorpej switch (vendor) { 210 1.2 thorpej case PCIC_VENDOR_I82365SLR0: 211 1.2 thorpej return ("Intel 82365SL Revision 0"); 212 1.2 thorpej case PCIC_VENDOR_I82365SLR1: 213 1.2 thorpej return ("Intel 82365SL Revision 1"); 214 1.72.2.1 skrll case PCIC_VENDOR_CIRRUS_PD67XX: 215 1.72.2.1 skrll return ("Cirrus PD6710/2X"); 216 1.69 takemura case PCIC_VENDOR_I82365SL_DF: 217 1.69 takemura return ("Intel 82365SL-DF"); 218 1.69 takemura case PCIC_VENDOR_RICOH_5C296: 219 1.69 takemura return ("Ricoh RF5C296"); 220 1.69 takemura case PCIC_VENDOR_RICOH_5C396: 221 1.69 takemura return ("Ricoh RF5C396"); 222 1.69 takemura case PCIC_VENDOR_IBM: 223 1.69 takemura return ("IBM PCIC"); 224 1.69 takemura case PCIC_VENDOR_IBM_KING: 225 1.69 takemura return ("IBM KING"); 226 1.2 thorpej } 227 1.2 thorpej 228 1.2 thorpej return ("Unknown controller"); 229 1.2 thorpej } 230 1.2 thorpej 231 1.2 thorpej void 232 1.2 thorpej pcic_attach(sc) 233 1.2 thorpej struct pcic_softc *sc; 234 1.2 thorpej { 235 1.72.2.1 skrll int i, reg, chip, socket; 236 1.54 mycroft struct pcic_handle *h; 237 1.2 thorpej 238 1.33 chopps DPRINTF(("pcic ident regs:")); 239 1.2 thorpej 240 1.53 thorpej lockinit(&sc->sc_pcic_lock, PWAIT, "pciclk", 0, 0); 241 1.53 thorpej 242 1.33 chopps /* find and configure for the available sockets */ 243 1.33 chopps for (i = 0; i < PCIC_NSLOTS; i++) { 244 1.54 mycroft h = &sc->handle[i]; 245 1.33 chopps chip = i / 2; 246 1.33 chopps socket = i % 2; 247 1.54 mycroft 248 1.54 mycroft h->ph_parent = (struct device *)sc; 249 1.54 mycroft h->chip = chip; 250 1.54 mycroft h->sock = chip * PCIC_CHIP_OFFSET + socket * PCIC_SOCKET_OFFSET; 251 1.54 mycroft h->laststate = PCIC_LASTSTATE_EMPTY; 252 1.35 enami /* initialize pcic_read and pcic_write functions */ 253 1.54 mycroft h->ph_read = st_pcic_read; 254 1.54 mycroft h->ph_write = st_pcic_write; 255 1.54 mycroft h->ph_bus_t = sc->iot; 256 1.54 mycroft h->ph_bus_h = sc->ioh; 257 1.72.2.1 skrll h->flags = 0; 258 1.54 mycroft 259 1.33 chopps /* need to read vendor -- for cirrus to report no xtra chip */ 260 1.33 chopps if (socket == 0) 261 1.54 mycroft h->vendor = (h+1)->vendor = pcic_vendor(h); 262 1.54 mycroft 263 1.72.2.1 skrll switch (h->vendor) { 264 1.72.2.1 skrll case PCIC_VENDOR_NONE: 265 1.72.2.1 skrll /* no chip */ 266 1.72.2.1 skrll continue; 267 1.72.2.1 skrll case PCIC_VENDOR_CIRRUS_PD67XX: 268 1.72.2.1 skrll reg = pcic_read(h, PCIC_CIRRUS_CHIP_INFO); 269 1.72.2.1 skrll if (socket == 0 || 270 1.72.2.1 skrll (reg & PCIC_CIRRUS_CHIP_INFO_SLOTS)) 271 1.72.2.1 skrll h->flags = PCIC_FLAG_SOCKETP; 272 1.72.2.1 skrll break; 273 1.72.2.1 skrll default: 274 1.72.2.1 skrll /* 275 1.72.2.1 skrll * During the socket probe, read the ident register 276 1.72.2.1 skrll * twice. I don't understand why, but sometimes the 277 1.72.2.1 skrll * clone chips in hpcmips boxes read all-0s the first 278 1.72.2.1 skrll * time. -- mycroft 279 1.72.2.1 skrll */ 280 1.72.2.1 skrll reg = pcic_read(h, PCIC_IDENT); 281 1.72.2.1 skrll DPRINTF(("socket %d ident reg 0x%02x\n", i, reg)); 282 1.72.2.1 skrll reg = pcic_read(h, PCIC_IDENT); 283 1.72.2.1 skrll DPRINTF(("socket %d ident reg 0x%02x\n", i, reg)); 284 1.72.2.1 skrll if (pcic_ident_ok(reg)) 285 1.72.2.1 skrll h->flags = PCIC_FLAG_SOCKETP; 286 1.72.2.1 skrll break; 287 1.72.2.1 skrll } 288 1.2 thorpej } 289 1.2 thorpej 290 1.2 thorpej for (i = 0; i < PCIC_NSLOTS; i++) { 291 1.54 mycroft h = &sc->handle[i]; 292 1.54 mycroft 293 1.54 mycroft if (h->flags & PCIC_FLAG_SOCKETP) { 294 1.54 mycroft SIMPLEQ_INIT(&h->events); 295 1.33 chopps 296 1.72.2.1 skrll /* disable interrupts and leave socket in reset */ 297 1.72.2.1 skrll pcic_write(h, PCIC_INTR, 0); 298 1.72.2.3 skrll 299 1.72.2.3 skrll /* zero out the address windows */ 300 1.72.2.3 skrll pcic_write(h, PCIC_ADDRWIN_ENABLE, 0); 301 1.72.2.3 skrll 302 1.72.2.3 skrll /* power down the socket */ 303 1.72.2.3 skrll pcic_write(h, PCIC_PWRCTL, 0); 304 1.72.2.3 skrll 305 1.72.2.3 skrll pcic_write(h, PCIC_CSC_INTR, 0); 306 1.54 mycroft (void) pcic_read(h, PCIC_CSC); 307 1.2 thorpej } 308 1.2 thorpej } 309 1.2 thorpej 310 1.33 chopps /* print detected info */ 311 1.33 chopps for (i = 0; i < PCIC_NSLOTS; i += 2) { 312 1.54 mycroft h = &sc->handle[i]; 313 1.33 chopps chip = i / 2; 314 1.2 thorpej 315 1.72.2.1 skrll if (h->vendor == PCIC_VENDOR_NONE) 316 1.72.2.1 skrll continue; 317 1.72.2.1 skrll 318 1.72 thorpej aprint_normal("%s: controller %d (%s) has ", sc->dev.dv_xname, 319 1.72 thorpej chip, pcic_vendor_to_string(sc->handle[i].vendor)); 320 1.2 thorpej 321 1.54 mycroft if ((h->flags & PCIC_FLAG_SOCKETP) && 322 1.54 mycroft ((h+1)->flags & PCIC_FLAG_SOCKETP)) 323 1.72 thorpej aprint_normal("sockets A and B\n"); 324 1.54 mycroft else if (h->flags & PCIC_FLAG_SOCKETP) 325 1.72 thorpej aprint_normal("socket A only\n"); 326 1.54 mycroft else if ((h+1)->flags & PCIC_FLAG_SOCKETP) 327 1.72 thorpej aprint_normal("socket B only\n"); 328 1.2 thorpej else 329 1.72 thorpej aprint_normal("no sockets\n"); 330 1.2 thorpej } 331 1.2 thorpej } 332 1.2 thorpej 333 1.33 chopps /* 334 1.33 chopps * attach the sockets before we know what interrupts we have 335 1.33 chopps */ 336 1.2 thorpej void 337 1.2 thorpej pcic_attach_sockets(sc) 338 1.2 thorpej struct pcic_softc *sc; 339 1.2 thorpej { 340 1.2 thorpej int i; 341 1.2 thorpej 342 1.2 thorpej for (i = 0; i < PCIC_NSLOTS; i++) 343 1.2 thorpej if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 344 1.2 thorpej pcic_attach_socket(&sc->handle[i]); 345 1.2 thorpej } 346 1.2 thorpej 347 1.2 thorpej void 348 1.49 enami pcic_power(why, arg) 349 1.26 sommerfe int why; 350 1.26 sommerfe void *arg; 351 1.26 sommerfe { 352 1.26 sommerfe struct pcic_handle *h = (struct pcic_handle *)arg; 353 1.35 enami struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 354 1.33 chopps int reg; 355 1.33 chopps 356 1.33 chopps DPRINTF(("%s: power: why %d\n", h->ph_parent->dv_xname, why)); 357 1.26 sommerfe 358 1.26 sommerfe if (h->flags & PCIC_FLAG_SOCKETP) { 359 1.26 sommerfe if ((why == PWR_RESUME) && 360 1.26 sommerfe (pcic_read(h, PCIC_CSC_INTR) == 0)) { 361 1.26 sommerfe #ifdef PCICDEBUG 362 1.26 sommerfe char bitbuf[64]; 363 1.26 sommerfe #endif 364 1.33 chopps reg = PCIC_CSC_INTR_CD_ENABLE; 365 1.33 chopps if (sc->irq != -1) 366 1.33 chopps reg |= sc->irq << PCIC_CSC_INTR_IRQ_SHIFT; 367 1.33 chopps pcic_write(h, PCIC_CSC_INTR, reg); 368 1.26 sommerfe DPRINTF(("%s: CSC_INTR was zero; reset to %s\n", 369 1.26 sommerfe sc->dev.dv_xname, 370 1.26 sommerfe bitmask_snprintf(pcic_read(h, PCIC_CSC_INTR), 371 1.26 sommerfe PCIC_CSC_INTR_FORMAT, 372 1.26 sommerfe bitbuf, sizeof(bitbuf)))); 373 1.26 sommerfe } 374 1.42 itojun 375 1.42 itojun /* 376 1.42 itojun * check for card insertion or removal during suspend period. 377 1.42 itojun * XXX: the code can't cope with card swap (remove then insert). 378 1.42 itojun * how can we detect such situation? 379 1.42 itojun */ 380 1.42 itojun if (why == PWR_RESUME) 381 1.42 itojun (void)pcic_intr_socket(h); 382 1.26 sommerfe } 383 1.26 sommerfe } 384 1.26 sommerfe 385 1.26 sommerfe 386 1.33 chopps /* 387 1.33 chopps * attach a socket -- we don't know about irqs yet 388 1.33 chopps */ 389 1.26 sommerfe void 390 1.2 thorpej pcic_attach_socket(h) 391 1.2 thorpej struct pcic_handle *h; 392 1.2 thorpej { 393 1.2 thorpej struct pcmciabus_attach_args paa; 394 1.35 enami struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 395 1.2 thorpej 396 1.2 thorpej /* initialize the rest of the handle */ 397 1.2 thorpej 398 1.14 thorpej h->shutdown = 0; 399 1.2 thorpej h->memalloc = 0; 400 1.2 thorpej h->ioalloc = 0; 401 1.2 thorpej h->ih_irq = 0; 402 1.2 thorpej 403 1.2 thorpej /* now, config one pcmcia device per socket */ 404 1.2 thorpej 405 1.25 haya paa.paa_busname = "pcmcia"; 406 1.25 haya paa.pct = (pcmcia_chipset_tag_t) sc->pct; 407 1.2 thorpej paa.pch = (pcmcia_chipset_handle_t) h; 408 1.25 haya paa.iobase = sc->iobase; 409 1.25 haya paa.iosize = sc->iosize; 410 1.2 thorpej 411 1.33 chopps h->pcmcia = config_found_sm(&sc->dev, &paa, pcic_print, pcic_submatch); 412 1.50 mycroft if (h->pcmcia == NULL) { 413 1.50 mycroft h->flags &= ~PCIC_FLAG_SOCKETP; 414 1.33 chopps return; 415 1.50 mycroft } 416 1.2 thorpej 417 1.33 chopps /* 418 1.33 chopps * queue creation of a kernel thread to handle insert/removal events. 419 1.33 chopps */ 420 1.33 chopps #ifdef DIAGNOSTIC 421 1.33 chopps if (h->event_thread != NULL) 422 1.33 chopps panic("pcic_attach_socket: event thread"); 423 1.33 chopps #endif 424 1.33 chopps config_pending_incr(); 425 1.33 chopps kthread_create(pcic_create_event_thread, h); 426 1.33 chopps } 427 1.2 thorpej 428 1.33 chopps /* 429 1.33 chopps * now finish attaching the sockets, we are ready to allocate 430 1.33 chopps * interrupts 431 1.33 chopps */ 432 1.33 chopps void 433 1.33 chopps pcic_attach_sockets_finish(sc) 434 1.33 chopps struct pcic_softc *sc; 435 1.33 chopps { 436 1.33 chopps int i; 437 1.33 chopps 438 1.33 chopps for (i = 0; i < PCIC_NSLOTS; i++) 439 1.51 mycroft if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 440 1.33 chopps pcic_attach_socket_finish(&sc->handle[i]); 441 1.33 chopps } 442 1.33 chopps 443 1.33 chopps /* 444 1.33 chopps * finishing attaching the socket. Interrupts may now be on 445 1.33 chopps * if so expects the pcic interrupt to be blocked 446 1.33 chopps */ 447 1.33 chopps void 448 1.33 chopps pcic_attach_socket_finish(h) 449 1.33 chopps struct pcic_handle *h; 450 1.33 chopps { 451 1.35 enami struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 452 1.72.2.3 skrll int reg; 453 1.33 chopps 454 1.46 nathanw DPRINTF(("%s: attach finish socket %ld\n", h->ph_parent->dv_xname, 455 1.46 nathanw (long) (h - &sc->handle[0]))); 456 1.51 mycroft 457 1.33 chopps /* 458 1.33 chopps * Set up a powerhook to ensure it continues to interrupt on 459 1.33 chopps * card detect even after suspend. 460 1.33 chopps * (this works around a bug seen in suspend-to-disk on the 461 1.33 chopps * Sony VAIO Z505; on resume, the CSC_INTR state is not preserved). 462 1.33 chopps */ 463 1.33 chopps powerhook_establish(pcic_power, h); 464 1.33 chopps 465 1.33 chopps /* enable interrupts on card detect, poll for them if no irq avail */ 466 1.33 chopps reg = PCIC_CSC_INTR_CD_ENABLE; 467 1.57 thorpej if (sc->irq == -1) { 468 1.57 thorpej if (sc->poll_established == 0) { 469 1.57 thorpej callout_init(&sc->poll_ch); 470 1.57 thorpej callout_reset(&sc->poll_ch, hz / 2, pcic_poll_intr, sc); 471 1.57 thorpej sc->poll_established = 1; 472 1.57 thorpej } 473 1.57 thorpej } else 474 1.33 chopps reg |= sc->irq << PCIC_CSC_INTR_IRQ_SHIFT; 475 1.33 chopps pcic_write(h, PCIC_CSC_INTR, reg); 476 1.33 chopps 477 1.33 chopps /* steer above mgmt interrupt to configured place */ 478 1.72.2.1 skrll if (sc->irq == 0) 479 1.72.2.3 skrll pcic_write(h, PCIC_INTR, PCIC_INTR_ENABLE); 480 1.33 chopps 481 1.33 chopps /* clear possible card detect interrupt */ 482 1.72.2.3 skrll (void) pcic_read(h, PCIC_CSC); 483 1.33 chopps 484 1.33 chopps DPRINTF(("%s: attach finish vendor 0x%02x\n", h->ph_parent->dv_xname, 485 1.33 chopps h->vendor)); 486 1.33 chopps 487 1.33 chopps /* unsleep the cirrus controller */ 488 1.72.2.1 skrll if (h->vendor == PCIC_VENDOR_CIRRUS_PD67XX) { 489 1.33 chopps reg = pcic_read(h, PCIC_CIRRUS_MISC_CTL_2); 490 1.33 chopps if (reg & PCIC_CIRRUS_MISC_CTL_2_SUSPEND) { 491 1.33 chopps DPRINTF(("%s: socket %02x was suspended\n", 492 1.35 enami h->ph_parent->dv_xname, h->sock)); 493 1.33 chopps reg &= ~PCIC_CIRRUS_MISC_CTL_2_SUSPEND; 494 1.33 chopps pcic_write(h, PCIC_CIRRUS_MISC_CTL_2, reg); 495 1.33 chopps } 496 1.33 chopps } 497 1.33 chopps 498 1.33 chopps /* if there's a card there, then attach it. */ 499 1.33 chopps reg = pcic_read(h, PCIC_IF_STATUS); 500 1.33 chopps if ((reg & PCIC_IF_STATUS_CARDDETECT_MASK) == 501 1.33 chopps PCIC_IF_STATUS_CARDDETECT_PRESENT) { 502 1.33 chopps pcic_queue_event(h, PCIC_EVENT_INSERTION); 503 1.33 chopps h->laststate = PCIC_LASTSTATE_PRESENT; 504 1.33 chopps } else { 505 1.33 chopps h->laststate = PCIC_LASTSTATE_EMPTY; 506 1.33 chopps } 507 1.2 thorpej } 508 1.2 thorpej 509 1.2 thorpej void 510 1.14 thorpej pcic_create_event_thread(arg) 511 1.14 thorpej void *arg; 512 1.14 thorpej { 513 1.14 thorpej struct pcic_handle *h = arg; 514 1.14 thorpej const char *cs; 515 1.14 thorpej 516 1.14 thorpej switch (h->sock) { 517 1.14 thorpej case C0SA: 518 1.14 thorpej cs = "0,0"; 519 1.14 thorpej break; 520 1.14 thorpej case C0SB: 521 1.14 thorpej cs = "0,1"; 522 1.14 thorpej break; 523 1.14 thorpej case C1SA: 524 1.14 thorpej cs = "1,0"; 525 1.14 thorpej break; 526 1.14 thorpej case C1SB: 527 1.14 thorpej cs = "1,1"; 528 1.14 thorpej break; 529 1.14 thorpej default: 530 1.14 thorpej panic("pcic_create_event_thread: unknown pcic socket"); 531 1.14 thorpej } 532 1.14 thorpej 533 1.24 thorpej if (kthread_create1(pcic_event_thread, h, &h->event_thread, 534 1.25 haya "%s,%s", h->ph_parent->dv_xname, cs)) { 535 1.14 thorpej printf("%s: unable to create event thread for sock 0x%02x\n", 536 1.25 haya h->ph_parent->dv_xname, h->sock); 537 1.14 thorpej panic("pcic_create_event_thread"); 538 1.14 thorpej } 539 1.14 thorpej } 540 1.14 thorpej 541 1.14 thorpej void 542 1.14 thorpej pcic_event_thread(arg) 543 1.14 thorpej void *arg; 544 1.14 thorpej { 545 1.14 thorpej struct pcic_handle *h = arg; 546 1.14 thorpej struct pcic_event *pe; 547 1.29 enami int s, first = 1; 548 1.35 enami struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 549 1.14 thorpej 550 1.14 thorpej while (h->shutdown == 0) { 551 1.53 thorpej /* 552 1.53 thorpej * Serialize event processing on the PCIC. We may 553 1.53 thorpej * sleep while we hold this lock. 554 1.53 thorpej */ 555 1.53 thorpej (void) lockmgr(&sc->sc_pcic_lock, LK_EXCLUSIVE, NULL); 556 1.53 thorpej 557 1.14 thorpej s = splhigh(); 558 1.14 thorpej if ((pe = SIMPLEQ_FIRST(&h->events)) == NULL) { 559 1.14 thorpej splx(s); 560 1.29 enami if (first) { 561 1.29 enami first = 0; 562 1.29 enami config_pending_decr(); 563 1.29 enami } 564 1.53 thorpej /* 565 1.53 thorpej * No events to process; release the PCIC lock. 566 1.53 thorpej */ 567 1.53 thorpej (void) lockmgr(&sc->sc_pcic_lock, LK_RELEASE, NULL); 568 1.14 thorpej (void) tsleep(&h->events, PWAIT, "pcicev", 0); 569 1.14 thorpej continue; 570 1.20 msaitoh } else { 571 1.20 msaitoh splx(s); 572 1.20 msaitoh /* sleep .25s to be enqueued chatterling interrupts */ 573 1.35 enami (void) tsleep((caddr_t)pcic_event_thread, PWAIT, 574 1.35 enami "pcicss", hz/4); 575 1.14 thorpej } 576 1.20 msaitoh s = splhigh(); 577 1.66 lukem SIMPLEQ_REMOVE_HEAD(&h->events, pe_q); 578 1.14 thorpej splx(s); 579 1.14 thorpej 580 1.14 thorpej switch (pe->pe_type) { 581 1.14 thorpej case PCIC_EVENT_INSERTION: 582 1.20 msaitoh s = splhigh(); 583 1.20 msaitoh while (1) { 584 1.20 msaitoh struct pcic_event *pe1, *pe2; 585 1.20 msaitoh 586 1.20 msaitoh if ((pe1 = SIMPLEQ_FIRST(&h->events)) == NULL) 587 1.20 msaitoh break; 588 1.20 msaitoh if (pe1->pe_type != PCIC_EVENT_REMOVAL) 589 1.20 msaitoh break; 590 1.20 msaitoh if ((pe2 = SIMPLEQ_NEXT(pe1, pe_q)) == NULL) 591 1.20 msaitoh break; 592 1.20 msaitoh if (pe2->pe_type == PCIC_EVENT_INSERTION) { 593 1.66 lukem SIMPLEQ_REMOVE_HEAD(&h->events, pe_q); 594 1.20 msaitoh free(pe1, M_TEMP); 595 1.66 lukem SIMPLEQ_REMOVE_HEAD(&h->events, pe_q); 596 1.20 msaitoh free(pe2, M_TEMP); 597 1.20 msaitoh } 598 1.20 msaitoh } 599 1.20 msaitoh splx(s); 600 1.20 msaitoh 601 1.35 enami DPRINTF(("%s: insertion event\n", 602 1.35 enami h->ph_parent->dv_xname)); 603 1.14 thorpej pcic_attach_card(h); 604 1.14 thorpej break; 605 1.14 thorpej 606 1.14 thorpej case PCIC_EVENT_REMOVAL: 607 1.20 msaitoh s = splhigh(); 608 1.20 msaitoh while (1) { 609 1.20 msaitoh struct pcic_event *pe1, *pe2; 610 1.20 msaitoh 611 1.20 msaitoh if ((pe1 = SIMPLEQ_FIRST(&h->events)) == NULL) 612 1.20 msaitoh break; 613 1.20 msaitoh if (pe1->pe_type != PCIC_EVENT_INSERTION) 614 1.20 msaitoh break; 615 1.20 msaitoh if ((pe2 = SIMPLEQ_NEXT(pe1, pe_q)) == NULL) 616 1.20 msaitoh break; 617 1.20 msaitoh if (pe2->pe_type == PCIC_EVENT_REMOVAL) { 618 1.66 lukem SIMPLEQ_REMOVE_HEAD(&h->events, pe_q); 619 1.20 msaitoh free(pe1, M_TEMP); 620 1.66 lukem SIMPLEQ_REMOVE_HEAD(&h->events, pe_q); 621 1.20 msaitoh free(pe2, M_TEMP); 622 1.20 msaitoh } 623 1.20 msaitoh } 624 1.20 msaitoh splx(s); 625 1.20 msaitoh 626 1.35 enami DPRINTF(("%s: removal event\n", 627 1.35 enami h->ph_parent->dv_xname)); 628 1.15 thorpej pcic_detach_card(h, DETACH_FORCE); 629 1.14 thorpej break; 630 1.14 thorpej 631 1.14 thorpej default: 632 1.14 thorpej panic("pcic_event_thread: unknown event %d", 633 1.14 thorpej pe->pe_type); 634 1.14 thorpej } 635 1.14 thorpej free(pe, M_TEMP); 636 1.53 thorpej 637 1.53 thorpej (void) lockmgr(&sc->sc_pcic_lock, LK_RELEASE, NULL); 638 1.14 thorpej } 639 1.14 thorpej 640 1.14 thorpej h->event_thread = NULL; 641 1.14 thorpej 642 1.14 thorpej /* In case parent is waiting for us to exit. */ 643 1.25 haya wakeup(sc); 644 1.14 thorpej 645 1.14 thorpej kthread_exit(0); 646 1.14 thorpej } 647 1.14 thorpej 648 1.2 thorpej int 649 1.2 thorpej pcic_submatch(parent, cf, aux) 650 1.2 thorpej struct device *parent; 651 1.2 thorpej struct cfdata *cf; 652 1.2 thorpej void *aux; 653 1.2 thorpej { 654 1.2 thorpej 655 1.3 enami struct pcmciabus_attach_args *paa = aux; 656 1.2 thorpej struct pcic_handle *h = (struct pcic_handle *) paa->pch; 657 1.2 thorpej 658 1.2 thorpej switch (h->sock) { 659 1.2 thorpej case C0SA: 660 1.72.2.1 skrll if (cf->pcmciabuscf_controller != 661 1.16 thorpej PCMCIABUSCF_CONTROLLER_DEFAULT && 662 1.72.2.1 skrll cf->pcmciabuscf_controller != 0) 663 1.2 thorpej return 0; 664 1.72.2.1 skrll if (cf->pcmciabuscf_socket != 665 1.16 thorpej PCMCIABUSCF_SOCKET_DEFAULT && 666 1.72.2.1 skrll cf->pcmciabuscf_socket != 0) 667 1.2 thorpej return 0; 668 1.2 thorpej 669 1.2 thorpej break; 670 1.2 thorpej case C0SB: 671 1.72.2.1 skrll if (cf->pcmciabuscf_controller != 672 1.16 thorpej PCMCIABUSCF_CONTROLLER_DEFAULT && 673 1.72.2.1 skrll cf->pcmciabuscf_controller != 0) 674 1.2 thorpej return 0; 675 1.72.2.1 skrll if (cf->pcmciabuscf_socket != 676 1.16 thorpej PCMCIABUSCF_SOCKET_DEFAULT && 677 1.72.2.1 skrll cf->pcmciabuscf_socket != 1) 678 1.2 thorpej return 0; 679 1.2 thorpej 680 1.2 thorpej break; 681 1.2 thorpej case C1SA: 682 1.72.2.1 skrll if (cf->pcmciabuscf_controller != 683 1.16 thorpej PCMCIABUSCF_CONTROLLER_DEFAULT && 684 1.72.2.1 skrll cf->pcmciabuscf_controller != 1) 685 1.2 thorpej return 0; 686 1.72.2.1 skrll if (cf->pcmciabuscf_socket != 687 1.16 thorpej PCMCIABUSCF_SOCKET_DEFAULT && 688 1.72.2.1 skrll cf->pcmciabuscf_socket != 0) 689 1.2 thorpej return 0; 690 1.2 thorpej 691 1.2 thorpej break; 692 1.2 thorpej case C1SB: 693 1.72.2.1 skrll if (cf->pcmciabuscf_controller != 694 1.16 thorpej PCMCIABUSCF_CONTROLLER_DEFAULT && 695 1.72.2.1 skrll cf->pcmciabuscf_controller != 1) 696 1.2 thorpej return 0; 697 1.72.2.1 skrll if (cf->pcmciabuscf_socket != 698 1.16 thorpej PCMCIABUSCF_SOCKET_DEFAULT && 699 1.72.2.1 skrll cf->pcmciabuscf_socket != 1) 700 1.2 thorpej return 0; 701 1.2 thorpej 702 1.2 thorpej break; 703 1.2 thorpej default: 704 1.2 thorpej panic("unknown pcic socket"); 705 1.2 thorpej } 706 1.2 thorpej 707 1.67 thorpej return (config_match(parent, cf, aux)); 708 1.2 thorpej } 709 1.2 thorpej 710 1.2 thorpej int 711 1.2 thorpej pcic_print(arg, pnp) 712 1.2 thorpej void *arg; 713 1.2 thorpej const char *pnp; 714 1.2 thorpej { 715 1.3 enami struct pcmciabus_attach_args *paa = arg; 716 1.2 thorpej struct pcic_handle *h = (struct pcic_handle *) paa->pch; 717 1.2 thorpej 718 1.2 thorpej /* Only "pcmcia"s can attach to "pcic"s... easy. */ 719 1.2 thorpej if (pnp) 720 1.70 thorpej aprint_normal("pcmcia at %s", pnp); 721 1.2 thorpej 722 1.2 thorpej switch (h->sock) { 723 1.2 thorpej case C0SA: 724 1.70 thorpej aprint_normal(" controller 0 socket 0"); 725 1.2 thorpej break; 726 1.2 thorpej case C0SB: 727 1.70 thorpej aprint_normal(" controller 0 socket 1"); 728 1.2 thorpej break; 729 1.2 thorpej case C1SA: 730 1.70 thorpej aprint_normal(" controller 1 socket 0"); 731 1.2 thorpej break; 732 1.2 thorpej case C1SB: 733 1.70 thorpej aprint_normal(" controller 1 socket 1"); 734 1.2 thorpej break; 735 1.2 thorpej default: 736 1.2 thorpej panic("unknown pcic socket"); 737 1.2 thorpej } 738 1.2 thorpej 739 1.2 thorpej return (UNCONF); 740 1.2 thorpej } 741 1.2 thorpej 742 1.33 chopps void 743 1.33 chopps pcic_poll_intr(arg) 744 1.33 chopps void *arg; 745 1.33 chopps { 746 1.33 chopps struct pcic_softc *sc; 747 1.33 chopps int i, s; 748 1.33 chopps 749 1.33 chopps s = spltty(); 750 1.33 chopps sc = arg; 751 1.33 chopps for (i = 0; i < PCIC_NSLOTS; i++) 752 1.33 chopps if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 753 1.33 chopps (void)pcic_intr_socket(&sc->handle[i]); 754 1.57 thorpej callout_reset(&sc->poll_ch, hz / 2, pcic_poll_intr, sc); 755 1.33 chopps splx(s); 756 1.33 chopps } 757 1.33 chopps 758 1.2 thorpej int 759 1.2 thorpej pcic_intr(arg) 760 1.2 thorpej void *arg; 761 1.2 thorpej { 762 1.3 enami struct pcic_softc *sc = arg; 763 1.2 thorpej int i, ret = 0; 764 1.2 thorpej 765 1.2 thorpej DPRINTF(("%s: intr\n", sc->dev.dv_xname)); 766 1.2 thorpej 767 1.2 thorpej for (i = 0; i < PCIC_NSLOTS; i++) 768 1.2 thorpej if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 769 1.2 thorpej ret += pcic_intr_socket(&sc->handle[i]); 770 1.2 thorpej 771 1.2 thorpej return (ret ? 1 : 0); 772 1.2 thorpej } 773 1.2 thorpej 774 1.2 thorpej int 775 1.2 thorpej pcic_intr_socket(h) 776 1.2 thorpej struct pcic_handle *h; 777 1.2 thorpej { 778 1.2 thorpej int cscreg; 779 1.2 thorpej 780 1.2 thorpej cscreg = pcic_read(h, PCIC_CSC); 781 1.2 thorpej 782 1.2 thorpej cscreg &= (PCIC_CSC_GPI | 783 1.2 thorpej PCIC_CSC_CD | 784 1.2 thorpej PCIC_CSC_READY | 785 1.2 thorpej PCIC_CSC_BATTWARN | 786 1.2 thorpej PCIC_CSC_BATTDEAD); 787 1.2 thorpej 788 1.2 thorpej if (cscreg & PCIC_CSC_GPI) { 789 1.25 haya DPRINTF(("%s: %02x GPI\n", h->ph_parent->dv_xname, h->sock)); 790 1.2 thorpej } 791 1.2 thorpej if (cscreg & PCIC_CSC_CD) { 792 1.2 thorpej int statreg; 793 1.2 thorpej 794 1.2 thorpej statreg = pcic_read(h, PCIC_IF_STATUS); 795 1.2 thorpej 796 1.25 haya DPRINTF(("%s: %02x CD %x\n", h->ph_parent->dv_xname, h->sock, 797 1.2 thorpej statreg)); 798 1.2 thorpej 799 1.2 thorpej if ((statreg & PCIC_IF_STATUS_CARDDETECT_MASK) == 800 1.2 thorpej PCIC_IF_STATUS_CARDDETECT_PRESENT) { 801 1.20 msaitoh if (h->laststate != PCIC_LASTSTATE_PRESENT) { 802 1.14 thorpej DPRINTF(("%s: enqueing INSERTION event\n", 803 1.25 haya h->ph_parent->dv_xname)); 804 1.14 thorpej pcic_queue_event(h, PCIC_EVENT_INSERTION); 805 1.14 thorpej } 806 1.20 msaitoh h->laststate = PCIC_LASTSTATE_PRESENT; 807 1.2 thorpej } else { 808 1.20 msaitoh if (h->laststate == PCIC_LASTSTATE_PRESENT) { 809 1.15 thorpej /* Deactivate the card now. */ 810 1.15 thorpej DPRINTF(("%s: deactivating card\n", 811 1.25 haya h->ph_parent->dv_xname)); 812 1.15 thorpej pcic_deactivate_card(h); 813 1.15 thorpej 814 1.14 thorpej DPRINTF(("%s: enqueing REMOVAL event\n", 815 1.25 haya h->ph_parent->dv_xname)); 816 1.14 thorpej pcic_queue_event(h, PCIC_EVENT_REMOVAL); 817 1.14 thorpej } 818 1.72.2.3 skrll h->laststate = PCIC_LASTSTATE_EMPTY; 819 1.2 thorpej } 820 1.2 thorpej } 821 1.2 thorpej if (cscreg & PCIC_CSC_READY) { 822 1.25 haya DPRINTF(("%s: %02x READY\n", h->ph_parent->dv_xname, h->sock)); 823 1.2 thorpej /* shouldn't happen */ 824 1.2 thorpej } 825 1.2 thorpej if (cscreg & PCIC_CSC_BATTWARN) { 826 1.35 enami DPRINTF(("%s: %02x BATTWARN\n", h->ph_parent->dv_xname, 827 1.35 enami h->sock)); 828 1.2 thorpej } 829 1.2 thorpej if (cscreg & PCIC_CSC_BATTDEAD) { 830 1.35 enami DPRINTF(("%s: %02x BATTDEAD\n", h->ph_parent->dv_xname, 831 1.35 enami h->sock)); 832 1.2 thorpej } 833 1.2 thorpej return (cscreg ? 1 : 0); 834 1.14 thorpej } 835 1.14 thorpej 836 1.14 thorpej void 837 1.14 thorpej pcic_queue_event(h, event) 838 1.14 thorpej struct pcic_handle *h; 839 1.14 thorpej int event; 840 1.14 thorpej { 841 1.14 thorpej struct pcic_event *pe; 842 1.14 thorpej int s; 843 1.14 thorpej 844 1.14 thorpej pe = malloc(sizeof(*pe), M_TEMP, M_NOWAIT); 845 1.14 thorpej if (pe == NULL) 846 1.14 thorpej panic("pcic_queue_event: can't allocate event"); 847 1.14 thorpej 848 1.14 thorpej pe->pe_type = event; 849 1.14 thorpej s = splhigh(); 850 1.14 thorpej SIMPLEQ_INSERT_TAIL(&h->events, pe, pe_q); 851 1.14 thorpej splx(s); 852 1.14 thorpej wakeup(&h->events); 853 1.2 thorpej } 854 1.2 thorpej 855 1.2 thorpej void 856 1.2 thorpej pcic_attach_card(h) 857 1.2 thorpej struct pcic_handle *h; 858 1.2 thorpej { 859 1.15 thorpej 860 1.20 msaitoh if (!(h->flags & PCIC_FLAG_CARDP)) { 861 1.20 msaitoh /* call the MI attach function */ 862 1.20 msaitoh pcmcia_card_attach(h->pcmcia); 863 1.2 thorpej 864 1.20 msaitoh h->flags |= PCIC_FLAG_CARDP; 865 1.20 msaitoh } else { 866 1.20 msaitoh DPRINTF(("pcic_attach_card: already attached")); 867 1.20 msaitoh } 868 1.2 thorpej } 869 1.2 thorpej 870 1.2 thorpej void 871 1.15 thorpej pcic_detach_card(h, flags) 872 1.2 thorpej struct pcic_handle *h; 873 1.15 thorpej int flags; /* DETACH_* */ 874 1.2 thorpej { 875 1.15 thorpej 876 1.20 msaitoh if (h->flags & PCIC_FLAG_CARDP) { 877 1.20 msaitoh h->flags &= ~PCIC_FLAG_CARDP; 878 1.2 thorpej 879 1.20 msaitoh /* call the MI detach function */ 880 1.20 msaitoh pcmcia_card_detach(h->pcmcia, flags); 881 1.20 msaitoh } else { 882 1.20 msaitoh DPRINTF(("pcic_detach_card: already detached")); 883 1.20 msaitoh } 884 1.15 thorpej } 885 1.15 thorpej 886 1.15 thorpej void 887 1.15 thorpej pcic_deactivate_card(h) 888 1.15 thorpej struct pcic_handle *h; 889 1.15 thorpej { 890 1.72.2.1 skrll int intr; 891 1.2 thorpej 892 1.15 thorpej /* call the MI deactivate function */ 893 1.15 thorpej pcmcia_card_deactivate(h->pcmcia); 894 1.2 thorpej 895 1.15 thorpej /* reset the socket */ 896 1.72.2.1 skrll intr = pcic_read(h, PCIC_INTR); 897 1.72.2.1 skrll intr &= PCIC_INTR_ENABLE; 898 1.72.2.1 skrll pcic_write(h, PCIC_INTR, intr); 899 1.72.2.3 skrll 900 1.72.2.3 skrll /* power down the socket */ 901 1.72.2.3 skrll pcic_write(h, PCIC_PWRCTL, 0); 902 1.2 thorpej } 903 1.2 thorpej 904 1.2 thorpej int 905 1.2 thorpej pcic_chip_mem_alloc(pch, size, pcmhp) 906 1.2 thorpej pcmcia_chipset_handle_t pch; 907 1.2 thorpej bus_size_t size; 908 1.2 thorpej struct pcmcia_mem_handle *pcmhp; 909 1.2 thorpej { 910 1.2 thorpej struct pcic_handle *h = (struct pcic_handle *) pch; 911 1.2 thorpej bus_space_handle_t memh; 912 1.2 thorpej bus_addr_t addr; 913 1.2 thorpej bus_size_t sizepg; 914 1.2 thorpej int i, mask, mhandle; 915 1.35 enami struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 916 1.2 thorpej 917 1.2 thorpej /* out of sc->memh, allocate as many pages as necessary */ 918 1.2 thorpej 919 1.2 thorpej /* convert size to PCIC pages */ 920 1.2 thorpej sizepg = (size + (PCIC_MEM_ALIGN - 1)) / PCIC_MEM_ALIGN; 921 1.19 christos if (sizepg > PCIC_MAX_MEM_PAGES) 922 1.19 christos return (1); 923 1.2 thorpej 924 1.2 thorpej mask = (1 << sizepg) - 1; 925 1.2 thorpej 926 1.2 thorpej addr = 0; /* XXX gcc -Wuninitialized */ 927 1.2 thorpej mhandle = 0; /* XXX gcc -Wuninitialized */ 928 1.2 thorpej 929 1.19 christos for (i = 0; i <= PCIC_MAX_MEM_PAGES - sizepg; i++) { 930 1.25 haya if ((sc->subregionmask & (mask << i)) == (mask << i)) { 931 1.25 haya if (bus_space_subregion(sc->memt, sc->memh, 932 1.2 thorpej i * PCIC_MEM_PAGESIZE, 933 1.2 thorpej sizepg * PCIC_MEM_PAGESIZE, &memh)) 934 1.2 thorpej return (1); 935 1.2 thorpej mhandle = mask << i; 936 1.25 haya addr = sc->membase + (i * PCIC_MEM_PAGESIZE); 937 1.25 haya sc->subregionmask &= ~(mhandle); 938 1.25 haya pcmhp->memt = sc->memt; 939 1.19 christos pcmhp->memh = memh; 940 1.19 christos pcmhp->addr = addr; 941 1.19 christos pcmhp->size = size; 942 1.19 christos pcmhp->mhandle = mhandle; 943 1.19 christos pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 944 1.19 christos return (0); 945 1.2 thorpej } 946 1.2 thorpej } 947 1.2 thorpej 948 1.19 christos return (1); 949 1.2 thorpej } 950 1.2 thorpej 951 1.2 thorpej void 952 1.2 thorpej pcic_chip_mem_free(pch, pcmhp) 953 1.2 thorpej pcmcia_chipset_handle_t pch; 954 1.2 thorpej struct pcmcia_mem_handle *pcmhp; 955 1.2 thorpej { 956 1.2 thorpej struct pcic_handle *h = (struct pcic_handle *) pch; 957 1.35 enami struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 958 1.2 thorpej 959 1.25 haya sc->subregionmask |= pcmhp->mhandle; 960 1.2 thorpej } 961 1.2 thorpej 962 1.62 jdolecek static const struct mem_map_index_st { 963 1.2 thorpej int sysmem_start_lsb; 964 1.2 thorpej int sysmem_start_msb; 965 1.2 thorpej int sysmem_stop_lsb; 966 1.2 thorpej int sysmem_stop_msb; 967 1.2 thorpej int cardmem_lsb; 968 1.2 thorpej int cardmem_msb; 969 1.2 thorpej int memenable; 970 1.2 thorpej } mem_map_index[] = { 971 1.2 thorpej { 972 1.2 thorpej PCIC_SYSMEM_ADDR0_START_LSB, 973 1.2 thorpej PCIC_SYSMEM_ADDR0_START_MSB, 974 1.2 thorpej PCIC_SYSMEM_ADDR0_STOP_LSB, 975 1.2 thorpej PCIC_SYSMEM_ADDR0_STOP_MSB, 976 1.2 thorpej PCIC_CARDMEM_ADDR0_LSB, 977 1.2 thorpej PCIC_CARDMEM_ADDR0_MSB, 978 1.2 thorpej PCIC_ADDRWIN_ENABLE_MEM0, 979 1.2 thorpej }, 980 1.2 thorpej { 981 1.2 thorpej PCIC_SYSMEM_ADDR1_START_LSB, 982 1.2 thorpej PCIC_SYSMEM_ADDR1_START_MSB, 983 1.2 thorpej PCIC_SYSMEM_ADDR1_STOP_LSB, 984 1.2 thorpej PCIC_SYSMEM_ADDR1_STOP_MSB, 985 1.2 thorpej PCIC_CARDMEM_ADDR1_LSB, 986 1.2 thorpej PCIC_CARDMEM_ADDR1_MSB, 987 1.2 thorpej PCIC_ADDRWIN_ENABLE_MEM1, 988 1.2 thorpej }, 989 1.2 thorpej { 990 1.2 thorpej PCIC_SYSMEM_ADDR2_START_LSB, 991 1.2 thorpej PCIC_SYSMEM_ADDR2_START_MSB, 992 1.2 thorpej PCIC_SYSMEM_ADDR2_STOP_LSB, 993 1.2 thorpej PCIC_SYSMEM_ADDR2_STOP_MSB, 994 1.2 thorpej PCIC_CARDMEM_ADDR2_LSB, 995 1.2 thorpej PCIC_CARDMEM_ADDR2_MSB, 996 1.2 thorpej PCIC_ADDRWIN_ENABLE_MEM2, 997 1.2 thorpej }, 998 1.2 thorpej { 999 1.2 thorpej PCIC_SYSMEM_ADDR3_START_LSB, 1000 1.2 thorpej PCIC_SYSMEM_ADDR3_START_MSB, 1001 1.2 thorpej PCIC_SYSMEM_ADDR3_STOP_LSB, 1002 1.2 thorpej PCIC_SYSMEM_ADDR3_STOP_MSB, 1003 1.2 thorpej PCIC_CARDMEM_ADDR3_LSB, 1004 1.2 thorpej PCIC_CARDMEM_ADDR3_MSB, 1005 1.2 thorpej PCIC_ADDRWIN_ENABLE_MEM3, 1006 1.2 thorpej }, 1007 1.2 thorpej { 1008 1.2 thorpej PCIC_SYSMEM_ADDR4_START_LSB, 1009 1.2 thorpej PCIC_SYSMEM_ADDR4_START_MSB, 1010 1.2 thorpej PCIC_SYSMEM_ADDR4_STOP_LSB, 1011 1.2 thorpej PCIC_SYSMEM_ADDR4_STOP_MSB, 1012 1.2 thorpej PCIC_CARDMEM_ADDR4_LSB, 1013 1.2 thorpej PCIC_CARDMEM_ADDR4_MSB, 1014 1.2 thorpej PCIC_ADDRWIN_ENABLE_MEM4, 1015 1.2 thorpej }, 1016 1.2 thorpej }; 1017 1.2 thorpej 1018 1.2 thorpej void 1019 1.2 thorpej pcic_chip_do_mem_map(h, win) 1020 1.2 thorpej struct pcic_handle *h; 1021 1.2 thorpej int win; 1022 1.2 thorpej { 1023 1.2 thorpej int reg; 1024 1.28 joda int kind = h->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 1025 1.35 enami int mem8 = 1026 1.47 chopps (h->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 1027 1.47 chopps || (kind == PCMCIA_MEM_ATTR); 1028 1.28 joda 1029 1.33 chopps DPRINTF(("mem8 %d\n", mem8)); 1030 1.33 chopps /* mem8 = 1; */ 1031 1.33 chopps 1032 1.2 thorpej pcic_write(h, mem_map_index[win].sysmem_start_lsb, 1033 1.2 thorpej (h->mem[win].addr >> PCIC_SYSMEM_ADDRX_SHIFT) & 0xff); 1034 1.2 thorpej pcic_write(h, mem_map_index[win].sysmem_start_msb, 1035 1.2 thorpej ((h->mem[win].addr >> (PCIC_SYSMEM_ADDRX_SHIFT + 8)) & 1036 1.43 joda PCIC_SYSMEM_ADDRX_START_MSB_ADDR_MASK) | 1037 1.44 enami (mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT)); 1038 1.2 thorpej 1039 1.2 thorpej pcic_write(h, mem_map_index[win].sysmem_stop_lsb, 1040 1.2 thorpej ((h->mem[win].addr + h->mem[win].size) >> 1041 1.2 thorpej PCIC_SYSMEM_ADDRX_SHIFT) & 0xff); 1042 1.2 thorpej pcic_write(h, mem_map_index[win].sysmem_stop_msb, 1043 1.2 thorpej (((h->mem[win].addr + h->mem[win].size) >> 1044 1.2 thorpej (PCIC_SYSMEM_ADDRX_SHIFT + 8)) & 1045 1.2 thorpej PCIC_SYSMEM_ADDRX_STOP_MSB_ADDR_MASK) | 1046 1.2 thorpej PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2); 1047 1.2 thorpej 1048 1.2 thorpej pcic_write(h, mem_map_index[win].cardmem_lsb, 1049 1.2 thorpej (h->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff); 1050 1.2 thorpej pcic_write(h, mem_map_index[win].cardmem_msb, 1051 1.2 thorpej ((h->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) & 1052 1.2 thorpej PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) | 1053 1.28 joda ((kind == PCMCIA_MEM_ATTR) ? 1054 1.2 thorpej PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0)); 1055 1.2 thorpej 1056 1.2 thorpej reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1057 1.43 joda reg |= (mem_map_index[win].memenable | PCIC_ADDRWIN_ENABLE_MEMCS16); 1058 1.2 thorpej pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1059 1.21 marc 1060 1.21 marc delay(100); 1061 1.2 thorpej 1062 1.2 thorpej #ifdef PCICDEBUG 1063 1.2 thorpej { 1064 1.2 thorpej int r1, r2, r3, r4, r5, r6; 1065 1.2 thorpej 1066 1.2 thorpej r1 = pcic_read(h, mem_map_index[win].sysmem_start_msb); 1067 1.2 thorpej r2 = pcic_read(h, mem_map_index[win].sysmem_start_lsb); 1068 1.2 thorpej r3 = pcic_read(h, mem_map_index[win].sysmem_stop_msb); 1069 1.2 thorpej r4 = pcic_read(h, mem_map_index[win].sysmem_stop_lsb); 1070 1.2 thorpej r5 = pcic_read(h, mem_map_index[win].cardmem_msb); 1071 1.2 thorpej r6 = pcic_read(h, mem_map_index[win].cardmem_lsb); 1072 1.2 thorpej 1073 1.2 thorpej DPRINTF(("pcic_chip_do_mem_map window %d: %02x%02x %02x%02x " 1074 1.2 thorpej "%02x%02x\n", win, r1, r2, r3, r4, r5, r6)); 1075 1.2 thorpej } 1076 1.2 thorpej #endif 1077 1.2 thorpej } 1078 1.2 thorpej 1079 1.2 thorpej int 1080 1.2 thorpej pcic_chip_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 1081 1.2 thorpej pcmcia_chipset_handle_t pch; 1082 1.2 thorpej int kind; 1083 1.2 thorpej bus_addr_t card_addr; 1084 1.2 thorpej bus_size_t size; 1085 1.2 thorpej struct pcmcia_mem_handle *pcmhp; 1086 1.65 soren bus_size_t *offsetp; 1087 1.2 thorpej int *windowp; 1088 1.2 thorpej { 1089 1.2 thorpej struct pcic_handle *h = (struct pcic_handle *) pch; 1090 1.2 thorpej bus_addr_t busaddr; 1091 1.2 thorpej long card_offset; 1092 1.2 thorpej int i, win; 1093 1.35 enami struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 1094 1.2 thorpej 1095 1.2 thorpej win = -1; 1096 1.2 thorpej for (i = 0; i < (sizeof(mem_map_index) / sizeof(mem_map_index[0])); 1097 1.2 thorpej i++) { 1098 1.2 thorpej if ((h->memalloc & (1 << i)) == 0) { 1099 1.2 thorpej win = i; 1100 1.2 thorpej h->memalloc |= (1 << i); 1101 1.2 thorpej break; 1102 1.2 thorpej } 1103 1.2 thorpej } 1104 1.2 thorpej 1105 1.2 thorpej if (win == -1) 1106 1.2 thorpej return (1); 1107 1.2 thorpej 1108 1.2 thorpej *windowp = win; 1109 1.2 thorpej 1110 1.2 thorpej /* XXX this is pretty gross */ 1111 1.2 thorpej 1112 1.25 haya if (sc->memt != pcmhp->memt) 1113 1.2 thorpej panic("pcic_chip_mem_map memt is bogus"); 1114 1.2 thorpej 1115 1.2 thorpej busaddr = pcmhp->addr; 1116 1.2 thorpej 1117 1.2 thorpej /* 1118 1.2 thorpej * compute the address offset to the pcmcia address space for the 1119 1.2 thorpej * pcic. this is intentionally signed. The masks and shifts below 1120 1.2 thorpej * will cause TRT to happen in the pcic registers. Deal with making 1121 1.2 thorpej * sure the address is aligned, and return the alignment offset. 1122 1.2 thorpej */ 1123 1.2 thorpej 1124 1.2 thorpej *offsetp = card_addr % PCIC_MEM_ALIGN; 1125 1.2 thorpej card_addr -= *offsetp; 1126 1.2 thorpej 1127 1.2 thorpej DPRINTF(("pcic_chip_mem_map window %d bus %lx+%lx+%lx at card addr " 1128 1.2 thorpej "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 1129 1.2 thorpej (u_long) card_addr)); 1130 1.2 thorpej 1131 1.2 thorpej /* 1132 1.2 thorpej * include the offset in the size, and decrement size by one, since 1133 1.2 thorpej * the hw wants start/stop 1134 1.2 thorpej */ 1135 1.2 thorpej size += *offsetp - 1; 1136 1.2 thorpej 1137 1.2 thorpej card_offset = (((long) card_addr) - ((long) busaddr)); 1138 1.2 thorpej 1139 1.2 thorpej h->mem[win].addr = busaddr; 1140 1.2 thorpej h->mem[win].size = size; 1141 1.2 thorpej h->mem[win].offset = card_offset; 1142 1.2 thorpej h->mem[win].kind = kind; 1143 1.2 thorpej 1144 1.2 thorpej pcic_chip_do_mem_map(h, win); 1145 1.2 thorpej 1146 1.2 thorpej return (0); 1147 1.2 thorpej } 1148 1.2 thorpej 1149 1.2 thorpej void 1150 1.2 thorpej pcic_chip_mem_unmap(pch, window) 1151 1.2 thorpej pcmcia_chipset_handle_t pch; 1152 1.2 thorpej int window; 1153 1.2 thorpej { 1154 1.2 thorpej struct pcic_handle *h = (struct pcic_handle *) pch; 1155 1.2 thorpej int reg; 1156 1.2 thorpej 1157 1.2 thorpej if (window >= (sizeof(mem_map_index) / sizeof(mem_map_index[0]))) 1158 1.2 thorpej panic("pcic_chip_mem_unmap: window out of range"); 1159 1.2 thorpej 1160 1.2 thorpej reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1161 1.2 thorpej reg &= ~mem_map_index[window].memenable; 1162 1.2 thorpej pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1163 1.2 thorpej 1164 1.2 thorpej h->memalloc &= ~(1 << window); 1165 1.2 thorpej } 1166 1.2 thorpej 1167 1.2 thorpej int 1168 1.2 thorpej pcic_chip_io_alloc(pch, start, size, align, pcihp) 1169 1.2 thorpej pcmcia_chipset_handle_t pch; 1170 1.2 thorpej bus_addr_t start; 1171 1.2 thorpej bus_size_t size; 1172 1.2 thorpej bus_size_t align; 1173 1.2 thorpej struct pcmcia_io_handle *pcihp; 1174 1.2 thorpej { 1175 1.2 thorpej struct pcic_handle *h = (struct pcic_handle *) pch; 1176 1.2 thorpej bus_space_tag_t iot; 1177 1.2 thorpej bus_space_handle_t ioh; 1178 1.2 thorpej bus_addr_t ioaddr; 1179 1.2 thorpej int flags = 0; 1180 1.35 enami struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 1181 1.2 thorpej 1182 1.2 thorpej /* 1183 1.2 thorpej * Allocate some arbitrary I/O space. 1184 1.2 thorpej */ 1185 1.2 thorpej 1186 1.25 haya iot = sc->iot; 1187 1.2 thorpej 1188 1.2 thorpej if (start) { 1189 1.2 thorpej ioaddr = start; 1190 1.2 thorpej if (bus_space_map(iot, start, size, 0, &ioh)) 1191 1.2 thorpej return (1); 1192 1.2 thorpej DPRINTF(("pcic_chip_io_alloc map port %lx+%lx\n", 1193 1.2 thorpej (u_long) ioaddr, (u_long) size)); 1194 1.2 thorpej } else { 1195 1.2 thorpej flags |= PCMCIA_IO_ALLOCATED; 1196 1.25 haya if (bus_space_alloc(iot, sc->iobase, 1197 1.25 haya sc->iobase + sc->iosize, size, align, 0, 0, 1198 1.2 thorpej &ioaddr, &ioh)) 1199 1.2 thorpej return (1); 1200 1.2 thorpej DPRINTF(("pcic_chip_io_alloc alloc port %lx+%lx\n", 1201 1.2 thorpej (u_long) ioaddr, (u_long) size)); 1202 1.2 thorpej } 1203 1.2 thorpej 1204 1.2 thorpej pcihp->iot = iot; 1205 1.2 thorpej pcihp->ioh = ioh; 1206 1.2 thorpej pcihp->addr = ioaddr; 1207 1.2 thorpej pcihp->size = size; 1208 1.2 thorpej pcihp->flags = flags; 1209 1.2 thorpej 1210 1.2 thorpej return (0); 1211 1.2 thorpej } 1212 1.2 thorpej 1213 1.2 thorpej void 1214 1.2 thorpej pcic_chip_io_free(pch, pcihp) 1215 1.2 thorpej pcmcia_chipset_handle_t pch; 1216 1.2 thorpej struct pcmcia_io_handle *pcihp; 1217 1.2 thorpej { 1218 1.2 thorpej bus_space_tag_t iot = pcihp->iot; 1219 1.2 thorpej bus_space_handle_t ioh = pcihp->ioh; 1220 1.2 thorpej bus_size_t size = pcihp->size; 1221 1.2 thorpej 1222 1.2 thorpej if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1223 1.2 thorpej bus_space_free(iot, ioh, size); 1224 1.2 thorpej else 1225 1.2 thorpej bus_space_unmap(iot, ioh, size); 1226 1.2 thorpej } 1227 1.2 thorpej 1228 1.2 thorpej 1229 1.62 jdolecek static const struct io_map_index_st { 1230 1.2 thorpej int start_lsb; 1231 1.2 thorpej int start_msb; 1232 1.2 thorpej int stop_lsb; 1233 1.2 thorpej int stop_msb; 1234 1.2 thorpej int ioenable; 1235 1.2 thorpej int ioctlmask; 1236 1.2 thorpej int ioctlbits[3]; /* indexed by PCMCIA_WIDTH_* */ 1237 1.2 thorpej } io_map_index[] = { 1238 1.2 thorpej { 1239 1.2 thorpej PCIC_IOADDR0_START_LSB, 1240 1.2 thorpej PCIC_IOADDR0_START_MSB, 1241 1.2 thorpej PCIC_IOADDR0_STOP_LSB, 1242 1.2 thorpej PCIC_IOADDR0_STOP_MSB, 1243 1.2 thorpej PCIC_ADDRWIN_ENABLE_IO0, 1244 1.2 thorpej PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 1245 1.2 thorpej PCIC_IOCTL_IO0_IOCS16SRC_MASK | PCIC_IOCTL_IO0_DATASIZE_MASK, 1246 1.2 thorpej { 1247 1.2 thorpej PCIC_IOCTL_IO0_IOCS16SRC_CARD, 1248 1.6 enami PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1249 1.6 enami PCIC_IOCTL_IO0_DATASIZE_8BIT, 1250 1.6 enami PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1251 1.6 enami PCIC_IOCTL_IO0_DATASIZE_16BIT, 1252 1.2 thorpej }, 1253 1.2 thorpej }, 1254 1.2 thorpej { 1255 1.2 thorpej PCIC_IOADDR1_START_LSB, 1256 1.2 thorpej PCIC_IOADDR1_START_MSB, 1257 1.2 thorpej PCIC_IOADDR1_STOP_LSB, 1258 1.2 thorpej PCIC_IOADDR1_STOP_MSB, 1259 1.2 thorpej PCIC_ADDRWIN_ENABLE_IO1, 1260 1.2 thorpej PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 1261 1.2 thorpej PCIC_IOCTL_IO1_IOCS16SRC_MASK | PCIC_IOCTL_IO1_DATASIZE_MASK, 1262 1.2 thorpej { 1263 1.2 thorpej PCIC_IOCTL_IO1_IOCS16SRC_CARD, 1264 1.2 thorpej PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE | 1265 1.2 thorpej PCIC_IOCTL_IO1_DATASIZE_8BIT, 1266 1.2 thorpej PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE | 1267 1.2 thorpej PCIC_IOCTL_IO1_DATASIZE_16BIT, 1268 1.2 thorpej }, 1269 1.2 thorpej }, 1270 1.2 thorpej }; 1271 1.2 thorpej 1272 1.2 thorpej void 1273 1.2 thorpej pcic_chip_do_io_map(h, win) 1274 1.2 thorpej struct pcic_handle *h; 1275 1.2 thorpej int win; 1276 1.2 thorpej { 1277 1.2 thorpej int reg; 1278 1.2 thorpej 1279 1.2 thorpej DPRINTF(("pcic_chip_do_io_map win %d addr %lx size %lx width %d\n", 1280 1.2 thorpej win, (long) h->io[win].addr, (long) h->io[win].size, 1281 1.2 thorpej h->io[win].width * 8)); 1282 1.2 thorpej 1283 1.2 thorpej pcic_write(h, io_map_index[win].start_lsb, h->io[win].addr & 0xff); 1284 1.2 thorpej pcic_write(h, io_map_index[win].start_msb, 1285 1.2 thorpej (h->io[win].addr >> 8) & 0xff); 1286 1.2 thorpej 1287 1.2 thorpej pcic_write(h, io_map_index[win].stop_lsb, 1288 1.2 thorpej (h->io[win].addr + h->io[win].size - 1) & 0xff); 1289 1.2 thorpej pcic_write(h, io_map_index[win].stop_msb, 1290 1.2 thorpej ((h->io[win].addr + h->io[win].size - 1) >> 8) & 0xff); 1291 1.2 thorpej 1292 1.2 thorpej reg = pcic_read(h, PCIC_IOCTL); 1293 1.2 thorpej reg &= ~io_map_index[win].ioctlmask; 1294 1.2 thorpej reg |= io_map_index[win].ioctlbits[h->io[win].width]; 1295 1.2 thorpej pcic_write(h, PCIC_IOCTL, reg); 1296 1.2 thorpej 1297 1.2 thorpej reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1298 1.2 thorpej reg |= io_map_index[win].ioenable; 1299 1.2 thorpej pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1300 1.2 thorpej } 1301 1.2 thorpej 1302 1.2 thorpej int 1303 1.2 thorpej pcic_chip_io_map(pch, width, offset, size, pcihp, windowp) 1304 1.2 thorpej pcmcia_chipset_handle_t pch; 1305 1.2 thorpej int width; 1306 1.2 thorpej bus_addr_t offset; 1307 1.2 thorpej bus_size_t size; 1308 1.2 thorpej struct pcmcia_io_handle *pcihp; 1309 1.2 thorpej int *windowp; 1310 1.2 thorpej { 1311 1.2 thorpej struct pcic_handle *h = (struct pcic_handle *) pch; 1312 1.2 thorpej bus_addr_t ioaddr = pcihp->addr + offset; 1313 1.4 enami int i, win; 1314 1.4 enami #ifdef PCICDEBUG 1315 1.2 thorpej static char *width_names[] = { "auto", "io8", "io16" }; 1316 1.4 enami #endif 1317 1.35 enami struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 1318 1.2 thorpej 1319 1.2 thorpej /* XXX Sanity check offset/size. */ 1320 1.2 thorpej 1321 1.2 thorpej win = -1; 1322 1.2 thorpej for (i = 0; i < (sizeof(io_map_index) / sizeof(io_map_index[0])); i++) { 1323 1.2 thorpej if ((h->ioalloc & (1 << i)) == 0) { 1324 1.2 thorpej win = i; 1325 1.2 thorpej h->ioalloc |= (1 << i); 1326 1.2 thorpej break; 1327 1.2 thorpej } 1328 1.2 thorpej } 1329 1.2 thorpej 1330 1.2 thorpej if (win == -1) 1331 1.2 thorpej return (1); 1332 1.2 thorpej 1333 1.2 thorpej *windowp = win; 1334 1.2 thorpej 1335 1.2 thorpej /* XXX this is pretty gross */ 1336 1.2 thorpej 1337 1.25 haya if (sc->iot != pcihp->iot) 1338 1.2 thorpej panic("pcic_chip_io_map iot is bogus"); 1339 1.2 thorpej 1340 1.2 thorpej DPRINTF(("pcic_chip_io_map window %d %s port %lx+%lx\n", 1341 1.2 thorpej win, width_names[width], (u_long) ioaddr, (u_long) size)); 1342 1.2 thorpej 1343 1.2 thorpej /* XXX wtf is this doing here? */ 1344 1.2 thorpej 1345 1.72.2.1 skrll printf("%s: port 0x%lx", sc->dev.dv_xname, (u_long) ioaddr); 1346 1.2 thorpej if (size > 1) 1347 1.2 thorpej printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 1348 1.72.2.1 skrll printf("\n"); 1349 1.2 thorpej 1350 1.2 thorpej h->io[win].addr = ioaddr; 1351 1.2 thorpej h->io[win].size = size; 1352 1.2 thorpej h->io[win].width = width; 1353 1.2 thorpej 1354 1.2 thorpej pcic_chip_do_io_map(h, win); 1355 1.2 thorpej 1356 1.2 thorpej return (0); 1357 1.2 thorpej } 1358 1.2 thorpej 1359 1.2 thorpej void 1360 1.2 thorpej pcic_chip_io_unmap(pch, window) 1361 1.2 thorpej pcmcia_chipset_handle_t pch; 1362 1.2 thorpej int window; 1363 1.2 thorpej { 1364 1.2 thorpej struct pcic_handle *h = (struct pcic_handle *) pch; 1365 1.2 thorpej int reg; 1366 1.2 thorpej 1367 1.2 thorpej if (window >= (sizeof(io_map_index) / sizeof(io_map_index[0]))) 1368 1.2 thorpej panic("pcic_chip_io_unmap: window out of range"); 1369 1.2 thorpej 1370 1.2 thorpej reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1371 1.2 thorpej reg &= ~io_map_index[window].ioenable; 1372 1.2 thorpej pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1373 1.2 thorpej 1374 1.2 thorpej h->ioalloc &= ~(1 << window); 1375 1.8 marc } 1376 1.8 marc 1377 1.72.2.3 skrll static int 1378 1.8 marc pcic_wait_ready(h) 1379 1.8 marc struct pcic_handle *h; 1380 1.8 marc { 1381 1.72.2.3 skrll u_int8_t stat; 1382 1.8 marc int i; 1383 1.8 marc 1384 1.31 chopps /* wait an initial 10ms for quick cards */ 1385 1.72.2.3 skrll stat = pcic_read(h, PCIC_IF_STATUS); 1386 1.72.2.3 skrll if (stat & PCIC_IF_STATUS_READY) 1387 1.72.2.3 skrll return (0); 1388 1.36 enami pcic_delay(h, 10, "pccwr0"); 1389 1.31 chopps for (i = 0; i < 50; i++) { 1390 1.72.2.3 skrll stat = pcic_read(h, PCIC_IF_STATUS); 1391 1.72.2.3 skrll if (stat & PCIC_IF_STATUS_READY) 1392 1.72.2.3 skrll return (0); 1393 1.72.2.3 skrll if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 1394 1.72.2.3 skrll PCIC_IF_STATUS_CARDDETECT_PRESENT) 1395 1.72.2.3 skrll return (ENXIO); 1396 1.31 chopps /* wait .1s (100ms) each iteration now */ 1397 1.36 enami pcic_delay(h, 100, "pccwr1"); 1398 1.8 marc } 1399 1.8 marc 1400 1.72.2.3 skrll printf("pcic_wait_ready: ready never happened, status=%02x\n", stat); 1401 1.72.2.3 skrll return (EWOULDBLOCK); 1402 1.2 thorpej } 1403 1.2 thorpej 1404 1.30 enami /* 1405 1.30 enami * Perform long (msec order) delay. 1406 1.30 enami */ 1407 1.30 enami static void 1408 1.36 enami pcic_delay(h, timo, wmesg) 1409 1.30 enami struct pcic_handle *h; 1410 1.30 enami int timo; /* in ms. must not be zero */ 1411 1.36 enami const char *wmesg; 1412 1.30 enami { 1413 1.30 enami 1414 1.30 enami #ifdef DIAGNOSTIC 1415 1.72.2.3 skrll if (timo <= 0) 1416 1.72.2.3 skrll panic("pcic_delay: called with timeout %d", timo); 1417 1.72.2.3 skrll if (!curlwp) 1418 1.72.2.3 skrll panic("pcic_delay: called in interrupt context"); 1419 1.72.2.3 skrll if (!h->event_thread) 1420 1.72.2.3 skrll panic("pcic_delay: no event thread"); 1421 1.30 enami #endif 1422 1.48 dbj DPRINTF(("pcic_delay: \"%s\" %p, sleep %d ms\n", 1423 1.49 enami wmesg, h->event_thread, timo)); 1424 1.40 enami tsleep(pcic_delay, PWAIT, wmesg, roundup(timo * hz, 1000) / 1000); 1425 1.30 enami } 1426 1.30 enami 1427 1.2 thorpej void 1428 1.2 thorpej pcic_chip_socket_enable(pch) 1429 1.2 thorpej pcmcia_chipset_handle_t pch; 1430 1.2 thorpej { 1431 1.2 thorpej struct pcic_handle *h = (struct pcic_handle *) pch; 1432 1.72.2.3 skrll int win; 1433 1.72.2.3 skrll u_int8_t power, intr; 1434 1.72.2.3 skrll #ifdef DIAGNOSTIC 1435 1.34 chopps int reg; 1436 1.34 chopps #endif 1437 1.2 thorpej 1438 1.41 chopps #ifdef DIAGNOSTIC 1439 1.41 chopps if (h->flags & PCIC_FLAG_ENABLED) 1440 1.61 mycroft printf("pcic_chip_socket_enable: enabling twice\n"); 1441 1.41 chopps #endif 1442 1.41 chopps 1443 1.72.2.3 skrll /* disable interrupts; assert RESET */ 1444 1.39 enami intr = pcic_read(h, PCIC_INTR); 1445 1.72.2.3 skrll intr &= PCIC_INTR_ENABLE; 1446 1.34 chopps pcic_write(h, PCIC_INTR, intr); 1447 1.2 thorpej 1448 1.72.2.2 skrll /* zero out the address windows */ 1449 1.72.2.2 skrll pcic_write(h, PCIC_ADDRWIN_ENABLE, 0); 1450 1.72.2.2 skrll 1451 1.72.2.3 skrll /* power off; assert output enable bit */ 1452 1.72.2.3 skrll power = PCIC_PWRCTL_OE; 1453 1.72.2.3 skrll pcic_write(h, PCIC_PWRCTL, power); 1454 1.69 takemura 1455 1.69 takemura /* 1456 1.69 takemura * power hack for RICOH RF5C[23]96 1457 1.69 takemura */ 1458 1.69 takemura switch( h->vendor ) { 1459 1.69 takemura case PCIC_VENDOR_RICOH_5C296: 1460 1.69 takemura case PCIC_VENDOR_RICOH_5C396: 1461 1.72.2.1 skrll { 1462 1.72.2.1 skrll int regtmp; 1463 1.69 takemura regtmp = pcic_read(h, PCIC_RICOH_REG_MCR2); 1464 1.72.2.1 skrll #ifdef RICOH_POWER_HACK 1465 1.72.2.1 skrll regtmp |= PCIC_RICOH_MCR2_VCC_DIRECT; 1466 1.72.2.1 skrll #else 1467 1.72.2.1 skrll regtmp &= ~(PCIC_RICOH_MCR2_VCC_DIRECT|PCIC_RICOH_MCR2_VCC_SEL_3V); 1468 1.72.2.1 skrll #endif 1469 1.69 takemura pcic_write(h, PCIC_RICOH_REG_MCR2, regtmp); 1470 1.72.2.1 skrll } 1471 1.69 takemura break; 1472 1.69 takemura default: 1473 1.69 takemura break; 1474 1.69 takemura } 1475 1.9 enami 1476 1.22 mycroft #ifdef VADEM_POWER_HACK 1477 1.25 haya bus_space_write_1(sc->iot, sc->ioh, PCIC_REG_INDEX, 0x0e); 1478 1.25 haya bus_space_write_1(sc->iot, sc->ioh, PCIC_REG_INDEX, 0x37); 1479 1.22 mycroft printf("prcr = %02x\n", pcic_read(h, 0x02)); 1480 1.22 mycroft printf("cvsr = %02x\n", pcic_read(h, 0x2f)); 1481 1.22 mycroft printf("DANGER WILL ROBINSON! Changing voltage select!\n"); 1482 1.22 mycroft pcic_write(h, 0x2f, pcic_read(h, 0x2f) & ~0x03); 1483 1.22 mycroft printf("cvsr = %02x\n", pcic_read(h, 0x2f)); 1484 1.22 mycroft #endif 1485 1.72.2.3 skrll 1486 1.2 thorpej /* power up the socket */ 1487 1.72.2.3 skrll power |= PCIC_PWRCTL_PWR_ENABLE | PCIC_PWRCTL_VPP1_VCC; 1488 1.72.2.3 skrll pcic_write(h, PCIC_PWRCTL, power); 1489 1.9 enami 1490 1.9 enami /* 1491 1.72.2.3 skrll * Table 4-18 and figure 4-6 of the PC Card specifiction say: 1492 1.72.2.3 skrll * Vcc Rising Time (Tpr) = 100ms 1493 1.72.2.3 skrll * RESET Width (Th (Hi-z RESET)) = 1ms 1494 1.72.2.3 skrll * RESET Width (Tw (RESET)) = 10us 1495 1.12 msaitoh * 1496 1.12 msaitoh * some machines require some more time to be settled 1497 1.72.2.3 skrll * (100ms is added here). 1498 1.9 enami */ 1499 1.72.2.3 skrll pcic_delay(h, 200 + 1, "pccen1"); 1500 1.38 chopps 1501 1.72.2.3 skrll /* negate RESET */ 1502 1.72.2.3 skrll intr |= PCIC_INTR_RESET; 1503 1.38 chopps pcic_write(h, PCIC_INTR, intr); 1504 1.9 enami 1505 1.9 enami /* 1506 1.72.2.3 skrll * RESET Setup Time (Tsu (RESET)) = 20ms 1507 1.9 enami */ 1508 1.30 enami pcic_delay(h, 20, "pccen2"); 1509 1.2 thorpej 1510 1.20 msaitoh #ifdef DIAGNOSTIC 1511 1.72.2.3 skrll reg = pcic_read(h, PCIC_IF_STATUS); 1512 1.72.2.3 skrll if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 1513 1.72.2.3 skrll printf("pcic_chip_socket_enable: no power, status=%x\n", reg); 1514 1.20 msaitoh #endif 1515 1.72.2.3 skrll 1516 1.38 chopps /* wait for the chip to finish initializing */ 1517 1.72.2.3 skrll if (pcic_wait_ready(h)) { 1518 1.72.2.3 skrll /* XXX return a failure status?? */ 1519 1.72.2.3 skrll pcic_write(h, PCIC_PWRCTL, 0); 1520 1.72.2.3 skrll return; 1521 1.72.2.3 skrll } 1522 1.2 thorpej 1523 1.2 thorpej /* reinstall all the memory and io mappings */ 1524 1.2 thorpej for (win = 0; win < PCIC_MEM_WINS; win++) 1525 1.2 thorpej if (h->memalloc & (1 << win)) 1526 1.2 thorpej pcic_chip_do_mem_map(h, win); 1527 1.2 thorpej for (win = 0; win < PCIC_IO_WINS; win++) 1528 1.2 thorpej if (h->ioalloc & (1 << win)) 1529 1.2 thorpej pcic_chip_do_io_map(h, win); 1530 1.34 chopps 1531 1.41 chopps h->flags |= PCIC_FLAG_ENABLED; 1532 1.2 thorpej } 1533 1.2 thorpej 1534 1.2 thorpej void 1535 1.2 thorpej pcic_chip_socket_disable(pch) 1536 1.2 thorpej pcmcia_chipset_handle_t pch; 1537 1.2 thorpej { 1538 1.2 thorpej struct pcic_handle *h = (struct pcic_handle *) pch; 1539 1.72.2.3 skrll u_int8_t intr; 1540 1.2 thorpej 1541 1.2 thorpej DPRINTF(("pcic_chip_socket_disable\n")); 1542 1.38 chopps 1543 1.72.2.3 skrll /* disable interrupts; assert RESET */ 1544 1.39 enami intr = pcic_read(h, PCIC_INTR); 1545 1.72.2.3 skrll intr &= PCIC_INTR_ENABLE; 1546 1.38 chopps pcic_write(h, PCIC_INTR, intr); 1547 1.2 thorpej 1548 1.52 mycroft /* zero out the address windows */ 1549 1.52 mycroft pcic_write(h, PCIC_ADDRWIN_ENABLE, 0); 1550 1.41 chopps 1551 1.72.2.3 skrll /* disable socket: negate output enable bit and power off */ 1552 1.72.2.2 skrll pcic_write(h, PCIC_PWRCTL, 0); 1553 1.72.2.2 skrll 1554 1.72.2.3 skrll /* 1555 1.72.2.3 skrll * Vcc Falling Time (Tpf) = 300ms 1556 1.72.2.3 skrll */ 1557 1.72.2.3 skrll pcic_delay(h, 300, "pccwr1"); 1558 1.72.2.3 skrll 1559 1.41 chopps h->flags &= ~PCIC_FLAG_ENABLED; 1560 1.25 haya } 1561 1.25 haya 1562 1.72.2.2 skrll void 1563 1.72.2.2 skrll pcic_chip_socket_settype(pch, type) 1564 1.72.2.2 skrll pcmcia_chipset_handle_t pch; 1565 1.72.2.2 skrll int type; 1566 1.72.2.2 skrll { 1567 1.72.2.2 skrll struct pcic_handle *h = (struct pcic_handle *) pch; 1568 1.72.2.2 skrll int intr; 1569 1.72.2.2 skrll 1570 1.72.2.2 skrll intr = pcic_read(h, PCIC_INTR); 1571 1.72.2.2 skrll intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 1572 1.72.2.2 skrll if (type == PCMCIA_IFTYPE_IO) { 1573 1.72.2.2 skrll intr |= PCIC_INTR_CARDTYPE_IO; 1574 1.72.2.2 skrll intr |= h->ih_irq << PCIC_INTR_IRQ_SHIFT; 1575 1.72.2.2 skrll } else 1576 1.72.2.2 skrll intr |= PCIC_INTR_CARDTYPE_MEM; 1577 1.72.2.2 skrll pcic_write(h, PCIC_INTR, intr); 1578 1.72.2.2 skrll 1579 1.72.2.2 skrll DPRINTF(("%s: pcic_chip_socket_settype %02x type %s %02x\n", 1580 1.72.2.2 skrll h->ph_parent->dv_xname, h->sock, 1581 1.72.2.2 skrll ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 1582 1.72.2.2 skrll } 1583 1.72.2.2 skrll 1584 1.25 haya static u_int8_t 1585 1.25 haya st_pcic_read(h, idx) 1586 1.27 sommerfe struct pcic_handle *h; 1587 1.27 sommerfe int idx; 1588 1.25 haya { 1589 1.35 enami 1590 1.27 sommerfe if (idx != -1) 1591 1.27 sommerfe bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_INDEX, 1592 1.27 sommerfe h->sock + idx); 1593 1.35 enami return (bus_space_read_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_DATA)); 1594 1.25 haya } 1595 1.25 haya 1596 1.25 haya static void 1597 1.25 haya st_pcic_write(h, idx, data) 1598 1.27 sommerfe struct pcic_handle *h; 1599 1.27 sommerfe int idx; 1600 1.27 sommerfe u_int8_t data; 1601 1.27 sommerfe { 1602 1.35 enami 1603 1.27 sommerfe if (idx != -1) 1604 1.27 sommerfe bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_INDEX, 1605 1.27 sommerfe h->sock + idx); 1606 1.27 sommerfe bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_DATA, data); 1607 1.2 thorpej } 1608
Indexes created Mon Oct 27 17:09:47 GMT 2025