i82365.c revision 1.72.2.7
1 1.72.2.7 skrll /* $NetBSD: i82365.c,v 1.72.2.7 2005/03/04 16:41:28 skrll Exp $ */ 2 1.72.2.3 skrll 3 1.72.2.3 skrll /* 4 1.72.2.3 skrll * Copyright (c) 2004 Charles M. Hannum. All rights reserved. 5 1.72.2.3 skrll * 6 1.72.2.3 skrll * Redistribution and use in source and binary forms, with or without 7 1.72.2.3 skrll * modification, are permitted provided that the following conditions 8 1.72.2.3 skrll * are met: 9 1.72.2.3 skrll * 1. Redistributions of source code must retain the above copyright 10 1.72.2.3 skrll * notice, this list of conditions and the following disclaimer. 11 1.72.2.3 skrll * 2. Redistributions in binary form must reproduce the above copyright 12 1.72.2.3 skrll * notice, this list of conditions and the following disclaimer in the 13 1.72.2.3 skrll * documentation and/or other materials provided with the distribution. 14 1.72.2.3 skrll * 3. All advertising materials mentioning features or use of this software 15 1.72.2.3 skrll * must display the following acknowledgement: 16 1.72.2.3 skrll * This product includes software developed by Charles M. Hannum. 17 1.72.2.3 skrll * 4. The name of the author may not be used to endorse or promote products 18 1.72.2.3 skrll * derived from this software without specific prior written permission. 19 1.72.2.3 skrll */ 20 1.2 thorpej 21 1.2 thorpej /* 22 1.33 chopps * Copyright (c) 2000 Christian E. Hopps. All rights reserved. 23 1.2 thorpej * Copyright (c) 1997 Marc Horowitz. All rights reserved. 24 1.2 thorpej * 25 1.2 thorpej * Redistribution and use in source and binary forms, with or without 26 1.2 thorpej * modification, are permitted provided that the following conditions 27 1.2 thorpej * are met: 28 1.2 thorpej * 1. Redistributions of source code must retain the above copyright 29 1.2 thorpej * notice, this list of conditions and the following disclaimer. 30 1.2 thorpej * 2. Redistributions in binary form must reproduce the above copyright 31 1.2 thorpej * notice, this list of conditions and the following disclaimer in the 32 1.2 thorpej * documentation and/or other materials provided with the distribution. 33 1.2 thorpej * 3. All advertising materials mentioning features or use of this software 34 1.2 thorpej * must display the following acknowledgement: 35 1.2 thorpej * This product includes software developed by Marc Horowitz. 36 1.2 thorpej * 4. The name of the author may not be used to endorse or promote products 37 1.2 thorpej * derived from this software without specific prior written permission. 38 1.2 thorpej * 39 1.2 thorpej * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 40 1.2 thorpej * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 41 1.2 thorpej * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 42 1.2 thorpej * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 43 1.2 thorpej * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 44 1.2 thorpej * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 45 1.2 thorpej * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 46 1.2 thorpej * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 47 1.2 thorpej * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 48 1.2 thorpej * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 49 1.2 thorpej */ 50 1.63 lukem 51 1.63 lukem #include <sys/cdefs.h> 52 1.72.2.7 skrll __KERNEL_RCSID(0, "$NetBSD: i82365.c,v 1.72.2.7 2005/03/04 16:41:28 skrll Exp $"); 53 1.63 lukem 54 1.63 lukem #define PCICDEBUG 55 1.2 thorpej 56 1.2 thorpej #include <sys/param.h> 57 1.2 thorpej #include <sys/systm.h> 58 1.2 thorpej #include <sys/device.h> 59 1.2 thorpej #include <sys/extent.h> 60 1.20 msaitoh #include <sys/kernel.h> 61 1.2 thorpej #include <sys/malloc.h> 62 1.14 thorpej #include <sys/kthread.h> 63 1.2 thorpej 64 1.2 thorpej #include <machine/bus.h> 65 1.2 thorpej #include <machine/intr.h> 66 1.2 thorpej 67 1.2 thorpej #include <dev/pcmcia/pcmciareg.h> 68 1.2 thorpej #include <dev/pcmcia/pcmciavar.h> 69 1.2 thorpej 70 1.2 thorpej #include <dev/ic/i82365reg.h> 71 1.2 thorpej #include <dev/ic/i82365var.h> 72 1.2 thorpej 73 1.72.2.4 skrll #include "locators.h" 74 1.72.2.4 skrll 75 1.2 thorpej #ifdef PCICDEBUG 76 1.2 thorpej int pcic_debug = 0; 77 1.2 thorpej #define DPRINTF(arg) if (pcic_debug) printf arg; 78 1.2 thorpej #else 79 1.2 thorpej #define DPRINTF(arg) 80 1.2 thorpej #endif 81 1.2 thorpej 82 1.2 thorpej /* 83 1.2 thorpej * Individual drivers will allocate their own memory and io regions. Memory 84 1.2 thorpej * regions must be a multiple of 4k, aligned on a 4k boundary. 85 1.2 thorpej */ 86 1.2 thorpej 87 1.2 thorpej #define PCIC_MEM_ALIGN PCIC_MEM_PAGESIZE 88 1.2 thorpej 89 1.72.2.6 skrll void pcic_attach_socket(struct pcic_handle *); 90 1.72.2.6 skrll void pcic_attach_socket_finish(struct pcic_handle *); 91 1.2 thorpej 92 1.72.2.6 skrll int pcic_submatch(struct device *, struct cfdata *, 93 1.72.2.6 skrll const locdesc_t *, void *); 94 1.72.2.6 skrll int pcic_print (void *arg, const char *pnp); 95 1.72.2.6 skrll int pcic_intr_socket(struct pcic_handle *); 96 1.72.2.6 skrll void pcic_poll_intr(void *); 97 1.2 thorpej 98 1.72.2.6 skrll void pcic_attach_card(struct pcic_handle *); 99 1.72.2.6 skrll void pcic_detach_card(struct pcic_handle *, int); 100 1.72.2.6 skrll void pcic_deactivate_card(struct pcic_handle *); 101 1.2 thorpej 102 1.72.2.6 skrll void pcic_chip_do_mem_map(struct pcic_handle *, int); 103 1.72.2.6 skrll void pcic_chip_do_io_map(struct pcic_handle *, int); 104 1.2 thorpej 105 1.72.2.6 skrll void pcic_create_event_thread(void *); 106 1.72.2.6 skrll void pcic_event_thread(void *); 107 1.14 thorpej 108 1.72.2.6 skrll void pcic_queue_event(struct pcic_handle *, int); 109 1.72.2.6 skrll void pcic_power(int, void *); 110 1.14 thorpej 111 1.72.2.6 skrll static int pcic_wait_ready(struct pcic_handle *); 112 1.72.2.6 skrll static void pcic_delay(struct pcic_handle *, int, const char *); 113 1.8 marc 114 1.72.2.6 skrll static u_int8_t st_pcic_read(struct pcic_handle *, int); 115 1.72.2.6 skrll static void st_pcic_write(struct pcic_handle *, int, u_int8_t); 116 1.25 haya 117 1.2 thorpej int 118 1.2 thorpej pcic_ident_ok(ident) 119 1.2 thorpej int ident; 120 1.2 thorpej { 121 1.2 thorpej /* this is very empirical and heuristic */ 122 1.2 thorpej 123 1.2 thorpej if ((ident == 0) || (ident == 0xff) || (ident & PCIC_IDENT_ZERO)) 124 1.2 thorpej return (0); 125 1.2 thorpej 126 1.72.2.1 skrll if ((ident & PCIC_IDENT_REV_MASK) == 0) 127 1.72.2.1 skrll return (0); 128 1.72.2.1 skrll 129 1.2 thorpej if ((ident & PCIC_IDENT_IFTYPE_MASK) != PCIC_IDENT_IFTYPE_MEM_AND_IO) { 130 1.2 thorpej #ifdef DIAGNOSTIC 131 1.2 thorpej printf("pcic: does not support memory and I/O cards, " 132 1.2 thorpej "ignored (ident=%0x)\n", ident); 133 1.2 thorpej #endif 134 1.2 thorpej return (0); 135 1.2 thorpej } 136 1.72.2.1 skrll 137 1.2 thorpej return (1); 138 1.2 thorpej } 139 1.2 thorpej 140 1.2 thorpej int 141 1.2 thorpej pcic_vendor(h) 142 1.2 thorpej struct pcic_handle *h; 143 1.2 thorpej { 144 1.2 thorpej int reg; 145 1.69 takemura int vendor; 146 1.2 thorpej 147 1.2 thorpej reg = pcic_read(h, PCIC_IDENT); 148 1.2 thorpej 149 1.72.2.1 skrll if ((reg & PCIC_IDENT_REV_MASK) == 0) 150 1.72.2.1 skrll return (PCIC_VENDOR_NONE); 151 1.72.2.1 skrll 152 1.69 takemura switch (reg) { 153 1.72.2.1 skrll case 0x00: 154 1.72.2.1 skrll case 0xff: 155 1.72.2.1 skrll return (PCIC_VENDOR_NONE); 156 1.69 takemura case PCIC_IDENT_ID_INTEL0: 157 1.69 takemura vendor = PCIC_VENDOR_I82365SLR0; 158 1.69 takemura break; 159 1.69 takemura case PCIC_IDENT_ID_INTEL1: 160 1.69 takemura vendor = PCIC_VENDOR_I82365SLR1; 161 1.69 takemura break; 162 1.69 takemura case PCIC_IDENT_ID_INTEL2: 163 1.69 takemura vendor = PCIC_VENDOR_I82365SL_DF; 164 1.69 takemura break; 165 1.69 takemura case PCIC_IDENT_ID_IBM1: 166 1.69 takemura case PCIC_IDENT_ID_IBM2: 167 1.69 takemura vendor = PCIC_VENDOR_IBM; 168 1.69 takemura break; 169 1.69 takemura case PCIC_IDENT_ID_IBM3: 170 1.69 takemura vendor = PCIC_VENDOR_IBM_KING; 171 1.69 takemura break; 172 1.69 takemura default: 173 1.69 takemura vendor = PCIC_VENDOR_UNKNOWN; 174 1.69 takemura break; 175 1.69 takemura } 176 1.69 takemura 177 1.69 takemura if (vendor == PCIC_VENDOR_I82365SLR0 || 178 1.69 takemura vendor == PCIC_VENDOR_I82365SLR1) { 179 1.69 takemura /* 180 1.72.2.1 skrll * Check for Cirrus PD67xx. 181 1.72.2.1 skrll * the chip_id of the cirrus toggles between 11 and 00 after a 182 1.72.2.1 skrll * write. weird. 183 1.72.2.1 skrll */ 184 1.72.2.1 skrll pcic_write(h, PCIC_CIRRUS_CHIP_INFO, 0); 185 1.72.2.1 skrll reg = pcic_read(h, -1); 186 1.72.2.1 skrll if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) == 187 1.72.2.1 skrll PCIC_CIRRUS_CHIP_INFO_CHIP_ID) { 188 1.72.2.1 skrll reg = pcic_read(h, -1); 189 1.72.2.1 skrll if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) == 0) 190 1.72.2.1 skrll return (PCIC_VENDOR_CIRRUS_PD67XX); 191 1.72.2.1 skrll } 192 1.72.2.1 skrll 193 1.72.2.1 skrll /* 194 1.69 takemura * check for Ricoh RF5C[23]96 195 1.69 takemura */ 196 1.69 takemura reg = pcic_read(h, PCIC_RICOH_REG_CHIP_ID); 197 1.69 takemura switch (reg) { 198 1.69 takemura case PCIC_RICOH_CHIP_ID_5C296: 199 1.72.2.1 skrll return (PCIC_VENDOR_RICOH_5C296); 200 1.69 takemura case PCIC_RICOH_CHIP_ID_5C396: 201 1.72.2.1 skrll return (PCIC_VENDOR_RICOH_5C396); 202 1.69 takemura } 203 1.69 takemura } 204 1.69 takemura 205 1.72.2.1 skrll return (vendor); 206 1.2 thorpej } 207 1.2 thorpej 208 1.2 thorpej char * 209 1.2 thorpej pcic_vendor_to_string(vendor) 210 1.2 thorpej int vendor; 211 1.2 thorpej { 212 1.2 thorpej switch (vendor) { 213 1.2 thorpej case PCIC_VENDOR_I82365SLR0: 214 1.2 thorpej return ("Intel 82365SL Revision 0"); 215 1.2 thorpej case PCIC_VENDOR_I82365SLR1: 216 1.2 thorpej return ("Intel 82365SL Revision 1"); 217 1.72.2.1 skrll case PCIC_VENDOR_CIRRUS_PD67XX: 218 1.72.2.1 skrll return ("Cirrus PD6710/2X"); 219 1.69 takemura case PCIC_VENDOR_I82365SL_DF: 220 1.69 takemura return ("Intel 82365SL-DF"); 221 1.69 takemura case PCIC_VENDOR_RICOH_5C296: 222 1.69 takemura return ("Ricoh RF5C296"); 223 1.69 takemura case PCIC_VENDOR_RICOH_5C396: 224 1.69 takemura return ("Ricoh RF5C396"); 225 1.69 takemura case PCIC_VENDOR_IBM: 226 1.69 takemura return ("IBM PCIC"); 227 1.69 takemura case PCIC_VENDOR_IBM_KING: 228 1.69 takemura return ("IBM KING"); 229 1.2 thorpej } 230 1.2 thorpej 231 1.2 thorpej return ("Unknown controller"); 232 1.2 thorpej } 233 1.2 thorpej 234 1.2 thorpej void 235 1.2 thorpej pcic_attach(sc) 236 1.2 thorpej struct pcic_softc *sc; 237 1.2 thorpej { 238 1.72.2.1 skrll int i, reg, chip, socket; 239 1.54 mycroft struct pcic_handle *h; 240 1.2 thorpej 241 1.33 chopps DPRINTF(("pcic ident regs:")); 242 1.2 thorpej 243 1.53 thorpej lockinit(&sc->sc_pcic_lock, PWAIT, "pciclk", 0, 0); 244 1.53 thorpej 245 1.33 chopps /* find and configure for the available sockets */ 246 1.33 chopps for (i = 0; i < PCIC_NSLOTS; i++) { 247 1.54 mycroft h = &sc->handle[i]; 248 1.33 chopps chip = i / 2; 249 1.33 chopps socket = i % 2; 250 1.54 mycroft 251 1.54 mycroft h->ph_parent = (struct device *)sc; 252 1.54 mycroft h->chip = chip; 253 1.72.2.4 skrll h->socket = socket; 254 1.54 mycroft h->sock = chip * PCIC_CHIP_OFFSET + socket * PCIC_SOCKET_OFFSET; 255 1.54 mycroft h->laststate = PCIC_LASTSTATE_EMPTY; 256 1.35 enami /* initialize pcic_read and pcic_write functions */ 257 1.54 mycroft h->ph_read = st_pcic_read; 258 1.54 mycroft h->ph_write = st_pcic_write; 259 1.54 mycroft h->ph_bus_t = sc->iot; 260 1.54 mycroft h->ph_bus_h = sc->ioh; 261 1.72.2.1 skrll h->flags = 0; 262 1.54 mycroft 263 1.33 chopps /* need to read vendor -- for cirrus to report no xtra chip */ 264 1.33 chopps if (socket == 0) 265 1.54 mycroft h->vendor = (h+1)->vendor = pcic_vendor(h); 266 1.54 mycroft 267 1.72.2.1 skrll switch (h->vendor) { 268 1.72.2.1 skrll case PCIC_VENDOR_NONE: 269 1.72.2.1 skrll /* no chip */ 270 1.72.2.1 skrll continue; 271 1.72.2.1 skrll case PCIC_VENDOR_CIRRUS_PD67XX: 272 1.72.2.1 skrll reg = pcic_read(h, PCIC_CIRRUS_CHIP_INFO); 273 1.72.2.1 skrll if (socket == 0 || 274 1.72.2.1 skrll (reg & PCIC_CIRRUS_CHIP_INFO_SLOTS)) 275 1.72.2.1 skrll h->flags = PCIC_FLAG_SOCKETP; 276 1.72.2.1 skrll break; 277 1.72.2.7 skrll default: 278 1.72.2.1 skrll /* 279 1.72.2.1 skrll * During the socket probe, read the ident register 280 1.72.2.1 skrll * twice. I don't understand why, but sometimes the 281 1.72.2.1 skrll * clone chips in hpcmips boxes read all-0s the first 282 1.72.2.1 skrll * time. -- mycroft 283 1.72.2.1 skrll */ 284 1.72.2.1 skrll reg = pcic_read(h, PCIC_IDENT); 285 1.72.2.1 skrll DPRINTF(("socket %d ident reg 0x%02x\n", i, reg)); 286 1.72.2.1 skrll reg = pcic_read(h, PCIC_IDENT); 287 1.72.2.1 skrll DPRINTF(("socket %d ident reg 0x%02x\n", i, reg)); 288 1.72.2.1 skrll if (pcic_ident_ok(reg)) 289 1.72.2.1 skrll h->flags = PCIC_FLAG_SOCKETP; 290 1.72.2.1 skrll break; 291 1.72.2.1 skrll } 292 1.2 thorpej } 293 1.2 thorpej 294 1.2 thorpej for (i = 0; i < PCIC_NSLOTS; i++) { 295 1.54 mycroft h = &sc->handle[i]; 296 1.54 mycroft 297 1.54 mycroft if (h->flags & PCIC_FLAG_SOCKETP) { 298 1.54 mycroft SIMPLEQ_INIT(&h->events); 299 1.33 chopps 300 1.72.2.1 skrll /* disable interrupts and leave socket in reset */ 301 1.72.2.1 skrll pcic_write(h, PCIC_INTR, 0); 302 1.72.2.3 skrll 303 1.72.2.3 skrll /* zero out the address windows */ 304 1.72.2.3 skrll pcic_write(h, PCIC_ADDRWIN_ENABLE, 0); 305 1.72.2.3 skrll 306 1.72.2.3 skrll /* power down the socket */ 307 1.72.2.3 skrll pcic_write(h, PCIC_PWRCTL, 0); 308 1.72.2.3 skrll 309 1.72.2.3 skrll pcic_write(h, PCIC_CSC_INTR, 0); 310 1.54 mycroft (void) pcic_read(h, PCIC_CSC); 311 1.2 thorpej } 312 1.2 thorpej } 313 1.2 thorpej 314 1.33 chopps /* print detected info */ 315 1.33 chopps for (i = 0; i < PCIC_NSLOTS; i += 2) { 316 1.54 mycroft h = &sc->handle[i]; 317 1.33 chopps chip = i / 2; 318 1.2 thorpej 319 1.72.2.1 skrll if (h->vendor == PCIC_VENDOR_NONE) 320 1.72.2.1 skrll continue; 321 1.72.2.1 skrll 322 1.72 thorpej aprint_normal("%s: controller %d (%s) has ", sc->dev.dv_xname, 323 1.72 thorpej chip, pcic_vendor_to_string(sc->handle[i].vendor)); 324 1.2 thorpej 325 1.54 mycroft if ((h->flags & PCIC_FLAG_SOCKETP) && 326 1.54 mycroft ((h+1)->flags & PCIC_FLAG_SOCKETP)) 327 1.72 thorpej aprint_normal("sockets A and B\n"); 328 1.54 mycroft else if (h->flags & PCIC_FLAG_SOCKETP) 329 1.72 thorpej aprint_normal("socket A only\n"); 330 1.54 mycroft else if ((h+1)->flags & PCIC_FLAG_SOCKETP) 331 1.72 thorpej aprint_normal("socket B only\n"); 332 1.2 thorpej else 333 1.72 thorpej aprint_normal("no sockets\n"); 334 1.2 thorpej } 335 1.2 thorpej } 336 1.2 thorpej 337 1.33 chopps /* 338 1.33 chopps * attach the sockets before we know what interrupts we have 339 1.33 chopps */ 340 1.2 thorpej void 341 1.2 thorpej pcic_attach_sockets(sc) 342 1.2 thorpej struct pcic_softc *sc; 343 1.2 thorpej { 344 1.2 thorpej int i; 345 1.2 thorpej 346 1.2 thorpej for (i = 0; i < PCIC_NSLOTS; i++) 347 1.2 thorpej if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 348 1.2 thorpej pcic_attach_socket(&sc->handle[i]); 349 1.2 thorpej } 350 1.2 thorpej 351 1.2 thorpej void 352 1.49 enami pcic_power(why, arg) 353 1.26 sommerfe int why; 354 1.26 sommerfe void *arg; 355 1.26 sommerfe { 356 1.26 sommerfe struct pcic_handle *h = (struct pcic_handle *)arg; 357 1.35 enami struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 358 1.33 chopps int reg; 359 1.33 chopps 360 1.33 chopps DPRINTF(("%s: power: why %d\n", h->ph_parent->dv_xname, why)); 361 1.26 sommerfe 362 1.26 sommerfe if (h->flags & PCIC_FLAG_SOCKETP) { 363 1.26 sommerfe if ((why == PWR_RESUME) && 364 1.26 sommerfe (pcic_read(h, PCIC_CSC_INTR) == 0)) { 365 1.26 sommerfe #ifdef PCICDEBUG 366 1.26 sommerfe char bitbuf[64]; 367 1.26 sommerfe #endif 368 1.33 chopps reg = PCIC_CSC_INTR_CD_ENABLE; 369 1.33 chopps if (sc->irq != -1) 370 1.33 chopps reg |= sc->irq << PCIC_CSC_INTR_IRQ_SHIFT; 371 1.33 chopps pcic_write(h, PCIC_CSC_INTR, reg); 372 1.26 sommerfe DPRINTF(("%s: CSC_INTR was zero; reset to %s\n", 373 1.26 sommerfe sc->dev.dv_xname, 374 1.26 sommerfe bitmask_snprintf(pcic_read(h, PCIC_CSC_INTR), 375 1.26 sommerfe PCIC_CSC_INTR_FORMAT, 376 1.26 sommerfe bitbuf, sizeof(bitbuf)))); 377 1.26 sommerfe } 378 1.42 itojun 379 1.42 itojun /* 380 1.42 itojun * check for card insertion or removal during suspend period. 381 1.42 itojun * XXX: the code can't cope with card swap (remove then insert). 382 1.42 itojun * how can we detect such situation? 383 1.42 itojun */ 384 1.42 itojun if (why == PWR_RESUME) 385 1.42 itojun (void)pcic_intr_socket(h); 386 1.26 sommerfe } 387 1.26 sommerfe } 388 1.26 sommerfe 389 1.26 sommerfe 390 1.33 chopps /* 391 1.33 chopps * attach a socket -- we don't know about irqs yet 392 1.33 chopps */ 393 1.26 sommerfe void 394 1.2 thorpej pcic_attach_socket(h) 395 1.2 thorpej struct pcic_handle *h; 396 1.2 thorpej { 397 1.2 thorpej struct pcmciabus_attach_args paa; 398 1.35 enami struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 399 1.72.2.4 skrll int help[3]; 400 1.72.2.4 skrll locdesc_t *ldesc = (void *)help; /* XXX */ 401 1.2 thorpej 402 1.2 thorpej /* initialize the rest of the handle */ 403 1.2 thorpej 404 1.14 thorpej h->shutdown = 0; 405 1.2 thorpej h->memalloc = 0; 406 1.2 thorpej h->ioalloc = 0; 407 1.2 thorpej h->ih_irq = 0; 408 1.2 thorpej 409 1.2 thorpej /* now, config one pcmcia device per socket */ 410 1.2 thorpej 411 1.25 haya paa.paa_busname = "pcmcia"; 412 1.25 haya paa.pct = (pcmcia_chipset_tag_t) sc->pct; 413 1.2 thorpej paa.pch = (pcmcia_chipset_handle_t) h; 414 1.25 haya paa.iobase = sc->iobase; 415 1.25 haya paa.iosize = sc->iosize; 416 1.2 thorpej 417 1.72.2.4 skrll ldesc->len = 2; 418 1.72.2.4 skrll ldesc->locs[PCMCIABUSCF_CONTROLLER] = h->chip; 419 1.72.2.4 skrll ldesc->locs[PCMCIABUSCF_SOCKET] = h->socket; 420 1.72.2.4 skrll 421 1.72.2.4 skrll h->pcmcia = config_found_sm_loc(&sc->dev, "pcmciabus", ldesc, &paa, 422 1.72.2.4 skrll pcic_print, pcic_submatch); 423 1.50 mycroft if (h->pcmcia == NULL) { 424 1.50 mycroft h->flags &= ~PCIC_FLAG_SOCKETP; 425 1.33 chopps return; 426 1.50 mycroft } 427 1.2 thorpej 428 1.33 chopps /* 429 1.33 chopps * queue creation of a kernel thread to handle insert/removal events. 430 1.33 chopps */ 431 1.33 chopps #ifdef DIAGNOSTIC 432 1.33 chopps if (h->event_thread != NULL) 433 1.33 chopps panic("pcic_attach_socket: event thread"); 434 1.33 chopps #endif 435 1.33 chopps config_pending_incr(); 436 1.33 chopps kthread_create(pcic_create_event_thread, h); 437 1.33 chopps } 438 1.2 thorpej 439 1.33 chopps /* 440 1.33 chopps * now finish attaching the sockets, we are ready to allocate 441 1.33 chopps * interrupts 442 1.33 chopps */ 443 1.33 chopps void 444 1.33 chopps pcic_attach_sockets_finish(sc) 445 1.33 chopps struct pcic_softc *sc; 446 1.33 chopps { 447 1.33 chopps int i; 448 1.33 chopps 449 1.33 chopps for (i = 0; i < PCIC_NSLOTS; i++) 450 1.51 mycroft if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 451 1.33 chopps pcic_attach_socket_finish(&sc->handle[i]); 452 1.33 chopps } 453 1.33 chopps 454 1.33 chopps /* 455 1.33 chopps * finishing attaching the socket. Interrupts may now be on 456 1.33 chopps * if so expects the pcic interrupt to be blocked 457 1.33 chopps */ 458 1.33 chopps void 459 1.33 chopps pcic_attach_socket_finish(h) 460 1.33 chopps struct pcic_handle *h; 461 1.33 chopps { 462 1.35 enami struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 463 1.72.2.3 skrll int reg; 464 1.33 chopps 465 1.46 nathanw DPRINTF(("%s: attach finish socket %ld\n", h->ph_parent->dv_xname, 466 1.46 nathanw (long) (h - &sc->handle[0]))); 467 1.51 mycroft 468 1.33 chopps /* 469 1.33 chopps * Set up a powerhook to ensure it continues to interrupt on 470 1.33 chopps * card detect even after suspend. 471 1.33 chopps * (this works around a bug seen in suspend-to-disk on the 472 1.33 chopps * Sony VAIO Z505; on resume, the CSC_INTR state is not preserved). 473 1.33 chopps */ 474 1.33 chopps powerhook_establish(pcic_power, h); 475 1.33 chopps 476 1.33 chopps /* enable interrupts on card detect, poll for them if no irq avail */ 477 1.33 chopps reg = PCIC_CSC_INTR_CD_ENABLE; 478 1.57 thorpej if (sc->irq == -1) { 479 1.57 thorpej if (sc->poll_established == 0) { 480 1.57 thorpej callout_init(&sc->poll_ch); 481 1.57 thorpej callout_reset(&sc->poll_ch, hz / 2, pcic_poll_intr, sc); 482 1.57 thorpej sc->poll_established = 1; 483 1.57 thorpej } 484 1.57 thorpej } else 485 1.33 chopps reg |= sc->irq << PCIC_CSC_INTR_IRQ_SHIFT; 486 1.33 chopps pcic_write(h, PCIC_CSC_INTR, reg); 487 1.33 chopps 488 1.33 chopps /* steer above mgmt interrupt to configured place */ 489 1.72.2.1 skrll if (sc->irq == 0) 490 1.72.2.3 skrll pcic_write(h, PCIC_INTR, PCIC_INTR_ENABLE); 491 1.33 chopps 492 1.33 chopps /* clear possible card detect interrupt */ 493 1.72.2.3 skrll (void) pcic_read(h, PCIC_CSC); 494 1.33 chopps 495 1.33 chopps DPRINTF(("%s: attach finish vendor 0x%02x\n", h->ph_parent->dv_xname, 496 1.33 chopps h->vendor)); 497 1.33 chopps 498 1.33 chopps /* unsleep the cirrus controller */ 499 1.72.2.1 skrll if (h->vendor == PCIC_VENDOR_CIRRUS_PD67XX) { 500 1.33 chopps reg = pcic_read(h, PCIC_CIRRUS_MISC_CTL_2); 501 1.33 chopps if (reg & PCIC_CIRRUS_MISC_CTL_2_SUSPEND) { 502 1.33 chopps DPRINTF(("%s: socket %02x was suspended\n", 503 1.35 enami h->ph_parent->dv_xname, h->sock)); 504 1.33 chopps reg &= ~PCIC_CIRRUS_MISC_CTL_2_SUSPEND; 505 1.33 chopps pcic_write(h, PCIC_CIRRUS_MISC_CTL_2, reg); 506 1.33 chopps } 507 1.33 chopps } 508 1.33 chopps 509 1.33 chopps /* if there's a card there, then attach it. */ 510 1.33 chopps reg = pcic_read(h, PCIC_IF_STATUS); 511 1.33 chopps if ((reg & PCIC_IF_STATUS_CARDDETECT_MASK) == 512 1.33 chopps PCIC_IF_STATUS_CARDDETECT_PRESENT) { 513 1.33 chopps pcic_queue_event(h, PCIC_EVENT_INSERTION); 514 1.33 chopps h->laststate = PCIC_LASTSTATE_PRESENT; 515 1.33 chopps } else { 516 1.33 chopps h->laststate = PCIC_LASTSTATE_EMPTY; 517 1.33 chopps } 518 1.2 thorpej } 519 1.2 thorpej 520 1.2 thorpej void 521 1.14 thorpej pcic_create_event_thread(arg) 522 1.14 thorpej void *arg; 523 1.14 thorpej { 524 1.14 thorpej struct pcic_handle *h = arg; 525 1.72.2.4 skrll char cs[4]; 526 1.14 thorpej 527 1.72.2.4 skrll snprintf(cs, sizeof(cs), "%d,%d", h->chip, h->socket); 528 1.14 thorpej 529 1.24 thorpej if (kthread_create1(pcic_event_thread, h, &h->event_thread, 530 1.25 haya "%s,%s", h->ph_parent->dv_xname, cs)) { 531 1.14 thorpej printf("%s: unable to create event thread for sock 0x%02x\n", 532 1.25 haya h->ph_parent->dv_xname, h->sock); 533 1.14 thorpej panic("pcic_create_event_thread"); 534 1.14 thorpej } 535 1.14 thorpej } 536 1.14 thorpej 537 1.14 thorpej void 538 1.14 thorpej pcic_event_thread(arg) 539 1.14 thorpej void *arg; 540 1.14 thorpej { 541 1.14 thorpej struct pcic_handle *h = arg; 542 1.14 thorpej struct pcic_event *pe; 543 1.29 enami int s, first = 1; 544 1.35 enami struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 545 1.14 thorpej 546 1.14 thorpej while (h->shutdown == 0) { 547 1.53 thorpej /* 548 1.53 thorpej * Serialize event processing on the PCIC. We may 549 1.53 thorpej * sleep while we hold this lock. 550 1.53 thorpej */ 551 1.53 thorpej (void) lockmgr(&sc->sc_pcic_lock, LK_EXCLUSIVE, NULL); 552 1.53 thorpej 553 1.14 thorpej s = splhigh(); 554 1.14 thorpej if ((pe = SIMPLEQ_FIRST(&h->events)) == NULL) { 555 1.14 thorpej splx(s); 556 1.29 enami if (first) { 557 1.29 enami first = 0; 558 1.29 enami config_pending_decr(); 559 1.29 enami } 560 1.53 thorpej /* 561 1.53 thorpej * No events to process; release the PCIC lock. 562 1.53 thorpej */ 563 1.53 thorpej (void) lockmgr(&sc->sc_pcic_lock, LK_RELEASE, NULL); 564 1.14 thorpej (void) tsleep(&h->events, PWAIT, "pcicev", 0); 565 1.14 thorpej continue; 566 1.20 msaitoh } else { 567 1.20 msaitoh splx(s); 568 1.20 msaitoh /* sleep .25s to be enqueued chatterling interrupts */ 569 1.35 enami (void) tsleep((caddr_t)pcic_event_thread, PWAIT, 570 1.35 enami "pcicss", hz/4); 571 1.14 thorpej } 572 1.20 msaitoh s = splhigh(); 573 1.66 lukem SIMPLEQ_REMOVE_HEAD(&h->events, pe_q); 574 1.14 thorpej splx(s); 575 1.14 thorpej 576 1.14 thorpej switch (pe->pe_type) { 577 1.14 thorpej case PCIC_EVENT_INSERTION: 578 1.20 msaitoh s = splhigh(); 579 1.20 msaitoh while (1) { 580 1.20 msaitoh struct pcic_event *pe1, *pe2; 581 1.20 msaitoh 582 1.20 msaitoh if ((pe1 = SIMPLEQ_FIRST(&h->events)) == NULL) 583 1.20 msaitoh break; 584 1.20 msaitoh if (pe1->pe_type != PCIC_EVENT_REMOVAL) 585 1.20 msaitoh break; 586 1.20 msaitoh if ((pe2 = SIMPLEQ_NEXT(pe1, pe_q)) == NULL) 587 1.20 msaitoh break; 588 1.20 msaitoh if (pe2->pe_type == PCIC_EVENT_INSERTION) { 589 1.66 lukem SIMPLEQ_REMOVE_HEAD(&h->events, pe_q); 590 1.20 msaitoh free(pe1, M_TEMP); 591 1.66 lukem SIMPLEQ_REMOVE_HEAD(&h->events, pe_q); 592 1.20 msaitoh free(pe2, M_TEMP); 593 1.20 msaitoh } 594 1.20 msaitoh } 595 1.20 msaitoh splx(s); 596 1.72.2.7 skrll 597 1.35 enami DPRINTF(("%s: insertion event\n", 598 1.35 enami h->ph_parent->dv_xname)); 599 1.14 thorpej pcic_attach_card(h); 600 1.14 thorpej break; 601 1.14 thorpej 602 1.14 thorpej case PCIC_EVENT_REMOVAL: 603 1.20 msaitoh s = splhigh(); 604 1.20 msaitoh while (1) { 605 1.20 msaitoh struct pcic_event *pe1, *pe2; 606 1.20 msaitoh 607 1.20 msaitoh if ((pe1 = SIMPLEQ_FIRST(&h->events)) == NULL) 608 1.20 msaitoh break; 609 1.20 msaitoh if (pe1->pe_type != PCIC_EVENT_INSERTION) 610 1.20 msaitoh break; 611 1.20 msaitoh if ((pe2 = SIMPLEQ_NEXT(pe1, pe_q)) == NULL) 612 1.20 msaitoh break; 613 1.20 msaitoh if (pe2->pe_type == PCIC_EVENT_REMOVAL) { 614 1.66 lukem SIMPLEQ_REMOVE_HEAD(&h->events, pe_q); 615 1.20 msaitoh free(pe1, M_TEMP); 616 1.66 lukem SIMPLEQ_REMOVE_HEAD(&h->events, pe_q); 617 1.20 msaitoh free(pe2, M_TEMP); 618 1.20 msaitoh } 619 1.20 msaitoh } 620 1.20 msaitoh splx(s); 621 1.20 msaitoh 622 1.35 enami DPRINTF(("%s: removal event\n", 623 1.35 enami h->ph_parent->dv_xname)); 624 1.15 thorpej pcic_detach_card(h, DETACH_FORCE); 625 1.14 thorpej break; 626 1.14 thorpej 627 1.14 thorpej default: 628 1.14 thorpej panic("pcic_event_thread: unknown event %d", 629 1.14 thorpej pe->pe_type); 630 1.14 thorpej } 631 1.14 thorpej free(pe, M_TEMP); 632 1.53 thorpej 633 1.53 thorpej (void) lockmgr(&sc->sc_pcic_lock, LK_RELEASE, NULL); 634 1.14 thorpej } 635 1.14 thorpej 636 1.14 thorpej h->event_thread = NULL; 637 1.14 thorpej 638 1.14 thorpej /* In case parent is waiting for us to exit. */ 639 1.25 haya wakeup(sc); 640 1.14 thorpej 641 1.14 thorpej kthread_exit(0); 642 1.14 thorpej } 643 1.14 thorpej 644 1.2 thorpej int 645 1.72.2.4 skrll pcic_submatch(parent, cf, ldesc, aux) 646 1.2 thorpej struct device *parent; 647 1.2 thorpej struct cfdata *cf; 648 1.72.2.4 skrll const locdesc_t *ldesc; 649 1.2 thorpej void *aux; 650 1.2 thorpej { 651 1.2 thorpej 652 1.72.2.4 skrll if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != PCMCIABUSCF_CONTROLLER_DEFAULT && 653 1.72.2.4 skrll cf->cf_loc[PCMCIABUSCF_CONTROLLER] != ldesc->locs[PCMCIABUSCF_CONTROLLER]) 654 1.2 thorpej return 0; 655 1.72.2.4 skrll if (cf->cf_loc[PCMCIABUSCF_SOCKET] != PCMCIABUSCF_SOCKET_DEFAULT && 656 1.72.2.4 skrll cf->cf_loc[PCMCIABUSCF_SOCKET] != ldesc->locs[PCMCIABUSCF_SOCKET]) 657 1.2 thorpej return 0; 658 1.2 thorpej 659 1.67 thorpej return (config_match(parent, cf, aux)); 660 1.2 thorpej } 661 1.2 thorpej 662 1.2 thorpej int 663 1.2 thorpej pcic_print(arg, pnp) 664 1.2 thorpej void *arg; 665 1.2 thorpej const char *pnp; 666 1.2 thorpej { 667 1.3 enami struct pcmciabus_attach_args *paa = arg; 668 1.2 thorpej struct pcic_handle *h = (struct pcic_handle *) paa->pch; 669 1.2 thorpej 670 1.2 thorpej /* Only "pcmcia"s can attach to "pcic"s... easy. */ 671 1.2 thorpej if (pnp) 672 1.70 thorpej aprint_normal("pcmcia at %s", pnp); 673 1.2 thorpej 674 1.72.2.4 skrll aprint_normal(" controller %d socket %d", h->chip, h->socket); 675 1.2 thorpej 676 1.2 thorpej return (UNCONF); 677 1.2 thorpej } 678 1.2 thorpej 679 1.33 chopps void 680 1.33 chopps pcic_poll_intr(arg) 681 1.33 chopps void *arg; 682 1.33 chopps { 683 1.33 chopps struct pcic_softc *sc; 684 1.33 chopps int i, s; 685 1.33 chopps 686 1.33 chopps s = spltty(); 687 1.33 chopps sc = arg; 688 1.33 chopps for (i = 0; i < PCIC_NSLOTS; i++) 689 1.33 chopps if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 690 1.33 chopps (void)pcic_intr_socket(&sc->handle[i]); 691 1.57 thorpej callout_reset(&sc->poll_ch, hz / 2, pcic_poll_intr, sc); 692 1.33 chopps splx(s); 693 1.33 chopps } 694 1.33 chopps 695 1.2 thorpej int 696 1.2 thorpej pcic_intr(arg) 697 1.2 thorpej void *arg; 698 1.2 thorpej { 699 1.3 enami struct pcic_softc *sc = arg; 700 1.2 thorpej int i, ret = 0; 701 1.2 thorpej 702 1.2 thorpej DPRINTF(("%s: intr\n", sc->dev.dv_xname)); 703 1.2 thorpej 704 1.2 thorpej for (i = 0; i < PCIC_NSLOTS; i++) 705 1.2 thorpej if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 706 1.2 thorpej ret += pcic_intr_socket(&sc->handle[i]); 707 1.2 thorpej 708 1.2 thorpej return (ret ? 1 : 0); 709 1.2 thorpej } 710 1.2 thorpej 711 1.2 thorpej int 712 1.2 thorpej pcic_intr_socket(h) 713 1.2 thorpej struct pcic_handle *h; 714 1.2 thorpej { 715 1.2 thorpej int cscreg; 716 1.2 thorpej 717 1.2 thorpej cscreg = pcic_read(h, PCIC_CSC); 718 1.2 thorpej 719 1.2 thorpej cscreg &= (PCIC_CSC_GPI | 720 1.2 thorpej PCIC_CSC_CD | 721 1.2 thorpej PCIC_CSC_READY | 722 1.2 thorpej PCIC_CSC_BATTWARN | 723 1.2 thorpej PCIC_CSC_BATTDEAD); 724 1.2 thorpej 725 1.2 thorpej if (cscreg & PCIC_CSC_GPI) { 726 1.25 haya DPRINTF(("%s: %02x GPI\n", h->ph_parent->dv_xname, h->sock)); 727 1.2 thorpej } 728 1.2 thorpej if (cscreg & PCIC_CSC_CD) { 729 1.2 thorpej int statreg; 730 1.2 thorpej 731 1.2 thorpej statreg = pcic_read(h, PCIC_IF_STATUS); 732 1.2 thorpej 733 1.25 haya DPRINTF(("%s: %02x CD %x\n", h->ph_parent->dv_xname, h->sock, 734 1.2 thorpej statreg)); 735 1.2 thorpej 736 1.2 thorpej if ((statreg & PCIC_IF_STATUS_CARDDETECT_MASK) == 737 1.2 thorpej PCIC_IF_STATUS_CARDDETECT_PRESENT) { 738 1.20 msaitoh if (h->laststate != PCIC_LASTSTATE_PRESENT) { 739 1.14 thorpej DPRINTF(("%s: enqueing INSERTION event\n", 740 1.25 haya h->ph_parent->dv_xname)); 741 1.14 thorpej pcic_queue_event(h, PCIC_EVENT_INSERTION); 742 1.14 thorpej } 743 1.20 msaitoh h->laststate = PCIC_LASTSTATE_PRESENT; 744 1.2 thorpej } else { 745 1.20 msaitoh if (h->laststate == PCIC_LASTSTATE_PRESENT) { 746 1.15 thorpej /* Deactivate the card now. */ 747 1.15 thorpej DPRINTF(("%s: deactivating card\n", 748 1.25 haya h->ph_parent->dv_xname)); 749 1.15 thorpej pcic_deactivate_card(h); 750 1.15 thorpej 751 1.14 thorpej DPRINTF(("%s: enqueing REMOVAL event\n", 752 1.25 haya h->ph_parent->dv_xname)); 753 1.14 thorpej pcic_queue_event(h, PCIC_EVENT_REMOVAL); 754 1.14 thorpej } 755 1.72.2.3 skrll h->laststate = PCIC_LASTSTATE_EMPTY; 756 1.2 thorpej } 757 1.2 thorpej } 758 1.2 thorpej if (cscreg & PCIC_CSC_READY) { 759 1.25 haya DPRINTF(("%s: %02x READY\n", h->ph_parent->dv_xname, h->sock)); 760 1.2 thorpej /* shouldn't happen */ 761 1.2 thorpej } 762 1.2 thorpej if (cscreg & PCIC_CSC_BATTWARN) { 763 1.35 enami DPRINTF(("%s: %02x BATTWARN\n", h->ph_parent->dv_xname, 764 1.35 enami h->sock)); 765 1.2 thorpej } 766 1.2 thorpej if (cscreg & PCIC_CSC_BATTDEAD) { 767 1.35 enami DPRINTF(("%s: %02x BATTDEAD\n", h->ph_parent->dv_xname, 768 1.35 enami h->sock)); 769 1.2 thorpej } 770 1.2 thorpej return (cscreg ? 1 : 0); 771 1.14 thorpej } 772 1.14 thorpej 773 1.14 thorpej void 774 1.14 thorpej pcic_queue_event(h, event) 775 1.14 thorpej struct pcic_handle *h; 776 1.14 thorpej int event; 777 1.14 thorpej { 778 1.14 thorpej struct pcic_event *pe; 779 1.14 thorpej int s; 780 1.14 thorpej 781 1.14 thorpej pe = malloc(sizeof(*pe), M_TEMP, M_NOWAIT); 782 1.14 thorpej if (pe == NULL) 783 1.14 thorpej panic("pcic_queue_event: can't allocate event"); 784 1.14 thorpej 785 1.14 thorpej pe->pe_type = event; 786 1.14 thorpej s = splhigh(); 787 1.14 thorpej SIMPLEQ_INSERT_TAIL(&h->events, pe, pe_q); 788 1.14 thorpej splx(s); 789 1.14 thorpej wakeup(&h->events); 790 1.2 thorpej } 791 1.2 thorpej 792 1.2 thorpej void 793 1.2 thorpej pcic_attach_card(h) 794 1.2 thorpej struct pcic_handle *h; 795 1.2 thorpej { 796 1.15 thorpej 797 1.20 msaitoh if (!(h->flags & PCIC_FLAG_CARDP)) { 798 1.20 msaitoh /* call the MI attach function */ 799 1.20 msaitoh pcmcia_card_attach(h->pcmcia); 800 1.2 thorpej 801 1.20 msaitoh h->flags |= PCIC_FLAG_CARDP; 802 1.20 msaitoh } else { 803 1.20 msaitoh DPRINTF(("pcic_attach_card: already attached")); 804 1.20 msaitoh } 805 1.2 thorpej } 806 1.2 thorpej 807 1.2 thorpej void 808 1.15 thorpej pcic_detach_card(h, flags) 809 1.2 thorpej struct pcic_handle *h; 810 1.15 thorpej int flags; /* DETACH_* */ 811 1.2 thorpej { 812 1.15 thorpej 813 1.20 msaitoh if (h->flags & PCIC_FLAG_CARDP) { 814 1.20 msaitoh h->flags &= ~PCIC_FLAG_CARDP; 815 1.2 thorpej 816 1.20 msaitoh /* call the MI detach function */ 817 1.20 msaitoh pcmcia_card_detach(h->pcmcia, flags); 818 1.20 msaitoh } else { 819 1.20 msaitoh DPRINTF(("pcic_detach_card: already detached")); 820 1.20 msaitoh } 821 1.15 thorpej } 822 1.15 thorpej 823 1.15 thorpej void 824 1.15 thorpej pcic_deactivate_card(h) 825 1.15 thorpej struct pcic_handle *h; 826 1.15 thorpej { 827 1.72.2.1 skrll int intr; 828 1.2 thorpej 829 1.15 thorpej /* call the MI deactivate function */ 830 1.15 thorpej pcmcia_card_deactivate(h->pcmcia); 831 1.2 thorpej 832 1.15 thorpej /* reset the socket */ 833 1.72.2.1 skrll intr = pcic_read(h, PCIC_INTR); 834 1.72.2.1 skrll intr &= PCIC_INTR_ENABLE; 835 1.72.2.1 skrll pcic_write(h, PCIC_INTR, intr); 836 1.72.2.3 skrll 837 1.72.2.3 skrll /* power down the socket */ 838 1.72.2.3 skrll pcic_write(h, PCIC_PWRCTL, 0); 839 1.2 thorpej } 840 1.2 thorpej 841 1.72.2.7 skrll int 842 1.2 thorpej pcic_chip_mem_alloc(pch, size, pcmhp) 843 1.2 thorpej pcmcia_chipset_handle_t pch; 844 1.2 thorpej bus_size_t size; 845 1.2 thorpej struct pcmcia_mem_handle *pcmhp; 846 1.2 thorpej { 847 1.2 thorpej struct pcic_handle *h = (struct pcic_handle *) pch; 848 1.2 thorpej bus_space_handle_t memh; 849 1.2 thorpej bus_addr_t addr; 850 1.2 thorpej bus_size_t sizepg; 851 1.2 thorpej int i, mask, mhandle; 852 1.35 enami struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 853 1.2 thorpej 854 1.2 thorpej /* out of sc->memh, allocate as many pages as necessary */ 855 1.2 thorpej 856 1.2 thorpej /* convert size to PCIC pages */ 857 1.2 thorpej sizepg = (size + (PCIC_MEM_ALIGN - 1)) / PCIC_MEM_ALIGN; 858 1.19 christos if (sizepg > PCIC_MAX_MEM_PAGES) 859 1.19 christos return (1); 860 1.2 thorpej 861 1.2 thorpej mask = (1 << sizepg) - 1; 862 1.2 thorpej 863 1.2 thorpej addr = 0; /* XXX gcc -Wuninitialized */ 864 1.2 thorpej mhandle = 0; /* XXX gcc -Wuninitialized */ 865 1.2 thorpej 866 1.19 christos for (i = 0; i <= PCIC_MAX_MEM_PAGES - sizepg; i++) { 867 1.25 haya if ((sc->subregionmask & (mask << i)) == (mask << i)) { 868 1.25 haya if (bus_space_subregion(sc->memt, sc->memh, 869 1.2 thorpej i * PCIC_MEM_PAGESIZE, 870 1.2 thorpej sizepg * PCIC_MEM_PAGESIZE, &memh)) 871 1.2 thorpej return (1); 872 1.2 thorpej mhandle = mask << i; 873 1.25 haya addr = sc->membase + (i * PCIC_MEM_PAGESIZE); 874 1.25 haya sc->subregionmask &= ~(mhandle); 875 1.25 haya pcmhp->memt = sc->memt; 876 1.19 christos pcmhp->memh = memh; 877 1.19 christos pcmhp->addr = addr; 878 1.19 christos pcmhp->size = size; 879 1.19 christos pcmhp->mhandle = mhandle; 880 1.19 christos pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 881 1.19 christos return (0); 882 1.2 thorpej } 883 1.2 thorpej } 884 1.2 thorpej 885 1.19 christos return (1); 886 1.2 thorpej } 887 1.2 thorpej 888 1.72.2.7 skrll void 889 1.2 thorpej pcic_chip_mem_free(pch, pcmhp) 890 1.2 thorpej pcmcia_chipset_handle_t pch; 891 1.2 thorpej struct pcmcia_mem_handle *pcmhp; 892 1.2 thorpej { 893 1.2 thorpej struct pcic_handle *h = (struct pcic_handle *) pch; 894 1.35 enami struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 895 1.2 thorpej 896 1.25 haya sc->subregionmask |= pcmhp->mhandle; 897 1.2 thorpej } 898 1.2 thorpej 899 1.62 jdolecek static const struct mem_map_index_st { 900 1.2 thorpej int sysmem_start_lsb; 901 1.2 thorpej int sysmem_start_msb; 902 1.2 thorpej int sysmem_stop_lsb; 903 1.2 thorpej int sysmem_stop_msb; 904 1.2 thorpej int cardmem_lsb; 905 1.2 thorpej int cardmem_msb; 906 1.2 thorpej int memenable; 907 1.2 thorpej } mem_map_index[] = { 908 1.2 thorpej { 909 1.2 thorpej PCIC_SYSMEM_ADDR0_START_LSB, 910 1.2 thorpej PCIC_SYSMEM_ADDR0_START_MSB, 911 1.2 thorpej PCIC_SYSMEM_ADDR0_STOP_LSB, 912 1.2 thorpej PCIC_SYSMEM_ADDR0_STOP_MSB, 913 1.2 thorpej PCIC_CARDMEM_ADDR0_LSB, 914 1.2 thorpej PCIC_CARDMEM_ADDR0_MSB, 915 1.2 thorpej PCIC_ADDRWIN_ENABLE_MEM0, 916 1.2 thorpej }, 917 1.2 thorpej { 918 1.2 thorpej PCIC_SYSMEM_ADDR1_START_LSB, 919 1.2 thorpej PCIC_SYSMEM_ADDR1_START_MSB, 920 1.2 thorpej PCIC_SYSMEM_ADDR1_STOP_LSB, 921 1.2 thorpej PCIC_SYSMEM_ADDR1_STOP_MSB, 922 1.2 thorpej PCIC_CARDMEM_ADDR1_LSB, 923 1.2 thorpej PCIC_CARDMEM_ADDR1_MSB, 924 1.2 thorpej PCIC_ADDRWIN_ENABLE_MEM1, 925 1.2 thorpej }, 926 1.2 thorpej { 927 1.2 thorpej PCIC_SYSMEM_ADDR2_START_LSB, 928 1.2 thorpej PCIC_SYSMEM_ADDR2_START_MSB, 929 1.2 thorpej PCIC_SYSMEM_ADDR2_STOP_LSB, 930 1.2 thorpej PCIC_SYSMEM_ADDR2_STOP_MSB, 931 1.2 thorpej PCIC_CARDMEM_ADDR2_LSB, 932 1.2 thorpej PCIC_CARDMEM_ADDR2_MSB, 933 1.2 thorpej PCIC_ADDRWIN_ENABLE_MEM2, 934 1.2 thorpej }, 935 1.2 thorpej { 936 1.2 thorpej PCIC_SYSMEM_ADDR3_START_LSB, 937 1.2 thorpej PCIC_SYSMEM_ADDR3_START_MSB, 938 1.2 thorpej PCIC_SYSMEM_ADDR3_STOP_LSB, 939 1.2 thorpej PCIC_SYSMEM_ADDR3_STOP_MSB, 940 1.2 thorpej PCIC_CARDMEM_ADDR3_LSB, 941 1.2 thorpej PCIC_CARDMEM_ADDR3_MSB, 942 1.2 thorpej PCIC_ADDRWIN_ENABLE_MEM3, 943 1.2 thorpej }, 944 1.2 thorpej { 945 1.2 thorpej PCIC_SYSMEM_ADDR4_START_LSB, 946 1.2 thorpej PCIC_SYSMEM_ADDR4_START_MSB, 947 1.2 thorpej PCIC_SYSMEM_ADDR4_STOP_LSB, 948 1.2 thorpej PCIC_SYSMEM_ADDR4_STOP_MSB, 949 1.2 thorpej PCIC_CARDMEM_ADDR4_LSB, 950 1.2 thorpej PCIC_CARDMEM_ADDR4_MSB, 951 1.2 thorpej PCIC_ADDRWIN_ENABLE_MEM4, 952 1.2 thorpej }, 953 1.2 thorpej }; 954 1.2 thorpej 955 1.72.2.7 skrll void 956 1.2 thorpej pcic_chip_do_mem_map(h, win) 957 1.2 thorpej struct pcic_handle *h; 958 1.2 thorpej int win; 959 1.2 thorpej { 960 1.2 thorpej int reg; 961 1.28 joda int kind = h->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 962 1.35 enami int mem8 = 963 1.47 chopps (h->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8 964 1.47 chopps || (kind == PCMCIA_MEM_ATTR); 965 1.28 joda 966 1.33 chopps DPRINTF(("mem8 %d\n", mem8)); 967 1.33 chopps /* mem8 = 1; */ 968 1.33 chopps 969 1.2 thorpej pcic_write(h, mem_map_index[win].sysmem_start_lsb, 970 1.2 thorpej (h->mem[win].addr >> PCIC_SYSMEM_ADDRX_SHIFT) & 0xff); 971 1.2 thorpej pcic_write(h, mem_map_index[win].sysmem_start_msb, 972 1.2 thorpej ((h->mem[win].addr >> (PCIC_SYSMEM_ADDRX_SHIFT + 8)) & 973 1.43 joda PCIC_SYSMEM_ADDRX_START_MSB_ADDR_MASK) | 974 1.44 enami (mem8 ? 0 : PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT)); 975 1.2 thorpej 976 1.2 thorpej pcic_write(h, mem_map_index[win].sysmem_stop_lsb, 977 1.2 thorpej ((h->mem[win].addr + h->mem[win].size) >> 978 1.2 thorpej PCIC_SYSMEM_ADDRX_SHIFT) & 0xff); 979 1.2 thorpej pcic_write(h, mem_map_index[win].sysmem_stop_msb, 980 1.2 thorpej (((h->mem[win].addr + h->mem[win].size) >> 981 1.2 thorpej (PCIC_SYSMEM_ADDRX_SHIFT + 8)) & 982 1.2 thorpej PCIC_SYSMEM_ADDRX_STOP_MSB_ADDR_MASK) | 983 1.2 thorpej PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2); 984 1.2 thorpej 985 1.2 thorpej pcic_write(h, mem_map_index[win].cardmem_lsb, 986 1.2 thorpej (h->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff); 987 1.2 thorpej pcic_write(h, mem_map_index[win].cardmem_msb, 988 1.2 thorpej ((h->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) & 989 1.2 thorpej PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) | 990 1.28 joda ((kind == PCMCIA_MEM_ATTR) ? 991 1.2 thorpej PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0)); 992 1.2 thorpej 993 1.2 thorpej reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 994 1.43 joda reg |= (mem_map_index[win].memenable | PCIC_ADDRWIN_ENABLE_MEMCS16); 995 1.2 thorpej pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 996 1.21 marc 997 1.21 marc delay(100); 998 1.2 thorpej 999 1.2 thorpej #ifdef PCICDEBUG 1000 1.2 thorpej { 1001 1.2 thorpej int r1, r2, r3, r4, r5, r6; 1002 1.2 thorpej 1003 1.2 thorpej r1 = pcic_read(h, mem_map_index[win].sysmem_start_msb); 1004 1.2 thorpej r2 = pcic_read(h, mem_map_index[win].sysmem_start_lsb); 1005 1.2 thorpej r3 = pcic_read(h, mem_map_index[win].sysmem_stop_msb); 1006 1.2 thorpej r4 = pcic_read(h, mem_map_index[win].sysmem_stop_lsb); 1007 1.2 thorpej r5 = pcic_read(h, mem_map_index[win].cardmem_msb); 1008 1.2 thorpej r6 = pcic_read(h, mem_map_index[win].cardmem_lsb); 1009 1.2 thorpej 1010 1.2 thorpej DPRINTF(("pcic_chip_do_mem_map window %d: %02x%02x %02x%02x " 1011 1.2 thorpej "%02x%02x\n", win, r1, r2, r3, r4, r5, r6)); 1012 1.2 thorpej } 1013 1.2 thorpej #endif 1014 1.2 thorpej } 1015 1.2 thorpej 1016 1.72.2.7 skrll int 1017 1.2 thorpej pcic_chip_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 1018 1.2 thorpej pcmcia_chipset_handle_t pch; 1019 1.2 thorpej int kind; 1020 1.2 thorpej bus_addr_t card_addr; 1021 1.2 thorpej bus_size_t size; 1022 1.2 thorpej struct pcmcia_mem_handle *pcmhp; 1023 1.65 soren bus_size_t *offsetp; 1024 1.2 thorpej int *windowp; 1025 1.2 thorpej { 1026 1.2 thorpej struct pcic_handle *h = (struct pcic_handle *) pch; 1027 1.2 thorpej bus_addr_t busaddr; 1028 1.2 thorpej long card_offset; 1029 1.2 thorpej int i, win; 1030 1.35 enami struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 1031 1.2 thorpej 1032 1.2 thorpej win = -1; 1033 1.2 thorpej for (i = 0; i < (sizeof(mem_map_index) / sizeof(mem_map_index[0])); 1034 1.2 thorpej i++) { 1035 1.2 thorpej if ((h->memalloc & (1 << i)) == 0) { 1036 1.2 thorpej win = i; 1037 1.2 thorpej h->memalloc |= (1 << i); 1038 1.2 thorpej break; 1039 1.2 thorpej } 1040 1.2 thorpej } 1041 1.2 thorpej 1042 1.2 thorpej if (win == -1) 1043 1.2 thorpej return (1); 1044 1.2 thorpej 1045 1.2 thorpej *windowp = win; 1046 1.2 thorpej 1047 1.2 thorpej /* XXX this is pretty gross */ 1048 1.2 thorpej 1049 1.25 haya if (sc->memt != pcmhp->memt) 1050 1.2 thorpej panic("pcic_chip_mem_map memt is bogus"); 1051 1.2 thorpej 1052 1.2 thorpej busaddr = pcmhp->addr; 1053 1.2 thorpej 1054 1.2 thorpej /* 1055 1.2 thorpej * compute the address offset to the pcmcia address space for the 1056 1.2 thorpej * pcic. this is intentionally signed. The masks and shifts below 1057 1.2 thorpej * will cause TRT to happen in the pcic registers. Deal with making 1058 1.2 thorpej * sure the address is aligned, and return the alignment offset. 1059 1.2 thorpej */ 1060 1.2 thorpej 1061 1.2 thorpej *offsetp = card_addr % PCIC_MEM_ALIGN; 1062 1.2 thorpej card_addr -= *offsetp; 1063 1.2 thorpej 1064 1.2 thorpej DPRINTF(("pcic_chip_mem_map window %d bus %lx+%lx+%lx at card addr " 1065 1.2 thorpej "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 1066 1.2 thorpej (u_long) card_addr)); 1067 1.2 thorpej 1068 1.2 thorpej /* 1069 1.2 thorpej * include the offset in the size, and decrement size by one, since 1070 1.2 thorpej * the hw wants start/stop 1071 1.2 thorpej */ 1072 1.2 thorpej size += *offsetp - 1; 1073 1.2 thorpej 1074 1.2 thorpej card_offset = (((long) card_addr) - ((long) busaddr)); 1075 1.2 thorpej 1076 1.2 thorpej h->mem[win].addr = busaddr; 1077 1.2 thorpej h->mem[win].size = size; 1078 1.2 thorpej h->mem[win].offset = card_offset; 1079 1.2 thorpej h->mem[win].kind = kind; 1080 1.2 thorpej 1081 1.2 thorpej pcic_chip_do_mem_map(h, win); 1082 1.2 thorpej 1083 1.2 thorpej return (0); 1084 1.2 thorpej } 1085 1.2 thorpej 1086 1.72.2.7 skrll void 1087 1.2 thorpej pcic_chip_mem_unmap(pch, window) 1088 1.2 thorpej pcmcia_chipset_handle_t pch; 1089 1.2 thorpej int window; 1090 1.2 thorpej { 1091 1.2 thorpej struct pcic_handle *h = (struct pcic_handle *) pch; 1092 1.2 thorpej int reg; 1093 1.2 thorpej 1094 1.2 thorpej if (window >= (sizeof(mem_map_index) / sizeof(mem_map_index[0]))) 1095 1.2 thorpej panic("pcic_chip_mem_unmap: window out of range"); 1096 1.2 thorpej 1097 1.2 thorpej reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1098 1.2 thorpej reg &= ~mem_map_index[window].memenable; 1099 1.2 thorpej pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1100 1.2 thorpej 1101 1.2 thorpej h->memalloc &= ~(1 << window); 1102 1.2 thorpej } 1103 1.2 thorpej 1104 1.72.2.7 skrll int 1105 1.2 thorpej pcic_chip_io_alloc(pch, start, size, align, pcihp) 1106 1.2 thorpej pcmcia_chipset_handle_t pch; 1107 1.2 thorpej bus_addr_t start; 1108 1.2 thorpej bus_size_t size; 1109 1.2 thorpej bus_size_t align; 1110 1.2 thorpej struct pcmcia_io_handle *pcihp; 1111 1.2 thorpej { 1112 1.2 thorpej struct pcic_handle *h = (struct pcic_handle *) pch; 1113 1.2 thorpej bus_space_tag_t iot; 1114 1.2 thorpej bus_space_handle_t ioh; 1115 1.2 thorpej bus_addr_t ioaddr; 1116 1.2 thorpej int flags = 0; 1117 1.35 enami struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 1118 1.2 thorpej 1119 1.2 thorpej /* 1120 1.2 thorpej * Allocate some arbitrary I/O space. 1121 1.2 thorpej */ 1122 1.2 thorpej 1123 1.25 haya iot = sc->iot; 1124 1.2 thorpej 1125 1.2 thorpej if (start) { 1126 1.2 thorpej ioaddr = start; 1127 1.2 thorpej if (bus_space_map(iot, start, size, 0, &ioh)) 1128 1.2 thorpej return (1); 1129 1.2 thorpej DPRINTF(("pcic_chip_io_alloc map port %lx+%lx\n", 1130 1.2 thorpej (u_long) ioaddr, (u_long) size)); 1131 1.2 thorpej } else { 1132 1.2 thorpej flags |= PCMCIA_IO_ALLOCATED; 1133 1.25 haya if (bus_space_alloc(iot, sc->iobase, 1134 1.25 haya sc->iobase + sc->iosize, size, align, 0, 0, 1135 1.2 thorpej &ioaddr, &ioh)) 1136 1.2 thorpej return (1); 1137 1.2 thorpej DPRINTF(("pcic_chip_io_alloc alloc port %lx+%lx\n", 1138 1.2 thorpej (u_long) ioaddr, (u_long) size)); 1139 1.2 thorpej } 1140 1.2 thorpej 1141 1.2 thorpej pcihp->iot = iot; 1142 1.2 thorpej pcihp->ioh = ioh; 1143 1.2 thorpej pcihp->addr = ioaddr; 1144 1.2 thorpej pcihp->size = size; 1145 1.2 thorpej pcihp->flags = flags; 1146 1.2 thorpej 1147 1.2 thorpej return (0); 1148 1.2 thorpej } 1149 1.2 thorpej 1150 1.72.2.7 skrll void 1151 1.2 thorpej pcic_chip_io_free(pch, pcihp) 1152 1.2 thorpej pcmcia_chipset_handle_t pch; 1153 1.2 thorpej struct pcmcia_io_handle *pcihp; 1154 1.2 thorpej { 1155 1.2 thorpej bus_space_tag_t iot = pcihp->iot; 1156 1.2 thorpej bus_space_handle_t ioh = pcihp->ioh; 1157 1.2 thorpej bus_size_t size = pcihp->size; 1158 1.2 thorpej 1159 1.2 thorpej if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1160 1.2 thorpej bus_space_free(iot, ioh, size); 1161 1.2 thorpej else 1162 1.2 thorpej bus_space_unmap(iot, ioh, size); 1163 1.2 thorpej } 1164 1.2 thorpej 1165 1.2 thorpej 1166 1.62 jdolecek static const struct io_map_index_st { 1167 1.2 thorpej int start_lsb; 1168 1.2 thorpej int start_msb; 1169 1.2 thorpej int stop_lsb; 1170 1.2 thorpej int stop_msb; 1171 1.2 thorpej int ioenable; 1172 1.2 thorpej int ioctlmask; 1173 1.2 thorpej int ioctlbits[3]; /* indexed by PCMCIA_WIDTH_* */ 1174 1.2 thorpej } io_map_index[] = { 1175 1.2 thorpej { 1176 1.2 thorpej PCIC_IOADDR0_START_LSB, 1177 1.2 thorpej PCIC_IOADDR0_START_MSB, 1178 1.2 thorpej PCIC_IOADDR0_STOP_LSB, 1179 1.2 thorpej PCIC_IOADDR0_STOP_MSB, 1180 1.2 thorpej PCIC_ADDRWIN_ENABLE_IO0, 1181 1.2 thorpej PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 1182 1.2 thorpej PCIC_IOCTL_IO0_IOCS16SRC_MASK | PCIC_IOCTL_IO0_DATASIZE_MASK, 1183 1.2 thorpej { 1184 1.2 thorpej PCIC_IOCTL_IO0_IOCS16SRC_CARD, 1185 1.6 enami PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1186 1.6 enami PCIC_IOCTL_IO0_DATASIZE_8BIT, 1187 1.6 enami PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1188 1.6 enami PCIC_IOCTL_IO0_DATASIZE_16BIT, 1189 1.2 thorpej }, 1190 1.2 thorpej }, 1191 1.2 thorpej { 1192 1.2 thorpej PCIC_IOADDR1_START_LSB, 1193 1.2 thorpej PCIC_IOADDR1_START_MSB, 1194 1.2 thorpej PCIC_IOADDR1_STOP_LSB, 1195 1.2 thorpej PCIC_IOADDR1_STOP_MSB, 1196 1.2 thorpej PCIC_ADDRWIN_ENABLE_IO1, 1197 1.2 thorpej PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 1198 1.2 thorpej PCIC_IOCTL_IO1_IOCS16SRC_MASK | PCIC_IOCTL_IO1_DATASIZE_MASK, 1199 1.2 thorpej { 1200 1.2 thorpej PCIC_IOCTL_IO1_IOCS16SRC_CARD, 1201 1.2 thorpej PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE | 1202 1.2 thorpej PCIC_IOCTL_IO1_DATASIZE_8BIT, 1203 1.2 thorpej PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE | 1204 1.2 thorpej PCIC_IOCTL_IO1_DATASIZE_16BIT, 1205 1.2 thorpej }, 1206 1.2 thorpej }, 1207 1.2 thorpej }; 1208 1.2 thorpej 1209 1.72.2.7 skrll void 1210 1.2 thorpej pcic_chip_do_io_map(h, win) 1211 1.2 thorpej struct pcic_handle *h; 1212 1.2 thorpej int win; 1213 1.2 thorpej { 1214 1.2 thorpej int reg; 1215 1.2 thorpej 1216 1.2 thorpej DPRINTF(("pcic_chip_do_io_map win %d addr %lx size %lx width %d\n", 1217 1.2 thorpej win, (long) h->io[win].addr, (long) h->io[win].size, 1218 1.2 thorpej h->io[win].width * 8)); 1219 1.2 thorpej 1220 1.2 thorpej pcic_write(h, io_map_index[win].start_lsb, h->io[win].addr & 0xff); 1221 1.2 thorpej pcic_write(h, io_map_index[win].start_msb, 1222 1.2 thorpej (h->io[win].addr >> 8) & 0xff); 1223 1.2 thorpej 1224 1.2 thorpej pcic_write(h, io_map_index[win].stop_lsb, 1225 1.2 thorpej (h->io[win].addr + h->io[win].size - 1) & 0xff); 1226 1.2 thorpej pcic_write(h, io_map_index[win].stop_msb, 1227 1.2 thorpej ((h->io[win].addr + h->io[win].size - 1) >> 8) & 0xff); 1228 1.2 thorpej 1229 1.2 thorpej reg = pcic_read(h, PCIC_IOCTL); 1230 1.2 thorpej reg &= ~io_map_index[win].ioctlmask; 1231 1.2 thorpej reg |= io_map_index[win].ioctlbits[h->io[win].width]; 1232 1.2 thorpej pcic_write(h, PCIC_IOCTL, reg); 1233 1.2 thorpej 1234 1.2 thorpej reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1235 1.2 thorpej reg |= io_map_index[win].ioenable; 1236 1.2 thorpej pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1237 1.2 thorpej } 1238 1.2 thorpej 1239 1.72.2.7 skrll int 1240 1.2 thorpej pcic_chip_io_map(pch, width, offset, size, pcihp, windowp) 1241 1.2 thorpej pcmcia_chipset_handle_t pch; 1242 1.2 thorpej int width; 1243 1.2 thorpej bus_addr_t offset; 1244 1.2 thorpej bus_size_t size; 1245 1.2 thorpej struct pcmcia_io_handle *pcihp; 1246 1.2 thorpej int *windowp; 1247 1.2 thorpej { 1248 1.2 thorpej struct pcic_handle *h = (struct pcic_handle *) pch; 1249 1.2 thorpej bus_addr_t ioaddr = pcihp->addr + offset; 1250 1.4 enami int i, win; 1251 1.4 enami #ifdef PCICDEBUG 1252 1.2 thorpej static char *width_names[] = { "auto", "io8", "io16" }; 1253 1.4 enami #endif 1254 1.35 enami struct pcic_softc *sc = (struct pcic_softc *)h->ph_parent; 1255 1.2 thorpej 1256 1.2 thorpej /* XXX Sanity check offset/size. */ 1257 1.2 thorpej 1258 1.2 thorpej win = -1; 1259 1.2 thorpej for (i = 0; i < (sizeof(io_map_index) / sizeof(io_map_index[0])); i++) { 1260 1.2 thorpej if ((h->ioalloc & (1 << i)) == 0) { 1261 1.2 thorpej win = i; 1262 1.2 thorpej h->ioalloc |= (1 << i); 1263 1.2 thorpej break; 1264 1.2 thorpej } 1265 1.2 thorpej } 1266 1.2 thorpej 1267 1.2 thorpej if (win == -1) 1268 1.2 thorpej return (1); 1269 1.2 thorpej 1270 1.2 thorpej *windowp = win; 1271 1.2 thorpej 1272 1.2 thorpej /* XXX this is pretty gross */ 1273 1.2 thorpej 1274 1.25 haya if (sc->iot != pcihp->iot) 1275 1.2 thorpej panic("pcic_chip_io_map iot is bogus"); 1276 1.2 thorpej 1277 1.2 thorpej DPRINTF(("pcic_chip_io_map window %d %s port %lx+%lx\n", 1278 1.2 thorpej win, width_names[width], (u_long) ioaddr, (u_long) size)); 1279 1.2 thorpej 1280 1.2 thorpej /* XXX wtf is this doing here? */ 1281 1.2 thorpej 1282 1.72.2.1 skrll printf("%s: port 0x%lx", sc->dev.dv_xname, (u_long) ioaddr); 1283 1.2 thorpej if (size > 1) 1284 1.2 thorpej printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 1285 1.72.2.1 skrll printf("\n"); 1286 1.2 thorpej 1287 1.2 thorpej h->io[win].addr = ioaddr; 1288 1.2 thorpej h->io[win].size = size; 1289 1.2 thorpej h->io[win].width = width; 1290 1.2 thorpej 1291 1.2 thorpej pcic_chip_do_io_map(h, win); 1292 1.2 thorpej 1293 1.2 thorpej return (0); 1294 1.2 thorpej } 1295 1.2 thorpej 1296 1.72.2.7 skrll void 1297 1.2 thorpej pcic_chip_io_unmap(pch, window) 1298 1.2 thorpej pcmcia_chipset_handle_t pch; 1299 1.2 thorpej int window; 1300 1.2 thorpej { 1301 1.2 thorpej struct pcic_handle *h = (struct pcic_handle *) pch; 1302 1.2 thorpej int reg; 1303 1.2 thorpej 1304 1.2 thorpej if (window >= (sizeof(io_map_index) / sizeof(io_map_index[0]))) 1305 1.2 thorpej panic("pcic_chip_io_unmap: window out of range"); 1306 1.2 thorpej 1307 1.2 thorpej reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1308 1.2 thorpej reg &= ~io_map_index[window].ioenable; 1309 1.2 thorpej pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1310 1.2 thorpej 1311 1.2 thorpej h->ioalloc &= ~(1 << window); 1312 1.8 marc } 1313 1.8 marc 1314 1.72.2.3 skrll static int 1315 1.8 marc pcic_wait_ready(h) 1316 1.8 marc struct pcic_handle *h; 1317 1.8 marc { 1318 1.72.2.3 skrll u_int8_t stat; 1319 1.8 marc int i; 1320 1.8 marc 1321 1.31 chopps /* wait an initial 10ms for quick cards */ 1322 1.72.2.3 skrll stat = pcic_read(h, PCIC_IF_STATUS); 1323 1.72.2.3 skrll if (stat & PCIC_IF_STATUS_READY) 1324 1.72.2.3 skrll return (0); 1325 1.36 enami pcic_delay(h, 10, "pccwr0"); 1326 1.31 chopps for (i = 0; i < 50; i++) { 1327 1.72.2.3 skrll stat = pcic_read(h, PCIC_IF_STATUS); 1328 1.72.2.3 skrll if (stat & PCIC_IF_STATUS_READY) 1329 1.72.2.3 skrll return (0); 1330 1.72.2.3 skrll if ((stat & PCIC_IF_STATUS_CARDDETECT_MASK) != 1331 1.72.2.3 skrll PCIC_IF_STATUS_CARDDETECT_PRESENT) 1332 1.72.2.3 skrll return (ENXIO); 1333 1.31 chopps /* wait .1s (100ms) each iteration now */ 1334 1.36 enami pcic_delay(h, 100, "pccwr1"); 1335 1.8 marc } 1336 1.8 marc 1337 1.72.2.3 skrll printf("pcic_wait_ready: ready never happened, status=%02x\n", stat); 1338 1.72.2.3 skrll return (EWOULDBLOCK); 1339 1.2 thorpej } 1340 1.2 thorpej 1341 1.30 enami /* 1342 1.30 enami * Perform long (msec order) delay. 1343 1.72.2.7 skrll */ 1344 1.30 enami static void 1345 1.36 enami pcic_delay(h, timo, wmesg) 1346 1.30 enami struct pcic_handle *h; 1347 1.30 enami int timo; /* in ms. must not be zero */ 1348 1.36 enami const char *wmesg; 1349 1.30 enami { 1350 1.30 enami 1351 1.30 enami #ifdef DIAGNOSTIC 1352 1.72.2.3 skrll if (timo <= 0) 1353 1.72.2.3 skrll panic("pcic_delay: called with timeout %d", timo); 1354 1.72.2.3 skrll if (!curlwp) 1355 1.72.2.3 skrll panic("pcic_delay: called in interrupt context"); 1356 1.72.2.3 skrll if (!h->event_thread) 1357 1.72.2.3 skrll panic("pcic_delay: no event thread"); 1358 1.30 enami #endif 1359 1.48 dbj DPRINTF(("pcic_delay: \"%s\" %p, sleep %d ms\n", 1360 1.49 enami wmesg, h->event_thread, timo)); 1361 1.40 enami tsleep(pcic_delay, PWAIT, wmesg, roundup(timo * hz, 1000) / 1000); 1362 1.30 enami } 1363 1.30 enami 1364 1.2 thorpej void 1365 1.2 thorpej pcic_chip_socket_enable(pch) 1366 1.2 thorpej pcmcia_chipset_handle_t pch; 1367 1.2 thorpej { 1368 1.2 thorpej struct pcic_handle *h = (struct pcic_handle *) pch; 1369 1.72.2.3 skrll int win; 1370 1.72.2.3 skrll u_int8_t power, intr; 1371 1.72.2.3 skrll #ifdef DIAGNOSTIC 1372 1.34 chopps int reg; 1373 1.34 chopps #endif 1374 1.2 thorpej 1375 1.41 chopps #ifdef DIAGNOSTIC 1376 1.41 chopps if (h->flags & PCIC_FLAG_ENABLED) 1377 1.61 mycroft printf("pcic_chip_socket_enable: enabling twice\n"); 1378 1.41 chopps #endif 1379 1.41 chopps 1380 1.72.2.3 skrll /* disable interrupts; assert RESET */ 1381 1.39 enami intr = pcic_read(h, PCIC_INTR); 1382 1.72.2.3 skrll intr &= PCIC_INTR_ENABLE; 1383 1.34 chopps pcic_write(h, PCIC_INTR, intr); 1384 1.2 thorpej 1385 1.72.2.2 skrll /* zero out the address windows */ 1386 1.72.2.2 skrll pcic_write(h, PCIC_ADDRWIN_ENABLE, 0); 1387 1.72.2.2 skrll 1388 1.72.2.3 skrll /* power off; assert output enable bit */ 1389 1.72.2.3 skrll power = PCIC_PWRCTL_OE; 1390 1.72.2.3 skrll pcic_write(h, PCIC_PWRCTL, power); 1391 1.69 takemura 1392 1.69 takemura /* 1393 1.69 takemura * power hack for RICOH RF5C[23]96 1394 1.69 takemura */ 1395 1.69 takemura switch( h->vendor ) { 1396 1.69 takemura case PCIC_VENDOR_RICOH_5C296: 1397 1.69 takemura case PCIC_VENDOR_RICOH_5C396: 1398 1.72.2.1 skrll { 1399 1.72.2.1 skrll int regtmp; 1400 1.69 takemura regtmp = pcic_read(h, PCIC_RICOH_REG_MCR2); 1401 1.72.2.1 skrll #ifdef RICOH_POWER_HACK 1402 1.72.2.1 skrll regtmp |= PCIC_RICOH_MCR2_VCC_DIRECT; 1403 1.72.2.1 skrll #else 1404 1.72.2.1 skrll regtmp &= ~(PCIC_RICOH_MCR2_VCC_DIRECT|PCIC_RICOH_MCR2_VCC_SEL_3V); 1405 1.72.2.1 skrll #endif 1406 1.69 takemura pcic_write(h, PCIC_RICOH_REG_MCR2, regtmp); 1407 1.72.2.1 skrll } 1408 1.69 takemura break; 1409 1.69 takemura default: 1410 1.69 takemura break; 1411 1.69 takemura } 1412 1.9 enami 1413 1.22 mycroft #ifdef VADEM_POWER_HACK 1414 1.25 haya bus_space_write_1(sc->iot, sc->ioh, PCIC_REG_INDEX, 0x0e); 1415 1.25 haya bus_space_write_1(sc->iot, sc->ioh, PCIC_REG_INDEX, 0x37); 1416 1.22 mycroft printf("prcr = %02x\n", pcic_read(h, 0x02)); 1417 1.22 mycroft printf("cvsr = %02x\n", pcic_read(h, 0x2f)); 1418 1.22 mycroft printf("DANGER WILL ROBINSON! Changing voltage select!\n"); 1419 1.22 mycroft pcic_write(h, 0x2f, pcic_read(h, 0x2f) & ~0x03); 1420 1.22 mycroft printf("cvsr = %02x\n", pcic_read(h, 0x2f)); 1421 1.22 mycroft #endif 1422 1.72.2.3 skrll 1423 1.2 thorpej /* power up the socket */ 1424 1.72.2.3 skrll power |= PCIC_PWRCTL_PWR_ENABLE | PCIC_PWRCTL_VPP1_VCC; 1425 1.72.2.3 skrll pcic_write(h, PCIC_PWRCTL, power); 1426 1.9 enami 1427 1.9 enami /* 1428 1.72.2.3 skrll * Table 4-18 and figure 4-6 of the PC Card specifiction say: 1429 1.72.2.3 skrll * Vcc Rising Time (Tpr) = 100ms 1430 1.72.2.3 skrll * RESET Width (Th (Hi-z RESET)) = 1ms 1431 1.72.2.3 skrll * RESET Width (Tw (RESET)) = 10us 1432 1.12 msaitoh * 1433 1.12 msaitoh * some machines require some more time to be settled 1434 1.72.2.3 skrll * (100ms is added here). 1435 1.9 enami */ 1436 1.72.2.3 skrll pcic_delay(h, 200 + 1, "pccen1"); 1437 1.38 chopps 1438 1.72.2.3 skrll /* negate RESET */ 1439 1.72.2.3 skrll intr |= PCIC_INTR_RESET; 1440 1.38 chopps pcic_write(h, PCIC_INTR, intr); 1441 1.9 enami 1442 1.9 enami /* 1443 1.72.2.3 skrll * RESET Setup Time (Tsu (RESET)) = 20ms 1444 1.9 enami */ 1445 1.30 enami pcic_delay(h, 20, "pccen2"); 1446 1.2 thorpej 1447 1.20 msaitoh #ifdef DIAGNOSTIC 1448 1.72.2.3 skrll reg = pcic_read(h, PCIC_IF_STATUS); 1449 1.72.2.3 skrll if ((reg & PCIC_IF_STATUS_POWERACTIVE) == 0) 1450 1.72.2.3 skrll printf("pcic_chip_socket_enable: no power, status=%x\n", reg); 1451 1.20 msaitoh #endif 1452 1.72.2.3 skrll 1453 1.38 chopps /* wait for the chip to finish initializing */ 1454 1.72.2.3 skrll if (pcic_wait_ready(h)) { 1455 1.72.2.3 skrll /* XXX return a failure status?? */ 1456 1.72.2.3 skrll pcic_write(h, PCIC_PWRCTL, 0); 1457 1.72.2.3 skrll return; 1458 1.72.2.3 skrll } 1459 1.2 thorpej 1460 1.2 thorpej /* reinstall all the memory and io mappings */ 1461 1.2 thorpej for (win = 0; win < PCIC_MEM_WINS; win++) 1462 1.2 thorpej if (h->memalloc & (1 << win)) 1463 1.2 thorpej pcic_chip_do_mem_map(h, win); 1464 1.2 thorpej for (win = 0; win < PCIC_IO_WINS; win++) 1465 1.2 thorpej if (h->ioalloc & (1 << win)) 1466 1.2 thorpej pcic_chip_do_io_map(h, win); 1467 1.34 chopps 1468 1.41 chopps h->flags |= PCIC_FLAG_ENABLED; 1469 1.2 thorpej } 1470 1.2 thorpej 1471 1.2 thorpej void 1472 1.2 thorpej pcic_chip_socket_disable(pch) 1473 1.2 thorpej pcmcia_chipset_handle_t pch; 1474 1.2 thorpej { 1475 1.2 thorpej struct pcic_handle *h = (struct pcic_handle *) pch; 1476 1.72.2.3 skrll u_int8_t intr; 1477 1.2 thorpej 1478 1.2 thorpej DPRINTF(("pcic_chip_socket_disable\n")); 1479 1.38 chopps 1480 1.72.2.3 skrll /* disable interrupts; assert RESET */ 1481 1.39 enami intr = pcic_read(h, PCIC_INTR); 1482 1.72.2.3 skrll intr &= PCIC_INTR_ENABLE; 1483 1.38 chopps pcic_write(h, PCIC_INTR, intr); 1484 1.2 thorpej 1485 1.52 mycroft /* zero out the address windows */ 1486 1.52 mycroft pcic_write(h, PCIC_ADDRWIN_ENABLE, 0); 1487 1.41 chopps 1488 1.72.2.3 skrll /* disable socket: negate output enable bit and power off */ 1489 1.72.2.2 skrll pcic_write(h, PCIC_PWRCTL, 0); 1490 1.72.2.2 skrll 1491 1.72.2.3 skrll /* 1492 1.72.2.3 skrll * Vcc Falling Time (Tpf) = 300ms 1493 1.72.2.3 skrll */ 1494 1.72.2.3 skrll pcic_delay(h, 300, "pccwr1"); 1495 1.72.2.3 skrll 1496 1.41 chopps h->flags &= ~PCIC_FLAG_ENABLED; 1497 1.25 haya } 1498 1.25 haya 1499 1.72.2.2 skrll void 1500 1.72.2.2 skrll pcic_chip_socket_settype(pch, type) 1501 1.72.2.2 skrll pcmcia_chipset_handle_t pch; 1502 1.72.2.2 skrll int type; 1503 1.72.2.2 skrll { 1504 1.72.2.2 skrll struct pcic_handle *h = (struct pcic_handle *) pch; 1505 1.72.2.2 skrll int intr; 1506 1.72.2.2 skrll 1507 1.72.2.2 skrll intr = pcic_read(h, PCIC_INTR); 1508 1.72.2.2 skrll intr &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_CARDTYPE_MASK); 1509 1.72.2.2 skrll if (type == PCMCIA_IFTYPE_IO) { 1510 1.72.2.2 skrll intr |= PCIC_INTR_CARDTYPE_IO; 1511 1.72.2.2 skrll intr |= h->ih_irq << PCIC_INTR_IRQ_SHIFT; 1512 1.72.2.2 skrll } else 1513 1.72.2.2 skrll intr |= PCIC_INTR_CARDTYPE_MEM; 1514 1.72.2.2 skrll pcic_write(h, PCIC_INTR, intr); 1515 1.72.2.2 skrll 1516 1.72.2.2 skrll DPRINTF(("%s: pcic_chip_socket_settype %02x type %s %02x\n", 1517 1.72.2.2 skrll h->ph_parent->dv_xname, h->sock, 1518 1.72.2.2 skrll ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr)); 1519 1.72.2.2 skrll } 1520 1.72.2.2 skrll 1521 1.25 haya static u_int8_t 1522 1.25 haya st_pcic_read(h, idx) 1523 1.27 sommerfe struct pcic_handle *h; 1524 1.27 sommerfe int idx; 1525 1.25 haya { 1526 1.35 enami 1527 1.27 sommerfe if (idx != -1) 1528 1.27 sommerfe bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_INDEX, 1529 1.27 sommerfe h->sock + idx); 1530 1.35 enami return (bus_space_read_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_DATA)); 1531 1.25 haya } 1532 1.25 haya 1533 1.25 haya static void 1534 1.25 haya st_pcic_write(h, idx, data) 1535 1.27 sommerfe struct pcic_handle *h; 1536 1.27 sommerfe int idx; 1537 1.27 sommerfe u_int8_t data; 1538 1.27 sommerfe { 1539 1.35 enami 1540 1.27 sommerfe if (idx != -1) 1541 1.27 sommerfe bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_INDEX, 1542 1.27 sommerfe h->sock + idx); 1543 1.27 sommerfe bus_space_write_1(h->ph_bus_t, h->ph_bus_h, PCIC_REG_DATA, data); 1544 1.2 thorpej } 1545
Indexes created Tue Oct 28 02:10:10 GMT 2025