i82365.c revision 1.14
1 /* $NetBSD: i82365.c,v 1.14 1998/11/16 22:41:01 thorpej Exp $ */ 2 3 #define PCICDEBUG 4 5 /* 6 * Copyright (c) 1997 Marc Horowitz. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Marc Horowitz. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/types.h> 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/device.h> 38 #include <sys/extent.h> 39 #include <sys/malloc.h> 40 #include <sys/kthread.h> 41 42 #include <vm/vm.h> 43 44 #include <machine/bus.h> 45 #include <machine/intr.h> 46 47 #include <dev/pcmcia/pcmciareg.h> 48 #include <dev/pcmcia/pcmciavar.h> 49 50 #include <dev/ic/i82365reg.h> 51 #include <dev/ic/i82365var.h> 52 53 #include "locators.h" 54 55 #ifdef PCICDEBUG 56 int pcic_debug = 0; 57 #define DPRINTF(arg) if (pcic_debug) printf arg; 58 #else 59 #define DPRINTF(arg) 60 #endif 61 62 #define PCIC_VENDOR_UNKNOWN 0 63 #define PCIC_VENDOR_I82365SLR0 1 64 #define PCIC_VENDOR_I82365SLR1 2 65 #define PCIC_VENDOR_CIRRUS_PD6710 3 66 #define PCIC_VENDOR_CIRRUS_PD672X 4 67 68 /* 69 * Individual drivers will allocate their own memory and io regions. Memory 70 * regions must be a multiple of 4k, aligned on a 4k boundary. 71 */ 72 73 #define PCIC_MEM_ALIGN PCIC_MEM_PAGESIZE 74 75 void pcic_attach_socket __P((struct pcic_handle *)); 76 void pcic_init_socket __P((struct pcic_handle *)); 77 78 int pcic_submatch __P((struct device *, struct cfdata *, void *)); 79 int pcic_print __P((void *arg, const char *pnp)); 80 int pcic_intr_socket __P((struct pcic_handle *)); 81 82 void pcic_attach_card __P((struct pcic_handle *)); 83 void pcic_detach_card __P((struct pcic_handle *)); 84 85 void pcic_chip_do_mem_map __P((struct pcic_handle *, int)); 86 void pcic_chip_do_io_map __P((struct pcic_handle *, int)); 87 88 void pcic_create_event_thread __P((void *)); 89 void pcic_event_thread __P((void *)); 90 91 void pcic_queue_event __P((struct pcic_handle *, int)); 92 93 static void pcic_wait_ready __P((struct pcic_handle *)); 94 95 int 96 pcic_ident_ok(ident) 97 int ident; 98 { 99 /* this is very empirical and heuristic */ 100 101 if ((ident == 0) || (ident == 0xff) || (ident & PCIC_IDENT_ZERO)) 102 return (0); 103 104 if ((ident & PCIC_IDENT_IFTYPE_MASK) != PCIC_IDENT_IFTYPE_MEM_AND_IO) { 105 #ifdef DIAGNOSTIC 106 printf("pcic: does not support memory and I/O cards, " 107 "ignored (ident=%0x)\n", ident); 108 #endif 109 return (0); 110 } 111 return (1); 112 } 113 114 int 115 pcic_vendor(h) 116 struct pcic_handle *h; 117 { 118 int reg; 119 120 /* 121 * the chip_id of the cirrus toggles between 11 and 00 after a write. 122 * weird. 123 */ 124 125 pcic_write(h, PCIC_CIRRUS_CHIP_INFO, 0); 126 reg = pcic_read(h, -1); 127 128 if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) == 129 PCIC_CIRRUS_CHIP_INFO_CHIP_ID) { 130 reg = pcic_read(h, -1); 131 if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) == 0) { 132 if (reg & PCIC_CIRRUS_CHIP_INFO_SLOTS) 133 return (PCIC_VENDOR_CIRRUS_PD672X); 134 else 135 return (PCIC_VENDOR_CIRRUS_PD6710); 136 } 137 } 138 /* XXX how do I identify the GD6729? */ 139 140 reg = pcic_read(h, PCIC_IDENT); 141 142 if ((reg & PCIC_IDENT_REV_MASK) == PCIC_IDENT_REV_I82365SLR0) 143 return (PCIC_VENDOR_I82365SLR0); 144 else 145 return (PCIC_VENDOR_I82365SLR1); 146 147 return (PCIC_VENDOR_UNKNOWN); 148 } 149 150 char * 151 pcic_vendor_to_string(vendor) 152 int vendor; 153 { 154 switch (vendor) { 155 case PCIC_VENDOR_I82365SLR0: 156 return ("Intel 82365SL Revision 0"); 157 case PCIC_VENDOR_I82365SLR1: 158 return ("Intel 82365SL Revision 1"); 159 case PCIC_VENDOR_CIRRUS_PD6710: 160 return ("Cirrus PD6710"); 161 case PCIC_VENDOR_CIRRUS_PD672X: 162 return ("Cirrus PD672X"); 163 } 164 165 return ("Unknown controller"); 166 } 167 168 void 169 pcic_attach(sc) 170 struct pcic_softc *sc; 171 { 172 int vendor, count, i, reg; 173 174 /* now check for each controller/socket */ 175 176 /* 177 * this could be done with a loop, but it would violate the 178 * abstraction 179 */ 180 181 count = 0; 182 183 DPRINTF(("pcic ident regs:")); 184 185 sc->handle[0].sc = sc; 186 sc->handle[0].sock = C0SA; 187 if (pcic_ident_ok(reg = pcic_read(&sc->handle[0], PCIC_IDENT))) { 188 sc->handle[0].flags = PCIC_FLAG_SOCKETP; 189 count++; 190 } else { 191 sc->handle[0].flags = 0; 192 } 193 194 DPRINTF((" 0x%02x", reg)); 195 196 sc->handle[1].sc = sc; 197 sc->handle[1].sock = C0SB; 198 if (pcic_ident_ok(reg = pcic_read(&sc->handle[1], PCIC_IDENT))) { 199 sc->handle[1].flags = PCIC_FLAG_SOCKETP; 200 count++; 201 } else { 202 sc->handle[1].flags = 0; 203 } 204 205 DPRINTF((" 0x%02x", reg)); 206 207 sc->handle[2].sc = sc; 208 sc->handle[2].sock = C1SA; 209 if (pcic_ident_ok(reg = pcic_read(&sc->handle[2], PCIC_IDENT))) { 210 sc->handle[2].flags = PCIC_FLAG_SOCKETP; 211 count++; 212 } else { 213 sc->handle[2].flags = 0; 214 } 215 216 DPRINTF((" 0x%02x", reg)); 217 218 sc->handle[3].sc = sc; 219 sc->handle[3].sock = C1SB; 220 if (pcic_ident_ok(reg = pcic_read(&sc->handle[3], PCIC_IDENT))) { 221 sc->handle[3].flags = PCIC_FLAG_SOCKETP; 222 count++; 223 } else { 224 sc->handle[3].flags = 0; 225 } 226 227 DPRINTF((" 0x%02x\n", reg)); 228 229 if (count == 0) 230 panic("pcic_attach: attach found no sockets"); 231 232 /* establish the interrupt */ 233 234 /* XXX block interrupts? */ 235 236 for (i = 0; i < PCIC_NSLOTS; i++) { 237 SIMPLEQ_INIT(&sc->handle[i].events); 238 #if 0 239 /* 240 * this should work, but w/o it, setting tty flags hangs at 241 * boot time. 242 */ 243 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 244 #endif 245 { 246 pcic_write(&sc->handle[i], PCIC_CSC_INTR, 0); 247 pcic_read(&sc->handle[i], PCIC_CSC); 248 } 249 } 250 251 if ((sc->handle[0].flags & PCIC_FLAG_SOCKETP) || 252 (sc->handle[1].flags & PCIC_FLAG_SOCKETP)) { 253 vendor = pcic_vendor(&sc->handle[0]); 254 255 printf("%s: controller 0 (%s) has ", sc->dev.dv_xname, 256 pcic_vendor_to_string(vendor)); 257 258 if ((sc->handle[0].flags & PCIC_FLAG_SOCKETP) && 259 (sc->handle[1].flags & PCIC_FLAG_SOCKETP)) 260 printf("sockets A and B\n"); 261 else if (sc->handle[0].flags & PCIC_FLAG_SOCKETP) 262 printf("socket A only\n"); 263 else 264 printf("socket B only\n"); 265 266 if (sc->handle[0].flags & PCIC_FLAG_SOCKETP) 267 sc->handle[0].vendor = vendor; 268 if (sc->handle[1].flags & PCIC_FLAG_SOCKETP) 269 sc->handle[1].vendor = vendor; 270 } 271 if ((sc->handle[2].flags & PCIC_FLAG_SOCKETP) || 272 (sc->handle[3].flags & PCIC_FLAG_SOCKETP)) { 273 vendor = pcic_vendor(&sc->handle[2]); 274 275 printf("%s: controller 1 (%s) has ", sc->dev.dv_xname, 276 pcic_vendor_to_string(vendor)); 277 278 if ((sc->handle[2].flags & PCIC_FLAG_SOCKETP) && 279 (sc->handle[3].flags & PCIC_FLAG_SOCKETP)) 280 printf("sockets A and B\n"); 281 else if (sc->handle[2].flags & PCIC_FLAG_SOCKETP) 282 printf("socket A only\n"); 283 else 284 printf("socket B only\n"); 285 286 if (sc->handle[2].flags & PCIC_FLAG_SOCKETP) 287 sc->handle[2].vendor = vendor; 288 if (sc->handle[3].flags & PCIC_FLAG_SOCKETP) 289 sc->handle[3].vendor = vendor; 290 } 291 } 292 293 void 294 pcic_attach_sockets(sc) 295 struct pcic_softc *sc; 296 { 297 int i; 298 299 for (i = 0; i < PCIC_NSLOTS; i++) 300 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 301 pcic_attach_socket(&sc->handle[i]); 302 } 303 304 void 305 pcic_attach_socket(h) 306 struct pcic_handle *h; 307 { 308 struct pcmciabus_attach_args paa; 309 310 /* initialize the rest of the handle */ 311 312 h->shutdown = 0; 313 h->memalloc = 0; 314 h->ioalloc = 0; 315 h->ih_irq = 0; 316 317 /* now, config one pcmcia device per socket */ 318 319 paa.pct = (pcmcia_chipset_tag_t) h->sc->pct; 320 paa.pch = (pcmcia_chipset_handle_t) h; 321 paa.iobase = h->sc->iobase; 322 paa.iosize = h->sc->iosize; 323 324 h->pcmcia = config_found_sm(&h->sc->dev, &paa, pcic_print, 325 pcic_submatch); 326 327 /* if there's actually a pcmcia device attached, initialize the slot */ 328 329 if (h->pcmcia) 330 pcic_init_socket(h); 331 } 332 333 void 334 pcic_create_event_thread(arg) 335 void *arg; 336 { 337 struct pcic_handle *h = arg; 338 const char *cs; 339 340 switch (h->sock) { 341 case C0SA: 342 cs = "0,0"; 343 break; 344 case C0SB: 345 cs = "0,1"; 346 break; 347 case C1SA: 348 cs = "1,0"; 349 break; 350 case C1SB: 351 cs = "1,1"; 352 break; 353 default: 354 panic("pcic_create_event_thread: unknown pcic socket"); 355 } 356 357 if (kthread_create(pcic_event_thread, h, &h->event_thread, 358 "%s,%s", h->sc->dev.dv_xname, cs)) { 359 printf("%s: unable to create event thread for sock 0x%02x\n", 360 h->sc->dev.dv_xname, h->sock); 361 panic("pcic_create_event_thread"); 362 } 363 } 364 365 void 366 pcic_event_thread(arg) 367 void *arg; 368 { 369 struct pcic_handle *h = arg; 370 struct pcic_event *pe; 371 int s; 372 373 while (h->shutdown == 0) { 374 s = splhigh(); 375 if ((pe = SIMPLEQ_FIRST(&h->events)) == NULL) { 376 splx(s); 377 (void) tsleep(&h->events, PWAIT, "pcicev", 0); 378 continue; 379 } 380 SIMPLEQ_REMOVE_HEAD(&h->events, pe, pe_q); 381 splx(s); 382 383 switch (pe->pe_type) { 384 case PCIC_EVENT_INSERTION: 385 DPRINTF(("%s: insertion event\n", h->sc->dev.dv_xname)); 386 pcic_attach_card(h); 387 break; 388 389 case PCIC_EVENT_REMOVAL: 390 DPRINTF(("%s: removal event\n", h->sc->dev.dv_xname)); 391 pcic_detach_card(h); 392 break; 393 394 default: 395 panic("pcic_event_thread: unknown event %d", 396 pe->pe_type); 397 } 398 free(pe, M_TEMP); 399 } 400 401 h->event_thread = NULL; 402 403 /* In case parent is waiting for us to exit. */ 404 wakeup(h->sc); 405 406 kthread_exit(0); 407 } 408 409 void 410 pcic_init_socket(h) 411 struct pcic_handle *h; 412 { 413 int reg; 414 415 /* 416 * queue creation of a kernel thread to handle insert/removal events. 417 */ 418 #ifdef DIAGNOSTIC 419 if (h->event_thread != NULL) 420 panic("pcic_attach_socket: event thread"); 421 #endif 422 kthread_create_deferred(pcic_create_event_thread, h); 423 424 /* set up the card to interrupt on card detect */ 425 426 pcic_write(h, PCIC_CSC_INTR, (h->sc->irq << PCIC_CSC_INTR_IRQ_SHIFT) | 427 PCIC_CSC_INTR_CD_ENABLE); 428 pcic_write(h, PCIC_INTR, 0); 429 pcic_read(h, PCIC_CSC); 430 431 /* unsleep the cirrus controller */ 432 433 if ((h->vendor == PCIC_VENDOR_CIRRUS_PD6710) || 434 (h->vendor == PCIC_VENDOR_CIRRUS_PD672X)) { 435 reg = pcic_read(h, PCIC_CIRRUS_MISC_CTL_2); 436 if (reg & PCIC_CIRRUS_MISC_CTL_2_SUSPEND) { 437 DPRINTF(("%s: socket %02x was suspended\n", 438 h->sc->dev.dv_xname, h->sock)); 439 reg &= ~PCIC_CIRRUS_MISC_CTL_2_SUSPEND; 440 pcic_write(h, PCIC_CIRRUS_MISC_CTL_2, reg); 441 } 442 } 443 /* if there's a card there, then attach it. */ 444 445 reg = pcic_read(h, PCIC_IF_STATUS); 446 447 if ((reg & PCIC_IF_STATUS_CARDDETECT_MASK) == 448 PCIC_IF_STATUS_CARDDETECT_PRESENT) 449 pcic_attach_card(h); 450 } 451 452 int 453 pcic_submatch(parent, cf, aux) 454 struct device *parent; 455 struct cfdata *cf; 456 void *aux; 457 { 458 459 struct pcmciabus_attach_args *paa = aux; 460 struct pcic_handle *h = (struct pcic_handle *) paa->pch; 461 462 switch (h->sock) { 463 case C0SA: 464 if (cf->cf_loc[PCICCF_CONTROLLER] != 465 PCICCF_CONTROLLER_DEFAULT && 466 cf->cf_loc[PCICCF_CONTROLLER] != 0) 467 return 0; 468 if (cf->cf_loc[PCICCF_SOCKET] != PCICCF_SOCKET_DEFAULT && 469 cf->cf_loc[PCICCF_SOCKET] != 0) 470 return 0; 471 472 break; 473 case C0SB: 474 if (cf->cf_loc[PCICCF_CONTROLLER] != 475 PCICCF_CONTROLLER_DEFAULT && 476 cf->cf_loc[PCICCF_CONTROLLER] != 0) 477 return 0; 478 if (cf->cf_loc[PCICCF_SOCKET] != PCICCF_SOCKET_DEFAULT && 479 cf->cf_loc[PCICCF_SOCKET] != 1) 480 return 0; 481 482 break; 483 case C1SA: 484 if (cf->cf_loc[PCICCF_CONTROLLER] != 485 PCICCF_CONTROLLER_DEFAULT && 486 cf->cf_loc[PCICCF_CONTROLLER] != 1) 487 return 0; 488 if (cf->cf_loc[PCICCF_SOCKET] != PCICCF_SOCKET_DEFAULT && 489 cf->cf_loc[PCICCF_SOCKET] != 0) 490 return 0; 491 492 break; 493 case C1SB: 494 if (cf->cf_loc[PCICCF_CONTROLLER] != 495 PCICCF_CONTROLLER_DEFAULT && 496 cf->cf_loc[PCICCF_CONTROLLER] != 1) 497 return 0; 498 if (cf->cf_loc[PCICCF_SOCKET] != PCICCF_SOCKET_DEFAULT && 499 cf->cf_loc[PCICCF_SOCKET] != 1) 500 return 0; 501 502 break; 503 default: 504 panic("unknown pcic socket"); 505 } 506 507 return ((*cf->cf_attach->ca_match)(parent, cf, aux)); 508 } 509 510 int 511 pcic_print(arg, pnp) 512 void *arg; 513 const char *pnp; 514 { 515 struct pcmciabus_attach_args *paa = arg; 516 struct pcic_handle *h = (struct pcic_handle *) paa->pch; 517 518 /* Only "pcmcia"s can attach to "pcic"s... easy. */ 519 if (pnp) 520 printf("pcmcia at %s", pnp); 521 522 switch (h->sock) { 523 case C0SA: 524 printf(" controller 0 socket 0"); 525 break; 526 case C0SB: 527 printf(" controller 0 socket 1"); 528 break; 529 case C1SA: 530 printf(" controller 1 socket 0"); 531 break; 532 case C1SB: 533 printf(" controller 1 socket 1"); 534 break; 535 default: 536 panic("unknown pcic socket"); 537 } 538 539 return (UNCONF); 540 } 541 542 int 543 pcic_intr(arg) 544 void *arg; 545 { 546 struct pcic_softc *sc = arg; 547 int i, ret = 0; 548 549 DPRINTF(("%s: intr\n", sc->dev.dv_xname)); 550 551 for (i = 0; i < PCIC_NSLOTS; i++) 552 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 553 ret += pcic_intr_socket(&sc->handle[i]); 554 555 return (ret ? 1 : 0); 556 } 557 558 int 559 pcic_intr_socket(h) 560 struct pcic_handle *h; 561 { 562 int cscreg; 563 564 cscreg = pcic_read(h, PCIC_CSC); 565 566 cscreg &= (PCIC_CSC_GPI | 567 PCIC_CSC_CD | 568 PCIC_CSC_READY | 569 PCIC_CSC_BATTWARN | 570 PCIC_CSC_BATTDEAD); 571 572 if (cscreg & PCIC_CSC_GPI) { 573 DPRINTF(("%s: %02x GPI\n", h->sc->dev.dv_xname, h->sock)); 574 } 575 if (cscreg & PCIC_CSC_CD) { 576 int statreg; 577 578 statreg = pcic_read(h, PCIC_IF_STATUS); 579 580 DPRINTF(("%s: %02x CD %x\n", h->sc->dev.dv_xname, h->sock, 581 statreg)); 582 583 if ((statreg & PCIC_IF_STATUS_CARDDETECT_MASK) == 584 PCIC_IF_STATUS_CARDDETECT_PRESENT) { 585 if (!(h->flags & PCIC_FLAG_CARDP)) { 586 DPRINTF(("%s: enqueing INSERTION event\n", 587 h->sc->dev.dv_xname)); 588 pcic_queue_event(h, PCIC_EVENT_INSERTION); 589 } 590 } else { 591 if (h->flags & PCIC_FLAG_CARDP) { 592 /* XXX Should deactivate children NOW. */ 593 DPRINTF(("%s: enqueing REMOVAL event\n", 594 h->sc->dev.dv_xname)); 595 pcic_queue_event(h, PCIC_EVENT_REMOVAL); 596 } 597 } 598 } 599 if (cscreg & PCIC_CSC_READY) { 600 DPRINTF(("%s: %02x READY\n", h->sc->dev.dv_xname, h->sock)); 601 /* shouldn't happen */ 602 } 603 if (cscreg & PCIC_CSC_BATTWARN) { 604 DPRINTF(("%s: %02x BATTWARN\n", h->sc->dev.dv_xname, h->sock)); 605 } 606 if (cscreg & PCIC_CSC_BATTDEAD) { 607 DPRINTF(("%s: %02x BATTDEAD\n", h->sc->dev.dv_xname, h->sock)); 608 } 609 return (cscreg ? 1 : 0); 610 } 611 612 void 613 pcic_queue_event(h, event) 614 struct pcic_handle *h; 615 int event; 616 { 617 struct pcic_event *pe; 618 int s; 619 620 pe = malloc(sizeof(*pe), M_TEMP, M_NOWAIT); 621 if (pe == NULL) 622 panic("pcic_queue_event: can't allocate event"); 623 624 pe->pe_type = event; 625 s = splhigh(); 626 SIMPLEQ_INSERT_TAIL(&h->events, pe, pe_q); 627 splx(s); 628 wakeup(&h->events); 629 } 630 631 void 632 pcic_attach_card(h) 633 struct pcic_handle *h; 634 { 635 if (h->flags & PCIC_FLAG_CARDP) 636 panic("pcic_attach_card: already attached"); 637 638 /* call the MI attach function */ 639 640 pcmcia_card_attach(h->pcmcia); 641 642 h->flags |= PCIC_FLAG_CARDP; 643 } 644 645 void 646 pcic_detach_card(h) 647 struct pcic_handle *h; 648 { 649 if (!(h->flags & PCIC_FLAG_CARDP)) 650 panic("pcic_attach_card: already detached"); 651 652 h->flags &= ~PCIC_FLAG_CARDP; 653 654 /* call the MI attach function */ 655 656 pcmcia_card_detach(h->pcmcia); 657 658 /* disable card detect resume and configuration reset */ 659 660 /* power down the socket */ 661 662 pcic_write(h, PCIC_PWRCTL, 0); 663 664 /* reset the card */ 665 666 pcic_write(h, PCIC_INTR, 0); 667 } 668 669 int 670 pcic_chip_mem_alloc(pch, size, pcmhp) 671 pcmcia_chipset_handle_t pch; 672 bus_size_t size; 673 struct pcmcia_mem_handle *pcmhp; 674 { 675 struct pcic_handle *h = (struct pcic_handle *) pch; 676 bus_space_handle_t memh; 677 bus_addr_t addr; 678 bus_size_t sizepg; 679 int i, mask, mhandle; 680 681 /* out of sc->memh, allocate as many pages as necessary */ 682 683 /* convert size to PCIC pages */ 684 sizepg = (size + (PCIC_MEM_ALIGN - 1)) / PCIC_MEM_ALIGN; 685 686 mask = (1 << sizepg) - 1; 687 688 addr = 0; /* XXX gcc -Wuninitialized */ 689 mhandle = 0; /* XXX gcc -Wuninitialized */ 690 691 for (i = 0; i < (PCIC_MEM_PAGES + 1 - sizepg); i++) { 692 if ((h->sc->subregionmask & (mask << i)) == (mask << i)) { 693 if (bus_space_subregion(h->sc->memt, h->sc->memh, 694 i * PCIC_MEM_PAGESIZE, 695 sizepg * PCIC_MEM_PAGESIZE, &memh)) 696 return (1); 697 mhandle = mask << i; 698 addr = h->sc->membase + (i * PCIC_MEM_PAGESIZE); 699 h->sc->subregionmask &= ~(mhandle); 700 break; 701 } 702 } 703 704 if (i == (PCIC_MEM_PAGES + 1 - size)) 705 return (1); 706 707 DPRINTF(("pcic_chip_mem_alloc bus addr 0x%lx+0x%lx\n", (u_long) addr, 708 (u_long) size)); 709 710 pcmhp->memt = h->sc->memt; 711 pcmhp->memh = memh; 712 pcmhp->addr = addr; 713 pcmhp->size = size; 714 pcmhp->mhandle = mhandle; 715 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 716 717 return (0); 718 } 719 720 void 721 pcic_chip_mem_free(pch, pcmhp) 722 pcmcia_chipset_handle_t pch; 723 struct pcmcia_mem_handle *pcmhp; 724 { 725 struct pcic_handle *h = (struct pcic_handle *) pch; 726 727 h->sc->subregionmask |= pcmhp->mhandle; 728 } 729 730 static struct mem_map_index_st { 731 int sysmem_start_lsb; 732 int sysmem_start_msb; 733 int sysmem_stop_lsb; 734 int sysmem_stop_msb; 735 int cardmem_lsb; 736 int cardmem_msb; 737 int memenable; 738 } mem_map_index[] = { 739 { 740 PCIC_SYSMEM_ADDR0_START_LSB, 741 PCIC_SYSMEM_ADDR0_START_MSB, 742 PCIC_SYSMEM_ADDR0_STOP_LSB, 743 PCIC_SYSMEM_ADDR0_STOP_MSB, 744 PCIC_CARDMEM_ADDR0_LSB, 745 PCIC_CARDMEM_ADDR0_MSB, 746 PCIC_ADDRWIN_ENABLE_MEM0, 747 }, 748 { 749 PCIC_SYSMEM_ADDR1_START_LSB, 750 PCIC_SYSMEM_ADDR1_START_MSB, 751 PCIC_SYSMEM_ADDR1_STOP_LSB, 752 PCIC_SYSMEM_ADDR1_STOP_MSB, 753 PCIC_CARDMEM_ADDR1_LSB, 754 PCIC_CARDMEM_ADDR1_MSB, 755 PCIC_ADDRWIN_ENABLE_MEM1, 756 }, 757 { 758 PCIC_SYSMEM_ADDR2_START_LSB, 759 PCIC_SYSMEM_ADDR2_START_MSB, 760 PCIC_SYSMEM_ADDR2_STOP_LSB, 761 PCIC_SYSMEM_ADDR2_STOP_MSB, 762 PCIC_CARDMEM_ADDR2_LSB, 763 PCIC_CARDMEM_ADDR2_MSB, 764 PCIC_ADDRWIN_ENABLE_MEM2, 765 }, 766 { 767 PCIC_SYSMEM_ADDR3_START_LSB, 768 PCIC_SYSMEM_ADDR3_START_MSB, 769 PCIC_SYSMEM_ADDR3_STOP_LSB, 770 PCIC_SYSMEM_ADDR3_STOP_MSB, 771 PCIC_CARDMEM_ADDR3_LSB, 772 PCIC_CARDMEM_ADDR3_MSB, 773 PCIC_ADDRWIN_ENABLE_MEM3, 774 }, 775 { 776 PCIC_SYSMEM_ADDR4_START_LSB, 777 PCIC_SYSMEM_ADDR4_START_MSB, 778 PCIC_SYSMEM_ADDR4_STOP_LSB, 779 PCIC_SYSMEM_ADDR4_STOP_MSB, 780 PCIC_CARDMEM_ADDR4_LSB, 781 PCIC_CARDMEM_ADDR4_MSB, 782 PCIC_ADDRWIN_ENABLE_MEM4, 783 }, 784 }; 785 786 void 787 pcic_chip_do_mem_map(h, win) 788 struct pcic_handle *h; 789 int win; 790 { 791 int reg; 792 793 pcic_write(h, mem_map_index[win].sysmem_start_lsb, 794 (h->mem[win].addr >> PCIC_SYSMEM_ADDRX_SHIFT) & 0xff); 795 pcic_write(h, mem_map_index[win].sysmem_start_msb, 796 ((h->mem[win].addr >> (PCIC_SYSMEM_ADDRX_SHIFT + 8)) & 797 PCIC_SYSMEM_ADDRX_START_MSB_ADDR_MASK)); 798 799 #if 0 800 /* XXX do I want 16 bit all the time? */ 801 PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT; 802 #endif 803 804 pcic_write(h, mem_map_index[win].sysmem_stop_lsb, 805 ((h->mem[win].addr + h->mem[win].size) >> 806 PCIC_SYSMEM_ADDRX_SHIFT) & 0xff); 807 pcic_write(h, mem_map_index[win].sysmem_stop_msb, 808 (((h->mem[win].addr + h->mem[win].size) >> 809 (PCIC_SYSMEM_ADDRX_SHIFT + 8)) & 810 PCIC_SYSMEM_ADDRX_STOP_MSB_ADDR_MASK) | 811 PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2); 812 813 pcic_write(h, mem_map_index[win].cardmem_lsb, 814 (h->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff); 815 pcic_write(h, mem_map_index[win].cardmem_msb, 816 ((h->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) & 817 PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) | 818 ((h->mem[win].kind == PCMCIA_MEM_ATTR) ? 819 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0)); 820 821 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 822 reg |= (mem_map_index[win].memenable | PCIC_ADDRWIN_ENABLE_MEMCS16); 823 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 824 825 #ifdef PCICDEBUG 826 { 827 int r1, r2, r3, r4, r5, r6; 828 829 r1 = pcic_read(h, mem_map_index[win].sysmem_start_msb); 830 r2 = pcic_read(h, mem_map_index[win].sysmem_start_lsb); 831 r3 = pcic_read(h, mem_map_index[win].sysmem_stop_msb); 832 r4 = pcic_read(h, mem_map_index[win].sysmem_stop_lsb); 833 r5 = pcic_read(h, mem_map_index[win].cardmem_msb); 834 r6 = pcic_read(h, mem_map_index[win].cardmem_lsb); 835 836 DPRINTF(("pcic_chip_do_mem_map window %d: %02x%02x %02x%02x " 837 "%02x%02x\n", win, r1, r2, r3, r4, r5, r6)); 838 } 839 #endif 840 } 841 842 int 843 pcic_chip_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 844 pcmcia_chipset_handle_t pch; 845 int kind; 846 bus_addr_t card_addr; 847 bus_size_t size; 848 struct pcmcia_mem_handle *pcmhp; 849 bus_addr_t *offsetp; 850 int *windowp; 851 { 852 struct pcic_handle *h = (struct pcic_handle *) pch; 853 bus_addr_t busaddr; 854 long card_offset; 855 int i, win; 856 857 win = -1; 858 for (i = 0; i < (sizeof(mem_map_index) / sizeof(mem_map_index[0])); 859 i++) { 860 if ((h->memalloc & (1 << i)) == 0) { 861 win = i; 862 h->memalloc |= (1 << i); 863 break; 864 } 865 } 866 867 if (win == -1) 868 return (1); 869 870 *windowp = win; 871 872 /* XXX this is pretty gross */ 873 874 if (h->sc->memt != pcmhp->memt) 875 panic("pcic_chip_mem_map memt is bogus"); 876 877 busaddr = pcmhp->addr; 878 879 /* 880 * compute the address offset to the pcmcia address space for the 881 * pcic. this is intentionally signed. The masks and shifts below 882 * will cause TRT to happen in the pcic registers. Deal with making 883 * sure the address is aligned, and return the alignment offset. 884 */ 885 886 *offsetp = card_addr % PCIC_MEM_ALIGN; 887 card_addr -= *offsetp; 888 889 DPRINTF(("pcic_chip_mem_map window %d bus %lx+%lx+%lx at card addr " 890 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 891 (u_long) card_addr)); 892 893 /* 894 * include the offset in the size, and decrement size by one, since 895 * the hw wants start/stop 896 */ 897 size += *offsetp - 1; 898 899 card_offset = (((long) card_addr) - ((long) busaddr)); 900 901 h->mem[win].addr = busaddr; 902 h->mem[win].size = size; 903 h->mem[win].offset = card_offset; 904 h->mem[win].kind = kind; 905 906 pcic_chip_do_mem_map(h, win); 907 908 return (0); 909 } 910 911 void 912 pcic_chip_mem_unmap(pch, window) 913 pcmcia_chipset_handle_t pch; 914 int window; 915 { 916 struct pcic_handle *h = (struct pcic_handle *) pch; 917 int reg; 918 919 if (window >= (sizeof(mem_map_index) / sizeof(mem_map_index[0]))) 920 panic("pcic_chip_mem_unmap: window out of range"); 921 922 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 923 reg &= ~mem_map_index[window].memenable; 924 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 925 926 h->memalloc &= ~(1 << window); 927 } 928 929 int 930 pcic_chip_io_alloc(pch, start, size, align, pcihp) 931 pcmcia_chipset_handle_t pch; 932 bus_addr_t start; 933 bus_size_t size; 934 bus_size_t align; 935 struct pcmcia_io_handle *pcihp; 936 { 937 struct pcic_handle *h = (struct pcic_handle *) pch; 938 bus_space_tag_t iot; 939 bus_space_handle_t ioh; 940 bus_addr_t ioaddr; 941 int flags = 0; 942 943 /* 944 * Allocate some arbitrary I/O space. 945 */ 946 947 iot = h->sc->iot; 948 949 if (start) { 950 ioaddr = start; 951 if (bus_space_map(iot, start, size, 0, &ioh)) 952 return (1); 953 DPRINTF(("pcic_chip_io_alloc map port %lx+%lx\n", 954 (u_long) ioaddr, (u_long) size)); 955 } else { 956 flags |= PCMCIA_IO_ALLOCATED; 957 if (bus_space_alloc(iot, h->sc->iobase, 958 h->sc->iobase + h->sc->iosize, size, align, 0, 0, 959 &ioaddr, &ioh)) 960 return (1); 961 DPRINTF(("pcic_chip_io_alloc alloc port %lx+%lx\n", 962 (u_long) ioaddr, (u_long) size)); 963 } 964 965 pcihp->iot = iot; 966 pcihp->ioh = ioh; 967 pcihp->addr = ioaddr; 968 pcihp->size = size; 969 pcihp->flags = flags; 970 971 return (0); 972 } 973 974 void 975 pcic_chip_io_free(pch, pcihp) 976 pcmcia_chipset_handle_t pch; 977 struct pcmcia_io_handle *pcihp; 978 { 979 bus_space_tag_t iot = pcihp->iot; 980 bus_space_handle_t ioh = pcihp->ioh; 981 bus_size_t size = pcihp->size; 982 983 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 984 bus_space_free(iot, ioh, size); 985 else 986 bus_space_unmap(iot, ioh, size); 987 } 988 989 990 static struct io_map_index_st { 991 int start_lsb; 992 int start_msb; 993 int stop_lsb; 994 int stop_msb; 995 int ioenable; 996 int ioctlmask; 997 int ioctlbits[3]; /* indexed by PCMCIA_WIDTH_* */ 998 } io_map_index[] = { 999 { 1000 PCIC_IOADDR0_START_LSB, 1001 PCIC_IOADDR0_START_MSB, 1002 PCIC_IOADDR0_STOP_LSB, 1003 PCIC_IOADDR0_STOP_MSB, 1004 PCIC_ADDRWIN_ENABLE_IO0, 1005 PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 1006 PCIC_IOCTL_IO0_IOCS16SRC_MASK | PCIC_IOCTL_IO0_DATASIZE_MASK, 1007 { 1008 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 1009 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1010 PCIC_IOCTL_IO0_DATASIZE_8BIT, 1011 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1012 PCIC_IOCTL_IO0_DATASIZE_16BIT, 1013 }, 1014 }, 1015 { 1016 PCIC_IOADDR1_START_LSB, 1017 PCIC_IOADDR1_START_MSB, 1018 PCIC_IOADDR1_STOP_LSB, 1019 PCIC_IOADDR1_STOP_MSB, 1020 PCIC_ADDRWIN_ENABLE_IO1, 1021 PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 1022 PCIC_IOCTL_IO1_IOCS16SRC_MASK | PCIC_IOCTL_IO1_DATASIZE_MASK, 1023 { 1024 PCIC_IOCTL_IO1_IOCS16SRC_CARD, 1025 PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE | 1026 PCIC_IOCTL_IO1_DATASIZE_8BIT, 1027 PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE | 1028 PCIC_IOCTL_IO1_DATASIZE_16BIT, 1029 }, 1030 }, 1031 }; 1032 1033 void 1034 pcic_chip_do_io_map(h, win) 1035 struct pcic_handle *h; 1036 int win; 1037 { 1038 int reg; 1039 1040 DPRINTF(("pcic_chip_do_io_map win %d addr %lx size %lx width %d\n", 1041 win, (long) h->io[win].addr, (long) h->io[win].size, 1042 h->io[win].width * 8)); 1043 1044 pcic_write(h, io_map_index[win].start_lsb, h->io[win].addr & 0xff); 1045 pcic_write(h, io_map_index[win].start_msb, 1046 (h->io[win].addr >> 8) & 0xff); 1047 1048 pcic_write(h, io_map_index[win].stop_lsb, 1049 (h->io[win].addr + h->io[win].size - 1) & 0xff); 1050 pcic_write(h, io_map_index[win].stop_msb, 1051 ((h->io[win].addr + h->io[win].size - 1) >> 8) & 0xff); 1052 1053 reg = pcic_read(h, PCIC_IOCTL); 1054 reg &= ~io_map_index[win].ioctlmask; 1055 reg |= io_map_index[win].ioctlbits[h->io[win].width]; 1056 pcic_write(h, PCIC_IOCTL, reg); 1057 1058 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1059 reg |= io_map_index[win].ioenable; 1060 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1061 } 1062 1063 int 1064 pcic_chip_io_map(pch, width, offset, size, pcihp, windowp) 1065 pcmcia_chipset_handle_t pch; 1066 int width; 1067 bus_addr_t offset; 1068 bus_size_t size; 1069 struct pcmcia_io_handle *pcihp; 1070 int *windowp; 1071 { 1072 struct pcic_handle *h = (struct pcic_handle *) pch; 1073 bus_addr_t ioaddr = pcihp->addr + offset; 1074 int i, win; 1075 #ifdef PCICDEBUG 1076 static char *width_names[] = { "auto", "io8", "io16" }; 1077 #endif 1078 1079 /* XXX Sanity check offset/size. */ 1080 1081 win = -1; 1082 for (i = 0; i < (sizeof(io_map_index) / sizeof(io_map_index[0])); i++) { 1083 if ((h->ioalloc & (1 << i)) == 0) { 1084 win = i; 1085 h->ioalloc |= (1 << i); 1086 break; 1087 } 1088 } 1089 1090 if (win == -1) 1091 return (1); 1092 1093 *windowp = win; 1094 1095 /* XXX this is pretty gross */ 1096 1097 if (h->sc->iot != pcihp->iot) 1098 panic("pcic_chip_io_map iot is bogus"); 1099 1100 DPRINTF(("pcic_chip_io_map window %d %s port %lx+%lx\n", 1101 win, width_names[width], (u_long) ioaddr, (u_long) size)); 1102 1103 /* XXX wtf is this doing here? */ 1104 1105 printf(" port 0x%lx", (u_long) ioaddr); 1106 if (size > 1) 1107 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 1108 1109 h->io[win].addr = ioaddr; 1110 h->io[win].size = size; 1111 h->io[win].width = width; 1112 1113 pcic_chip_do_io_map(h, win); 1114 1115 return (0); 1116 } 1117 1118 void 1119 pcic_chip_io_unmap(pch, window) 1120 pcmcia_chipset_handle_t pch; 1121 int window; 1122 { 1123 struct pcic_handle *h = (struct pcic_handle *) pch; 1124 int reg; 1125 1126 if (window >= (sizeof(io_map_index) / sizeof(io_map_index[0]))) 1127 panic("pcic_chip_io_unmap: window out of range"); 1128 1129 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1130 reg &= ~io_map_index[window].ioenable; 1131 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1132 1133 h->ioalloc &= ~(1 << window); 1134 } 1135 1136 static void 1137 pcic_wait_ready(h) 1138 struct pcic_handle *h; 1139 { 1140 int i; 1141 1142 for (i = 0; i < 10000; i++) { 1143 if (pcic_read(h, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) 1144 return; 1145 delay(500); 1146 #ifdef PCICDEBUG 1147 if (pcic_debug) { 1148 if ((i>5000) && (i%100 == 99)) 1149 printf("."); 1150 } 1151 #endif 1152 } 1153 1154 #ifdef DIAGNOSTIC 1155 printf("pcic_wait_ready: ready never happened, status = %02x\n", 1156 pcic_read(h, PCIC_IF_STATUS)); 1157 #endif 1158 } 1159 1160 void 1161 pcic_chip_socket_enable(pch) 1162 pcmcia_chipset_handle_t pch; 1163 { 1164 struct pcic_handle *h = (struct pcic_handle *) pch; 1165 int cardtype, reg, win; 1166 1167 /* this bit is mostly stolen from pcic_attach_card */ 1168 1169 /* power down the socket to reset it, clear the card reset pin */ 1170 1171 pcic_write(h, PCIC_PWRCTL, 0); 1172 1173 /* 1174 * wait 300ms until power fails (Tpf). Then, wait 100ms since 1175 * we are changing Vcc (Toff). 1176 */ 1177 delay((300 + 100) * 1000); 1178 1179 /* power up the socket */ 1180 1181 pcic_write(h, PCIC_PWRCTL, PCIC_PWRCTL_DISABLE_RESETDRV 1182 | PCIC_PWRCTL_PWR_ENABLE); 1183 1184 /* 1185 * wait 100ms until power raise (Tpr) and 20ms to become 1186 * stable (Tsu(Vcc)). 1187 * 1188 * some machines require some more time to be settled 1189 * (another 200ms is added here). 1190 */ 1191 delay((100 + 20 + 200) * 1000); 1192 1193 pcic_write(h, PCIC_PWRCTL, PCIC_PWRCTL_DISABLE_RESETDRV | PCIC_PWRCTL_OE 1194 | PCIC_PWRCTL_PWR_ENABLE); 1195 pcic_write(h, PCIC_INTR, 0); 1196 1197 /* 1198 * hold RESET at least 10us. 1199 */ 1200 delay(10); 1201 1202 /* clear the reset flag */ 1203 1204 pcic_write(h, PCIC_INTR, PCIC_INTR_RESET); 1205 1206 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 1207 1208 delay(20000); 1209 1210 /* wait for the chip to finish initializing */ 1211 1212 pcic_wait_ready(h); 1213 1214 /* zero out the address windows */ 1215 1216 pcic_write(h, PCIC_ADDRWIN_ENABLE, 0); 1217 1218 /* set the card type */ 1219 1220 cardtype = pcmcia_card_gettype(h->pcmcia); 1221 1222 reg = pcic_read(h, PCIC_INTR); 1223 reg &= ~PCIC_INTR_CARDTYPE_MASK; 1224 reg |= ((cardtype == PCMCIA_IFTYPE_IO) ? 1225 PCIC_INTR_CARDTYPE_IO : 1226 PCIC_INTR_CARDTYPE_MEM); 1227 reg |= h->ih_irq; 1228 pcic_write(h, PCIC_INTR, reg); 1229 1230 DPRINTF(("%s: pcic_chip_socket_enable %02x cardtype %s %02x\n", 1231 h->sc->dev.dv_xname, h->sock, 1232 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), reg)); 1233 1234 /* reinstall all the memory and io mappings */ 1235 1236 for (win = 0; win < PCIC_MEM_WINS; win++) 1237 if (h->memalloc & (1 << win)) 1238 pcic_chip_do_mem_map(h, win); 1239 1240 for (win = 0; win < PCIC_IO_WINS; win++) 1241 if (h->ioalloc & (1 << win)) 1242 pcic_chip_do_io_map(h, win); 1243 } 1244 1245 void 1246 pcic_chip_socket_disable(pch) 1247 pcmcia_chipset_handle_t pch; 1248 { 1249 struct pcic_handle *h = (struct pcic_handle *) pch; 1250 1251 DPRINTF(("pcic_chip_socket_disable\n")); 1252 1253 /* power down the socket */ 1254 1255 pcic_write(h, PCIC_PWRCTL, 0); 1256 1257 /* 1258 * wait 300ms until power fails (Tpf). 1259 */ 1260 delay(300 * 1000); 1261 } 1262
Indexes created Fri Sep 26 20:09:58 GMT 2025