i82365.c revision 1.15
1 /* $NetBSD: i82365.c,v 1.15 1998/11/17 08:49:11 thorpej Exp $ */ 2 3 #define PCICDEBUG 4 5 /* 6 * Copyright (c) 1997 Marc Horowitz. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Marc Horowitz. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/types.h> 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/device.h> 38 #include <sys/extent.h> 39 #include <sys/malloc.h> 40 #include <sys/kthread.h> 41 42 #include <vm/vm.h> 43 44 #include <machine/bus.h> 45 #include <machine/intr.h> 46 47 #include <dev/pcmcia/pcmciareg.h> 48 #include <dev/pcmcia/pcmciavar.h> 49 50 #include <dev/ic/i82365reg.h> 51 #include <dev/ic/i82365var.h> 52 53 #include "locators.h" 54 55 #ifdef PCICDEBUG 56 int pcic_debug = 0; 57 #define DPRINTF(arg) if (pcic_debug) printf arg; 58 #else 59 #define DPRINTF(arg) 60 #endif 61 62 #define PCIC_VENDOR_UNKNOWN 0 63 #define PCIC_VENDOR_I82365SLR0 1 64 #define PCIC_VENDOR_I82365SLR1 2 65 #define PCIC_VENDOR_CIRRUS_PD6710 3 66 #define PCIC_VENDOR_CIRRUS_PD672X 4 67 68 /* 69 * Individual drivers will allocate their own memory and io regions. Memory 70 * regions must be a multiple of 4k, aligned on a 4k boundary. 71 */ 72 73 #define PCIC_MEM_ALIGN PCIC_MEM_PAGESIZE 74 75 void pcic_attach_socket __P((struct pcic_handle *)); 76 void pcic_init_socket __P((struct pcic_handle *)); 77 78 int pcic_submatch __P((struct device *, struct cfdata *, void *)); 79 int pcic_print __P((void *arg, const char *pnp)); 80 int pcic_intr_socket __P((struct pcic_handle *)); 81 82 void pcic_attach_card __P((struct pcic_handle *)); 83 void pcic_detach_card __P((struct pcic_handle *, int)); 84 void pcic_deactivate_card __P((struct pcic_handle *)); 85 86 void pcic_chip_do_mem_map __P((struct pcic_handle *, int)); 87 void pcic_chip_do_io_map __P((struct pcic_handle *, int)); 88 89 void pcic_create_event_thread __P((void *)); 90 void pcic_event_thread __P((void *)); 91 92 void pcic_queue_event __P((struct pcic_handle *, int)); 93 94 static void pcic_wait_ready __P((struct pcic_handle *)); 95 96 int 97 pcic_ident_ok(ident) 98 int ident; 99 { 100 /* this is very empirical and heuristic */ 101 102 if ((ident == 0) || (ident == 0xff) || (ident & PCIC_IDENT_ZERO)) 103 return (0); 104 105 if ((ident & PCIC_IDENT_IFTYPE_MASK) != PCIC_IDENT_IFTYPE_MEM_AND_IO) { 106 #ifdef DIAGNOSTIC 107 printf("pcic: does not support memory and I/O cards, " 108 "ignored (ident=%0x)\n", ident); 109 #endif 110 return (0); 111 } 112 return (1); 113 } 114 115 int 116 pcic_vendor(h) 117 struct pcic_handle *h; 118 { 119 int reg; 120 121 /* 122 * the chip_id of the cirrus toggles between 11 and 00 after a write. 123 * weird. 124 */ 125 126 pcic_write(h, PCIC_CIRRUS_CHIP_INFO, 0); 127 reg = pcic_read(h, -1); 128 129 if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) == 130 PCIC_CIRRUS_CHIP_INFO_CHIP_ID) { 131 reg = pcic_read(h, -1); 132 if ((reg & PCIC_CIRRUS_CHIP_INFO_CHIP_ID) == 0) { 133 if (reg & PCIC_CIRRUS_CHIP_INFO_SLOTS) 134 return (PCIC_VENDOR_CIRRUS_PD672X); 135 else 136 return (PCIC_VENDOR_CIRRUS_PD6710); 137 } 138 } 139 /* XXX how do I identify the GD6729? */ 140 141 reg = pcic_read(h, PCIC_IDENT); 142 143 if ((reg & PCIC_IDENT_REV_MASK) == PCIC_IDENT_REV_I82365SLR0) 144 return (PCIC_VENDOR_I82365SLR0); 145 else 146 return (PCIC_VENDOR_I82365SLR1); 147 148 return (PCIC_VENDOR_UNKNOWN); 149 } 150 151 char * 152 pcic_vendor_to_string(vendor) 153 int vendor; 154 { 155 switch (vendor) { 156 case PCIC_VENDOR_I82365SLR0: 157 return ("Intel 82365SL Revision 0"); 158 case PCIC_VENDOR_I82365SLR1: 159 return ("Intel 82365SL Revision 1"); 160 case PCIC_VENDOR_CIRRUS_PD6710: 161 return ("Cirrus PD6710"); 162 case PCIC_VENDOR_CIRRUS_PD672X: 163 return ("Cirrus PD672X"); 164 } 165 166 return ("Unknown controller"); 167 } 168 169 void 170 pcic_attach(sc) 171 struct pcic_softc *sc; 172 { 173 int vendor, count, i, reg; 174 175 /* now check for each controller/socket */ 176 177 /* 178 * this could be done with a loop, but it would violate the 179 * abstraction 180 */ 181 182 count = 0; 183 184 DPRINTF(("pcic ident regs:")); 185 186 sc->handle[0].sc = sc; 187 sc->handle[0].sock = C0SA; 188 if (pcic_ident_ok(reg = pcic_read(&sc->handle[0], PCIC_IDENT))) { 189 sc->handle[0].flags = PCIC_FLAG_SOCKETP; 190 count++; 191 } else { 192 sc->handle[0].flags = 0; 193 } 194 195 DPRINTF((" 0x%02x", reg)); 196 197 sc->handle[1].sc = sc; 198 sc->handle[1].sock = C0SB; 199 if (pcic_ident_ok(reg = pcic_read(&sc->handle[1], PCIC_IDENT))) { 200 sc->handle[1].flags = PCIC_FLAG_SOCKETP; 201 count++; 202 } else { 203 sc->handle[1].flags = 0; 204 } 205 206 DPRINTF((" 0x%02x", reg)); 207 208 sc->handle[2].sc = sc; 209 sc->handle[2].sock = C1SA; 210 if (pcic_ident_ok(reg = pcic_read(&sc->handle[2], PCIC_IDENT))) { 211 sc->handle[2].flags = PCIC_FLAG_SOCKETP; 212 count++; 213 } else { 214 sc->handle[2].flags = 0; 215 } 216 217 DPRINTF((" 0x%02x", reg)); 218 219 sc->handle[3].sc = sc; 220 sc->handle[3].sock = C1SB; 221 if (pcic_ident_ok(reg = pcic_read(&sc->handle[3], PCIC_IDENT))) { 222 sc->handle[3].flags = PCIC_FLAG_SOCKETP; 223 count++; 224 } else { 225 sc->handle[3].flags = 0; 226 } 227 228 DPRINTF((" 0x%02x\n", reg)); 229 230 if (count == 0) 231 panic("pcic_attach: attach found no sockets"); 232 233 /* establish the interrupt */ 234 235 /* XXX block interrupts? */ 236 237 for (i = 0; i < PCIC_NSLOTS; i++) { 238 SIMPLEQ_INIT(&sc->handle[i].events); 239 #if 0 240 /* 241 * this should work, but w/o it, setting tty flags hangs at 242 * boot time. 243 */ 244 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 245 #endif 246 { 247 pcic_write(&sc->handle[i], PCIC_CSC_INTR, 0); 248 pcic_read(&sc->handle[i], PCIC_CSC); 249 } 250 } 251 252 if ((sc->handle[0].flags & PCIC_FLAG_SOCKETP) || 253 (sc->handle[1].flags & PCIC_FLAG_SOCKETP)) { 254 vendor = pcic_vendor(&sc->handle[0]); 255 256 printf("%s: controller 0 (%s) has ", sc->dev.dv_xname, 257 pcic_vendor_to_string(vendor)); 258 259 if ((sc->handle[0].flags & PCIC_FLAG_SOCKETP) && 260 (sc->handle[1].flags & PCIC_FLAG_SOCKETP)) 261 printf("sockets A and B\n"); 262 else if (sc->handle[0].flags & PCIC_FLAG_SOCKETP) 263 printf("socket A only\n"); 264 else 265 printf("socket B only\n"); 266 267 if (sc->handle[0].flags & PCIC_FLAG_SOCKETP) 268 sc->handle[0].vendor = vendor; 269 if (sc->handle[1].flags & PCIC_FLAG_SOCKETP) 270 sc->handle[1].vendor = vendor; 271 } 272 if ((sc->handle[2].flags & PCIC_FLAG_SOCKETP) || 273 (sc->handle[3].flags & PCIC_FLAG_SOCKETP)) { 274 vendor = pcic_vendor(&sc->handle[2]); 275 276 printf("%s: controller 1 (%s) has ", sc->dev.dv_xname, 277 pcic_vendor_to_string(vendor)); 278 279 if ((sc->handle[2].flags & PCIC_FLAG_SOCKETP) && 280 (sc->handle[3].flags & PCIC_FLAG_SOCKETP)) 281 printf("sockets A and B\n"); 282 else if (sc->handle[2].flags & PCIC_FLAG_SOCKETP) 283 printf("socket A only\n"); 284 else 285 printf("socket B only\n"); 286 287 if (sc->handle[2].flags & PCIC_FLAG_SOCKETP) 288 sc->handle[2].vendor = vendor; 289 if (sc->handle[3].flags & PCIC_FLAG_SOCKETP) 290 sc->handle[3].vendor = vendor; 291 } 292 } 293 294 void 295 pcic_attach_sockets(sc) 296 struct pcic_softc *sc; 297 { 298 int i; 299 300 for (i = 0; i < PCIC_NSLOTS; i++) 301 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 302 pcic_attach_socket(&sc->handle[i]); 303 } 304 305 void 306 pcic_attach_socket(h) 307 struct pcic_handle *h; 308 { 309 struct pcmciabus_attach_args paa; 310 311 /* initialize the rest of the handle */ 312 313 h->shutdown = 0; 314 h->memalloc = 0; 315 h->ioalloc = 0; 316 h->ih_irq = 0; 317 318 /* now, config one pcmcia device per socket */ 319 320 paa.pct = (pcmcia_chipset_tag_t) h->sc->pct; 321 paa.pch = (pcmcia_chipset_handle_t) h; 322 paa.iobase = h->sc->iobase; 323 paa.iosize = h->sc->iosize; 324 325 h->pcmcia = config_found_sm(&h->sc->dev, &paa, pcic_print, 326 pcic_submatch); 327 328 /* if there's actually a pcmcia device attached, initialize the slot */ 329 330 if (h->pcmcia) 331 pcic_init_socket(h); 332 } 333 334 void 335 pcic_create_event_thread(arg) 336 void *arg; 337 { 338 struct pcic_handle *h = arg; 339 const char *cs; 340 341 switch (h->sock) { 342 case C0SA: 343 cs = "0,0"; 344 break; 345 case C0SB: 346 cs = "0,1"; 347 break; 348 case C1SA: 349 cs = "1,0"; 350 break; 351 case C1SB: 352 cs = "1,1"; 353 break; 354 default: 355 panic("pcic_create_event_thread: unknown pcic socket"); 356 } 357 358 if (kthread_create(pcic_event_thread, h, &h->event_thread, 359 "%s,%s", h->sc->dev.dv_xname, cs)) { 360 printf("%s: unable to create event thread for sock 0x%02x\n", 361 h->sc->dev.dv_xname, h->sock); 362 panic("pcic_create_event_thread"); 363 } 364 } 365 366 void 367 pcic_event_thread(arg) 368 void *arg; 369 { 370 struct pcic_handle *h = arg; 371 struct pcic_event *pe; 372 int s; 373 374 while (h->shutdown == 0) { 375 s = splhigh(); 376 if ((pe = SIMPLEQ_FIRST(&h->events)) == NULL) { 377 splx(s); 378 (void) tsleep(&h->events, PWAIT, "pcicev", 0); 379 continue; 380 } 381 SIMPLEQ_REMOVE_HEAD(&h->events, pe, pe_q); 382 splx(s); 383 384 switch (pe->pe_type) { 385 case PCIC_EVENT_INSERTION: 386 DPRINTF(("%s: insertion event\n", h->sc->dev.dv_xname)); 387 pcic_attach_card(h); 388 break; 389 390 case PCIC_EVENT_REMOVAL: 391 DPRINTF(("%s: removal event\n", h->sc->dev.dv_xname)); 392 pcic_detach_card(h, DETACH_FORCE); 393 break; 394 395 default: 396 panic("pcic_event_thread: unknown event %d", 397 pe->pe_type); 398 } 399 free(pe, M_TEMP); 400 } 401 402 h->event_thread = NULL; 403 404 /* In case parent is waiting for us to exit. */ 405 wakeup(h->sc); 406 407 kthread_exit(0); 408 } 409 410 void 411 pcic_init_socket(h) 412 struct pcic_handle *h; 413 { 414 int reg; 415 416 /* 417 * queue creation of a kernel thread to handle insert/removal events. 418 */ 419 #ifdef DIAGNOSTIC 420 if (h->event_thread != NULL) 421 panic("pcic_attach_socket: event thread"); 422 #endif 423 kthread_create_deferred(pcic_create_event_thread, h); 424 425 /* set up the card to interrupt on card detect */ 426 427 pcic_write(h, PCIC_CSC_INTR, (h->sc->irq << PCIC_CSC_INTR_IRQ_SHIFT) | 428 PCIC_CSC_INTR_CD_ENABLE); 429 pcic_write(h, PCIC_INTR, 0); 430 pcic_read(h, PCIC_CSC); 431 432 /* unsleep the cirrus controller */ 433 434 if ((h->vendor == PCIC_VENDOR_CIRRUS_PD6710) || 435 (h->vendor == PCIC_VENDOR_CIRRUS_PD672X)) { 436 reg = pcic_read(h, PCIC_CIRRUS_MISC_CTL_2); 437 if (reg & PCIC_CIRRUS_MISC_CTL_2_SUSPEND) { 438 DPRINTF(("%s: socket %02x was suspended\n", 439 h->sc->dev.dv_xname, h->sock)); 440 reg &= ~PCIC_CIRRUS_MISC_CTL_2_SUSPEND; 441 pcic_write(h, PCIC_CIRRUS_MISC_CTL_2, reg); 442 } 443 } 444 /* if there's a card there, then attach it. */ 445 446 reg = pcic_read(h, PCIC_IF_STATUS); 447 448 if ((reg & PCIC_IF_STATUS_CARDDETECT_MASK) == 449 PCIC_IF_STATUS_CARDDETECT_PRESENT) 450 pcic_attach_card(h); 451 } 452 453 int 454 pcic_submatch(parent, cf, aux) 455 struct device *parent; 456 struct cfdata *cf; 457 void *aux; 458 { 459 460 struct pcmciabus_attach_args *paa = aux; 461 struct pcic_handle *h = (struct pcic_handle *) paa->pch; 462 463 switch (h->sock) { 464 case C0SA: 465 if (cf->cf_loc[PCICCF_CONTROLLER] != 466 PCICCF_CONTROLLER_DEFAULT && 467 cf->cf_loc[PCICCF_CONTROLLER] != 0) 468 return 0; 469 if (cf->cf_loc[PCICCF_SOCKET] != PCICCF_SOCKET_DEFAULT && 470 cf->cf_loc[PCICCF_SOCKET] != 0) 471 return 0; 472 473 break; 474 case C0SB: 475 if (cf->cf_loc[PCICCF_CONTROLLER] != 476 PCICCF_CONTROLLER_DEFAULT && 477 cf->cf_loc[PCICCF_CONTROLLER] != 0) 478 return 0; 479 if (cf->cf_loc[PCICCF_SOCKET] != PCICCF_SOCKET_DEFAULT && 480 cf->cf_loc[PCICCF_SOCKET] != 1) 481 return 0; 482 483 break; 484 case C1SA: 485 if (cf->cf_loc[PCICCF_CONTROLLER] != 486 PCICCF_CONTROLLER_DEFAULT && 487 cf->cf_loc[PCICCF_CONTROLLER] != 1) 488 return 0; 489 if (cf->cf_loc[PCICCF_SOCKET] != PCICCF_SOCKET_DEFAULT && 490 cf->cf_loc[PCICCF_SOCKET] != 0) 491 return 0; 492 493 break; 494 case C1SB: 495 if (cf->cf_loc[PCICCF_CONTROLLER] != 496 PCICCF_CONTROLLER_DEFAULT && 497 cf->cf_loc[PCICCF_CONTROLLER] != 1) 498 return 0; 499 if (cf->cf_loc[PCICCF_SOCKET] != PCICCF_SOCKET_DEFAULT && 500 cf->cf_loc[PCICCF_SOCKET] != 1) 501 return 0; 502 503 break; 504 default: 505 panic("unknown pcic socket"); 506 } 507 508 return ((*cf->cf_attach->ca_match)(parent, cf, aux)); 509 } 510 511 int 512 pcic_print(arg, pnp) 513 void *arg; 514 const char *pnp; 515 { 516 struct pcmciabus_attach_args *paa = arg; 517 struct pcic_handle *h = (struct pcic_handle *) paa->pch; 518 519 /* Only "pcmcia"s can attach to "pcic"s... easy. */ 520 if (pnp) 521 printf("pcmcia at %s", pnp); 522 523 switch (h->sock) { 524 case C0SA: 525 printf(" controller 0 socket 0"); 526 break; 527 case C0SB: 528 printf(" controller 0 socket 1"); 529 break; 530 case C1SA: 531 printf(" controller 1 socket 0"); 532 break; 533 case C1SB: 534 printf(" controller 1 socket 1"); 535 break; 536 default: 537 panic("unknown pcic socket"); 538 } 539 540 return (UNCONF); 541 } 542 543 int 544 pcic_intr(arg) 545 void *arg; 546 { 547 struct pcic_softc *sc = arg; 548 int i, ret = 0; 549 550 DPRINTF(("%s: intr\n", sc->dev.dv_xname)); 551 552 for (i = 0; i < PCIC_NSLOTS; i++) 553 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 554 ret += pcic_intr_socket(&sc->handle[i]); 555 556 return (ret ? 1 : 0); 557 } 558 559 int 560 pcic_intr_socket(h) 561 struct pcic_handle *h; 562 { 563 int cscreg; 564 565 cscreg = pcic_read(h, PCIC_CSC); 566 567 cscreg &= (PCIC_CSC_GPI | 568 PCIC_CSC_CD | 569 PCIC_CSC_READY | 570 PCIC_CSC_BATTWARN | 571 PCIC_CSC_BATTDEAD); 572 573 if (cscreg & PCIC_CSC_GPI) { 574 DPRINTF(("%s: %02x GPI\n", h->sc->dev.dv_xname, h->sock)); 575 } 576 if (cscreg & PCIC_CSC_CD) { 577 int statreg; 578 579 statreg = pcic_read(h, PCIC_IF_STATUS); 580 581 DPRINTF(("%s: %02x CD %x\n", h->sc->dev.dv_xname, h->sock, 582 statreg)); 583 584 if ((statreg & PCIC_IF_STATUS_CARDDETECT_MASK) == 585 PCIC_IF_STATUS_CARDDETECT_PRESENT) { 586 if (!(h->flags & PCIC_FLAG_CARDP)) { 587 DPRINTF(("%s: enqueing INSERTION event\n", 588 h->sc->dev.dv_xname)); 589 pcic_queue_event(h, PCIC_EVENT_INSERTION); 590 } 591 } else { 592 if (h->flags & PCIC_FLAG_CARDP) { 593 /* Deactivate the card now. */ 594 DPRINTF(("%s: deactivating card\n", 595 h->sc->dev.dv_xname)); 596 pcic_deactivate_card(h); 597 598 DPRINTF(("%s: enqueing REMOVAL event\n", 599 h->sc->dev.dv_xname)); 600 pcic_queue_event(h, PCIC_EVENT_REMOVAL); 601 } 602 } 603 } 604 if (cscreg & PCIC_CSC_READY) { 605 DPRINTF(("%s: %02x READY\n", h->sc->dev.dv_xname, h->sock)); 606 /* shouldn't happen */ 607 } 608 if (cscreg & PCIC_CSC_BATTWARN) { 609 DPRINTF(("%s: %02x BATTWARN\n", h->sc->dev.dv_xname, h->sock)); 610 } 611 if (cscreg & PCIC_CSC_BATTDEAD) { 612 DPRINTF(("%s: %02x BATTDEAD\n", h->sc->dev.dv_xname, h->sock)); 613 } 614 return (cscreg ? 1 : 0); 615 } 616 617 void 618 pcic_queue_event(h, event) 619 struct pcic_handle *h; 620 int event; 621 { 622 struct pcic_event *pe; 623 int s; 624 625 pe = malloc(sizeof(*pe), M_TEMP, M_NOWAIT); 626 if (pe == NULL) 627 panic("pcic_queue_event: can't allocate event"); 628 629 pe->pe_type = event; 630 s = splhigh(); 631 SIMPLEQ_INSERT_TAIL(&h->events, pe, pe_q); 632 splx(s); 633 wakeup(&h->events); 634 } 635 636 void 637 pcic_attach_card(h) 638 struct pcic_handle *h; 639 { 640 641 if (h->flags & PCIC_FLAG_CARDP) 642 panic("pcic_attach_card: already attached"); 643 644 /* call the MI attach function */ 645 pcmcia_card_attach(h->pcmcia); 646 647 h->flags |= PCIC_FLAG_CARDP; 648 } 649 650 void 651 pcic_detach_card(h, flags) 652 struct pcic_handle *h; 653 int flags; /* DETACH_* */ 654 { 655 656 if (!(h->flags & PCIC_FLAG_CARDP)) 657 panic("pcic_attach_card: already detached"); 658 659 h->flags &= ~PCIC_FLAG_CARDP; 660 661 /* call the MI detach function */ 662 pcmcia_card_detach(h->pcmcia, flags); 663 } 664 665 void 666 pcic_deactivate_card(h) 667 struct pcic_handle *h; 668 { 669 670 if (!(h->flags & PCIC_FLAG_CARDP)) 671 panic("pcic_deactivate_card: already detached"); 672 673 /* call the MI deactivate function */ 674 pcmcia_card_deactivate(h->pcmcia); 675 676 /* power down the socket */ 677 pcic_write(h, PCIC_PWRCTL, 0); 678 679 /* reset the socket */ 680 pcic_write(h, PCIC_INTR, 0); 681 } 682 683 int 684 pcic_chip_mem_alloc(pch, size, pcmhp) 685 pcmcia_chipset_handle_t pch; 686 bus_size_t size; 687 struct pcmcia_mem_handle *pcmhp; 688 { 689 struct pcic_handle *h = (struct pcic_handle *) pch; 690 bus_space_handle_t memh; 691 bus_addr_t addr; 692 bus_size_t sizepg; 693 int i, mask, mhandle; 694 695 /* out of sc->memh, allocate as many pages as necessary */ 696 697 /* convert size to PCIC pages */ 698 sizepg = (size + (PCIC_MEM_ALIGN - 1)) / PCIC_MEM_ALIGN; 699 700 mask = (1 << sizepg) - 1; 701 702 addr = 0; /* XXX gcc -Wuninitialized */ 703 mhandle = 0; /* XXX gcc -Wuninitialized */ 704 705 for (i = 0; i < (PCIC_MEM_PAGES + 1 - sizepg); i++) { 706 if ((h->sc->subregionmask & (mask << i)) == (mask << i)) { 707 if (bus_space_subregion(h->sc->memt, h->sc->memh, 708 i * PCIC_MEM_PAGESIZE, 709 sizepg * PCIC_MEM_PAGESIZE, &memh)) 710 return (1); 711 mhandle = mask << i; 712 addr = h->sc->membase + (i * PCIC_MEM_PAGESIZE); 713 h->sc->subregionmask &= ~(mhandle); 714 break; 715 } 716 } 717 718 if (i == (PCIC_MEM_PAGES + 1 - size)) 719 return (1); 720 721 DPRINTF(("pcic_chip_mem_alloc bus addr 0x%lx+0x%lx\n", (u_long) addr, 722 (u_long) size)); 723 724 pcmhp->memt = h->sc->memt; 725 pcmhp->memh = memh; 726 pcmhp->addr = addr; 727 pcmhp->size = size; 728 pcmhp->mhandle = mhandle; 729 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE; 730 731 return (0); 732 } 733 734 void 735 pcic_chip_mem_free(pch, pcmhp) 736 pcmcia_chipset_handle_t pch; 737 struct pcmcia_mem_handle *pcmhp; 738 { 739 struct pcic_handle *h = (struct pcic_handle *) pch; 740 741 h->sc->subregionmask |= pcmhp->mhandle; 742 } 743 744 static struct mem_map_index_st { 745 int sysmem_start_lsb; 746 int sysmem_start_msb; 747 int sysmem_stop_lsb; 748 int sysmem_stop_msb; 749 int cardmem_lsb; 750 int cardmem_msb; 751 int memenable; 752 } mem_map_index[] = { 753 { 754 PCIC_SYSMEM_ADDR0_START_LSB, 755 PCIC_SYSMEM_ADDR0_START_MSB, 756 PCIC_SYSMEM_ADDR0_STOP_LSB, 757 PCIC_SYSMEM_ADDR0_STOP_MSB, 758 PCIC_CARDMEM_ADDR0_LSB, 759 PCIC_CARDMEM_ADDR0_MSB, 760 PCIC_ADDRWIN_ENABLE_MEM0, 761 }, 762 { 763 PCIC_SYSMEM_ADDR1_START_LSB, 764 PCIC_SYSMEM_ADDR1_START_MSB, 765 PCIC_SYSMEM_ADDR1_STOP_LSB, 766 PCIC_SYSMEM_ADDR1_STOP_MSB, 767 PCIC_CARDMEM_ADDR1_LSB, 768 PCIC_CARDMEM_ADDR1_MSB, 769 PCIC_ADDRWIN_ENABLE_MEM1, 770 }, 771 { 772 PCIC_SYSMEM_ADDR2_START_LSB, 773 PCIC_SYSMEM_ADDR2_START_MSB, 774 PCIC_SYSMEM_ADDR2_STOP_LSB, 775 PCIC_SYSMEM_ADDR2_STOP_MSB, 776 PCIC_CARDMEM_ADDR2_LSB, 777 PCIC_CARDMEM_ADDR2_MSB, 778 PCIC_ADDRWIN_ENABLE_MEM2, 779 }, 780 { 781 PCIC_SYSMEM_ADDR3_START_LSB, 782 PCIC_SYSMEM_ADDR3_START_MSB, 783 PCIC_SYSMEM_ADDR3_STOP_LSB, 784 PCIC_SYSMEM_ADDR3_STOP_MSB, 785 PCIC_CARDMEM_ADDR3_LSB, 786 PCIC_CARDMEM_ADDR3_MSB, 787 PCIC_ADDRWIN_ENABLE_MEM3, 788 }, 789 { 790 PCIC_SYSMEM_ADDR4_START_LSB, 791 PCIC_SYSMEM_ADDR4_START_MSB, 792 PCIC_SYSMEM_ADDR4_STOP_LSB, 793 PCIC_SYSMEM_ADDR4_STOP_MSB, 794 PCIC_CARDMEM_ADDR4_LSB, 795 PCIC_CARDMEM_ADDR4_MSB, 796 PCIC_ADDRWIN_ENABLE_MEM4, 797 }, 798 }; 799 800 void 801 pcic_chip_do_mem_map(h, win) 802 struct pcic_handle *h; 803 int win; 804 { 805 int reg; 806 807 pcic_write(h, mem_map_index[win].sysmem_start_lsb, 808 (h->mem[win].addr >> PCIC_SYSMEM_ADDRX_SHIFT) & 0xff); 809 pcic_write(h, mem_map_index[win].sysmem_start_msb, 810 ((h->mem[win].addr >> (PCIC_SYSMEM_ADDRX_SHIFT + 8)) & 811 PCIC_SYSMEM_ADDRX_START_MSB_ADDR_MASK)); 812 813 #if 0 814 /* XXX do I want 16 bit all the time? */ 815 PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT; 816 #endif 817 818 pcic_write(h, mem_map_index[win].sysmem_stop_lsb, 819 ((h->mem[win].addr + h->mem[win].size) >> 820 PCIC_SYSMEM_ADDRX_SHIFT) & 0xff); 821 pcic_write(h, mem_map_index[win].sysmem_stop_msb, 822 (((h->mem[win].addr + h->mem[win].size) >> 823 (PCIC_SYSMEM_ADDRX_SHIFT + 8)) & 824 PCIC_SYSMEM_ADDRX_STOP_MSB_ADDR_MASK) | 825 PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2); 826 827 pcic_write(h, mem_map_index[win].cardmem_lsb, 828 (h->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff); 829 pcic_write(h, mem_map_index[win].cardmem_msb, 830 ((h->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8)) & 831 PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK) | 832 ((h->mem[win].kind == PCMCIA_MEM_ATTR) ? 833 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0)); 834 835 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 836 reg |= (mem_map_index[win].memenable | PCIC_ADDRWIN_ENABLE_MEMCS16); 837 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 838 839 #ifdef PCICDEBUG 840 { 841 int r1, r2, r3, r4, r5, r6; 842 843 r1 = pcic_read(h, mem_map_index[win].sysmem_start_msb); 844 r2 = pcic_read(h, mem_map_index[win].sysmem_start_lsb); 845 r3 = pcic_read(h, mem_map_index[win].sysmem_stop_msb); 846 r4 = pcic_read(h, mem_map_index[win].sysmem_stop_lsb); 847 r5 = pcic_read(h, mem_map_index[win].cardmem_msb); 848 r6 = pcic_read(h, mem_map_index[win].cardmem_lsb); 849 850 DPRINTF(("pcic_chip_do_mem_map window %d: %02x%02x %02x%02x " 851 "%02x%02x\n", win, r1, r2, r3, r4, r5, r6)); 852 } 853 #endif 854 } 855 856 int 857 pcic_chip_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 858 pcmcia_chipset_handle_t pch; 859 int kind; 860 bus_addr_t card_addr; 861 bus_size_t size; 862 struct pcmcia_mem_handle *pcmhp; 863 bus_addr_t *offsetp; 864 int *windowp; 865 { 866 struct pcic_handle *h = (struct pcic_handle *) pch; 867 bus_addr_t busaddr; 868 long card_offset; 869 int i, win; 870 871 win = -1; 872 for (i = 0; i < (sizeof(mem_map_index) / sizeof(mem_map_index[0])); 873 i++) { 874 if ((h->memalloc & (1 << i)) == 0) { 875 win = i; 876 h->memalloc |= (1 << i); 877 break; 878 } 879 } 880 881 if (win == -1) 882 return (1); 883 884 *windowp = win; 885 886 /* XXX this is pretty gross */ 887 888 if (h->sc->memt != pcmhp->memt) 889 panic("pcic_chip_mem_map memt is bogus"); 890 891 busaddr = pcmhp->addr; 892 893 /* 894 * compute the address offset to the pcmcia address space for the 895 * pcic. this is intentionally signed. The masks and shifts below 896 * will cause TRT to happen in the pcic registers. Deal with making 897 * sure the address is aligned, and return the alignment offset. 898 */ 899 900 *offsetp = card_addr % PCIC_MEM_ALIGN; 901 card_addr -= *offsetp; 902 903 DPRINTF(("pcic_chip_mem_map window %d bus %lx+%lx+%lx at card addr " 904 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 905 (u_long) card_addr)); 906 907 /* 908 * include the offset in the size, and decrement size by one, since 909 * the hw wants start/stop 910 */ 911 size += *offsetp - 1; 912 913 card_offset = (((long) card_addr) - ((long) busaddr)); 914 915 h->mem[win].addr = busaddr; 916 h->mem[win].size = size; 917 h->mem[win].offset = card_offset; 918 h->mem[win].kind = kind; 919 920 pcic_chip_do_mem_map(h, win); 921 922 return (0); 923 } 924 925 void 926 pcic_chip_mem_unmap(pch, window) 927 pcmcia_chipset_handle_t pch; 928 int window; 929 { 930 struct pcic_handle *h = (struct pcic_handle *) pch; 931 int reg; 932 933 if (window >= (sizeof(mem_map_index) / sizeof(mem_map_index[0]))) 934 panic("pcic_chip_mem_unmap: window out of range"); 935 936 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 937 reg &= ~mem_map_index[window].memenable; 938 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 939 940 h->memalloc &= ~(1 << window); 941 } 942 943 int 944 pcic_chip_io_alloc(pch, start, size, align, pcihp) 945 pcmcia_chipset_handle_t pch; 946 bus_addr_t start; 947 bus_size_t size; 948 bus_size_t align; 949 struct pcmcia_io_handle *pcihp; 950 { 951 struct pcic_handle *h = (struct pcic_handle *) pch; 952 bus_space_tag_t iot; 953 bus_space_handle_t ioh; 954 bus_addr_t ioaddr; 955 int flags = 0; 956 957 /* 958 * Allocate some arbitrary I/O space. 959 */ 960 961 iot = h->sc->iot; 962 963 if (start) { 964 ioaddr = start; 965 if (bus_space_map(iot, start, size, 0, &ioh)) 966 return (1); 967 DPRINTF(("pcic_chip_io_alloc map port %lx+%lx\n", 968 (u_long) ioaddr, (u_long) size)); 969 } else { 970 flags |= PCMCIA_IO_ALLOCATED; 971 if (bus_space_alloc(iot, h->sc->iobase, 972 h->sc->iobase + h->sc->iosize, size, align, 0, 0, 973 &ioaddr, &ioh)) 974 return (1); 975 DPRINTF(("pcic_chip_io_alloc alloc port %lx+%lx\n", 976 (u_long) ioaddr, (u_long) size)); 977 } 978 979 pcihp->iot = iot; 980 pcihp->ioh = ioh; 981 pcihp->addr = ioaddr; 982 pcihp->size = size; 983 pcihp->flags = flags; 984 985 return (0); 986 } 987 988 void 989 pcic_chip_io_free(pch, pcihp) 990 pcmcia_chipset_handle_t pch; 991 struct pcmcia_io_handle *pcihp; 992 { 993 bus_space_tag_t iot = pcihp->iot; 994 bus_space_handle_t ioh = pcihp->ioh; 995 bus_size_t size = pcihp->size; 996 997 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 998 bus_space_free(iot, ioh, size); 999 else 1000 bus_space_unmap(iot, ioh, size); 1001 } 1002 1003 1004 static struct io_map_index_st { 1005 int start_lsb; 1006 int start_msb; 1007 int stop_lsb; 1008 int stop_msb; 1009 int ioenable; 1010 int ioctlmask; 1011 int ioctlbits[3]; /* indexed by PCMCIA_WIDTH_* */ 1012 } io_map_index[] = { 1013 { 1014 PCIC_IOADDR0_START_LSB, 1015 PCIC_IOADDR0_START_MSB, 1016 PCIC_IOADDR0_STOP_LSB, 1017 PCIC_IOADDR0_STOP_MSB, 1018 PCIC_ADDRWIN_ENABLE_IO0, 1019 PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT | 1020 PCIC_IOCTL_IO0_IOCS16SRC_MASK | PCIC_IOCTL_IO0_DATASIZE_MASK, 1021 { 1022 PCIC_IOCTL_IO0_IOCS16SRC_CARD, 1023 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1024 PCIC_IOCTL_IO0_DATASIZE_8BIT, 1025 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE | 1026 PCIC_IOCTL_IO0_DATASIZE_16BIT, 1027 }, 1028 }, 1029 { 1030 PCIC_IOADDR1_START_LSB, 1031 PCIC_IOADDR1_START_MSB, 1032 PCIC_IOADDR1_STOP_LSB, 1033 PCIC_IOADDR1_STOP_MSB, 1034 PCIC_ADDRWIN_ENABLE_IO1, 1035 PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT | 1036 PCIC_IOCTL_IO1_IOCS16SRC_MASK | PCIC_IOCTL_IO1_DATASIZE_MASK, 1037 { 1038 PCIC_IOCTL_IO1_IOCS16SRC_CARD, 1039 PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE | 1040 PCIC_IOCTL_IO1_DATASIZE_8BIT, 1041 PCIC_IOCTL_IO1_IOCS16SRC_DATASIZE | 1042 PCIC_IOCTL_IO1_DATASIZE_16BIT, 1043 }, 1044 }, 1045 }; 1046 1047 void 1048 pcic_chip_do_io_map(h, win) 1049 struct pcic_handle *h; 1050 int win; 1051 { 1052 int reg; 1053 1054 DPRINTF(("pcic_chip_do_io_map win %d addr %lx size %lx width %d\n", 1055 win, (long) h->io[win].addr, (long) h->io[win].size, 1056 h->io[win].width * 8)); 1057 1058 pcic_write(h, io_map_index[win].start_lsb, h->io[win].addr & 0xff); 1059 pcic_write(h, io_map_index[win].start_msb, 1060 (h->io[win].addr >> 8) & 0xff); 1061 1062 pcic_write(h, io_map_index[win].stop_lsb, 1063 (h->io[win].addr + h->io[win].size - 1) & 0xff); 1064 pcic_write(h, io_map_index[win].stop_msb, 1065 ((h->io[win].addr + h->io[win].size - 1) >> 8) & 0xff); 1066 1067 reg = pcic_read(h, PCIC_IOCTL); 1068 reg &= ~io_map_index[win].ioctlmask; 1069 reg |= io_map_index[win].ioctlbits[h->io[win].width]; 1070 pcic_write(h, PCIC_IOCTL, reg); 1071 1072 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1073 reg |= io_map_index[win].ioenable; 1074 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1075 } 1076 1077 int 1078 pcic_chip_io_map(pch, width, offset, size, pcihp, windowp) 1079 pcmcia_chipset_handle_t pch; 1080 int width; 1081 bus_addr_t offset; 1082 bus_size_t size; 1083 struct pcmcia_io_handle *pcihp; 1084 int *windowp; 1085 { 1086 struct pcic_handle *h = (struct pcic_handle *) pch; 1087 bus_addr_t ioaddr = pcihp->addr + offset; 1088 int i, win; 1089 #ifdef PCICDEBUG 1090 static char *width_names[] = { "auto", "io8", "io16" }; 1091 #endif 1092 1093 /* XXX Sanity check offset/size. */ 1094 1095 win = -1; 1096 for (i = 0; i < (sizeof(io_map_index) / sizeof(io_map_index[0])); i++) { 1097 if ((h->ioalloc & (1 << i)) == 0) { 1098 win = i; 1099 h->ioalloc |= (1 << i); 1100 break; 1101 } 1102 } 1103 1104 if (win == -1) 1105 return (1); 1106 1107 *windowp = win; 1108 1109 /* XXX this is pretty gross */ 1110 1111 if (h->sc->iot != pcihp->iot) 1112 panic("pcic_chip_io_map iot is bogus"); 1113 1114 DPRINTF(("pcic_chip_io_map window %d %s port %lx+%lx\n", 1115 win, width_names[width], (u_long) ioaddr, (u_long) size)); 1116 1117 /* XXX wtf is this doing here? */ 1118 1119 printf(" port 0x%lx", (u_long) ioaddr); 1120 if (size > 1) 1121 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 1122 1123 h->io[win].addr = ioaddr; 1124 h->io[win].size = size; 1125 h->io[win].width = width; 1126 1127 pcic_chip_do_io_map(h, win); 1128 1129 return (0); 1130 } 1131 1132 void 1133 pcic_chip_io_unmap(pch, window) 1134 pcmcia_chipset_handle_t pch; 1135 int window; 1136 { 1137 struct pcic_handle *h = (struct pcic_handle *) pch; 1138 int reg; 1139 1140 if (window >= (sizeof(io_map_index) / sizeof(io_map_index[0]))) 1141 panic("pcic_chip_io_unmap: window out of range"); 1142 1143 reg = pcic_read(h, PCIC_ADDRWIN_ENABLE); 1144 reg &= ~io_map_index[window].ioenable; 1145 pcic_write(h, PCIC_ADDRWIN_ENABLE, reg); 1146 1147 h->ioalloc &= ~(1 << window); 1148 } 1149 1150 static void 1151 pcic_wait_ready(h) 1152 struct pcic_handle *h; 1153 { 1154 int i; 1155 1156 for (i = 0; i < 10000; i++) { 1157 if (pcic_read(h, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) 1158 return; 1159 delay(500); 1160 #ifdef PCICDEBUG 1161 if (pcic_debug) { 1162 if ((i>5000) && (i%100 == 99)) 1163 printf("."); 1164 } 1165 #endif 1166 } 1167 1168 #ifdef DIAGNOSTIC 1169 printf("pcic_wait_ready: ready never happened, status = %02x\n", 1170 pcic_read(h, PCIC_IF_STATUS)); 1171 #endif 1172 } 1173 1174 void 1175 pcic_chip_socket_enable(pch) 1176 pcmcia_chipset_handle_t pch; 1177 { 1178 struct pcic_handle *h = (struct pcic_handle *) pch; 1179 int cardtype, reg, win; 1180 1181 /* this bit is mostly stolen from pcic_attach_card */ 1182 1183 /* power down the socket to reset it, clear the card reset pin */ 1184 1185 pcic_write(h, PCIC_PWRCTL, 0); 1186 1187 /* 1188 * wait 300ms until power fails (Tpf). Then, wait 100ms since 1189 * we are changing Vcc (Toff). 1190 */ 1191 delay((300 + 100) * 1000); 1192 1193 /* power up the socket */ 1194 1195 pcic_write(h, PCIC_PWRCTL, PCIC_PWRCTL_DISABLE_RESETDRV 1196 | PCIC_PWRCTL_PWR_ENABLE); 1197 1198 /* 1199 * wait 100ms until power raise (Tpr) and 20ms to become 1200 * stable (Tsu(Vcc)). 1201 * 1202 * some machines require some more time to be settled 1203 * (another 200ms is added here). 1204 */ 1205 delay((100 + 20 + 200) * 1000); 1206 1207 pcic_write(h, PCIC_PWRCTL, PCIC_PWRCTL_DISABLE_RESETDRV | PCIC_PWRCTL_OE 1208 | PCIC_PWRCTL_PWR_ENABLE); 1209 pcic_write(h, PCIC_INTR, 0); 1210 1211 /* 1212 * hold RESET at least 10us. 1213 */ 1214 delay(10); 1215 1216 /* clear the reset flag */ 1217 1218 pcic_write(h, PCIC_INTR, PCIC_INTR_RESET); 1219 1220 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 1221 1222 delay(20000); 1223 1224 /* wait for the chip to finish initializing */ 1225 1226 pcic_wait_ready(h); 1227 1228 /* zero out the address windows */ 1229 1230 pcic_write(h, PCIC_ADDRWIN_ENABLE, 0); 1231 1232 /* set the card type */ 1233 1234 cardtype = pcmcia_card_gettype(h->pcmcia); 1235 1236 reg = pcic_read(h, PCIC_INTR); 1237 reg &= ~PCIC_INTR_CARDTYPE_MASK; 1238 reg |= ((cardtype == PCMCIA_IFTYPE_IO) ? 1239 PCIC_INTR_CARDTYPE_IO : 1240 PCIC_INTR_CARDTYPE_MEM); 1241 reg |= h->ih_irq; 1242 pcic_write(h, PCIC_INTR, reg); 1243 1244 DPRINTF(("%s: pcic_chip_socket_enable %02x cardtype %s %02x\n", 1245 h->sc->dev.dv_xname, h->sock, 1246 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), reg)); 1247 1248 /* reinstall all the memory and io mappings */ 1249 1250 for (win = 0; win < PCIC_MEM_WINS; win++) 1251 if (h->memalloc & (1 << win)) 1252 pcic_chip_do_mem_map(h, win); 1253 1254 for (win = 0; win < PCIC_IO_WINS; win++) 1255 if (h->ioalloc & (1 << win)) 1256 pcic_chip_do_io_map(h, win); 1257 } 1258 1259 void 1260 pcic_chip_socket_disable(pch) 1261 pcmcia_chipset_handle_t pch; 1262 { 1263 struct pcic_handle *h = (struct pcic_handle *) pch; 1264 1265 DPRINTF(("pcic_chip_socket_disable\n")); 1266 1267 /* power down the socket */ 1268 1269 pcic_write(h, PCIC_PWRCTL, 0); 1270 1271 /* 1272 * wait 300ms until power fails (Tpf). 1273 */ 1274 delay(300 * 1000); 1275 } 1276
Indexes created Mon Sep 29 21:09:56 GMT 2025